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Revert "drm/i915: Make intel_display_suspend atomic, v2."
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
114
115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116 {
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121 }
122
123 typedef struct {
124 int min, max;
125 } intel_range_t;
126
127 typedef struct {
128 int dot_limit;
129 int p2_slow, p2_fast;
130 } intel_p2_t;
131
132 typedef struct intel_limit intel_limit_t;
133 struct intel_limit {
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
136 };
137
138 int
139 intel_pch_rawclk(struct drm_device *dev)
140 {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146 }
147
148 static inline u32 /* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device *dev)
150 {
151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
156 }
157
158 static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182 };
183
184 static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
208 };
209
210 static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
221 };
222
223
224 static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
236 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
250 };
251
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
263 },
264 };
265
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
277 },
278 };
279
280 static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
293 };
294
295 static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
306 };
307
308 /* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
313 static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 };
351
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
364 };
365
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
377 };
378
379 static const intel_limit_t intel_limits_vlv = {
380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
393 };
394
395 static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409 };
410
411 static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421 };
422
423 static void vlv_clock(int refclk, intel_clock_t *clock)
424 {
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
431 }
432
433 static bool
434 needs_modeset(struct drm_crtc_state *state)
435 {
436 return state->mode_changed || state->active_changed;
437 }
438
439 /**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
446
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
449 return true;
450
451 return false;
452 }
453
454 /**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
462 {
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
468
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
474
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
477 return true;
478 }
479
480 WARN_ON(num_connectors == 0);
481
482 return false;
483 }
484
485 static const intel_limit_t *
486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
487 {
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
490
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
503 } else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *
510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
511 {
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
514
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
518 else
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
527
528 return limit;
529 }
530
531 static const intel_limit_t *
532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
533 {
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
546 else
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
557 } else {
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
562 else
563 limit = &intel_limits_i8xx_dac;
564 }
565 return limit;
566 }
567
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
577 }
578
579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580 {
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582 }
583
584 static void i9xx_clock(int refclk, intel_clock_t *clock)
585 {
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592 }
593
594 static void chv_clock(int refclk, intel_clock_t *clock)
595 {
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603 }
604
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
606 /**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
611 static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
614 {
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
623
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
642
643 return true;
644 }
645
646 static bool
647 i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
651 {
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
654 intel_clock_t clock;
655 int err = target;
656
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
658 /*
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
662 */
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
674 memset(best_clock, 0, sizeof(*best_clock));
675
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
686 int this_err;
687
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707 }
708
709 static bool
710 pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
714 {
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
717 intel_clock_t clock;
718 int err = target;
719
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
721 /*
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
725 */
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
737 memset(best_clock, 0, sizeof(*best_clock));
738
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
747 int this_err;
748
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
752 continue;
753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768 }
769
770 static bool
771 g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
775 {
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
778 intel_clock_t clock;
779 int max_n;
780 bool found;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
783 found = false;
784
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
813 continue;
814
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
826 return found;
827 }
828
829 /*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838 {
839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867 }
868
869 static bool
870 vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
874 {
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
877 intel_clock_t clock;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
881 bool found = false;
882
883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
886
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
895 unsigned int ppm;
896
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
901
902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
904 continue;
905
906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
911
912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
915 }
916 }
917 }
918 }
919
920 return found;
921 }
922
923 static bool
924 chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928 {
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
975 }
976 }
977
978 return found;
979 }
980
981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983 {
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988 }
989
990 bool intel_crtc_active(struct drm_crtc *crtc)
991 {
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
999 *
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
1006 */
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009 }
1010
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013 {
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017 return intel_crtc->config->cpu_transcoder;
1018 }
1019
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021 {
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037 }
1038
1039 /*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1053 *
1054 */
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056 {
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1064
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 } else {
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1073 }
1074 }
1075
1076 /*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085 {
1086 u32 bit;
1087
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
1103 switch (port->port) {
1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119 }
1120
1121 static const char *state_string(bool enabled)
1122 {
1123 return enabled ? "on" : "off";
1124 }
1125
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1129 {
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 {
1145 u32 val;
1146 bool cur_state;
1147
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1151
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162 {
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165 if (crtc->config->shared_dpll < 0)
1166 return NULL;
1167
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169 }
1170
1171 /* For ILK+ */
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
1175 {
1176 bool cur_state;
1177 struct intel_dpll_hw_state hw_state;
1178
1179 if (WARN (!pll,
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1181 return;
1182
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 int reg;
1193 u32 val;
1194 bool cur_state;
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
1197
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217 {
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228 }
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240 return;
1241
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1244 return;
1245
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249 }
1250
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
1268 {
1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
1273 bool locked = true;
1274
1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
1292 } else {
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301 locked = false;
1302
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1305 pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310 {
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316 else
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 int reg;
1330 u32 val;
1331 bool cur_state;
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
1334
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338 state = true;
1339
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1356 {
1357 int reg;
1358 u32 val;
1359 bool cur_state;
1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1367 }
1368
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374 {
1375 struct drm_device *dev = dev_priv->dev;
1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
1387 return;
1388 }
1389
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1399 }
1400 }
1401
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404 {
1405 struct drm_device *dev = dev_priv->dev;
1406 int reg, sprite;
1407 u32 val;
1408
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 }
1437 }
1438
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1440 {
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1443 }
1444
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 {
1447 u32 val;
1448 bool enabled;
1449
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456 }
1457
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
1460 {
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
1471 }
1472
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1475 {
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492 }
1493
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496 {
1497 if ((val & SDVO_ENABLE) == 0)
1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502 return false;
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1506 } else {
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508 return false;
1509 }
1510 return true;
1511 }
1512
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515 {
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527 }
1528
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531 {
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542 }
1543
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1546 {
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1551
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559 {
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1564
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1568 }
1569
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572 {
1573 int reg;
1574 u32 val;
1575
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1584 pipe_name(pipe));
1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void intel_init_dpio(struct drm_device *dev)
1598 {
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
1615 }
1616
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1619 {
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1658 {
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669 mutex_lock(&dev_priv->sb_lock);
1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676 mutex_unlock(&dev_priv->sb_lock);
1677
1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1693 }
1694
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1696 {
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->base.state->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704 return count;
1705 }
1706
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1708 {
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
1751
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 !intel_num_dvo_pipes(dev)) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
1812 if (pipe == PIPE_B)
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1816
1817 }
1818
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820 {
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822 u32 val;
1823
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1826
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1833
1834 mutex_lock(&dev_priv->sb_lock);
1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
1852 mutex_unlock(&dev_priv->sb_lock);
1853 }
1854
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1858 {
1859 u32 port_mask;
1860 int dpll_reg;
1861
1862 switch (dport->port) {
1863 case PORT_B:
1864 port_mask = DPLL_PORTB_READY_MASK;
1865 dpll_reg = DPLL(0);
1866 break;
1867 case PORT_C:
1868 port_mask = DPLL_PORTC_READY_MASK;
1869 dpll_reg = DPLL(0);
1870 expected_mask <<= 4;
1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1875 break;
1876 default:
1877 BUG();
1878 }
1879
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883 }
1884
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886 {
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891 if (WARN_ON(pll == NULL))
1892 return;
1893
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902 }
1903
1904 /**
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913 {
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918 if (WARN_ON(pll == NULL))
1919 return;
1920
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1922 return;
1923
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1927
1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
1930 assert_shared_dpll_enabled(dev_priv, pll);
1931 return;
1932 }
1933 WARN_ON(pll->on);
1934
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1939 pll->on = true;
1940 }
1941
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943 {
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1951 return;
1952
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1954 return;
1955
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1959
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1962 return;
1963 }
1964
1965 assert_shared_dpll_enabled(dev_priv, pll);
1966 WARN_ON(!pll->on);
1967 if (--pll->active)
1968 return;
1969
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1972 pll->on = false;
1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975 }
1976
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
1979 {
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1984
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2003 }
2004
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
2011 * make the BPC in transcoder be consistent with
2012 * that in pipeconf reg.
2013 */
2014 val &= ~PIPECONF_BPC_MASK;
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
2016 }
2017
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2020 if (HAS_PCH_IBX(dev_priv->dev) &&
2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 else
2024 val |= TRANS_INTERLACED;
2025 else
2026 val |= TRANS_PROGRESSIVE;
2027
2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2031 }
2032
2033 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2034 enum transcoder cpu_transcoder)
2035 {
2036 u32 val, pipeconf_val;
2037
2038 /* PCH only available on ILK+ */
2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2040
2041 /* FDI must be feeding us bits for PCH ports */
2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2044
2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2049
2050 val = TRANS_ENABLE;
2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2052
2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
2055 val |= TRANS_INTERLACED;
2056 else
2057 val |= TRANS_PROGRESSIVE;
2058
2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2061 DRM_ERROR("Failed to enable PCH transcoder\n");
2062 }
2063
2064 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
2066 {
2067 struct drm_device *dev = dev_priv->dev;
2068 uint32_t reg, val;
2069
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2073
2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2076
2077 reg = PCH_TRANSCONF(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2084
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2091 }
2092 }
2093
2094 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2095 {
2096 u32 val;
2097
2098 val = I915_READ(LPT_TRANSCONF);
2099 val &= ~TRANS_ENABLE;
2100 I915_WRITE(LPT_TRANSCONF, val);
2101 /* wait for PCH transcoder off, transcoder state */
2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2103 DRM_ERROR("Failed to disable PCH transcoder\n");
2104
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2108 I915_WRITE(_TRANSA_CHICKEN2, val);
2109 }
2110
2111 /**
2112 * intel_enable_pipe - enable a pipe, asserting requirements
2113 * @crtc: crtc responsible for the pipe
2114 *
2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2117 */
2118 static void intel_enable_pipe(struct intel_crtc *crtc)
2119 {
2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 pipe);
2125 enum pipe pch_transcoder;
2126 int reg;
2127 u32 val;
2128
2129 assert_planes_disabled(dev_priv, pipe);
2130 assert_cursor_disabled(dev_priv, pipe);
2131 assert_sprites_disabled(dev_priv, pipe);
2132
2133 if (HAS_PCH_LPT(dev_priv->dev))
2134 pch_transcoder = TRANSCODER_A;
2135 else
2136 pch_transcoder = pipe;
2137
2138 /*
2139 * A pipe without a PLL won't actually be able to drive bits from
2140 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2141 * need the check.
2142 */
2143 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2145 assert_dsi_pll_enabled(dev_priv);
2146 else
2147 assert_pll_enabled(dev_priv, pipe);
2148 else {
2149 if (crtc->config->has_pch_encoder) {
2150 /* if driving the PCH, we need FDI enabled */
2151 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2152 assert_fdi_tx_pll_enabled(dev_priv,
2153 (enum pipe) cpu_transcoder);
2154 }
2155 /* FIXME: assert CPU port conditions for SNB+ */
2156 }
2157
2158 reg = PIPECONF(cpu_transcoder);
2159 val = I915_READ(reg);
2160 if (val & PIPECONF_ENABLE) {
2161 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2162 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2163 return;
2164 }
2165
2166 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 POSTING_READ(reg);
2168 }
2169
2170 /**
2171 * intel_disable_pipe - disable a pipe, asserting requirements
2172 * @crtc: crtc whose pipes is to be disabled
2173 *
2174 * Disable the pipe of @crtc, making sure that various hardware
2175 * specific requirements are met, if applicable, e.g. plane
2176 * disabled, panel fitter off, etc.
2177 *
2178 * Will wait until the pipe has shut down before returning.
2179 */
2180 static void intel_disable_pipe(struct intel_crtc *crtc)
2181 {
2182 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2183 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2184 enum pipe pipe = crtc->pipe;
2185 int reg;
2186 u32 val;
2187
2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
2193 assert_cursor_disabled(dev_priv, pipe);
2194 assert_sprites_disabled(dev_priv, pipe);
2195
2196 reg = PIPECONF(cpu_transcoder);
2197 val = I915_READ(reg);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
2205 if (crtc->config->double_wide)
2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 /**
2219 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2220 * @plane: plane to be enabled
2221 * @crtc: crtc for the plane
2222 *
2223 * Enable @plane on @crtc, making sure that the pipe is running first.
2224 */
2225 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2226 struct drm_crtc *crtc)
2227 {
2228 struct drm_device *dev = plane->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2233 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2234 to_intel_plane_state(plane->state)->visible = true;
2235
2236 dev_priv->display.update_primary_plane(crtc, plane->fb,
2237 crtc->x, crtc->y);
2238 }
2239
2240 static bool need_vtd_wa(struct drm_device *dev)
2241 {
2242 #ifdef CONFIG_INTEL_IOMMU
2243 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2244 return true;
2245 #endif
2246 return false;
2247 }
2248
2249 unsigned int
2250 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2251 uint64_t fb_format_modifier)
2252 {
2253 unsigned int tile_height;
2254 uint32_t pixel_bytes;
2255
2256 switch (fb_format_modifier) {
2257 case DRM_FORMAT_MOD_NONE:
2258 tile_height = 1;
2259 break;
2260 case I915_FORMAT_MOD_X_TILED:
2261 tile_height = IS_GEN2(dev) ? 16 : 8;
2262 break;
2263 case I915_FORMAT_MOD_Y_TILED:
2264 tile_height = 32;
2265 break;
2266 case I915_FORMAT_MOD_Yf_TILED:
2267 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2268 switch (pixel_bytes) {
2269 default:
2270 case 1:
2271 tile_height = 64;
2272 break;
2273 case 2:
2274 case 4:
2275 tile_height = 32;
2276 break;
2277 case 8:
2278 tile_height = 16;
2279 break;
2280 case 16:
2281 WARN_ONCE(1,
2282 "128-bit pixels are not supported for display!");
2283 tile_height = 16;
2284 break;
2285 }
2286 break;
2287 default:
2288 MISSING_CASE(fb_format_modifier);
2289 tile_height = 1;
2290 break;
2291 }
2292
2293 return tile_height;
2294 }
2295
2296 unsigned int
2297 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2298 uint32_t pixel_format, uint64_t fb_format_modifier)
2299 {
2300 return ALIGN(height, intel_tile_height(dev, pixel_format,
2301 fb_format_modifier));
2302 }
2303
2304 static int
2305 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state)
2307 {
2308 struct intel_rotation_info *info = &view->rotation_info;
2309
2310 *view = i915_ggtt_view_normal;
2311
2312 if (!plane_state)
2313 return 0;
2314
2315 if (!intel_rotation_90_or_270(plane_state->rotation))
2316 return 0;
2317
2318 *view = i915_ggtt_view_rotated;
2319
2320 info->height = fb->height;
2321 info->pixel_format = fb->pixel_format;
2322 info->pitch = fb->pitches[0];
2323 info->fb_modifier = fb->modifier[0];
2324
2325 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330 struct drm_framebuffer *fb,
2331 const struct drm_plane_state *plane_state,
2332 struct intel_engine_cs *pipelined)
2333 {
2334 struct drm_device *dev = fb->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337 struct i915_ggtt_view view;
2338 u32 alignment;
2339 int ret;
2340
2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
2345 if (INTEL_INFO(dev)->gen >= 9)
2346 alignment = 256 * 1024;
2347 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2348 alignment = 128 * 1024;
2349 else if (INTEL_INFO(dev)->gen >= 4)
2350 alignment = 4 * 1024;
2351 else
2352 alignment = 64 * 1024;
2353 break;
2354 case I915_FORMAT_MOD_X_TILED:
2355 if (INTEL_INFO(dev)->gen >= 9)
2356 alignment = 256 * 1024;
2357 else {
2358 /* pin() will align the object as required by fence */
2359 alignment = 0;
2360 }
2361 break;
2362 case I915_FORMAT_MOD_Y_TILED:
2363 case I915_FORMAT_MOD_Yf_TILED:
2364 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2365 "Y tiling bo slipped through, driver bug!\n"))
2366 return -EINVAL;
2367 alignment = 1 * 1024 * 1024;
2368 break;
2369 default:
2370 MISSING_CASE(fb->modifier[0]);
2371 return -EINVAL;
2372 }
2373
2374 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375 if (ret)
2376 return ret;
2377
2378 /* Note that the w/a also requires 64 PTE of padding following the
2379 * bo. We currently fill all unused PTE with the shadow page and so
2380 * we should always have valid PTE following the scanout preventing
2381 * the VT-d warning.
2382 */
2383 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2384 alignment = 256 * 1024;
2385
2386 /*
2387 * Global gtt pte registers are special registers which actually forward
2388 * writes to a chunk of system memory. Which means that there is no risk
2389 * that the register values disappear as soon as we call
2390 * intel_runtime_pm_put(), so it is correct to wrap only the
2391 * pin/unpin/fence and not more.
2392 */
2393 intel_runtime_pm_get(dev_priv);
2394
2395 dev_priv->mm.interruptible = false;
2396 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2397 &view);
2398 if (ret)
2399 goto err_interruptible;
2400
2401 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2402 * fence, whereas 965+ only requires a fence if using
2403 * framebuffer compression. For simplicity, we always install
2404 * a fence as the cost is not that onerous.
2405 */
2406 ret = i915_gem_object_get_fence(obj);
2407 if (ret)
2408 goto err_unpin;
2409
2410 i915_gem_object_pin_fence(obj);
2411
2412 dev_priv->mm.interruptible = true;
2413 intel_runtime_pm_put(dev_priv);
2414 return 0;
2415
2416 err_unpin:
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2418 err_interruptible:
2419 dev_priv->mm.interruptible = true;
2420 intel_runtime_pm_put(dev_priv);
2421 return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
2426 {
2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428 struct i915_ggtt_view view;
2429 int ret;
2430
2431 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2432
2433 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2434 WARN_ONCE(ret, "Couldn't get view from plane state!");
2435
2436 i915_gem_object_unpin_fence(obj);
2437 i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
2446 {
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2449
2450 tile_rows = *y / 8;
2451 *y %= 8;
2452
2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
2458 unsigned int offset;
2459
2460 offset = *y * pitch + *x * cpp;
2461 *y = 0;
2462 *x = (offset & 4095) / cpp;
2463 return offset & -4096;
2464 }
2465 }
2466
2467 static int i9xx_format_to_fourcc(int format)
2468 {
2469 switch (format) {
2470 case DISPPLANE_8BPP:
2471 return DRM_FORMAT_C8;
2472 case DISPPLANE_BGRX555:
2473 return DRM_FORMAT_XRGB1555;
2474 case DISPPLANE_BGRX565:
2475 return DRM_FORMAT_RGB565;
2476 default:
2477 case DISPPLANE_BGRX888:
2478 return DRM_FORMAT_XRGB8888;
2479 case DISPPLANE_RGBX888:
2480 return DRM_FORMAT_XBGR8888;
2481 case DISPPLANE_BGRX101010:
2482 return DRM_FORMAT_XRGB2101010;
2483 case DISPPLANE_RGBX101010:
2484 return DRM_FORMAT_XBGR2101010;
2485 }
2486 }
2487
2488 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2489 {
2490 switch (format) {
2491 case PLANE_CTL_FORMAT_RGB_565:
2492 return DRM_FORMAT_RGB565;
2493 default:
2494 case PLANE_CTL_FORMAT_XRGB_8888:
2495 if (rgb_order) {
2496 if (alpha)
2497 return DRM_FORMAT_ABGR8888;
2498 else
2499 return DRM_FORMAT_XBGR8888;
2500 } else {
2501 if (alpha)
2502 return DRM_FORMAT_ARGB8888;
2503 else
2504 return DRM_FORMAT_XRGB8888;
2505 }
2506 case PLANE_CTL_FORMAT_XRGB_2101010:
2507 if (rgb_order)
2508 return DRM_FORMAT_XBGR2101010;
2509 else
2510 return DRM_FORMAT_XRGB2101010;
2511 }
2512 }
2513
2514 static bool
2515 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2516 struct intel_initial_plane_config *plane_config)
2517 {
2518 struct drm_device *dev = crtc->base.dev;
2519 struct drm_i915_gem_object *obj = NULL;
2520 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2521 struct drm_framebuffer *fb = &plane_config->fb->base;
2522 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2523 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2524 PAGE_SIZE);
2525
2526 size_aligned -= base_aligned;
2527
2528 if (plane_config->size == 0)
2529 return false;
2530
2531 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2532 base_aligned,
2533 base_aligned,
2534 size_aligned);
2535 if (!obj)
2536 return false;
2537
2538 obj->tiling_mode = plane_config->tiling;
2539 if (obj->tiling_mode == I915_TILING_X)
2540 obj->stride = fb->pitches[0];
2541
2542 mode_cmd.pixel_format = fb->pixel_format;
2543 mode_cmd.width = fb->width;
2544 mode_cmd.height = fb->height;
2545 mode_cmd.pitches[0] = fb->pitches[0];
2546 mode_cmd.modifier[0] = fb->modifier[0];
2547 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2548
2549 mutex_lock(&dev->struct_mutex);
2550 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2551 &mode_cmd, obj)) {
2552 DRM_DEBUG_KMS("intel fb init failed\n");
2553 goto out_unref_obj;
2554 }
2555 mutex_unlock(&dev->struct_mutex);
2556
2557 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2558 return true;
2559
2560 out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
2563 return false;
2564 }
2565
2566 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2567 static void
2568 update_state_fb(struct drm_plane *plane)
2569 {
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578 }
2579
2580 static void
2581 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
2583 {
2584 struct drm_device *dev = intel_crtc->base.dev;
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2588 struct drm_i915_gem_object *obj;
2589 struct drm_plane *primary = intel_crtc->base.primary;
2590 struct drm_framebuffer *fb;
2591
2592 if (!plane_config->fb)
2593 return;
2594
2595 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2596 fb = &plane_config->fb->base;
2597 goto valid_fb;
2598 }
2599
2600 kfree(plane_config->fb);
2601
2602 /*
2603 * Failed to alloc the obj, check to see if we should share
2604 * an fb with another CRTC instead
2605 */
2606 for_each_crtc(dev, c) {
2607 i = to_intel_crtc(c);
2608
2609 if (c == &intel_crtc->base)
2610 continue;
2611
2612 if (!i->active)
2613 continue;
2614
2615 fb = c->primary->fb;
2616 if (!fb)
2617 continue;
2618
2619 obj = intel_fb_obj(fb);
2620 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2621 drm_framebuffer_reference(fb);
2622 goto valid_fb;
2623 }
2624 }
2625
2626 return;
2627
2628 valid_fb:
2629 obj = intel_fb_obj(fb);
2630 if (obj->tiling_mode != I915_TILING_NONE)
2631 dev_priv->preserve_bios_swizzle = true;
2632
2633 primary->fb = fb;
2634 primary->crtc = primary->state->crtc = &intel_crtc->base;
2635 update_state_fb(primary);
2636 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2637 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2638 }
2639
2640 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2641 struct drm_framebuffer *fb,
2642 int x, int y)
2643 {
2644 struct drm_device *dev = crtc->dev;
2645 struct drm_i915_private *dev_priv = dev->dev_private;
2646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2647 struct drm_plane *primary = crtc->primary;
2648 bool visible = to_intel_plane_state(primary->state)->visible;
2649 struct drm_i915_gem_object *obj;
2650 int plane = intel_crtc->plane;
2651 unsigned long linear_offset;
2652 u32 dspcntr;
2653 u32 reg = DSPCNTR(plane);
2654 int pixel_size;
2655
2656 if (!visible || !fb) {
2657 I915_WRITE(reg, 0);
2658 if (INTEL_INFO(dev)->gen >= 4)
2659 I915_WRITE(DSPSURF(plane), 0);
2660 else
2661 I915_WRITE(DSPADDR(plane), 0);
2662 POSTING_READ(reg);
2663 return;
2664 }
2665
2666 obj = intel_fb_obj(fb);
2667 if (WARN_ON(obj == NULL))
2668 return;
2669
2670 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2671
2672 dspcntr = DISPPLANE_GAMMA_ENABLE;
2673
2674 dspcntr |= DISPLAY_PLANE_ENABLE;
2675
2676 if (INTEL_INFO(dev)->gen < 4) {
2677 if (intel_crtc->pipe == PIPE_B)
2678 dspcntr |= DISPPLANE_SEL_PIPE_B;
2679
2680 /* pipesrc and dspsize control the size that is scaled from,
2681 * which should always be the user's requested size.
2682 */
2683 I915_WRITE(DSPSIZE(plane),
2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
2686 I915_WRITE(DSPPOS(plane), 0);
2687 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2688 I915_WRITE(PRIMSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(PRIMPOS(plane), 0);
2692 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2693 }
2694
2695 switch (fb->pixel_format) {
2696 case DRM_FORMAT_C8:
2697 dspcntr |= DISPPLANE_8BPP;
2698 break;
2699 case DRM_FORMAT_XRGB1555:
2700 dspcntr |= DISPPLANE_BGRX555;
2701 break;
2702 case DRM_FORMAT_RGB565:
2703 dspcntr |= DISPPLANE_BGRX565;
2704 break;
2705 case DRM_FORMAT_XRGB8888:
2706 dspcntr |= DISPPLANE_BGRX888;
2707 break;
2708 case DRM_FORMAT_XBGR8888:
2709 dspcntr |= DISPPLANE_RGBX888;
2710 break;
2711 case DRM_FORMAT_XRGB2101010:
2712 dspcntr |= DISPPLANE_BGRX101010;
2713 break;
2714 case DRM_FORMAT_XBGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
2716 break;
2717 default:
2718 BUG();
2719 }
2720
2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
2724
2725 if (IS_G4X(dev))
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
2729
2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2733 pixel_size,
2734 fb->pitches[0]);
2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
2737 intel_crtc->dspaddr_offset = linear_offset;
2738 }
2739
2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
2761 } else
2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2763 POSTING_READ(reg);
2764 }
2765
2766 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
2769 {
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
2775 struct drm_i915_gem_object *obj;
2776 int plane = intel_crtc->plane;
2777 unsigned long linear_offset;
2778 u32 dspcntr;
2779 u32 reg = DSPCNTR(plane);
2780 int pixel_size;
2781
2782 if (!visible || !fb) {
2783 I915_WRITE(reg, 0);
2784 I915_WRITE(DSPSURF(plane), 0);
2785 POSTING_READ(reg);
2786 return;
2787 }
2788
2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2791 return;
2792
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
2797 dspcntr |= DISPLAY_PLANE_ENABLE;
2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2801
2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
2808 break;
2809 case DRM_FORMAT_XRGB8888:
2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
2819 dspcntr |= DISPPLANE_RGBX101010;
2820 break;
2821 default:
2822 BUG();
2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
2827
2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2830
2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
2832 intel_crtc->dspaddr_offset =
2833 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2834 pixel_size,
2835 fb->pitches[0]);
2836 linear_offset -= intel_crtc->dspaddr_offset;
2837 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2838 dspcntr |= DISPPLANE_ROTATE_180;
2839
2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2841 x += (intel_crtc->config->pipe_src_w - 1);
2842 y += (intel_crtc->config->pipe_src_h - 1);
2843
2844 /* Finding the last pixel of the last line of the display
2845 data and adding to linear_offset*/
2846 linear_offset +=
2847 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2848 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2849 }
2850 }
2851
2852 I915_WRITE(reg, dspcntr);
2853
2854 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2855 I915_WRITE(DSPSURF(plane),
2856 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2857 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2858 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2859 } else {
2860 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2861 I915_WRITE(DSPLINOFF(plane), linear_offset);
2862 }
2863 POSTING_READ(reg);
2864 }
2865
2866 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2867 uint32_t pixel_format)
2868 {
2869 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2870
2871 /*
2872 * The stride is either expressed as a multiple of 64 bytes
2873 * chunks for linear buffers or in number of tiles for tiled
2874 * buffers.
2875 */
2876 switch (fb_modifier) {
2877 case DRM_FORMAT_MOD_NONE:
2878 return 64;
2879 case I915_FORMAT_MOD_X_TILED:
2880 if (INTEL_INFO(dev)->gen == 2)
2881 return 128;
2882 return 512;
2883 case I915_FORMAT_MOD_Y_TILED:
2884 /* No need to check for old gens and Y tiling since this is
2885 * about the display engine and those will be blocked before
2886 * we get here.
2887 */
2888 return 128;
2889 case I915_FORMAT_MOD_Yf_TILED:
2890 if (bits_per_pixel == 8)
2891 return 64;
2892 else
2893 return 128;
2894 default:
2895 MISSING_CASE(fb_modifier);
2896 return 64;
2897 }
2898 }
2899
2900 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2901 struct drm_i915_gem_object *obj)
2902 {
2903 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904
2905 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2906 view = &i915_ggtt_view_rotated;
2907
2908 return i915_gem_obj_ggtt_offset_view(obj, view);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct drm_device *dev;
2917 struct drm_i915_private *dev_priv;
2918 struct intel_crtc_scaler_state *scaler_state;
2919 int i;
2920
2921 if (!intel_crtc || !intel_crtc->config)
2922 return;
2923
2924 dev = intel_crtc->base.dev;
2925 dev_priv = dev->dev_private;
2926 scaler_state = &intel_crtc->config->scaler_state;
2927
2928 /* loop through and disable scalers that aren't in use */
2929 for (i = 0; i < intel_crtc->num_scalers; i++) {
2930 if (!scaler_state->scalers[i].in_use) {
2931 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2932 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2934 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2935 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936 }
2937 }
2938 }
2939
2940 u32 skl_plane_ctl_format(uint32_t pixel_format)
2941 {
2942 switch (pixel_format) {
2943 case DRM_FORMAT_C8:
2944 return PLANE_CTL_FORMAT_INDEXED;
2945 case DRM_FORMAT_RGB565:
2946 return PLANE_CTL_FORMAT_RGB_565;
2947 case DRM_FORMAT_XBGR8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2949 case DRM_FORMAT_XRGB8888:
2950 return PLANE_CTL_FORMAT_XRGB_8888;
2951 /*
2952 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2953 * to be already pre-multiplied. We need to add a knob (or a different
2954 * DRM_FORMAT) for user-space to configure that.
2955 */
2956 case DRM_FORMAT_ABGR8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2958 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2959 case DRM_FORMAT_ARGB8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 |
2961 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2962 case DRM_FORMAT_XRGB2101010:
2963 return PLANE_CTL_FORMAT_XRGB_2101010;
2964 case DRM_FORMAT_XBGR2101010:
2965 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2966 case DRM_FORMAT_YUYV:
2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2968 case DRM_FORMAT_YVYU:
2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2970 case DRM_FORMAT_UYVY:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2972 case DRM_FORMAT_VYUY:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2974 default:
2975 MISSING_CASE(pixel_format);
2976 }
2977
2978 return 0;
2979 }
2980
2981 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2982 {
2983 switch (fb_modifier) {
2984 case DRM_FORMAT_MOD_NONE:
2985 break;
2986 case I915_FORMAT_MOD_X_TILED:
2987 return PLANE_CTL_TILED_X;
2988 case I915_FORMAT_MOD_Y_TILED:
2989 return PLANE_CTL_TILED_Y;
2990 case I915_FORMAT_MOD_Yf_TILED:
2991 return PLANE_CTL_TILED_YF;
2992 default:
2993 MISSING_CASE(fb_modifier);
2994 }
2995
2996 return 0;
2997 }
2998
2999 u32 skl_plane_ctl_rotation(unsigned int rotation)
3000 {
3001 switch (rotation) {
3002 case BIT(DRM_ROTATE_0):
3003 break;
3004 /*
3005 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3006 * while i915 HW rotation is clockwise, thats why this swapping.
3007 */
3008 case BIT(DRM_ROTATE_90):
3009 return PLANE_CTL_ROTATE_270;
3010 case BIT(DRM_ROTATE_180):
3011 return PLANE_CTL_ROTATE_180;
3012 case BIT(DRM_ROTATE_270):
3013 return PLANE_CTL_ROTATE_90;
3014 default:
3015 MISSING_CASE(rotation);
3016 }
3017
3018 return 0;
3019 }
3020
3021 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3022 struct drm_framebuffer *fb,
3023 int x, int y)
3024 {
3025 struct drm_device *dev = crtc->dev;
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028 struct drm_plane *plane = crtc->primary;
3029 bool visible = to_intel_plane_state(plane->state)->visible;
3030 struct drm_i915_gem_object *obj;
3031 int pipe = intel_crtc->pipe;
3032 u32 plane_ctl, stride_div, stride;
3033 u32 tile_height, plane_offset, plane_size;
3034 unsigned int rotation;
3035 int x_offset, y_offset;
3036 unsigned long surf_addr;
3037 struct intel_crtc_state *crtc_state = intel_crtc->config;
3038 struct intel_plane_state *plane_state;
3039 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3040 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041 int scaler_id = -1;
3042
3043 plane_state = to_intel_plane_state(plane->state);
3044
3045 if (!visible || !fb) {
3046 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3047 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3048 POSTING_READ(PLANE_CTL(pipe, 0));
3049 return;
3050 }
3051
3052 plane_ctl = PLANE_CTL_ENABLE |
3053 PLANE_CTL_PIPE_GAMMA_ENABLE |
3054 PLANE_CTL_PIPE_CSC_ENABLE;
3055
3056 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3057 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3058 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3059
3060 rotation = plane->state->rotation;
3061 plane_ctl |= skl_plane_ctl_rotation(rotation);
3062
3063 obj = intel_fb_obj(fb);
3064 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3065 fb->pixel_format);
3066 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067
3068 /*
3069 * FIXME: intel_plane_state->src, dst aren't set when transitional
3070 * update_plane helpers are called from legacy paths.
3071 * Once full atomic crtc is available, below check can be avoided.
3072 */
3073 if (drm_rect_width(&plane_state->src)) {
3074 scaler_id = plane_state->scaler_id;
3075 src_x = plane_state->src.x1 >> 16;
3076 src_y = plane_state->src.y1 >> 16;
3077 src_w = drm_rect_width(&plane_state->src) >> 16;
3078 src_h = drm_rect_height(&plane_state->src) >> 16;
3079 dst_x = plane_state->dst.x1;
3080 dst_y = plane_state->dst.y1;
3081 dst_w = drm_rect_width(&plane_state->dst);
3082 dst_h = drm_rect_height(&plane_state->dst);
3083
3084 WARN_ON(x != src_x || y != src_y);
3085 } else {
3086 src_w = intel_crtc->config->pipe_src_w;
3087 src_h = intel_crtc->config->pipe_src_h;
3088 }
3089
3090 if (intel_rotation_90_or_270(rotation)) {
3091 /* stride = Surface height in tiles */
3092 tile_height = intel_tile_height(dev, fb->pixel_format,
3093 fb->modifier[0]);
3094 stride = DIV_ROUND_UP(fb->height, tile_height);
3095 x_offset = stride * tile_height - y - src_h;
3096 y_offset = x;
3097 plane_size = (src_w - 1) << 16 | (src_h - 1);
3098 } else {
3099 stride = fb->pitches[0] / stride_div;
3100 x_offset = x;
3101 y_offset = y;
3102 plane_size = (src_h - 1) << 16 | (src_w - 1);
3103 }
3104 plane_offset = y_offset << 16 | x_offset;
3105
3106 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3107 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3108 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3109 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3110
3111 if (scaler_id >= 0) {
3112 uint32_t ps_ctrl = 0;
3113
3114 WARN_ON(!dst_w || !dst_h);
3115 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3116 crtc_state->scaler_state.scalers[scaler_id].mode;
3117 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3118 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3119 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3120 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3121 I915_WRITE(PLANE_POS(pipe, 0), 0);
3122 } else {
3123 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124 }
3125
3126 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3127
3128 POSTING_READ(PLANE_SURF(pipe, 0));
3129 }
3130
3131 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3132 static int
3133 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3134 int x, int y, enum mode_set_atomic state)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138
3139 if (dev_priv->display.disable_fbc)
3140 dev_priv->display.disable_fbc(dev);
3141
3142 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143
3144 return 0;
3145 }
3146
3147 static void intel_complete_page_flips(struct drm_device *dev)
3148 {
3149 struct drm_crtc *crtc;
3150
3151 for_each_crtc(dev, crtc) {
3152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153 enum plane plane = intel_crtc->plane;
3154
3155 intel_prepare_page_flip(dev, plane);
3156 intel_finish_page_flip_plane(dev, plane);
3157 }
3158 }
3159
3160 static void intel_update_primary_planes(struct drm_device *dev)
3161 {
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 struct drm_crtc *crtc;
3164
3165 for_each_crtc(dev, crtc) {
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
3168 drm_modeset_lock(&crtc->mutex, NULL);
3169 /*
3170 * FIXME: Once we have proper support for primary planes (and
3171 * disabling them without disabling the entire crtc) allow again
3172 * a NULL crtc->primary->fb.
3173 */
3174 if (intel_crtc->active && crtc->primary->fb)
3175 dev_priv->display.update_primary_plane(crtc,
3176 crtc->primary->fb,
3177 crtc->x,
3178 crtc->y);
3179 drm_modeset_unlock(&crtc->mutex);
3180 }
3181 }
3182
3183 void intel_prepare_reset(struct drm_device *dev)
3184 {
3185 /* no reset support for gen2 */
3186 if (IS_GEN2(dev))
3187 return;
3188
3189 /* reset doesn't touch the display */
3190 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191 return;
3192
3193 drm_modeset_lock_all(dev);
3194 /*
3195 * Disabling the crtcs gracefully seems nicer. Also the
3196 * g33 docs say we should at least disable all the planes.
3197 */
3198 intel_display_suspend(dev);
3199 }
3200
3201 void intel_finish_reset(struct drm_device *dev)
3202 {
3203 struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205 /*
3206 * Flips in the rings will be nuked by the reset,
3207 * so complete all pending flips so that user space
3208 * will get its events and not get stuck.
3209 */
3210 intel_complete_page_flips(dev);
3211
3212 /* no reset support for gen2 */
3213 if (IS_GEN2(dev))
3214 return;
3215
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3218 /*
3219 * Flips in the rings have been nuked by the reset,
3220 * so update the base address of all primary
3221 * planes to the the last fb to make sure we're
3222 * showing the correct fb after a reset.
3223 */
3224 intel_update_primary_planes(dev);
3225 return;
3226 }
3227
3228 /*
3229 * The display has been reset as well,
3230 * so need a full re-initialization.
3231 */
3232 intel_runtime_pm_disable_interrupts(dev_priv);
3233 intel_runtime_pm_enable_interrupts(dev_priv);
3234
3235 intel_modeset_init_hw(dev);
3236
3237 spin_lock_irq(&dev_priv->irq_lock);
3238 if (dev_priv->display.hpd_irq_setup)
3239 dev_priv->display.hpd_irq_setup(dev);
3240 spin_unlock_irq(&dev_priv->irq_lock);
3241
3242 intel_modeset_setup_hw_state(dev, true);
3243
3244 intel_hpd_init(dev_priv);
3245
3246 drm_modeset_unlock_all(dev);
3247 }
3248
3249 static void
3250 intel_finish_fb(struct drm_framebuffer *old_fb)
3251 {
3252 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3253 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3254 bool was_interruptible = dev_priv->mm.interruptible;
3255 int ret;
3256
3257 /* Big Hammer, we also need to ensure that any pending
3258 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3259 * current scanout is retired before unpinning the old
3260 * framebuffer. Note that we rely on userspace rendering
3261 * into the buffer attached to the pipe they are waiting
3262 * on. If not, userspace generates a GPU hang with IPEHR
3263 * point to the MI_WAIT_FOR_EVENT.
3264 *
3265 * This should only fail upon a hung GPU, in which case we
3266 * can safely continue.
3267 */
3268 dev_priv->mm.interruptible = false;
3269 ret = i915_gem_object_wait_rendering(obj, true);
3270 dev_priv->mm.interruptible = was_interruptible;
3271
3272 WARN_ON(ret);
3273 }
3274
3275 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276 {
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280 bool pending;
3281
3282 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 return false;
3285
3286 spin_lock_irq(&dev->event_lock);
3287 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3288 spin_unlock_irq(&dev->event_lock);
3289
3290 return pending;
3291 }
3292
3293 static void intel_update_pipe_size(struct intel_crtc *crtc)
3294 {
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 const struct drm_display_mode *adjusted_mode;
3298
3299 if (!i915.fastboot)
3300 return;
3301
3302 /*
3303 * Update pipe size and adjust fitter if needed: the reason for this is
3304 * that in compute_mode_changes we check the native mode (not the pfit
3305 * mode) to see if we can flip rather than do a full mode set. In the
3306 * fastboot case, we'll flip, but if we don't update the pipesrc and
3307 * pfit state, we'll end up with a big fb scanned out into the wrong
3308 * sized surface.
3309 *
3310 * To fix this properly, we need to hoist the checks up into
3311 * compute_mode_changes (or above), check the actual pfit state and
3312 * whether the platform allows pfit disable with pipe active, and only
3313 * then update the pipesrc and pfit state, even on the flip path.
3314 */
3315
3316 adjusted_mode = &crtc->config->base.adjusted_mode;
3317
3318 I915_WRITE(PIPESRC(crtc->pipe),
3319 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3320 (adjusted_mode->crtc_vdisplay - 1));
3321 if (!crtc->config->pch_pfit.enabled &&
3322 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3324 I915_WRITE(PF_CTL(crtc->pipe), 0);
3325 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3327 }
3328 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3329 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3330 }
3331
3332 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3333 {
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int pipe = intel_crtc->pipe;
3338 u32 reg, temp;
3339
3340 /* enable normal train */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
3343 if (IS_IVYBRIDGE(dev)) {
3344 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3345 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3346 } else {
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3349 }
3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 if (HAS_PCH_CPT(dev)) {
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE;
3360 }
3361 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3362
3363 /* wait one idle pattern time */
3364 POSTING_READ(reg);
3365 udelay(1000);
3366
3367 /* IVB wants error correction enabled */
3368 if (IS_IVYBRIDGE(dev))
3369 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3370 FDI_FE_ERRC_ENABLE);
3371 }
3372
3373 /* The FDI link training functions for ILK/Ibexpeak. */
3374 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3375 {
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379 int pipe = intel_crtc->pipe;
3380 u32 reg, temp, tries;
3381
3382 /* FDI needs bits from pipe first */
3383 assert_pipe_enabled(dev_priv, pipe);
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392 I915_READ(reg);
3393 udelay(150);
3394
3395 /* enable CPU FDI TX and PCH FDI RX */
3396 reg = FDI_TX_CTL(pipe);
3397 temp = I915_READ(reg);
3398 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3399 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3400 temp &= ~FDI_LINK_TRAIN_NONE;
3401 temp |= FDI_LINK_TRAIN_PATTERN_1;
3402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3403
3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
3408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3409
3410 POSTING_READ(reg);
3411 udelay(150);
3412
3413 /* Ironlake workaround, enable clock pointer after FDI enable*/
3414 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3416 FDI_RX_PHASE_SYNC_POINTER_EN);
3417
3418 reg = FDI_RX_IIR(pipe);
3419 for (tries = 0; tries < 5; tries++) {
3420 temp = I915_READ(reg);
3421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423 if ((temp & FDI_RX_BIT_LOCK)) {
3424 DRM_DEBUG_KMS("FDI train 1 done.\n");
3425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3426 break;
3427 }
3428 }
3429 if (tries == 5)
3430 DRM_ERROR("FDI train 1 fail!\n");
3431
3432 /* Train 2 */
3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~FDI_LINK_TRAIN_NONE;
3436 temp |= FDI_LINK_TRAIN_PATTERN_2;
3437 I915_WRITE(reg, temp);
3438
3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
3443 I915_WRITE(reg, temp);
3444
3445 POSTING_READ(reg);
3446 udelay(150);
3447
3448 reg = FDI_RX_IIR(pipe);
3449 for (tries = 0; tries < 5; tries++) {
3450 temp = I915_READ(reg);
3451 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3452
3453 if (temp & FDI_RX_SYMBOL_LOCK) {
3454 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3455 DRM_DEBUG_KMS("FDI train 2 done.\n");
3456 break;
3457 }
3458 }
3459 if (tries == 5)
3460 DRM_ERROR("FDI train 2 fail!\n");
3461
3462 DRM_DEBUG_KMS("FDI train done\n");
3463
3464 }
3465
3466 static const int snb_b_fdi_train_param[] = {
3467 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3468 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3469 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3470 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471 };
3472
3473 /* The FDI link training functions for SNB/Cougarpoint. */
3474 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3475 {
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
3480 u32 reg, temp, i, retry;
3481
3482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3483 for train result */
3484 reg = FDI_RX_IMR(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~FDI_RX_SYMBOL_LOCK;
3487 temp &= ~FDI_RX_BIT_LOCK;
3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
3491 udelay(150);
3492
3493 /* enable CPU FDI TX and PCH FDI RX */
3494 reg = FDI_TX_CTL(pipe);
3495 temp = I915_READ(reg);
3496 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3497 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1;
3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 /* SNB-B */
3502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3503 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3504
3505 I915_WRITE(FDI_RX_MISC(pipe),
3506 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3507
3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 if (HAS_PCH_CPT(dev)) {
3511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3513 } else {
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_1;
3516 }
3517 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3518
3519 POSTING_READ(reg);
3520 udelay(150);
3521
3522 for (i = 0; i < 4; i++) {
3523 reg = FDI_TX_CTL(pipe);
3524 temp = I915_READ(reg);
3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= snb_b_fdi_train_param[i];
3527 I915_WRITE(reg, temp);
3528
3529 POSTING_READ(reg);
3530 udelay(500);
3531
3532 for (retry = 0; retry < 5; retry++) {
3533 reg = FDI_RX_IIR(pipe);
3534 temp = I915_READ(reg);
3535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536 if (temp & FDI_RX_BIT_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3538 DRM_DEBUG_KMS("FDI train 1 done.\n");
3539 break;
3540 }
3541 udelay(50);
3542 }
3543 if (retry < 5)
3544 break;
3545 }
3546 if (i == 4)
3547 DRM_ERROR("FDI train 1 fail!\n");
3548
3549 /* Train 2 */
3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_2;
3554 if (IS_GEN6(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556 /* SNB-B */
3557 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3558 }
3559 I915_WRITE(reg, temp);
3560
3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if (HAS_PCH_CPT(dev)) {
3564 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3565 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3566 } else {
3567 temp &= ~FDI_LINK_TRAIN_NONE;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 }
3570 I915_WRITE(reg, temp);
3571
3572 POSTING_READ(reg);
3573 udelay(150);
3574
3575 for (i = 0; i < 4; i++) {
3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3579 temp |= snb_b_fdi_train_param[i];
3580 I915_WRITE(reg, temp);
3581
3582 POSTING_READ(reg);
3583 udelay(500);
3584
3585 for (retry = 0; retry < 5; retry++) {
3586 reg = FDI_RX_IIR(pipe);
3587 temp = I915_READ(reg);
3588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3589 if (temp & FDI_RX_SYMBOL_LOCK) {
3590 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3591 DRM_DEBUG_KMS("FDI train 2 done.\n");
3592 break;
3593 }
3594 udelay(50);
3595 }
3596 if (retry < 5)
3597 break;
3598 }
3599 if (i == 4)
3600 DRM_ERROR("FDI train 2 fail!\n");
3601
3602 DRM_DEBUG_KMS("FDI train done.\n");
3603 }
3604
3605 /* Manual link training for Ivy Bridge A0 parts */
3606 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3607 {
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
3612 u32 reg, temp, i, j;
3613
3614 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3615 for train result */
3616 reg = FDI_RX_IMR(pipe);
3617 temp = I915_READ(reg);
3618 temp &= ~FDI_RX_SYMBOL_LOCK;
3619 temp &= ~FDI_RX_BIT_LOCK;
3620 I915_WRITE(reg, temp);
3621
3622 POSTING_READ(reg);
3623 udelay(150);
3624
3625 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3626 I915_READ(FDI_RX_IIR(pipe)));
3627
3628 /* Try each vswing and preemphasis setting twice before moving on */
3629 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3630 /* disable first in case we need to retry */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3634 temp &= ~FDI_TX_ENABLE;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_AUTO;
3640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3641 temp &= ~FDI_RX_ENABLE;
3642 I915_WRITE(reg, temp);
3643
3644 /* enable CPU FDI TX and PCH FDI RX */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3649 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3651 temp |= snb_b_fdi_train_param[j/2];
3652 temp |= FDI_COMPOSITE_SYNC;
3653 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3654
3655 I915_WRITE(FDI_RX_MISC(pipe),
3656 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3657
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3661 temp |= FDI_COMPOSITE_SYNC;
3662 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3663
3664 POSTING_READ(reg);
3665 udelay(1); /* should be 0.5us */
3666
3667 for (i = 0; i < 4; i++) {
3668 reg = FDI_RX_IIR(pipe);
3669 temp = I915_READ(reg);
3670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3671
3672 if (temp & FDI_RX_BIT_LOCK ||
3673 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3674 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3675 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3676 i);
3677 break;
3678 }
3679 udelay(1); /* should be 0.5us */
3680 }
3681 if (i == 4) {
3682 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3683 continue;
3684 }
3685
3686 /* Train 2 */
3687 reg = FDI_TX_CTL(pipe);
3688 temp = I915_READ(reg);
3689 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3697 I915_WRITE(reg, temp);
3698
3699 POSTING_READ(reg);
3700 udelay(2); /* should be 1.5us */
3701
3702 for (i = 0; i < 4; i++) {
3703 reg = FDI_RX_IIR(pipe);
3704 temp = I915_READ(reg);
3705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3706
3707 if (temp & FDI_RX_SYMBOL_LOCK ||
3708 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3711 i);
3712 goto train_done;
3713 }
3714 udelay(2); /* should be 1.5us */
3715 }
3716 if (i == 4)
3717 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3718 }
3719
3720 train_done:
3721 DRM_DEBUG_KMS("FDI train done.\n");
3722 }
3723
3724 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3725 {
3726 struct drm_device *dev = intel_crtc->base.dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 int pipe = intel_crtc->pipe;
3729 u32 reg, temp;
3730
3731
3732 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3736 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3738 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3739
3740 POSTING_READ(reg);
3741 udelay(200);
3742
3743 /* Switch from Rawclk to PCDclk */
3744 temp = I915_READ(reg);
3745 I915_WRITE(reg, temp | FDI_PCDCLK);
3746
3747 POSTING_READ(reg);
3748 udelay(200);
3749
3750 /* Enable CPU FDI TX PLL, always on for Ironlake */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3754 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758 }
3759 }
3760
3761 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3762 {
3763 struct drm_device *dev = intel_crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int pipe = intel_crtc->pipe;
3766 u32 reg, temp;
3767
3768 /* Switch from PCDclk to Rawclk */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3772
3773 /* Disable CPU FDI TX PLL */
3774 reg = FDI_TX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3784
3785 /* Wait for the clocks to turn off. */
3786 POSTING_READ(reg);
3787 udelay(100);
3788 }
3789
3790 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3791 {
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 int pipe = intel_crtc->pipe;
3796 u32 reg, temp;
3797
3798 /* disable CPU FDI tx and PCH FDI rx */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802 POSTING_READ(reg);
3803
3804 reg = FDI_RX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~(0x7 << 16);
3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3808 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 /* Ironlake workaround, disable clock pointer after downing FDI */
3814 if (HAS_PCH_IBX(dev))
3815 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3816
3817 /* still set train pattern 1 */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~FDI_LINK_TRAIN_NONE;
3821 temp |= FDI_LINK_TRAIN_PATTERN_1;
3822 I915_WRITE(reg, temp);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 if (HAS_PCH_CPT(dev)) {
3827 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3828 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3829 } else {
3830 temp &= ~FDI_LINK_TRAIN_NONE;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1;
3832 }
3833 /* BPC in FDI rx is consistent with that in PIPECONF */
3834 temp &= ~(0x07 << 16);
3835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(100);
3840 }
3841
3842 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3843 {
3844 struct intel_crtc *crtc;
3845
3846 /* Note that we don't need to be called with mode_config.lock here
3847 * as our list of CRTC objects is static for the lifetime of the
3848 * device and so cannot disappear as we iterate. Similarly, we can
3849 * happily treat the predicates as racy, atomic checks as userspace
3850 * cannot claim and pin a new fb without at least acquring the
3851 * struct_mutex and so serialising with us.
3852 */
3853 for_each_intel_crtc(dev, crtc) {
3854 if (atomic_read(&crtc->unpin_work_count) == 0)
3855 continue;
3856
3857 if (crtc->unpin_work)
3858 intel_wait_for_vblank(dev, crtc->pipe);
3859
3860 return true;
3861 }
3862
3863 return false;
3864 }
3865
3866 static void page_flip_completed(struct intel_crtc *intel_crtc)
3867 {
3868 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3869 struct intel_unpin_work *work = intel_crtc->unpin_work;
3870
3871 /* ensure that the unpin work is consistent wrt ->pending. */
3872 smp_rmb();
3873 intel_crtc->unpin_work = NULL;
3874
3875 if (work->event)
3876 drm_send_vblank_event(intel_crtc->base.dev,
3877 intel_crtc->pipe,
3878 work->event);
3879
3880 drm_crtc_vblank_put(&intel_crtc->base);
3881
3882 wake_up_all(&dev_priv->pending_flip_queue);
3883 queue_work(dev_priv->wq, &work->work);
3884
3885 trace_i915_flip_complete(intel_crtc->plane,
3886 work->pending_flip_obj);
3887 }
3888
3889 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3890 {
3891 struct drm_device *dev = crtc->dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3895 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3896 !intel_crtc_has_pending_flip(crtc),
3897 60*HZ) == 0)) {
3898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3899
3900 spin_lock_irq(&dev->event_lock);
3901 if (intel_crtc->unpin_work) {
3902 WARN_ONCE(1, "Removing stuck page flip\n");
3903 page_flip_completed(intel_crtc);
3904 }
3905 spin_unlock_irq(&dev->event_lock);
3906 }
3907
3908 if (crtc->primary->fb) {
3909 mutex_lock(&dev->struct_mutex);
3910 intel_finish_fb(crtc->primary->fb);
3911 mutex_unlock(&dev->struct_mutex);
3912 }
3913 }
3914
3915 /* Program iCLKIP clock to the desired frequency */
3916 static void lpt_program_iclkip(struct drm_crtc *crtc)
3917 {
3918 struct drm_device *dev = crtc->dev;
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3921 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922 u32 temp;
3923
3924 mutex_lock(&dev_priv->sb_lock);
3925
3926 /* It is necessary to ungate the pixclk gate prior to programming
3927 * the divisors, and gate it back when it is done.
3928 */
3929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3930
3931 /* Disable SSCCTL */
3932 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3933 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3934 SBI_SSCCTL_DISABLE,
3935 SBI_ICLK);
3936
3937 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3938 if (clock == 20000) {
3939 auxdiv = 1;
3940 divsel = 0x41;
3941 phaseinc = 0x20;
3942 } else {
3943 /* The iCLK virtual clock root frequency is in MHz,
3944 * but the adjusted_mode->crtc_clock in in KHz. To get the
3945 * divisors, it is necessary to divide one by another, so we
3946 * convert the virtual clock precision to KHz here for higher
3947 * precision.
3948 */
3949 u32 iclk_virtual_root_freq = 172800 * 1000;
3950 u32 iclk_pi_range = 64;
3951 u32 desired_divisor, msb_divisor_value, pi_value;
3952
3953 desired_divisor = (iclk_virtual_root_freq / clock);
3954 msb_divisor_value = desired_divisor / iclk_pi_range;
3955 pi_value = desired_divisor % iclk_pi_range;
3956
3957 auxdiv = 0;
3958 divsel = msb_divisor_value - 2;
3959 phaseinc = pi_value;
3960 }
3961
3962 /* This should not happen with any sane values */
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3964 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3965 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3966 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3967
3968 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3969 clock,
3970 auxdiv,
3971 divsel,
3972 phasedir,
3973 phaseinc);
3974
3975 /* Program SSCDIVINTPHASE6 */
3976 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3977 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3979 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3980 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3981 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3982 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3983 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3984
3985 /* Program SSCAUXDIV */
3986 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3987 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3988 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3989 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3990
3991 /* Enable modulator and associated divider */
3992 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3993 temp &= ~SBI_SSCCTL_DISABLE;
3994 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3995
3996 /* Wait for initialization time */
3997 udelay(24);
3998
3999 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4000
4001 mutex_unlock(&dev_priv->sb_lock);
4002 }
4003
4004 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4005 enum pipe pch_transcoder)
4006 {
4007 struct drm_device *dev = crtc->base.dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4010
4011 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4012 I915_READ(HTOTAL(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4014 I915_READ(HBLANK(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4016 I915_READ(HSYNC(cpu_transcoder)));
4017
4018 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4019 I915_READ(VTOTAL(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4021 I915_READ(VBLANK(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4023 I915_READ(VSYNC(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4025 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026 }
4027
4028 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4029 {
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 uint32_t temp;
4032
4033 temp = I915_READ(SOUTH_CHICKEN1);
4034 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4035 return;
4036
4037 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4039
4040 temp &= ~FDI_BC_BIFURCATION_SELECT;
4041 if (enable)
4042 temp |= FDI_BC_BIFURCATION_SELECT;
4043
4044 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4045 I915_WRITE(SOUTH_CHICKEN1, temp);
4046 POSTING_READ(SOUTH_CHICKEN1);
4047 }
4048
4049 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4050 {
4051 struct drm_device *dev = intel_crtc->base.dev;
4052
4053 switch (intel_crtc->pipe) {
4054 case PIPE_A:
4055 break;
4056 case PIPE_B:
4057 if (intel_crtc->config->fdi_lanes > 2)
4058 cpt_set_fdi_bc_bifurcation(dev, false);
4059 else
4060 cpt_set_fdi_bc_bifurcation(dev, true);
4061
4062 break;
4063 case PIPE_C:
4064 cpt_set_fdi_bc_bifurcation(dev, true);
4065
4066 break;
4067 default:
4068 BUG();
4069 }
4070 }
4071
4072 /*
4073 * Enable PCH resources required for PCH ports:
4074 * - PCH PLLs
4075 * - FDI training & RX/TX
4076 * - update transcoder timings
4077 * - DP transcoding bits
4078 * - transcoder
4079 */
4080 static void ironlake_pch_enable(struct drm_crtc *crtc)
4081 {
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085 int pipe = intel_crtc->pipe;
4086 u32 reg, temp;
4087
4088 assert_pch_transcoder_disabled(dev_priv, pipe);
4089
4090 if (IS_IVYBRIDGE(dev))
4091 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4092
4093 /* Write the TU size bits before fdi link training, so that error
4094 * detection works. */
4095 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4096 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4097
4098 /* For PCH output, training FDI link */
4099 dev_priv->display.fdi_link_train(crtc);
4100
4101 /* We need to program the right clock selection before writing the pixel
4102 * mutliplier into the DPLL. */
4103 if (HAS_PCH_CPT(dev)) {
4104 u32 sel;
4105
4106 temp = I915_READ(PCH_DPLL_SEL);
4107 temp |= TRANS_DPLL_ENABLE(pipe);
4108 sel = TRANS_DPLLB_SEL(pipe);
4109 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4110 temp |= sel;
4111 else
4112 temp &= ~sel;
4113 I915_WRITE(PCH_DPLL_SEL, temp);
4114 }
4115
4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
4123 intel_enable_shared_dpll(intel_crtc);
4124
4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129 intel_fdi_normal_train(crtc);
4130
4131 /* For PCH DP, enable TRANS_DP_CTL */
4132 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4133 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4134 reg = TRANS_DP_CTL(pipe);
4135 temp = I915_READ(reg);
4136 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4137 TRANS_DP_SYNC_MASK |
4138 TRANS_DP_BPC_MASK);
4139 temp |= TRANS_DP_OUTPUT_ENABLE;
4140 temp |= bpc << 9; /* same format but at 11:9 */
4141
4142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4146
4147 switch (intel_trans_dp_port_sel(crtc)) {
4148 case PCH_DP_B:
4149 temp |= TRANS_DP_PORT_SEL_B;
4150 break;
4151 case PCH_DP_C:
4152 temp |= TRANS_DP_PORT_SEL_C;
4153 break;
4154 case PCH_DP_D:
4155 temp |= TRANS_DP_PORT_SEL_D;
4156 break;
4157 default:
4158 BUG();
4159 }
4160
4161 I915_WRITE(reg, temp);
4162 }
4163
4164 ironlake_enable_pch_transcoder(dev_priv, pipe);
4165 }
4166
4167 static void lpt_pch_enable(struct drm_crtc *crtc)
4168 {
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4173
4174 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4175
4176 lpt_program_iclkip(crtc);
4177
4178 /* Set transcoder timing. */
4179 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4180
4181 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4182 }
4183
4184 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4185 struct intel_crtc_state *crtc_state)
4186 {
4187 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4188 struct intel_shared_dpll *pll;
4189 struct intel_shared_dpll_config *shared_dpll;
4190 enum intel_dpll_id i;
4191
4192 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4193
4194 if (HAS_PCH_IBX(dev_priv->dev)) {
4195 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4196 i = (enum intel_dpll_id) crtc->pipe;
4197 pll = &dev_priv->shared_dplls[i];
4198
4199 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4200 crtc->base.base.id, pll->name);
4201
4202 WARN_ON(shared_dpll[i].crtc_mask);
4203
4204 goto found;
4205 }
4206
4207 if (IS_BROXTON(dev_priv->dev)) {
4208 /* PLL is attached to port in bxt */
4209 struct intel_encoder *encoder;
4210 struct intel_digital_port *intel_dig_port;
4211
4212 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4213 if (WARN_ON(!encoder))
4214 return NULL;
4215
4216 intel_dig_port = enc_to_dig_port(&encoder->base);
4217 /* 1:1 mapping between ports and PLLs */
4218 i = (enum intel_dpll_id)intel_dig_port->port;
4219 pll = &dev_priv->shared_dplls[i];
4220 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4221 crtc->base.base.id, pll->name);
4222 WARN_ON(shared_dpll[i].crtc_mask);
4223
4224 goto found;
4225 }
4226
4227 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4228 pll = &dev_priv->shared_dplls[i];
4229
4230 /* Only want to check enabled timings first */
4231 if (shared_dpll[i].crtc_mask == 0)
4232 continue;
4233
4234 if (memcmp(&crtc_state->dpll_hw_state,
4235 &shared_dpll[i].hw_state,
4236 sizeof(crtc_state->dpll_hw_state)) == 0) {
4237 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4238 crtc->base.base.id, pll->name,
4239 shared_dpll[i].crtc_mask,
4240 pll->active);
4241 goto found;
4242 }
4243 }
4244
4245 /* Ok no matching timings, maybe there's a free one? */
4246 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4247 pll = &dev_priv->shared_dplls[i];
4248 if (shared_dpll[i].crtc_mask == 0) {
4249 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4250 crtc->base.base.id, pll->name);
4251 goto found;
4252 }
4253 }
4254
4255 return NULL;
4256
4257 found:
4258 if (shared_dpll[i].crtc_mask == 0)
4259 shared_dpll[i].hw_state =
4260 crtc_state->dpll_hw_state;
4261
4262 crtc_state->shared_dpll = i;
4263 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4264 pipe_name(crtc->pipe));
4265
4266 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4267
4268 return pll;
4269 }
4270
4271 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4272 {
4273 struct drm_i915_private *dev_priv = to_i915(state->dev);
4274 struct intel_shared_dpll_config *shared_dpll;
4275 struct intel_shared_dpll *pll;
4276 enum intel_dpll_id i;
4277
4278 if (!to_intel_atomic_state(state)->dpll_set)
4279 return;
4280
4281 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284 pll->config = shared_dpll[i];
4285 }
4286 }
4287
4288 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4289 {
4290 struct drm_i915_private *dev_priv = dev->dev_private;
4291 int dslreg = PIPEDSL(pipe);
4292 u32 temp;
4293
4294 temp = I915_READ(dslreg);
4295 udelay(500);
4296 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4297 if (wait_for(I915_READ(dslreg) != temp, 5))
4298 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4299 }
4300 }
4301
4302 /**
4303 * skl_update_scaler_users - Stages update to crtc's scaler state
4304 * @intel_crtc: crtc
4305 * @crtc_state: crtc_state
4306 * @plane: plane (NULL indicates crtc is requesting update)
4307 * @plane_state: plane's state
4308 * @force_detach: request unconditional detachment of scaler
4309 *
4310 * This function updates scaler state for requested plane or crtc.
4311 * To request scaler usage update for a plane, caller shall pass plane pointer.
4312 * To request scaler usage update for crtc, caller shall pass plane pointer
4313 * as NULL.
4314 *
4315 * Return
4316 * 0 - scaler_usage updated successfully
4317 * error - requested scaling cannot be supported or other error condition
4318 */
4319 int
4320 skl_update_scaler_users(
4321 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4322 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4323 int force_detach)
4324 {
4325 int need_scaling;
4326 int idx;
4327 int src_w, src_h, dst_w, dst_h;
4328 int *scaler_id;
4329 struct drm_framebuffer *fb;
4330 struct intel_crtc_scaler_state *scaler_state;
4331 unsigned int rotation;
4332
4333 if (!intel_crtc || !crtc_state)
4334 return 0;
4335
4336 scaler_state = &crtc_state->scaler_state;
4337
4338 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4339 fb = intel_plane ? plane_state->base.fb : NULL;
4340
4341 if (intel_plane) {
4342 src_w = drm_rect_width(&plane_state->src) >> 16;
4343 src_h = drm_rect_height(&plane_state->src) >> 16;
4344 dst_w = drm_rect_width(&plane_state->dst);
4345 dst_h = drm_rect_height(&plane_state->dst);
4346 scaler_id = &plane_state->scaler_id;
4347 rotation = plane_state->base.rotation;
4348 } else {
4349 struct drm_display_mode *adjusted_mode =
4350 &crtc_state->base.adjusted_mode;
4351 src_w = crtc_state->pipe_src_w;
4352 src_h = crtc_state->pipe_src_h;
4353 dst_w = adjusted_mode->hdisplay;
4354 dst_h = adjusted_mode->vdisplay;
4355 scaler_id = &scaler_state->scaler_id;
4356 rotation = DRM_ROTATE_0;
4357 }
4358
4359 need_scaling = intel_rotation_90_or_270(rotation) ?
4360 (src_h != dst_w || src_w != dst_h):
4361 (src_w != dst_w || src_h != dst_h);
4362
4363 /*
4364 * if plane is being disabled or scaler is no more required or force detach
4365 * - free scaler binded to this plane/crtc
4366 * - in order to do this, update crtc->scaler_usage
4367 *
4368 * Here scaler state in crtc_state is set free so that
4369 * scaler can be assigned to other user. Actual register
4370 * update to free the scaler is done in plane/panel-fit programming.
4371 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4372 */
4373 if (force_detach || !need_scaling || (intel_plane &&
4374 (!fb || !plane_state->visible))) {
4375 if (*scaler_id >= 0) {
4376 scaler_state->scaler_users &= ~(1 << idx);
4377 scaler_state->scalers[*scaler_id].in_use = 0;
4378
4379 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4380 "crtc_state = %p scaler_users = 0x%x\n",
4381 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4382 intel_plane ? intel_plane->base.base.id :
4383 intel_crtc->base.base.id, crtc_state,
4384 scaler_state->scaler_users);
4385 *scaler_id = -1;
4386 }
4387 return 0;
4388 }
4389
4390 /* range checks */
4391 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4392 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4393
4394 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4395 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4396 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4397 "size is out of scaler range\n",
4398 intel_plane ? "PLANE" : "CRTC",
4399 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4400 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4401 return -EINVAL;
4402 }
4403
4404 /* check colorkey */
4405 if (WARN_ON(intel_plane &&
4406 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4407 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4408 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4409 return -EINVAL;
4410 }
4411
4412 /* Check src format */
4413 if (intel_plane) {
4414 switch (fb->pixel_format) {
4415 case DRM_FORMAT_RGB565:
4416 case DRM_FORMAT_XBGR8888:
4417 case DRM_FORMAT_XRGB8888:
4418 case DRM_FORMAT_ABGR8888:
4419 case DRM_FORMAT_ARGB8888:
4420 case DRM_FORMAT_XRGB2101010:
4421 case DRM_FORMAT_XBGR2101010:
4422 case DRM_FORMAT_YUYV:
4423 case DRM_FORMAT_YVYU:
4424 case DRM_FORMAT_UYVY:
4425 case DRM_FORMAT_VYUY:
4426 break;
4427 default:
4428 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4429 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4430 return -EINVAL;
4431 }
4432 }
4433
4434 /* mark this plane as a scaler user in crtc_state */
4435 scaler_state->scaler_users |= (1 << idx);
4436 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4437 "crtc_state = %p scaler_users = 0x%x\n",
4438 intel_plane ? "PLANE" : "CRTC",
4439 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4440 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4441 return 0;
4442 }
4443
4444 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4445 {
4446 struct drm_device *dev = crtc->base.dev;
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 int pipe = crtc->pipe;
4449 struct intel_crtc_scaler_state *scaler_state =
4450 &crtc->config->scaler_state;
4451
4452 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4453
4454 /* To update pfit, first update scaler state */
4455 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4456 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4457 skl_detach_scalers(crtc);
4458 if (!enable)
4459 return;
4460
4461 if (crtc->config->pch_pfit.enabled) {
4462 int id;
4463
4464 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4465 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4466 return;
4467 }
4468
4469 id = scaler_state->scaler_id;
4470 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4471 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4472 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4473 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4474
4475 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4476 }
4477 }
4478
4479 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4480 {
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 int pipe = crtc->pipe;
4484
4485 if (crtc->config->pch_pfit.enabled) {
4486 /* Force use of hard-coded filter coefficients
4487 * as some pre-programmed values are broken,
4488 * e.g. x201.
4489 */
4490 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4491 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4492 PF_PIPE_SEL_IVB(pipe));
4493 else
4494 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4495 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4496 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4497 }
4498 }
4499
4500 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4501 {
4502 struct drm_device *dev = crtc->dev;
4503 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4504 struct drm_plane *plane;
4505 struct intel_plane *intel_plane;
4506
4507 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4508 intel_plane = to_intel_plane(plane);
4509 if (intel_plane->pipe == pipe)
4510 intel_plane_restore(&intel_plane->base);
4511 }
4512 }
4513
4514 void hsw_enable_ips(struct intel_crtc *crtc)
4515 {
4516 struct drm_device *dev = crtc->base.dev;
4517 struct drm_i915_private *dev_priv = dev->dev_private;
4518
4519 if (!crtc->config->ips_enabled)
4520 return;
4521
4522 /* We can only enable IPS after we enable a plane and wait for a vblank */
4523 intel_wait_for_vblank(dev, crtc->pipe);
4524
4525 assert_plane_enabled(dev_priv, crtc->plane);
4526 if (IS_BROADWELL(dev)) {
4527 mutex_lock(&dev_priv->rps.hw_lock);
4528 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4529 mutex_unlock(&dev_priv->rps.hw_lock);
4530 /* Quoting Art Runyan: "its not safe to expect any particular
4531 * value in IPS_CTL bit 31 after enabling IPS through the
4532 * mailbox." Moreover, the mailbox may return a bogus state,
4533 * so we need to just enable it and continue on.
4534 */
4535 } else {
4536 I915_WRITE(IPS_CTL, IPS_ENABLE);
4537 /* The bit only becomes 1 in the next vblank, so this wait here
4538 * is essentially intel_wait_for_vblank. If we don't have this
4539 * and don't wait for vblanks until the end of crtc_enable, then
4540 * the HW state readout code will complain that the expected
4541 * IPS_CTL value is not the one we read. */
4542 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4543 DRM_ERROR("Timed out waiting for IPS enable\n");
4544 }
4545 }
4546
4547 void hsw_disable_ips(struct intel_crtc *crtc)
4548 {
4549 struct drm_device *dev = crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551
4552 if (!crtc->config->ips_enabled)
4553 return;
4554
4555 assert_plane_enabled(dev_priv, crtc->plane);
4556 if (IS_BROADWELL(dev)) {
4557 mutex_lock(&dev_priv->rps.hw_lock);
4558 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4559 mutex_unlock(&dev_priv->rps.hw_lock);
4560 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4561 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4562 DRM_ERROR("Timed out waiting for IPS disable\n");
4563 } else {
4564 I915_WRITE(IPS_CTL, 0);
4565 POSTING_READ(IPS_CTL);
4566 }
4567
4568 /* We need to wait for a vblank before we can disable the plane. */
4569 intel_wait_for_vblank(dev, crtc->pipe);
4570 }
4571
4572 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4573 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4574 {
4575 struct drm_device *dev = crtc->dev;
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4578 enum pipe pipe = intel_crtc->pipe;
4579 int palreg = PALETTE(pipe);
4580 int i;
4581 bool reenable_ips = false;
4582
4583 /* The clocks have to be on to load the palette. */
4584 if (!crtc->state->active)
4585 return;
4586
4587 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4588 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4589 assert_dsi_pll_enabled(dev_priv);
4590 else
4591 assert_pll_enabled(dev_priv, pipe);
4592 }
4593
4594 /* use legacy palette for Ironlake */
4595 if (!HAS_GMCH_DISPLAY(dev))
4596 palreg = LGC_PALETTE(pipe);
4597
4598 /* Workaround : Do not read or write the pipe palette/gamma data while
4599 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4600 */
4601 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4602 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4603 GAMMA_MODE_MODE_SPLIT)) {
4604 hsw_disable_ips(intel_crtc);
4605 reenable_ips = true;
4606 }
4607
4608 for (i = 0; i < 256; i++) {
4609 I915_WRITE(palreg + 4 * i,
4610 (intel_crtc->lut_r[i] << 16) |
4611 (intel_crtc->lut_g[i] << 8) |
4612 intel_crtc->lut_b[i]);
4613 }
4614
4615 if (reenable_ips)
4616 hsw_enable_ips(intel_crtc);
4617 }
4618
4619 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4620 {
4621 if (intel_crtc->overlay) {
4622 struct drm_device *dev = intel_crtc->base.dev;
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625 mutex_lock(&dev->struct_mutex);
4626 dev_priv->mm.interruptible = false;
4627 (void) intel_overlay_switch_off(intel_crtc->overlay);
4628 dev_priv->mm.interruptible = true;
4629 mutex_unlock(&dev->struct_mutex);
4630 }
4631
4632 /* Let userspace switch the overlay on again. In most cases userspace
4633 * has to recompute where to put it anyway.
4634 */
4635 }
4636
4637 /**
4638 * intel_post_enable_primary - Perform operations after enabling primary plane
4639 * @crtc: the CRTC whose primary plane was just enabled
4640 *
4641 * Performs potentially sleeping operations that must be done after the primary
4642 * plane is enabled, such as updating FBC and IPS. Note that this may be
4643 * called due to an explicit primary plane update, or due to an implicit
4644 * re-enable that is caused when a sprite plane is updated to no longer
4645 * completely hide the primary plane.
4646 */
4647 static void
4648 intel_post_enable_primary(struct drm_crtc *crtc)
4649 {
4650 struct drm_device *dev = crtc->dev;
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4653 int pipe = intel_crtc->pipe;
4654
4655 /*
4656 * BDW signals flip done immediately if the plane
4657 * is disabled, even if the plane enable is already
4658 * armed to occur at the next vblank :(
4659 */
4660 if (IS_BROADWELL(dev))
4661 intel_wait_for_vblank(dev, pipe);
4662
4663 /*
4664 * FIXME IPS should be fine as long as one plane is
4665 * enabled, but in practice it seems to have problems
4666 * when going from primary only to sprite only and vice
4667 * versa.
4668 */
4669 hsw_enable_ips(intel_crtc);
4670
4671 mutex_lock(&dev->struct_mutex);
4672 intel_fbc_update(dev);
4673 mutex_unlock(&dev->struct_mutex);
4674
4675 /*
4676 * Gen2 reports pipe underruns whenever all planes are disabled.
4677 * So don't enable underrun reporting before at least some planes
4678 * are enabled.
4679 * FIXME: Need to fix the logic to work when we turn off all planes
4680 * but leave the pipe running.
4681 */
4682 if (IS_GEN2(dev))
4683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4684
4685 /* Underruns don't raise interrupts, so check manually. */
4686 if (HAS_GMCH_DISPLAY(dev))
4687 i9xx_check_fifo_underruns(dev_priv);
4688 }
4689
4690 /**
4691 * intel_pre_disable_primary - Perform operations before disabling primary plane
4692 * @crtc: the CRTC whose primary plane is to be disabled
4693 *
4694 * Performs potentially sleeping operations that must be done before the
4695 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4696 * be called due to an explicit primary plane update, or due to an implicit
4697 * disable that is caused when a sprite plane completely hides the primary
4698 * plane.
4699 */
4700 static void
4701 intel_pre_disable_primary(struct drm_crtc *crtc)
4702 {
4703 struct drm_device *dev = crtc->dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 int pipe = intel_crtc->pipe;
4707
4708 /*
4709 * Gen2 reports pipe underruns whenever all planes are disabled.
4710 * So diasble underrun reporting before all the planes get disabled.
4711 * FIXME: Need to fix the logic to work when we turn off all planes
4712 * but leave the pipe running.
4713 */
4714 if (IS_GEN2(dev))
4715 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716
4717 /*
4718 * Vblank time updates from the shadow to live plane control register
4719 * are blocked if the memory self-refresh mode is active at that
4720 * moment. So to make sure the plane gets truly disabled, disable
4721 * first the self-refresh mode. The self-refresh enable bit in turn
4722 * will be checked/applied by the HW only at the next frame start
4723 * event which is after the vblank start event, so we need to have a
4724 * wait-for-vblank between disabling the plane and the pipe.
4725 */
4726 if (HAS_GMCH_DISPLAY(dev))
4727 intel_set_memory_cxsr(dev_priv, false);
4728
4729 mutex_lock(&dev->struct_mutex);
4730 if (dev_priv->fbc.crtc == intel_crtc)
4731 intel_fbc_disable(dev);
4732 mutex_unlock(&dev->struct_mutex);
4733
4734 /*
4735 * FIXME IPS should be fine as long as one plane is
4736 * enabled, but in practice it seems to have problems
4737 * when going from primary only to sprite only and vice
4738 * versa.
4739 */
4740 hsw_disable_ips(intel_crtc);
4741 }
4742
4743 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->dev;
4746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4747 int pipe = intel_crtc->pipe;
4748
4749 intel_enable_primary_hw_plane(crtc->primary, crtc);
4750 intel_enable_sprite_planes(crtc);
4751 intel_crtc_update_cursor(crtc, true);
4752
4753 intel_post_enable_primary(crtc);
4754
4755 /*
4756 * FIXME: Once we grow proper nuclear flip support out of this we need
4757 * to compute the mask of flip planes precisely. For the time being
4758 * consider this a flip to a NULL plane.
4759 */
4760 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4761 }
4762
4763 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4764 {
4765 struct drm_device *dev = crtc->dev;
4766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4767 struct intel_plane *intel_plane;
4768 int pipe = intel_crtc->pipe;
4769
4770 intel_crtc_wait_for_pending_flips(crtc);
4771
4772 intel_pre_disable_primary(crtc);
4773
4774 intel_crtc_dpms_overlay_disable(intel_crtc);
4775 for_each_intel_plane(dev, intel_plane) {
4776 if (intel_plane->pipe == pipe) {
4777 struct drm_crtc *from = intel_plane->base.crtc;
4778
4779 intel_plane->disable_plane(&intel_plane->base,
4780 from ?: crtc, true);
4781 }
4782 }
4783
4784 /*
4785 * FIXME: Once we grow proper nuclear flip support out of this we need
4786 * to compute the mask of flip planes precisely. For the time being
4787 * consider this a flip to a NULL plane.
4788 */
4789 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4790 }
4791
4792 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4793 {
4794 struct drm_device *dev = crtc->dev;
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4797 struct intel_encoder *encoder;
4798 int pipe = intel_crtc->pipe;
4799
4800 if (WARN_ON(intel_crtc->active))
4801 return;
4802
4803 if (intel_crtc->config->has_pch_encoder)
4804 intel_prepare_shared_dpll(intel_crtc);
4805
4806 if (intel_crtc->config->has_dp_encoder)
4807 intel_dp_set_m_n(intel_crtc, M1_N1);
4808
4809 intel_set_pipe_timings(intel_crtc);
4810
4811 if (intel_crtc->config->has_pch_encoder) {
4812 intel_cpu_transcoder_set_m_n(intel_crtc,
4813 &intel_crtc->config->fdi_m_n, NULL);
4814 }
4815
4816 ironlake_set_pipeconf(crtc);
4817
4818 intel_crtc->active = true;
4819
4820 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4821 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4822
4823 for_each_encoder_on_crtc(dev, crtc, encoder)
4824 if (encoder->pre_enable)
4825 encoder->pre_enable(encoder);
4826
4827 if (intel_crtc->config->has_pch_encoder) {
4828 /* Note: FDI PLL enabling _must_ be done before we enable the
4829 * cpu pipes, hence this is separate from all the other fdi/pch
4830 * enabling. */
4831 ironlake_fdi_pll_enable(intel_crtc);
4832 } else {
4833 assert_fdi_tx_disabled(dev_priv, pipe);
4834 assert_fdi_rx_disabled(dev_priv, pipe);
4835 }
4836
4837 ironlake_pfit_enable(intel_crtc);
4838
4839 /*
4840 * On ILK+ LUT must be loaded before the pipe is running but with
4841 * clocks enabled
4842 */
4843 intel_crtc_load_lut(crtc);
4844
4845 intel_update_watermarks(crtc);
4846 intel_enable_pipe(intel_crtc);
4847
4848 if (intel_crtc->config->has_pch_encoder)
4849 ironlake_pch_enable(crtc);
4850
4851 assert_vblank_disabled(crtc);
4852 drm_crtc_vblank_on(crtc);
4853
4854 for_each_encoder_on_crtc(dev, crtc, encoder)
4855 encoder->enable(encoder);
4856
4857 if (HAS_PCH_CPT(dev))
4858 cpt_verify_modeset(dev, intel_crtc->pipe);
4859 }
4860
4861 /* IPS only exists on ULT machines and is tied to pipe A. */
4862 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4863 {
4864 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4865 }
4866
4867 static void haswell_crtc_enable(struct drm_crtc *crtc)
4868 {
4869 struct drm_device *dev = crtc->dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4872 struct intel_encoder *encoder;
4873 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4874 struct intel_crtc_state *pipe_config =
4875 to_intel_crtc_state(crtc->state);
4876
4877 if (WARN_ON(intel_crtc->active))
4878 return;
4879
4880 if (intel_crtc_to_shared_dpll(intel_crtc))
4881 intel_enable_shared_dpll(intel_crtc);
4882
4883 if (intel_crtc->config->has_dp_encoder)
4884 intel_dp_set_m_n(intel_crtc, M1_N1);
4885
4886 intel_set_pipe_timings(intel_crtc);
4887
4888 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4889 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4890 intel_crtc->config->pixel_multiplier - 1);
4891 }
4892
4893 if (intel_crtc->config->has_pch_encoder) {
4894 intel_cpu_transcoder_set_m_n(intel_crtc,
4895 &intel_crtc->config->fdi_m_n, NULL);
4896 }
4897
4898 haswell_set_pipeconf(crtc);
4899
4900 intel_set_pipe_csc(crtc);
4901
4902 intel_crtc->active = true;
4903
4904 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4905 for_each_encoder_on_crtc(dev, crtc, encoder)
4906 if (encoder->pre_enable)
4907 encoder->pre_enable(encoder);
4908
4909 if (intel_crtc->config->has_pch_encoder) {
4910 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4911 true);
4912 dev_priv->display.fdi_link_train(crtc);
4913 }
4914
4915 intel_ddi_enable_pipe_clock(intel_crtc);
4916
4917 if (INTEL_INFO(dev)->gen == 9)
4918 skylake_pfit_update(intel_crtc, 1);
4919 else if (INTEL_INFO(dev)->gen < 9)
4920 ironlake_pfit_enable(intel_crtc);
4921 else
4922 MISSING_CASE(INTEL_INFO(dev)->gen);
4923
4924 /*
4925 * On ILK+ LUT must be loaded before the pipe is running but with
4926 * clocks enabled
4927 */
4928 intel_crtc_load_lut(crtc);
4929
4930 intel_ddi_set_pipe_settings(crtc);
4931 intel_ddi_enable_transcoder_func(crtc);
4932
4933 intel_update_watermarks(crtc);
4934 intel_enable_pipe(intel_crtc);
4935
4936 if (intel_crtc->config->has_pch_encoder)
4937 lpt_pch_enable(crtc);
4938
4939 if (intel_crtc->config->dp_encoder_is_mst)
4940 intel_ddi_set_vc_payload_alloc(crtc, true);
4941
4942 assert_vblank_disabled(crtc);
4943 drm_crtc_vblank_on(crtc);
4944
4945 for_each_encoder_on_crtc(dev, crtc, encoder) {
4946 encoder->enable(encoder);
4947 intel_opregion_notify_encoder(encoder, true);
4948 }
4949
4950 /* If we change the relative order between pipe/planes enabling, we need
4951 * to change the workaround. */
4952 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4953 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4954 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4955 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4956 }
4957 }
4958
4959 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4960 {
4961 struct drm_device *dev = crtc->base.dev;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 int pipe = crtc->pipe;
4964
4965 /* To avoid upsetting the power well on haswell only disable the pfit if
4966 * it's in use. The hw state code will make sure we get this right. */
4967 if (crtc->config->pch_pfit.enabled) {
4968 I915_WRITE(PF_CTL(pipe), 0);
4969 I915_WRITE(PF_WIN_POS(pipe), 0);
4970 I915_WRITE(PF_WIN_SZ(pipe), 0);
4971 }
4972 }
4973
4974 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4975 {
4976 struct drm_device *dev = crtc->dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4979 struct intel_encoder *encoder;
4980 int pipe = intel_crtc->pipe;
4981 u32 reg, temp;
4982
4983 if (WARN_ON(!intel_crtc->active))
4984 return;
4985
4986 for_each_encoder_on_crtc(dev, crtc, encoder)
4987 encoder->disable(encoder);
4988
4989 drm_crtc_vblank_off(crtc);
4990 assert_vblank_disabled(crtc);
4991
4992 if (intel_crtc->config->has_pch_encoder)
4993 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4994
4995 intel_disable_pipe(intel_crtc);
4996
4997 ironlake_pfit_disable(intel_crtc);
4998
4999 if (intel_crtc->config->has_pch_encoder)
5000 ironlake_fdi_disable(crtc);
5001
5002 for_each_encoder_on_crtc(dev, crtc, encoder)
5003 if (encoder->post_disable)
5004 encoder->post_disable(encoder);
5005
5006 if (intel_crtc->config->has_pch_encoder) {
5007 ironlake_disable_pch_transcoder(dev_priv, pipe);
5008
5009 if (HAS_PCH_CPT(dev)) {
5010 /* disable TRANS_DP_CTL */
5011 reg = TRANS_DP_CTL(pipe);
5012 temp = I915_READ(reg);
5013 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5014 TRANS_DP_PORT_SEL_MASK);
5015 temp |= TRANS_DP_PORT_SEL_NONE;
5016 I915_WRITE(reg, temp);
5017
5018 /* disable DPLL_SEL */
5019 temp = I915_READ(PCH_DPLL_SEL);
5020 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5021 I915_WRITE(PCH_DPLL_SEL, temp);
5022 }
5023
5024 /* disable PCH DPLL */
5025 intel_disable_shared_dpll(intel_crtc);
5026
5027 ironlake_fdi_pll_disable(intel_crtc);
5028 }
5029
5030 intel_crtc->active = false;
5031 intel_update_watermarks(crtc);
5032
5033 mutex_lock(&dev->struct_mutex);
5034 intel_fbc_update(dev);
5035 mutex_unlock(&dev->struct_mutex);
5036 }
5037
5038 static void haswell_crtc_disable(struct drm_crtc *crtc)
5039 {
5040 struct drm_device *dev = crtc->dev;
5041 struct drm_i915_private *dev_priv = dev->dev_private;
5042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5043 struct intel_encoder *encoder;
5044 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5045
5046 if (WARN_ON(!intel_crtc->active))
5047 return;
5048
5049 for_each_encoder_on_crtc(dev, crtc, encoder) {
5050 intel_opregion_notify_encoder(encoder, false);
5051 encoder->disable(encoder);
5052 }
5053
5054 drm_crtc_vblank_off(crtc);
5055 assert_vblank_disabled(crtc);
5056
5057 if (intel_crtc->config->has_pch_encoder)
5058 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5059 false);
5060 intel_disable_pipe(intel_crtc);
5061
5062 if (intel_crtc->config->dp_encoder_is_mst)
5063 intel_ddi_set_vc_payload_alloc(crtc, false);
5064
5065 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5066
5067 if (INTEL_INFO(dev)->gen == 9)
5068 skylake_pfit_update(intel_crtc, 0);
5069 else if (INTEL_INFO(dev)->gen < 9)
5070 ironlake_pfit_disable(intel_crtc);
5071 else
5072 MISSING_CASE(INTEL_INFO(dev)->gen);
5073
5074 intel_ddi_disable_pipe_clock(intel_crtc);
5075
5076 if (intel_crtc->config->has_pch_encoder) {
5077 lpt_disable_pch_transcoder(dev_priv);
5078 intel_ddi_fdi_disable(crtc);
5079 }
5080
5081 for_each_encoder_on_crtc(dev, crtc, encoder)
5082 if (encoder->post_disable)
5083 encoder->post_disable(encoder);
5084
5085 intel_crtc->active = false;
5086 intel_update_watermarks(crtc);
5087
5088 mutex_lock(&dev->struct_mutex);
5089 intel_fbc_update(dev);
5090 mutex_unlock(&dev->struct_mutex);
5091
5092 if (intel_crtc_to_shared_dpll(intel_crtc))
5093 intel_disable_shared_dpll(intel_crtc);
5094 }
5095
5096 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5097 {
5098 struct drm_device *dev = crtc->base.dev;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct intel_crtc_state *pipe_config = crtc->config;
5101
5102 if (!pipe_config->gmch_pfit.control)
5103 return;
5104
5105 /*
5106 * The panel fitter should only be adjusted whilst the pipe is disabled,
5107 * according to register description and PRM.
5108 */
5109 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5110 assert_pipe_disabled(dev_priv, crtc->pipe);
5111
5112 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5113 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5114
5115 /* Border color in case we don't scale up to the full screen. Black by
5116 * default, change to something else for debugging. */
5117 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5118 }
5119
5120 static enum intel_display_power_domain port_to_power_domain(enum port port)
5121 {
5122 switch (port) {
5123 case PORT_A:
5124 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5125 case PORT_B:
5126 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5127 case PORT_C:
5128 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5129 case PORT_D:
5130 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5131 default:
5132 WARN_ON_ONCE(1);
5133 return POWER_DOMAIN_PORT_OTHER;
5134 }
5135 }
5136
5137 #define for_each_power_domain(domain, mask) \
5138 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5139 if ((1 << (domain)) & (mask))
5140
5141 enum intel_display_power_domain
5142 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5143 {
5144 struct drm_device *dev = intel_encoder->base.dev;
5145 struct intel_digital_port *intel_dig_port;
5146
5147 switch (intel_encoder->type) {
5148 case INTEL_OUTPUT_UNKNOWN:
5149 /* Only DDI platforms should ever use this output type */
5150 WARN_ON_ONCE(!HAS_DDI(dev));
5151 case INTEL_OUTPUT_DISPLAYPORT:
5152 case INTEL_OUTPUT_HDMI:
5153 case INTEL_OUTPUT_EDP:
5154 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5155 return port_to_power_domain(intel_dig_port->port);
5156 case INTEL_OUTPUT_DP_MST:
5157 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5158 return port_to_power_domain(intel_dig_port->port);
5159 case INTEL_OUTPUT_ANALOG:
5160 return POWER_DOMAIN_PORT_CRT;
5161 case INTEL_OUTPUT_DSI:
5162 return POWER_DOMAIN_PORT_DSI;
5163 default:
5164 return POWER_DOMAIN_PORT_OTHER;
5165 }
5166 }
5167
5168 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5169 {
5170 struct drm_device *dev = crtc->dev;
5171 struct intel_encoder *intel_encoder;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 enum pipe pipe = intel_crtc->pipe;
5174 unsigned long mask;
5175 enum transcoder transcoder;
5176
5177 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5178
5179 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5180 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5181 if (intel_crtc->config->pch_pfit.enabled ||
5182 intel_crtc->config->pch_pfit.force_thru)
5183 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5184
5185 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5186 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5187
5188 return mask;
5189 }
5190
5191 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5192 {
5193 struct drm_device *dev = state->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5196 struct intel_crtc *crtc;
5197
5198 /*
5199 * First get all needed power domains, then put all unneeded, to avoid
5200 * any unnecessary toggling of the power wells.
5201 */
5202 for_each_intel_crtc(dev, crtc) {
5203 enum intel_display_power_domain domain;
5204
5205 if (!crtc->base.state->enable)
5206 continue;
5207
5208 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5209
5210 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5211 intel_display_power_get(dev_priv, domain);
5212 }
5213
5214 if (dev_priv->display.modeset_global_resources)
5215 dev_priv->display.modeset_global_resources(state);
5216
5217 for_each_intel_crtc(dev, crtc) {
5218 enum intel_display_power_domain domain;
5219
5220 for_each_power_domain(domain, crtc->enabled_power_domains)
5221 intel_display_power_put(dev_priv, domain);
5222
5223 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5224 }
5225
5226 intel_display_set_init_power(dev_priv, false);
5227 }
5228
5229 static void intel_update_max_cdclk(struct drm_device *dev)
5230 {
5231 struct drm_i915_private *dev_priv = dev->dev_private;
5232
5233 if (IS_SKYLAKE(dev)) {
5234 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5235
5236 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5237 dev_priv->max_cdclk_freq = 675000;
5238 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5239 dev_priv->max_cdclk_freq = 540000;
5240 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5241 dev_priv->max_cdclk_freq = 450000;
5242 else
5243 dev_priv->max_cdclk_freq = 337500;
5244 } else if (IS_BROADWELL(dev)) {
5245 /*
5246 * FIXME with extra cooling we can allow
5247 * 540 MHz for ULX and 675 Mhz for ULT.
5248 * How can we know if extra cooling is
5249 * available? PCI ID, VTB, something else?
5250 */
5251 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5252 dev_priv->max_cdclk_freq = 450000;
5253 else if (IS_BDW_ULX(dev))
5254 dev_priv->max_cdclk_freq = 450000;
5255 else if (IS_BDW_ULT(dev))
5256 dev_priv->max_cdclk_freq = 540000;
5257 else
5258 dev_priv->max_cdclk_freq = 675000;
5259 } else if (IS_VALLEYVIEW(dev)) {
5260 dev_priv->max_cdclk_freq = 400000;
5261 } else {
5262 /* otherwise assume cdclk is fixed */
5263 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5264 }
5265
5266 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5267 dev_priv->max_cdclk_freq);
5268 }
5269
5270 static void intel_update_cdclk(struct drm_device *dev)
5271 {
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273
5274 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5275 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5276 dev_priv->cdclk_freq);
5277
5278 /*
5279 * Program the gmbus_freq based on the cdclk frequency.
5280 * BSpec erroneously claims we should aim for 4MHz, but
5281 * in fact 1MHz is the correct frequency.
5282 */
5283 if (IS_VALLEYVIEW(dev)) {
5284 /*
5285 * Program the gmbus_freq based on the cdclk frequency.
5286 * BSpec erroneously claims we should aim for 4MHz, but
5287 * in fact 1MHz is the correct frequency.
5288 */
5289 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5290 }
5291
5292 if (dev_priv->max_cdclk_freq == 0)
5293 intel_update_max_cdclk(dev);
5294 }
5295
5296 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5297 {
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 uint32_t divider;
5300 uint32_t ratio;
5301 uint32_t current_freq;
5302 int ret;
5303
5304 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5305 switch (frequency) {
5306 case 144000:
5307 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5308 ratio = BXT_DE_PLL_RATIO(60);
5309 break;
5310 case 288000:
5311 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5312 ratio = BXT_DE_PLL_RATIO(60);
5313 break;
5314 case 384000:
5315 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5316 ratio = BXT_DE_PLL_RATIO(60);
5317 break;
5318 case 576000:
5319 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5320 ratio = BXT_DE_PLL_RATIO(60);
5321 break;
5322 case 624000:
5323 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5324 ratio = BXT_DE_PLL_RATIO(65);
5325 break;
5326 case 19200:
5327 /*
5328 * Bypass frequency with DE PLL disabled. Init ratio, divider
5329 * to suppress GCC warning.
5330 */
5331 ratio = 0;
5332 divider = 0;
5333 break;
5334 default:
5335 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5336
5337 return;
5338 }
5339
5340 mutex_lock(&dev_priv->rps.hw_lock);
5341 /* Inform power controller of upcoming frequency change */
5342 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5343 0x80000000);
5344 mutex_unlock(&dev_priv->rps.hw_lock);
5345
5346 if (ret) {
5347 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5348 ret, frequency);
5349 return;
5350 }
5351
5352 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5353 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5354 current_freq = current_freq * 500 + 1000;
5355
5356 /*
5357 * DE PLL has to be disabled when
5358 * - setting to 19.2MHz (bypass, PLL isn't used)
5359 * - before setting to 624MHz (PLL needs toggling)
5360 * - before setting to any frequency from 624MHz (PLL needs toggling)
5361 */
5362 if (frequency == 19200 || frequency == 624000 ||
5363 current_freq == 624000) {
5364 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5365 /* Timeout 200us */
5366 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5367 1))
5368 DRM_ERROR("timout waiting for DE PLL unlock\n");
5369 }
5370
5371 if (frequency != 19200) {
5372 uint32_t val;
5373
5374 val = I915_READ(BXT_DE_PLL_CTL);
5375 val &= ~BXT_DE_PLL_RATIO_MASK;
5376 val |= ratio;
5377 I915_WRITE(BXT_DE_PLL_CTL, val);
5378
5379 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5380 /* Timeout 200us */
5381 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5382 DRM_ERROR("timeout waiting for DE PLL lock\n");
5383
5384 val = I915_READ(CDCLK_CTL);
5385 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5386 val |= divider;
5387 /*
5388 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5389 * enable otherwise.
5390 */
5391 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5392 if (frequency >= 500000)
5393 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5394
5395 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5396 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5397 val |= (frequency - 1000) / 500;
5398 I915_WRITE(CDCLK_CTL, val);
5399 }
5400
5401 mutex_lock(&dev_priv->rps.hw_lock);
5402 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5403 DIV_ROUND_UP(frequency, 25000));
5404 mutex_unlock(&dev_priv->rps.hw_lock);
5405
5406 if (ret) {
5407 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5408 ret, frequency);
5409 return;
5410 }
5411
5412 intel_update_cdclk(dev);
5413 }
5414
5415 void broxton_init_cdclk(struct drm_device *dev)
5416 {
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418 uint32_t val;
5419
5420 /*
5421 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5422 * or else the reset will hang because there is no PCH to respond.
5423 * Move the handshake programming to initialization sequence.
5424 * Previously was left up to BIOS.
5425 */
5426 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5427 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5428 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5429
5430 /* Enable PG1 for cdclk */
5431 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5432
5433 /* check if cd clock is enabled */
5434 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5435 DRM_DEBUG_KMS("Display already initialized\n");
5436 return;
5437 }
5438
5439 /*
5440 * FIXME:
5441 * - The initial CDCLK needs to be read from VBT.
5442 * Need to make this change after VBT has changes for BXT.
5443 * - check if setting the max (or any) cdclk freq is really necessary
5444 * here, it belongs to modeset time
5445 */
5446 broxton_set_cdclk(dev, 624000);
5447
5448 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5449 POSTING_READ(DBUF_CTL);
5450
5451 udelay(10);
5452
5453 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5454 DRM_ERROR("DBuf power enable timeout!\n");
5455 }
5456
5457 void broxton_uninit_cdclk(struct drm_device *dev)
5458 {
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460
5461 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5462 POSTING_READ(DBUF_CTL);
5463
5464 udelay(10);
5465
5466 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5467 DRM_ERROR("DBuf power disable timeout!\n");
5468
5469 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5470 broxton_set_cdclk(dev, 19200);
5471
5472 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5473 }
5474
5475 static const struct skl_cdclk_entry {
5476 unsigned int freq;
5477 unsigned int vco;
5478 } skl_cdclk_frequencies[] = {
5479 { .freq = 308570, .vco = 8640 },
5480 { .freq = 337500, .vco = 8100 },
5481 { .freq = 432000, .vco = 8640 },
5482 { .freq = 450000, .vco = 8100 },
5483 { .freq = 540000, .vco = 8100 },
5484 { .freq = 617140, .vco = 8640 },
5485 { .freq = 675000, .vco = 8100 },
5486 };
5487
5488 static unsigned int skl_cdclk_decimal(unsigned int freq)
5489 {
5490 return (freq - 1000) / 500;
5491 }
5492
5493 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5494 {
5495 unsigned int i;
5496
5497 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5498 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5499
5500 if (e->freq == freq)
5501 return e->vco;
5502 }
5503
5504 return 8100;
5505 }
5506
5507 static void
5508 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5509 {
5510 unsigned int min_freq;
5511 u32 val;
5512
5513 /* select the minimum CDCLK before enabling DPLL 0 */
5514 val = I915_READ(CDCLK_CTL);
5515 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5516 val |= CDCLK_FREQ_337_308;
5517
5518 if (required_vco == 8640)
5519 min_freq = 308570;
5520 else
5521 min_freq = 337500;
5522
5523 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5524
5525 I915_WRITE(CDCLK_CTL, val);
5526 POSTING_READ(CDCLK_CTL);
5527
5528 /*
5529 * We always enable DPLL0 with the lowest link rate possible, but still
5530 * taking into account the VCO required to operate the eDP panel at the
5531 * desired frequency. The usual DP link rates operate with a VCO of
5532 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5533 * The modeset code is responsible for the selection of the exact link
5534 * rate later on, with the constraint of choosing a frequency that
5535 * works with required_vco.
5536 */
5537 val = I915_READ(DPLL_CTRL1);
5538
5539 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5540 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5541 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5542 if (required_vco == 8640)
5543 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5544 SKL_DPLL0);
5545 else
5546 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5547 SKL_DPLL0);
5548
5549 I915_WRITE(DPLL_CTRL1, val);
5550 POSTING_READ(DPLL_CTRL1);
5551
5552 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5553
5554 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5555 DRM_ERROR("DPLL0 not locked\n");
5556 }
5557
5558 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5559 {
5560 int ret;
5561 u32 val;
5562
5563 /* inform PCU we want to change CDCLK */
5564 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5565 mutex_lock(&dev_priv->rps.hw_lock);
5566 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5567 mutex_unlock(&dev_priv->rps.hw_lock);
5568
5569 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5570 }
5571
5572 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5573 {
5574 unsigned int i;
5575
5576 for (i = 0; i < 15; i++) {
5577 if (skl_cdclk_pcu_ready(dev_priv))
5578 return true;
5579 udelay(10);
5580 }
5581
5582 return false;
5583 }
5584
5585 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5586 {
5587 struct drm_device *dev = dev_priv->dev;
5588 u32 freq_select, pcu_ack;
5589
5590 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5591
5592 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5593 DRM_ERROR("failed to inform PCU about cdclk change\n");
5594 return;
5595 }
5596
5597 /* set CDCLK_CTL */
5598 switch(freq) {
5599 case 450000:
5600 case 432000:
5601 freq_select = CDCLK_FREQ_450_432;
5602 pcu_ack = 1;
5603 break;
5604 case 540000:
5605 freq_select = CDCLK_FREQ_540;
5606 pcu_ack = 2;
5607 break;
5608 case 308570:
5609 case 337500:
5610 default:
5611 freq_select = CDCLK_FREQ_337_308;
5612 pcu_ack = 0;
5613 break;
5614 case 617140:
5615 case 675000:
5616 freq_select = CDCLK_FREQ_675_617;
5617 pcu_ack = 3;
5618 break;
5619 }
5620
5621 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5622 POSTING_READ(CDCLK_CTL);
5623
5624 /* inform PCU of the change */
5625 mutex_lock(&dev_priv->rps.hw_lock);
5626 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5627 mutex_unlock(&dev_priv->rps.hw_lock);
5628
5629 intel_update_cdclk(dev);
5630 }
5631
5632 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5633 {
5634 /* disable DBUF power */
5635 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5636 POSTING_READ(DBUF_CTL);
5637
5638 udelay(10);
5639
5640 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5641 DRM_ERROR("DBuf power disable timeout\n");
5642
5643 /* disable DPLL0 */
5644 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5645 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5646 DRM_ERROR("Couldn't disable DPLL0\n");
5647
5648 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5649 }
5650
5651 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5652 {
5653 u32 val;
5654 unsigned int required_vco;
5655
5656 /* enable PCH reset handshake */
5657 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5658 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5659
5660 /* enable PG1 and Misc I/O */
5661 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5662
5663 /* DPLL0 already enabed !? */
5664 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5665 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5666 return;
5667 }
5668
5669 /* enable DPLL0 */
5670 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5671 skl_dpll0_enable(dev_priv, required_vco);
5672
5673 /* set CDCLK to the frequency the BIOS chose */
5674 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5675
5676 /* enable DBUF power */
5677 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5678 POSTING_READ(DBUF_CTL);
5679
5680 udelay(10);
5681
5682 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5683 DRM_ERROR("DBuf power enable timeout\n");
5684 }
5685
5686 /* returns HPLL frequency in kHz */
5687 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5688 {
5689 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5690
5691 /* Obtain SKU information */
5692 mutex_lock(&dev_priv->sb_lock);
5693 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5694 CCK_FUSE_HPLL_FREQ_MASK;
5695 mutex_unlock(&dev_priv->sb_lock);
5696
5697 return vco_freq[hpll_freq] * 1000;
5698 }
5699
5700 /* Adjust CDclk dividers to allow high res or save power if possible */
5701 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5702 {
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 u32 val, cmd;
5705
5706 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5707 != dev_priv->cdclk_freq);
5708
5709 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5710 cmd = 2;
5711 else if (cdclk == 266667)
5712 cmd = 1;
5713 else
5714 cmd = 0;
5715
5716 mutex_lock(&dev_priv->rps.hw_lock);
5717 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5718 val &= ~DSPFREQGUAR_MASK;
5719 val |= (cmd << DSPFREQGUAR_SHIFT);
5720 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5721 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5722 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5723 50)) {
5724 DRM_ERROR("timed out waiting for CDclk change\n");
5725 }
5726 mutex_unlock(&dev_priv->rps.hw_lock);
5727
5728 mutex_lock(&dev_priv->sb_lock);
5729
5730 if (cdclk == 400000) {
5731 u32 divider;
5732
5733 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5734
5735 /* adjust cdclk divider */
5736 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5737 val &= ~DISPLAY_FREQUENCY_VALUES;
5738 val |= divider;
5739 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5740
5741 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5742 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5743 50))
5744 DRM_ERROR("timed out waiting for CDclk change\n");
5745 }
5746
5747 /* adjust self-refresh exit latency value */
5748 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5749 val &= ~0x7f;
5750
5751 /*
5752 * For high bandwidth configs, we set a higher latency in the bunit
5753 * so that the core display fetch happens in time to avoid underruns.
5754 */
5755 if (cdclk == 400000)
5756 val |= 4500 / 250; /* 4.5 usec */
5757 else
5758 val |= 3000 / 250; /* 3.0 usec */
5759 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5760
5761 mutex_unlock(&dev_priv->sb_lock);
5762
5763 intel_update_cdclk(dev);
5764 }
5765
5766 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5767 {
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769 u32 val, cmd;
5770
5771 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5772 != dev_priv->cdclk_freq);
5773
5774 switch (cdclk) {
5775 case 333333:
5776 case 320000:
5777 case 266667:
5778 case 200000:
5779 break;
5780 default:
5781 MISSING_CASE(cdclk);
5782 return;
5783 }
5784
5785 /*
5786 * Specs are full of misinformation, but testing on actual
5787 * hardware has shown that we just need to write the desired
5788 * CCK divider into the Punit register.
5789 */
5790 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5791
5792 mutex_lock(&dev_priv->rps.hw_lock);
5793 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5794 val &= ~DSPFREQGUAR_MASK_CHV;
5795 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5796 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5797 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5798 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5799 50)) {
5800 DRM_ERROR("timed out waiting for CDclk change\n");
5801 }
5802 mutex_unlock(&dev_priv->rps.hw_lock);
5803
5804 intel_update_cdclk(dev);
5805 }
5806
5807 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5808 int max_pixclk)
5809 {
5810 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5811 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5812
5813 /*
5814 * Really only a few cases to deal with, as only 4 CDclks are supported:
5815 * 200MHz
5816 * 267MHz
5817 * 320/333MHz (depends on HPLL freq)
5818 * 400MHz (VLV only)
5819 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5820 * of the lower bin and adjust if needed.
5821 *
5822 * We seem to get an unstable or solid color picture at 200MHz.
5823 * Not sure what's wrong. For now use 200MHz only when all pipes
5824 * are off.
5825 */
5826 if (!IS_CHERRYVIEW(dev_priv) &&
5827 max_pixclk > freq_320*limit/100)
5828 return 400000;
5829 else if (max_pixclk > 266667*limit/100)
5830 return freq_320;
5831 else if (max_pixclk > 0)
5832 return 266667;
5833 else
5834 return 200000;
5835 }
5836
5837 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5838 int max_pixclk)
5839 {
5840 /*
5841 * FIXME:
5842 * - remove the guardband, it's not needed on BXT
5843 * - set 19.2MHz bypass frequency if there are no active pipes
5844 */
5845 if (max_pixclk > 576000*9/10)
5846 return 624000;
5847 else if (max_pixclk > 384000*9/10)
5848 return 576000;
5849 else if (max_pixclk > 288000*9/10)
5850 return 384000;
5851 else if (max_pixclk > 144000*9/10)
5852 return 288000;
5853 else
5854 return 144000;
5855 }
5856
5857 /* Compute the max pixel clock for new configuration. Uses atomic state if
5858 * that's non-NULL, look at current state otherwise. */
5859 static int intel_mode_max_pixclk(struct drm_device *dev,
5860 struct drm_atomic_state *state)
5861 {
5862 struct intel_crtc *intel_crtc;
5863 struct intel_crtc_state *crtc_state;
5864 int max_pixclk = 0;
5865
5866 for_each_intel_crtc(dev, intel_crtc) {
5867 if (state)
5868 crtc_state =
5869 intel_atomic_get_crtc_state(state, intel_crtc);
5870 else
5871 crtc_state = intel_crtc->config;
5872 if (IS_ERR(crtc_state))
5873 return PTR_ERR(crtc_state);
5874
5875 if (!crtc_state->base.enable)
5876 continue;
5877
5878 max_pixclk = max(max_pixclk,
5879 crtc_state->base.adjusted_mode.crtc_clock);
5880 }
5881
5882 return max_pixclk;
5883 }
5884
5885 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5886 {
5887 struct drm_i915_private *dev_priv = to_i915(state->dev);
5888 struct drm_crtc *crtc;
5889 struct drm_crtc_state *crtc_state;
5890 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5891 int cdclk, ret = 0;
5892
5893 if (max_pixclk < 0)
5894 return max_pixclk;
5895
5896 if (IS_VALLEYVIEW(dev_priv))
5897 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5898 else
5899 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5900
5901 if (cdclk == dev_priv->cdclk_freq)
5902 return 0;
5903
5904 /* add all active pipes to the state */
5905 for_each_crtc(state->dev, crtc) {
5906 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5907 if (IS_ERR(crtc_state))
5908 return PTR_ERR(crtc_state);
5909
5910 if (!crtc_state->active || needs_modeset(crtc_state))
5911 continue;
5912
5913 crtc_state->mode_changed = true;
5914
5915 ret = drm_atomic_add_affected_connectors(state, crtc);
5916 if (ret)
5917 break;
5918
5919 ret = drm_atomic_add_affected_planes(state, crtc);
5920 if (ret)
5921 break;
5922 }
5923
5924 return ret;
5925 }
5926
5927 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5928 {
5929 unsigned int credits, default_credits;
5930
5931 if (IS_CHERRYVIEW(dev_priv))
5932 default_credits = PFI_CREDIT(12);
5933 else
5934 default_credits = PFI_CREDIT(8);
5935
5936 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5937 /* CHV suggested value is 31 or 63 */
5938 if (IS_CHERRYVIEW(dev_priv))
5939 credits = PFI_CREDIT_31;
5940 else
5941 credits = PFI_CREDIT(15);
5942 } else {
5943 credits = default_credits;
5944 }
5945
5946 /*
5947 * WA - write default credits before re-programming
5948 * FIXME: should we also set the resend bit here?
5949 */
5950 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5951 default_credits);
5952
5953 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5954 credits | PFI_CREDIT_RESEND);
5955
5956 /*
5957 * FIXME is this guaranteed to clear
5958 * immediately or should we poll for it?
5959 */
5960 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5961 }
5962
5963 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5964 {
5965 struct drm_device *dev = old_state->dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5968 int req_cdclk;
5969
5970 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5971 * never fail. */
5972 if (WARN_ON(max_pixclk < 0))
5973 return;
5974
5975 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5976
5977 if (req_cdclk != dev_priv->cdclk_freq) {
5978 /*
5979 * FIXME: We can end up here with all power domains off, yet
5980 * with a CDCLK frequency other than the minimum. To account
5981 * for this take the PIPE-A power domain, which covers the HW
5982 * blocks needed for the following programming. This can be
5983 * removed once it's guaranteed that we get here either with
5984 * the minimum CDCLK set, or the required power domains
5985 * enabled.
5986 */
5987 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5988
5989 if (IS_CHERRYVIEW(dev))
5990 cherryview_set_cdclk(dev, req_cdclk);
5991 else
5992 valleyview_set_cdclk(dev, req_cdclk);
5993
5994 vlv_program_pfi_credits(dev_priv);
5995
5996 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5997 }
5998 }
5999
6000 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6001 {
6002 struct drm_device *dev = crtc->dev;
6003 struct drm_i915_private *dev_priv = to_i915(dev);
6004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6005 struct intel_encoder *encoder;
6006 int pipe = intel_crtc->pipe;
6007 bool is_dsi;
6008
6009 if (WARN_ON(intel_crtc->active))
6010 return;
6011
6012 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6013
6014 if (!is_dsi) {
6015 if (IS_CHERRYVIEW(dev))
6016 chv_prepare_pll(intel_crtc, intel_crtc->config);
6017 else
6018 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6019 }
6020
6021 if (intel_crtc->config->has_dp_encoder)
6022 intel_dp_set_m_n(intel_crtc, M1_N1);
6023
6024 intel_set_pipe_timings(intel_crtc);
6025
6026 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028
6029 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6030 I915_WRITE(CHV_CANVAS(pipe), 0);
6031 }
6032
6033 i9xx_set_pipeconf(intel_crtc);
6034
6035 intel_crtc->active = true;
6036
6037 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6038
6039 for_each_encoder_on_crtc(dev, crtc, encoder)
6040 if (encoder->pre_pll_enable)
6041 encoder->pre_pll_enable(encoder);
6042
6043 if (!is_dsi) {
6044 if (IS_CHERRYVIEW(dev))
6045 chv_enable_pll(intel_crtc, intel_crtc->config);
6046 else
6047 vlv_enable_pll(intel_crtc, intel_crtc->config);
6048 }
6049
6050 for_each_encoder_on_crtc(dev, crtc, encoder)
6051 if (encoder->pre_enable)
6052 encoder->pre_enable(encoder);
6053
6054 i9xx_pfit_enable(intel_crtc);
6055
6056 intel_crtc_load_lut(crtc);
6057
6058 intel_update_watermarks(crtc);
6059 intel_enable_pipe(intel_crtc);
6060
6061 assert_vblank_disabled(crtc);
6062 drm_crtc_vblank_on(crtc);
6063
6064 for_each_encoder_on_crtc(dev, crtc, encoder)
6065 encoder->enable(encoder);
6066 }
6067
6068 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6069 {
6070 struct drm_device *dev = crtc->base.dev;
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072
6073 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6074 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6075 }
6076
6077 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6078 {
6079 struct drm_device *dev = crtc->dev;
6080 struct drm_i915_private *dev_priv = to_i915(dev);
6081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6082 struct intel_encoder *encoder;
6083 int pipe = intel_crtc->pipe;
6084
6085 if (WARN_ON(intel_crtc->active))
6086 return;
6087
6088 i9xx_set_pll_dividers(intel_crtc);
6089
6090 if (intel_crtc->config->has_dp_encoder)
6091 intel_dp_set_m_n(intel_crtc, M1_N1);
6092
6093 intel_set_pipe_timings(intel_crtc);
6094
6095 i9xx_set_pipeconf(intel_crtc);
6096
6097 intel_crtc->active = true;
6098
6099 if (!IS_GEN2(dev))
6100 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6101
6102 for_each_encoder_on_crtc(dev, crtc, encoder)
6103 if (encoder->pre_enable)
6104 encoder->pre_enable(encoder);
6105
6106 i9xx_enable_pll(intel_crtc);
6107
6108 i9xx_pfit_enable(intel_crtc);
6109
6110 intel_crtc_load_lut(crtc);
6111
6112 intel_update_watermarks(crtc);
6113 intel_enable_pipe(intel_crtc);
6114
6115 assert_vblank_disabled(crtc);
6116 drm_crtc_vblank_on(crtc);
6117
6118 for_each_encoder_on_crtc(dev, crtc, encoder)
6119 encoder->enable(encoder);
6120 }
6121
6122 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6123 {
6124 struct drm_device *dev = crtc->base.dev;
6125 struct drm_i915_private *dev_priv = dev->dev_private;
6126
6127 if (!crtc->config->gmch_pfit.control)
6128 return;
6129
6130 assert_pipe_disabled(dev_priv, crtc->pipe);
6131
6132 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6133 I915_READ(PFIT_CONTROL));
6134 I915_WRITE(PFIT_CONTROL, 0);
6135 }
6136
6137 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6138 {
6139 struct drm_device *dev = crtc->dev;
6140 struct drm_i915_private *dev_priv = dev->dev_private;
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6142 struct intel_encoder *encoder;
6143 int pipe = intel_crtc->pipe;
6144
6145 if (WARN_ON(!intel_crtc->active))
6146 return;
6147
6148 /*
6149 * On gen2 planes are double buffered but the pipe isn't, so we must
6150 * wait for planes to fully turn off before disabling the pipe.
6151 * We also need to wait on all gmch platforms because of the
6152 * self-refresh mode constraint explained above.
6153 */
6154 intel_wait_for_vblank(dev, pipe);
6155
6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 encoder->disable(encoder);
6158
6159 drm_crtc_vblank_off(crtc);
6160 assert_vblank_disabled(crtc);
6161
6162 intel_disable_pipe(intel_crtc);
6163
6164 i9xx_pfit_disable(intel_crtc);
6165
6166 for_each_encoder_on_crtc(dev, crtc, encoder)
6167 if (encoder->post_disable)
6168 encoder->post_disable(encoder);
6169
6170 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6171 if (IS_CHERRYVIEW(dev))
6172 chv_disable_pll(dev_priv, pipe);
6173 else if (IS_VALLEYVIEW(dev))
6174 vlv_disable_pll(dev_priv, pipe);
6175 else
6176 i9xx_disable_pll(intel_crtc);
6177 }
6178
6179 if (!IS_GEN2(dev))
6180 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6181
6182 intel_crtc->active = false;
6183 intel_update_watermarks(crtc);
6184
6185 mutex_lock(&dev->struct_mutex);
6186 intel_fbc_update(dev);
6187 mutex_unlock(&dev->struct_mutex);
6188 }
6189
6190 /*
6191 * turn all crtc's off, but do not adjust state
6192 * This has to be paired with a call to intel_modeset_setup_hw_state.
6193 */
6194 void intel_display_suspend(struct drm_device *dev)
6195 {
6196 struct drm_i915_private *dev_priv = to_i915(dev);
6197 struct drm_crtc *crtc;
6198
6199 for_each_crtc(dev, crtc) {
6200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6201 enum intel_display_power_domain domain;
6202 unsigned long domains;
6203
6204 if (!intel_crtc->active)
6205 continue;
6206
6207 intel_crtc_disable_planes(crtc);
6208 dev_priv->display.crtc_disable(crtc);
6209
6210 domains = intel_crtc->enabled_power_domains;
6211 for_each_power_domain(domain, domains)
6212 intel_display_power_put(dev_priv, domain);
6213 intel_crtc->enabled_power_domains = 0;
6214 }
6215 }
6216
6217 /* Master function to enable/disable CRTC and corresponding power wells */
6218 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6219 {
6220 struct drm_device *dev = crtc->dev;
6221 struct drm_mode_config *config = &dev->mode_config;
6222 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224 struct intel_crtc_state *pipe_config;
6225 struct drm_atomic_state *state;
6226 int ret;
6227
6228 if (enable == intel_crtc->active)
6229 return 0;
6230
6231 if (enable && !crtc->state->enable)
6232 return 0;
6233
6234 /* this function should be called with drm_modeset_lock_all for now */
6235 if (WARN_ON(!ctx))
6236 return -EIO;
6237 lockdep_assert_held(&ctx->ww_ctx);
6238
6239 state = drm_atomic_state_alloc(dev);
6240 if (WARN_ON(!state))
6241 return -ENOMEM;
6242
6243 state->acquire_ctx = ctx;
6244 state->allow_modeset = true;
6245
6246 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6247 if (IS_ERR(pipe_config)) {
6248 ret = PTR_ERR(pipe_config);
6249 goto err;
6250 }
6251 pipe_config->base.active = enable;
6252
6253 ret = intel_set_mode(state);
6254 if (!ret)
6255 return ret;
6256
6257 err:
6258 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6259 drm_atomic_state_free(state);
6260 return ret;
6261 }
6262
6263 /**
6264 * Sets the power management mode of the pipe and plane.
6265 */
6266 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6267 {
6268 struct drm_device *dev = crtc->dev;
6269 struct intel_encoder *intel_encoder;
6270 bool enable = false;
6271
6272 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6273 enable |= intel_encoder->connectors_active;
6274
6275 intel_crtc_control(crtc, enable);
6276 }
6277
6278 void intel_encoder_destroy(struct drm_encoder *encoder)
6279 {
6280 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6281
6282 drm_encoder_cleanup(encoder);
6283 kfree(intel_encoder);
6284 }
6285
6286 /* Simple dpms helper for encoders with just one connector, no cloning and only
6287 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6288 * state of the entire output pipe. */
6289 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6290 {
6291 if (mode == DRM_MODE_DPMS_ON) {
6292 encoder->connectors_active = true;
6293
6294 intel_crtc_update_dpms(encoder->base.crtc);
6295 } else {
6296 encoder->connectors_active = false;
6297
6298 intel_crtc_update_dpms(encoder->base.crtc);
6299 }
6300 }
6301
6302 /* Cross check the actual hw state with our own modeset state tracking (and it's
6303 * internal consistency). */
6304 static void intel_connector_check_state(struct intel_connector *connector)
6305 {
6306 if (connector->get_hw_state(connector)) {
6307 struct intel_encoder *encoder = connector->encoder;
6308 struct drm_crtc *crtc;
6309 bool encoder_enabled;
6310 enum pipe pipe;
6311
6312 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6313 connector->base.base.id,
6314 connector->base.name);
6315
6316 /* there is no real hw state for MST connectors */
6317 if (connector->mst_port)
6318 return;
6319
6320 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6321 "wrong connector dpms state\n");
6322 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6323 "active connector not linked to encoder\n");
6324
6325 if (encoder) {
6326 I915_STATE_WARN(!encoder->connectors_active,
6327 "encoder->connectors_active not set\n");
6328
6329 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6330 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6331 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6332 return;
6333
6334 crtc = encoder->base.crtc;
6335
6336 I915_STATE_WARN(!crtc->state->enable,
6337 "crtc not enabled\n");
6338 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6339 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6340 "encoder active on the wrong pipe\n");
6341 }
6342 }
6343 }
6344
6345 int intel_connector_init(struct intel_connector *connector)
6346 {
6347 struct drm_connector_state *connector_state;
6348
6349 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6350 if (!connector_state)
6351 return -ENOMEM;
6352
6353 connector->base.state = connector_state;
6354 return 0;
6355 }
6356
6357 struct intel_connector *intel_connector_alloc(void)
6358 {
6359 struct intel_connector *connector;
6360
6361 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6362 if (!connector)
6363 return NULL;
6364
6365 if (intel_connector_init(connector) < 0) {
6366 kfree(connector);
6367 return NULL;
6368 }
6369
6370 return connector;
6371 }
6372
6373 /* Even simpler default implementation, if there's really no special case to
6374 * consider. */
6375 void intel_connector_dpms(struct drm_connector *connector, int mode)
6376 {
6377 /* All the simple cases only support two dpms states. */
6378 if (mode != DRM_MODE_DPMS_ON)
6379 mode = DRM_MODE_DPMS_OFF;
6380
6381 if (mode == connector->dpms)
6382 return;
6383
6384 connector->dpms = mode;
6385
6386 /* Only need to change hw state when actually enabled */
6387 if (connector->encoder)
6388 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6389
6390 intel_modeset_check_state(connector->dev);
6391 }
6392
6393 /* Simple connector->get_hw_state implementation for encoders that support only
6394 * one connector and no cloning and hence the encoder state determines the state
6395 * of the connector. */
6396 bool intel_connector_get_hw_state(struct intel_connector *connector)
6397 {
6398 enum pipe pipe = 0;
6399 struct intel_encoder *encoder = connector->encoder;
6400
6401 return encoder->get_hw_state(encoder, &pipe);
6402 }
6403
6404 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6405 {
6406 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6407 return crtc_state->fdi_lanes;
6408
6409 return 0;
6410 }
6411
6412 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6413 struct intel_crtc_state *pipe_config)
6414 {
6415 struct drm_atomic_state *state = pipe_config->base.state;
6416 struct intel_crtc *other_crtc;
6417 struct intel_crtc_state *other_crtc_state;
6418
6419 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6420 pipe_name(pipe), pipe_config->fdi_lanes);
6421 if (pipe_config->fdi_lanes > 4) {
6422 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6423 pipe_name(pipe), pipe_config->fdi_lanes);
6424 return -EINVAL;
6425 }
6426
6427 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6428 if (pipe_config->fdi_lanes > 2) {
6429 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6430 pipe_config->fdi_lanes);
6431 return -EINVAL;
6432 } else {
6433 return 0;
6434 }
6435 }
6436
6437 if (INTEL_INFO(dev)->num_pipes == 2)
6438 return 0;
6439
6440 /* Ivybridge 3 pipe is really complicated */
6441 switch (pipe) {
6442 case PIPE_A:
6443 return 0;
6444 case PIPE_B:
6445 if (pipe_config->fdi_lanes <= 2)
6446 return 0;
6447
6448 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6449 other_crtc_state =
6450 intel_atomic_get_crtc_state(state, other_crtc);
6451 if (IS_ERR(other_crtc_state))
6452 return PTR_ERR(other_crtc_state);
6453
6454 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6455 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6456 pipe_name(pipe), pipe_config->fdi_lanes);
6457 return -EINVAL;
6458 }
6459 return 0;
6460 case PIPE_C:
6461 if (pipe_config->fdi_lanes > 2) {
6462 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6463 pipe_name(pipe), pipe_config->fdi_lanes);
6464 return -EINVAL;
6465 }
6466
6467 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6468 other_crtc_state =
6469 intel_atomic_get_crtc_state(state, other_crtc);
6470 if (IS_ERR(other_crtc_state))
6471 return PTR_ERR(other_crtc_state);
6472
6473 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6474 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6475 return -EINVAL;
6476 }
6477 return 0;
6478 default:
6479 BUG();
6480 }
6481 }
6482
6483 #define RETRY 1
6484 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6485 struct intel_crtc_state *pipe_config)
6486 {
6487 struct drm_device *dev = intel_crtc->base.dev;
6488 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6489 int lane, link_bw, fdi_dotclock, ret;
6490 bool needs_recompute = false;
6491
6492 retry:
6493 /* FDI is a binary signal running at ~2.7GHz, encoding
6494 * each output octet as 10 bits. The actual frequency
6495 * is stored as a divider into a 100MHz clock, and the
6496 * mode pixel clock is stored in units of 1KHz.
6497 * Hence the bw of each lane in terms of the mode signal
6498 * is:
6499 */
6500 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6501
6502 fdi_dotclock = adjusted_mode->crtc_clock;
6503
6504 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6505 pipe_config->pipe_bpp);
6506
6507 pipe_config->fdi_lanes = lane;
6508
6509 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6510 link_bw, &pipe_config->fdi_m_n);
6511
6512 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6513 intel_crtc->pipe, pipe_config);
6514 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6515 pipe_config->pipe_bpp -= 2*3;
6516 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6517 pipe_config->pipe_bpp);
6518 needs_recompute = true;
6519 pipe_config->bw_constrained = true;
6520
6521 goto retry;
6522 }
6523
6524 if (needs_recompute)
6525 return RETRY;
6526
6527 return ret;
6528 }
6529
6530 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6531 struct intel_crtc_state *pipe_config)
6532 {
6533 if (pipe_config->pipe_bpp > 24)
6534 return false;
6535
6536 /* HSW can handle pixel rate up to cdclk? */
6537 if (IS_HASWELL(dev_priv->dev))
6538 return true;
6539
6540 /*
6541 * We compare against max which means we must take
6542 * the increased cdclk requirement into account when
6543 * calculating the new cdclk.
6544 *
6545 * Should measure whether using a lower cdclk w/o IPS
6546 */
6547 return ilk_pipe_pixel_rate(pipe_config) <=
6548 dev_priv->max_cdclk_freq * 95 / 100;
6549 }
6550
6551 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6552 struct intel_crtc_state *pipe_config)
6553 {
6554 struct drm_device *dev = crtc->base.dev;
6555 struct drm_i915_private *dev_priv = dev->dev_private;
6556
6557 pipe_config->ips_enabled = i915.enable_ips &&
6558 hsw_crtc_supports_ips(crtc) &&
6559 pipe_config_supports_ips(dev_priv, pipe_config);
6560 }
6561
6562 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6563 struct intel_crtc_state *pipe_config)
6564 {
6565 struct drm_device *dev = crtc->base.dev;
6566 struct drm_i915_private *dev_priv = dev->dev_private;
6567 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6568 int ret;
6569
6570 /* FIXME should check pixel clock limits on all platforms */
6571 if (INTEL_INFO(dev)->gen < 4) {
6572 int clock_limit = dev_priv->max_cdclk_freq;
6573
6574 /*
6575 * Enable pixel doubling when the dot clock
6576 * is > 90% of the (display) core speed.
6577 *
6578 * GDG double wide on either pipe,
6579 * otherwise pipe A only.
6580 */
6581 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6582 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6583 clock_limit *= 2;
6584 pipe_config->double_wide = true;
6585 }
6586
6587 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6588 return -EINVAL;
6589 }
6590
6591 /*
6592 * Pipe horizontal size must be even in:
6593 * - DVO ganged mode
6594 * - LVDS dual channel mode
6595 * - Double wide pipe
6596 */
6597 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6598 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6599 pipe_config->pipe_src_w &= ~1;
6600
6601 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6602 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6603 */
6604 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6605 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6606 return -EINVAL;
6607
6608 if (HAS_IPS(dev))
6609 hsw_compute_ips_config(crtc, pipe_config);
6610
6611 if (pipe_config->has_pch_encoder)
6612 return ironlake_fdi_compute_config(crtc, pipe_config);
6613
6614 /* FIXME: remove below call once atomic mode set is place and all crtc
6615 * related checks called from atomic_crtc_check function */
6616 ret = 0;
6617 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6618 crtc, pipe_config->base.state);
6619 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6620
6621 return ret;
6622 }
6623
6624 static int skylake_get_display_clock_speed(struct drm_device *dev)
6625 {
6626 struct drm_i915_private *dev_priv = to_i915(dev);
6627 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6628 uint32_t cdctl = I915_READ(CDCLK_CTL);
6629 uint32_t linkrate;
6630
6631 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6632 return 24000; /* 24MHz is the cd freq with NSSC ref */
6633
6634 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6635 return 540000;
6636
6637 linkrate = (I915_READ(DPLL_CTRL1) &
6638 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6639
6640 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6641 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6642 /* vco 8640 */
6643 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6644 case CDCLK_FREQ_450_432:
6645 return 432000;
6646 case CDCLK_FREQ_337_308:
6647 return 308570;
6648 case CDCLK_FREQ_675_617:
6649 return 617140;
6650 default:
6651 WARN(1, "Unknown cd freq selection\n");
6652 }
6653 } else {
6654 /* vco 8100 */
6655 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6656 case CDCLK_FREQ_450_432:
6657 return 450000;
6658 case CDCLK_FREQ_337_308:
6659 return 337500;
6660 case CDCLK_FREQ_675_617:
6661 return 675000;
6662 default:
6663 WARN(1, "Unknown cd freq selection\n");
6664 }
6665 }
6666
6667 /* error case, do as if DPLL0 isn't enabled */
6668 return 24000;
6669 }
6670
6671 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6672 {
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 uint32_t lcpll = I915_READ(LCPLL_CTL);
6675 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6676
6677 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6678 return 800000;
6679 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6680 return 450000;
6681 else if (freq == LCPLL_CLK_FREQ_450)
6682 return 450000;
6683 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6684 return 540000;
6685 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6686 return 337500;
6687 else
6688 return 675000;
6689 }
6690
6691 static int haswell_get_display_clock_speed(struct drm_device *dev)
6692 {
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694 uint32_t lcpll = I915_READ(LCPLL_CTL);
6695 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6696
6697 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6698 return 800000;
6699 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6700 return 450000;
6701 else if (freq == LCPLL_CLK_FREQ_450)
6702 return 450000;
6703 else if (IS_HSW_ULT(dev))
6704 return 337500;
6705 else
6706 return 540000;
6707 }
6708
6709 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6710 {
6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 u32 val;
6713 int divider;
6714
6715 if (dev_priv->hpll_freq == 0)
6716 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6717
6718 mutex_lock(&dev_priv->sb_lock);
6719 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6720 mutex_unlock(&dev_priv->sb_lock);
6721
6722 divider = val & DISPLAY_FREQUENCY_VALUES;
6723
6724 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6725 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6726 "cdclk change in progress\n");
6727
6728 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6729 }
6730
6731 static int ilk_get_display_clock_speed(struct drm_device *dev)
6732 {
6733 return 450000;
6734 }
6735
6736 static int i945_get_display_clock_speed(struct drm_device *dev)
6737 {
6738 return 400000;
6739 }
6740
6741 static int i915_get_display_clock_speed(struct drm_device *dev)
6742 {
6743 return 333333;
6744 }
6745
6746 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6747 {
6748 return 200000;
6749 }
6750
6751 static int pnv_get_display_clock_speed(struct drm_device *dev)
6752 {
6753 u16 gcfgc = 0;
6754
6755 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6756
6757 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6758 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6759 return 266667;
6760 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6761 return 333333;
6762 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6763 return 444444;
6764 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6765 return 200000;
6766 default:
6767 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6768 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6769 return 133333;
6770 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6771 return 166667;
6772 }
6773 }
6774
6775 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6776 {
6777 u16 gcfgc = 0;
6778
6779 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780
6781 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6782 return 133333;
6783 else {
6784 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6785 case GC_DISPLAY_CLOCK_333_MHZ:
6786 return 333333;
6787 default:
6788 case GC_DISPLAY_CLOCK_190_200_MHZ:
6789 return 190000;
6790 }
6791 }
6792 }
6793
6794 static int i865_get_display_clock_speed(struct drm_device *dev)
6795 {
6796 return 266667;
6797 }
6798
6799 static int i85x_get_display_clock_speed(struct drm_device *dev)
6800 {
6801 u16 hpllcc = 0;
6802
6803 /*
6804 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6805 * encoding is different :(
6806 * FIXME is this the right way to detect 852GM/852GMV?
6807 */
6808 if (dev->pdev->revision == 0x1)
6809 return 133333;
6810
6811 pci_bus_read_config_word(dev->pdev->bus,
6812 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6813
6814 /* Assume that the hardware is in the high speed state. This
6815 * should be the default.
6816 */
6817 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6818 case GC_CLOCK_133_200:
6819 case GC_CLOCK_133_200_2:
6820 case GC_CLOCK_100_200:
6821 return 200000;
6822 case GC_CLOCK_166_250:
6823 return 250000;
6824 case GC_CLOCK_100_133:
6825 return 133333;
6826 case GC_CLOCK_133_266:
6827 case GC_CLOCK_133_266_2:
6828 case GC_CLOCK_166_266:
6829 return 266667;
6830 }
6831
6832 /* Shouldn't happen */
6833 return 0;
6834 }
6835
6836 static int i830_get_display_clock_speed(struct drm_device *dev)
6837 {
6838 return 133333;
6839 }
6840
6841 static unsigned int intel_hpll_vco(struct drm_device *dev)
6842 {
6843 struct drm_i915_private *dev_priv = dev->dev_private;
6844 static const unsigned int blb_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 4800000,
6849 [4] = 6400000,
6850 };
6851 static const unsigned int pnv_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 4800000,
6856 [4] = 2666667,
6857 };
6858 static const unsigned int cl_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 6400000,
6863 [4] = 3333333,
6864 [5] = 3566667,
6865 [6] = 4266667,
6866 };
6867 static const unsigned int elk_vco[8] = {
6868 [0] = 3200000,
6869 [1] = 4000000,
6870 [2] = 5333333,
6871 [3] = 4800000,
6872 };
6873 static const unsigned int ctg_vco[8] = {
6874 [0] = 3200000,
6875 [1] = 4000000,
6876 [2] = 5333333,
6877 [3] = 6400000,
6878 [4] = 2666667,
6879 [5] = 4266667,
6880 };
6881 const unsigned int *vco_table;
6882 unsigned int vco;
6883 uint8_t tmp = 0;
6884
6885 /* FIXME other chipsets? */
6886 if (IS_GM45(dev))
6887 vco_table = ctg_vco;
6888 else if (IS_G4X(dev))
6889 vco_table = elk_vco;
6890 else if (IS_CRESTLINE(dev))
6891 vco_table = cl_vco;
6892 else if (IS_PINEVIEW(dev))
6893 vco_table = pnv_vco;
6894 else if (IS_G33(dev))
6895 vco_table = blb_vco;
6896 else
6897 return 0;
6898
6899 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6900
6901 vco = vco_table[tmp & 0x7];
6902 if (vco == 0)
6903 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6904 else
6905 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6906
6907 return vco;
6908 }
6909
6910 static int gm45_get_display_clock_speed(struct drm_device *dev)
6911 {
6912 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6913 uint16_t tmp = 0;
6914
6915 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6916
6917 cdclk_sel = (tmp >> 12) & 0x1;
6918
6919 switch (vco) {
6920 case 2666667:
6921 case 4000000:
6922 case 5333333:
6923 return cdclk_sel ? 333333 : 222222;
6924 case 3200000:
6925 return cdclk_sel ? 320000 : 228571;
6926 default:
6927 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6928 return 222222;
6929 }
6930 }
6931
6932 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6933 {
6934 static const uint8_t div_3200[] = { 16, 10, 8 };
6935 static const uint8_t div_4000[] = { 20, 12, 10 };
6936 static const uint8_t div_5333[] = { 24, 16, 14 };
6937 const uint8_t *div_table;
6938 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6939 uint16_t tmp = 0;
6940
6941 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942
6943 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6944
6945 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6946 goto fail;
6947
6948 switch (vco) {
6949 case 3200000:
6950 div_table = div_3200;
6951 break;
6952 case 4000000:
6953 div_table = div_4000;
6954 break;
6955 case 5333333:
6956 div_table = div_5333;
6957 break;
6958 default:
6959 goto fail;
6960 }
6961
6962 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6963
6964 fail:
6965 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6966 return 200000;
6967 }
6968
6969 static int g33_get_display_clock_speed(struct drm_device *dev)
6970 {
6971 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6972 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6973 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6974 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6975 const uint8_t *div_table;
6976 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6977 uint16_t tmp = 0;
6978
6979 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6980
6981 cdclk_sel = (tmp >> 4) & 0x7;
6982
6983 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6984 goto fail;
6985
6986 switch (vco) {
6987 case 3200000:
6988 div_table = div_3200;
6989 break;
6990 case 4000000:
6991 div_table = div_4000;
6992 break;
6993 case 4800000:
6994 div_table = div_4800;
6995 break;
6996 case 5333333:
6997 div_table = div_5333;
6998 break;
6999 default:
7000 goto fail;
7001 }
7002
7003 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7004
7005 fail:
7006 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7007 return 190476;
7008 }
7009
7010 static void
7011 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7012 {
7013 while (*num > DATA_LINK_M_N_MASK ||
7014 *den > DATA_LINK_M_N_MASK) {
7015 *num >>= 1;
7016 *den >>= 1;
7017 }
7018 }
7019
7020 static void compute_m_n(unsigned int m, unsigned int n,
7021 uint32_t *ret_m, uint32_t *ret_n)
7022 {
7023 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7024 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7025 intel_reduce_m_n_ratio(ret_m, ret_n);
7026 }
7027
7028 void
7029 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7030 int pixel_clock, int link_clock,
7031 struct intel_link_m_n *m_n)
7032 {
7033 m_n->tu = 64;
7034
7035 compute_m_n(bits_per_pixel * pixel_clock,
7036 link_clock * nlanes * 8,
7037 &m_n->gmch_m, &m_n->gmch_n);
7038
7039 compute_m_n(pixel_clock, link_clock,
7040 &m_n->link_m, &m_n->link_n);
7041 }
7042
7043 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7044 {
7045 if (i915.panel_use_ssc >= 0)
7046 return i915.panel_use_ssc != 0;
7047 return dev_priv->vbt.lvds_use_ssc
7048 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7049 }
7050
7051 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7052 int num_connectors)
7053 {
7054 struct drm_device *dev = crtc_state->base.crtc->dev;
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056 int refclk;
7057
7058 WARN_ON(!crtc_state->base.state);
7059
7060 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7061 refclk = 100000;
7062 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7063 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7064 refclk = dev_priv->vbt.lvds_ssc_freq;
7065 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7066 } else if (!IS_GEN2(dev)) {
7067 refclk = 96000;
7068 } else {
7069 refclk = 48000;
7070 }
7071
7072 return refclk;
7073 }
7074
7075 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7076 {
7077 return (1 << dpll->n) << 16 | dpll->m2;
7078 }
7079
7080 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7081 {
7082 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7083 }
7084
7085 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7086 struct intel_crtc_state *crtc_state,
7087 intel_clock_t *reduced_clock)
7088 {
7089 struct drm_device *dev = crtc->base.dev;
7090 u32 fp, fp2 = 0;
7091
7092 if (IS_PINEVIEW(dev)) {
7093 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7094 if (reduced_clock)
7095 fp2 = pnv_dpll_compute_fp(reduced_clock);
7096 } else {
7097 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7098 if (reduced_clock)
7099 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7100 }
7101
7102 crtc_state->dpll_hw_state.fp0 = fp;
7103
7104 crtc->lowfreq_avail = false;
7105 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7106 reduced_clock) {
7107 crtc_state->dpll_hw_state.fp1 = fp2;
7108 crtc->lowfreq_avail = true;
7109 } else {
7110 crtc_state->dpll_hw_state.fp1 = fp;
7111 }
7112 }
7113
7114 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7115 pipe)
7116 {
7117 u32 reg_val;
7118
7119 /*
7120 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7121 * and set it to a reasonable value instead.
7122 */
7123 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7124 reg_val &= 0xffffff00;
7125 reg_val |= 0x00000030;
7126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127
7128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7129 reg_val &= 0x8cffffff;
7130 reg_val = 0x8c000000;
7131 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132
7133 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7134 reg_val &= 0xffffff00;
7135 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7136
7137 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7138 reg_val &= 0x00ffffff;
7139 reg_val |= 0xb0000000;
7140 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7141 }
7142
7143 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7144 struct intel_link_m_n *m_n)
7145 {
7146 struct drm_device *dev = crtc->base.dev;
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 int pipe = crtc->pipe;
7149
7150 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7151 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7152 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7153 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7154 }
7155
7156 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7157 struct intel_link_m_n *m_n,
7158 struct intel_link_m_n *m2_n2)
7159 {
7160 struct drm_device *dev = crtc->base.dev;
7161 struct drm_i915_private *dev_priv = dev->dev_private;
7162 int pipe = crtc->pipe;
7163 enum transcoder transcoder = crtc->config->cpu_transcoder;
7164
7165 if (INTEL_INFO(dev)->gen >= 5) {
7166 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7167 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7168 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7169 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7170 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7171 * for gen < 8) and if DRRS is supported (to make sure the
7172 * registers are not unnecessarily accessed).
7173 */
7174 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7175 crtc->config->has_drrs) {
7176 I915_WRITE(PIPE_DATA_M2(transcoder),
7177 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7178 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7179 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7180 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7181 }
7182 } else {
7183 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7184 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7185 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7186 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7187 }
7188 }
7189
7190 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7191 {
7192 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7193
7194 if (m_n == M1_N1) {
7195 dp_m_n = &crtc->config->dp_m_n;
7196 dp_m2_n2 = &crtc->config->dp_m2_n2;
7197 } else if (m_n == M2_N2) {
7198
7199 /*
7200 * M2_N2 registers are not supported. Hence m2_n2 divider value
7201 * needs to be programmed into M1_N1.
7202 */
7203 dp_m_n = &crtc->config->dp_m2_n2;
7204 } else {
7205 DRM_ERROR("Unsupported divider value\n");
7206 return;
7207 }
7208
7209 if (crtc->config->has_pch_encoder)
7210 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7211 else
7212 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7213 }
7214
7215 static void vlv_update_pll(struct intel_crtc *crtc,
7216 struct intel_crtc_state *pipe_config)
7217 {
7218 u32 dpll, dpll_md;
7219
7220 /*
7221 * Enable DPIO clock input. We should never disable the reference
7222 * clock for pipe B, since VGA hotplug / manual detection depends
7223 * on it.
7224 */
7225 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7226 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7227 /* We should never disable this, set it here for state tracking */
7228 if (crtc->pipe == PIPE_B)
7229 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7230 dpll |= DPLL_VCO_ENABLE;
7231 pipe_config->dpll_hw_state.dpll = dpll;
7232
7233 dpll_md = (pipe_config->pixel_multiplier - 1)
7234 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7235 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7236 }
7237
7238 static void vlv_prepare_pll(struct intel_crtc *crtc,
7239 const struct intel_crtc_state *pipe_config)
7240 {
7241 struct drm_device *dev = crtc->base.dev;
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 int pipe = crtc->pipe;
7244 u32 mdiv;
7245 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7246 u32 coreclk, reg_val;
7247
7248 mutex_lock(&dev_priv->sb_lock);
7249
7250 bestn = pipe_config->dpll.n;
7251 bestm1 = pipe_config->dpll.m1;
7252 bestm2 = pipe_config->dpll.m2;
7253 bestp1 = pipe_config->dpll.p1;
7254 bestp2 = pipe_config->dpll.p2;
7255
7256 /* See eDP HDMI DPIO driver vbios notes doc */
7257
7258 /* PLL B needs special handling */
7259 if (pipe == PIPE_B)
7260 vlv_pllb_recal_opamp(dev_priv, pipe);
7261
7262 /* Set up Tx target for periodic Rcomp update */
7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7264
7265 /* Disable target IRef on PLL */
7266 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7267 reg_val &= 0x00ffffff;
7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7269
7270 /* Disable fast lock */
7271 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7272
7273 /* Set idtafcrecal before PLL is enabled */
7274 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7275 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7276 mdiv |= ((bestn << DPIO_N_SHIFT));
7277 mdiv |= (1 << DPIO_K_SHIFT);
7278
7279 /*
7280 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7281 * but we don't support that).
7282 * Note: don't use the DAC post divider as it seems unstable.
7283 */
7284 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7286
7287 mdiv |= DPIO_ENABLE_CALIBRATION;
7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7289
7290 /* Set HBR and RBR LPF coefficients */
7291 if (pipe_config->port_clock == 162000 ||
7292 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7293 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7295 0x009f0003);
7296 else
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7298 0x00d0000f);
7299
7300 if (pipe_config->has_dp_encoder) {
7301 /* Use SSC source */
7302 if (pipe == PIPE_A)
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7304 0x0df40000);
7305 else
7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7307 0x0df70000);
7308 } else { /* HDMI or VGA */
7309 /* Use bend source */
7310 if (pipe == PIPE_A)
7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7312 0x0df70000);
7313 else
7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7315 0x0df40000);
7316 }
7317
7318 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7319 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7320 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7321 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7322 coreclk |= 0x01000000;
7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7324
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7326 mutex_unlock(&dev_priv->sb_lock);
7327 }
7328
7329 static void chv_update_pll(struct intel_crtc *crtc,
7330 struct intel_crtc_state *pipe_config)
7331 {
7332 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7333 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7334 DPLL_VCO_ENABLE;
7335 if (crtc->pipe != PIPE_A)
7336 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7337
7338 pipe_config->dpll_hw_state.dpll_md =
7339 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7340 }
7341
7342 static void chv_prepare_pll(struct intel_crtc *crtc,
7343 const struct intel_crtc_state *pipe_config)
7344 {
7345 struct drm_device *dev = crtc->base.dev;
7346 struct drm_i915_private *dev_priv = dev->dev_private;
7347 int pipe = crtc->pipe;
7348 int dpll_reg = DPLL(crtc->pipe);
7349 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7350 u32 loopfilter, tribuf_calcntr;
7351 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7352 u32 dpio_val;
7353 int vco;
7354
7355 bestn = pipe_config->dpll.n;
7356 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7357 bestm1 = pipe_config->dpll.m1;
7358 bestm2 = pipe_config->dpll.m2 >> 22;
7359 bestp1 = pipe_config->dpll.p1;
7360 bestp2 = pipe_config->dpll.p2;
7361 vco = pipe_config->dpll.vco;
7362 dpio_val = 0;
7363 loopfilter = 0;
7364
7365 /*
7366 * Enable Refclk and SSC
7367 */
7368 I915_WRITE(dpll_reg,
7369 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7370
7371 mutex_lock(&dev_priv->sb_lock);
7372
7373 /* p1 and p2 divider */
7374 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7375 5 << DPIO_CHV_S1_DIV_SHIFT |
7376 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7377 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7378 1 << DPIO_CHV_K_DIV_SHIFT);
7379
7380 /* Feedback post-divider - m2 */
7381 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7382
7383 /* Feedback refclk divider - n and m1 */
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7385 DPIO_CHV_M1_DIV_BY_2 |
7386 1 << DPIO_CHV_N_DIV_SHIFT);
7387
7388 /* M2 fraction division */
7389 if (bestm2_frac)
7390 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7391
7392 /* M2 fraction division enable */
7393 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7394 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7395 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7396 if (bestm2_frac)
7397 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7399
7400 /* Program digital lock detect threshold */
7401 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7402 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7403 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7404 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7405 if (!bestm2_frac)
7406 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7407 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7408
7409 /* Loop filter */
7410 if (vco == 5400000) {
7411 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7412 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7413 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414 tribuf_calcntr = 0x9;
7415 } else if (vco <= 6200000) {
7416 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7417 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7418 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7419 tribuf_calcntr = 0x9;
7420 } else if (vco <= 6480000) {
7421 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7422 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7423 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424 tribuf_calcntr = 0x8;
7425 } else {
7426 /* Not supported. Apply the same limits as in the max case */
7427 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7428 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7429 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7430 tribuf_calcntr = 0;
7431 }
7432 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7433
7434 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7435 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7436 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7437 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7438
7439 /* AFC Recal */
7440 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7441 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7442 DPIO_AFC_RECAL);
7443
7444 mutex_unlock(&dev_priv->sb_lock);
7445 }
7446
7447 /**
7448 * vlv_force_pll_on - forcibly enable just the PLL
7449 * @dev_priv: i915 private structure
7450 * @pipe: pipe PLL to enable
7451 * @dpll: PLL configuration
7452 *
7453 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7454 * in cases where we need the PLL enabled even when @pipe is not going to
7455 * be enabled.
7456 */
7457 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7458 const struct dpll *dpll)
7459 {
7460 struct intel_crtc *crtc =
7461 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7462 struct intel_crtc_state pipe_config = {
7463 .base.crtc = &crtc->base,
7464 .pixel_multiplier = 1,
7465 .dpll = *dpll,
7466 };
7467
7468 if (IS_CHERRYVIEW(dev)) {
7469 chv_update_pll(crtc, &pipe_config);
7470 chv_prepare_pll(crtc, &pipe_config);
7471 chv_enable_pll(crtc, &pipe_config);
7472 } else {
7473 vlv_update_pll(crtc, &pipe_config);
7474 vlv_prepare_pll(crtc, &pipe_config);
7475 vlv_enable_pll(crtc, &pipe_config);
7476 }
7477 }
7478
7479 /**
7480 * vlv_force_pll_off - forcibly disable just the PLL
7481 * @dev_priv: i915 private structure
7482 * @pipe: pipe PLL to disable
7483 *
7484 * Disable the PLL for @pipe. To be used in cases where we need
7485 * the PLL enabled even when @pipe is not going to be enabled.
7486 */
7487 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7488 {
7489 if (IS_CHERRYVIEW(dev))
7490 chv_disable_pll(to_i915(dev), pipe);
7491 else
7492 vlv_disable_pll(to_i915(dev), pipe);
7493 }
7494
7495 static void i9xx_update_pll(struct intel_crtc *crtc,
7496 struct intel_crtc_state *crtc_state,
7497 intel_clock_t *reduced_clock,
7498 int num_connectors)
7499 {
7500 struct drm_device *dev = crtc->base.dev;
7501 struct drm_i915_private *dev_priv = dev->dev_private;
7502 u32 dpll;
7503 bool is_sdvo;
7504 struct dpll *clock = &crtc_state->dpll;
7505
7506 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7507
7508 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7510
7511 dpll = DPLL_VGA_MODE_DIS;
7512
7513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7514 dpll |= DPLLB_MODE_LVDS;
7515 else
7516 dpll |= DPLLB_MODE_DAC_SERIAL;
7517
7518 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7519 dpll |= (crtc_state->pixel_multiplier - 1)
7520 << SDVO_MULTIPLIER_SHIFT_HIRES;
7521 }
7522
7523 if (is_sdvo)
7524 dpll |= DPLL_SDVO_HIGH_SPEED;
7525
7526 if (crtc_state->has_dp_encoder)
7527 dpll |= DPLL_SDVO_HIGH_SPEED;
7528
7529 /* compute bitmask from p1 value */
7530 if (IS_PINEVIEW(dev))
7531 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7532 else {
7533 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7534 if (IS_G4X(dev) && reduced_clock)
7535 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7536 }
7537 switch (clock->p2) {
7538 case 5:
7539 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7540 break;
7541 case 7:
7542 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7543 break;
7544 case 10:
7545 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7546 break;
7547 case 14:
7548 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7549 break;
7550 }
7551 if (INTEL_INFO(dev)->gen >= 4)
7552 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7553
7554 if (crtc_state->sdvo_tv_clock)
7555 dpll |= PLL_REF_INPUT_TVCLKINBC;
7556 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7557 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7558 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7559 else
7560 dpll |= PLL_REF_INPUT_DREFCLK;
7561
7562 dpll |= DPLL_VCO_ENABLE;
7563 crtc_state->dpll_hw_state.dpll = dpll;
7564
7565 if (INTEL_INFO(dev)->gen >= 4) {
7566 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7567 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7568 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7569 }
7570 }
7571
7572 static void i8xx_update_pll(struct intel_crtc *crtc,
7573 struct intel_crtc_state *crtc_state,
7574 intel_clock_t *reduced_clock,
7575 int num_connectors)
7576 {
7577 struct drm_device *dev = crtc->base.dev;
7578 struct drm_i915_private *dev_priv = dev->dev_private;
7579 u32 dpll;
7580 struct dpll *clock = &crtc_state->dpll;
7581
7582 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7583
7584 dpll = DPLL_VGA_MODE_DIS;
7585
7586 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7588 } else {
7589 if (clock->p1 == 2)
7590 dpll |= PLL_P1_DIVIDE_BY_TWO;
7591 else
7592 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593 if (clock->p2 == 4)
7594 dpll |= PLL_P2_DIVIDE_BY_4;
7595 }
7596
7597 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7598 dpll |= DPLL_DVO_2X_MODE;
7599
7600 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7601 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7602 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7603 else
7604 dpll |= PLL_REF_INPUT_DREFCLK;
7605
7606 dpll |= DPLL_VCO_ENABLE;
7607 crtc_state->dpll_hw_state.dpll = dpll;
7608 }
7609
7610 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7611 {
7612 struct drm_device *dev = intel_crtc->base.dev;
7613 struct drm_i915_private *dev_priv = dev->dev_private;
7614 enum pipe pipe = intel_crtc->pipe;
7615 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7616 struct drm_display_mode *adjusted_mode =
7617 &intel_crtc->config->base.adjusted_mode;
7618 uint32_t crtc_vtotal, crtc_vblank_end;
7619 int vsyncshift = 0;
7620
7621 /* We need to be careful not to changed the adjusted mode, for otherwise
7622 * the hw state checker will get angry at the mismatch. */
7623 crtc_vtotal = adjusted_mode->crtc_vtotal;
7624 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7625
7626 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7627 /* the chip adds 2 halflines automatically */
7628 crtc_vtotal -= 1;
7629 crtc_vblank_end -= 1;
7630
7631 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7632 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7633 else
7634 vsyncshift = adjusted_mode->crtc_hsync_start -
7635 adjusted_mode->crtc_htotal / 2;
7636 if (vsyncshift < 0)
7637 vsyncshift += adjusted_mode->crtc_htotal;
7638 }
7639
7640 if (INTEL_INFO(dev)->gen > 3)
7641 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7642
7643 I915_WRITE(HTOTAL(cpu_transcoder),
7644 (adjusted_mode->crtc_hdisplay - 1) |
7645 ((adjusted_mode->crtc_htotal - 1) << 16));
7646 I915_WRITE(HBLANK(cpu_transcoder),
7647 (adjusted_mode->crtc_hblank_start - 1) |
7648 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7649 I915_WRITE(HSYNC(cpu_transcoder),
7650 (adjusted_mode->crtc_hsync_start - 1) |
7651 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7652
7653 I915_WRITE(VTOTAL(cpu_transcoder),
7654 (adjusted_mode->crtc_vdisplay - 1) |
7655 ((crtc_vtotal - 1) << 16));
7656 I915_WRITE(VBLANK(cpu_transcoder),
7657 (adjusted_mode->crtc_vblank_start - 1) |
7658 ((crtc_vblank_end - 1) << 16));
7659 I915_WRITE(VSYNC(cpu_transcoder),
7660 (adjusted_mode->crtc_vsync_start - 1) |
7661 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7662
7663 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7664 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7665 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7666 * bits. */
7667 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7668 (pipe == PIPE_B || pipe == PIPE_C))
7669 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7670
7671 /* pipesrc controls the size that is scaled from, which should
7672 * always be the user's requested size.
7673 */
7674 I915_WRITE(PIPESRC(pipe),
7675 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7676 (intel_crtc->config->pipe_src_h - 1));
7677 }
7678
7679 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7680 struct intel_crtc_state *pipe_config)
7681 {
7682 struct drm_device *dev = crtc->base.dev;
7683 struct drm_i915_private *dev_priv = dev->dev_private;
7684 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7685 uint32_t tmp;
7686
7687 tmp = I915_READ(HTOTAL(cpu_transcoder));
7688 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7690 tmp = I915_READ(HBLANK(cpu_transcoder));
7691 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7693 tmp = I915_READ(HSYNC(cpu_transcoder));
7694 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7696
7697 tmp = I915_READ(VTOTAL(cpu_transcoder));
7698 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7699 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7700 tmp = I915_READ(VBLANK(cpu_transcoder));
7701 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7702 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7703 tmp = I915_READ(VSYNC(cpu_transcoder));
7704 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7705 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7706
7707 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7708 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7709 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7710 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7711 }
7712
7713 tmp = I915_READ(PIPESRC(crtc->pipe));
7714 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7715 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7716
7717 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7718 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7719 }
7720
7721 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7722 struct intel_crtc_state *pipe_config)
7723 {
7724 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7725 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7726 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7727 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7728
7729 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7730 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7731 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7732 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7733
7734 mode->flags = pipe_config->base.adjusted_mode.flags;
7735
7736 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7737 mode->flags |= pipe_config->base.adjusted_mode.flags;
7738 }
7739
7740 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7741 {
7742 struct drm_device *dev = intel_crtc->base.dev;
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7744 uint32_t pipeconf;
7745
7746 pipeconf = 0;
7747
7748 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7749 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7750 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7751
7752 if (intel_crtc->config->double_wide)
7753 pipeconf |= PIPECONF_DOUBLE_WIDE;
7754
7755 /* only g4x and later have fancy bpc/dither controls */
7756 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7757 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7758 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7759 pipeconf |= PIPECONF_DITHER_EN |
7760 PIPECONF_DITHER_TYPE_SP;
7761
7762 switch (intel_crtc->config->pipe_bpp) {
7763 case 18:
7764 pipeconf |= PIPECONF_6BPC;
7765 break;
7766 case 24:
7767 pipeconf |= PIPECONF_8BPC;
7768 break;
7769 case 30:
7770 pipeconf |= PIPECONF_10BPC;
7771 break;
7772 default:
7773 /* Case prevented by intel_choose_pipe_bpp_dither. */
7774 BUG();
7775 }
7776 }
7777
7778 if (HAS_PIPE_CXSR(dev)) {
7779 if (intel_crtc->lowfreq_avail) {
7780 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7781 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7782 } else {
7783 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7784 }
7785 }
7786
7787 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7788 if (INTEL_INFO(dev)->gen < 4 ||
7789 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7790 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7791 else
7792 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7793 } else
7794 pipeconf |= PIPECONF_PROGRESSIVE;
7795
7796 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7797 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7798
7799 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7800 POSTING_READ(PIPECONF(intel_crtc->pipe));
7801 }
7802
7803 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7804 struct intel_crtc_state *crtc_state)
7805 {
7806 struct drm_device *dev = crtc->base.dev;
7807 struct drm_i915_private *dev_priv = dev->dev_private;
7808 int refclk, num_connectors = 0;
7809 intel_clock_t clock, reduced_clock;
7810 bool ok, has_reduced_clock = false;
7811 bool is_lvds = false, is_dsi = false;
7812 struct intel_encoder *encoder;
7813 const intel_limit_t *limit;
7814 struct drm_atomic_state *state = crtc_state->base.state;
7815 struct drm_connector *connector;
7816 struct drm_connector_state *connector_state;
7817 int i;
7818
7819 memset(&crtc_state->dpll_hw_state, 0,
7820 sizeof(crtc_state->dpll_hw_state));
7821
7822 for_each_connector_in_state(state, connector, connector_state, i) {
7823 if (connector_state->crtc != &crtc->base)
7824 continue;
7825
7826 encoder = to_intel_encoder(connector_state->best_encoder);
7827
7828 switch (encoder->type) {
7829 case INTEL_OUTPUT_LVDS:
7830 is_lvds = true;
7831 break;
7832 case INTEL_OUTPUT_DSI:
7833 is_dsi = true;
7834 break;
7835 default:
7836 break;
7837 }
7838
7839 num_connectors++;
7840 }
7841
7842 if (is_dsi)
7843 return 0;
7844
7845 if (!crtc_state->clock_set) {
7846 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7847
7848 /*
7849 * Returns a set of divisors for the desired target clock with
7850 * the given refclk, or FALSE. The returned values represent
7851 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7852 * 2) / p1 / p2.
7853 */
7854 limit = intel_limit(crtc_state, refclk);
7855 ok = dev_priv->display.find_dpll(limit, crtc_state,
7856 crtc_state->port_clock,
7857 refclk, NULL, &clock);
7858 if (!ok) {
7859 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7860 return -EINVAL;
7861 }
7862
7863 if (is_lvds && dev_priv->lvds_downclock_avail) {
7864 /*
7865 * Ensure we match the reduced clock's P to the target
7866 * clock. If the clocks don't match, we can't switch
7867 * the display clock by using the FP0/FP1. In such case
7868 * we will disable the LVDS downclock feature.
7869 */
7870 has_reduced_clock =
7871 dev_priv->display.find_dpll(limit, crtc_state,
7872 dev_priv->lvds_downclock,
7873 refclk, &clock,
7874 &reduced_clock);
7875 }
7876 /* Compat-code for transition, will disappear. */
7877 crtc_state->dpll.n = clock.n;
7878 crtc_state->dpll.m1 = clock.m1;
7879 crtc_state->dpll.m2 = clock.m2;
7880 crtc_state->dpll.p1 = clock.p1;
7881 crtc_state->dpll.p2 = clock.p2;
7882 }
7883
7884 if (IS_GEN2(dev)) {
7885 i8xx_update_pll(crtc, crtc_state,
7886 has_reduced_clock ? &reduced_clock : NULL,
7887 num_connectors);
7888 } else if (IS_CHERRYVIEW(dev)) {
7889 chv_update_pll(crtc, crtc_state);
7890 } else if (IS_VALLEYVIEW(dev)) {
7891 vlv_update_pll(crtc, crtc_state);
7892 } else {
7893 i9xx_update_pll(crtc, crtc_state,
7894 has_reduced_clock ? &reduced_clock : NULL,
7895 num_connectors);
7896 }
7897
7898 return 0;
7899 }
7900
7901 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7902 struct intel_crtc_state *pipe_config)
7903 {
7904 struct drm_device *dev = crtc->base.dev;
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 uint32_t tmp;
7907
7908 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7909 return;
7910
7911 tmp = I915_READ(PFIT_CONTROL);
7912 if (!(tmp & PFIT_ENABLE))
7913 return;
7914
7915 /* Check whether the pfit is attached to our pipe. */
7916 if (INTEL_INFO(dev)->gen < 4) {
7917 if (crtc->pipe != PIPE_B)
7918 return;
7919 } else {
7920 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7921 return;
7922 }
7923
7924 pipe_config->gmch_pfit.control = tmp;
7925 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7926 if (INTEL_INFO(dev)->gen < 5)
7927 pipe_config->gmch_pfit.lvds_border_bits =
7928 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7929 }
7930
7931 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7932 struct intel_crtc_state *pipe_config)
7933 {
7934 struct drm_device *dev = crtc->base.dev;
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 int pipe = pipe_config->cpu_transcoder;
7937 intel_clock_t clock;
7938 u32 mdiv;
7939 int refclk = 100000;
7940
7941 /* In case of MIPI DPLL will not even be used */
7942 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7943 return;
7944
7945 mutex_lock(&dev_priv->sb_lock);
7946 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7947 mutex_unlock(&dev_priv->sb_lock);
7948
7949 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7950 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7951 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7952 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7953 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7954
7955 vlv_clock(refclk, &clock);
7956
7957 /* clock.dot is the fast clock */
7958 pipe_config->port_clock = clock.dot / 5;
7959 }
7960
7961 static void
7962 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7963 struct intel_initial_plane_config *plane_config)
7964 {
7965 struct drm_device *dev = crtc->base.dev;
7966 struct drm_i915_private *dev_priv = dev->dev_private;
7967 u32 val, base, offset;
7968 int pipe = crtc->pipe, plane = crtc->plane;
7969 int fourcc, pixel_format;
7970 unsigned int aligned_height;
7971 struct drm_framebuffer *fb;
7972 struct intel_framebuffer *intel_fb;
7973
7974 val = I915_READ(DSPCNTR(plane));
7975 if (!(val & DISPLAY_PLANE_ENABLE))
7976 return;
7977
7978 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7979 if (!intel_fb) {
7980 DRM_DEBUG_KMS("failed to alloc fb\n");
7981 return;
7982 }
7983
7984 fb = &intel_fb->base;
7985
7986 if (INTEL_INFO(dev)->gen >= 4) {
7987 if (val & DISPPLANE_TILED) {
7988 plane_config->tiling = I915_TILING_X;
7989 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7990 }
7991 }
7992
7993 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7994 fourcc = i9xx_format_to_fourcc(pixel_format);
7995 fb->pixel_format = fourcc;
7996 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7997
7998 if (INTEL_INFO(dev)->gen >= 4) {
7999 if (plane_config->tiling)
8000 offset = I915_READ(DSPTILEOFF(plane));
8001 else
8002 offset = I915_READ(DSPLINOFF(plane));
8003 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8004 } else {
8005 base = I915_READ(DSPADDR(plane));
8006 }
8007 plane_config->base = base;
8008
8009 val = I915_READ(PIPESRC(pipe));
8010 fb->width = ((val >> 16) & 0xfff) + 1;
8011 fb->height = ((val >> 0) & 0xfff) + 1;
8012
8013 val = I915_READ(DSPSTRIDE(pipe));
8014 fb->pitches[0] = val & 0xffffffc0;
8015
8016 aligned_height = intel_fb_align_height(dev, fb->height,
8017 fb->pixel_format,
8018 fb->modifier[0]);
8019
8020 plane_config->size = fb->pitches[0] * aligned_height;
8021
8022 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8023 pipe_name(pipe), plane, fb->width, fb->height,
8024 fb->bits_per_pixel, base, fb->pitches[0],
8025 plane_config->size);
8026
8027 plane_config->fb = intel_fb;
8028 }
8029
8030 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8031 struct intel_crtc_state *pipe_config)
8032 {
8033 struct drm_device *dev = crtc->base.dev;
8034 struct drm_i915_private *dev_priv = dev->dev_private;
8035 int pipe = pipe_config->cpu_transcoder;
8036 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8037 intel_clock_t clock;
8038 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8039 int refclk = 100000;
8040
8041 mutex_lock(&dev_priv->sb_lock);
8042 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8043 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8044 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8045 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8046 mutex_unlock(&dev_priv->sb_lock);
8047
8048 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8049 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8050 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8051 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8052 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8053
8054 chv_clock(refclk, &clock);
8055
8056 /* clock.dot is the fast clock */
8057 pipe_config->port_clock = clock.dot / 5;
8058 }
8059
8060 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8061 struct intel_crtc_state *pipe_config)
8062 {
8063 struct drm_device *dev = crtc->base.dev;
8064 struct drm_i915_private *dev_priv = dev->dev_private;
8065 uint32_t tmp;
8066
8067 if (!intel_display_power_is_enabled(dev_priv,
8068 POWER_DOMAIN_PIPE(crtc->pipe)))
8069 return false;
8070
8071 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8072 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8073
8074 tmp = I915_READ(PIPECONF(crtc->pipe));
8075 if (!(tmp & PIPECONF_ENABLE))
8076 return false;
8077
8078 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8079 switch (tmp & PIPECONF_BPC_MASK) {
8080 case PIPECONF_6BPC:
8081 pipe_config->pipe_bpp = 18;
8082 break;
8083 case PIPECONF_8BPC:
8084 pipe_config->pipe_bpp = 24;
8085 break;
8086 case PIPECONF_10BPC:
8087 pipe_config->pipe_bpp = 30;
8088 break;
8089 default:
8090 break;
8091 }
8092 }
8093
8094 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8095 pipe_config->limited_color_range = true;
8096
8097 if (INTEL_INFO(dev)->gen < 4)
8098 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8099
8100 intel_get_pipe_timings(crtc, pipe_config);
8101
8102 i9xx_get_pfit_config(crtc, pipe_config);
8103
8104 if (INTEL_INFO(dev)->gen >= 4) {
8105 tmp = I915_READ(DPLL_MD(crtc->pipe));
8106 pipe_config->pixel_multiplier =
8107 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8108 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8109 pipe_config->dpll_hw_state.dpll_md = tmp;
8110 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8111 tmp = I915_READ(DPLL(crtc->pipe));
8112 pipe_config->pixel_multiplier =
8113 ((tmp & SDVO_MULTIPLIER_MASK)
8114 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8115 } else {
8116 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8117 * port and will be fixed up in the encoder->get_config
8118 * function. */
8119 pipe_config->pixel_multiplier = 1;
8120 }
8121 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8122 if (!IS_VALLEYVIEW(dev)) {
8123 /*
8124 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8125 * on 830. Filter it out here so that we don't
8126 * report errors due to that.
8127 */
8128 if (IS_I830(dev))
8129 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8130
8131 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8132 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8133 } else {
8134 /* Mask out read-only status bits. */
8135 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8136 DPLL_PORTC_READY_MASK |
8137 DPLL_PORTB_READY_MASK);
8138 }
8139
8140 if (IS_CHERRYVIEW(dev))
8141 chv_crtc_clock_get(crtc, pipe_config);
8142 else if (IS_VALLEYVIEW(dev))
8143 vlv_crtc_clock_get(crtc, pipe_config);
8144 else
8145 i9xx_crtc_clock_get(crtc, pipe_config);
8146
8147 return true;
8148 }
8149
8150 static void ironlake_init_pch_refclk(struct drm_device *dev)
8151 {
8152 struct drm_i915_private *dev_priv = dev->dev_private;
8153 struct intel_encoder *encoder;
8154 u32 val, final;
8155 bool has_lvds = false;
8156 bool has_cpu_edp = false;
8157 bool has_panel = false;
8158 bool has_ck505 = false;
8159 bool can_ssc = false;
8160
8161 /* We need to take the global config into account */
8162 for_each_intel_encoder(dev, encoder) {
8163 switch (encoder->type) {
8164 case INTEL_OUTPUT_LVDS:
8165 has_panel = true;
8166 has_lvds = true;
8167 break;
8168 case INTEL_OUTPUT_EDP:
8169 has_panel = true;
8170 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8171 has_cpu_edp = true;
8172 break;
8173 default:
8174 break;
8175 }
8176 }
8177
8178 if (HAS_PCH_IBX(dev)) {
8179 has_ck505 = dev_priv->vbt.display_clock_mode;
8180 can_ssc = has_ck505;
8181 } else {
8182 has_ck505 = false;
8183 can_ssc = true;
8184 }
8185
8186 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8187 has_panel, has_lvds, has_ck505);
8188
8189 /* Ironlake: try to setup display ref clock before DPLL
8190 * enabling. This is only under driver's control after
8191 * PCH B stepping, previous chipset stepping should be
8192 * ignoring this setting.
8193 */
8194 val = I915_READ(PCH_DREF_CONTROL);
8195
8196 /* As we must carefully and slowly disable/enable each source in turn,
8197 * compute the final state we want first and check if we need to
8198 * make any changes at all.
8199 */
8200 final = val;
8201 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8202 if (has_ck505)
8203 final |= DREF_NONSPREAD_CK505_ENABLE;
8204 else
8205 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8206
8207 final &= ~DREF_SSC_SOURCE_MASK;
8208 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8209 final &= ~DREF_SSC1_ENABLE;
8210
8211 if (has_panel) {
8212 final |= DREF_SSC_SOURCE_ENABLE;
8213
8214 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8215 final |= DREF_SSC1_ENABLE;
8216
8217 if (has_cpu_edp) {
8218 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8219 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8220 else
8221 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8222 } else
8223 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8224 } else {
8225 final |= DREF_SSC_SOURCE_DISABLE;
8226 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8227 }
8228
8229 if (final == val)
8230 return;
8231
8232 /* Always enable nonspread source */
8233 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8234
8235 if (has_ck505)
8236 val |= DREF_NONSPREAD_CK505_ENABLE;
8237 else
8238 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8239
8240 if (has_panel) {
8241 val &= ~DREF_SSC_SOURCE_MASK;
8242 val |= DREF_SSC_SOURCE_ENABLE;
8243
8244 /* SSC must be turned on before enabling the CPU output */
8245 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8246 DRM_DEBUG_KMS("Using SSC on panel\n");
8247 val |= DREF_SSC1_ENABLE;
8248 } else
8249 val &= ~DREF_SSC1_ENABLE;
8250
8251 /* Get SSC going before enabling the outputs */
8252 I915_WRITE(PCH_DREF_CONTROL, val);
8253 POSTING_READ(PCH_DREF_CONTROL);
8254 udelay(200);
8255
8256 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8257
8258 /* Enable CPU source on CPU attached eDP */
8259 if (has_cpu_edp) {
8260 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8261 DRM_DEBUG_KMS("Using SSC on eDP\n");
8262 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8263 } else
8264 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8265 } else
8266 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8267
8268 I915_WRITE(PCH_DREF_CONTROL, val);
8269 POSTING_READ(PCH_DREF_CONTROL);
8270 udelay(200);
8271 } else {
8272 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8273
8274 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8275
8276 /* Turn off CPU output */
8277 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8278
8279 I915_WRITE(PCH_DREF_CONTROL, val);
8280 POSTING_READ(PCH_DREF_CONTROL);
8281 udelay(200);
8282
8283 /* Turn off the SSC source */
8284 val &= ~DREF_SSC_SOURCE_MASK;
8285 val |= DREF_SSC_SOURCE_DISABLE;
8286
8287 /* Turn off SSC1 */
8288 val &= ~DREF_SSC1_ENABLE;
8289
8290 I915_WRITE(PCH_DREF_CONTROL, val);
8291 POSTING_READ(PCH_DREF_CONTROL);
8292 udelay(200);
8293 }
8294
8295 BUG_ON(val != final);
8296 }
8297
8298 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8299 {
8300 uint32_t tmp;
8301
8302 tmp = I915_READ(SOUTH_CHICKEN2);
8303 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8304 I915_WRITE(SOUTH_CHICKEN2, tmp);
8305
8306 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8307 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8308 DRM_ERROR("FDI mPHY reset assert timeout\n");
8309
8310 tmp = I915_READ(SOUTH_CHICKEN2);
8311 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8312 I915_WRITE(SOUTH_CHICKEN2, tmp);
8313
8314 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8315 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8316 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8317 }
8318
8319 /* WaMPhyProgramming:hsw */
8320 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8321 {
8322 uint32_t tmp;
8323
8324 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8325 tmp &= ~(0xFF << 24);
8326 tmp |= (0x12 << 24);
8327 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8328
8329 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8330 tmp |= (1 << 11);
8331 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8332
8333 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8334 tmp |= (1 << 11);
8335 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8338 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8339 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8342 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8343 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8346 tmp &= ~(7 << 13);
8347 tmp |= (5 << 13);
8348 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8351 tmp &= ~(7 << 13);
8352 tmp |= (5 << 13);
8353 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8354
8355 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8356 tmp &= ~0xFF;
8357 tmp |= 0x1C;
8358 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8361 tmp &= ~0xFF;
8362 tmp |= 0x1C;
8363 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8366 tmp &= ~(0xFF << 16);
8367 tmp |= (0x1C << 16);
8368 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8369
8370 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8371 tmp &= ~(0xFF << 16);
8372 tmp |= (0x1C << 16);
8373 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8374
8375 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8376 tmp |= (1 << 27);
8377 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8378
8379 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8380 tmp |= (1 << 27);
8381 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8382
8383 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8384 tmp &= ~(0xF << 28);
8385 tmp |= (4 << 28);
8386 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8387
8388 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8389 tmp &= ~(0xF << 28);
8390 tmp |= (4 << 28);
8391 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8392 }
8393
8394 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8395 * Programming" based on the parameters passed:
8396 * - Sequence to enable CLKOUT_DP
8397 * - Sequence to enable CLKOUT_DP without spread
8398 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8399 */
8400 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8401 bool with_fdi)
8402 {
8403 struct drm_i915_private *dev_priv = dev->dev_private;
8404 uint32_t reg, tmp;
8405
8406 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8407 with_spread = true;
8408 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8409 with_fdi, "LP PCH doesn't have FDI\n"))
8410 with_fdi = false;
8411
8412 mutex_lock(&dev_priv->sb_lock);
8413
8414 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8415 tmp &= ~SBI_SSCCTL_DISABLE;
8416 tmp |= SBI_SSCCTL_PATHALT;
8417 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8418
8419 udelay(24);
8420
8421 if (with_spread) {
8422 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8423 tmp &= ~SBI_SSCCTL_PATHALT;
8424 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8425
8426 if (with_fdi) {
8427 lpt_reset_fdi_mphy(dev_priv);
8428 lpt_program_fdi_mphy(dev_priv);
8429 }
8430 }
8431
8432 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8433 SBI_GEN0 : SBI_DBUFF0;
8434 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8435 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8436 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8437
8438 mutex_unlock(&dev_priv->sb_lock);
8439 }
8440
8441 /* Sequence to disable CLKOUT_DP */
8442 static void lpt_disable_clkout_dp(struct drm_device *dev)
8443 {
8444 struct drm_i915_private *dev_priv = dev->dev_private;
8445 uint32_t reg, tmp;
8446
8447 mutex_lock(&dev_priv->sb_lock);
8448
8449 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8450 SBI_GEN0 : SBI_DBUFF0;
8451 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8452 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8453 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8454
8455 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8456 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8457 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8458 tmp |= SBI_SSCCTL_PATHALT;
8459 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8460 udelay(32);
8461 }
8462 tmp |= SBI_SSCCTL_DISABLE;
8463 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8464 }
8465
8466 mutex_unlock(&dev_priv->sb_lock);
8467 }
8468
8469 static void lpt_init_pch_refclk(struct drm_device *dev)
8470 {
8471 struct intel_encoder *encoder;
8472 bool has_vga = false;
8473
8474 for_each_intel_encoder(dev, encoder) {
8475 switch (encoder->type) {
8476 case INTEL_OUTPUT_ANALOG:
8477 has_vga = true;
8478 break;
8479 default:
8480 break;
8481 }
8482 }
8483
8484 if (has_vga)
8485 lpt_enable_clkout_dp(dev, true, true);
8486 else
8487 lpt_disable_clkout_dp(dev);
8488 }
8489
8490 /*
8491 * Initialize reference clocks when the driver loads
8492 */
8493 void intel_init_pch_refclk(struct drm_device *dev)
8494 {
8495 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8496 ironlake_init_pch_refclk(dev);
8497 else if (HAS_PCH_LPT(dev))
8498 lpt_init_pch_refclk(dev);
8499 }
8500
8501 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8502 {
8503 struct drm_device *dev = crtc_state->base.crtc->dev;
8504 struct drm_i915_private *dev_priv = dev->dev_private;
8505 struct drm_atomic_state *state = crtc_state->base.state;
8506 struct drm_connector *connector;
8507 struct drm_connector_state *connector_state;
8508 struct intel_encoder *encoder;
8509 int num_connectors = 0, i;
8510 bool is_lvds = false;
8511
8512 for_each_connector_in_state(state, connector, connector_state, i) {
8513 if (connector_state->crtc != crtc_state->base.crtc)
8514 continue;
8515
8516 encoder = to_intel_encoder(connector_state->best_encoder);
8517
8518 switch (encoder->type) {
8519 case INTEL_OUTPUT_LVDS:
8520 is_lvds = true;
8521 break;
8522 default:
8523 break;
8524 }
8525 num_connectors++;
8526 }
8527
8528 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8529 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8530 dev_priv->vbt.lvds_ssc_freq);
8531 return dev_priv->vbt.lvds_ssc_freq;
8532 }
8533
8534 return 120000;
8535 }
8536
8537 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8538 {
8539 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8541 int pipe = intel_crtc->pipe;
8542 uint32_t val;
8543
8544 val = 0;
8545
8546 switch (intel_crtc->config->pipe_bpp) {
8547 case 18:
8548 val |= PIPECONF_6BPC;
8549 break;
8550 case 24:
8551 val |= PIPECONF_8BPC;
8552 break;
8553 case 30:
8554 val |= PIPECONF_10BPC;
8555 break;
8556 case 36:
8557 val |= PIPECONF_12BPC;
8558 break;
8559 default:
8560 /* Case prevented by intel_choose_pipe_bpp_dither. */
8561 BUG();
8562 }
8563
8564 if (intel_crtc->config->dither)
8565 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8566
8567 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8568 val |= PIPECONF_INTERLACED_ILK;
8569 else
8570 val |= PIPECONF_PROGRESSIVE;
8571
8572 if (intel_crtc->config->limited_color_range)
8573 val |= PIPECONF_COLOR_RANGE_SELECT;
8574
8575 I915_WRITE(PIPECONF(pipe), val);
8576 POSTING_READ(PIPECONF(pipe));
8577 }
8578
8579 /*
8580 * Set up the pipe CSC unit.
8581 *
8582 * Currently only full range RGB to limited range RGB conversion
8583 * is supported, but eventually this should handle various
8584 * RGB<->YCbCr scenarios as well.
8585 */
8586 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8587 {
8588 struct drm_device *dev = crtc->dev;
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8591 int pipe = intel_crtc->pipe;
8592 uint16_t coeff = 0x7800; /* 1.0 */
8593
8594 /*
8595 * TODO: Check what kind of values actually come out of the pipe
8596 * with these coeff/postoff values and adjust to get the best
8597 * accuracy. Perhaps we even need to take the bpc value into
8598 * consideration.
8599 */
8600
8601 if (intel_crtc->config->limited_color_range)
8602 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8603
8604 /*
8605 * GY/GU and RY/RU should be the other way around according
8606 * to BSpec, but reality doesn't agree. Just set them up in
8607 * a way that results in the correct picture.
8608 */
8609 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8610 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8611
8612 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8613 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8614
8615 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8616 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8617
8618 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8619 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8620 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8621
8622 if (INTEL_INFO(dev)->gen > 6) {
8623 uint16_t postoff = 0;
8624
8625 if (intel_crtc->config->limited_color_range)
8626 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8627
8628 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8629 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8630 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8631
8632 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8633 } else {
8634 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8635
8636 if (intel_crtc->config->limited_color_range)
8637 mode |= CSC_BLACK_SCREEN_OFFSET;
8638
8639 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8640 }
8641 }
8642
8643 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8644 {
8645 struct drm_device *dev = crtc->dev;
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8648 enum pipe pipe = intel_crtc->pipe;
8649 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8650 uint32_t val;
8651
8652 val = 0;
8653
8654 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8655 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8656
8657 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8658 val |= PIPECONF_INTERLACED_ILK;
8659 else
8660 val |= PIPECONF_PROGRESSIVE;
8661
8662 I915_WRITE(PIPECONF(cpu_transcoder), val);
8663 POSTING_READ(PIPECONF(cpu_transcoder));
8664
8665 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8666 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8667
8668 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8669 val = 0;
8670
8671 switch (intel_crtc->config->pipe_bpp) {
8672 case 18:
8673 val |= PIPEMISC_DITHER_6_BPC;
8674 break;
8675 case 24:
8676 val |= PIPEMISC_DITHER_8_BPC;
8677 break;
8678 case 30:
8679 val |= PIPEMISC_DITHER_10_BPC;
8680 break;
8681 case 36:
8682 val |= PIPEMISC_DITHER_12_BPC;
8683 break;
8684 default:
8685 /* Case prevented by pipe_config_set_bpp. */
8686 BUG();
8687 }
8688
8689 if (intel_crtc->config->dither)
8690 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8691
8692 I915_WRITE(PIPEMISC(pipe), val);
8693 }
8694 }
8695
8696 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8697 struct intel_crtc_state *crtc_state,
8698 intel_clock_t *clock,
8699 bool *has_reduced_clock,
8700 intel_clock_t *reduced_clock)
8701 {
8702 struct drm_device *dev = crtc->dev;
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 int refclk;
8705 const intel_limit_t *limit;
8706 bool ret, is_lvds = false;
8707
8708 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8709
8710 refclk = ironlake_get_refclk(crtc_state);
8711
8712 /*
8713 * Returns a set of divisors for the desired target clock with the given
8714 * refclk, or FALSE. The returned values represent the clock equation:
8715 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8716 */
8717 limit = intel_limit(crtc_state, refclk);
8718 ret = dev_priv->display.find_dpll(limit, crtc_state,
8719 crtc_state->port_clock,
8720 refclk, NULL, clock);
8721 if (!ret)
8722 return false;
8723
8724 if (is_lvds && dev_priv->lvds_downclock_avail) {
8725 /*
8726 * Ensure we match the reduced clock's P to the target clock.
8727 * If the clocks don't match, we can't switch the display clock
8728 * by using the FP0/FP1. In such case we will disable the LVDS
8729 * downclock feature.
8730 */
8731 *has_reduced_clock =
8732 dev_priv->display.find_dpll(limit, crtc_state,
8733 dev_priv->lvds_downclock,
8734 refclk, clock,
8735 reduced_clock);
8736 }
8737
8738 return true;
8739 }
8740
8741 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8742 {
8743 /*
8744 * Account for spread spectrum to avoid
8745 * oversubscribing the link. Max center spread
8746 * is 2.5%; use 5% for safety's sake.
8747 */
8748 u32 bps = target_clock * bpp * 21 / 20;
8749 return DIV_ROUND_UP(bps, link_bw * 8);
8750 }
8751
8752 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8753 {
8754 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8755 }
8756
8757 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8758 struct intel_crtc_state *crtc_state,
8759 u32 *fp,
8760 intel_clock_t *reduced_clock, u32 *fp2)
8761 {
8762 struct drm_crtc *crtc = &intel_crtc->base;
8763 struct drm_device *dev = crtc->dev;
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8765 struct drm_atomic_state *state = crtc_state->base.state;
8766 struct drm_connector *connector;
8767 struct drm_connector_state *connector_state;
8768 struct intel_encoder *encoder;
8769 uint32_t dpll;
8770 int factor, num_connectors = 0, i;
8771 bool is_lvds = false, is_sdvo = false;
8772
8773 for_each_connector_in_state(state, connector, connector_state, i) {
8774 if (connector_state->crtc != crtc_state->base.crtc)
8775 continue;
8776
8777 encoder = to_intel_encoder(connector_state->best_encoder);
8778
8779 switch (encoder->type) {
8780 case INTEL_OUTPUT_LVDS:
8781 is_lvds = true;
8782 break;
8783 case INTEL_OUTPUT_SDVO:
8784 case INTEL_OUTPUT_HDMI:
8785 is_sdvo = true;
8786 break;
8787 default:
8788 break;
8789 }
8790
8791 num_connectors++;
8792 }
8793
8794 /* Enable autotuning of the PLL clock (if permissible) */
8795 factor = 21;
8796 if (is_lvds) {
8797 if ((intel_panel_use_ssc(dev_priv) &&
8798 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8799 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8800 factor = 25;
8801 } else if (crtc_state->sdvo_tv_clock)
8802 factor = 20;
8803
8804 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8805 *fp |= FP_CB_TUNE;
8806
8807 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8808 *fp2 |= FP_CB_TUNE;
8809
8810 dpll = 0;
8811
8812 if (is_lvds)
8813 dpll |= DPLLB_MODE_LVDS;
8814 else
8815 dpll |= DPLLB_MODE_DAC_SERIAL;
8816
8817 dpll |= (crtc_state->pixel_multiplier - 1)
8818 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8819
8820 if (is_sdvo)
8821 dpll |= DPLL_SDVO_HIGH_SPEED;
8822 if (crtc_state->has_dp_encoder)
8823 dpll |= DPLL_SDVO_HIGH_SPEED;
8824
8825 /* compute bitmask from p1 value */
8826 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8827 /* also FPA1 */
8828 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8829
8830 switch (crtc_state->dpll.p2) {
8831 case 5:
8832 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8833 break;
8834 case 7:
8835 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8836 break;
8837 case 10:
8838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8839 break;
8840 case 14:
8841 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8842 break;
8843 }
8844
8845 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8846 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8847 else
8848 dpll |= PLL_REF_INPUT_DREFCLK;
8849
8850 return dpll | DPLL_VCO_ENABLE;
8851 }
8852
8853 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8854 struct intel_crtc_state *crtc_state)
8855 {
8856 struct drm_device *dev = crtc->base.dev;
8857 intel_clock_t clock, reduced_clock;
8858 u32 dpll = 0, fp = 0, fp2 = 0;
8859 bool ok, has_reduced_clock = false;
8860 bool is_lvds = false;
8861 struct intel_shared_dpll *pll;
8862
8863 memset(&crtc_state->dpll_hw_state, 0,
8864 sizeof(crtc_state->dpll_hw_state));
8865
8866 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8867
8868 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8869 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8870
8871 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8872 &has_reduced_clock, &reduced_clock);
8873 if (!ok && !crtc_state->clock_set) {
8874 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8875 return -EINVAL;
8876 }
8877 /* Compat-code for transition, will disappear. */
8878 if (!crtc_state->clock_set) {
8879 crtc_state->dpll.n = clock.n;
8880 crtc_state->dpll.m1 = clock.m1;
8881 crtc_state->dpll.m2 = clock.m2;
8882 crtc_state->dpll.p1 = clock.p1;
8883 crtc_state->dpll.p2 = clock.p2;
8884 }
8885
8886 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8887 if (crtc_state->has_pch_encoder) {
8888 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8889 if (has_reduced_clock)
8890 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8891
8892 dpll = ironlake_compute_dpll(crtc, crtc_state,
8893 &fp, &reduced_clock,
8894 has_reduced_clock ? &fp2 : NULL);
8895
8896 crtc_state->dpll_hw_state.dpll = dpll;
8897 crtc_state->dpll_hw_state.fp0 = fp;
8898 if (has_reduced_clock)
8899 crtc_state->dpll_hw_state.fp1 = fp2;
8900 else
8901 crtc_state->dpll_hw_state.fp1 = fp;
8902
8903 pll = intel_get_shared_dpll(crtc, crtc_state);
8904 if (pll == NULL) {
8905 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8906 pipe_name(crtc->pipe));
8907 return -EINVAL;
8908 }
8909 }
8910
8911 if (is_lvds && has_reduced_clock)
8912 crtc->lowfreq_avail = true;
8913 else
8914 crtc->lowfreq_avail = false;
8915
8916 return 0;
8917 }
8918
8919 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8920 struct intel_link_m_n *m_n)
8921 {
8922 struct drm_device *dev = crtc->base.dev;
8923 struct drm_i915_private *dev_priv = dev->dev_private;
8924 enum pipe pipe = crtc->pipe;
8925
8926 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8927 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8928 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8929 & ~TU_SIZE_MASK;
8930 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8931 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8932 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8933 }
8934
8935 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8936 enum transcoder transcoder,
8937 struct intel_link_m_n *m_n,
8938 struct intel_link_m_n *m2_n2)
8939 {
8940 struct drm_device *dev = crtc->base.dev;
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8942 enum pipe pipe = crtc->pipe;
8943
8944 if (INTEL_INFO(dev)->gen >= 5) {
8945 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8946 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8947 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8948 & ~TU_SIZE_MASK;
8949 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8950 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8951 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8952 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8953 * gen < 8) and if DRRS is supported (to make sure the
8954 * registers are not unnecessarily read).
8955 */
8956 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8957 crtc->config->has_drrs) {
8958 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8959 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8960 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8961 & ~TU_SIZE_MASK;
8962 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8963 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8964 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8965 }
8966 } else {
8967 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8968 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8969 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8970 & ~TU_SIZE_MASK;
8971 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8972 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8973 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8974 }
8975 }
8976
8977 void intel_dp_get_m_n(struct intel_crtc *crtc,
8978 struct intel_crtc_state *pipe_config)
8979 {
8980 if (pipe_config->has_pch_encoder)
8981 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8982 else
8983 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8984 &pipe_config->dp_m_n,
8985 &pipe_config->dp_m2_n2);
8986 }
8987
8988 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8989 struct intel_crtc_state *pipe_config)
8990 {
8991 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8992 &pipe_config->fdi_m_n, NULL);
8993 }
8994
8995 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8996 struct intel_crtc_state *pipe_config)
8997 {
8998 struct drm_device *dev = crtc->base.dev;
8999 struct drm_i915_private *dev_priv = dev->dev_private;
9000 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9001 uint32_t ps_ctrl = 0;
9002 int id = -1;
9003 int i;
9004
9005 /* find scaler attached to this pipe */
9006 for (i = 0; i < crtc->num_scalers; i++) {
9007 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9008 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9009 id = i;
9010 pipe_config->pch_pfit.enabled = true;
9011 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9012 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9013 break;
9014 }
9015 }
9016
9017 scaler_state->scaler_id = id;
9018 if (id >= 0) {
9019 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9020 } else {
9021 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9022 }
9023 }
9024
9025 static void
9026 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9027 struct intel_initial_plane_config *plane_config)
9028 {
9029 struct drm_device *dev = crtc->base.dev;
9030 struct drm_i915_private *dev_priv = dev->dev_private;
9031 u32 val, base, offset, stride_mult, tiling;
9032 int pipe = crtc->pipe;
9033 int fourcc, pixel_format;
9034 unsigned int aligned_height;
9035 struct drm_framebuffer *fb;
9036 struct intel_framebuffer *intel_fb;
9037
9038 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9039 if (!intel_fb) {
9040 DRM_DEBUG_KMS("failed to alloc fb\n");
9041 return;
9042 }
9043
9044 fb = &intel_fb->base;
9045
9046 val = I915_READ(PLANE_CTL(pipe, 0));
9047 if (!(val & PLANE_CTL_ENABLE))
9048 goto error;
9049
9050 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9051 fourcc = skl_format_to_fourcc(pixel_format,
9052 val & PLANE_CTL_ORDER_RGBX,
9053 val & PLANE_CTL_ALPHA_MASK);
9054 fb->pixel_format = fourcc;
9055 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9056
9057 tiling = val & PLANE_CTL_TILED_MASK;
9058 switch (tiling) {
9059 case PLANE_CTL_TILED_LINEAR:
9060 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9061 break;
9062 case PLANE_CTL_TILED_X:
9063 plane_config->tiling = I915_TILING_X;
9064 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9065 break;
9066 case PLANE_CTL_TILED_Y:
9067 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9068 break;
9069 case PLANE_CTL_TILED_YF:
9070 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9071 break;
9072 default:
9073 MISSING_CASE(tiling);
9074 goto error;
9075 }
9076
9077 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9078 plane_config->base = base;
9079
9080 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9081
9082 val = I915_READ(PLANE_SIZE(pipe, 0));
9083 fb->height = ((val >> 16) & 0xfff) + 1;
9084 fb->width = ((val >> 0) & 0x1fff) + 1;
9085
9086 val = I915_READ(PLANE_STRIDE(pipe, 0));
9087 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9088 fb->pixel_format);
9089 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9090
9091 aligned_height = intel_fb_align_height(dev, fb->height,
9092 fb->pixel_format,
9093 fb->modifier[0]);
9094
9095 plane_config->size = fb->pitches[0] * aligned_height;
9096
9097 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9098 pipe_name(pipe), fb->width, fb->height,
9099 fb->bits_per_pixel, base, fb->pitches[0],
9100 plane_config->size);
9101
9102 plane_config->fb = intel_fb;
9103 return;
9104
9105 error:
9106 kfree(fb);
9107 }
9108
9109 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9110 struct intel_crtc_state *pipe_config)
9111 {
9112 struct drm_device *dev = crtc->base.dev;
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 uint32_t tmp;
9115
9116 tmp = I915_READ(PF_CTL(crtc->pipe));
9117
9118 if (tmp & PF_ENABLE) {
9119 pipe_config->pch_pfit.enabled = true;
9120 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9121 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9122
9123 /* We currently do not free assignements of panel fitters on
9124 * ivb/hsw (since we don't use the higher upscaling modes which
9125 * differentiates them) so just WARN about this case for now. */
9126 if (IS_GEN7(dev)) {
9127 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9128 PF_PIPE_SEL_IVB(crtc->pipe));
9129 }
9130 }
9131 }
9132
9133 static void
9134 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9135 struct intel_initial_plane_config *plane_config)
9136 {
9137 struct drm_device *dev = crtc->base.dev;
9138 struct drm_i915_private *dev_priv = dev->dev_private;
9139 u32 val, base, offset;
9140 int pipe = crtc->pipe;
9141 int fourcc, pixel_format;
9142 unsigned int aligned_height;
9143 struct drm_framebuffer *fb;
9144 struct intel_framebuffer *intel_fb;
9145
9146 val = I915_READ(DSPCNTR(pipe));
9147 if (!(val & DISPLAY_PLANE_ENABLE))
9148 return;
9149
9150 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9151 if (!intel_fb) {
9152 DRM_DEBUG_KMS("failed to alloc fb\n");
9153 return;
9154 }
9155
9156 fb = &intel_fb->base;
9157
9158 if (INTEL_INFO(dev)->gen >= 4) {
9159 if (val & DISPPLANE_TILED) {
9160 plane_config->tiling = I915_TILING_X;
9161 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9162 }
9163 }
9164
9165 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9166 fourcc = i9xx_format_to_fourcc(pixel_format);
9167 fb->pixel_format = fourcc;
9168 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9169
9170 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9171 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9172 offset = I915_READ(DSPOFFSET(pipe));
9173 } else {
9174 if (plane_config->tiling)
9175 offset = I915_READ(DSPTILEOFF(pipe));
9176 else
9177 offset = I915_READ(DSPLINOFF(pipe));
9178 }
9179 plane_config->base = base;
9180
9181 val = I915_READ(PIPESRC(pipe));
9182 fb->width = ((val >> 16) & 0xfff) + 1;
9183 fb->height = ((val >> 0) & 0xfff) + 1;
9184
9185 val = I915_READ(DSPSTRIDE(pipe));
9186 fb->pitches[0] = val & 0xffffffc0;
9187
9188 aligned_height = intel_fb_align_height(dev, fb->height,
9189 fb->pixel_format,
9190 fb->modifier[0]);
9191
9192 plane_config->size = fb->pitches[0] * aligned_height;
9193
9194 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9195 pipe_name(pipe), fb->width, fb->height,
9196 fb->bits_per_pixel, base, fb->pitches[0],
9197 plane_config->size);
9198
9199 plane_config->fb = intel_fb;
9200 }
9201
9202 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9203 struct intel_crtc_state *pipe_config)
9204 {
9205 struct drm_device *dev = crtc->base.dev;
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 uint32_t tmp;
9208
9209 if (!intel_display_power_is_enabled(dev_priv,
9210 POWER_DOMAIN_PIPE(crtc->pipe)))
9211 return false;
9212
9213 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9214 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9215
9216 tmp = I915_READ(PIPECONF(crtc->pipe));
9217 if (!(tmp & PIPECONF_ENABLE))
9218 return false;
9219
9220 switch (tmp & PIPECONF_BPC_MASK) {
9221 case PIPECONF_6BPC:
9222 pipe_config->pipe_bpp = 18;
9223 break;
9224 case PIPECONF_8BPC:
9225 pipe_config->pipe_bpp = 24;
9226 break;
9227 case PIPECONF_10BPC:
9228 pipe_config->pipe_bpp = 30;
9229 break;
9230 case PIPECONF_12BPC:
9231 pipe_config->pipe_bpp = 36;
9232 break;
9233 default:
9234 break;
9235 }
9236
9237 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9238 pipe_config->limited_color_range = true;
9239
9240 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9241 struct intel_shared_dpll *pll;
9242
9243 pipe_config->has_pch_encoder = true;
9244
9245 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9246 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9247 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9248
9249 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9250
9251 if (HAS_PCH_IBX(dev_priv->dev)) {
9252 pipe_config->shared_dpll =
9253 (enum intel_dpll_id) crtc->pipe;
9254 } else {
9255 tmp = I915_READ(PCH_DPLL_SEL);
9256 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9257 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9258 else
9259 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9260 }
9261
9262 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9263
9264 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9265 &pipe_config->dpll_hw_state));
9266
9267 tmp = pipe_config->dpll_hw_state.dpll;
9268 pipe_config->pixel_multiplier =
9269 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9270 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9271
9272 ironlake_pch_clock_get(crtc, pipe_config);
9273 } else {
9274 pipe_config->pixel_multiplier = 1;
9275 }
9276
9277 intel_get_pipe_timings(crtc, pipe_config);
9278
9279 ironlake_get_pfit_config(crtc, pipe_config);
9280
9281 return true;
9282 }
9283
9284 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9285 {
9286 struct drm_device *dev = dev_priv->dev;
9287 struct intel_crtc *crtc;
9288
9289 for_each_intel_crtc(dev, crtc)
9290 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9291 pipe_name(crtc->pipe));
9292
9293 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9294 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9295 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9296 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9297 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9298 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9299 "CPU PWM1 enabled\n");
9300 if (IS_HASWELL(dev))
9301 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9302 "CPU PWM2 enabled\n");
9303 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9304 "PCH PWM1 enabled\n");
9305 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9306 "Utility pin enabled\n");
9307 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9308
9309 /*
9310 * In theory we can still leave IRQs enabled, as long as only the HPD
9311 * interrupts remain enabled. We used to check for that, but since it's
9312 * gen-specific and since we only disable LCPLL after we fully disable
9313 * the interrupts, the check below should be enough.
9314 */
9315 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9316 }
9317
9318 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9319 {
9320 struct drm_device *dev = dev_priv->dev;
9321
9322 if (IS_HASWELL(dev))
9323 return I915_READ(D_COMP_HSW);
9324 else
9325 return I915_READ(D_COMP_BDW);
9326 }
9327
9328 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9329 {
9330 struct drm_device *dev = dev_priv->dev;
9331
9332 if (IS_HASWELL(dev)) {
9333 mutex_lock(&dev_priv->rps.hw_lock);
9334 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9335 val))
9336 DRM_ERROR("Failed to write to D_COMP\n");
9337 mutex_unlock(&dev_priv->rps.hw_lock);
9338 } else {
9339 I915_WRITE(D_COMP_BDW, val);
9340 POSTING_READ(D_COMP_BDW);
9341 }
9342 }
9343
9344 /*
9345 * This function implements pieces of two sequences from BSpec:
9346 * - Sequence for display software to disable LCPLL
9347 * - Sequence for display software to allow package C8+
9348 * The steps implemented here are just the steps that actually touch the LCPLL
9349 * register. Callers should take care of disabling all the display engine
9350 * functions, doing the mode unset, fixing interrupts, etc.
9351 */
9352 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9353 bool switch_to_fclk, bool allow_power_down)
9354 {
9355 uint32_t val;
9356
9357 assert_can_disable_lcpll(dev_priv);
9358
9359 val = I915_READ(LCPLL_CTL);
9360
9361 if (switch_to_fclk) {
9362 val |= LCPLL_CD_SOURCE_FCLK;
9363 I915_WRITE(LCPLL_CTL, val);
9364
9365 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9366 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9367 DRM_ERROR("Switching to FCLK failed\n");
9368
9369 val = I915_READ(LCPLL_CTL);
9370 }
9371
9372 val |= LCPLL_PLL_DISABLE;
9373 I915_WRITE(LCPLL_CTL, val);
9374 POSTING_READ(LCPLL_CTL);
9375
9376 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9377 DRM_ERROR("LCPLL still locked\n");
9378
9379 val = hsw_read_dcomp(dev_priv);
9380 val |= D_COMP_COMP_DISABLE;
9381 hsw_write_dcomp(dev_priv, val);
9382 ndelay(100);
9383
9384 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9385 1))
9386 DRM_ERROR("D_COMP RCOMP still in progress\n");
9387
9388 if (allow_power_down) {
9389 val = I915_READ(LCPLL_CTL);
9390 val |= LCPLL_POWER_DOWN_ALLOW;
9391 I915_WRITE(LCPLL_CTL, val);
9392 POSTING_READ(LCPLL_CTL);
9393 }
9394 }
9395
9396 /*
9397 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9398 * source.
9399 */
9400 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9401 {
9402 uint32_t val;
9403
9404 val = I915_READ(LCPLL_CTL);
9405
9406 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9407 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9408 return;
9409
9410 /*
9411 * Make sure we're not on PC8 state before disabling PC8, otherwise
9412 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9413 */
9414 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9415
9416 if (val & LCPLL_POWER_DOWN_ALLOW) {
9417 val &= ~LCPLL_POWER_DOWN_ALLOW;
9418 I915_WRITE(LCPLL_CTL, val);
9419 POSTING_READ(LCPLL_CTL);
9420 }
9421
9422 val = hsw_read_dcomp(dev_priv);
9423 val |= D_COMP_COMP_FORCE;
9424 val &= ~D_COMP_COMP_DISABLE;
9425 hsw_write_dcomp(dev_priv, val);
9426
9427 val = I915_READ(LCPLL_CTL);
9428 val &= ~LCPLL_PLL_DISABLE;
9429 I915_WRITE(LCPLL_CTL, val);
9430
9431 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9432 DRM_ERROR("LCPLL not locked yet\n");
9433
9434 if (val & LCPLL_CD_SOURCE_FCLK) {
9435 val = I915_READ(LCPLL_CTL);
9436 val &= ~LCPLL_CD_SOURCE_FCLK;
9437 I915_WRITE(LCPLL_CTL, val);
9438
9439 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9440 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9441 DRM_ERROR("Switching back to LCPLL failed\n");
9442 }
9443
9444 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9445 intel_update_cdclk(dev_priv->dev);
9446 }
9447
9448 /*
9449 * Package states C8 and deeper are really deep PC states that can only be
9450 * reached when all the devices on the system allow it, so even if the graphics
9451 * device allows PC8+, it doesn't mean the system will actually get to these
9452 * states. Our driver only allows PC8+ when going into runtime PM.
9453 *
9454 * The requirements for PC8+ are that all the outputs are disabled, the power
9455 * well is disabled and most interrupts are disabled, and these are also
9456 * requirements for runtime PM. When these conditions are met, we manually do
9457 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9458 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9459 * hang the machine.
9460 *
9461 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9462 * the state of some registers, so when we come back from PC8+ we need to
9463 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9464 * need to take care of the registers kept by RC6. Notice that this happens even
9465 * if we don't put the device in PCI D3 state (which is what currently happens
9466 * because of the runtime PM support).
9467 *
9468 * For more, read "Display Sequences for Package C8" on the hardware
9469 * documentation.
9470 */
9471 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9472 {
9473 struct drm_device *dev = dev_priv->dev;
9474 uint32_t val;
9475
9476 DRM_DEBUG_KMS("Enabling package C8+\n");
9477
9478 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9479 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9480 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9481 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9482 }
9483
9484 lpt_disable_clkout_dp(dev);
9485 hsw_disable_lcpll(dev_priv, true, true);
9486 }
9487
9488 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9489 {
9490 struct drm_device *dev = dev_priv->dev;
9491 uint32_t val;
9492
9493 DRM_DEBUG_KMS("Disabling package C8+\n");
9494
9495 hsw_restore_lcpll(dev_priv);
9496 lpt_init_pch_refclk(dev);
9497
9498 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9499 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9500 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9501 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9502 }
9503
9504 intel_prepare_ddi(dev);
9505 }
9506
9507 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9508 {
9509 struct drm_device *dev = old_state->dev;
9510 struct drm_i915_private *dev_priv = dev->dev_private;
9511 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9512 int req_cdclk;
9513
9514 /* see the comment in valleyview_modeset_global_resources */
9515 if (WARN_ON(max_pixclk < 0))
9516 return;
9517
9518 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9519
9520 if (req_cdclk != dev_priv->cdclk_freq)
9521 broxton_set_cdclk(dev, req_cdclk);
9522 }
9523
9524 /* compute the max rate for new configuration */
9525 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9526 {
9527 struct drm_device *dev = dev_priv->dev;
9528 struct intel_crtc *intel_crtc;
9529 struct drm_crtc *crtc;
9530 int max_pixel_rate = 0;
9531 int pixel_rate;
9532
9533 for_each_crtc(dev, crtc) {
9534 if (!crtc->state->enable)
9535 continue;
9536
9537 intel_crtc = to_intel_crtc(crtc);
9538 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9539
9540 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9541 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9542 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9543
9544 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9545 }
9546
9547 return max_pixel_rate;
9548 }
9549
9550 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9551 {
9552 struct drm_i915_private *dev_priv = dev->dev_private;
9553 uint32_t val, data;
9554 int ret;
9555
9556 if (WARN((I915_READ(LCPLL_CTL) &
9557 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9558 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9559 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9560 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9561 "trying to change cdclk frequency with cdclk not enabled\n"))
9562 return;
9563
9564 mutex_lock(&dev_priv->rps.hw_lock);
9565 ret = sandybridge_pcode_write(dev_priv,
9566 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9567 mutex_unlock(&dev_priv->rps.hw_lock);
9568 if (ret) {
9569 DRM_ERROR("failed to inform pcode about cdclk change\n");
9570 return;
9571 }
9572
9573 val = I915_READ(LCPLL_CTL);
9574 val |= LCPLL_CD_SOURCE_FCLK;
9575 I915_WRITE(LCPLL_CTL, val);
9576
9577 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9578 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9579 DRM_ERROR("Switching to FCLK failed\n");
9580
9581 val = I915_READ(LCPLL_CTL);
9582 val &= ~LCPLL_CLK_FREQ_MASK;
9583
9584 switch (cdclk) {
9585 case 450000:
9586 val |= LCPLL_CLK_FREQ_450;
9587 data = 0;
9588 break;
9589 case 540000:
9590 val |= LCPLL_CLK_FREQ_54O_BDW;
9591 data = 1;
9592 break;
9593 case 337500:
9594 val |= LCPLL_CLK_FREQ_337_5_BDW;
9595 data = 2;
9596 break;
9597 case 675000:
9598 val |= LCPLL_CLK_FREQ_675_BDW;
9599 data = 3;
9600 break;
9601 default:
9602 WARN(1, "invalid cdclk frequency\n");
9603 return;
9604 }
9605
9606 I915_WRITE(LCPLL_CTL, val);
9607
9608 val = I915_READ(LCPLL_CTL);
9609 val &= ~LCPLL_CD_SOURCE_FCLK;
9610 I915_WRITE(LCPLL_CTL, val);
9611
9612 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9613 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9614 DRM_ERROR("Switching back to LCPLL failed\n");
9615
9616 mutex_lock(&dev_priv->rps.hw_lock);
9617 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9618 mutex_unlock(&dev_priv->rps.hw_lock);
9619
9620 intel_update_cdclk(dev);
9621
9622 WARN(cdclk != dev_priv->cdclk_freq,
9623 "cdclk requested %d kHz but got %d kHz\n",
9624 cdclk, dev_priv->cdclk_freq);
9625 }
9626
9627 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9628 int max_pixel_rate)
9629 {
9630 int cdclk;
9631
9632 /*
9633 * FIXME should also account for plane ratio
9634 * once 64bpp pixel formats are supported.
9635 */
9636 if (max_pixel_rate > 540000)
9637 cdclk = 675000;
9638 else if (max_pixel_rate > 450000)
9639 cdclk = 540000;
9640 else if (max_pixel_rate > 337500)
9641 cdclk = 450000;
9642 else
9643 cdclk = 337500;
9644
9645 /*
9646 * FIXME move the cdclk caclulation to
9647 * compute_config() so we can fail gracegully.
9648 */
9649 if (cdclk > dev_priv->max_cdclk_freq) {
9650 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9651 cdclk, dev_priv->max_cdclk_freq);
9652 cdclk = dev_priv->max_cdclk_freq;
9653 }
9654
9655 return cdclk;
9656 }
9657
9658 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9659 {
9660 struct drm_i915_private *dev_priv = to_i915(state->dev);
9661 struct drm_crtc *crtc;
9662 struct drm_crtc_state *crtc_state;
9663 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9664 int cdclk, i;
9665
9666 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9667
9668 if (cdclk == dev_priv->cdclk_freq)
9669 return 0;
9670
9671 /* add all active pipes to the state */
9672 for_each_crtc(state->dev, crtc) {
9673 if (!crtc->state->enable)
9674 continue;
9675
9676 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9677 if (IS_ERR(crtc_state))
9678 return PTR_ERR(crtc_state);
9679 }
9680
9681 /* disable/enable all currently active pipes while we change cdclk */
9682 for_each_crtc_in_state(state, crtc, crtc_state, i)
9683 if (crtc_state->enable)
9684 crtc_state->mode_changed = true;
9685
9686 return 0;
9687 }
9688
9689 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9690 {
9691 struct drm_device *dev = state->dev;
9692 struct drm_i915_private *dev_priv = dev->dev_private;
9693 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9694 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9695
9696 if (req_cdclk != dev_priv->cdclk_freq)
9697 broadwell_set_cdclk(dev, req_cdclk);
9698 }
9699
9700 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9701 struct intel_crtc_state *crtc_state)
9702 {
9703 if (!intel_ddi_pll_select(crtc, crtc_state))
9704 return -EINVAL;
9705
9706 crtc->lowfreq_avail = false;
9707
9708 return 0;
9709 }
9710
9711 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9712 enum port port,
9713 struct intel_crtc_state *pipe_config)
9714 {
9715 switch (port) {
9716 case PORT_A:
9717 pipe_config->ddi_pll_sel = SKL_DPLL0;
9718 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9719 break;
9720 case PORT_B:
9721 pipe_config->ddi_pll_sel = SKL_DPLL1;
9722 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9723 break;
9724 case PORT_C:
9725 pipe_config->ddi_pll_sel = SKL_DPLL2;
9726 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9727 break;
9728 default:
9729 DRM_ERROR("Incorrect port type\n");
9730 }
9731 }
9732
9733 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9734 enum port port,
9735 struct intel_crtc_state *pipe_config)
9736 {
9737 u32 temp, dpll_ctl1;
9738
9739 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9740 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9741
9742 switch (pipe_config->ddi_pll_sel) {
9743 case SKL_DPLL0:
9744 /*
9745 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9746 * of the shared DPLL framework and thus needs to be read out
9747 * separately
9748 */
9749 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9750 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9751 break;
9752 case SKL_DPLL1:
9753 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9754 break;
9755 case SKL_DPLL2:
9756 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9757 break;
9758 case SKL_DPLL3:
9759 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9760 break;
9761 }
9762 }
9763
9764 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9765 enum port port,
9766 struct intel_crtc_state *pipe_config)
9767 {
9768 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9769
9770 switch (pipe_config->ddi_pll_sel) {
9771 case PORT_CLK_SEL_WRPLL1:
9772 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9773 break;
9774 case PORT_CLK_SEL_WRPLL2:
9775 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9776 break;
9777 }
9778 }
9779
9780 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9781 struct intel_crtc_state *pipe_config)
9782 {
9783 struct drm_device *dev = crtc->base.dev;
9784 struct drm_i915_private *dev_priv = dev->dev_private;
9785 struct intel_shared_dpll *pll;
9786 enum port port;
9787 uint32_t tmp;
9788
9789 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9790
9791 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9792
9793 if (IS_SKYLAKE(dev))
9794 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9795 else if (IS_BROXTON(dev))
9796 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9797 else
9798 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9799
9800 if (pipe_config->shared_dpll >= 0) {
9801 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9802
9803 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9804 &pipe_config->dpll_hw_state));
9805 }
9806
9807 /*
9808 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9809 * DDI E. So just check whether this pipe is wired to DDI E and whether
9810 * the PCH transcoder is on.
9811 */
9812 if (INTEL_INFO(dev)->gen < 9 &&
9813 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9814 pipe_config->has_pch_encoder = true;
9815
9816 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9817 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9818 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9819
9820 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9821 }
9822 }
9823
9824 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9825 struct intel_crtc_state *pipe_config)
9826 {
9827 struct drm_device *dev = crtc->base.dev;
9828 struct drm_i915_private *dev_priv = dev->dev_private;
9829 enum intel_display_power_domain pfit_domain;
9830 uint32_t tmp;
9831
9832 if (!intel_display_power_is_enabled(dev_priv,
9833 POWER_DOMAIN_PIPE(crtc->pipe)))
9834 return false;
9835
9836 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9837 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9838
9839 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9840 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9841 enum pipe trans_edp_pipe;
9842 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9843 default:
9844 WARN(1, "unknown pipe linked to edp transcoder\n");
9845 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9846 case TRANS_DDI_EDP_INPUT_A_ON:
9847 trans_edp_pipe = PIPE_A;
9848 break;
9849 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9850 trans_edp_pipe = PIPE_B;
9851 break;
9852 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9853 trans_edp_pipe = PIPE_C;
9854 break;
9855 }
9856
9857 if (trans_edp_pipe == crtc->pipe)
9858 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9859 }
9860
9861 if (!intel_display_power_is_enabled(dev_priv,
9862 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9863 return false;
9864
9865 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9866 if (!(tmp & PIPECONF_ENABLE))
9867 return false;
9868
9869 haswell_get_ddi_port_state(crtc, pipe_config);
9870
9871 intel_get_pipe_timings(crtc, pipe_config);
9872
9873 if (INTEL_INFO(dev)->gen >= 9) {
9874 skl_init_scalers(dev, crtc, pipe_config);
9875 }
9876
9877 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9878
9879 if (INTEL_INFO(dev)->gen >= 9) {
9880 pipe_config->scaler_state.scaler_id = -1;
9881 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9882 }
9883
9884 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9885 if (INTEL_INFO(dev)->gen == 9)
9886 skylake_get_pfit_config(crtc, pipe_config);
9887 else if (INTEL_INFO(dev)->gen < 9)
9888 ironlake_get_pfit_config(crtc, pipe_config);
9889 else
9890 MISSING_CASE(INTEL_INFO(dev)->gen);
9891 }
9892
9893 if (IS_HASWELL(dev))
9894 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9895 (I915_READ(IPS_CTL) & IPS_ENABLE);
9896
9897 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9898 pipe_config->pixel_multiplier =
9899 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9900 } else {
9901 pipe_config->pixel_multiplier = 1;
9902 }
9903
9904 return true;
9905 }
9906
9907 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9908 {
9909 struct drm_device *dev = crtc->dev;
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9912 uint32_t cntl = 0, size = 0;
9913
9914 if (base) {
9915 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9916 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9917 unsigned int stride = roundup_pow_of_two(width) * 4;
9918
9919 switch (stride) {
9920 default:
9921 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9922 width, stride);
9923 stride = 256;
9924 /* fallthrough */
9925 case 256:
9926 case 512:
9927 case 1024:
9928 case 2048:
9929 break;
9930 }
9931
9932 cntl |= CURSOR_ENABLE |
9933 CURSOR_GAMMA_ENABLE |
9934 CURSOR_FORMAT_ARGB |
9935 CURSOR_STRIDE(stride);
9936
9937 size = (height << 12) | width;
9938 }
9939
9940 if (intel_crtc->cursor_cntl != 0 &&
9941 (intel_crtc->cursor_base != base ||
9942 intel_crtc->cursor_size != size ||
9943 intel_crtc->cursor_cntl != cntl)) {
9944 /* On these chipsets we can only modify the base/size/stride
9945 * whilst the cursor is disabled.
9946 */
9947 I915_WRITE(_CURACNTR, 0);
9948 POSTING_READ(_CURACNTR);
9949 intel_crtc->cursor_cntl = 0;
9950 }
9951
9952 if (intel_crtc->cursor_base != base) {
9953 I915_WRITE(_CURABASE, base);
9954 intel_crtc->cursor_base = base;
9955 }
9956
9957 if (intel_crtc->cursor_size != size) {
9958 I915_WRITE(CURSIZE, size);
9959 intel_crtc->cursor_size = size;
9960 }
9961
9962 if (intel_crtc->cursor_cntl != cntl) {
9963 I915_WRITE(_CURACNTR, cntl);
9964 POSTING_READ(_CURACNTR);
9965 intel_crtc->cursor_cntl = cntl;
9966 }
9967 }
9968
9969 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9970 {
9971 struct drm_device *dev = crtc->dev;
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9974 int pipe = intel_crtc->pipe;
9975 uint32_t cntl;
9976
9977 cntl = 0;
9978 if (base) {
9979 cntl = MCURSOR_GAMMA_ENABLE;
9980 switch (intel_crtc->base.cursor->state->crtc_w) {
9981 case 64:
9982 cntl |= CURSOR_MODE_64_ARGB_AX;
9983 break;
9984 case 128:
9985 cntl |= CURSOR_MODE_128_ARGB_AX;
9986 break;
9987 case 256:
9988 cntl |= CURSOR_MODE_256_ARGB_AX;
9989 break;
9990 default:
9991 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9992 return;
9993 }
9994 cntl |= pipe << 28; /* Connect to correct pipe */
9995
9996 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9997 cntl |= CURSOR_PIPE_CSC_ENABLE;
9998 }
9999
10000 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10001 cntl |= CURSOR_ROTATE_180;
10002
10003 if (intel_crtc->cursor_cntl != cntl) {
10004 I915_WRITE(CURCNTR(pipe), cntl);
10005 POSTING_READ(CURCNTR(pipe));
10006 intel_crtc->cursor_cntl = cntl;
10007 }
10008
10009 /* and commit changes on next vblank */
10010 I915_WRITE(CURBASE(pipe), base);
10011 POSTING_READ(CURBASE(pipe));
10012
10013 intel_crtc->cursor_base = base;
10014 }
10015
10016 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10017 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10018 bool on)
10019 {
10020 struct drm_device *dev = crtc->dev;
10021 struct drm_i915_private *dev_priv = dev->dev_private;
10022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10023 int pipe = intel_crtc->pipe;
10024 int x = crtc->cursor_x;
10025 int y = crtc->cursor_y;
10026 u32 base = 0, pos = 0;
10027
10028 if (on)
10029 base = intel_crtc->cursor_addr;
10030
10031 if (x >= intel_crtc->config->pipe_src_w)
10032 base = 0;
10033
10034 if (y >= intel_crtc->config->pipe_src_h)
10035 base = 0;
10036
10037 if (x < 0) {
10038 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10039 base = 0;
10040
10041 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10042 x = -x;
10043 }
10044 pos |= x << CURSOR_X_SHIFT;
10045
10046 if (y < 0) {
10047 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10048 base = 0;
10049
10050 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10051 y = -y;
10052 }
10053 pos |= y << CURSOR_Y_SHIFT;
10054
10055 if (base == 0 && intel_crtc->cursor_base == 0)
10056 return;
10057
10058 I915_WRITE(CURPOS(pipe), pos);
10059
10060 /* ILK+ do this automagically */
10061 if (HAS_GMCH_DISPLAY(dev) &&
10062 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10063 base += (intel_crtc->base.cursor->state->crtc_h *
10064 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10065 }
10066
10067 if (IS_845G(dev) || IS_I865G(dev))
10068 i845_update_cursor(crtc, base);
10069 else
10070 i9xx_update_cursor(crtc, base);
10071 }
10072
10073 static bool cursor_size_ok(struct drm_device *dev,
10074 uint32_t width, uint32_t height)
10075 {
10076 if (width == 0 || height == 0)
10077 return false;
10078
10079 /*
10080 * 845g/865g are special in that they are only limited by
10081 * the width of their cursors, the height is arbitrary up to
10082 * the precision of the register. Everything else requires
10083 * square cursors, limited to a few power-of-two sizes.
10084 */
10085 if (IS_845G(dev) || IS_I865G(dev)) {
10086 if ((width & 63) != 0)
10087 return false;
10088
10089 if (width > (IS_845G(dev) ? 64 : 512))
10090 return false;
10091
10092 if (height > 1023)
10093 return false;
10094 } else {
10095 switch (width | height) {
10096 case 256:
10097 case 128:
10098 if (IS_GEN2(dev))
10099 return false;
10100 case 64:
10101 break;
10102 default:
10103 return false;
10104 }
10105 }
10106
10107 return true;
10108 }
10109
10110 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10111 u16 *blue, uint32_t start, uint32_t size)
10112 {
10113 int end = (start + size > 256) ? 256 : start + size, i;
10114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10115
10116 for (i = start; i < end; i++) {
10117 intel_crtc->lut_r[i] = red[i] >> 8;
10118 intel_crtc->lut_g[i] = green[i] >> 8;
10119 intel_crtc->lut_b[i] = blue[i] >> 8;
10120 }
10121
10122 intel_crtc_load_lut(crtc);
10123 }
10124
10125 /* VESA 640x480x72Hz mode to set on the pipe */
10126 static struct drm_display_mode load_detect_mode = {
10127 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10128 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10129 };
10130
10131 struct drm_framebuffer *
10132 __intel_framebuffer_create(struct drm_device *dev,
10133 struct drm_mode_fb_cmd2 *mode_cmd,
10134 struct drm_i915_gem_object *obj)
10135 {
10136 struct intel_framebuffer *intel_fb;
10137 int ret;
10138
10139 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10140 if (!intel_fb) {
10141 drm_gem_object_unreference(&obj->base);
10142 return ERR_PTR(-ENOMEM);
10143 }
10144
10145 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10146 if (ret)
10147 goto err;
10148
10149 return &intel_fb->base;
10150 err:
10151 drm_gem_object_unreference(&obj->base);
10152 kfree(intel_fb);
10153
10154 return ERR_PTR(ret);
10155 }
10156
10157 static struct drm_framebuffer *
10158 intel_framebuffer_create(struct drm_device *dev,
10159 struct drm_mode_fb_cmd2 *mode_cmd,
10160 struct drm_i915_gem_object *obj)
10161 {
10162 struct drm_framebuffer *fb;
10163 int ret;
10164
10165 ret = i915_mutex_lock_interruptible(dev);
10166 if (ret)
10167 return ERR_PTR(ret);
10168 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10169 mutex_unlock(&dev->struct_mutex);
10170
10171 return fb;
10172 }
10173
10174 static u32
10175 intel_framebuffer_pitch_for_width(int width, int bpp)
10176 {
10177 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10178 return ALIGN(pitch, 64);
10179 }
10180
10181 static u32
10182 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10183 {
10184 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10185 return PAGE_ALIGN(pitch * mode->vdisplay);
10186 }
10187
10188 static struct drm_framebuffer *
10189 intel_framebuffer_create_for_mode(struct drm_device *dev,
10190 struct drm_display_mode *mode,
10191 int depth, int bpp)
10192 {
10193 struct drm_i915_gem_object *obj;
10194 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10195
10196 obj = i915_gem_alloc_object(dev,
10197 intel_framebuffer_size_for_mode(mode, bpp));
10198 if (obj == NULL)
10199 return ERR_PTR(-ENOMEM);
10200
10201 mode_cmd.width = mode->hdisplay;
10202 mode_cmd.height = mode->vdisplay;
10203 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10204 bpp);
10205 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10206
10207 return intel_framebuffer_create(dev, &mode_cmd, obj);
10208 }
10209
10210 static struct drm_framebuffer *
10211 mode_fits_in_fbdev(struct drm_device *dev,
10212 struct drm_display_mode *mode)
10213 {
10214 #ifdef CONFIG_DRM_I915_FBDEV
10215 struct drm_i915_private *dev_priv = dev->dev_private;
10216 struct drm_i915_gem_object *obj;
10217 struct drm_framebuffer *fb;
10218
10219 if (!dev_priv->fbdev)
10220 return NULL;
10221
10222 if (!dev_priv->fbdev->fb)
10223 return NULL;
10224
10225 obj = dev_priv->fbdev->fb->obj;
10226 BUG_ON(!obj);
10227
10228 fb = &dev_priv->fbdev->fb->base;
10229 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10230 fb->bits_per_pixel))
10231 return NULL;
10232
10233 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10234 return NULL;
10235
10236 return fb;
10237 #else
10238 return NULL;
10239 #endif
10240 }
10241
10242 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10243 struct drm_crtc *crtc,
10244 struct drm_display_mode *mode,
10245 struct drm_framebuffer *fb,
10246 int x, int y)
10247 {
10248 struct drm_plane_state *plane_state;
10249 int hdisplay, vdisplay;
10250 int ret;
10251
10252 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10253 if (IS_ERR(plane_state))
10254 return PTR_ERR(plane_state);
10255
10256 if (mode)
10257 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10258 else
10259 hdisplay = vdisplay = 0;
10260
10261 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10262 if (ret)
10263 return ret;
10264 drm_atomic_set_fb_for_plane(plane_state, fb);
10265 plane_state->crtc_x = 0;
10266 plane_state->crtc_y = 0;
10267 plane_state->crtc_w = hdisplay;
10268 plane_state->crtc_h = vdisplay;
10269 plane_state->src_x = x << 16;
10270 plane_state->src_y = y << 16;
10271 plane_state->src_w = hdisplay << 16;
10272 plane_state->src_h = vdisplay << 16;
10273
10274 return 0;
10275 }
10276
10277 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10278 struct drm_display_mode *mode,
10279 struct intel_load_detect_pipe *old,
10280 struct drm_modeset_acquire_ctx *ctx)
10281 {
10282 struct intel_crtc *intel_crtc;
10283 struct intel_encoder *intel_encoder =
10284 intel_attached_encoder(connector);
10285 struct drm_crtc *possible_crtc;
10286 struct drm_encoder *encoder = &intel_encoder->base;
10287 struct drm_crtc *crtc = NULL;
10288 struct drm_device *dev = encoder->dev;
10289 struct drm_framebuffer *fb;
10290 struct drm_mode_config *config = &dev->mode_config;
10291 struct drm_atomic_state *state = NULL;
10292 struct drm_connector_state *connector_state;
10293 struct intel_crtc_state *crtc_state;
10294 int ret, i = -1;
10295
10296 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10297 connector->base.id, connector->name,
10298 encoder->base.id, encoder->name);
10299
10300 retry:
10301 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10302 if (ret)
10303 goto fail;
10304
10305 /*
10306 * Algorithm gets a little messy:
10307 *
10308 * - if the connector already has an assigned crtc, use it (but make
10309 * sure it's on first)
10310 *
10311 * - try to find the first unused crtc that can drive this connector,
10312 * and use that if we find one
10313 */
10314
10315 /* See if we already have a CRTC for this connector */
10316 if (encoder->crtc) {
10317 crtc = encoder->crtc;
10318
10319 ret = drm_modeset_lock(&crtc->mutex, ctx);
10320 if (ret)
10321 goto fail;
10322 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10323 if (ret)
10324 goto fail;
10325
10326 old->dpms_mode = connector->dpms;
10327 old->load_detect_temp = false;
10328
10329 /* Make sure the crtc and connector are running */
10330 if (connector->dpms != DRM_MODE_DPMS_ON)
10331 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10332
10333 return true;
10334 }
10335
10336 /* Find an unused one (if possible) */
10337 for_each_crtc(dev, possible_crtc) {
10338 i++;
10339 if (!(encoder->possible_crtcs & (1 << i)))
10340 continue;
10341 if (possible_crtc->state->enable)
10342 continue;
10343
10344 crtc = possible_crtc;
10345 break;
10346 }
10347
10348 /*
10349 * If we didn't find an unused CRTC, don't use any.
10350 */
10351 if (!crtc) {
10352 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10353 goto fail;
10354 }
10355
10356 ret = drm_modeset_lock(&crtc->mutex, ctx);
10357 if (ret)
10358 goto fail;
10359 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10360 if (ret)
10361 goto fail;
10362
10363 intel_crtc = to_intel_crtc(crtc);
10364 old->dpms_mode = connector->dpms;
10365 old->load_detect_temp = true;
10366 old->release_fb = NULL;
10367
10368 state = drm_atomic_state_alloc(dev);
10369 if (!state)
10370 return false;
10371
10372 state->acquire_ctx = ctx;
10373
10374 connector_state = drm_atomic_get_connector_state(state, connector);
10375 if (IS_ERR(connector_state)) {
10376 ret = PTR_ERR(connector_state);
10377 goto fail;
10378 }
10379
10380 connector_state->crtc = crtc;
10381 connector_state->best_encoder = &intel_encoder->base;
10382
10383 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10384 if (IS_ERR(crtc_state)) {
10385 ret = PTR_ERR(crtc_state);
10386 goto fail;
10387 }
10388
10389 crtc_state->base.active = crtc_state->base.enable = true;
10390
10391 if (!mode)
10392 mode = &load_detect_mode;
10393
10394 /* We need a framebuffer large enough to accommodate all accesses
10395 * that the plane may generate whilst we perform load detection.
10396 * We can not rely on the fbcon either being present (we get called
10397 * during its initialisation to detect all boot displays, or it may
10398 * not even exist) or that it is large enough to satisfy the
10399 * requested mode.
10400 */
10401 fb = mode_fits_in_fbdev(dev, mode);
10402 if (fb == NULL) {
10403 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10404 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10405 old->release_fb = fb;
10406 } else
10407 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10408 if (IS_ERR(fb)) {
10409 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10410 goto fail;
10411 }
10412
10413 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10414 if (ret)
10415 goto fail;
10416
10417 drm_mode_copy(&crtc_state->base.mode, mode);
10418
10419 if (intel_set_mode(state)) {
10420 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10421 if (old->release_fb)
10422 old->release_fb->funcs->destroy(old->release_fb);
10423 goto fail;
10424 }
10425 crtc->primary->crtc = crtc;
10426
10427 /* let the connector get through one full cycle before testing */
10428 intel_wait_for_vblank(dev, intel_crtc->pipe);
10429 return true;
10430
10431 fail:
10432 drm_atomic_state_free(state);
10433 state = NULL;
10434
10435 if (ret == -EDEADLK) {
10436 drm_modeset_backoff(ctx);
10437 goto retry;
10438 }
10439
10440 return false;
10441 }
10442
10443 void intel_release_load_detect_pipe(struct drm_connector *connector,
10444 struct intel_load_detect_pipe *old,
10445 struct drm_modeset_acquire_ctx *ctx)
10446 {
10447 struct drm_device *dev = connector->dev;
10448 struct intel_encoder *intel_encoder =
10449 intel_attached_encoder(connector);
10450 struct drm_encoder *encoder = &intel_encoder->base;
10451 struct drm_crtc *crtc = encoder->crtc;
10452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10453 struct drm_atomic_state *state;
10454 struct drm_connector_state *connector_state;
10455 struct intel_crtc_state *crtc_state;
10456 int ret;
10457
10458 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10459 connector->base.id, connector->name,
10460 encoder->base.id, encoder->name);
10461
10462 if (old->load_detect_temp) {
10463 state = drm_atomic_state_alloc(dev);
10464 if (!state)
10465 goto fail;
10466
10467 state->acquire_ctx = ctx;
10468
10469 connector_state = drm_atomic_get_connector_state(state, connector);
10470 if (IS_ERR(connector_state))
10471 goto fail;
10472
10473 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10474 if (IS_ERR(crtc_state))
10475 goto fail;
10476
10477 connector_state->best_encoder = NULL;
10478 connector_state->crtc = NULL;
10479
10480 crtc_state->base.enable = crtc_state->base.active = false;
10481
10482 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10483 0, 0);
10484 if (ret)
10485 goto fail;
10486
10487 ret = intel_set_mode(state);
10488 if (ret)
10489 goto fail;
10490
10491 if (old->release_fb) {
10492 drm_framebuffer_unregister_private(old->release_fb);
10493 drm_framebuffer_unreference(old->release_fb);
10494 }
10495
10496 return;
10497 }
10498
10499 /* Switch crtc and encoder back off if necessary */
10500 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10501 connector->funcs->dpms(connector, old->dpms_mode);
10502
10503 return;
10504 fail:
10505 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10506 drm_atomic_state_free(state);
10507 }
10508
10509 static int i9xx_pll_refclk(struct drm_device *dev,
10510 const struct intel_crtc_state *pipe_config)
10511 {
10512 struct drm_i915_private *dev_priv = dev->dev_private;
10513 u32 dpll = pipe_config->dpll_hw_state.dpll;
10514
10515 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10516 return dev_priv->vbt.lvds_ssc_freq;
10517 else if (HAS_PCH_SPLIT(dev))
10518 return 120000;
10519 else if (!IS_GEN2(dev))
10520 return 96000;
10521 else
10522 return 48000;
10523 }
10524
10525 /* Returns the clock of the currently programmed mode of the given pipe. */
10526 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10527 struct intel_crtc_state *pipe_config)
10528 {
10529 struct drm_device *dev = crtc->base.dev;
10530 struct drm_i915_private *dev_priv = dev->dev_private;
10531 int pipe = pipe_config->cpu_transcoder;
10532 u32 dpll = pipe_config->dpll_hw_state.dpll;
10533 u32 fp;
10534 intel_clock_t clock;
10535 int refclk = i9xx_pll_refclk(dev, pipe_config);
10536
10537 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10538 fp = pipe_config->dpll_hw_state.fp0;
10539 else
10540 fp = pipe_config->dpll_hw_state.fp1;
10541
10542 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10543 if (IS_PINEVIEW(dev)) {
10544 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10545 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10546 } else {
10547 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10548 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10549 }
10550
10551 if (!IS_GEN2(dev)) {
10552 if (IS_PINEVIEW(dev))
10553 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10554 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10555 else
10556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10557 DPLL_FPA01_P1_POST_DIV_SHIFT);
10558
10559 switch (dpll & DPLL_MODE_MASK) {
10560 case DPLLB_MODE_DAC_SERIAL:
10561 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10562 5 : 10;
10563 break;
10564 case DPLLB_MODE_LVDS:
10565 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10566 7 : 14;
10567 break;
10568 default:
10569 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10570 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10571 return;
10572 }
10573
10574 if (IS_PINEVIEW(dev))
10575 pineview_clock(refclk, &clock);
10576 else
10577 i9xx_clock(refclk, &clock);
10578 } else {
10579 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10580 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10581
10582 if (is_lvds) {
10583 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10584 DPLL_FPA01_P1_POST_DIV_SHIFT);
10585
10586 if (lvds & LVDS_CLKB_POWER_UP)
10587 clock.p2 = 7;
10588 else
10589 clock.p2 = 14;
10590 } else {
10591 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10592 clock.p1 = 2;
10593 else {
10594 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10595 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10596 }
10597 if (dpll & PLL_P2_DIVIDE_BY_4)
10598 clock.p2 = 4;
10599 else
10600 clock.p2 = 2;
10601 }
10602
10603 i9xx_clock(refclk, &clock);
10604 }
10605
10606 /*
10607 * This value includes pixel_multiplier. We will use
10608 * port_clock to compute adjusted_mode.crtc_clock in the
10609 * encoder's get_config() function.
10610 */
10611 pipe_config->port_clock = clock.dot;
10612 }
10613
10614 int intel_dotclock_calculate(int link_freq,
10615 const struct intel_link_m_n *m_n)
10616 {
10617 /*
10618 * The calculation for the data clock is:
10619 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10620 * But we want to avoid losing precison if possible, so:
10621 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10622 *
10623 * and the link clock is simpler:
10624 * link_clock = (m * link_clock) / n
10625 */
10626
10627 if (!m_n->link_n)
10628 return 0;
10629
10630 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10631 }
10632
10633 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10634 struct intel_crtc_state *pipe_config)
10635 {
10636 struct drm_device *dev = crtc->base.dev;
10637
10638 /* read out port_clock from the DPLL */
10639 i9xx_crtc_clock_get(crtc, pipe_config);
10640
10641 /*
10642 * This value does not include pixel_multiplier.
10643 * We will check that port_clock and adjusted_mode.crtc_clock
10644 * agree once we know their relationship in the encoder's
10645 * get_config() function.
10646 */
10647 pipe_config->base.adjusted_mode.crtc_clock =
10648 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10649 &pipe_config->fdi_m_n);
10650 }
10651
10652 /** Returns the currently programmed mode of the given pipe. */
10653 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10654 struct drm_crtc *crtc)
10655 {
10656 struct drm_i915_private *dev_priv = dev->dev_private;
10657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10658 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10659 struct drm_display_mode *mode;
10660 struct intel_crtc_state pipe_config;
10661 int htot = I915_READ(HTOTAL(cpu_transcoder));
10662 int hsync = I915_READ(HSYNC(cpu_transcoder));
10663 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10664 int vsync = I915_READ(VSYNC(cpu_transcoder));
10665 enum pipe pipe = intel_crtc->pipe;
10666
10667 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10668 if (!mode)
10669 return NULL;
10670
10671 /*
10672 * Construct a pipe_config sufficient for getting the clock info
10673 * back out of crtc_clock_get.
10674 *
10675 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10676 * to use a real value here instead.
10677 */
10678 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10679 pipe_config.pixel_multiplier = 1;
10680 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10681 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10682 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10683 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10684
10685 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10686 mode->hdisplay = (htot & 0xffff) + 1;
10687 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10688 mode->hsync_start = (hsync & 0xffff) + 1;
10689 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10690 mode->vdisplay = (vtot & 0xffff) + 1;
10691 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10692 mode->vsync_start = (vsync & 0xffff) + 1;
10693 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10694
10695 drm_mode_set_name(mode);
10696
10697 return mode;
10698 }
10699
10700 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10701 {
10702 struct drm_device *dev = crtc->dev;
10703 struct drm_i915_private *dev_priv = dev->dev_private;
10704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10705
10706 if (!HAS_GMCH_DISPLAY(dev))
10707 return;
10708
10709 if (!dev_priv->lvds_downclock_avail)
10710 return;
10711
10712 /*
10713 * Since this is called by a timer, we should never get here in
10714 * the manual case.
10715 */
10716 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10717 int pipe = intel_crtc->pipe;
10718 int dpll_reg = DPLL(pipe);
10719 int dpll;
10720
10721 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10722
10723 assert_panel_unlocked(dev_priv, pipe);
10724
10725 dpll = I915_READ(dpll_reg);
10726 dpll |= DISPLAY_RATE_SELECT_FPA1;
10727 I915_WRITE(dpll_reg, dpll);
10728 intel_wait_for_vblank(dev, pipe);
10729 dpll = I915_READ(dpll_reg);
10730 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10731 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10732 }
10733
10734 }
10735
10736 void intel_mark_busy(struct drm_device *dev)
10737 {
10738 struct drm_i915_private *dev_priv = dev->dev_private;
10739
10740 if (dev_priv->mm.busy)
10741 return;
10742
10743 intel_runtime_pm_get(dev_priv);
10744 i915_update_gfx_val(dev_priv);
10745 if (INTEL_INFO(dev)->gen >= 6)
10746 gen6_rps_busy(dev_priv);
10747 dev_priv->mm.busy = true;
10748 }
10749
10750 void intel_mark_idle(struct drm_device *dev)
10751 {
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753 struct drm_crtc *crtc;
10754
10755 if (!dev_priv->mm.busy)
10756 return;
10757
10758 dev_priv->mm.busy = false;
10759
10760 for_each_crtc(dev, crtc) {
10761 if (!crtc->primary->fb)
10762 continue;
10763
10764 intel_decrease_pllclock(crtc);
10765 }
10766
10767 if (INTEL_INFO(dev)->gen >= 6)
10768 gen6_rps_idle(dev->dev_private);
10769
10770 intel_runtime_pm_put(dev_priv);
10771 }
10772
10773 static void intel_crtc_destroy(struct drm_crtc *crtc)
10774 {
10775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10776 struct drm_device *dev = crtc->dev;
10777 struct intel_unpin_work *work;
10778
10779 spin_lock_irq(&dev->event_lock);
10780 work = intel_crtc->unpin_work;
10781 intel_crtc->unpin_work = NULL;
10782 spin_unlock_irq(&dev->event_lock);
10783
10784 if (work) {
10785 cancel_work_sync(&work->work);
10786 kfree(work);
10787 }
10788
10789 drm_crtc_cleanup(crtc);
10790
10791 kfree(intel_crtc);
10792 }
10793
10794 static void intel_unpin_work_fn(struct work_struct *__work)
10795 {
10796 struct intel_unpin_work *work =
10797 container_of(__work, struct intel_unpin_work, work);
10798 struct drm_device *dev = work->crtc->dev;
10799 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10800
10801 mutex_lock(&dev->struct_mutex);
10802 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10803 drm_gem_object_unreference(&work->pending_flip_obj->base);
10804
10805 intel_fbc_update(dev);
10806
10807 if (work->flip_queued_req)
10808 i915_gem_request_assign(&work->flip_queued_req, NULL);
10809 mutex_unlock(&dev->struct_mutex);
10810
10811 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10812 drm_framebuffer_unreference(work->old_fb);
10813
10814 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10815 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10816
10817 kfree(work);
10818 }
10819
10820 static void do_intel_finish_page_flip(struct drm_device *dev,
10821 struct drm_crtc *crtc)
10822 {
10823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10824 struct intel_unpin_work *work;
10825 unsigned long flags;
10826
10827 /* Ignore early vblank irqs */
10828 if (intel_crtc == NULL)
10829 return;
10830
10831 /*
10832 * This is called both by irq handlers and the reset code (to complete
10833 * lost pageflips) so needs the full irqsave spinlocks.
10834 */
10835 spin_lock_irqsave(&dev->event_lock, flags);
10836 work = intel_crtc->unpin_work;
10837
10838 /* Ensure we don't miss a work->pending update ... */
10839 smp_rmb();
10840
10841 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10842 spin_unlock_irqrestore(&dev->event_lock, flags);
10843 return;
10844 }
10845
10846 page_flip_completed(intel_crtc);
10847
10848 spin_unlock_irqrestore(&dev->event_lock, flags);
10849 }
10850
10851 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10852 {
10853 struct drm_i915_private *dev_priv = dev->dev_private;
10854 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10855
10856 do_intel_finish_page_flip(dev, crtc);
10857 }
10858
10859 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10860 {
10861 struct drm_i915_private *dev_priv = dev->dev_private;
10862 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10863
10864 do_intel_finish_page_flip(dev, crtc);
10865 }
10866
10867 /* Is 'a' after or equal to 'b'? */
10868 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10869 {
10870 return !((a - b) & 0x80000000);
10871 }
10872
10873 static bool page_flip_finished(struct intel_crtc *crtc)
10874 {
10875 struct drm_device *dev = crtc->base.dev;
10876 struct drm_i915_private *dev_priv = dev->dev_private;
10877
10878 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10879 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10880 return true;
10881
10882 /*
10883 * The relevant registers doen't exist on pre-ctg.
10884 * As the flip done interrupt doesn't trigger for mmio
10885 * flips on gmch platforms, a flip count check isn't
10886 * really needed there. But since ctg has the registers,
10887 * include it in the check anyway.
10888 */
10889 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10890 return true;
10891
10892 /*
10893 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10894 * used the same base address. In that case the mmio flip might
10895 * have completed, but the CS hasn't even executed the flip yet.
10896 *
10897 * A flip count check isn't enough as the CS might have updated
10898 * the base address just after start of vblank, but before we
10899 * managed to process the interrupt. This means we'd complete the
10900 * CS flip too soon.
10901 *
10902 * Combining both checks should get us a good enough result. It may
10903 * still happen that the CS flip has been executed, but has not
10904 * yet actually completed. But in case the base address is the same
10905 * anyway, we don't really care.
10906 */
10907 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10908 crtc->unpin_work->gtt_offset &&
10909 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10910 crtc->unpin_work->flip_count);
10911 }
10912
10913 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10914 {
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 struct intel_crtc *intel_crtc =
10917 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10918 unsigned long flags;
10919
10920
10921 /*
10922 * This is called both by irq handlers and the reset code (to complete
10923 * lost pageflips) so needs the full irqsave spinlocks.
10924 *
10925 * NB: An MMIO update of the plane base pointer will also
10926 * generate a page-flip completion irq, i.e. every modeset
10927 * is also accompanied by a spurious intel_prepare_page_flip().
10928 */
10929 spin_lock_irqsave(&dev->event_lock, flags);
10930 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10931 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10932 spin_unlock_irqrestore(&dev->event_lock, flags);
10933 }
10934
10935 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10936 {
10937 /* Ensure that the work item is consistent when activating it ... */
10938 smp_wmb();
10939 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10940 /* and that it is marked active as soon as the irq could fire. */
10941 smp_wmb();
10942 }
10943
10944 static int intel_gen2_queue_flip(struct drm_device *dev,
10945 struct drm_crtc *crtc,
10946 struct drm_framebuffer *fb,
10947 struct drm_i915_gem_object *obj,
10948 struct intel_engine_cs *ring,
10949 uint32_t flags)
10950 {
10951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10952 u32 flip_mask;
10953 int ret;
10954
10955 ret = intel_ring_begin(ring, 6);
10956 if (ret)
10957 return ret;
10958
10959 /* Can't queue multiple flips, so wait for the previous
10960 * one to finish before executing the next.
10961 */
10962 if (intel_crtc->plane)
10963 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10964 else
10965 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10966 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10967 intel_ring_emit(ring, MI_NOOP);
10968 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10969 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10970 intel_ring_emit(ring, fb->pitches[0]);
10971 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10972 intel_ring_emit(ring, 0); /* aux display base address, unused */
10973
10974 intel_mark_page_flip_active(intel_crtc);
10975 __intel_ring_advance(ring);
10976 return 0;
10977 }
10978
10979 static int intel_gen3_queue_flip(struct drm_device *dev,
10980 struct drm_crtc *crtc,
10981 struct drm_framebuffer *fb,
10982 struct drm_i915_gem_object *obj,
10983 struct intel_engine_cs *ring,
10984 uint32_t flags)
10985 {
10986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10987 u32 flip_mask;
10988 int ret;
10989
10990 ret = intel_ring_begin(ring, 6);
10991 if (ret)
10992 return ret;
10993
10994 if (intel_crtc->plane)
10995 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10996 else
10997 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10998 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10999 intel_ring_emit(ring, MI_NOOP);
11000 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11001 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11002 intel_ring_emit(ring, fb->pitches[0]);
11003 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11004 intel_ring_emit(ring, MI_NOOP);
11005
11006 intel_mark_page_flip_active(intel_crtc);
11007 __intel_ring_advance(ring);
11008 return 0;
11009 }
11010
11011 static int intel_gen4_queue_flip(struct drm_device *dev,
11012 struct drm_crtc *crtc,
11013 struct drm_framebuffer *fb,
11014 struct drm_i915_gem_object *obj,
11015 struct intel_engine_cs *ring,
11016 uint32_t flags)
11017 {
11018 struct drm_i915_private *dev_priv = dev->dev_private;
11019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11020 uint32_t pf, pipesrc;
11021 int ret;
11022
11023 ret = intel_ring_begin(ring, 4);
11024 if (ret)
11025 return ret;
11026
11027 /* i965+ uses the linear or tiled offsets from the
11028 * Display Registers (which do not change across a page-flip)
11029 * so we need only reprogram the base address.
11030 */
11031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033 intel_ring_emit(ring, fb->pitches[0]);
11034 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11035 obj->tiling_mode);
11036
11037 /* XXX Enabling the panel-fitter across page-flip is so far
11038 * untested on non-native modes, so ignore it for now.
11039 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11040 */
11041 pf = 0;
11042 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11043 intel_ring_emit(ring, pf | pipesrc);
11044
11045 intel_mark_page_flip_active(intel_crtc);
11046 __intel_ring_advance(ring);
11047 return 0;
11048 }
11049
11050 static int intel_gen6_queue_flip(struct drm_device *dev,
11051 struct drm_crtc *crtc,
11052 struct drm_framebuffer *fb,
11053 struct drm_i915_gem_object *obj,
11054 struct intel_engine_cs *ring,
11055 uint32_t flags)
11056 {
11057 struct drm_i915_private *dev_priv = dev->dev_private;
11058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11059 uint32_t pf, pipesrc;
11060 int ret;
11061
11062 ret = intel_ring_begin(ring, 4);
11063 if (ret)
11064 return ret;
11065
11066 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11068 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11069 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11070
11071 /* Contrary to the suggestions in the documentation,
11072 * "Enable Panel Fitter" does not seem to be required when page
11073 * flipping with a non-native mode, and worse causes a normal
11074 * modeset to fail.
11075 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11076 */
11077 pf = 0;
11078 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11079 intel_ring_emit(ring, pf | pipesrc);
11080
11081 intel_mark_page_flip_active(intel_crtc);
11082 __intel_ring_advance(ring);
11083 return 0;
11084 }
11085
11086 static int intel_gen7_queue_flip(struct drm_device *dev,
11087 struct drm_crtc *crtc,
11088 struct drm_framebuffer *fb,
11089 struct drm_i915_gem_object *obj,
11090 struct intel_engine_cs *ring,
11091 uint32_t flags)
11092 {
11093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11094 uint32_t plane_bit = 0;
11095 int len, ret;
11096
11097 switch (intel_crtc->plane) {
11098 case PLANE_A:
11099 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11100 break;
11101 case PLANE_B:
11102 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11103 break;
11104 case PLANE_C:
11105 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11106 break;
11107 default:
11108 WARN_ONCE(1, "unknown plane in flip command\n");
11109 return -ENODEV;
11110 }
11111
11112 len = 4;
11113 if (ring->id == RCS) {
11114 len += 6;
11115 /*
11116 * On Gen 8, SRM is now taking an extra dword to accommodate
11117 * 48bits addresses, and we need a NOOP for the batch size to
11118 * stay even.
11119 */
11120 if (IS_GEN8(dev))
11121 len += 2;
11122 }
11123
11124 /*
11125 * BSpec MI_DISPLAY_FLIP for IVB:
11126 * "The full packet must be contained within the same cache line."
11127 *
11128 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11129 * cacheline, if we ever start emitting more commands before
11130 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11131 * then do the cacheline alignment, and finally emit the
11132 * MI_DISPLAY_FLIP.
11133 */
11134 ret = intel_ring_cacheline_align(ring);
11135 if (ret)
11136 return ret;
11137
11138 ret = intel_ring_begin(ring, len);
11139 if (ret)
11140 return ret;
11141
11142 /* Unmask the flip-done completion message. Note that the bspec says that
11143 * we should do this for both the BCS and RCS, and that we must not unmask
11144 * more than one flip event at any time (or ensure that one flip message
11145 * can be sent by waiting for flip-done prior to queueing new flips).
11146 * Experimentation says that BCS works despite DERRMR masking all
11147 * flip-done completion events and that unmasking all planes at once
11148 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11149 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11150 */
11151 if (ring->id == RCS) {
11152 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11153 intel_ring_emit(ring, DERRMR);
11154 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11155 DERRMR_PIPEB_PRI_FLIP_DONE |
11156 DERRMR_PIPEC_PRI_FLIP_DONE));
11157 if (IS_GEN8(dev))
11158 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11159 MI_SRM_LRM_GLOBAL_GTT);
11160 else
11161 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11162 MI_SRM_LRM_GLOBAL_GTT);
11163 intel_ring_emit(ring, DERRMR);
11164 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11165 if (IS_GEN8(dev)) {
11166 intel_ring_emit(ring, 0);
11167 intel_ring_emit(ring, MI_NOOP);
11168 }
11169 }
11170
11171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11172 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11173 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11174 intel_ring_emit(ring, (MI_NOOP));
11175
11176 intel_mark_page_flip_active(intel_crtc);
11177 __intel_ring_advance(ring);
11178 return 0;
11179 }
11180
11181 static bool use_mmio_flip(struct intel_engine_cs *ring,
11182 struct drm_i915_gem_object *obj)
11183 {
11184 /*
11185 * This is not being used for older platforms, because
11186 * non-availability of flip done interrupt forces us to use
11187 * CS flips. Older platforms derive flip done using some clever
11188 * tricks involving the flip_pending status bits and vblank irqs.
11189 * So using MMIO flips there would disrupt this mechanism.
11190 */
11191
11192 if (ring == NULL)
11193 return true;
11194
11195 if (INTEL_INFO(ring->dev)->gen < 5)
11196 return false;
11197
11198 if (i915.use_mmio_flip < 0)
11199 return false;
11200 else if (i915.use_mmio_flip > 0)
11201 return true;
11202 else if (i915.enable_execlists)
11203 return true;
11204 else
11205 return ring != i915_gem_request_get_ring(obj->last_write_req);
11206 }
11207
11208 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11209 {
11210 struct drm_device *dev = intel_crtc->base.dev;
11211 struct drm_i915_private *dev_priv = dev->dev_private;
11212 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11213 const enum pipe pipe = intel_crtc->pipe;
11214 u32 ctl, stride;
11215
11216 ctl = I915_READ(PLANE_CTL(pipe, 0));
11217 ctl &= ~PLANE_CTL_TILED_MASK;
11218 switch (fb->modifier[0]) {
11219 case DRM_FORMAT_MOD_NONE:
11220 break;
11221 case I915_FORMAT_MOD_X_TILED:
11222 ctl |= PLANE_CTL_TILED_X;
11223 break;
11224 case I915_FORMAT_MOD_Y_TILED:
11225 ctl |= PLANE_CTL_TILED_Y;
11226 break;
11227 case I915_FORMAT_MOD_Yf_TILED:
11228 ctl |= PLANE_CTL_TILED_YF;
11229 break;
11230 default:
11231 MISSING_CASE(fb->modifier[0]);
11232 }
11233
11234 /*
11235 * The stride is either expressed as a multiple of 64 bytes chunks for
11236 * linear buffers or in number of tiles for tiled buffers.
11237 */
11238 stride = fb->pitches[0] /
11239 intel_fb_stride_alignment(dev, fb->modifier[0],
11240 fb->pixel_format);
11241
11242 /*
11243 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11244 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11245 */
11246 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11247 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11248
11249 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11250 POSTING_READ(PLANE_SURF(pipe, 0));
11251 }
11252
11253 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11254 {
11255 struct drm_device *dev = intel_crtc->base.dev;
11256 struct drm_i915_private *dev_priv = dev->dev_private;
11257 struct intel_framebuffer *intel_fb =
11258 to_intel_framebuffer(intel_crtc->base.primary->fb);
11259 struct drm_i915_gem_object *obj = intel_fb->obj;
11260 u32 dspcntr;
11261 u32 reg;
11262
11263 reg = DSPCNTR(intel_crtc->plane);
11264 dspcntr = I915_READ(reg);
11265
11266 if (obj->tiling_mode != I915_TILING_NONE)
11267 dspcntr |= DISPPLANE_TILED;
11268 else
11269 dspcntr &= ~DISPPLANE_TILED;
11270
11271 I915_WRITE(reg, dspcntr);
11272
11273 I915_WRITE(DSPSURF(intel_crtc->plane),
11274 intel_crtc->unpin_work->gtt_offset);
11275 POSTING_READ(DSPSURF(intel_crtc->plane));
11276
11277 }
11278
11279 /*
11280 * XXX: This is the temporary way to update the plane registers until we get
11281 * around to using the usual plane update functions for MMIO flips
11282 */
11283 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11284 {
11285 struct drm_device *dev = intel_crtc->base.dev;
11286 bool atomic_update;
11287 u32 start_vbl_count;
11288
11289 intel_mark_page_flip_active(intel_crtc);
11290
11291 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11292
11293 if (INTEL_INFO(dev)->gen >= 9)
11294 skl_do_mmio_flip(intel_crtc);
11295 else
11296 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11297 ilk_do_mmio_flip(intel_crtc);
11298
11299 if (atomic_update)
11300 intel_pipe_update_end(intel_crtc, start_vbl_count);
11301 }
11302
11303 static void intel_mmio_flip_work_func(struct work_struct *work)
11304 {
11305 struct intel_mmio_flip *mmio_flip =
11306 container_of(work, struct intel_mmio_flip, work);
11307
11308 if (mmio_flip->req)
11309 WARN_ON(__i915_wait_request(mmio_flip->req,
11310 mmio_flip->crtc->reset_counter,
11311 false, NULL,
11312 &mmio_flip->i915->rps.mmioflips));
11313
11314 intel_do_mmio_flip(mmio_flip->crtc);
11315
11316 i915_gem_request_unreference__unlocked(mmio_flip->req);
11317 kfree(mmio_flip);
11318 }
11319
11320 static int intel_queue_mmio_flip(struct drm_device *dev,
11321 struct drm_crtc *crtc,
11322 struct drm_framebuffer *fb,
11323 struct drm_i915_gem_object *obj,
11324 struct intel_engine_cs *ring,
11325 uint32_t flags)
11326 {
11327 struct intel_mmio_flip *mmio_flip;
11328
11329 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11330 if (mmio_flip == NULL)
11331 return -ENOMEM;
11332
11333 mmio_flip->i915 = to_i915(dev);
11334 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11335 mmio_flip->crtc = to_intel_crtc(crtc);
11336
11337 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11338 schedule_work(&mmio_flip->work);
11339
11340 return 0;
11341 }
11342
11343 static int intel_default_queue_flip(struct drm_device *dev,
11344 struct drm_crtc *crtc,
11345 struct drm_framebuffer *fb,
11346 struct drm_i915_gem_object *obj,
11347 struct intel_engine_cs *ring,
11348 uint32_t flags)
11349 {
11350 return -ENODEV;
11351 }
11352
11353 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11354 struct drm_crtc *crtc)
11355 {
11356 struct drm_i915_private *dev_priv = dev->dev_private;
11357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11358 struct intel_unpin_work *work = intel_crtc->unpin_work;
11359 u32 addr;
11360
11361 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11362 return true;
11363
11364 if (!work->enable_stall_check)
11365 return false;
11366
11367 if (work->flip_ready_vblank == 0) {
11368 if (work->flip_queued_req &&
11369 !i915_gem_request_completed(work->flip_queued_req, true))
11370 return false;
11371
11372 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11373 }
11374
11375 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11376 return false;
11377
11378 /* Potential stall - if we see that the flip has happened,
11379 * assume a missed interrupt. */
11380 if (INTEL_INFO(dev)->gen >= 4)
11381 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11382 else
11383 addr = I915_READ(DSPADDR(intel_crtc->plane));
11384
11385 /* There is a potential issue here with a false positive after a flip
11386 * to the same address. We could address this by checking for a
11387 * non-incrementing frame counter.
11388 */
11389 return addr == work->gtt_offset;
11390 }
11391
11392 void intel_check_page_flip(struct drm_device *dev, int pipe)
11393 {
11394 struct drm_i915_private *dev_priv = dev->dev_private;
11395 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11397 struct intel_unpin_work *work;
11398
11399 WARN_ON(!in_interrupt());
11400
11401 if (crtc == NULL)
11402 return;
11403
11404 spin_lock(&dev->event_lock);
11405 work = intel_crtc->unpin_work;
11406 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11407 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11408 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11409 page_flip_completed(intel_crtc);
11410 work = NULL;
11411 }
11412 if (work != NULL &&
11413 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11414 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11415 spin_unlock(&dev->event_lock);
11416 }
11417
11418 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11419 struct drm_framebuffer *fb,
11420 struct drm_pending_vblank_event *event,
11421 uint32_t page_flip_flags)
11422 {
11423 struct drm_device *dev = crtc->dev;
11424 struct drm_i915_private *dev_priv = dev->dev_private;
11425 struct drm_framebuffer *old_fb = crtc->primary->fb;
11426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11428 struct drm_plane *primary = crtc->primary;
11429 enum pipe pipe = intel_crtc->pipe;
11430 struct intel_unpin_work *work;
11431 struct intel_engine_cs *ring;
11432 bool mmio_flip;
11433 int ret;
11434
11435 /*
11436 * drm_mode_page_flip_ioctl() should already catch this, but double
11437 * check to be safe. In the future we may enable pageflipping from
11438 * a disabled primary plane.
11439 */
11440 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11441 return -EBUSY;
11442
11443 /* Can't change pixel format via MI display flips. */
11444 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11445 return -EINVAL;
11446
11447 /*
11448 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11449 * Note that pitch changes could also affect these register.
11450 */
11451 if (INTEL_INFO(dev)->gen > 3 &&
11452 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11453 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11454 return -EINVAL;
11455
11456 if (i915_terminally_wedged(&dev_priv->gpu_error))
11457 goto out_hang;
11458
11459 work = kzalloc(sizeof(*work), GFP_KERNEL);
11460 if (work == NULL)
11461 return -ENOMEM;
11462
11463 work->event = event;
11464 work->crtc = crtc;
11465 work->old_fb = old_fb;
11466 INIT_WORK(&work->work, intel_unpin_work_fn);
11467
11468 ret = drm_crtc_vblank_get(crtc);
11469 if (ret)
11470 goto free_work;
11471
11472 /* We borrow the event spin lock for protecting unpin_work */
11473 spin_lock_irq(&dev->event_lock);
11474 if (intel_crtc->unpin_work) {
11475 /* Before declaring the flip queue wedged, check if
11476 * the hardware completed the operation behind our backs.
11477 */
11478 if (__intel_pageflip_stall_check(dev, crtc)) {
11479 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11480 page_flip_completed(intel_crtc);
11481 } else {
11482 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11483 spin_unlock_irq(&dev->event_lock);
11484
11485 drm_crtc_vblank_put(crtc);
11486 kfree(work);
11487 return -EBUSY;
11488 }
11489 }
11490 intel_crtc->unpin_work = work;
11491 spin_unlock_irq(&dev->event_lock);
11492
11493 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11494 flush_workqueue(dev_priv->wq);
11495
11496 /* Reference the objects for the scheduled work. */
11497 drm_framebuffer_reference(work->old_fb);
11498 drm_gem_object_reference(&obj->base);
11499
11500 crtc->primary->fb = fb;
11501 update_state_fb(crtc->primary);
11502
11503 work->pending_flip_obj = obj;
11504
11505 ret = i915_mutex_lock_interruptible(dev);
11506 if (ret)
11507 goto cleanup;
11508
11509 atomic_inc(&intel_crtc->unpin_work_count);
11510 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11511
11512 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11513 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11514
11515 if (IS_VALLEYVIEW(dev)) {
11516 ring = &dev_priv->ring[BCS];
11517 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11518 /* vlv: DISPLAY_FLIP fails to change tiling */
11519 ring = NULL;
11520 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11521 ring = &dev_priv->ring[BCS];
11522 } else if (INTEL_INFO(dev)->gen >= 7) {
11523 ring = i915_gem_request_get_ring(obj->last_write_req);
11524 if (ring == NULL || ring->id != RCS)
11525 ring = &dev_priv->ring[BCS];
11526 } else {
11527 ring = &dev_priv->ring[RCS];
11528 }
11529
11530 mmio_flip = use_mmio_flip(ring, obj);
11531
11532 /* When using CS flips, we want to emit semaphores between rings.
11533 * However, when using mmio flips we will create a task to do the
11534 * synchronisation, so all we want here is to pin the framebuffer
11535 * into the display plane and skip any waits.
11536 */
11537 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11538 crtc->primary->state,
11539 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11540 if (ret)
11541 goto cleanup_pending;
11542
11543 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11544 + intel_crtc->dspaddr_offset;
11545
11546 if (mmio_flip) {
11547 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11548 page_flip_flags);
11549 if (ret)
11550 goto cleanup_unpin;
11551
11552 i915_gem_request_assign(&work->flip_queued_req,
11553 obj->last_write_req);
11554 } else {
11555 if (obj->last_write_req) {
11556 ret = i915_gem_check_olr(obj->last_write_req);
11557 if (ret)
11558 goto cleanup_unpin;
11559 }
11560
11561 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11562 page_flip_flags);
11563 if (ret)
11564 goto cleanup_unpin;
11565
11566 i915_gem_request_assign(&work->flip_queued_req,
11567 intel_ring_get_request(ring));
11568 }
11569
11570 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11571 work->enable_stall_check = true;
11572
11573 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11574 INTEL_FRONTBUFFER_PRIMARY(pipe));
11575
11576 intel_fbc_disable(dev);
11577 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11578 mutex_unlock(&dev->struct_mutex);
11579
11580 trace_i915_flip_request(intel_crtc->plane, obj);
11581
11582 return 0;
11583
11584 cleanup_unpin:
11585 intel_unpin_fb_obj(fb, crtc->primary->state);
11586 cleanup_pending:
11587 atomic_dec(&intel_crtc->unpin_work_count);
11588 mutex_unlock(&dev->struct_mutex);
11589 cleanup:
11590 crtc->primary->fb = old_fb;
11591 update_state_fb(crtc->primary);
11592
11593 drm_gem_object_unreference_unlocked(&obj->base);
11594 drm_framebuffer_unreference(work->old_fb);
11595
11596 spin_lock_irq(&dev->event_lock);
11597 intel_crtc->unpin_work = NULL;
11598 spin_unlock_irq(&dev->event_lock);
11599
11600 drm_crtc_vblank_put(crtc);
11601 free_work:
11602 kfree(work);
11603
11604 if (ret == -EIO) {
11605 out_hang:
11606 ret = intel_plane_restore(primary);
11607 if (ret == 0 && event) {
11608 spin_lock_irq(&dev->event_lock);
11609 drm_send_vblank_event(dev, pipe, event);
11610 spin_unlock_irq(&dev->event_lock);
11611 }
11612 }
11613 return ret;
11614 }
11615
11616 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11617 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11618 .load_lut = intel_crtc_load_lut,
11619 .atomic_begin = intel_begin_crtc_commit,
11620 .atomic_flush = intel_finish_crtc_commit,
11621 };
11622
11623 /* Transitional helper to copy current connector/encoder state to
11624 * connector->state. This is needed so that code that is partially
11625 * converted to atomic does the right thing.
11626 */
11627 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11628 {
11629 struct intel_connector *connector;
11630
11631 for_each_intel_connector(dev, connector) {
11632 if (connector->base.encoder) {
11633 connector->base.state->best_encoder =
11634 connector->base.encoder;
11635 connector->base.state->crtc =
11636 connector->base.encoder->crtc;
11637 } else {
11638 connector->base.state->best_encoder = NULL;
11639 connector->base.state->crtc = NULL;
11640 }
11641 }
11642 }
11643
11644 static void
11645 connected_sink_compute_bpp(struct intel_connector *connector,
11646 struct intel_crtc_state *pipe_config)
11647 {
11648 int bpp = pipe_config->pipe_bpp;
11649
11650 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11651 connector->base.base.id,
11652 connector->base.name);
11653
11654 /* Don't use an invalid EDID bpc value */
11655 if (connector->base.display_info.bpc &&
11656 connector->base.display_info.bpc * 3 < bpp) {
11657 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11658 bpp, connector->base.display_info.bpc*3);
11659 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11660 }
11661
11662 /* Clamp bpp to 8 on screens without EDID 1.4 */
11663 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11664 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11665 bpp);
11666 pipe_config->pipe_bpp = 24;
11667 }
11668 }
11669
11670 static int
11671 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11672 struct intel_crtc_state *pipe_config)
11673 {
11674 struct drm_device *dev = crtc->base.dev;
11675 struct drm_atomic_state *state;
11676 struct drm_connector *connector;
11677 struct drm_connector_state *connector_state;
11678 int bpp, i;
11679
11680 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11681 bpp = 10*3;
11682 else if (INTEL_INFO(dev)->gen >= 5)
11683 bpp = 12*3;
11684 else
11685 bpp = 8*3;
11686
11687
11688 pipe_config->pipe_bpp = bpp;
11689
11690 state = pipe_config->base.state;
11691
11692 /* Clamp display bpp to EDID value */
11693 for_each_connector_in_state(state, connector, connector_state, i) {
11694 if (connector_state->crtc != &crtc->base)
11695 continue;
11696
11697 connected_sink_compute_bpp(to_intel_connector(connector),
11698 pipe_config);
11699 }
11700
11701 return bpp;
11702 }
11703
11704 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11705 {
11706 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11707 "type: 0x%x flags: 0x%x\n",
11708 mode->crtc_clock,
11709 mode->crtc_hdisplay, mode->crtc_hsync_start,
11710 mode->crtc_hsync_end, mode->crtc_htotal,
11711 mode->crtc_vdisplay, mode->crtc_vsync_start,
11712 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11713 }
11714
11715 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11716 struct intel_crtc_state *pipe_config,
11717 const char *context)
11718 {
11719 struct drm_device *dev = crtc->base.dev;
11720 struct drm_plane *plane;
11721 struct intel_plane *intel_plane;
11722 struct intel_plane_state *state;
11723 struct drm_framebuffer *fb;
11724
11725 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11726 context, pipe_config, pipe_name(crtc->pipe));
11727
11728 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11729 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11730 pipe_config->pipe_bpp, pipe_config->dither);
11731 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11732 pipe_config->has_pch_encoder,
11733 pipe_config->fdi_lanes,
11734 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11735 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11736 pipe_config->fdi_m_n.tu);
11737 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11738 pipe_config->has_dp_encoder,
11739 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11740 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11741 pipe_config->dp_m_n.tu);
11742
11743 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11744 pipe_config->has_dp_encoder,
11745 pipe_config->dp_m2_n2.gmch_m,
11746 pipe_config->dp_m2_n2.gmch_n,
11747 pipe_config->dp_m2_n2.link_m,
11748 pipe_config->dp_m2_n2.link_n,
11749 pipe_config->dp_m2_n2.tu);
11750
11751 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11752 pipe_config->has_audio,
11753 pipe_config->has_infoframe);
11754
11755 DRM_DEBUG_KMS("requested mode:\n");
11756 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11757 DRM_DEBUG_KMS("adjusted mode:\n");
11758 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11759 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11760 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11761 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11762 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11763 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11764 crtc->num_scalers,
11765 pipe_config->scaler_state.scaler_users,
11766 pipe_config->scaler_state.scaler_id);
11767 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11768 pipe_config->gmch_pfit.control,
11769 pipe_config->gmch_pfit.pgm_ratios,
11770 pipe_config->gmch_pfit.lvds_border_bits);
11771 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11772 pipe_config->pch_pfit.pos,
11773 pipe_config->pch_pfit.size,
11774 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11775 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11776 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11777
11778 if (IS_BROXTON(dev)) {
11779 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11780 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11781 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11782 pipe_config->ddi_pll_sel,
11783 pipe_config->dpll_hw_state.ebb0,
11784 pipe_config->dpll_hw_state.pll0,
11785 pipe_config->dpll_hw_state.pll1,
11786 pipe_config->dpll_hw_state.pll2,
11787 pipe_config->dpll_hw_state.pll3,
11788 pipe_config->dpll_hw_state.pll6,
11789 pipe_config->dpll_hw_state.pll8,
11790 pipe_config->dpll_hw_state.pcsdw12);
11791 } else if (IS_SKYLAKE(dev)) {
11792 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11793 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11794 pipe_config->ddi_pll_sel,
11795 pipe_config->dpll_hw_state.ctrl1,
11796 pipe_config->dpll_hw_state.cfgcr1,
11797 pipe_config->dpll_hw_state.cfgcr2);
11798 } else if (HAS_DDI(dev)) {
11799 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11800 pipe_config->ddi_pll_sel,
11801 pipe_config->dpll_hw_state.wrpll);
11802 } else {
11803 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11804 "fp0: 0x%x, fp1: 0x%x\n",
11805 pipe_config->dpll_hw_state.dpll,
11806 pipe_config->dpll_hw_state.dpll_md,
11807 pipe_config->dpll_hw_state.fp0,
11808 pipe_config->dpll_hw_state.fp1);
11809 }
11810
11811 DRM_DEBUG_KMS("planes on this crtc\n");
11812 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11813 intel_plane = to_intel_plane(plane);
11814 if (intel_plane->pipe != crtc->pipe)
11815 continue;
11816
11817 state = to_intel_plane_state(plane->state);
11818 fb = state->base.fb;
11819 if (!fb) {
11820 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11821 "disabled, scaler_id = %d\n",
11822 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11823 plane->base.id, intel_plane->pipe,
11824 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11825 drm_plane_index(plane), state->scaler_id);
11826 continue;
11827 }
11828
11829 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11830 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11831 plane->base.id, intel_plane->pipe,
11832 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11833 drm_plane_index(plane));
11834 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11835 fb->base.id, fb->width, fb->height, fb->pixel_format);
11836 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11837 state->scaler_id,
11838 state->src.x1 >> 16, state->src.y1 >> 16,
11839 drm_rect_width(&state->src) >> 16,
11840 drm_rect_height(&state->src) >> 16,
11841 state->dst.x1, state->dst.y1,
11842 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11843 }
11844 }
11845
11846 static bool encoders_cloneable(const struct intel_encoder *a,
11847 const struct intel_encoder *b)
11848 {
11849 /* masks could be asymmetric, so check both ways */
11850 return a == b || (a->cloneable & (1 << b->type) &&
11851 b->cloneable & (1 << a->type));
11852 }
11853
11854 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11855 struct intel_crtc *crtc,
11856 struct intel_encoder *encoder)
11857 {
11858 struct intel_encoder *source_encoder;
11859 struct drm_connector *connector;
11860 struct drm_connector_state *connector_state;
11861 int i;
11862
11863 for_each_connector_in_state(state, connector, connector_state, i) {
11864 if (connector_state->crtc != &crtc->base)
11865 continue;
11866
11867 source_encoder =
11868 to_intel_encoder(connector_state->best_encoder);
11869 if (!encoders_cloneable(encoder, source_encoder))
11870 return false;
11871 }
11872
11873 return true;
11874 }
11875
11876 static bool check_encoder_cloning(struct drm_atomic_state *state,
11877 struct intel_crtc *crtc)
11878 {
11879 struct intel_encoder *encoder;
11880 struct drm_connector *connector;
11881 struct drm_connector_state *connector_state;
11882 int i;
11883
11884 for_each_connector_in_state(state, connector, connector_state, i) {
11885 if (connector_state->crtc != &crtc->base)
11886 continue;
11887
11888 encoder = to_intel_encoder(connector_state->best_encoder);
11889 if (!check_single_encoder_cloning(state, crtc, encoder))
11890 return false;
11891 }
11892
11893 return true;
11894 }
11895
11896 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11897 {
11898 struct drm_device *dev = state->dev;
11899 struct intel_encoder *encoder;
11900 struct drm_connector *connector;
11901 struct drm_connector_state *connector_state;
11902 unsigned int used_ports = 0;
11903 int i;
11904
11905 /*
11906 * Walk the connector list instead of the encoder
11907 * list to detect the problem on ddi platforms
11908 * where there's just one encoder per digital port.
11909 */
11910 for_each_connector_in_state(state, connector, connector_state, i) {
11911 if (!connector_state->best_encoder)
11912 continue;
11913
11914 encoder = to_intel_encoder(connector_state->best_encoder);
11915
11916 WARN_ON(!connector_state->crtc);
11917
11918 switch (encoder->type) {
11919 unsigned int port_mask;
11920 case INTEL_OUTPUT_UNKNOWN:
11921 if (WARN_ON(!HAS_DDI(dev)))
11922 break;
11923 case INTEL_OUTPUT_DISPLAYPORT:
11924 case INTEL_OUTPUT_HDMI:
11925 case INTEL_OUTPUT_EDP:
11926 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11927
11928 /* the same port mustn't appear more than once */
11929 if (used_ports & port_mask)
11930 return false;
11931
11932 used_ports |= port_mask;
11933 default:
11934 break;
11935 }
11936 }
11937
11938 return true;
11939 }
11940
11941 static void
11942 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11943 {
11944 struct drm_crtc_state tmp_state;
11945 struct intel_crtc_scaler_state scaler_state;
11946 struct intel_dpll_hw_state dpll_hw_state;
11947 enum intel_dpll_id shared_dpll;
11948 uint32_t ddi_pll_sel;
11949
11950 /* FIXME: before the switch to atomic started, a new pipe_config was
11951 * kzalloc'd. Code that depends on any field being zero should be
11952 * fixed, so that the crtc_state can be safely duplicated. For now,
11953 * only fields that are know to not cause problems are preserved. */
11954
11955 tmp_state = crtc_state->base;
11956 scaler_state = crtc_state->scaler_state;
11957 shared_dpll = crtc_state->shared_dpll;
11958 dpll_hw_state = crtc_state->dpll_hw_state;
11959 ddi_pll_sel = crtc_state->ddi_pll_sel;
11960
11961 memset(crtc_state, 0, sizeof *crtc_state);
11962
11963 crtc_state->base = tmp_state;
11964 crtc_state->scaler_state = scaler_state;
11965 crtc_state->shared_dpll = shared_dpll;
11966 crtc_state->dpll_hw_state = dpll_hw_state;
11967 crtc_state->ddi_pll_sel = ddi_pll_sel;
11968 }
11969
11970 static int
11971 intel_modeset_pipe_config(struct drm_crtc *crtc,
11972 struct drm_atomic_state *state)
11973 {
11974 struct drm_crtc_state *crtc_state;
11975 struct intel_crtc_state *pipe_config;
11976 struct intel_encoder *encoder;
11977 struct drm_connector *connector;
11978 struct drm_connector_state *connector_state;
11979 int base_bpp, ret = -EINVAL;
11980 int i;
11981 bool retry = true;
11982
11983 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11984 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11985 return -EINVAL;
11986 }
11987
11988 if (!check_digital_port_conflicts(state)) {
11989 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11990 return -EINVAL;
11991 }
11992
11993 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
11994 if (WARN_ON(!crtc_state))
11995 return -EINVAL;
11996
11997 pipe_config = to_intel_crtc_state(crtc_state);
11998
11999 /*
12000 * XXX: Add all connectors to make the crtc state match the encoders.
12001 */
12002 if (!needs_modeset(&pipe_config->base)) {
12003 ret = drm_atomic_add_affected_connectors(state, crtc);
12004 if (ret)
12005 return ret;
12006 }
12007
12008 clear_intel_crtc_state(pipe_config);
12009
12010 pipe_config->cpu_transcoder =
12011 (enum transcoder) to_intel_crtc(crtc)->pipe;
12012
12013 /*
12014 * Sanitize sync polarity flags based on requested ones. If neither
12015 * positive or negative polarity is requested, treat this as meaning
12016 * negative polarity.
12017 */
12018 if (!(pipe_config->base.adjusted_mode.flags &
12019 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12020 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12021
12022 if (!(pipe_config->base.adjusted_mode.flags &
12023 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12024 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12025
12026 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12027 * plane pixel format and any sink constraints into account. Returns the
12028 * source plane bpp so that dithering can be selected on mismatches
12029 * after encoders and crtc also have had their say. */
12030 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12031 pipe_config);
12032 if (base_bpp < 0)
12033 goto fail;
12034
12035 /*
12036 * Determine the real pipe dimensions. Note that stereo modes can
12037 * increase the actual pipe size due to the frame doubling and
12038 * insertion of additional space for blanks between the frame. This
12039 * is stored in the crtc timings. We use the requested mode to do this
12040 * computation to clearly distinguish it from the adjusted mode, which
12041 * can be changed by the connectors in the below retry loop.
12042 */
12043 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12044 &pipe_config->pipe_src_w,
12045 &pipe_config->pipe_src_h);
12046
12047 encoder_retry:
12048 /* Ensure the port clock defaults are reset when retrying. */
12049 pipe_config->port_clock = 0;
12050 pipe_config->pixel_multiplier = 1;
12051
12052 /* Fill in default crtc timings, allow encoders to overwrite them. */
12053 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12054 CRTC_STEREO_DOUBLE);
12055
12056 /* Pass our mode to the connectors and the CRTC to give them a chance to
12057 * adjust it according to limitations or connector properties, and also
12058 * a chance to reject the mode entirely.
12059 */
12060 for_each_connector_in_state(state, connector, connector_state, i) {
12061 if (connector_state->crtc != crtc)
12062 continue;
12063
12064 encoder = to_intel_encoder(connector_state->best_encoder);
12065
12066 if (!(encoder->compute_config(encoder, pipe_config))) {
12067 DRM_DEBUG_KMS("Encoder config failure\n");
12068 goto fail;
12069 }
12070 }
12071
12072 /* Set default port clock if not overwritten by the encoder. Needs to be
12073 * done afterwards in case the encoder adjusts the mode. */
12074 if (!pipe_config->port_clock)
12075 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12076 * pipe_config->pixel_multiplier;
12077
12078 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12079 if (ret < 0) {
12080 DRM_DEBUG_KMS("CRTC fixup failed\n");
12081 goto fail;
12082 }
12083
12084 if (ret == RETRY) {
12085 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12086 ret = -EINVAL;
12087 goto fail;
12088 }
12089
12090 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12091 retry = false;
12092 goto encoder_retry;
12093 }
12094
12095 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12096 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12097 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12098
12099 /* Check if we need to force a modeset */
12100 if (pipe_config->has_audio !=
12101 to_intel_crtc_state(crtc->state)->has_audio) {
12102 pipe_config->base.mode_changed = true;
12103 ret = drm_atomic_add_affected_planes(state, crtc);
12104 }
12105
12106 /*
12107 * Note we have an issue here with infoframes: current code
12108 * only updates them on the full mode set path per hw
12109 * requirements. So here we should be checking for any
12110 * required changes and forcing a mode set.
12111 */
12112 fail:
12113 return ret;
12114 }
12115
12116 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12117 {
12118 struct drm_encoder *encoder;
12119 struct drm_device *dev = crtc->dev;
12120
12121 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12122 if (encoder->crtc == crtc)
12123 return true;
12124
12125 return false;
12126 }
12127
12128 static void
12129 intel_modeset_update_state(struct drm_atomic_state *state)
12130 {
12131 struct drm_device *dev = state->dev;
12132 struct intel_encoder *intel_encoder;
12133 struct drm_crtc *crtc;
12134 struct drm_crtc_state *crtc_state;
12135 struct drm_connector *connector;
12136
12137 intel_shared_dpll_commit(state);
12138
12139 for_each_intel_encoder(dev, intel_encoder) {
12140 if (!intel_encoder->base.crtc)
12141 continue;
12142
12143 crtc = intel_encoder->base.crtc;
12144 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12145 if (!crtc_state || !needs_modeset(crtc->state))
12146 continue;
12147
12148 intel_encoder->connectors_active = false;
12149 }
12150
12151 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12152
12153 /* Double check state. */
12154 for_each_crtc(dev, crtc) {
12155 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12156
12157 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12158
12159 /* Update hwmode for vblank functions */
12160 if (crtc->state->active)
12161 crtc->hwmode = crtc->state->adjusted_mode;
12162 else
12163 crtc->hwmode.crtc_clock = 0;
12164 }
12165
12166 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12167 if (!connector->encoder || !connector->encoder->crtc)
12168 continue;
12169
12170 crtc = connector->encoder->crtc;
12171 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12172 if (!crtc_state || !needs_modeset(crtc->state))
12173 continue;
12174
12175 if (crtc->state->active) {
12176 struct drm_property *dpms_property =
12177 dev->mode_config.dpms_property;
12178
12179 connector->dpms = DRM_MODE_DPMS_ON;
12180 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12181
12182 intel_encoder = to_intel_encoder(connector->encoder);
12183 intel_encoder->connectors_active = true;
12184 } else
12185 connector->dpms = DRM_MODE_DPMS_OFF;
12186 }
12187 }
12188
12189 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12190 {
12191 int diff;
12192
12193 if (clock1 == clock2)
12194 return true;
12195
12196 if (!clock1 || !clock2)
12197 return false;
12198
12199 diff = abs(clock1 - clock2);
12200
12201 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12202 return true;
12203
12204 return false;
12205 }
12206
12207 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12208 list_for_each_entry((intel_crtc), \
12209 &(dev)->mode_config.crtc_list, \
12210 base.head) \
12211 if (mask & (1 <<(intel_crtc)->pipe))
12212
12213 static bool
12214 intel_pipe_config_compare(struct drm_device *dev,
12215 struct intel_crtc_state *current_config,
12216 struct intel_crtc_state *pipe_config)
12217 {
12218 #define PIPE_CONF_CHECK_X(name) \
12219 if (current_config->name != pipe_config->name) { \
12220 DRM_ERROR("mismatch in " #name " " \
12221 "(expected 0x%08x, found 0x%08x)\n", \
12222 current_config->name, \
12223 pipe_config->name); \
12224 return false; \
12225 }
12226
12227 #define PIPE_CONF_CHECK_I(name) \
12228 if (current_config->name != pipe_config->name) { \
12229 DRM_ERROR("mismatch in " #name " " \
12230 "(expected %i, found %i)\n", \
12231 current_config->name, \
12232 pipe_config->name); \
12233 return false; \
12234 }
12235
12236 /* This is required for BDW+ where there is only one set of registers for
12237 * switching between high and low RR.
12238 * This macro can be used whenever a comparison has to be made between one
12239 * hw state and multiple sw state variables.
12240 */
12241 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12242 if ((current_config->name != pipe_config->name) && \
12243 (current_config->alt_name != pipe_config->name)) { \
12244 DRM_ERROR("mismatch in " #name " " \
12245 "(expected %i or %i, found %i)\n", \
12246 current_config->name, \
12247 current_config->alt_name, \
12248 pipe_config->name); \
12249 return false; \
12250 }
12251
12252 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12253 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12254 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12255 "(expected %i, found %i)\n", \
12256 current_config->name & (mask), \
12257 pipe_config->name & (mask)); \
12258 return false; \
12259 }
12260
12261 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12262 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12263 DRM_ERROR("mismatch in " #name " " \
12264 "(expected %i, found %i)\n", \
12265 current_config->name, \
12266 pipe_config->name); \
12267 return false; \
12268 }
12269
12270 #define PIPE_CONF_QUIRK(quirk) \
12271 ((current_config->quirks | pipe_config->quirks) & (quirk))
12272
12273 PIPE_CONF_CHECK_I(cpu_transcoder);
12274
12275 PIPE_CONF_CHECK_I(has_pch_encoder);
12276 PIPE_CONF_CHECK_I(fdi_lanes);
12277 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12278 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12279 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12280 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12281 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12282
12283 PIPE_CONF_CHECK_I(has_dp_encoder);
12284
12285 if (INTEL_INFO(dev)->gen < 8) {
12286 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12287 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12288 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12289 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12290 PIPE_CONF_CHECK_I(dp_m_n.tu);
12291
12292 if (current_config->has_drrs) {
12293 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12294 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12295 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12296 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12297 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12298 }
12299 } else {
12300 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12301 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12302 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12303 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12304 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12305 }
12306
12307 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12308 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12309 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12310 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12311 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12312 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12313
12314 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12315 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12316 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12317 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12318 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12319 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12320
12321 PIPE_CONF_CHECK_I(pixel_multiplier);
12322 PIPE_CONF_CHECK_I(has_hdmi_sink);
12323 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12324 IS_VALLEYVIEW(dev))
12325 PIPE_CONF_CHECK_I(limited_color_range);
12326 PIPE_CONF_CHECK_I(has_infoframe);
12327
12328 PIPE_CONF_CHECK_I(has_audio);
12329
12330 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12331 DRM_MODE_FLAG_INTERLACE);
12332
12333 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12334 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12335 DRM_MODE_FLAG_PHSYNC);
12336 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12337 DRM_MODE_FLAG_NHSYNC);
12338 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12339 DRM_MODE_FLAG_PVSYNC);
12340 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12341 DRM_MODE_FLAG_NVSYNC);
12342 }
12343
12344 PIPE_CONF_CHECK_I(pipe_src_w);
12345 PIPE_CONF_CHECK_I(pipe_src_h);
12346
12347 /*
12348 * FIXME: BIOS likes to set up a cloned config with lvds+external
12349 * screen. Since we don't yet re-compute the pipe config when moving
12350 * just the lvds port away to another pipe the sw tracking won't match.
12351 *
12352 * Proper atomic modesets with recomputed global state will fix this.
12353 * Until then just don't check gmch state for inherited modes.
12354 */
12355 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12356 PIPE_CONF_CHECK_I(gmch_pfit.control);
12357 /* pfit ratios are autocomputed by the hw on gen4+ */
12358 if (INTEL_INFO(dev)->gen < 4)
12359 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12360 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12361 }
12362
12363 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12364 if (current_config->pch_pfit.enabled) {
12365 PIPE_CONF_CHECK_I(pch_pfit.pos);
12366 PIPE_CONF_CHECK_I(pch_pfit.size);
12367 }
12368
12369 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12370
12371 /* BDW+ don't expose a synchronous way to read the state */
12372 if (IS_HASWELL(dev))
12373 PIPE_CONF_CHECK_I(ips_enabled);
12374
12375 PIPE_CONF_CHECK_I(double_wide);
12376
12377 PIPE_CONF_CHECK_X(ddi_pll_sel);
12378
12379 PIPE_CONF_CHECK_I(shared_dpll);
12380 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12381 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12382 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12383 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12384 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12385 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12386 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12387 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12388
12389 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12390 PIPE_CONF_CHECK_I(pipe_bpp);
12391
12392 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12393 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12394
12395 #undef PIPE_CONF_CHECK_X
12396 #undef PIPE_CONF_CHECK_I
12397 #undef PIPE_CONF_CHECK_I_ALT
12398 #undef PIPE_CONF_CHECK_FLAGS
12399 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12400 #undef PIPE_CONF_QUIRK
12401
12402 return true;
12403 }
12404
12405 static void check_wm_state(struct drm_device *dev)
12406 {
12407 struct drm_i915_private *dev_priv = dev->dev_private;
12408 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12409 struct intel_crtc *intel_crtc;
12410 int plane;
12411
12412 if (INTEL_INFO(dev)->gen < 9)
12413 return;
12414
12415 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12416 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12417
12418 for_each_intel_crtc(dev, intel_crtc) {
12419 struct skl_ddb_entry *hw_entry, *sw_entry;
12420 const enum pipe pipe = intel_crtc->pipe;
12421
12422 if (!intel_crtc->active)
12423 continue;
12424
12425 /* planes */
12426 for_each_plane(dev_priv, pipe, plane) {
12427 hw_entry = &hw_ddb.plane[pipe][plane];
12428 sw_entry = &sw_ddb->plane[pipe][plane];
12429
12430 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12431 continue;
12432
12433 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12434 "(expected (%u,%u), found (%u,%u))\n",
12435 pipe_name(pipe), plane + 1,
12436 sw_entry->start, sw_entry->end,
12437 hw_entry->start, hw_entry->end);
12438 }
12439
12440 /* cursor */
12441 hw_entry = &hw_ddb.cursor[pipe];
12442 sw_entry = &sw_ddb->cursor[pipe];
12443
12444 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12445 continue;
12446
12447 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12448 "(expected (%u,%u), found (%u,%u))\n",
12449 pipe_name(pipe),
12450 sw_entry->start, sw_entry->end,
12451 hw_entry->start, hw_entry->end);
12452 }
12453 }
12454
12455 static void
12456 check_connector_state(struct drm_device *dev)
12457 {
12458 struct intel_connector *connector;
12459
12460 for_each_intel_connector(dev, connector) {
12461 struct drm_encoder *encoder = connector->base.encoder;
12462 struct drm_connector_state *state = connector->base.state;
12463
12464 /* This also checks the encoder/connector hw state with the
12465 * ->get_hw_state callbacks. */
12466 intel_connector_check_state(connector);
12467
12468 I915_STATE_WARN(state->best_encoder != encoder,
12469 "connector's staged encoder doesn't match current encoder\n");
12470 }
12471 }
12472
12473 static void
12474 check_encoder_state(struct drm_device *dev)
12475 {
12476 struct intel_encoder *encoder;
12477 struct intel_connector *connector;
12478
12479 for_each_intel_encoder(dev, encoder) {
12480 bool enabled = false;
12481 bool active = false;
12482 enum pipe pipe, tracked_pipe;
12483
12484 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12485 encoder->base.base.id,
12486 encoder->base.name);
12487
12488 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12489 "encoder's active_connectors set, but no crtc\n");
12490
12491 for_each_intel_connector(dev, connector) {
12492 if (connector->base.encoder != &encoder->base)
12493 continue;
12494 enabled = true;
12495 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12496 active = true;
12497
12498 I915_STATE_WARN(connector->base.state->crtc != encoder->base.crtc,
12499 "encoder's stage crtc doesn't match current crtc\n");
12500 }
12501 /*
12502 * for MST connectors if we unplug the connector is gone
12503 * away but the encoder is still connected to a crtc
12504 * until a modeset happens in response to the hotplug.
12505 */
12506 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12507 continue;
12508
12509 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12510 "encoder's enabled state mismatch "
12511 "(expected %i, found %i)\n",
12512 !!encoder->base.crtc, enabled);
12513 I915_STATE_WARN(active && !encoder->base.crtc,
12514 "active encoder with no crtc\n");
12515
12516 I915_STATE_WARN(encoder->connectors_active != active,
12517 "encoder's computed active state doesn't match tracked active state "
12518 "(expected %i, found %i)\n", active, encoder->connectors_active);
12519
12520 active = encoder->get_hw_state(encoder, &pipe);
12521 I915_STATE_WARN(active != encoder->connectors_active,
12522 "encoder's hw state doesn't match sw tracking "
12523 "(expected %i, found %i)\n",
12524 encoder->connectors_active, active);
12525
12526 if (!encoder->base.crtc)
12527 continue;
12528
12529 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12530 I915_STATE_WARN(active && pipe != tracked_pipe,
12531 "active encoder's pipe doesn't match"
12532 "(expected %i, found %i)\n",
12533 tracked_pipe, pipe);
12534
12535 }
12536 }
12537
12538 static void
12539 check_crtc_state(struct drm_device *dev)
12540 {
12541 struct drm_i915_private *dev_priv = dev->dev_private;
12542 struct intel_crtc *crtc;
12543 struct intel_encoder *encoder;
12544 struct intel_crtc_state pipe_config;
12545
12546 for_each_intel_crtc(dev, crtc) {
12547 bool enabled = false;
12548 bool active = false;
12549
12550 memset(&pipe_config, 0, sizeof(pipe_config));
12551
12552 DRM_DEBUG_KMS("[CRTC:%d]\n",
12553 crtc->base.base.id);
12554
12555 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12556 "active crtc, but not enabled in sw tracking\n");
12557
12558 for_each_intel_encoder(dev, encoder) {
12559 if (encoder->base.crtc != &crtc->base)
12560 continue;
12561 enabled = true;
12562 if (encoder->connectors_active)
12563 active = true;
12564 }
12565
12566 I915_STATE_WARN(active != crtc->active,
12567 "crtc's computed active state doesn't match tracked active state "
12568 "(expected %i, found %i)\n", active, crtc->active);
12569 I915_STATE_WARN(enabled != crtc->base.state->enable,
12570 "crtc's computed enabled state doesn't match tracked enabled state "
12571 "(expected %i, found %i)\n", enabled,
12572 crtc->base.state->enable);
12573
12574 active = dev_priv->display.get_pipe_config(crtc,
12575 &pipe_config);
12576
12577 /* hw state is inconsistent with the pipe quirk */
12578 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12579 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12580 active = crtc->active;
12581
12582 for_each_intel_encoder(dev, encoder) {
12583 enum pipe pipe;
12584 if (encoder->base.crtc != &crtc->base)
12585 continue;
12586 if (encoder->get_hw_state(encoder, &pipe))
12587 encoder->get_config(encoder, &pipe_config);
12588 }
12589
12590 I915_STATE_WARN(crtc->active != active,
12591 "crtc active state doesn't match with hw state "
12592 "(expected %i, found %i)\n", crtc->active, active);
12593
12594 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12595 "transitional active state does not match atomic hw state "
12596 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12597
12598 if (active &&
12599 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12600 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12601 intel_dump_pipe_config(crtc, &pipe_config,
12602 "[hw state]");
12603 intel_dump_pipe_config(crtc, crtc->config,
12604 "[sw state]");
12605 }
12606 }
12607 }
12608
12609 static void
12610 check_shared_dpll_state(struct drm_device *dev)
12611 {
12612 struct drm_i915_private *dev_priv = dev->dev_private;
12613 struct intel_crtc *crtc;
12614 struct intel_dpll_hw_state dpll_hw_state;
12615 int i;
12616
12617 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12618 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12619 int enabled_crtcs = 0, active_crtcs = 0;
12620 bool active;
12621
12622 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12623
12624 DRM_DEBUG_KMS("%s\n", pll->name);
12625
12626 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12627
12628 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12629 "more active pll users than references: %i vs %i\n",
12630 pll->active, hweight32(pll->config.crtc_mask));
12631 I915_STATE_WARN(pll->active && !pll->on,
12632 "pll in active use but not on in sw tracking\n");
12633 I915_STATE_WARN(pll->on && !pll->active,
12634 "pll in on but not on in use in sw tracking\n");
12635 I915_STATE_WARN(pll->on != active,
12636 "pll on state mismatch (expected %i, found %i)\n",
12637 pll->on, active);
12638
12639 for_each_intel_crtc(dev, crtc) {
12640 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12641 enabled_crtcs++;
12642 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12643 active_crtcs++;
12644 }
12645 I915_STATE_WARN(pll->active != active_crtcs,
12646 "pll active crtcs mismatch (expected %i, found %i)\n",
12647 pll->active, active_crtcs);
12648 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12649 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12650 hweight32(pll->config.crtc_mask), enabled_crtcs);
12651
12652 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12653 sizeof(dpll_hw_state)),
12654 "pll hw state mismatch\n");
12655 }
12656 }
12657
12658 void
12659 intel_modeset_check_state(struct drm_device *dev)
12660 {
12661 check_wm_state(dev);
12662 check_connector_state(dev);
12663 check_encoder_state(dev);
12664 check_crtc_state(dev);
12665 check_shared_dpll_state(dev);
12666 }
12667
12668 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12669 int dotclock)
12670 {
12671 /*
12672 * FDI already provided one idea for the dotclock.
12673 * Yell if the encoder disagrees.
12674 */
12675 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12676 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12677 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12678 }
12679
12680 static void update_scanline_offset(struct intel_crtc *crtc)
12681 {
12682 struct drm_device *dev = crtc->base.dev;
12683
12684 /*
12685 * The scanline counter increments at the leading edge of hsync.
12686 *
12687 * On most platforms it starts counting from vtotal-1 on the
12688 * first active line. That means the scanline counter value is
12689 * always one less than what we would expect. Ie. just after
12690 * start of vblank, which also occurs at start of hsync (on the
12691 * last active line), the scanline counter will read vblank_start-1.
12692 *
12693 * On gen2 the scanline counter starts counting from 1 instead
12694 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12695 * to keep the value positive), instead of adding one.
12696 *
12697 * On HSW+ the behaviour of the scanline counter depends on the output
12698 * type. For DP ports it behaves like most other platforms, but on HDMI
12699 * there's an extra 1 line difference. So we need to add two instead of
12700 * one to the value.
12701 */
12702 if (IS_GEN2(dev)) {
12703 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12704 int vtotal;
12705
12706 vtotal = mode->crtc_vtotal;
12707 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12708 vtotal /= 2;
12709
12710 crtc->scanline_offset = vtotal - 1;
12711 } else if (HAS_DDI(dev) &&
12712 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12713 crtc->scanline_offset = 2;
12714 } else
12715 crtc->scanline_offset = 1;
12716 }
12717
12718 static int intel_modeset_setup_plls(struct drm_atomic_state *state)
12719 {
12720 struct drm_device *dev = state->dev;
12721 struct drm_i915_private *dev_priv = to_i915(dev);
12722 unsigned clear_pipes = 0;
12723 struct intel_crtc *intel_crtc;
12724 struct intel_crtc_state *intel_crtc_state;
12725 struct drm_crtc *crtc;
12726 struct drm_crtc_state *crtc_state;
12727 int ret = 0;
12728 int i;
12729
12730 if (!dev_priv->display.crtc_compute_clock)
12731 return 0;
12732
12733 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12734 intel_crtc = to_intel_crtc(crtc);
12735 intel_crtc_state = to_intel_crtc_state(crtc_state);
12736
12737 if (needs_modeset(crtc_state)) {
12738 clear_pipes |= 1 << intel_crtc->pipe;
12739 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12740 }
12741 }
12742
12743 if (clear_pipes) {
12744 struct intel_shared_dpll_config *shared_dpll =
12745 intel_atomic_get_shared_dpll_state(state);
12746
12747 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12748 shared_dpll[i].crtc_mask &= ~clear_pipes;
12749 }
12750
12751 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12752 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12753 continue;
12754
12755 intel_crtc = to_intel_crtc(crtc);
12756 intel_crtc_state = to_intel_crtc_state(crtc_state);
12757
12758 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12759 intel_crtc_state);
12760 if (ret)
12761 return ret;
12762 }
12763
12764 return ret;
12765 }
12766
12767 /*
12768 * This implements the workaround described in the "notes" section of the mode
12769 * set sequence documentation. When going from no pipes or single pipe to
12770 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12771 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12772 */
12773 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12774 {
12775 struct drm_crtc_state *crtc_state;
12776 struct intel_crtc *intel_crtc;
12777 struct drm_crtc *crtc;
12778 struct intel_crtc_state *first_crtc_state = NULL;
12779 struct intel_crtc_state *other_crtc_state = NULL;
12780 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12781 int i;
12782
12783 /* look at all crtc's that are going to be enabled in during modeset */
12784 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12785 intel_crtc = to_intel_crtc(crtc);
12786
12787 if (!crtc_state->active || !needs_modeset(crtc_state))
12788 continue;
12789
12790 if (first_crtc_state) {
12791 other_crtc_state = to_intel_crtc_state(crtc_state);
12792 break;
12793 } else {
12794 first_crtc_state = to_intel_crtc_state(crtc_state);
12795 first_pipe = intel_crtc->pipe;
12796 }
12797 }
12798
12799 /* No workaround needed? */
12800 if (!first_crtc_state)
12801 return 0;
12802
12803 /* w/a possibly needed, check how many crtc's are already enabled. */
12804 for_each_intel_crtc(state->dev, intel_crtc) {
12805 struct intel_crtc_state *pipe_config;
12806
12807 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12808 if (IS_ERR(pipe_config))
12809 return PTR_ERR(pipe_config);
12810
12811 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12812
12813 if (!pipe_config->base.active ||
12814 needs_modeset(&pipe_config->base))
12815 continue;
12816
12817 /* 2 or more enabled crtcs means no need for w/a */
12818 if (enabled_pipe != INVALID_PIPE)
12819 return 0;
12820
12821 enabled_pipe = intel_crtc->pipe;
12822 }
12823
12824 if (enabled_pipe != INVALID_PIPE)
12825 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12826 else if (other_crtc_state)
12827 other_crtc_state->hsw_workaround_pipe = first_pipe;
12828
12829 return 0;
12830 }
12831
12832 /* Code that should eventually be part of atomic_check() */
12833 static int intel_modeset_checks(struct drm_atomic_state *state)
12834 {
12835 struct drm_device *dev = state->dev;
12836 int ret;
12837
12838 /*
12839 * See if the config requires any additional preparation, e.g.
12840 * to adjust global state with pipes off. We need to do this
12841 * here so we can get the modeset_pipe updated config for the new
12842 * mode set on this crtc. For other crtcs we need to use the
12843 * adjusted_mode bits in the crtc directly.
12844 */
12845 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12846 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12847 ret = valleyview_modeset_global_pipes(state);
12848 else
12849 ret = broadwell_modeset_global_pipes(state);
12850
12851 if (ret)
12852 return ret;
12853 }
12854
12855 ret = intel_modeset_setup_plls(state);
12856 if (ret)
12857 return ret;
12858
12859 if (IS_HASWELL(dev))
12860 ret = haswell_mode_set_planes_workaround(state);
12861
12862 return ret;
12863 }
12864
12865 static int
12866 intel_modeset_compute_config(struct drm_atomic_state *state)
12867 {
12868 struct drm_crtc *crtc;
12869 struct drm_crtc_state *crtc_state;
12870 int ret, i;
12871
12872 ret = drm_atomic_helper_check_modeset(state->dev, state);
12873 if (ret)
12874 return ret;
12875
12876 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12877 if (!crtc_state->enable &&
12878 WARN_ON(crtc_state->active))
12879 crtc_state->active = false;
12880
12881 if (!crtc_state->enable)
12882 continue;
12883
12884 ret = intel_modeset_pipe_config(crtc, state);
12885 if (ret)
12886 return ret;
12887
12888 intel_dump_pipe_config(to_intel_crtc(crtc),
12889 to_intel_crtc_state(crtc_state),
12890 "[modeset]");
12891 }
12892
12893 ret = intel_modeset_checks(state);
12894 if (ret)
12895 return ret;
12896
12897 return drm_atomic_helper_check_planes(state->dev, state);
12898 }
12899
12900 static int __intel_set_mode(struct drm_atomic_state *state)
12901 {
12902 struct drm_device *dev = state->dev;
12903 struct drm_i915_private *dev_priv = dev->dev_private;
12904 struct drm_crtc *crtc;
12905 struct drm_crtc_state *crtc_state;
12906 int ret = 0;
12907 int i;
12908
12909 ret = drm_atomic_helper_prepare_planes(dev, state);
12910 if (ret)
12911 return ret;
12912
12913 drm_atomic_helper_swap_state(dev, state);
12914
12915 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12916 if (!needs_modeset(crtc->state) || !crtc_state->active)
12917 continue;
12918
12919 intel_crtc_disable_planes(crtc);
12920 dev_priv->display.crtc_disable(crtc);
12921 }
12922
12923 /* Only after disabling all output pipelines that will be changed can we
12924 * update the the output configuration. */
12925 intel_modeset_update_state(state);
12926
12927 /* The state has been swaped above, so state actually contains the
12928 * old state now. */
12929
12930 modeset_update_crtc_power_domains(state);
12931
12932 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12933 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12934 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
12935
12936 if (!needs_modeset(crtc->state) || !crtc->state->active)
12937 continue;
12938
12939 update_scanline_offset(to_intel_crtc(crtc));
12940
12941 dev_priv->display.crtc_enable(crtc);
12942 intel_crtc_enable_planes(crtc);
12943 }
12944
12945 /* FIXME: add subpixel order */
12946
12947 drm_atomic_helper_cleanup_planes(dev, state);
12948
12949 drm_atomic_state_free(state);
12950
12951 return 0;
12952 }
12953
12954 static int intel_set_mode_checked(struct drm_atomic_state *state)
12955 {
12956 struct drm_device *dev = state->dev;
12957 int ret;
12958
12959 ret = __intel_set_mode(state);
12960 if (ret == 0)
12961 intel_modeset_check_state(dev);
12962
12963 return ret;
12964 }
12965
12966 static int intel_set_mode(struct drm_atomic_state *state)
12967 {
12968 int ret;
12969
12970 ret = intel_modeset_compute_config(state);
12971 if (ret)
12972 return ret;
12973
12974 return intel_set_mode_checked(state);
12975 }
12976
12977 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12978 {
12979 struct drm_device *dev = crtc->dev;
12980 struct drm_atomic_state *state;
12981 struct intel_crtc *intel_crtc;
12982 struct intel_encoder *encoder;
12983 struct intel_connector *connector;
12984 struct drm_connector_state *connector_state;
12985 struct intel_crtc_state *crtc_state;
12986 int ret;
12987
12988 state = drm_atomic_state_alloc(dev);
12989 if (!state) {
12990 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12991 crtc->base.id);
12992 return;
12993 }
12994
12995 state->acquire_ctx = dev->mode_config.acquire_ctx;
12996
12997 /* The force restore path in the HW readout code relies on the staged
12998 * config still keeping the user requested config while the actual
12999 * state has been overwritten by the configuration read from HW. We
13000 * need to copy the staged config to the atomic state, otherwise the
13001 * mode set will just reapply the state the HW is already in. */
13002 for_each_intel_encoder(dev, encoder) {
13003 if (encoder->base.crtc != crtc)
13004 continue;
13005
13006 for_each_intel_connector(dev, connector) {
13007 if (connector->base.state->best_encoder != &encoder->base)
13008 continue;
13009
13010 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13011 if (IS_ERR(connector_state)) {
13012 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13013 connector->base.base.id,
13014 connector->base.name,
13015 PTR_ERR(connector_state));
13016 continue;
13017 }
13018
13019 connector_state->crtc = crtc;
13020 }
13021 }
13022
13023 for_each_intel_crtc(dev, intel_crtc) {
13024 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13025 if (IS_ERR(crtc_state)) {
13026 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13027 intel_crtc->base.base.id,
13028 PTR_ERR(crtc_state));
13029 continue;
13030 }
13031
13032 if (&intel_crtc->base == crtc)
13033 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13034 }
13035
13036 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13037 crtc->primary->fb, crtc->x, crtc->y);
13038
13039 ret = intel_set_mode(state);
13040 if (ret)
13041 drm_atomic_state_free(state);
13042 }
13043
13044 #undef for_each_intel_crtc_masked
13045
13046 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13047 struct drm_mode_set *set)
13048 {
13049 int ro;
13050
13051 for (ro = 0; ro < set->num_connectors; ro++)
13052 if (set->connectors[ro] == &connector->base)
13053 return true;
13054
13055 return false;
13056 }
13057
13058 static int
13059 intel_modeset_stage_output_state(struct drm_device *dev,
13060 struct drm_mode_set *set,
13061 struct drm_atomic_state *state)
13062 {
13063 struct intel_connector *connector;
13064 struct drm_connector *drm_connector;
13065 struct drm_connector_state *connector_state;
13066 struct drm_crtc *crtc;
13067 struct drm_crtc_state *crtc_state;
13068 int i, ret;
13069
13070 /* The upper layers ensure that we either disable a crtc or have a list
13071 * of connectors. For paranoia, double-check this. */
13072 WARN_ON(!set->fb && (set->num_connectors != 0));
13073 WARN_ON(set->fb && (set->num_connectors == 0));
13074
13075 for_each_intel_connector(dev, connector) {
13076 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13077
13078 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13079 continue;
13080
13081 connector_state =
13082 drm_atomic_get_connector_state(state, &connector->base);
13083 if (IS_ERR(connector_state))
13084 return PTR_ERR(connector_state);
13085
13086 if (in_mode_set) {
13087 int pipe = to_intel_crtc(set->crtc)->pipe;
13088 connector_state->best_encoder =
13089 &intel_find_encoder(connector, pipe)->base;
13090 }
13091
13092 if (connector->base.state->crtc != set->crtc)
13093 continue;
13094
13095 /* If we disable the crtc, disable all its connectors. Also, if
13096 * the connector is on the changing crtc but not on the new
13097 * connector list, disable it. */
13098 if (!set->fb || !in_mode_set) {
13099 connector_state->best_encoder = NULL;
13100
13101 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13102 connector->base.base.id,
13103 connector->base.name);
13104 }
13105 }
13106 /* connector->new_encoder is now updated for all connectors. */
13107
13108 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13109 connector = to_intel_connector(drm_connector);
13110
13111 if (!connector_state->best_encoder) {
13112 ret = drm_atomic_set_crtc_for_connector(connector_state,
13113 NULL);
13114 if (ret)
13115 return ret;
13116
13117 continue;
13118 }
13119
13120 if (intel_connector_in_mode_set(connector, set)) {
13121 struct drm_crtc *crtc = connector->base.state->crtc;
13122
13123 /* If this connector was in a previous crtc, add it
13124 * to the state. We might need to disable it. */
13125 if (crtc) {
13126 crtc_state =
13127 drm_atomic_get_crtc_state(state, crtc);
13128 if (IS_ERR(crtc_state))
13129 return PTR_ERR(crtc_state);
13130 }
13131
13132 ret = drm_atomic_set_crtc_for_connector(connector_state,
13133 set->crtc);
13134 if (ret)
13135 return ret;
13136 }
13137
13138 /* Make sure the new CRTC will work with the encoder */
13139 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13140 connector_state->crtc)) {
13141 return -EINVAL;
13142 }
13143
13144 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13145 connector->base.base.id,
13146 connector->base.name,
13147 connector_state->crtc->base.id);
13148
13149 if (connector_state->best_encoder != &connector->encoder->base)
13150 connector->encoder =
13151 to_intel_encoder(connector_state->best_encoder);
13152 }
13153
13154 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13155 bool has_connectors;
13156
13157 ret = drm_atomic_add_affected_connectors(state, crtc);
13158 if (ret)
13159 return ret;
13160
13161 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13162 if (has_connectors != crtc_state->enable)
13163 crtc_state->enable =
13164 crtc_state->active = has_connectors;
13165 }
13166
13167 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13168 set->fb, set->x, set->y);
13169 if (ret)
13170 return ret;
13171
13172 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13173 if (IS_ERR(crtc_state))
13174 return PTR_ERR(crtc_state);
13175
13176 if (set->mode)
13177 drm_mode_copy(&crtc_state->mode, set->mode);
13178
13179 if (set->num_connectors)
13180 crtc_state->active = true;
13181
13182 return 0;
13183 }
13184
13185 static int intel_crtc_set_config(struct drm_mode_set *set)
13186 {
13187 struct drm_device *dev;
13188 struct drm_atomic_state *state = NULL;
13189 int ret;
13190
13191 BUG_ON(!set);
13192 BUG_ON(!set->crtc);
13193 BUG_ON(!set->crtc->helper_private);
13194
13195 /* Enforce sane interface api - has been abused by the fb helper. */
13196 BUG_ON(!set->mode && set->fb);
13197 BUG_ON(set->fb && set->num_connectors == 0);
13198
13199 if (set->fb) {
13200 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13201 set->crtc->base.id, set->fb->base.id,
13202 (int)set->num_connectors, set->x, set->y);
13203 } else {
13204 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13205 }
13206
13207 dev = set->crtc->dev;
13208
13209 state = drm_atomic_state_alloc(dev);
13210 if (!state)
13211 return -ENOMEM;
13212
13213 state->acquire_ctx = dev->mode_config.acquire_ctx;
13214
13215 ret = intel_modeset_stage_output_state(dev, set, state);
13216 if (ret)
13217 goto out;
13218
13219 ret = intel_modeset_compute_config(state);
13220 if (ret)
13221 goto out;
13222
13223 intel_update_pipe_size(to_intel_crtc(set->crtc));
13224
13225 ret = intel_set_mode_checked(state);
13226 if (ret) {
13227 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13228 set->crtc->base.id, ret);
13229 }
13230
13231 out:
13232 if (ret)
13233 drm_atomic_state_free(state);
13234 return ret;
13235 }
13236
13237 static const struct drm_crtc_funcs intel_crtc_funcs = {
13238 .gamma_set = intel_crtc_gamma_set,
13239 .set_config = intel_crtc_set_config,
13240 .destroy = intel_crtc_destroy,
13241 .page_flip = intel_crtc_page_flip,
13242 .atomic_duplicate_state = intel_crtc_duplicate_state,
13243 .atomic_destroy_state = intel_crtc_destroy_state,
13244 };
13245
13246 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13247 struct intel_shared_dpll *pll,
13248 struct intel_dpll_hw_state *hw_state)
13249 {
13250 uint32_t val;
13251
13252 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13253 return false;
13254
13255 val = I915_READ(PCH_DPLL(pll->id));
13256 hw_state->dpll = val;
13257 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13258 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13259
13260 return val & DPLL_VCO_ENABLE;
13261 }
13262
13263 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13264 struct intel_shared_dpll *pll)
13265 {
13266 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13267 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13268 }
13269
13270 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13271 struct intel_shared_dpll *pll)
13272 {
13273 /* PCH refclock must be enabled first */
13274 ibx_assert_pch_refclk_enabled(dev_priv);
13275
13276 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13277
13278 /* Wait for the clocks to stabilize. */
13279 POSTING_READ(PCH_DPLL(pll->id));
13280 udelay(150);
13281
13282 /* The pixel multiplier can only be updated once the
13283 * DPLL is enabled and the clocks are stable.
13284 *
13285 * So write it again.
13286 */
13287 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13288 POSTING_READ(PCH_DPLL(pll->id));
13289 udelay(200);
13290 }
13291
13292 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13293 struct intel_shared_dpll *pll)
13294 {
13295 struct drm_device *dev = dev_priv->dev;
13296 struct intel_crtc *crtc;
13297
13298 /* Make sure no transcoder isn't still depending on us. */
13299 for_each_intel_crtc(dev, crtc) {
13300 if (intel_crtc_to_shared_dpll(crtc) == pll)
13301 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13302 }
13303
13304 I915_WRITE(PCH_DPLL(pll->id), 0);
13305 POSTING_READ(PCH_DPLL(pll->id));
13306 udelay(200);
13307 }
13308
13309 static char *ibx_pch_dpll_names[] = {
13310 "PCH DPLL A",
13311 "PCH DPLL B",
13312 };
13313
13314 static void ibx_pch_dpll_init(struct drm_device *dev)
13315 {
13316 struct drm_i915_private *dev_priv = dev->dev_private;
13317 int i;
13318
13319 dev_priv->num_shared_dpll = 2;
13320
13321 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13322 dev_priv->shared_dplls[i].id = i;
13323 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13324 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13325 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13326 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13327 dev_priv->shared_dplls[i].get_hw_state =
13328 ibx_pch_dpll_get_hw_state;
13329 }
13330 }
13331
13332 static void intel_shared_dpll_init(struct drm_device *dev)
13333 {
13334 struct drm_i915_private *dev_priv = dev->dev_private;
13335
13336 intel_update_cdclk(dev);
13337
13338 if (HAS_DDI(dev))
13339 intel_ddi_pll_init(dev);
13340 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13341 ibx_pch_dpll_init(dev);
13342 else
13343 dev_priv->num_shared_dpll = 0;
13344
13345 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13346 }
13347
13348 /**
13349 * intel_wm_need_update - Check whether watermarks need updating
13350 * @plane: drm plane
13351 * @state: new plane state
13352 *
13353 * Check current plane state versus the new one to determine whether
13354 * watermarks need to be recalculated.
13355 *
13356 * Returns true or false.
13357 */
13358 bool intel_wm_need_update(struct drm_plane *plane,
13359 struct drm_plane_state *state)
13360 {
13361 /* Update watermarks on tiling changes. */
13362 if (!plane->state->fb || !state->fb ||
13363 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13364 plane->state->rotation != state->rotation)
13365 return true;
13366
13367 return false;
13368 }
13369
13370 /**
13371 * intel_prepare_plane_fb - Prepare fb for usage on plane
13372 * @plane: drm plane to prepare for
13373 * @fb: framebuffer to prepare for presentation
13374 *
13375 * Prepares a framebuffer for usage on a display plane. Generally this
13376 * involves pinning the underlying object and updating the frontbuffer tracking
13377 * bits. Some older platforms need special physical address handling for
13378 * cursor planes.
13379 *
13380 * Returns 0 on success, negative error code on failure.
13381 */
13382 int
13383 intel_prepare_plane_fb(struct drm_plane *plane,
13384 struct drm_framebuffer *fb,
13385 const struct drm_plane_state *new_state)
13386 {
13387 struct drm_device *dev = plane->dev;
13388 struct intel_plane *intel_plane = to_intel_plane(plane);
13389 enum pipe pipe = intel_plane->pipe;
13390 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13391 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13392 unsigned frontbuffer_bits = 0;
13393 int ret = 0;
13394
13395 if (!obj)
13396 return 0;
13397
13398 switch (plane->type) {
13399 case DRM_PLANE_TYPE_PRIMARY:
13400 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13401 break;
13402 case DRM_PLANE_TYPE_CURSOR:
13403 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13404 break;
13405 case DRM_PLANE_TYPE_OVERLAY:
13406 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13407 break;
13408 }
13409
13410 mutex_lock(&dev->struct_mutex);
13411
13412 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13413 INTEL_INFO(dev)->cursor_needs_physical) {
13414 int align = IS_I830(dev) ? 16 * 1024 : 256;
13415 ret = i915_gem_object_attach_phys(obj, align);
13416 if (ret)
13417 DRM_DEBUG_KMS("failed to attach phys object\n");
13418 } else {
13419 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13420 }
13421
13422 if (ret == 0)
13423 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13424
13425 mutex_unlock(&dev->struct_mutex);
13426
13427 return ret;
13428 }
13429
13430 /**
13431 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13432 * @plane: drm plane to clean up for
13433 * @fb: old framebuffer that was on plane
13434 *
13435 * Cleans up a framebuffer that has just been removed from a plane.
13436 */
13437 void
13438 intel_cleanup_plane_fb(struct drm_plane *plane,
13439 struct drm_framebuffer *fb,
13440 const struct drm_plane_state *old_state)
13441 {
13442 struct drm_device *dev = plane->dev;
13443 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13444
13445 if (WARN_ON(!obj))
13446 return;
13447
13448 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13449 !INTEL_INFO(dev)->cursor_needs_physical) {
13450 mutex_lock(&dev->struct_mutex);
13451 intel_unpin_fb_obj(fb, old_state);
13452 mutex_unlock(&dev->struct_mutex);
13453 }
13454 }
13455
13456 int
13457 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13458 {
13459 int max_scale;
13460 struct drm_device *dev;
13461 struct drm_i915_private *dev_priv;
13462 int crtc_clock, cdclk;
13463
13464 if (!intel_crtc || !crtc_state)
13465 return DRM_PLANE_HELPER_NO_SCALING;
13466
13467 dev = intel_crtc->base.dev;
13468 dev_priv = dev->dev_private;
13469 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13470 cdclk = dev_priv->display.get_display_clock_speed(dev);
13471
13472 if (!crtc_clock || !cdclk)
13473 return DRM_PLANE_HELPER_NO_SCALING;
13474
13475 /*
13476 * skl max scale is lower of:
13477 * close to 3 but not 3, -1 is for that purpose
13478 * or
13479 * cdclk/crtc_clock
13480 */
13481 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13482
13483 return max_scale;
13484 }
13485
13486 static int
13487 intel_check_primary_plane(struct drm_plane *plane,
13488 struct intel_plane_state *state)
13489 {
13490 struct drm_device *dev = plane->dev;
13491 struct drm_i915_private *dev_priv = dev->dev_private;
13492 struct drm_crtc *crtc = state->base.crtc;
13493 struct intel_crtc *intel_crtc;
13494 struct intel_crtc_state *crtc_state;
13495 struct drm_framebuffer *fb = state->base.fb;
13496 struct drm_rect *dest = &state->dst;
13497 struct drm_rect *src = &state->src;
13498 const struct drm_rect *clip = &state->clip;
13499 bool can_position = false;
13500 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13501 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13502 int ret;
13503
13504 crtc = crtc ? crtc : plane->crtc;
13505 intel_crtc = to_intel_crtc(crtc);
13506 crtc_state = state->base.state ?
13507 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13508
13509 if (INTEL_INFO(dev)->gen >= 9) {
13510 /* use scaler when colorkey is not required */
13511 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13512 min_scale = 1;
13513 max_scale = skl_max_scale(intel_crtc, crtc_state);
13514 }
13515 can_position = true;
13516 }
13517
13518 ret = drm_plane_helper_check_update(plane, crtc, fb,
13519 src, dest, clip,
13520 min_scale,
13521 max_scale,
13522 can_position, true,
13523 &state->visible);
13524 if (ret)
13525 return ret;
13526
13527 if (intel_crtc->active) {
13528 struct intel_plane_state *old_state =
13529 to_intel_plane_state(plane->state);
13530
13531 intel_crtc->atomic.wait_for_flips = true;
13532
13533 /*
13534 * FBC does not work on some platforms for rotated
13535 * planes, so disable it when rotation is not 0 and
13536 * update it when rotation is set back to 0.
13537 *
13538 * FIXME: This is redundant with the fbc update done in
13539 * the primary plane enable function except that that
13540 * one is done too late. We eventually need to unify
13541 * this.
13542 */
13543 if (state->visible &&
13544 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13545 dev_priv->fbc.crtc == intel_crtc &&
13546 state->base.rotation != BIT(DRM_ROTATE_0)) {
13547 intel_crtc->atomic.disable_fbc = true;
13548 }
13549
13550 if (state->visible && !old_state->visible) {
13551 /*
13552 * BDW signals flip done immediately if the plane
13553 * is disabled, even if the plane enable is already
13554 * armed to occur at the next vblank :(
13555 */
13556 if (IS_BROADWELL(dev))
13557 intel_crtc->atomic.wait_vblank = true;
13558
13559 if (crtc_state && !needs_modeset(&crtc_state->base))
13560 intel_crtc->atomic.post_enable_primary = true;
13561 }
13562
13563 if (!state->visible && old_state->visible &&
13564 crtc_state && !needs_modeset(&crtc_state->base))
13565 intel_crtc->atomic.pre_disable_primary = true;
13566
13567 intel_crtc->atomic.fb_bits |=
13568 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13569
13570 intel_crtc->atomic.update_fbc = true;
13571
13572 if (intel_wm_need_update(plane, &state->base))
13573 intel_crtc->atomic.update_wm = true;
13574 }
13575
13576 if (INTEL_INFO(dev)->gen >= 9) {
13577 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13578 to_intel_plane(plane), state, 0);
13579 if (ret)
13580 return ret;
13581 }
13582
13583 return 0;
13584 }
13585
13586 static void
13587 intel_commit_primary_plane(struct drm_plane *plane,
13588 struct intel_plane_state *state)
13589 {
13590 struct drm_crtc *crtc = state->base.crtc;
13591 struct drm_framebuffer *fb = state->base.fb;
13592 struct drm_device *dev = plane->dev;
13593 struct drm_i915_private *dev_priv = dev->dev_private;
13594 struct intel_crtc *intel_crtc;
13595 struct drm_rect *src = &state->src;
13596
13597 crtc = crtc ? crtc : plane->crtc;
13598 intel_crtc = to_intel_crtc(crtc);
13599
13600 plane->fb = fb;
13601 crtc->x = src->x1 >> 16;
13602 crtc->y = src->y1 >> 16;
13603
13604 if (intel_crtc->active) {
13605 if (state->visible)
13606 /* FIXME: kill this fastboot hack */
13607 intel_update_pipe_size(intel_crtc);
13608
13609 dev_priv->display.update_primary_plane(crtc, plane->fb,
13610 crtc->x, crtc->y);
13611 }
13612 }
13613
13614 static void
13615 intel_disable_primary_plane(struct drm_plane *plane,
13616 struct drm_crtc *crtc,
13617 bool force)
13618 {
13619 struct drm_device *dev = plane->dev;
13620 struct drm_i915_private *dev_priv = dev->dev_private;
13621
13622 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13623 }
13624
13625 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13626 {
13627 struct drm_device *dev = crtc->dev;
13628 struct drm_i915_private *dev_priv = dev->dev_private;
13629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13630 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
13631 struct intel_plane *intel_plane;
13632 struct drm_plane *p;
13633 unsigned fb_bits = 0;
13634
13635 /* Track fb's for any planes being disabled */
13636 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13637 intel_plane = to_intel_plane(p);
13638
13639 if (intel_crtc->atomic.disabled_planes &
13640 (1 << drm_plane_index(p))) {
13641 switch (p->type) {
13642 case DRM_PLANE_TYPE_PRIMARY:
13643 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13644 break;
13645 case DRM_PLANE_TYPE_CURSOR:
13646 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13647 break;
13648 case DRM_PLANE_TYPE_OVERLAY:
13649 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13650 break;
13651 }
13652
13653 mutex_lock(&dev->struct_mutex);
13654 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13655 mutex_unlock(&dev->struct_mutex);
13656 }
13657 }
13658
13659 if (intel_crtc->atomic.wait_for_flips)
13660 intel_crtc_wait_for_pending_flips(crtc);
13661
13662 if (intel_crtc->atomic.disable_fbc)
13663 intel_fbc_disable(dev);
13664
13665 if (intel_crtc->atomic.pre_disable_primary)
13666 intel_pre_disable_primary(crtc);
13667
13668 if (intel_crtc->atomic.update_wm)
13669 intel_update_watermarks(crtc);
13670
13671 intel_runtime_pm_get(dev_priv);
13672
13673 /* Perform vblank evasion around commit operation */
13674 if (crtc_state->active && !needs_modeset(crtc_state))
13675 intel_crtc->atomic.evade =
13676 intel_pipe_update_start(intel_crtc,
13677 &intel_crtc->atomic.start_vbl_count);
13678 }
13679
13680 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13681 {
13682 struct drm_device *dev = crtc->dev;
13683 struct drm_i915_private *dev_priv = dev->dev_private;
13684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13685 struct drm_plane *p;
13686
13687 if (intel_crtc->atomic.evade)
13688 intel_pipe_update_end(intel_crtc,
13689 intel_crtc->atomic.start_vbl_count);
13690
13691 intel_runtime_pm_put(dev_priv);
13692
13693 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13694 intel_wait_for_vblank(dev, intel_crtc->pipe);
13695
13696 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13697
13698 if (intel_crtc->atomic.update_fbc) {
13699 mutex_lock(&dev->struct_mutex);
13700 intel_fbc_update(dev);
13701 mutex_unlock(&dev->struct_mutex);
13702 }
13703
13704 if (intel_crtc->atomic.post_enable_primary)
13705 intel_post_enable_primary(crtc);
13706
13707 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13708 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13709 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13710 false, false);
13711
13712 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13713 }
13714
13715 /**
13716 * intel_plane_destroy - destroy a plane
13717 * @plane: plane to destroy
13718 *
13719 * Common destruction function for all types of planes (primary, cursor,
13720 * sprite).
13721 */
13722 void intel_plane_destroy(struct drm_plane *plane)
13723 {
13724 struct intel_plane *intel_plane = to_intel_plane(plane);
13725 drm_plane_cleanup(plane);
13726 kfree(intel_plane);
13727 }
13728
13729 const struct drm_plane_funcs intel_plane_funcs = {
13730 .update_plane = drm_atomic_helper_update_plane,
13731 .disable_plane = drm_atomic_helper_disable_plane,
13732 .destroy = intel_plane_destroy,
13733 .set_property = drm_atomic_helper_plane_set_property,
13734 .atomic_get_property = intel_plane_atomic_get_property,
13735 .atomic_set_property = intel_plane_atomic_set_property,
13736 .atomic_duplicate_state = intel_plane_duplicate_state,
13737 .atomic_destroy_state = intel_plane_destroy_state,
13738
13739 };
13740
13741 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13742 int pipe)
13743 {
13744 struct intel_plane *primary;
13745 struct intel_plane_state *state;
13746 const uint32_t *intel_primary_formats;
13747 int num_formats;
13748
13749 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13750 if (primary == NULL)
13751 return NULL;
13752
13753 state = intel_create_plane_state(&primary->base);
13754 if (!state) {
13755 kfree(primary);
13756 return NULL;
13757 }
13758 primary->base.state = &state->base;
13759
13760 primary->can_scale = false;
13761 primary->max_downscale = 1;
13762 if (INTEL_INFO(dev)->gen >= 9) {
13763 primary->can_scale = true;
13764 state->scaler_id = -1;
13765 }
13766 primary->pipe = pipe;
13767 primary->plane = pipe;
13768 primary->check_plane = intel_check_primary_plane;
13769 primary->commit_plane = intel_commit_primary_plane;
13770 primary->disable_plane = intel_disable_primary_plane;
13771 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13772 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13773 primary->plane = !pipe;
13774
13775 if (INTEL_INFO(dev)->gen >= 9) {
13776 intel_primary_formats = skl_primary_formats;
13777 num_formats = ARRAY_SIZE(skl_primary_formats);
13778 } else if (INTEL_INFO(dev)->gen >= 4) {
13779 intel_primary_formats = i965_primary_formats;
13780 num_formats = ARRAY_SIZE(i965_primary_formats);
13781 } else {
13782 intel_primary_formats = i8xx_primary_formats;
13783 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13784 }
13785
13786 drm_universal_plane_init(dev, &primary->base, 0,
13787 &intel_plane_funcs,
13788 intel_primary_formats, num_formats,
13789 DRM_PLANE_TYPE_PRIMARY);
13790
13791 if (INTEL_INFO(dev)->gen >= 4)
13792 intel_create_rotation_property(dev, primary);
13793
13794 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13795
13796 return &primary->base;
13797 }
13798
13799 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13800 {
13801 if (!dev->mode_config.rotation_property) {
13802 unsigned long flags = BIT(DRM_ROTATE_0) |
13803 BIT(DRM_ROTATE_180);
13804
13805 if (INTEL_INFO(dev)->gen >= 9)
13806 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13807
13808 dev->mode_config.rotation_property =
13809 drm_mode_create_rotation_property(dev, flags);
13810 }
13811 if (dev->mode_config.rotation_property)
13812 drm_object_attach_property(&plane->base.base,
13813 dev->mode_config.rotation_property,
13814 plane->base.state->rotation);
13815 }
13816
13817 static int
13818 intel_check_cursor_plane(struct drm_plane *plane,
13819 struct intel_plane_state *state)
13820 {
13821 struct drm_crtc *crtc = state->base.crtc;
13822 struct drm_device *dev = plane->dev;
13823 struct drm_framebuffer *fb = state->base.fb;
13824 struct drm_rect *dest = &state->dst;
13825 struct drm_rect *src = &state->src;
13826 const struct drm_rect *clip = &state->clip;
13827 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13828 struct intel_crtc *intel_crtc;
13829 unsigned stride;
13830 int ret;
13831
13832 crtc = crtc ? crtc : plane->crtc;
13833 intel_crtc = to_intel_crtc(crtc);
13834
13835 ret = drm_plane_helper_check_update(plane, crtc, fb,
13836 src, dest, clip,
13837 DRM_PLANE_HELPER_NO_SCALING,
13838 DRM_PLANE_HELPER_NO_SCALING,
13839 true, true, &state->visible);
13840 if (ret)
13841 return ret;
13842
13843
13844 /* if we want to turn off the cursor ignore width and height */
13845 if (!obj)
13846 goto finish;
13847
13848 /* Check for which cursor types we support */
13849 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13850 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13851 state->base.crtc_w, state->base.crtc_h);
13852 return -EINVAL;
13853 }
13854
13855 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13856 if (obj->base.size < stride * state->base.crtc_h) {
13857 DRM_DEBUG_KMS("buffer is too small\n");
13858 return -ENOMEM;
13859 }
13860
13861 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13862 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13863 ret = -EINVAL;
13864 }
13865
13866 finish:
13867 if (intel_crtc->active) {
13868 if (plane->state->crtc_w != state->base.crtc_w)
13869 intel_crtc->atomic.update_wm = true;
13870
13871 intel_crtc->atomic.fb_bits |=
13872 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13873 }
13874
13875 return ret;
13876 }
13877
13878 static void
13879 intel_disable_cursor_plane(struct drm_plane *plane,
13880 struct drm_crtc *crtc,
13881 bool force)
13882 {
13883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13884
13885 if (!force) {
13886 plane->fb = NULL;
13887 intel_crtc->cursor_bo = NULL;
13888 intel_crtc->cursor_addr = 0;
13889 }
13890
13891 intel_crtc_update_cursor(crtc, false);
13892 }
13893
13894 static void
13895 intel_commit_cursor_plane(struct drm_plane *plane,
13896 struct intel_plane_state *state)
13897 {
13898 struct drm_crtc *crtc = state->base.crtc;
13899 struct drm_device *dev = plane->dev;
13900 struct intel_crtc *intel_crtc;
13901 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13902 uint32_t addr;
13903
13904 crtc = crtc ? crtc : plane->crtc;
13905 intel_crtc = to_intel_crtc(crtc);
13906
13907 plane->fb = state->base.fb;
13908 crtc->cursor_x = state->base.crtc_x;
13909 crtc->cursor_y = state->base.crtc_y;
13910
13911 if (intel_crtc->cursor_bo == obj)
13912 goto update;
13913
13914 if (!obj)
13915 addr = 0;
13916 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13917 addr = i915_gem_obj_ggtt_offset(obj);
13918 else
13919 addr = obj->phys_handle->busaddr;
13920
13921 intel_crtc->cursor_addr = addr;
13922 intel_crtc->cursor_bo = obj;
13923 update:
13924
13925 if (intel_crtc->active)
13926 intel_crtc_update_cursor(crtc, state->visible);
13927 }
13928
13929 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13930 int pipe)
13931 {
13932 struct intel_plane *cursor;
13933 struct intel_plane_state *state;
13934
13935 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13936 if (cursor == NULL)
13937 return NULL;
13938
13939 state = intel_create_plane_state(&cursor->base);
13940 if (!state) {
13941 kfree(cursor);
13942 return NULL;
13943 }
13944 cursor->base.state = &state->base;
13945
13946 cursor->can_scale = false;
13947 cursor->max_downscale = 1;
13948 cursor->pipe = pipe;
13949 cursor->plane = pipe;
13950 cursor->check_plane = intel_check_cursor_plane;
13951 cursor->commit_plane = intel_commit_cursor_plane;
13952 cursor->disable_plane = intel_disable_cursor_plane;
13953
13954 drm_universal_plane_init(dev, &cursor->base, 0,
13955 &intel_plane_funcs,
13956 intel_cursor_formats,
13957 ARRAY_SIZE(intel_cursor_formats),
13958 DRM_PLANE_TYPE_CURSOR);
13959
13960 if (INTEL_INFO(dev)->gen >= 4) {
13961 if (!dev->mode_config.rotation_property)
13962 dev->mode_config.rotation_property =
13963 drm_mode_create_rotation_property(dev,
13964 BIT(DRM_ROTATE_0) |
13965 BIT(DRM_ROTATE_180));
13966 if (dev->mode_config.rotation_property)
13967 drm_object_attach_property(&cursor->base.base,
13968 dev->mode_config.rotation_property,
13969 state->base.rotation);
13970 }
13971
13972 if (INTEL_INFO(dev)->gen >=9)
13973 state->scaler_id = -1;
13974
13975 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13976
13977 return &cursor->base;
13978 }
13979
13980 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13981 struct intel_crtc_state *crtc_state)
13982 {
13983 int i;
13984 struct intel_scaler *intel_scaler;
13985 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13986
13987 for (i = 0; i < intel_crtc->num_scalers; i++) {
13988 intel_scaler = &scaler_state->scalers[i];
13989 intel_scaler->in_use = 0;
13990 intel_scaler->id = i;
13991
13992 intel_scaler->mode = PS_SCALER_MODE_DYN;
13993 }
13994
13995 scaler_state->scaler_id = -1;
13996 }
13997
13998 static void intel_crtc_init(struct drm_device *dev, int pipe)
13999 {
14000 struct drm_i915_private *dev_priv = dev->dev_private;
14001 struct intel_crtc *intel_crtc;
14002 struct intel_crtc_state *crtc_state = NULL;
14003 struct drm_plane *primary = NULL;
14004 struct drm_plane *cursor = NULL;
14005 int i, ret;
14006
14007 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14008 if (intel_crtc == NULL)
14009 return;
14010
14011 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14012 if (!crtc_state)
14013 goto fail;
14014 intel_crtc->config = crtc_state;
14015 intel_crtc->base.state = &crtc_state->base;
14016 crtc_state->base.crtc = &intel_crtc->base;
14017
14018 /* initialize shared scalers */
14019 if (INTEL_INFO(dev)->gen >= 9) {
14020 if (pipe == PIPE_C)
14021 intel_crtc->num_scalers = 1;
14022 else
14023 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14024
14025 skl_init_scalers(dev, intel_crtc, crtc_state);
14026 }
14027
14028 primary = intel_primary_plane_create(dev, pipe);
14029 if (!primary)
14030 goto fail;
14031
14032 cursor = intel_cursor_plane_create(dev, pipe);
14033 if (!cursor)
14034 goto fail;
14035
14036 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14037 cursor, &intel_crtc_funcs);
14038 if (ret)
14039 goto fail;
14040
14041 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14042 for (i = 0; i < 256; i++) {
14043 intel_crtc->lut_r[i] = i;
14044 intel_crtc->lut_g[i] = i;
14045 intel_crtc->lut_b[i] = i;
14046 }
14047
14048 /*
14049 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14050 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14051 */
14052 intel_crtc->pipe = pipe;
14053 intel_crtc->plane = pipe;
14054 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14055 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14056 intel_crtc->plane = !pipe;
14057 }
14058
14059 intel_crtc->cursor_base = ~0;
14060 intel_crtc->cursor_cntl = ~0;
14061 intel_crtc->cursor_size = ~0;
14062
14063 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14064 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14065 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14066 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14067
14068 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14069
14070 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14071 return;
14072
14073 fail:
14074 if (primary)
14075 drm_plane_cleanup(primary);
14076 if (cursor)
14077 drm_plane_cleanup(cursor);
14078 kfree(crtc_state);
14079 kfree(intel_crtc);
14080 }
14081
14082 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14083 {
14084 struct drm_encoder *encoder = connector->base.encoder;
14085 struct drm_device *dev = connector->base.dev;
14086
14087 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14088
14089 if (!encoder || WARN_ON(!encoder->crtc))
14090 return INVALID_PIPE;
14091
14092 return to_intel_crtc(encoder->crtc)->pipe;
14093 }
14094
14095 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14096 struct drm_file *file)
14097 {
14098 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14099 struct drm_crtc *drmmode_crtc;
14100 struct intel_crtc *crtc;
14101
14102 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14103
14104 if (!drmmode_crtc) {
14105 DRM_ERROR("no such CRTC id\n");
14106 return -ENOENT;
14107 }
14108
14109 crtc = to_intel_crtc(drmmode_crtc);
14110 pipe_from_crtc_id->pipe = crtc->pipe;
14111
14112 return 0;
14113 }
14114
14115 static int intel_encoder_clones(struct intel_encoder *encoder)
14116 {
14117 struct drm_device *dev = encoder->base.dev;
14118 struct intel_encoder *source_encoder;
14119 int index_mask = 0;
14120 int entry = 0;
14121
14122 for_each_intel_encoder(dev, source_encoder) {
14123 if (encoders_cloneable(encoder, source_encoder))
14124 index_mask |= (1 << entry);
14125
14126 entry++;
14127 }
14128
14129 return index_mask;
14130 }
14131
14132 static bool has_edp_a(struct drm_device *dev)
14133 {
14134 struct drm_i915_private *dev_priv = dev->dev_private;
14135
14136 if (!IS_MOBILE(dev))
14137 return false;
14138
14139 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14140 return false;
14141
14142 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14143 return false;
14144
14145 return true;
14146 }
14147
14148 static bool intel_crt_present(struct drm_device *dev)
14149 {
14150 struct drm_i915_private *dev_priv = dev->dev_private;
14151
14152 if (INTEL_INFO(dev)->gen >= 9)
14153 return false;
14154
14155 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14156 return false;
14157
14158 if (IS_CHERRYVIEW(dev))
14159 return false;
14160
14161 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14162 return false;
14163
14164 return true;
14165 }
14166
14167 static void intel_setup_outputs(struct drm_device *dev)
14168 {
14169 struct drm_i915_private *dev_priv = dev->dev_private;
14170 struct intel_encoder *encoder;
14171 bool dpd_is_edp = false;
14172
14173 intel_lvds_init(dev);
14174
14175 if (intel_crt_present(dev))
14176 intel_crt_init(dev);
14177
14178 if (IS_BROXTON(dev)) {
14179 /*
14180 * FIXME: Broxton doesn't support port detection via the
14181 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14182 * detect the ports.
14183 */
14184 intel_ddi_init(dev, PORT_A);
14185 intel_ddi_init(dev, PORT_B);
14186 intel_ddi_init(dev, PORT_C);
14187 } else if (HAS_DDI(dev)) {
14188 int found;
14189
14190 /*
14191 * Haswell uses DDI functions to detect digital outputs.
14192 * On SKL pre-D0 the strap isn't connected, so we assume
14193 * it's there.
14194 */
14195 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14196 /* WaIgnoreDDIAStrap: skl */
14197 if (found ||
14198 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14199 intel_ddi_init(dev, PORT_A);
14200
14201 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14202 * register */
14203 found = I915_READ(SFUSE_STRAP);
14204
14205 if (found & SFUSE_STRAP_DDIB_DETECTED)
14206 intel_ddi_init(dev, PORT_B);
14207 if (found & SFUSE_STRAP_DDIC_DETECTED)
14208 intel_ddi_init(dev, PORT_C);
14209 if (found & SFUSE_STRAP_DDID_DETECTED)
14210 intel_ddi_init(dev, PORT_D);
14211 } else if (HAS_PCH_SPLIT(dev)) {
14212 int found;
14213 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14214
14215 if (has_edp_a(dev))
14216 intel_dp_init(dev, DP_A, PORT_A);
14217
14218 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14219 /* PCH SDVOB multiplex with HDMIB */
14220 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14221 if (!found)
14222 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14223 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14224 intel_dp_init(dev, PCH_DP_B, PORT_B);
14225 }
14226
14227 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14228 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14229
14230 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14231 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14232
14233 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14234 intel_dp_init(dev, PCH_DP_C, PORT_C);
14235
14236 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14237 intel_dp_init(dev, PCH_DP_D, PORT_D);
14238 } else if (IS_VALLEYVIEW(dev)) {
14239 /*
14240 * The DP_DETECTED bit is the latched state of the DDC
14241 * SDA pin at boot. However since eDP doesn't require DDC
14242 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14243 * eDP ports may have been muxed to an alternate function.
14244 * Thus we can't rely on the DP_DETECTED bit alone to detect
14245 * eDP ports. Consult the VBT as well as DP_DETECTED to
14246 * detect eDP ports.
14247 */
14248 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14249 !intel_dp_is_edp(dev, PORT_B))
14250 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14251 PORT_B);
14252 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14253 intel_dp_is_edp(dev, PORT_B))
14254 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14255
14256 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14257 !intel_dp_is_edp(dev, PORT_C))
14258 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14259 PORT_C);
14260 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14261 intel_dp_is_edp(dev, PORT_C))
14262 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14263
14264 if (IS_CHERRYVIEW(dev)) {
14265 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14266 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14267 PORT_D);
14268 /* eDP not supported on port D, so don't check VBT */
14269 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14270 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14271 }
14272
14273 intel_dsi_init(dev);
14274 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14275 bool found = false;
14276
14277 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14278 DRM_DEBUG_KMS("probing SDVOB\n");
14279 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14280 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14281 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14282 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14283 }
14284
14285 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14286 intel_dp_init(dev, DP_B, PORT_B);
14287 }
14288
14289 /* Before G4X SDVOC doesn't have its own detect register */
14290
14291 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14292 DRM_DEBUG_KMS("probing SDVOC\n");
14293 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14294 }
14295
14296 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14297
14298 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14299 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14300 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14301 }
14302 if (SUPPORTS_INTEGRATED_DP(dev))
14303 intel_dp_init(dev, DP_C, PORT_C);
14304 }
14305
14306 if (SUPPORTS_INTEGRATED_DP(dev) &&
14307 (I915_READ(DP_D) & DP_DETECTED))
14308 intel_dp_init(dev, DP_D, PORT_D);
14309 } else if (IS_GEN2(dev))
14310 intel_dvo_init(dev);
14311
14312 if (SUPPORTS_TV(dev))
14313 intel_tv_init(dev);
14314
14315 intel_psr_init(dev);
14316
14317 for_each_intel_encoder(dev, encoder) {
14318 encoder->base.possible_crtcs = encoder->crtc_mask;
14319 encoder->base.possible_clones =
14320 intel_encoder_clones(encoder);
14321 }
14322
14323 intel_init_pch_refclk(dev);
14324
14325 drm_helper_move_panel_connectors_to_head(dev);
14326 }
14327
14328 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14329 {
14330 struct drm_device *dev = fb->dev;
14331 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14332
14333 drm_framebuffer_cleanup(fb);
14334 mutex_lock(&dev->struct_mutex);
14335 WARN_ON(!intel_fb->obj->framebuffer_references--);
14336 drm_gem_object_unreference(&intel_fb->obj->base);
14337 mutex_unlock(&dev->struct_mutex);
14338 kfree(intel_fb);
14339 }
14340
14341 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14342 struct drm_file *file,
14343 unsigned int *handle)
14344 {
14345 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14346 struct drm_i915_gem_object *obj = intel_fb->obj;
14347
14348 return drm_gem_handle_create(file, &obj->base, handle);
14349 }
14350
14351 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14352 .destroy = intel_user_framebuffer_destroy,
14353 .create_handle = intel_user_framebuffer_create_handle,
14354 };
14355
14356 static
14357 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14358 uint32_t pixel_format)
14359 {
14360 u32 gen = INTEL_INFO(dev)->gen;
14361
14362 if (gen >= 9) {
14363 /* "The stride in bytes must not exceed the of the size of 8K
14364 * pixels and 32K bytes."
14365 */
14366 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14367 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14368 return 32*1024;
14369 } else if (gen >= 4) {
14370 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14371 return 16*1024;
14372 else
14373 return 32*1024;
14374 } else if (gen >= 3) {
14375 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14376 return 8*1024;
14377 else
14378 return 16*1024;
14379 } else {
14380 /* XXX DSPC is limited to 4k tiled */
14381 return 8*1024;
14382 }
14383 }
14384
14385 static int intel_framebuffer_init(struct drm_device *dev,
14386 struct intel_framebuffer *intel_fb,
14387 struct drm_mode_fb_cmd2 *mode_cmd,
14388 struct drm_i915_gem_object *obj)
14389 {
14390 unsigned int aligned_height;
14391 int ret;
14392 u32 pitch_limit, stride_alignment;
14393
14394 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14395
14396 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14397 /* Enforce that fb modifier and tiling mode match, but only for
14398 * X-tiled. This is needed for FBC. */
14399 if (!!(obj->tiling_mode == I915_TILING_X) !=
14400 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14401 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14402 return -EINVAL;
14403 }
14404 } else {
14405 if (obj->tiling_mode == I915_TILING_X)
14406 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14407 else if (obj->tiling_mode == I915_TILING_Y) {
14408 DRM_DEBUG("No Y tiling for legacy addfb\n");
14409 return -EINVAL;
14410 }
14411 }
14412
14413 /* Passed in modifier sanity checking. */
14414 switch (mode_cmd->modifier[0]) {
14415 case I915_FORMAT_MOD_Y_TILED:
14416 case I915_FORMAT_MOD_Yf_TILED:
14417 if (INTEL_INFO(dev)->gen < 9) {
14418 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14419 mode_cmd->modifier[0]);
14420 return -EINVAL;
14421 }
14422 case DRM_FORMAT_MOD_NONE:
14423 case I915_FORMAT_MOD_X_TILED:
14424 break;
14425 default:
14426 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14427 mode_cmd->modifier[0]);
14428 return -EINVAL;
14429 }
14430
14431 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14432 mode_cmd->pixel_format);
14433 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14434 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14435 mode_cmd->pitches[0], stride_alignment);
14436 return -EINVAL;
14437 }
14438
14439 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14440 mode_cmd->pixel_format);
14441 if (mode_cmd->pitches[0] > pitch_limit) {
14442 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14443 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14444 "tiled" : "linear",
14445 mode_cmd->pitches[0], pitch_limit);
14446 return -EINVAL;
14447 }
14448
14449 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14450 mode_cmd->pitches[0] != obj->stride) {
14451 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14452 mode_cmd->pitches[0], obj->stride);
14453 return -EINVAL;
14454 }
14455
14456 /* Reject formats not supported by any plane early. */
14457 switch (mode_cmd->pixel_format) {
14458 case DRM_FORMAT_C8:
14459 case DRM_FORMAT_RGB565:
14460 case DRM_FORMAT_XRGB8888:
14461 case DRM_FORMAT_ARGB8888:
14462 break;
14463 case DRM_FORMAT_XRGB1555:
14464 if (INTEL_INFO(dev)->gen > 3) {
14465 DRM_DEBUG("unsupported pixel format: %s\n",
14466 drm_get_format_name(mode_cmd->pixel_format));
14467 return -EINVAL;
14468 }
14469 break;
14470 case DRM_FORMAT_ABGR8888:
14471 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14472 DRM_DEBUG("unsupported pixel format: %s\n",
14473 drm_get_format_name(mode_cmd->pixel_format));
14474 return -EINVAL;
14475 }
14476 break;
14477 case DRM_FORMAT_XBGR8888:
14478 case DRM_FORMAT_XRGB2101010:
14479 case DRM_FORMAT_XBGR2101010:
14480 if (INTEL_INFO(dev)->gen < 4) {
14481 DRM_DEBUG("unsupported pixel format: %s\n",
14482 drm_get_format_name(mode_cmd->pixel_format));
14483 return -EINVAL;
14484 }
14485 break;
14486 case DRM_FORMAT_ABGR2101010:
14487 if (!IS_VALLEYVIEW(dev)) {
14488 DRM_DEBUG("unsupported pixel format: %s\n",
14489 drm_get_format_name(mode_cmd->pixel_format));
14490 return -EINVAL;
14491 }
14492 break;
14493 case DRM_FORMAT_YUYV:
14494 case DRM_FORMAT_UYVY:
14495 case DRM_FORMAT_YVYU:
14496 case DRM_FORMAT_VYUY:
14497 if (INTEL_INFO(dev)->gen < 5) {
14498 DRM_DEBUG("unsupported pixel format: %s\n",
14499 drm_get_format_name(mode_cmd->pixel_format));
14500 return -EINVAL;
14501 }
14502 break;
14503 default:
14504 DRM_DEBUG("unsupported pixel format: %s\n",
14505 drm_get_format_name(mode_cmd->pixel_format));
14506 return -EINVAL;
14507 }
14508
14509 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14510 if (mode_cmd->offsets[0] != 0)
14511 return -EINVAL;
14512
14513 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14514 mode_cmd->pixel_format,
14515 mode_cmd->modifier[0]);
14516 /* FIXME drm helper for size checks (especially planar formats)? */
14517 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14518 return -EINVAL;
14519
14520 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14521 intel_fb->obj = obj;
14522 intel_fb->obj->framebuffer_references++;
14523
14524 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14525 if (ret) {
14526 DRM_ERROR("framebuffer init failed %d\n", ret);
14527 return ret;
14528 }
14529
14530 return 0;
14531 }
14532
14533 static struct drm_framebuffer *
14534 intel_user_framebuffer_create(struct drm_device *dev,
14535 struct drm_file *filp,
14536 struct drm_mode_fb_cmd2 *mode_cmd)
14537 {
14538 struct drm_i915_gem_object *obj;
14539
14540 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14541 mode_cmd->handles[0]));
14542 if (&obj->base == NULL)
14543 return ERR_PTR(-ENOENT);
14544
14545 return intel_framebuffer_create(dev, mode_cmd, obj);
14546 }
14547
14548 #ifndef CONFIG_DRM_I915_FBDEV
14549 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14550 {
14551 }
14552 #endif
14553
14554 static const struct drm_mode_config_funcs intel_mode_funcs = {
14555 .fb_create = intel_user_framebuffer_create,
14556 .output_poll_changed = intel_fbdev_output_poll_changed,
14557 .atomic_check = intel_atomic_check,
14558 .atomic_commit = intel_atomic_commit,
14559 .atomic_state_alloc = intel_atomic_state_alloc,
14560 .atomic_state_clear = intel_atomic_state_clear,
14561 };
14562
14563 /* Set up chip specific display functions */
14564 static void intel_init_display(struct drm_device *dev)
14565 {
14566 struct drm_i915_private *dev_priv = dev->dev_private;
14567
14568 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14569 dev_priv->display.find_dpll = g4x_find_best_dpll;
14570 else if (IS_CHERRYVIEW(dev))
14571 dev_priv->display.find_dpll = chv_find_best_dpll;
14572 else if (IS_VALLEYVIEW(dev))
14573 dev_priv->display.find_dpll = vlv_find_best_dpll;
14574 else if (IS_PINEVIEW(dev))
14575 dev_priv->display.find_dpll = pnv_find_best_dpll;
14576 else
14577 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14578
14579 if (INTEL_INFO(dev)->gen >= 9) {
14580 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14581 dev_priv->display.get_initial_plane_config =
14582 skylake_get_initial_plane_config;
14583 dev_priv->display.crtc_compute_clock =
14584 haswell_crtc_compute_clock;
14585 dev_priv->display.crtc_enable = haswell_crtc_enable;
14586 dev_priv->display.crtc_disable = haswell_crtc_disable;
14587 dev_priv->display.update_primary_plane =
14588 skylake_update_primary_plane;
14589 } else if (HAS_DDI(dev)) {
14590 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14591 dev_priv->display.get_initial_plane_config =
14592 ironlake_get_initial_plane_config;
14593 dev_priv->display.crtc_compute_clock =
14594 haswell_crtc_compute_clock;
14595 dev_priv->display.crtc_enable = haswell_crtc_enable;
14596 dev_priv->display.crtc_disable = haswell_crtc_disable;
14597 dev_priv->display.update_primary_plane =
14598 ironlake_update_primary_plane;
14599 } else if (HAS_PCH_SPLIT(dev)) {
14600 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14601 dev_priv->display.get_initial_plane_config =
14602 ironlake_get_initial_plane_config;
14603 dev_priv->display.crtc_compute_clock =
14604 ironlake_crtc_compute_clock;
14605 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14606 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14607 dev_priv->display.update_primary_plane =
14608 ironlake_update_primary_plane;
14609 } else if (IS_VALLEYVIEW(dev)) {
14610 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14611 dev_priv->display.get_initial_plane_config =
14612 i9xx_get_initial_plane_config;
14613 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14614 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14615 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14616 dev_priv->display.update_primary_plane =
14617 i9xx_update_primary_plane;
14618 } else {
14619 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14620 dev_priv->display.get_initial_plane_config =
14621 i9xx_get_initial_plane_config;
14622 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14623 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14624 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14625 dev_priv->display.update_primary_plane =
14626 i9xx_update_primary_plane;
14627 }
14628
14629 /* Returns the core display clock speed */
14630 if (IS_SKYLAKE(dev))
14631 dev_priv->display.get_display_clock_speed =
14632 skylake_get_display_clock_speed;
14633 else if (IS_BROADWELL(dev))
14634 dev_priv->display.get_display_clock_speed =
14635 broadwell_get_display_clock_speed;
14636 else if (IS_HASWELL(dev))
14637 dev_priv->display.get_display_clock_speed =
14638 haswell_get_display_clock_speed;
14639 else if (IS_VALLEYVIEW(dev))
14640 dev_priv->display.get_display_clock_speed =
14641 valleyview_get_display_clock_speed;
14642 else if (IS_GEN5(dev))
14643 dev_priv->display.get_display_clock_speed =
14644 ilk_get_display_clock_speed;
14645 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14646 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14647 dev_priv->display.get_display_clock_speed =
14648 i945_get_display_clock_speed;
14649 else if (IS_GM45(dev))
14650 dev_priv->display.get_display_clock_speed =
14651 gm45_get_display_clock_speed;
14652 else if (IS_CRESTLINE(dev))
14653 dev_priv->display.get_display_clock_speed =
14654 i965gm_get_display_clock_speed;
14655 else if (IS_PINEVIEW(dev))
14656 dev_priv->display.get_display_clock_speed =
14657 pnv_get_display_clock_speed;
14658 else if (IS_G33(dev) || IS_G4X(dev))
14659 dev_priv->display.get_display_clock_speed =
14660 g33_get_display_clock_speed;
14661 else if (IS_I915G(dev))
14662 dev_priv->display.get_display_clock_speed =
14663 i915_get_display_clock_speed;
14664 else if (IS_I945GM(dev) || IS_845G(dev))
14665 dev_priv->display.get_display_clock_speed =
14666 i9xx_misc_get_display_clock_speed;
14667 else if (IS_PINEVIEW(dev))
14668 dev_priv->display.get_display_clock_speed =
14669 pnv_get_display_clock_speed;
14670 else if (IS_I915GM(dev))
14671 dev_priv->display.get_display_clock_speed =
14672 i915gm_get_display_clock_speed;
14673 else if (IS_I865G(dev))
14674 dev_priv->display.get_display_clock_speed =
14675 i865_get_display_clock_speed;
14676 else if (IS_I85X(dev))
14677 dev_priv->display.get_display_clock_speed =
14678 i85x_get_display_clock_speed;
14679 else { /* 830 */
14680 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14681 dev_priv->display.get_display_clock_speed =
14682 i830_get_display_clock_speed;
14683 }
14684
14685 if (IS_GEN5(dev)) {
14686 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14687 } else if (IS_GEN6(dev)) {
14688 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14689 } else if (IS_IVYBRIDGE(dev)) {
14690 /* FIXME: detect B0+ stepping and use auto training */
14691 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14692 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14693 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14694 if (IS_BROADWELL(dev))
14695 dev_priv->display.modeset_global_resources =
14696 broadwell_modeset_global_resources;
14697 } else if (IS_VALLEYVIEW(dev)) {
14698 dev_priv->display.modeset_global_resources =
14699 valleyview_modeset_global_resources;
14700 } else if (IS_BROXTON(dev)) {
14701 dev_priv->display.modeset_global_resources =
14702 broxton_modeset_global_resources;
14703 }
14704
14705 switch (INTEL_INFO(dev)->gen) {
14706 case 2:
14707 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14708 break;
14709
14710 case 3:
14711 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14712 break;
14713
14714 case 4:
14715 case 5:
14716 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14717 break;
14718
14719 case 6:
14720 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14721 break;
14722 case 7:
14723 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14724 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14725 break;
14726 case 9:
14727 /* Drop through - unsupported since execlist only. */
14728 default:
14729 /* Default just returns -ENODEV to indicate unsupported */
14730 dev_priv->display.queue_flip = intel_default_queue_flip;
14731 }
14732
14733 intel_panel_init_backlight_funcs(dev);
14734
14735 mutex_init(&dev_priv->pps_mutex);
14736 }
14737
14738 /*
14739 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14740 * resume, or other times. This quirk makes sure that's the case for
14741 * affected systems.
14742 */
14743 static void quirk_pipea_force(struct drm_device *dev)
14744 {
14745 struct drm_i915_private *dev_priv = dev->dev_private;
14746
14747 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14748 DRM_INFO("applying pipe a force quirk\n");
14749 }
14750
14751 static void quirk_pipeb_force(struct drm_device *dev)
14752 {
14753 struct drm_i915_private *dev_priv = dev->dev_private;
14754
14755 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14756 DRM_INFO("applying pipe b force quirk\n");
14757 }
14758
14759 /*
14760 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14761 */
14762 static void quirk_ssc_force_disable(struct drm_device *dev)
14763 {
14764 struct drm_i915_private *dev_priv = dev->dev_private;
14765 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14766 DRM_INFO("applying lvds SSC disable quirk\n");
14767 }
14768
14769 /*
14770 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14771 * brightness value
14772 */
14773 static void quirk_invert_brightness(struct drm_device *dev)
14774 {
14775 struct drm_i915_private *dev_priv = dev->dev_private;
14776 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14777 DRM_INFO("applying inverted panel brightness quirk\n");
14778 }
14779
14780 /* Some VBT's incorrectly indicate no backlight is present */
14781 static void quirk_backlight_present(struct drm_device *dev)
14782 {
14783 struct drm_i915_private *dev_priv = dev->dev_private;
14784 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14785 DRM_INFO("applying backlight present quirk\n");
14786 }
14787
14788 struct intel_quirk {
14789 int device;
14790 int subsystem_vendor;
14791 int subsystem_device;
14792 void (*hook)(struct drm_device *dev);
14793 };
14794
14795 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14796 struct intel_dmi_quirk {
14797 void (*hook)(struct drm_device *dev);
14798 const struct dmi_system_id (*dmi_id_list)[];
14799 };
14800
14801 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14802 {
14803 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14804 return 1;
14805 }
14806
14807 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14808 {
14809 .dmi_id_list = &(const struct dmi_system_id[]) {
14810 {
14811 .callback = intel_dmi_reverse_brightness,
14812 .ident = "NCR Corporation",
14813 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14814 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14815 },
14816 },
14817 { } /* terminating entry */
14818 },
14819 .hook = quirk_invert_brightness,
14820 },
14821 };
14822
14823 static struct intel_quirk intel_quirks[] = {
14824 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14825 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14826
14827 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14828 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14829
14830 /* 830 needs to leave pipe A & dpll A up */
14831 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14832
14833 /* 830 needs to leave pipe B & dpll B up */
14834 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14835
14836 /* Lenovo U160 cannot use SSC on LVDS */
14837 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14838
14839 /* Sony Vaio Y cannot use SSC on LVDS */
14840 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14841
14842 /* Acer Aspire 5734Z must invert backlight brightness */
14843 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14844
14845 /* Acer/eMachines G725 */
14846 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14847
14848 /* Acer/eMachines e725 */
14849 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14850
14851 /* Acer/Packard Bell NCL20 */
14852 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14853
14854 /* Acer Aspire 4736Z */
14855 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14856
14857 /* Acer Aspire 5336 */
14858 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14859
14860 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14861 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14862
14863 /* Acer C720 Chromebook (Core i3 4005U) */
14864 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14865
14866 /* Apple Macbook 2,1 (Core 2 T7400) */
14867 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14868
14869 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14870 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14871
14872 /* HP Chromebook 14 (Celeron 2955U) */
14873 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14874
14875 /* Dell Chromebook 11 */
14876 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14877 };
14878
14879 static void intel_init_quirks(struct drm_device *dev)
14880 {
14881 struct pci_dev *d = dev->pdev;
14882 int i;
14883
14884 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14885 struct intel_quirk *q = &intel_quirks[i];
14886
14887 if (d->device == q->device &&
14888 (d->subsystem_vendor == q->subsystem_vendor ||
14889 q->subsystem_vendor == PCI_ANY_ID) &&
14890 (d->subsystem_device == q->subsystem_device ||
14891 q->subsystem_device == PCI_ANY_ID))
14892 q->hook(dev);
14893 }
14894 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14895 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14896 intel_dmi_quirks[i].hook(dev);
14897 }
14898 }
14899
14900 /* Disable the VGA plane that we never use */
14901 static void i915_disable_vga(struct drm_device *dev)
14902 {
14903 struct drm_i915_private *dev_priv = dev->dev_private;
14904 u8 sr1;
14905 u32 vga_reg = i915_vgacntrl_reg(dev);
14906
14907 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14908 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14909 outb(SR01, VGA_SR_INDEX);
14910 sr1 = inb(VGA_SR_DATA);
14911 outb(sr1 | 1<<5, VGA_SR_DATA);
14912 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14913 udelay(300);
14914
14915 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14916 POSTING_READ(vga_reg);
14917 }
14918
14919 void intel_modeset_init_hw(struct drm_device *dev)
14920 {
14921 intel_update_cdclk(dev);
14922 intel_prepare_ddi(dev);
14923 intel_init_clock_gating(dev);
14924 intel_enable_gt_powersave(dev);
14925 }
14926
14927 void intel_modeset_init(struct drm_device *dev)
14928 {
14929 struct drm_i915_private *dev_priv = dev->dev_private;
14930 int sprite, ret;
14931 enum pipe pipe;
14932 struct intel_crtc *crtc;
14933
14934 drm_mode_config_init(dev);
14935
14936 dev->mode_config.min_width = 0;
14937 dev->mode_config.min_height = 0;
14938
14939 dev->mode_config.preferred_depth = 24;
14940 dev->mode_config.prefer_shadow = 1;
14941
14942 dev->mode_config.allow_fb_modifiers = true;
14943
14944 dev->mode_config.funcs = &intel_mode_funcs;
14945
14946 intel_init_quirks(dev);
14947
14948 intel_init_pm(dev);
14949
14950 if (INTEL_INFO(dev)->num_pipes == 0)
14951 return;
14952
14953 intel_init_display(dev);
14954 intel_init_audio(dev);
14955
14956 if (IS_GEN2(dev)) {
14957 dev->mode_config.max_width = 2048;
14958 dev->mode_config.max_height = 2048;
14959 } else if (IS_GEN3(dev)) {
14960 dev->mode_config.max_width = 4096;
14961 dev->mode_config.max_height = 4096;
14962 } else {
14963 dev->mode_config.max_width = 8192;
14964 dev->mode_config.max_height = 8192;
14965 }
14966
14967 if (IS_845G(dev) || IS_I865G(dev)) {
14968 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14969 dev->mode_config.cursor_height = 1023;
14970 } else if (IS_GEN2(dev)) {
14971 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14972 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14973 } else {
14974 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14975 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14976 }
14977
14978 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14979
14980 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14981 INTEL_INFO(dev)->num_pipes,
14982 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14983
14984 for_each_pipe(dev_priv, pipe) {
14985 intel_crtc_init(dev, pipe);
14986 for_each_sprite(dev_priv, pipe, sprite) {
14987 ret = intel_plane_init(dev, pipe, sprite);
14988 if (ret)
14989 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14990 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14991 }
14992 }
14993
14994 intel_init_dpio(dev);
14995
14996 intel_shared_dpll_init(dev);
14997
14998 /* Just disable it once at startup */
14999 i915_disable_vga(dev);
15000 intel_setup_outputs(dev);
15001
15002 /* Just in case the BIOS is doing something questionable. */
15003 intel_fbc_disable(dev);
15004
15005 drm_modeset_lock_all(dev);
15006 intel_modeset_setup_hw_state(dev, false);
15007 drm_modeset_unlock_all(dev);
15008
15009 for_each_intel_crtc(dev, crtc) {
15010 if (!crtc->active)
15011 continue;
15012
15013 /*
15014 * Note that reserving the BIOS fb up front prevents us
15015 * from stuffing other stolen allocations like the ring
15016 * on top. This prevents some ugliness at boot time, and
15017 * can even allow for smooth boot transitions if the BIOS
15018 * fb is large enough for the active pipe configuration.
15019 */
15020 if (dev_priv->display.get_initial_plane_config) {
15021 dev_priv->display.get_initial_plane_config(crtc,
15022 &crtc->plane_config);
15023 /*
15024 * If the fb is shared between multiple heads, we'll
15025 * just get the first one.
15026 */
15027 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15028 }
15029 }
15030 }
15031
15032 static void intel_enable_pipe_a(struct drm_device *dev)
15033 {
15034 struct intel_connector *connector;
15035 struct drm_connector *crt = NULL;
15036 struct intel_load_detect_pipe load_detect_temp;
15037 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15038
15039 /* We can't just switch on the pipe A, we need to set things up with a
15040 * proper mode and output configuration. As a gross hack, enable pipe A
15041 * by enabling the load detect pipe once. */
15042 for_each_intel_connector(dev, connector) {
15043 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15044 crt = &connector->base;
15045 break;
15046 }
15047 }
15048
15049 if (!crt)
15050 return;
15051
15052 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15053 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15054 }
15055
15056 static bool
15057 intel_check_plane_mapping(struct intel_crtc *crtc)
15058 {
15059 struct drm_device *dev = crtc->base.dev;
15060 struct drm_i915_private *dev_priv = dev->dev_private;
15061 u32 reg, val;
15062
15063 if (INTEL_INFO(dev)->num_pipes == 1)
15064 return true;
15065
15066 reg = DSPCNTR(!crtc->plane);
15067 val = I915_READ(reg);
15068
15069 if ((val & DISPLAY_PLANE_ENABLE) &&
15070 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15071 return false;
15072
15073 return true;
15074 }
15075
15076 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15077 {
15078 struct drm_device *dev = crtc->base.dev;
15079 struct drm_i915_private *dev_priv = dev->dev_private;
15080 u32 reg;
15081
15082 /* Clear any frame start delays used for debugging left by the BIOS */
15083 reg = PIPECONF(crtc->config->cpu_transcoder);
15084 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15085
15086 /* restore vblank interrupts to correct state */
15087 drm_crtc_vblank_reset(&crtc->base);
15088 if (crtc->active) {
15089 update_scanline_offset(crtc);
15090 drm_crtc_vblank_on(&crtc->base);
15091 }
15092
15093 /* We need to sanitize the plane -> pipe mapping first because this will
15094 * disable the crtc (and hence change the state) if it is wrong. Note
15095 * that gen4+ has a fixed plane -> pipe mapping. */
15096 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15097 struct intel_connector *connector;
15098 bool plane;
15099
15100 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15101 crtc->base.base.id);
15102
15103 /* Pipe has the wrong plane attached and the plane is active.
15104 * Temporarily change the plane mapping and disable everything
15105 * ... */
15106 plane = crtc->plane;
15107 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15108 crtc->base.primary->crtc = &crtc->base;
15109 crtc->plane = !plane;
15110 intel_crtc_control(&crtc->base, false);
15111 crtc->plane = plane;
15112
15113 /* ... and break all links. */
15114 for_each_intel_connector(dev, connector) {
15115 if (connector->encoder->base.crtc != &crtc->base)
15116 continue;
15117
15118 connector->base.dpms = DRM_MODE_DPMS_OFF;
15119 connector->base.encoder = NULL;
15120 }
15121 /* multiple connectors may have the same encoder:
15122 * handle them and break crtc link separately */
15123 for_each_intel_connector(dev, connector)
15124 if (connector->encoder->base.crtc == &crtc->base) {
15125 connector->encoder->base.crtc = NULL;
15126 connector->encoder->connectors_active = false;
15127 }
15128
15129 WARN_ON(crtc->active);
15130 crtc->base.state->enable = false;
15131 crtc->base.state->active = false;
15132 crtc->base.enabled = false;
15133 }
15134
15135 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15136 crtc->pipe == PIPE_A && !crtc->active) {
15137 /* BIOS forgot to enable pipe A, this mostly happens after
15138 * resume. Force-enable the pipe to fix this, the update_dpms
15139 * call below we restore the pipe to the right state, but leave
15140 * the required bits on. */
15141 intel_enable_pipe_a(dev);
15142 }
15143
15144 /* Adjust the state of the output pipe according to whether we
15145 * have active connectors/encoders. */
15146 intel_crtc_update_dpms(&crtc->base);
15147
15148 if (crtc->active != crtc->base.state->active) {
15149 struct intel_encoder *encoder;
15150
15151 /* This can happen either due to bugs in the get_hw_state
15152 * functions or because the pipe is force-enabled due to the
15153 * pipe A quirk. */
15154 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15155 crtc->base.base.id,
15156 crtc->base.state->enable ? "enabled" : "disabled",
15157 crtc->active ? "enabled" : "disabled");
15158
15159 crtc->base.state->enable = crtc->active;
15160 crtc->base.state->active = crtc->active;
15161 crtc->base.enabled = crtc->active;
15162
15163 /* Because we only establish the connector -> encoder ->
15164 * crtc links if something is active, this means the
15165 * crtc is now deactivated. Break the links. connector
15166 * -> encoder links are only establish when things are
15167 * actually up, hence no need to break them. */
15168 WARN_ON(crtc->active);
15169
15170 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15171 WARN_ON(encoder->connectors_active);
15172 encoder->base.crtc = NULL;
15173 }
15174 }
15175
15176 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15177 /*
15178 * We start out with underrun reporting disabled to avoid races.
15179 * For correct bookkeeping mark this on active crtcs.
15180 *
15181 * Also on gmch platforms we dont have any hardware bits to
15182 * disable the underrun reporting. Which means we need to start
15183 * out with underrun reporting disabled also on inactive pipes,
15184 * since otherwise we'll complain about the garbage we read when
15185 * e.g. coming up after runtime pm.
15186 *
15187 * No protection against concurrent access is required - at
15188 * worst a fifo underrun happens which also sets this to false.
15189 */
15190 crtc->cpu_fifo_underrun_disabled = true;
15191 crtc->pch_fifo_underrun_disabled = true;
15192 }
15193 }
15194
15195 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15196 {
15197 struct intel_connector *connector;
15198 struct drm_device *dev = encoder->base.dev;
15199
15200 /* We need to check both for a crtc link (meaning that the
15201 * encoder is active and trying to read from a pipe) and the
15202 * pipe itself being active. */
15203 bool has_active_crtc = encoder->base.crtc &&
15204 to_intel_crtc(encoder->base.crtc)->active;
15205
15206 if (encoder->connectors_active && !has_active_crtc) {
15207 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15208 encoder->base.base.id,
15209 encoder->base.name);
15210
15211 /* Connector is active, but has no active pipe. This is
15212 * fallout from our resume register restoring. Disable
15213 * the encoder manually again. */
15214 if (encoder->base.crtc) {
15215 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15216 encoder->base.base.id,
15217 encoder->base.name);
15218 encoder->disable(encoder);
15219 if (encoder->post_disable)
15220 encoder->post_disable(encoder);
15221 }
15222 encoder->base.crtc = NULL;
15223 encoder->connectors_active = false;
15224
15225 /* Inconsistent output/port/pipe state happens presumably due to
15226 * a bug in one of the get_hw_state functions. Or someplace else
15227 * in our code, like the register restore mess on resume. Clamp
15228 * things to off as a safer default. */
15229 for_each_intel_connector(dev, connector) {
15230 if (connector->encoder != encoder)
15231 continue;
15232 connector->base.dpms = DRM_MODE_DPMS_OFF;
15233 connector->base.encoder = NULL;
15234 }
15235 }
15236 /* Enabled encoders without active connectors will be fixed in
15237 * the crtc fixup. */
15238 }
15239
15240 void i915_redisable_vga_power_on(struct drm_device *dev)
15241 {
15242 struct drm_i915_private *dev_priv = dev->dev_private;
15243 u32 vga_reg = i915_vgacntrl_reg(dev);
15244
15245 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15246 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15247 i915_disable_vga(dev);
15248 }
15249 }
15250
15251 void i915_redisable_vga(struct drm_device *dev)
15252 {
15253 struct drm_i915_private *dev_priv = dev->dev_private;
15254
15255 /* This function can be called both from intel_modeset_setup_hw_state or
15256 * at a very early point in our resume sequence, where the power well
15257 * structures are not yet restored. Since this function is at a very
15258 * paranoid "someone might have enabled VGA while we were not looking"
15259 * level, just check if the power well is enabled instead of trying to
15260 * follow the "don't touch the power well if we don't need it" policy
15261 * the rest of the driver uses. */
15262 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15263 return;
15264
15265 i915_redisable_vga_power_on(dev);
15266 }
15267
15268 static bool primary_get_hw_state(struct intel_crtc *crtc)
15269 {
15270 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15271
15272 if (!crtc->base.enabled)
15273 return false;
15274
15275 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15276 }
15277
15278 static int readout_hw_crtc_state(struct drm_atomic_state *state,
15279 struct intel_crtc *crtc)
15280 {
15281 struct drm_i915_private *dev_priv = to_i915(state->dev);
15282 struct intel_crtc_state *crtc_state;
15283 struct drm_plane *primary = crtc->base.primary;
15284 struct drm_plane_state *drm_plane_state;
15285 struct intel_plane_state *plane_state;
15286 int ret;
15287
15288 crtc_state = intel_atomic_get_crtc_state(state, crtc);
15289 if (IS_ERR(crtc_state))
15290 return PTR_ERR(crtc_state);
15291
15292 ret = drm_atomic_add_affected_planes(state, &crtc->base);
15293 if (ret)
15294 return ret;
15295
15296 memset(crtc_state, 0, sizeof(*crtc_state));
15297 crtc_state->base.crtc = &crtc->base;
15298 crtc_state->base.state = state;
15299
15300 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15301
15302 crtc_state->base.enable = crtc_state->base.active =
15303 crtc->base.enabled = dev_priv->display.get_pipe_config(crtc, crtc_state);
15304
15305 /* update transitional state */
15306 crtc->active = crtc_state->base.active;
15307 crtc->config = crtc_state;
15308
15309 drm_plane_state = drm_atomic_get_plane_state(state, primary);
15310 if (IS_ERR(drm_plane_state))
15311 return PTR_ERR(drm_plane_state);
15312
15313 plane_state = to_intel_plane_state(drm_plane_state);
15314 plane_state->visible = primary_get_hw_state(crtc);
15315
15316 if (plane_state->visible) {
15317 primary->crtc = &crtc->base;
15318 crtc_state->base.plane_mask |= 1 << drm_plane_index(primary);
15319 } else
15320 crtc_state->base.plane_mask &= ~(1 << drm_plane_index(primary));
15321
15322 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15323 crtc->base.base.id,
15324 crtc_state->base.active ? "enabled" : "disabled");
15325
15326 return 0;
15327 }
15328
15329 static int readout_hw_pll_state(struct drm_atomic_state *state)
15330 {
15331 struct drm_i915_private *dev_priv = to_i915(state->dev);
15332 struct intel_shared_dpll_config *shared_dpll;
15333 struct intel_crtc *crtc;
15334 struct intel_crtc_state *crtc_state;
15335 int i;
15336
15337 shared_dpll = intel_atomic_get_shared_dpll_state(state);
15338 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15339 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15340
15341 pll->on = pll->get_hw_state(dev_priv, pll,
15342 &shared_dpll[i].hw_state);
15343
15344 pll->active = 0;
15345 shared_dpll[i].crtc_mask = 0;
15346
15347 for_each_intel_crtc(state->dev, crtc) {
15348 crtc_state = intel_atomic_get_crtc_state(state, crtc);
15349 if (IS_ERR(crtc_state))
15350 return PTR_ERR(crtc_state);
15351
15352 if (crtc_state->base.active &&
15353 crtc_state->shared_dpll == i) {
15354 pll->active++;
15355 shared_dpll[i].crtc_mask |=
15356 1 << crtc->pipe;
15357 }
15358 }
15359
15360 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15361 pll->name, shared_dpll[i].crtc_mask,
15362 pll->on);
15363
15364 if (shared_dpll[i].crtc_mask)
15365 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15366 }
15367
15368 return 0;
15369 }
15370
15371 static struct drm_connector_state *
15372 get_connector_state_for_encoder(struct drm_atomic_state *state,
15373 struct intel_encoder *encoder)
15374 {
15375 struct drm_connector *connector;
15376 struct drm_connector_state *connector_state;
15377 int i;
15378
15379 for_each_connector_in_state(state, connector, connector_state, i)
15380 if (connector_state->best_encoder == &encoder->base)
15381 return connector_state;
15382
15383 return NULL;
15384 }
15385
15386 static int readout_hw_connector_encoder_state(struct drm_atomic_state *state)
15387 {
15388 struct drm_device *dev = state->dev;
15389 struct drm_i915_private *dev_priv = to_i915(state->dev);
15390 struct intel_crtc *crtc;
15391 struct drm_crtc_state *drm_crtc_state;
15392 struct intel_crtc_state *crtc_state;
15393 struct intel_encoder *encoder;
15394 struct intel_connector *connector;
15395 struct drm_connector_state *connector_state;
15396 enum pipe pipe;
15397
15398 for_each_intel_connector(dev, connector) {
15399 connector_state =
15400 drm_atomic_get_connector_state(state, &connector->base);
15401 if (IS_ERR(connector_state))
15402 return PTR_ERR(connector_state);
15403
15404 if (connector->get_hw_state(connector)) {
15405 connector->base.dpms = DRM_MODE_DPMS_ON;
15406 connector->base.encoder = &connector->encoder->base;
15407 } else {
15408 connector->base.dpms = DRM_MODE_DPMS_OFF;
15409 connector->base.encoder = NULL;
15410 }
15411
15412 /* We'll update the crtc field when reading encoder state */
15413 connector_state->crtc = NULL;
15414
15415 connector_state->best_encoder = connector->base.encoder;
15416
15417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15418 connector->base.base.id,
15419 connector->base.name,
15420 connector->base.encoder ? "enabled" : "disabled");
15421 }
15422
15423 for_each_intel_encoder(dev, encoder) {
15424 pipe = 0;
15425
15426 connector_state =
15427 get_connector_state_for_encoder(state, encoder);
15428
15429 encoder->connectors_active = !!connector_state;
15430
15431 if (encoder->get_hw_state(encoder, &pipe)) {
15432 encoder->base.crtc =
15433 dev_priv->pipe_to_crtc_mapping[pipe];
15434 crtc = to_intel_crtc(encoder->base.crtc);
15435
15436 drm_crtc_state =
15437 state->crtc_states[drm_crtc_index(&crtc->base)];
15438 crtc_state = to_intel_crtc_state(drm_crtc_state);
15439
15440 encoder->get_config(encoder, crtc_state);
15441
15442 if (connector_state)
15443 connector_state->crtc = &crtc->base;
15444 } else {
15445 encoder->base.crtc = NULL;
15446 }
15447
15448 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15449 encoder->base.base.id,
15450 encoder->base.name,
15451 encoder->base.crtc ? "enabled" : "disabled",
15452 pipe_name(pipe));
15453 }
15454
15455 return 0;
15456 }
15457
15458 static struct drm_atomic_state *
15459 intel_modeset_readout_hw_state(struct drm_device *dev)
15460 {
15461 struct intel_crtc *crtc;
15462 int ret = 0;
15463
15464 struct drm_atomic_state *state;
15465
15466 state = drm_atomic_state_alloc(dev);
15467 if (!state)
15468 return ERR_PTR(-ENOMEM);
15469
15470 state->acquire_ctx = dev->mode_config.acquire_ctx;
15471
15472 for_each_intel_crtc(dev, crtc) {
15473 ret = readout_hw_crtc_state(state, crtc);
15474 if (ret)
15475 goto err_free;
15476 }
15477
15478 ret = readout_hw_pll_state(state);
15479 if (ret)
15480 goto err_free;
15481
15482 ret = readout_hw_connector_encoder_state(state);
15483 if (ret)
15484 goto err_free;
15485
15486 return state;
15487
15488 err_free:
15489 drm_atomic_state_free(state);
15490 return ERR_PTR(ret);
15491 }
15492
15493 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15494 * and i915 state tracking structures. */
15495 void intel_modeset_setup_hw_state(struct drm_device *dev,
15496 bool force_restore)
15497 {
15498 struct drm_i915_private *dev_priv = dev->dev_private;
15499 struct drm_crtc *crtc;
15500 struct drm_crtc_state *crtc_state;
15501 struct intel_encoder *encoder;
15502 struct drm_atomic_state *state;
15503 struct intel_shared_dpll_config shared_dplls[I915_NUM_PLLS];
15504 int i;
15505
15506 state = intel_modeset_readout_hw_state(dev);
15507 if (IS_ERR(state)) {
15508 DRM_ERROR("Failed to read out hw state\n");
15509 return;
15510 }
15511
15512 drm_atomic_helper_swap_state(dev, state);
15513
15514 /* swap sw/hw dpll state */
15515 intel_atomic_duplicate_dpll_state(dev_priv, shared_dplls);
15516 intel_shared_dpll_commit(state);
15517 memcpy(to_intel_atomic_state(state)->shared_dpll,
15518 shared_dplls, sizeof(*shared_dplls) * dev_priv->num_shared_dpll);
15519
15520 /* HW state is read out, now we need to sanitize this mess. */
15521 for_each_intel_encoder(dev, encoder) {
15522 intel_sanitize_encoder(encoder);
15523 }
15524
15525 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15527
15528 /* prevent unnneeded restores with force_restore */
15529 crtc_state->active_changed =
15530 crtc_state->mode_changed =
15531 crtc_state->planes_changed = false;
15532
15533 if (crtc->enabled) {
15534 intel_mode_from_pipe_config(&crtc->state->mode,
15535 to_intel_crtc_state(crtc->state));
15536
15537 drm_mode_copy(&crtc->mode, &crtc->state->mode);
15538 drm_mode_copy(&crtc->hwmode,
15539 &crtc->state->adjusted_mode);
15540 }
15541
15542 intel_sanitize_crtc(intel_crtc);
15543
15544 /*
15545 * sanitize_crtc may have forced an update of crtc->state,
15546 * so reload in intel_dump_pipe_config
15547 */
15548 intel_dump_pipe_config(intel_crtc,
15549 to_intel_crtc_state(crtc->state),
15550 "[setup_hw_state]");
15551 }
15552
15553 intel_modeset_update_connector_atomic_state(dev);
15554
15555 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15556 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15557
15558 if (!pll->on || pll->active)
15559 continue;
15560
15561 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15562
15563 pll->disable(dev_priv, pll);
15564 pll->on = false;
15565 }
15566
15567 if (IS_GEN9(dev))
15568 skl_wm_get_hw_state(dev);
15569 else if (HAS_PCH_SPLIT(dev))
15570 ilk_wm_get_hw_state(dev);
15571
15572 if (force_restore) {
15573 int ret;
15574
15575 i915_redisable_vga(dev);
15576
15577 ret = intel_set_mode(state);
15578 if (ret) {
15579 DRM_ERROR("Failed to restore previous mode\n");
15580 drm_atomic_state_free(state);
15581 }
15582 } else {
15583 drm_atomic_state_free(state);
15584 }
15585
15586 intel_modeset_check_state(dev);
15587 }
15588
15589 void intel_modeset_gem_init(struct drm_device *dev)
15590 {
15591 struct drm_i915_private *dev_priv = dev->dev_private;
15592 struct drm_crtc *c;
15593 struct drm_i915_gem_object *obj;
15594 int ret;
15595
15596 mutex_lock(&dev->struct_mutex);
15597 intel_init_gt_powersave(dev);
15598 mutex_unlock(&dev->struct_mutex);
15599
15600 /*
15601 * There may be no VBT; and if the BIOS enabled SSC we can
15602 * just keep using it to avoid unnecessary flicker. Whereas if the
15603 * BIOS isn't using it, don't assume it will work even if the VBT
15604 * indicates as much.
15605 */
15606 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15607 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15608 DREF_SSC1_ENABLE);
15609
15610 intel_modeset_init_hw(dev);
15611
15612 intel_setup_overlay(dev);
15613
15614 /*
15615 * Make sure any fbs we allocated at startup are properly
15616 * pinned & fenced. When we do the allocation it's too early
15617 * for this.
15618 */
15619 for_each_crtc(dev, c) {
15620 obj = intel_fb_obj(c->primary->fb);
15621 if (obj == NULL)
15622 continue;
15623
15624 mutex_lock(&dev->struct_mutex);
15625 ret = intel_pin_and_fence_fb_obj(c->primary,
15626 c->primary->fb,
15627 c->primary->state,
15628 NULL);
15629 mutex_unlock(&dev->struct_mutex);
15630 if (ret) {
15631 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15632 to_intel_crtc(c)->pipe);
15633 drm_framebuffer_unreference(c->primary->fb);
15634 c->primary->fb = NULL;
15635 c->primary->crtc = c->primary->state->crtc = NULL;
15636 update_state_fb(c->primary);
15637 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15638 }
15639 }
15640
15641 intel_backlight_register(dev);
15642 }
15643
15644 void intel_connector_unregister(struct intel_connector *intel_connector)
15645 {
15646 struct drm_connector *connector = &intel_connector->base;
15647
15648 intel_panel_destroy_backlight(connector);
15649 drm_connector_unregister(connector);
15650 }
15651
15652 void intel_modeset_cleanup(struct drm_device *dev)
15653 {
15654 struct drm_i915_private *dev_priv = dev->dev_private;
15655 struct drm_connector *connector;
15656
15657 intel_disable_gt_powersave(dev);
15658
15659 intel_backlight_unregister(dev);
15660
15661 /*
15662 * Interrupts and polling as the first thing to avoid creating havoc.
15663 * Too much stuff here (turning of connectors, ...) would
15664 * experience fancy races otherwise.
15665 */
15666 intel_irq_uninstall(dev_priv);
15667
15668 /*
15669 * Due to the hpd irq storm handling the hotplug work can re-arm the
15670 * poll handlers. Hence disable polling after hpd handling is shut down.
15671 */
15672 drm_kms_helper_poll_fini(dev);
15673
15674 mutex_lock(&dev->struct_mutex);
15675
15676 intel_unregister_dsm_handler();
15677
15678 intel_fbc_disable(dev);
15679
15680 mutex_unlock(&dev->struct_mutex);
15681
15682 /* flush any delayed tasks or pending work */
15683 flush_scheduled_work();
15684
15685 /* destroy the backlight and sysfs files before encoders/connectors */
15686 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15687 struct intel_connector *intel_connector;
15688
15689 intel_connector = to_intel_connector(connector);
15690 intel_connector->unregister(intel_connector);
15691 }
15692
15693 drm_mode_config_cleanup(dev);
15694
15695 intel_cleanup_overlay(dev);
15696
15697 mutex_lock(&dev->struct_mutex);
15698 intel_cleanup_gt_powersave(dev);
15699 mutex_unlock(&dev->struct_mutex);
15700 }
15701
15702 /*
15703 * Return which encoder is currently attached for connector.
15704 */
15705 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15706 {
15707 return &intel_attached_encoder(connector)->base;
15708 }
15709
15710 void intel_connector_attach_encoder(struct intel_connector *connector,
15711 struct intel_encoder *encoder)
15712 {
15713 connector->encoder = encoder;
15714 drm_mode_connector_attach_encoder(&connector->base,
15715 &encoder->base);
15716 }
15717
15718 /*
15719 * set vga decode state - true == enable VGA decode
15720 */
15721 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15722 {
15723 struct drm_i915_private *dev_priv = dev->dev_private;
15724 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15725 u16 gmch_ctrl;
15726
15727 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15728 DRM_ERROR("failed to read control word\n");
15729 return -EIO;
15730 }
15731
15732 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15733 return 0;
15734
15735 if (state)
15736 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15737 else
15738 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15739
15740 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15741 DRM_ERROR("failed to write control word\n");
15742 return -EIO;
15743 }
15744
15745 return 0;
15746 }
15747
15748 struct intel_display_error_state {
15749
15750 u32 power_well_driver;
15751
15752 int num_transcoders;
15753
15754 struct intel_cursor_error_state {
15755 u32 control;
15756 u32 position;
15757 u32 base;
15758 u32 size;
15759 } cursor[I915_MAX_PIPES];
15760
15761 struct intel_pipe_error_state {
15762 bool power_domain_on;
15763 u32 source;
15764 u32 stat;
15765 } pipe[I915_MAX_PIPES];
15766
15767 struct intel_plane_error_state {
15768 u32 control;
15769 u32 stride;
15770 u32 size;
15771 u32 pos;
15772 u32 addr;
15773 u32 surface;
15774 u32 tile_offset;
15775 } plane[I915_MAX_PIPES];
15776
15777 struct intel_transcoder_error_state {
15778 bool power_domain_on;
15779 enum transcoder cpu_transcoder;
15780
15781 u32 conf;
15782
15783 u32 htotal;
15784 u32 hblank;
15785 u32 hsync;
15786 u32 vtotal;
15787 u32 vblank;
15788 u32 vsync;
15789 } transcoder[4];
15790 };
15791
15792 struct intel_display_error_state *
15793 intel_display_capture_error_state(struct drm_device *dev)
15794 {
15795 struct drm_i915_private *dev_priv = dev->dev_private;
15796 struct intel_display_error_state *error;
15797 int transcoders[] = {
15798 TRANSCODER_A,
15799 TRANSCODER_B,
15800 TRANSCODER_C,
15801 TRANSCODER_EDP,
15802 };
15803 int i;
15804
15805 if (INTEL_INFO(dev)->num_pipes == 0)
15806 return NULL;
15807
15808 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15809 if (error == NULL)
15810 return NULL;
15811
15812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15813 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15814
15815 for_each_pipe(dev_priv, i) {
15816 error->pipe[i].power_domain_on =
15817 __intel_display_power_is_enabled(dev_priv,
15818 POWER_DOMAIN_PIPE(i));
15819 if (!error->pipe[i].power_domain_on)
15820 continue;
15821
15822 error->cursor[i].control = I915_READ(CURCNTR(i));
15823 error->cursor[i].position = I915_READ(CURPOS(i));
15824 error->cursor[i].base = I915_READ(CURBASE(i));
15825
15826 error->plane[i].control = I915_READ(DSPCNTR(i));
15827 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15828 if (INTEL_INFO(dev)->gen <= 3) {
15829 error->plane[i].size = I915_READ(DSPSIZE(i));
15830 error->plane[i].pos = I915_READ(DSPPOS(i));
15831 }
15832 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15833 error->plane[i].addr = I915_READ(DSPADDR(i));
15834 if (INTEL_INFO(dev)->gen >= 4) {
15835 error->plane[i].surface = I915_READ(DSPSURF(i));
15836 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15837 }
15838
15839 error->pipe[i].source = I915_READ(PIPESRC(i));
15840
15841 if (HAS_GMCH_DISPLAY(dev))
15842 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15843 }
15844
15845 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15846 if (HAS_DDI(dev_priv->dev))
15847 error->num_transcoders++; /* Account for eDP. */
15848
15849 for (i = 0; i < error->num_transcoders; i++) {
15850 enum transcoder cpu_transcoder = transcoders[i];
15851
15852 error->transcoder[i].power_domain_on =
15853 __intel_display_power_is_enabled(dev_priv,
15854 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15855 if (!error->transcoder[i].power_domain_on)
15856 continue;
15857
15858 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15859
15860 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15861 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15862 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15863 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15864 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15865 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15866 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15867 }
15868
15869 return error;
15870 }
15871
15872 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15873
15874 void
15875 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15876 struct drm_device *dev,
15877 struct intel_display_error_state *error)
15878 {
15879 struct drm_i915_private *dev_priv = dev->dev_private;
15880 int i;
15881
15882 if (!error)
15883 return;
15884
15885 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15886 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15887 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15888 error->power_well_driver);
15889 for_each_pipe(dev_priv, i) {
15890 err_printf(m, "Pipe [%d]:\n", i);
15891 err_printf(m, " Power: %s\n",
15892 error->pipe[i].power_domain_on ? "on" : "off");
15893 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15894 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15895
15896 err_printf(m, "Plane [%d]:\n", i);
15897 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15898 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15899 if (INTEL_INFO(dev)->gen <= 3) {
15900 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15901 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15902 }
15903 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15904 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15905 if (INTEL_INFO(dev)->gen >= 4) {
15906 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15907 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15908 }
15909
15910 err_printf(m, "Cursor [%d]:\n", i);
15911 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15912 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15913 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15914 }
15915
15916 for (i = 0; i < error->num_transcoders; i++) {
15917 err_printf(m, "CPU transcoder: %c\n",
15918 transcoder_name(error->transcoder[i].cpu_transcoder));
15919 err_printf(m, " Power: %s\n",
15920 error->transcoder[i].power_domain_on ? "on" : "off");
15921 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15922 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15923 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15924 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15925 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15926 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15927 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15928 }
15929 }
15930
15931 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15932 {
15933 struct intel_crtc *crtc;
15934
15935 for_each_intel_crtc(dev, crtc) {
15936 struct intel_unpin_work *work;
15937
15938 spin_lock_irq(&dev->event_lock);
15939
15940 work = crtc->unpin_work;
15941
15942 if (work && work->event &&
15943 work->event->base.file_priv == file) {
15944 kfree(work->event);
15945 work->event = NULL;
15946 }
15947
15948 spin_unlock_irq(&dev->event_lock);
15949 }
15950 }
Linux kernel - Deliverables
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