2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
78 static const uint32_t intel_cursor_formats
[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
84 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
85 struct intel_crtc_state
*pipe_config
);
86 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
87 struct intel_crtc_state
*pipe_config
);
89 static int intel_set_mode(struct drm_atomic_state
*state
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
103 const struct intel_crtc_state
*pipe_config
);
104 static void chv_prepare_pll(struct intel_crtc
*crtc
,
105 const struct intel_crtc_state
*pipe_config
);
106 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
107 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
108 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
109 struct intel_crtc_state
*crtc_state
);
110 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
112 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
113 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
115 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
117 if (!connector
->mst_port
)
118 return connector
->encoder
;
120 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
129 int p2_slow
, p2_fast
;
132 typedef struct intel_limit intel_limit_t
;
134 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
139 intel_pch_rawclk(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 WARN_ON(!HAS_PCH_SPLIT(dev
));
145 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
148 static inline u32
/* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device
*dev
)
152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
153 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
158 static const intel_limit_t intel_limits_i8xx_dac
= {
159 .dot
= { .min
= 25000, .max
= 350000 },
160 .vco
= { .min
= 908000, .max
= 1512000 },
161 .n
= { .min
= 2, .max
= 16 },
162 .m
= { .min
= 96, .max
= 140 },
163 .m1
= { .min
= 18, .max
= 26 },
164 .m2
= { .min
= 6, .max
= 16 },
165 .p
= { .min
= 4, .max
= 128 },
166 .p1
= { .min
= 2, .max
= 33 },
167 .p2
= { .dot_limit
= 165000,
168 .p2_slow
= 4, .p2_fast
= 2 },
171 static const intel_limit_t intel_limits_i8xx_dvo
= {
172 .dot
= { .min
= 25000, .max
= 350000 },
173 .vco
= { .min
= 908000, .max
= 1512000 },
174 .n
= { .min
= 2, .max
= 16 },
175 .m
= { .min
= 96, .max
= 140 },
176 .m1
= { .min
= 18, .max
= 26 },
177 .m2
= { .min
= 6, .max
= 16 },
178 .p
= { .min
= 4, .max
= 128 },
179 .p1
= { .min
= 2, .max
= 33 },
180 .p2
= { .dot_limit
= 165000,
181 .p2_slow
= 4, .p2_fast
= 4 },
184 static const intel_limit_t intel_limits_i8xx_lvds
= {
185 .dot
= { .min
= 25000, .max
= 350000 },
186 .vco
= { .min
= 908000, .max
= 1512000 },
187 .n
= { .min
= 2, .max
= 16 },
188 .m
= { .min
= 96, .max
= 140 },
189 .m1
= { .min
= 18, .max
= 26 },
190 .m2
= { .min
= 6, .max
= 16 },
191 .p
= { .min
= 4, .max
= 128 },
192 .p1
= { .min
= 1, .max
= 6 },
193 .p2
= { .dot_limit
= 165000,
194 .p2_slow
= 14, .p2_fast
= 7 },
197 static const intel_limit_t intel_limits_i9xx_sdvo
= {
198 .dot
= { .min
= 20000, .max
= 400000 },
199 .vco
= { .min
= 1400000, .max
= 2800000 },
200 .n
= { .min
= 1, .max
= 6 },
201 .m
= { .min
= 70, .max
= 120 },
202 .m1
= { .min
= 8, .max
= 18 },
203 .m2
= { .min
= 3, .max
= 7 },
204 .p
= { .min
= 5, .max
= 80 },
205 .p1
= { .min
= 1, .max
= 8 },
206 .p2
= { .dot_limit
= 200000,
207 .p2_slow
= 10, .p2_fast
= 5 },
210 static const intel_limit_t intel_limits_i9xx_lvds
= {
211 .dot
= { .min
= 20000, .max
= 400000 },
212 .vco
= { .min
= 1400000, .max
= 2800000 },
213 .n
= { .min
= 1, .max
= 6 },
214 .m
= { .min
= 70, .max
= 120 },
215 .m1
= { .min
= 8, .max
= 18 },
216 .m2
= { .min
= 3, .max
= 7 },
217 .p
= { .min
= 7, .max
= 98 },
218 .p1
= { .min
= 1, .max
= 8 },
219 .p2
= { .dot_limit
= 112000,
220 .p2_slow
= 14, .p2_fast
= 7 },
224 static const intel_limit_t intel_limits_g4x_sdvo
= {
225 .dot
= { .min
= 25000, .max
= 270000 },
226 .vco
= { .min
= 1750000, .max
= 3500000},
227 .n
= { .min
= 1, .max
= 4 },
228 .m
= { .min
= 104, .max
= 138 },
229 .m1
= { .min
= 17, .max
= 23 },
230 .m2
= { .min
= 5, .max
= 11 },
231 .p
= { .min
= 10, .max
= 30 },
232 .p1
= { .min
= 1, .max
= 3},
233 .p2
= { .dot_limit
= 270000,
239 static const intel_limit_t intel_limits_g4x_hdmi
= {
240 .dot
= { .min
= 22000, .max
= 400000 },
241 .vco
= { .min
= 1750000, .max
= 3500000},
242 .n
= { .min
= 1, .max
= 4 },
243 .m
= { .min
= 104, .max
= 138 },
244 .m1
= { .min
= 16, .max
= 23 },
245 .m2
= { .min
= 5, .max
= 11 },
246 .p
= { .min
= 5, .max
= 80 },
247 .p1
= { .min
= 1, .max
= 8},
248 .p2
= { .dot_limit
= 165000,
249 .p2_slow
= 10, .p2_fast
= 5 },
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
253 .dot
= { .min
= 20000, .max
= 115000 },
254 .vco
= { .min
= 1750000, .max
= 3500000 },
255 .n
= { .min
= 1, .max
= 3 },
256 .m
= { .min
= 104, .max
= 138 },
257 .m1
= { .min
= 17, .max
= 23 },
258 .m2
= { .min
= 5, .max
= 11 },
259 .p
= { .min
= 28, .max
= 112 },
260 .p1
= { .min
= 2, .max
= 8 },
261 .p2
= { .dot_limit
= 0,
262 .p2_slow
= 14, .p2_fast
= 14
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
267 .dot
= { .min
= 80000, .max
= 224000 },
268 .vco
= { .min
= 1750000, .max
= 3500000 },
269 .n
= { .min
= 1, .max
= 3 },
270 .m
= { .min
= 104, .max
= 138 },
271 .m1
= { .min
= 17, .max
= 23 },
272 .m2
= { .min
= 5, .max
= 11 },
273 .p
= { .min
= 14, .max
= 42 },
274 .p1
= { .min
= 2, .max
= 6 },
275 .p2
= { .dot_limit
= 0,
276 .p2_slow
= 7, .p2_fast
= 7
280 static const intel_limit_t intel_limits_pineview_sdvo
= {
281 .dot
= { .min
= 20000, .max
= 400000},
282 .vco
= { .min
= 1700000, .max
= 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n
= { .min
= 3, .max
= 6 },
285 .m
= { .min
= 2, .max
= 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1
= { .min
= 0, .max
= 0 },
288 .m2
= { .min
= 0, .max
= 254 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 200000,
292 .p2_slow
= 10, .p2_fast
= 5 },
295 static const intel_limit_t intel_limits_pineview_lvds
= {
296 .dot
= { .min
= 20000, .max
= 400000 },
297 .vco
= { .min
= 1700000, .max
= 3500000 },
298 .n
= { .min
= 3, .max
= 6 },
299 .m
= { .min
= 2, .max
= 256 },
300 .m1
= { .min
= 0, .max
= 0 },
301 .m2
= { .min
= 0, .max
= 254 },
302 .p
= { .min
= 7, .max
= 112 },
303 .p1
= { .min
= 1, .max
= 8 },
304 .p2
= { .dot_limit
= 112000,
305 .p2_slow
= 14, .p2_fast
= 14 },
308 /* Ironlake / Sandybridge
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
313 static const intel_limit_t intel_limits_ironlake_dac
= {
314 .dot
= { .min
= 25000, .max
= 350000 },
315 .vco
= { .min
= 1760000, .max
= 3510000 },
316 .n
= { .min
= 1, .max
= 5 },
317 .m
= { .min
= 79, .max
= 127 },
318 .m1
= { .min
= 12, .max
= 22 },
319 .m2
= { .min
= 5, .max
= 9 },
320 .p
= { .min
= 5, .max
= 80 },
321 .p1
= { .min
= 1, .max
= 8 },
322 .p2
= { .dot_limit
= 225000,
323 .p2_slow
= 10, .p2_fast
= 5 },
326 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
327 .dot
= { .min
= 25000, .max
= 350000 },
328 .vco
= { .min
= 1760000, .max
= 3510000 },
329 .n
= { .min
= 1, .max
= 3 },
330 .m
= { .min
= 79, .max
= 118 },
331 .m1
= { .min
= 12, .max
= 22 },
332 .m2
= { .min
= 5, .max
= 9 },
333 .p
= { .min
= 28, .max
= 112 },
334 .p1
= { .min
= 2, .max
= 8 },
335 .p2
= { .dot_limit
= 225000,
336 .p2_slow
= 14, .p2_fast
= 14 },
339 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 127 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 56 },
347 .p1
= { .min
= 2, .max
= 8 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000 },
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 79, .max
= 126 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 28, .max
= 112 },
361 .p1
= { .min
= 2, .max
= 8 },
362 .p2
= { .dot_limit
= 225000,
363 .p2_slow
= 14, .p2_fast
= 14 },
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
367 .dot
= { .min
= 25000, .max
= 350000 },
368 .vco
= { .min
= 1760000, .max
= 3510000 },
369 .n
= { .min
= 1, .max
= 3 },
370 .m
= { .min
= 79, .max
= 126 },
371 .m1
= { .min
= 12, .max
= 22 },
372 .m2
= { .min
= 5, .max
= 9 },
373 .p
= { .min
= 14, .max
= 42 },
374 .p1
= { .min
= 2, .max
= 6 },
375 .p2
= { .dot_limit
= 225000,
376 .p2_slow
= 7, .p2_fast
= 7 },
379 static const intel_limit_t intel_limits_vlv
= {
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
386 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
387 .vco
= { .min
= 4000000, .max
= 6000000 },
388 .n
= { .min
= 1, .max
= 7 },
389 .m1
= { .min
= 2, .max
= 3 },
390 .m2
= { .min
= 11, .max
= 156 },
391 .p1
= { .min
= 2, .max
= 3 },
392 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
395 static const intel_limit_t intel_limits_chv
= {
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
402 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
403 .vco
= { .min
= 4800000, .max
= 6480000 },
404 .n
= { .min
= 1, .max
= 1 },
405 .m1
= { .min
= 2, .max
= 2 },
406 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
407 .p1
= { .min
= 2, .max
= 4 },
408 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
411 static const intel_limit_t intel_limits_bxt
= {
412 /* FIXME: find real dot limits */
413 .dot
= { .min
= 0, .max
= INT_MAX
},
414 .vco
= { .min
= 4800000, .max
= 6480000 },
415 .n
= { .min
= 1, .max
= 1 },
416 .m1
= { .min
= 2, .max
= 2 },
417 /* FIXME: find real m2 limits */
418 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
419 .p1
= { .min
= 2, .max
= 4 },
420 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
423 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
425 clock
->m
= clock
->m1
* clock
->m2
;
426 clock
->p
= clock
->p1
* clock
->p2
;
427 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
429 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
430 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
434 needs_modeset(struct drm_crtc_state
*state
)
436 return state
->mode_changed
|| state
->active_changed
;
440 * Returns whether any output on the specified pipe is of the specified type
442 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
444 struct drm_device
*dev
= crtc
->base
.dev
;
445 struct intel_encoder
*encoder
;
447 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
448 if (encoder
->type
== type
)
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
463 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
464 struct drm_connector
*connector
;
465 struct drm_connector_state
*connector_state
;
466 struct intel_encoder
*encoder
;
467 int i
, num_connectors
= 0;
469 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
470 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
475 encoder
= to_intel_encoder(connector_state
->best_encoder
);
476 if (encoder
->type
== type
)
480 WARN_ON(num_connectors
== 0);
485 static const intel_limit_t
*
486 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
488 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
489 const intel_limit_t
*limit
;
491 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
492 if (intel_is_dual_link_lvds(dev
)) {
493 if (refclk
== 100000)
494 limit
= &intel_limits_ironlake_dual_lvds_100m
;
496 limit
= &intel_limits_ironlake_dual_lvds
;
498 if (refclk
== 100000)
499 limit
= &intel_limits_ironlake_single_lvds_100m
;
501 limit
= &intel_limits_ironlake_single_lvds
;
504 limit
= &intel_limits_ironlake_dac
;
509 static const intel_limit_t
*
510 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
512 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
513 const intel_limit_t
*limit
;
515 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
516 if (intel_is_dual_link_lvds(dev
))
517 limit
= &intel_limits_g4x_dual_channel_lvds
;
519 limit
= &intel_limits_g4x_single_channel_lvds
;
520 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
521 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
522 limit
= &intel_limits_g4x_hdmi
;
523 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
524 limit
= &intel_limits_g4x_sdvo
;
525 } else /* The option is for other outputs */
526 limit
= &intel_limits_i9xx_sdvo
;
531 static const intel_limit_t
*
532 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
534 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
535 const intel_limit_t
*limit
;
538 limit
= &intel_limits_bxt
;
539 else if (HAS_PCH_SPLIT(dev
))
540 limit
= intel_ironlake_limit(crtc_state
, refclk
);
541 else if (IS_G4X(dev
)) {
542 limit
= intel_g4x_limit(crtc_state
);
543 } else if (IS_PINEVIEW(dev
)) {
544 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
545 limit
= &intel_limits_pineview_lvds
;
547 limit
= &intel_limits_pineview_sdvo
;
548 } else if (IS_CHERRYVIEW(dev
)) {
549 limit
= &intel_limits_chv
;
550 } else if (IS_VALLEYVIEW(dev
)) {
551 limit
= &intel_limits_vlv
;
552 } else if (!IS_GEN2(dev
)) {
553 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
554 limit
= &intel_limits_i9xx_lvds
;
556 limit
= &intel_limits_i9xx_sdvo
;
558 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
559 limit
= &intel_limits_i8xx_lvds
;
560 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
561 limit
= &intel_limits_i8xx_dvo
;
563 limit
= &intel_limits_i8xx_dac
;
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
571 clock
->m
= clock
->m2
+ 2;
572 clock
->p
= clock
->p1
* clock
->p2
;
573 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
575 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
576 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
579 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
581 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
584 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
586 clock
->m
= i9xx_dpll_compute_m(clock
);
587 clock
->p
= clock
->p1
* clock
->p2
;
588 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
590 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
591 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
594 static void chv_clock(int refclk
, intel_clock_t
*clock
)
596 clock
->m
= clock
->m1
* clock
->m2
;
597 clock
->p
= clock
->p1
* clock
->p2
;
598 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
600 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
602 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
611 static bool intel_PLL_is_valid(struct drm_device
*dev
,
612 const intel_limit_t
*limit
,
613 const intel_clock_t
*clock
)
615 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
616 INTELPllInvalid("n out of range\n");
617 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
622 INTELPllInvalid("m1 out of range\n");
624 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
625 if (clock
->m1
<= clock
->m2
)
626 INTELPllInvalid("m1 <= m2\n");
628 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
629 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
630 INTELPllInvalid("p out of range\n");
631 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
632 INTELPllInvalid("m out of range\n");
635 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
640 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
641 INTELPllInvalid("dot out of range\n");
647 i9xx_find_best_dpll(const intel_limit_t
*limit
,
648 struct intel_crtc_state
*crtc_state
,
649 int target
, int refclk
, intel_clock_t
*match_clock
,
650 intel_clock_t
*best_clock
)
652 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
653 struct drm_device
*dev
= crtc
->base
.dev
;
657 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
663 if (intel_is_dual_link_lvds(dev
))
664 clock
.p2
= limit
->p2
.p2_fast
;
666 clock
.p2
= limit
->p2
.p2_slow
;
668 if (target
< limit
->p2
.dot_limit
)
669 clock
.p2
= limit
->p2
.p2_slow
;
671 clock
.p2
= limit
->p2
.p2_fast
;
674 memset(best_clock
, 0, sizeof(*best_clock
));
676 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
678 for (clock
.m2
= limit
->m2
.min
;
679 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
680 if (clock
.m2
>= clock
.m1
)
682 for (clock
.n
= limit
->n
.min
;
683 clock
.n
<= limit
->n
.max
; clock
.n
++) {
684 for (clock
.p1
= limit
->p1
.min
;
685 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
688 i9xx_clock(refclk
, &clock
);
689 if (!intel_PLL_is_valid(dev
, limit
,
693 clock
.p
!= match_clock
->p
)
696 this_err
= abs(clock
.dot
- target
);
697 if (this_err
< err
) {
706 return (err
!= target
);
710 pnv_find_best_dpll(const intel_limit_t
*limit
,
711 struct intel_crtc_state
*crtc_state
,
712 int target
, int refclk
, intel_clock_t
*match_clock
,
713 intel_clock_t
*best_clock
)
715 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
716 struct drm_device
*dev
= crtc
->base
.dev
;
720 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
726 if (intel_is_dual_link_lvds(dev
))
727 clock
.p2
= limit
->p2
.p2_fast
;
729 clock
.p2
= limit
->p2
.p2_slow
;
731 if (target
< limit
->p2
.dot_limit
)
732 clock
.p2
= limit
->p2
.p2_slow
;
734 clock
.p2
= limit
->p2
.p2_fast
;
737 memset(best_clock
, 0, sizeof(*best_clock
));
739 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
741 for (clock
.m2
= limit
->m2
.min
;
742 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
743 for (clock
.n
= limit
->n
.min
;
744 clock
.n
<= limit
->n
.max
; clock
.n
++) {
745 for (clock
.p1
= limit
->p1
.min
;
746 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
749 pineview_clock(refclk
, &clock
);
750 if (!intel_PLL_is_valid(dev
, limit
,
754 clock
.p
!= match_clock
->p
)
757 this_err
= abs(clock
.dot
- target
);
758 if (this_err
< err
) {
767 return (err
!= target
);
771 g4x_find_best_dpll(const intel_limit_t
*limit
,
772 struct intel_crtc_state
*crtc_state
,
773 int target
, int refclk
, intel_clock_t
*match_clock
,
774 intel_clock_t
*best_clock
)
776 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
777 struct drm_device
*dev
= crtc
->base
.dev
;
781 /* approximately equals target * 0.00585 */
782 int err_most
= (target
>> 8) + (target
>> 9);
785 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
786 if (intel_is_dual_link_lvds(dev
))
787 clock
.p2
= limit
->p2
.p2_fast
;
789 clock
.p2
= limit
->p2
.p2_slow
;
791 if (target
< limit
->p2
.dot_limit
)
792 clock
.p2
= limit
->p2
.p2_slow
;
794 clock
.p2
= limit
->p2
.p2_fast
;
797 memset(best_clock
, 0, sizeof(*best_clock
));
798 max_n
= limit
->n
.max
;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock
.m1
= limit
->m1
.max
;
803 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
804 for (clock
.m2
= limit
->m2
.max
;
805 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
806 for (clock
.p1
= limit
->p1
.max
;
807 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
810 i9xx_clock(refclk
, &clock
);
811 if (!intel_PLL_is_valid(dev
, limit
,
815 this_err
= abs(clock
.dot
- target
);
816 if (this_err
< err_most
) {
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
833 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
834 const intel_clock_t
*calculated_clock
,
835 const intel_clock_t
*best_clock
,
836 unsigned int best_error_ppm
,
837 unsigned int *error_ppm
)
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
843 if (IS_CHERRYVIEW(dev
)) {
846 return calculated_clock
->p
> best_clock
->p
;
849 if (WARN_ON_ONCE(!target_freq
))
852 *error_ppm
= div_u64(1000000ULL *
853 abs(target_freq
- calculated_clock
->dot
),
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
860 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
866 return *error_ppm
+ 10 < best_error_ppm
;
870 vlv_find_best_dpll(const intel_limit_t
*limit
,
871 struct intel_crtc_state
*crtc_state
,
872 int target
, int refclk
, intel_clock_t
*match_clock
,
873 intel_clock_t
*best_clock
)
875 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
876 struct drm_device
*dev
= crtc
->base
.dev
;
878 unsigned int bestppm
= 1000000;
879 /* min update 19.2 MHz */
880 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
883 target
*= 5; /* fast clock */
885 memset(best_clock
, 0, sizeof(*best_clock
));
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
889 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
890 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
891 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
892 clock
.p
= clock
.p1
* clock
.p2
;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
897 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
900 vlv_clock(refclk
, &clock
);
902 if (!intel_PLL_is_valid(dev
, limit
,
906 if (!vlv_PLL_is_optimal(dev
, target
,
924 chv_find_best_dpll(const intel_limit_t
*limit
,
925 struct intel_crtc_state
*crtc_state
,
926 int target
, int refclk
, intel_clock_t
*match_clock
,
927 intel_clock_t
*best_clock
)
929 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
930 struct drm_device
*dev
= crtc
->base
.dev
;
931 unsigned int best_error_ppm
;
936 memset(best_clock
, 0, sizeof(*best_clock
));
937 best_error_ppm
= 1000000;
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
944 clock
.n
= 1, clock
.m1
= 2;
945 target
*= 5; /* fast clock */
947 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
948 for (clock
.p2
= limit
->p2
.p2_fast
;
949 clock
.p2
>= limit
->p2
.p2_slow
;
950 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
951 unsigned int error_ppm
;
953 clock
.p
= clock
.p1
* clock
.p2
;
955 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
956 clock
.n
) << 22, refclk
* clock
.m1
);
958 if (m2
> INT_MAX
/clock
.m1
)
963 chv_clock(refclk
, &clock
);
965 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
968 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
969 best_error_ppm
, &error_ppm
))
973 best_error_ppm
= error_ppm
;
981 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
982 intel_clock_t
*best_clock
)
984 int refclk
= i9xx_get_refclk(crtc_state
, 0);
986 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
987 target_clock
, refclk
, NULL
, best_clock
);
990 bool intel_crtc_active(struct drm_crtc
*crtc
)
992 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1007 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1008 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1011 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1014 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1017 return intel_crtc
->config
->cpu_transcoder
;
1020 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1023 u32 reg
= PIPEDSL(pipe
);
1028 line_mask
= DSL_LINEMASK_GEN2
;
1030 line_mask
= DSL_LINEMASK_GEN3
;
1032 line1
= I915_READ(reg
) & line_mask
;
1034 line2
= I915_READ(reg
) & line_mask
;
1036 return line1
== line2
;
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1055 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1057 struct drm_device
*dev
= crtc
->base
.dev
;
1058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1059 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1060 enum pipe pipe
= crtc
->pipe
;
1062 if (INTEL_INFO(dev
)->gen
>= 4) {
1063 int reg
= PIPECONF(cpu_transcoder
);
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1068 WARN(1, "pipe_off wait timed out\n");
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1081 * Returns true if @port is connected, false otherwise.
1083 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1084 struct intel_digital_port
*port
)
1088 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1089 switch (port
->port
) {
1091 bit
= SDE_PORTB_HOTPLUG
;
1094 bit
= SDE_PORTC_HOTPLUG
;
1097 bit
= SDE_PORTD_HOTPLUG
;
1103 switch (port
->port
) {
1105 bit
= SDE_PORTB_HOTPLUG_CPT
;
1108 bit
= SDE_PORTC_HOTPLUG_CPT
;
1111 bit
= SDE_PORTD_HOTPLUG_CPT
;
1118 return I915_READ(SDEISR
) & bit
;
1121 static const char *state_string(bool enabled
)
1123 return enabled
? "on" : "off";
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private
*dev_priv
,
1128 enum pipe pipe
, bool state
)
1135 val
= I915_READ(reg
);
1136 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1137 I915_STATE_WARN(cur_state
!= state
,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1148 mutex_lock(&dev_priv
->sb_lock
);
1149 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1150 mutex_unlock(&dev_priv
->sb_lock
);
1152 cur_state
= val
& DSI_PLL_VCO_EN
;
1153 I915_STATE_WARN(cur_state
!= state
,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state
), state_string(cur_state
));
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1160 struct intel_shared_dpll
*
1161 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1163 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1165 if (crtc
->config
->shared_dpll
< 0)
1168 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1172 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1173 struct intel_shared_dpll
*pll
,
1177 struct intel_dpll_hw_state hw_state
;
1180 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1183 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1184 I915_STATE_WARN(cur_state
!= state
,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll
->name
, state_string(state
), state_string(cur_state
));
1189 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1190 enum pipe pipe
, bool state
)
1195 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1198 if (HAS_DDI(dev_priv
->dev
)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1201 val
= I915_READ(reg
);
1202 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1204 reg
= FDI_TX_CTL(pipe
);
1205 val
= I915_READ(reg
);
1206 cur_state
= !!(val
& FDI_TX_ENABLE
);
1208 I915_STATE_WARN(cur_state
!= state
,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state
), state_string(cur_state
));
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1215 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1216 enum pipe pipe
, bool state
)
1222 reg
= FDI_RX_CTL(pipe
);
1223 val
= I915_READ(reg
);
1224 cur_state
= !!(val
& FDI_RX_ENABLE
);
1225 I915_STATE_WARN(cur_state
!= state
,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state
), state_string(cur_state
));
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv
->dev
))
1246 reg
= FDI_TX_CTL(pipe
);
1247 val
= I915_READ(reg
);
1248 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1251 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1252 enum pipe pipe
, bool state
)
1258 reg
= FDI_RX_CTL(pipe
);
1259 val
= I915_READ(reg
);
1260 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1261 I915_STATE_WARN(cur_state
!= state
,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state
), state_string(cur_state
));
1266 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1269 struct drm_device
*dev
= dev_priv
->dev
;
1272 enum pipe panel_pipe
= PIPE_A
;
1275 if (WARN_ON(HAS_DDI(dev
)))
1278 if (HAS_PCH_SPLIT(dev
)) {
1281 pp_reg
= PCH_PP_CONTROL
;
1282 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1284 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1285 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1286 panel_pipe
= PIPE_B
;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev
)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1293 pp_reg
= PP_CONTROL
;
1294 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1295 panel_pipe
= PIPE_B
;
1298 val
= I915_READ(pp_reg
);
1299 if (!(val
& PANEL_POWER_ON
) ||
1300 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1303 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1304 "panel assertion failure, pipe %c regs locked\n",
1308 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1309 enum pipe pipe
, bool state
)
1311 struct drm_device
*dev
= dev_priv
->dev
;
1314 if (IS_845G(dev
) || IS_I865G(dev
))
1315 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1317 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1319 I915_STATE_WARN(cur_state
!= state
,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326 void assert_pipe(struct drm_i915_private
*dev_priv
,
1327 enum pipe pipe
, bool state
)
1332 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1337 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1340 if (!intel_display_power_is_enabled(dev_priv
,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1344 reg
= PIPECONF(cpu_transcoder
);
1345 val
= I915_READ(reg
);
1346 cur_state
= !!(val
& PIPECONF_ENABLE
);
1349 I915_STATE_WARN(cur_state
!= state
,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1354 static void assert_plane(struct drm_i915_private
*dev_priv
,
1355 enum plane plane
, bool state
)
1361 reg
= DSPCNTR(plane
);
1362 val
= I915_READ(reg
);
1363 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1364 I915_STATE_WARN(cur_state
!= state
,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane
), state_string(state
), state_string(cur_state
));
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1372 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1375 struct drm_device
*dev
= dev_priv
->dev
;
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev
)->gen
>= 4) {
1382 reg
= DSPCNTR(pipe
);
1383 val
= I915_READ(reg
);
1384 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1385 "plane %c assertion failure, should be disabled but not\n",
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv
, i
) {
1393 val
= I915_READ(reg
);
1394 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1395 DISPPLANE_SEL_PIPE_SHIFT
;
1396 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i
), pipe_name(pipe
));
1402 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1405 struct drm_device
*dev
= dev_priv
->dev
;
1409 if (INTEL_INFO(dev
)->gen
>= 9) {
1410 for_each_sprite(dev_priv
, pipe
, sprite
) {
1411 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1412 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite
, pipe_name(pipe
));
1416 } else if (IS_VALLEYVIEW(dev
)) {
1417 for_each_sprite(dev_priv
, pipe
, sprite
) {
1418 reg
= SPCNTR(pipe
, sprite
);
1419 val
= I915_READ(reg
);
1420 I915_STATE_WARN(val
& SP_ENABLE
,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1424 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1426 val
= I915_READ(reg
);
1427 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe
), pipe_name(pipe
));
1430 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1431 reg
= DVSCNTR(pipe
);
1432 val
= I915_READ(reg
);
1433 I915_STATE_WARN(val
& DVS_ENABLE
,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe
), pipe_name(pipe
));
1439 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1442 drm_crtc_vblank_put(crtc
);
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1452 val
= I915_READ(PCH_DREF_CONTROL
);
1453 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1454 DREF_SUPERSPREAD_SOURCE_MASK
));
1455 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1465 reg
= PCH_TRANSCONF(pipe
);
1466 val
= I915_READ(reg
);
1467 enabled
= !!(val
& TRANS_ENABLE
);
1468 I915_STATE_WARN(enabled
,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1474 enum pipe pipe
, u32 port_sel
, u32 val
)
1476 if ((val
& DP_PORT_EN
) == 0)
1479 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1480 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1481 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1482 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1484 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1485 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1488 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1494 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1495 enum pipe pipe
, u32 val
)
1497 if ((val
& SDVO_ENABLE
) == 0)
1500 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1501 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1503 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1504 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1507 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1513 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1514 enum pipe pipe
, u32 val
)
1516 if ((val
& LVDS_PORT_EN
) == 0)
1519 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1520 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1523 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1529 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1530 enum pipe pipe
, u32 val
)
1532 if ((val
& ADPA_DAC_ENABLE
) == 0)
1534 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1535 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1538 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1544 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1545 enum pipe pipe
, int reg
, u32 port_sel
)
1547 u32 val
= I915_READ(reg
);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg
, pipe_name(pipe
));
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1553 && (val
& DP_PIPEB_SELECT
),
1554 "IBX PCH dp port still using transcoder B\n");
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1558 enum pipe pipe
, int reg
)
1560 u32 val
= I915_READ(reg
);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg
, pipe_name(pipe
));
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1566 && (val
& SDVO_PIPE_B_SELECT
),
1567 "IBX PCH hdmi port still using transcoder B\n");
1570 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1576 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1577 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1578 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1581 val
= I915_READ(reg
);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1587 val
= I915_READ(reg
);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1593 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1594 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1597 static void intel_init_dpio(struct drm_device
*dev
)
1599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 if (!IS_VALLEYVIEW(dev
))
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1609 if (IS_CHERRYVIEW(dev
)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1617 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1618 const struct intel_crtc_state
*pipe_config
)
1620 struct drm_device
*dev
= crtc
->base
.dev
;
1621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1622 int reg
= DPLL(crtc
->pipe
);
1623 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1625 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv
->dev
))
1632 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1634 I915_WRITE(reg
, dpll
);
1638 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1641 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1642 POSTING_READ(DPLL_MD(crtc
->pipe
));
1644 /* We do this three times for luck */
1645 I915_WRITE(reg
, dpll
);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg
, dpll
);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg
, dpll
);
1653 udelay(150); /* wait for warmup */
1656 static void chv_enable_pll(struct intel_crtc
*crtc
,
1657 const struct intel_crtc_state
*pipe_config
)
1659 struct drm_device
*dev
= crtc
->base
.dev
;
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 int pipe
= crtc
->pipe
;
1662 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1665 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1669 mutex_lock(&dev_priv
->sb_lock
);
1671 /* Enable back the 10bit clock to display controller */
1672 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1673 tmp
|= DPIO_DCLKP_EN
;
1674 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1676 mutex_unlock(&dev_priv
->sb_lock
);
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1684 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1692 POSTING_READ(DPLL_MD(pipe
));
1695 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1697 struct intel_crtc
*crtc
;
1700 for_each_intel_crtc(dev
, crtc
)
1701 count
+= crtc
->base
.state
->active
&&
1702 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1707 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1709 struct drm_device
*dev
= crtc
->base
.dev
;
1710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1711 int reg
= DPLL(crtc
->pipe
);
1712 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1714 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1721 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1731 dpll
|= DPLL_DVO_2X_MODE
;
1732 I915_WRITE(DPLL(!crtc
->pipe
),
1733 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1736 /* Wait for the clocks to stabilize. */
1740 if (INTEL_INFO(dev
)->gen
>= 4) {
1741 I915_WRITE(DPLL_MD(crtc
->pipe
),
1742 crtc
->config
->dpll_hw_state
.dpll_md
);
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1747 * So write it again.
1749 I915_WRITE(reg
, dpll
);
1752 /* We do this three times for luck */
1753 I915_WRITE(reg
, dpll
);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg
, dpll
);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg
, dpll
);
1761 udelay(150); /* wait for warmup */
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1771 * Note! This is for pre-ILK only.
1773 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1775 struct drm_device
*dev
= crtc
->base
.dev
;
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 enum pipe pipe
= crtc
->pipe
;
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1781 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1782 !intel_num_dvo_pipes(dev
)) {
1783 I915_WRITE(DPLL(PIPE_B
),
1784 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1785 I915_WRITE(DPLL(PIPE_A
),
1786 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1791 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv
, pipe
);
1797 I915_WRITE(DPLL(pipe
), 0);
1798 POSTING_READ(DPLL(pipe
));
1801 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv
, pipe
);
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1813 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1814 I915_WRITE(DPLL(pipe
), val
);
1815 POSTING_READ(DPLL(pipe
));
1819 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1821 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv
, pipe
);
1827 /* Set PLL en = 0 */
1828 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1830 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1831 I915_WRITE(DPLL(pipe
), val
);
1832 POSTING_READ(DPLL(pipe
));
1834 mutex_lock(&dev_priv
->sb_lock
);
1836 /* Disable 10bit clock to display controller */
1837 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1838 val
&= ~DPIO_DCLKP_EN
;
1839 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1841 /* disable left/right clock distribution */
1842 if (pipe
!= PIPE_B
) {
1843 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1844 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1845 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1847 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1848 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1849 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1852 mutex_unlock(&dev_priv
->sb_lock
);
1855 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1856 struct intel_digital_port
*dport
,
1857 unsigned int expected_mask
)
1862 switch (dport
->port
) {
1864 port_mask
= DPLL_PORTB_READY_MASK
;
1868 port_mask
= DPLL_PORTC_READY_MASK
;
1870 expected_mask
<<= 4;
1873 port_mask
= DPLL_PORTD_READY_MASK
;
1874 dpll_reg
= DPIO_PHY_STATUS
;
1880 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1885 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1887 struct drm_device
*dev
= crtc
->base
.dev
;
1888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1889 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1891 if (WARN_ON(pll
== NULL
))
1894 WARN_ON(!pll
->config
.crtc_mask
);
1895 if (pll
->active
== 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1898 assert_shared_dpll_disabled(dev_priv
, pll
);
1900 pll
->mode_set(dev_priv
, pll
);
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1912 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1914 struct drm_device
*dev
= crtc
->base
.dev
;
1915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1916 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1918 if (WARN_ON(pll
== NULL
))
1921 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll
->name
, pll
->active
, pll
->on
,
1926 crtc
->base
.base
.id
);
1928 if (pll
->active
++) {
1930 assert_shared_dpll_enabled(dev_priv
, pll
);
1935 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1937 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1938 pll
->enable(dev_priv
, pll
);
1942 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1944 struct drm_device
*dev
= crtc
->base
.dev
;
1945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1950 if (WARN_ON(pll
== NULL
))
1953 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll
->name
, pll
->active
, pll
->on
,
1958 crtc
->base
.base
.id
);
1960 if (WARN_ON(pll
->active
== 0)) {
1961 assert_shared_dpll_disabled(dev_priv
, pll
);
1965 assert_shared_dpll_enabled(dev_priv
, pll
);
1970 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1971 pll
->disable(dev_priv
, pll
);
1974 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1980 struct drm_device
*dev
= dev_priv
->dev
;
1981 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1982 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1983 uint32_t reg
, val
, pipeconf_val
;
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev
));
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv
,
1990 intel_crtc_to_shared_dpll(intel_crtc
));
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv
, pipe
);
1994 assert_fdi_rx_enabled(dev_priv
, pipe
);
1996 if (HAS_PCH_CPT(dev
)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg
= TRANS_CHICKEN2(pipe
);
2000 val
= I915_READ(reg
);
2001 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2002 I915_WRITE(reg
, val
);
2005 reg
= PCH_TRANSCONF(pipe
);
2006 val
= I915_READ(reg
);
2007 pipeconf_val
= I915_READ(PIPECONF(pipe
));
2009 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
2015 val
&= ~PIPECONF_BPC_MASK
;
2016 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
2017 val
|= PIPECONF_8BPC
;
2019 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2022 val
&= ~TRANS_INTERLACE_MASK
;
2023 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2024 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2025 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2026 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2028 val
|= TRANS_INTERLACED
;
2030 val
|= TRANS_PROGRESSIVE
;
2032 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2033 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2037 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2038 enum transcoder cpu_transcoder
)
2040 u32 val
, pipeconf_val
;
2042 /* PCH only available on ILK+ */
2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2045 /* FDI must be feeding us bits for PCH ports */
2046 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2047 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2049 /* Workaround: set timing override bit. */
2050 val
= I915_READ(_TRANSA_CHICKEN2
);
2051 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2052 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2055 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2057 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2058 PIPECONF_INTERLACED_ILK
)
2059 val
|= TRANS_INTERLACED
;
2061 val
|= TRANS_PROGRESSIVE
;
2063 I915_WRITE(LPT_TRANSCONF
, val
);
2064 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2065 DRM_ERROR("Failed to enable PCH transcoder\n");
2068 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2071 struct drm_device
*dev
= dev_priv
->dev
;
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv
, pipe
);
2076 assert_fdi_rx_disabled(dev_priv
, pipe
);
2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv
, pipe
);
2081 reg
= PCH_TRANSCONF(pipe
);
2082 val
= I915_READ(reg
);
2083 val
&= ~TRANS_ENABLE
;
2084 I915_WRITE(reg
, val
);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2089 if (!HAS_PCH_IBX(dev
)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg
= TRANS_CHICKEN2(pipe
);
2092 val
= I915_READ(reg
);
2093 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2094 I915_WRITE(reg
, val
);
2098 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2102 val
= I915_READ(LPT_TRANSCONF
);
2103 val
&= ~TRANS_ENABLE
;
2104 I915_WRITE(LPT_TRANSCONF
, val
);
2105 /* wait for PCH transcoder off, transcoder state */
2106 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2107 DRM_ERROR("Failed to disable PCH transcoder\n");
2109 /* Workaround: clear timing override bit. */
2110 val
= I915_READ(_TRANSA_CHICKEN2
);
2111 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2112 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2116 * intel_enable_pipe - enable a pipe, asserting requirements
2117 * @crtc: crtc responsible for the pipe
2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2122 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2124 struct drm_device
*dev
= crtc
->base
.dev
;
2125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2126 enum pipe pipe
= crtc
->pipe
;
2127 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2129 enum pipe pch_transcoder
;
2133 assert_planes_disabled(dev_priv
, pipe
);
2134 assert_cursor_disabled(dev_priv
, pipe
);
2135 assert_sprites_disabled(dev_priv
, pipe
);
2137 if (HAS_PCH_LPT(dev_priv
->dev
))
2138 pch_transcoder
= TRANSCODER_A
;
2140 pch_transcoder
= pipe
;
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2147 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2148 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2149 assert_dsi_pll_enabled(dev_priv
);
2151 assert_pll_enabled(dev_priv
, pipe
);
2153 if (crtc
->config
->has_pch_encoder
) {
2154 /* if driving the PCH, we need FDI enabled */
2155 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2156 assert_fdi_tx_pll_enabled(dev_priv
,
2157 (enum pipe
) cpu_transcoder
);
2159 /* FIXME: assert CPU port conditions for SNB+ */
2162 reg
= PIPECONF(cpu_transcoder
);
2163 val
= I915_READ(reg
);
2164 if (val
& PIPECONF_ENABLE
) {
2165 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2166 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2170 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2175 * intel_disable_pipe - disable a pipe, asserting requirements
2176 * @crtc: crtc whose pipes is to be disabled
2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
2182 * Will wait until the pipe has shut down before returning.
2184 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2186 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2187 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2188 enum pipe pipe
= crtc
->pipe
;
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2196 assert_planes_disabled(dev_priv
, pipe
);
2197 assert_cursor_disabled(dev_priv
, pipe
);
2198 assert_sprites_disabled(dev_priv
, pipe
);
2200 reg
= PIPECONF(cpu_transcoder
);
2201 val
= I915_READ(reg
);
2202 if ((val
& PIPECONF_ENABLE
) == 0)
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2209 if (crtc
->config
->double_wide
)
2210 val
&= ~PIPECONF_DOUBLE_WIDE
;
2212 /* Don't disable pipe or pipe PLLs if needed */
2213 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2214 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2215 val
&= ~PIPECONF_ENABLE
;
2217 I915_WRITE(reg
, val
);
2218 if ((val
& PIPECONF_ENABLE
) == 0)
2219 intel_wait_for_pipe_off(crtc
);
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2230 struct drm_crtc
*crtc
)
2232 struct drm_device
*dev
= plane
->dev
;
2233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2238 to_intel_plane_state(plane
->state
)->visible
= true;
2240 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2244 static bool need_vtd_wa(struct drm_device
*dev
)
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2254 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2255 uint64_t fb_format_modifier
)
2257 unsigned int tile_height
;
2258 uint32_t pixel_bytes
;
2260 switch (fb_format_modifier
) {
2261 case DRM_FORMAT_MOD_NONE
:
2264 case I915_FORMAT_MOD_X_TILED
:
2265 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2267 case I915_FORMAT_MOD_Y_TILED
:
2270 case I915_FORMAT_MOD_Yf_TILED
:
2271 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2272 switch (pixel_bytes
) {
2286 "128-bit pixels are not supported for display!");
2292 MISSING_CASE(fb_format_modifier
);
2301 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2302 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2304 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2305 fb_format_modifier
));
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2310 const struct drm_plane_state
*plane_state
)
2312 struct intel_rotation_info
*info
= &view
->rotation_info
;
2314 *view
= i915_ggtt_view_normal
;
2319 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2322 *view
= i915_ggtt_view_rotated
;
2324 info
->height
= fb
->height
;
2325 info
->pixel_format
= fb
->pixel_format
;
2326 info
->pitch
= fb
->pitches
[0];
2327 info
->fb_modifier
= fb
->modifier
[0];
2332 static unsigned int intel_linear_alignment(struct drm_i915_private
*dev_priv
)
2334 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2336 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2337 IS_VALLEYVIEW(dev_priv
))
2339 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2346 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2347 struct drm_framebuffer
*fb
,
2348 const struct drm_plane_state
*plane_state
,
2349 struct intel_engine_cs
*pipelined
)
2351 struct drm_device
*dev
= fb
->dev
;
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2353 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2354 struct i915_ggtt_view view
;
2358 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2360 switch (fb
->modifier
[0]) {
2361 case DRM_FORMAT_MOD_NONE
:
2362 alignment
= intel_linear_alignment(dev_priv
);
2364 case I915_FORMAT_MOD_X_TILED
:
2365 if (INTEL_INFO(dev
)->gen
>= 9)
2366 alignment
= 256 * 1024;
2368 /* pin() will align the object as required by fence */
2372 case I915_FORMAT_MOD_Y_TILED
:
2373 case I915_FORMAT_MOD_Yf_TILED
:
2374 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2377 alignment
= 1 * 1024 * 1024;
2380 MISSING_CASE(fb
->modifier
[0]);
2384 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2393 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2394 alignment
= 256 * 1024;
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2403 intel_runtime_pm_get(dev_priv
);
2405 dev_priv
->mm
.interruptible
= false;
2406 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2409 goto err_interruptible
;
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2416 ret
= i915_gem_object_get_fence(obj
);
2420 i915_gem_object_pin_fence(obj
);
2422 dev_priv
->mm
.interruptible
= true;
2423 intel_runtime_pm_put(dev_priv
);
2427 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2429 dev_priv
->mm
.interruptible
= true;
2430 intel_runtime_pm_put(dev_priv
);
2434 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2435 const struct drm_plane_state
*plane_state
)
2437 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2438 struct i915_ggtt_view view
;
2441 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2443 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2444 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2446 i915_gem_object_unpin_fence(obj
);
2447 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
2454 unsigned int tiling_mode
,
2458 if (tiling_mode
!= I915_TILING_NONE
) {
2459 unsigned int tile_rows
, tiles
;
2464 tiles
= *x
/ (512/cpp
);
2467 return tile_rows
* pitch
* 8 + tiles
* 4096;
2469 unsigned int alignment
= intel_linear_alignment(dev_priv
) - 1;
2470 unsigned int offset
;
2472 offset
= *y
* pitch
+ *x
* cpp
;
2473 *y
= (offset
& alignment
) / pitch
;
2474 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2475 return offset
& ~alignment
;
2479 static int i9xx_format_to_fourcc(int format
)
2482 case DISPPLANE_8BPP
:
2483 return DRM_FORMAT_C8
;
2484 case DISPPLANE_BGRX555
:
2485 return DRM_FORMAT_XRGB1555
;
2486 case DISPPLANE_BGRX565
:
2487 return DRM_FORMAT_RGB565
;
2489 case DISPPLANE_BGRX888
:
2490 return DRM_FORMAT_XRGB8888
;
2491 case DISPPLANE_RGBX888
:
2492 return DRM_FORMAT_XBGR8888
;
2493 case DISPPLANE_BGRX101010
:
2494 return DRM_FORMAT_XRGB2101010
;
2495 case DISPPLANE_RGBX101010
:
2496 return DRM_FORMAT_XBGR2101010
;
2500 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2503 case PLANE_CTL_FORMAT_RGB_565
:
2504 return DRM_FORMAT_RGB565
;
2506 case PLANE_CTL_FORMAT_XRGB_8888
:
2509 return DRM_FORMAT_ABGR8888
;
2511 return DRM_FORMAT_XBGR8888
;
2514 return DRM_FORMAT_ARGB8888
;
2516 return DRM_FORMAT_XRGB8888
;
2518 case PLANE_CTL_FORMAT_XRGB_2101010
:
2520 return DRM_FORMAT_XBGR2101010
;
2522 return DRM_FORMAT_XRGB2101010
;
2527 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2528 struct intel_initial_plane_config
*plane_config
)
2530 struct drm_device
*dev
= crtc
->base
.dev
;
2531 struct drm_i915_gem_object
*obj
= NULL
;
2532 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2533 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2534 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2535 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2538 size_aligned
-= base_aligned
;
2540 if (plane_config
->size
== 0)
2543 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2550 obj
->tiling_mode
= plane_config
->tiling
;
2551 if (obj
->tiling_mode
== I915_TILING_X
)
2552 obj
->stride
= fb
->pitches
[0];
2554 mode_cmd
.pixel_format
= fb
->pixel_format
;
2555 mode_cmd
.width
= fb
->width
;
2556 mode_cmd
.height
= fb
->height
;
2557 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2558 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2559 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2561 mutex_lock(&dev
->struct_mutex
);
2562 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2564 DRM_DEBUG_KMS("intel fb init failed\n");
2567 mutex_unlock(&dev
->struct_mutex
);
2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2573 drm_gem_object_unreference(&obj
->base
);
2574 mutex_unlock(&dev
->struct_mutex
);
2578 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2580 update_state_fb(struct drm_plane
*plane
)
2582 if (plane
->fb
== plane
->state
->fb
)
2585 if (plane
->state
->fb
)
2586 drm_framebuffer_unreference(plane
->state
->fb
);
2587 plane
->state
->fb
= plane
->fb
;
2588 if (plane
->state
->fb
)
2589 drm_framebuffer_reference(plane
->state
->fb
);
2593 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2594 struct intel_initial_plane_config
*plane_config
)
2596 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2599 struct intel_crtc
*i
;
2600 struct drm_i915_gem_object
*obj
;
2601 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2602 struct drm_framebuffer
*fb
;
2604 if (!plane_config
->fb
)
2607 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2608 fb
= &plane_config
->fb
->base
;
2612 kfree(plane_config
->fb
);
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2618 for_each_crtc(dev
, c
) {
2619 i
= to_intel_crtc(c
);
2621 if (c
== &intel_crtc
->base
)
2627 fb
= c
->primary
->fb
;
2631 obj
= intel_fb_obj(fb
);
2632 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2633 drm_framebuffer_reference(fb
);
2641 obj
= intel_fb_obj(fb
);
2642 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2643 dev_priv
->preserve_bios_swizzle
= true;
2646 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2647 update_state_fb(primary
);
2648 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2649 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2652 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2653 struct drm_framebuffer
*fb
,
2656 struct drm_device
*dev
= crtc
->dev
;
2657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2658 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2659 struct drm_plane
*primary
= crtc
->primary
;
2660 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2661 struct drm_i915_gem_object
*obj
;
2662 int plane
= intel_crtc
->plane
;
2663 unsigned long linear_offset
;
2665 u32 reg
= DSPCNTR(plane
);
2668 if (!visible
|| !fb
) {
2670 if (INTEL_INFO(dev
)->gen
>= 4)
2671 I915_WRITE(DSPSURF(plane
), 0);
2673 I915_WRITE(DSPADDR(plane
), 0);
2678 obj
= intel_fb_obj(fb
);
2679 if (WARN_ON(obj
== NULL
))
2682 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2684 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2686 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2688 if (INTEL_INFO(dev
)->gen
< 4) {
2689 if (intel_crtc
->pipe
== PIPE_B
)
2690 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2695 I915_WRITE(DSPSIZE(plane
),
2696 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2697 (intel_crtc
->config
->pipe_src_w
- 1));
2698 I915_WRITE(DSPPOS(plane
), 0);
2699 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2700 I915_WRITE(PRIMSIZE(plane
),
2701 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2702 (intel_crtc
->config
->pipe_src_w
- 1));
2703 I915_WRITE(PRIMPOS(plane
), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2707 switch (fb
->pixel_format
) {
2709 dspcntr
|= DISPPLANE_8BPP
;
2711 case DRM_FORMAT_XRGB1555
:
2712 dspcntr
|= DISPPLANE_BGRX555
;
2714 case DRM_FORMAT_RGB565
:
2715 dspcntr
|= DISPPLANE_BGRX565
;
2717 case DRM_FORMAT_XRGB8888
:
2718 dspcntr
|= DISPPLANE_BGRX888
;
2720 case DRM_FORMAT_XBGR8888
:
2721 dspcntr
|= DISPPLANE_RGBX888
;
2723 case DRM_FORMAT_XRGB2101010
:
2724 dspcntr
|= DISPPLANE_BGRX101010
;
2726 case DRM_FORMAT_XBGR2101010
:
2727 dspcntr
|= DISPPLANE_RGBX101010
;
2733 if (INTEL_INFO(dev
)->gen
>= 4 &&
2734 obj
->tiling_mode
!= I915_TILING_NONE
)
2735 dspcntr
|= DISPPLANE_TILED
;
2738 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2740 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2742 if (INTEL_INFO(dev
)->gen
>= 4) {
2743 intel_crtc
->dspaddr_offset
=
2744 intel_gen4_compute_page_offset(dev_priv
,
2745 &x
, &y
, obj
->tiling_mode
,
2748 linear_offset
-= intel_crtc
->dspaddr_offset
;
2750 intel_crtc
->dspaddr_offset
= linear_offset
;
2753 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2754 dspcntr
|= DISPPLANE_ROTATE_180
;
2756 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2757 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2762 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2763 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2766 I915_WRITE(reg
, dspcntr
);
2768 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2769 if (INTEL_INFO(dev
)->gen
>= 4) {
2770 I915_WRITE(DSPSURF(plane
),
2771 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2772 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2773 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2775 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2779 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2780 struct drm_framebuffer
*fb
,
2783 struct drm_device
*dev
= crtc
->dev
;
2784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2786 struct drm_plane
*primary
= crtc
->primary
;
2787 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2788 struct drm_i915_gem_object
*obj
;
2789 int plane
= intel_crtc
->plane
;
2790 unsigned long linear_offset
;
2792 u32 reg
= DSPCNTR(plane
);
2795 if (!visible
|| !fb
) {
2797 I915_WRITE(DSPSURF(plane
), 0);
2802 obj
= intel_fb_obj(fb
);
2803 if (WARN_ON(obj
== NULL
))
2806 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2808 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2810 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2812 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2813 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2815 switch (fb
->pixel_format
) {
2817 dspcntr
|= DISPPLANE_8BPP
;
2819 case DRM_FORMAT_RGB565
:
2820 dspcntr
|= DISPPLANE_BGRX565
;
2822 case DRM_FORMAT_XRGB8888
:
2823 dspcntr
|= DISPPLANE_BGRX888
;
2825 case DRM_FORMAT_XBGR8888
:
2826 dspcntr
|= DISPPLANE_RGBX888
;
2828 case DRM_FORMAT_XRGB2101010
:
2829 dspcntr
|= DISPPLANE_BGRX101010
;
2831 case DRM_FORMAT_XBGR2101010
:
2832 dspcntr
|= DISPPLANE_RGBX101010
;
2838 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2839 dspcntr
|= DISPPLANE_TILED
;
2841 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2842 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2844 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2845 intel_crtc
->dspaddr_offset
=
2846 intel_gen4_compute_page_offset(dev_priv
,
2847 &x
, &y
, obj
->tiling_mode
,
2850 linear_offset
-= intel_crtc
->dspaddr_offset
;
2851 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2852 dspcntr
|= DISPPLANE_ROTATE_180
;
2854 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2855 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2856 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2861 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2862 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2866 I915_WRITE(reg
, dspcntr
);
2868 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2869 I915_WRITE(DSPSURF(plane
),
2870 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2871 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2872 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2874 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2875 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2880 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2881 uint32_t pixel_format
)
2883 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2890 switch (fb_modifier
) {
2891 case DRM_FORMAT_MOD_NONE
:
2893 case I915_FORMAT_MOD_X_TILED
:
2894 if (INTEL_INFO(dev
)->gen
== 2)
2897 case I915_FORMAT_MOD_Y_TILED
:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2903 case I915_FORMAT_MOD_Yf_TILED
:
2904 if (bits_per_pixel
== 8)
2909 MISSING_CASE(fb_modifier
);
2914 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2915 struct drm_i915_gem_object
*obj
)
2917 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2919 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2920 view
= &i915_ggtt_view_rotated
;
2922 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2928 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2930 struct drm_device
*dev
;
2931 struct drm_i915_private
*dev_priv
;
2932 struct intel_crtc_scaler_state
*scaler_state
;
2935 dev
= intel_crtc
->base
.dev
;
2936 dev_priv
= dev
->dev_private
;
2937 scaler_state
= &intel_crtc
->config
->scaler_state
;
2939 /* loop through and disable scalers that aren't in use */
2940 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2941 if (!scaler_state
->scalers
[i
].in_use
) {
2942 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2943 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2944 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2945 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2946 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2951 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2953 switch (pixel_format
) {
2955 return PLANE_CTL_FORMAT_INDEXED
;
2956 case DRM_FORMAT_RGB565
:
2957 return PLANE_CTL_FORMAT_RGB_565
;
2958 case DRM_FORMAT_XBGR8888
:
2959 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2960 case DRM_FORMAT_XRGB8888
:
2961 return PLANE_CTL_FORMAT_XRGB_8888
;
2963 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2964 * to be already pre-multiplied. We need to add a knob (or a different
2965 * DRM_FORMAT) for user-space to configure that.
2967 case DRM_FORMAT_ABGR8888
:
2968 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2969 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2970 case DRM_FORMAT_ARGB8888
:
2971 return PLANE_CTL_FORMAT_XRGB_8888
|
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2973 case DRM_FORMAT_XRGB2101010
:
2974 return PLANE_CTL_FORMAT_XRGB_2101010
;
2975 case DRM_FORMAT_XBGR2101010
:
2976 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2977 case DRM_FORMAT_YUYV
:
2978 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2979 case DRM_FORMAT_YVYU
:
2980 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2981 case DRM_FORMAT_UYVY
:
2982 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2983 case DRM_FORMAT_VYUY
:
2984 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
2986 MISSING_CASE(pixel_format
);
2992 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
2994 switch (fb_modifier
) {
2995 case DRM_FORMAT_MOD_NONE
:
2997 case I915_FORMAT_MOD_X_TILED
:
2998 return PLANE_CTL_TILED_X
;
2999 case I915_FORMAT_MOD_Y_TILED
:
3000 return PLANE_CTL_TILED_Y
;
3001 case I915_FORMAT_MOD_Yf_TILED
:
3002 return PLANE_CTL_TILED_YF
;
3004 MISSING_CASE(fb_modifier
);
3010 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3013 case BIT(DRM_ROTATE_0
):
3016 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3017 * while i915 HW rotation is clockwise, thats why this swapping.
3019 case BIT(DRM_ROTATE_90
):
3020 return PLANE_CTL_ROTATE_270
;
3021 case BIT(DRM_ROTATE_180
):
3022 return PLANE_CTL_ROTATE_180
;
3023 case BIT(DRM_ROTATE_270
):
3024 return PLANE_CTL_ROTATE_90
;
3026 MISSING_CASE(rotation
);
3032 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3033 struct drm_framebuffer
*fb
,
3036 struct drm_device
*dev
= crtc
->dev
;
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3039 struct drm_plane
*plane
= crtc
->primary
;
3040 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3041 struct drm_i915_gem_object
*obj
;
3042 int pipe
= intel_crtc
->pipe
;
3043 u32 plane_ctl
, stride_div
, stride
;
3044 u32 tile_height
, plane_offset
, plane_size
;
3045 unsigned int rotation
;
3046 int x_offset
, y_offset
;
3047 unsigned long surf_addr
;
3048 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3049 struct intel_plane_state
*plane_state
;
3050 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3051 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3054 plane_state
= to_intel_plane_state(plane
->state
);
3056 if (!visible
|| !fb
) {
3057 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3058 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3059 POSTING_READ(PLANE_CTL(pipe
, 0));
3063 plane_ctl
= PLANE_CTL_ENABLE
|
3064 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3065 PLANE_CTL_PIPE_CSC_ENABLE
;
3067 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3068 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3069 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3071 rotation
= plane
->state
->rotation
;
3072 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3074 obj
= intel_fb_obj(fb
);
3075 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3077 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3080 * FIXME: intel_plane_state->src, dst aren't set when transitional
3081 * update_plane helpers are called from legacy paths.
3082 * Once full atomic crtc is available, below check can be avoided.
3084 if (drm_rect_width(&plane_state
->src
)) {
3085 scaler_id
= plane_state
->scaler_id
;
3086 src_x
= plane_state
->src
.x1
>> 16;
3087 src_y
= plane_state
->src
.y1
>> 16;
3088 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3089 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3090 dst_x
= plane_state
->dst
.x1
;
3091 dst_y
= plane_state
->dst
.y1
;
3092 dst_w
= drm_rect_width(&plane_state
->dst
);
3093 dst_h
= drm_rect_height(&plane_state
->dst
);
3095 WARN_ON(x
!= src_x
|| y
!= src_y
);
3097 src_w
= intel_crtc
->config
->pipe_src_w
;
3098 src_h
= intel_crtc
->config
->pipe_src_h
;
3101 if (intel_rotation_90_or_270(rotation
)) {
3102 /* stride = Surface height in tiles */
3103 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3105 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3106 x_offset
= stride
* tile_height
- y
- src_h
;
3108 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3110 stride
= fb
->pitches
[0] / stride_div
;
3113 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3115 plane_offset
= y_offset
<< 16 | x_offset
;
3117 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3118 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3119 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3120 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3122 if (scaler_id
>= 0) {
3123 uint32_t ps_ctrl
= 0;
3125 WARN_ON(!dst_w
|| !dst_h
);
3126 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3127 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3128 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3129 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3130 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3131 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3132 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3134 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3137 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3139 POSTING_READ(PLANE_SURF(pipe
, 0));
3142 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3144 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3145 int x
, int y
, enum mode_set_atomic state
)
3147 struct drm_device
*dev
= crtc
->dev
;
3148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3150 if (dev_priv
->display
.disable_fbc
)
3151 dev_priv
->display
.disable_fbc(dev
);
3153 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3158 static void intel_complete_page_flips(struct drm_device
*dev
)
3160 struct drm_crtc
*crtc
;
3162 for_each_crtc(dev
, crtc
) {
3163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3164 enum plane plane
= intel_crtc
->plane
;
3166 intel_prepare_page_flip(dev
, plane
);
3167 intel_finish_page_flip_plane(dev
, plane
);
3171 static void intel_update_primary_planes(struct drm_device
*dev
)
3173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3174 struct drm_crtc
*crtc
;
3176 for_each_crtc(dev
, crtc
) {
3177 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3179 drm_modeset_lock(&crtc
->mutex
, NULL
);
3181 * FIXME: Once we have proper support for primary planes (and
3182 * disabling them without disabling the entire crtc) allow again
3183 * a NULL crtc->primary->fb.
3185 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3186 dev_priv
->display
.update_primary_plane(crtc
,
3190 drm_modeset_unlock(&crtc
->mutex
);
3194 void intel_prepare_reset(struct drm_device
*dev
)
3196 /* no reset support for gen2 */
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3204 drm_modeset_lock_all(dev
);
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3209 intel_display_suspend(dev
);
3212 void intel_finish_reset(struct drm_device
*dev
)
3214 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3221 intel_complete_page_flips(dev
);
3223 /* no reset support for gen2 */
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3235 intel_update_primary_planes(dev
);
3240 * The display has been reset as well,
3241 * so need a full re-initialization.
3243 intel_runtime_pm_disable_interrupts(dev_priv
);
3244 intel_runtime_pm_enable_interrupts(dev_priv
);
3246 intel_modeset_init_hw(dev
);
3248 spin_lock_irq(&dev_priv
->irq_lock
);
3249 if (dev_priv
->display
.hpd_irq_setup
)
3250 dev_priv
->display
.hpd_irq_setup(dev
);
3251 spin_unlock_irq(&dev_priv
->irq_lock
);
3253 intel_modeset_setup_hw_state(dev
, true);
3255 intel_hpd_init(dev_priv
);
3257 drm_modeset_unlock_all(dev
);
3261 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3263 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3264 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3265 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3268 /* Big Hammer, we also need to ensure that any pending
3269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3270 * current scanout is retired before unpinning the old
3271 * framebuffer. Note that we rely on userspace rendering
3272 * into the buffer attached to the pipe they are waiting
3273 * on. If not, userspace generates a GPU hang with IPEHR
3274 * point to the MI_WAIT_FOR_EVENT.
3276 * This should only fail upon a hung GPU, in which case we
3277 * can safely continue.
3279 dev_priv
->mm
.interruptible
= false;
3280 ret
= i915_gem_object_wait_rendering(obj
, true);
3281 dev_priv
->mm
.interruptible
= was_interruptible
;
3286 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3288 struct drm_device
*dev
= crtc
->dev
;
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3290 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3293 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3294 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3297 spin_lock_irq(&dev
->event_lock
);
3298 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3299 spin_unlock_irq(&dev
->event_lock
);
3304 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3306 struct drm_device
*dev
= crtc
->base
.dev
;
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3308 const struct drm_display_mode
*adjusted_mode
;
3314 * Update pipe size and adjust fitter if needed: the reason for this is
3315 * that in compute_mode_changes we check the native mode (not the pfit
3316 * mode) to see if we can flip rather than do a full mode set. In the
3317 * fastboot case, we'll flip, but if we don't update the pipesrc and
3318 * pfit state, we'll end up with a big fb scanned out into the wrong
3321 * To fix this properly, we need to hoist the checks up into
3322 * compute_mode_changes (or above), check the actual pfit state and
3323 * whether the platform allows pfit disable with pipe active, and only
3324 * then update the pipesrc and pfit state, even on the flip path.
3327 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3329 I915_WRITE(PIPESRC(crtc
->pipe
),
3330 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3331 (adjusted_mode
->crtc_vdisplay
- 1));
3332 if (!crtc
->config
->pch_pfit
.enabled
&&
3333 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3334 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3335 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3336 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3337 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3339 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3340 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3343 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3345 struct drm_device
*dev
= crtc
->dev
;
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3347 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3348 int pipe
= intel_crtc
->pipe
;
3351 /* enable normal train */
3352 reg
= FDI_TX_CTL(pipe
);
3353 temp
= I915_READ(reg
);
3354 if (IS_IVYBRIDGE(dev
)) {
3355 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3356 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3358 temp
&= ~FDI_LINK_TRAIN_NONE
;
3359 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3361 I915_WRITE(reg
, temp
);
3363 reg
= FDI_RX_CTL(pipe
);
3364 temp
= I915_READ(reg
);
3365 if (HAS_PCH_CPT(dev
)) {
3366 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3367 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3369 temp
&= ~FDI_LINK_TRAIN_NONE
;
3370 temp
|= FDI_LINK_TRAIN_NONE
;
3372 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3374 /* wait one idle pattern time */
3378 /* IVB wants error correction enabled */
3379 if (IS_IVYBRIDGE(dev
))
3380 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3381 FDI_FE_ERRC_ENABLE
);
3384 /* The FDI link training functions for ILK/Ibexpeak. */
3385 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3387 struct drm_device
*dev
= crtc
->dev
;
3388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3389 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3390 int pipe
= intel_crtc
->pipe
;
3391 u32 reg
, temp
, tries
;
3393 /* FDI needs bits from pipe first */
3394 assert_pipe_enabled(dev_priv
, pipe
);
3396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3398 reg
= FDI_RX_IMR(pipe
);
3399 temp
= I915_READ(reg
);
3400 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3401 temp
&= ~FDI_RX_BIT_LOCK
;
3402 I915_WRITE(reg
, temp
);
3406 /* enable CPU FDI TX and PCH FDI RX */
3407 reg
= FDI_TX_CTL(pipe
);
3408 temp
= I915_READ(reg
);
3409 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3410 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3411 temp
&= ~FDI_LINK_TRAIN_NONE
;
3412 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3413 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3415 reg
= FDI_RX_CTL(pipe
);
3416 temp
= I915_READ(reg
);
3417 temp
&= ~FDI_LINK_TRAIN_NONE
;
3418 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3419 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3424 /* Ironlake workaround, enable clock pointer after FDI enable*/
3425 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3426 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3427 FDI_RX_PHASE_SYNC_POINTER_EN
);
3429 reg
= FDI_RX_IIR(pipe
);
3430 for (tries
= 0; tries
< 5; tries
++) {
3431 temp
= I915_READ(reg
);
3432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3434 if ((temp
& FDI_RX_BIT_LOCK
)) {
3435 DRM_DEBUG_KMS("FDI train 1 done.\n");
3436 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3441 DRM_ERROR("FDI train 1 fail!\n");
3444 reg
= FDI_TX_CTL(pipe
);
3445 temp
= I915_READ(reg
);
3446 temp
&= ~FDI_LINK_TRAIN_NONE
;
3447 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3448 I915_WRITE(reg
, temp
);
3450 reg
= FDI_RX_CTL(pipe
);
3451 temp
= I915_READ(reg
);
3452 temp
&= ~FDI_LINK_TRAIN_NONE
;
3453 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3454 I915_WRITE(reg
, temp
);
3459 reg
= FDI_RX_IIR(pipe
);
3460 for (tries
= 0; tries
< 5; tries
++) {
3461 temp
= I915_READ(reg
);
3462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3464 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3465 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3466 DRM_DEBUG_KMS("FDI train 2 done.\n");
3471 DRM_ERROR("FDI train 2 fail!\n");
3473 DRM_DEBUG_KMS("FDI train done\n");
3477 static const int snb_b_fdi_train_param
[] = {
3478 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3479 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3481 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3484 /* The FDI link training functions for SNB/Cougarpoint. */
3485 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3487 struct drm_device
*dev
= crtc
->dev
;
3488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3489 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3490 int pipe
= intel_crtc
->pipe
;
3491 u32 reg
, temp
, i
, retry
;
3493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3495 reg
= FDI_RX_IMR(pipe
);
3496 temp
= I915_READ(reg
);
3497 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3498 temp
&= ~FDI_RX_BIT_LOCK
;
3499 I915_WRITE(reg
, temp
);
3504 /* enable CPU FDI TX and PCH FDI RX */
3505 reg
= FDI_TX_CTL(pipe
);
3506 temp
= I915_READ(reg
);
3507 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3508 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3509 temp
&= ~FDI_LINK_TRAIN_NONE
;
3510 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3511 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3513 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3514 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3516 I915_WRITE(FDI_RX_MISC(pipe
),
3517 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3519 reg
= FDI_RX_CTL(pipe
);
3520 temp
= I915_READ(reg
);
3521 if (HAS_PCH_CPT(dev
)) {
3522 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3523 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3525 temp
&= ~FDI_LINK_TRAIN_NONE
;
3526 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3528 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3533 for (i
= 0; i
< 4; i
++) {
3534 reg
= FDI_TX_CTL(pipe
);
3535 temp
= I915_READ(reg
);
3536 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3537 temp
|= snb_b_fdi_train_param
[i
];
3538 I915_WRITE(reg
, temp
);
3543 for (retry
= 0; retry
< 5; retry
++) {
3544 reg
= FDI_RX_IIR(pipe
);
3545 temp
= I915_READ(reg
);
3546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3547 if (temp
& FDI_RX_BIT_LOCK
) {
3548 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3549 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558 DRM_ERROR("FDI train 1 fail!\n");
3561 reg
= FDI_TX_CTL(pipe
);
3562 temp
= I915_READ(reg
);
3563 temp
&= ~FDI_LINK_TRAIN_NONE
;
3564 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3566 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3568 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3570 I915_WRITE(reg
, temp
);
3572 reg
= FDI_RX_CTL(pipe
);
3573 temp
= I915_READ(reg
);
3574 if (HAS_PCH_CPT(dev
)) {
3575 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3576 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3578 temp
&= ~FDI_LINK_TRAIN_NONE
;
3579 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3581 I915_WRITE(reg
, temp
);
3586 for (i
= 0; i
< 4; i
++) {
3587 reg
= FDI_TX_CTL(pipe
);
3588 temp
= I915_READ(reg
);
3589 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3590 temp
|= snb_b_fdi_train_param
[i
];
3591 I915_WRITE(reg
, temp
);
3596 for (retry
= 0; retry
< 5; retry
++) {
3597 reg
= FDI_RX_IIR(pipe
);
3598 temp
= I915_READ(reg
);
3599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3600 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3601 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3602 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611 DRM_ERROR("FDI train 2 fail!\n");
3613 DRM_DEBUG_KMS("FDI train done.\n");
3616 /* Manual link training for Ivy Bridge A0 parts */
3617 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3619 struct drm_device
*dev
= crtc
->dev
;
3620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3622 int pipe
= intel_crtc
->pipe
;
3623 u32 reg
, temp
, i
, j
;
3625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3627 reg
= FDI_RX_IMR(pipe
);
3628 temp
= I915_READ(reg
);
3629 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3630 temp
&= ~FDI_RX_BIT_LOCK
;
3631 I915_WRITE(reg
, temp
);
3636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3637 I915_READ(FDI_RX_IIR(pipe
)));
3639 /* Try each vswing and preemphasis setting twice before moving on */
3640 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3641 /* disable first in case we need to retry */
3642 reg
= FDI_TX_CTL(pipe
);
3643 temp
= I915_READ(reg
);
3644 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3645 temp
&= ~FDI_TX_ENABLE
;
3646 I915_WRITE(reg
, temp
);
3648 reg
= FDI_RX_CTL(pipe
);
3649 temp
= I915_READ(reg
);
3650 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3651 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3652 temp
&= ~FDI_RX_ENABLE
;
3653 I915_WRITE(reg
, temp
);
3655 /* enable CPU FDI TX and PCH FDI RX */
3656 reg
= FDI_TX_CTL(pipe
);
3657 temp
= I915_READ(reg
);
3658 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3659 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3660 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3661 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3662 temp
|= snb_b_fdi_train_param
[j
/2];
3663 temp
|= FDI_COMPOSITE_SYNC
;
3664 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3666 I915_WRITE(FDI_RX_MISC(pipe
),
3667 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3669 reg
= FDI_RX_CTL(pipe
);
3670 temp
= I915_READ(reg
);
3671 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3672 temp
|= FDI_COMPOSITE_SYNC
;
3673 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3676 udelay(1); /* should be 0.5us */
3678 for (i
= 0; i
< 4; i
++) {
3679 reg
= FDI_RX_IIR(pipe
);
3680 temp
= I915_READ(reg
);
3681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3683 if (temp
& FDI_RX_BIT_LOCK
||
3684 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3685 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3690 udelay(1); /* should be 0.5us */
3693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3698 reg
= FDI_TX_CTL(pipe
);
3699 temp
= I915_READ(reg
);
3700 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3701 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3702 I915_WRITE(reg
, temp
);
3704 reg
= FDI_RX_CTL(pipe
);
3705 temp
= I915_READ(reg
);
3706 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3707 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3708 I915_WRITE(reg
, temp
);
3711 udelay(2); /* should be 1.5us */
3713 for (i
= 0; i
< 4; i
++) {
3714 reg
= FDI_RX_IIR(pipe
);
3715 temp
= I915_READ(reg
);
3716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3718 if (temp
& FDI_RX_SYMBOL_LOCK
||
3719 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3720 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3725 udelay(2); /* should be 1.5us */
3728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3732 DRM_DEBUG_KMS("FDI train done.\n");
3735 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3737 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3739 int pipe
= intel_crtc
->pipe
;
3743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3744 reg
= FDI_RX_CTL(pipe
);
3745 temp
= I915_READ(reg
);
3746 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3747 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3748 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3749 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3754 /* Switch from Rawclk to PCDclk */
3755 temp
= I915_READ(reg
);
3756 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3761 /* Enable CPU FDI TX PLL, always on for Ironlake */
3762 reg
= FDI_TX_CTL(pipe
);
3763 temp
= I915_READ(reg
);
3764 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3765 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3772 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3774 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3776 int pipe
= intel_crtc
->pipe
;
3779 /* Switch from PCDclk to Rawclk */
3780 reg
= FDI_RX_CTL(pipe
);
3781 temp
= I915_READ(reg
);
3782 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3784 /* Disable CPU FDI TX PLL */
3785 reg
= FDI_TX_CTL(pipe
);
3786 temp
= I915_READ(reg
);
3787 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3792 reg
= FDI_RX_CTL(pipe
);
3793 temp
= I915_READ(reg
);
3794 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3796 /* Wait for the clocks to turn off. */
3801 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3803 struct drm_device
*dev
= crtc
->dev
;
3804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3805 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3806 int pipe
= intel_crtc
->pipe
;
3809 /* disable CPU FDI tx and PCH FDI rx */
3810 reg
= FDI_TX_CTL(pipe
);
3811 temp
= I915_READ(reg
);
3812 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3815 reg
= FDI_RX_CTL(pipe
);
3816 temp
= I915_READ(reg
);
3817 temp
&= ~(0x7 << 16);
3818 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3819 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3824 /* Ironlake workaround, disable clock pointer after downing FDI */
3825 if (HAS_PCH_IBX(dev
))
3826 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3828 /* still set train pattern 1 */
3829 reg
= FDI_TX_CTL(pipe
);
3830 temp
= I915_READ(reg
);
3831 temp
&= ~FDI_LINK_TRAIN_NONE
;
3832 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3833 I915_WRITE(reg
, temp
);
3835 reg
= FDI_RX_CTL(pipe
);
3836 temp
= I915_READ(reg
);
3837 if (HAS_PCH_CPT(dev
)) {
3838 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3839 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3841 temp
&= ~FDI_LINK_TRAIN_NONE
;
3842 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3844 /* BPC in FDI rx is consistent with that in PIPECONF */
3845 temp
&= ~(0x07 << 16);
3846 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3847 I915_WRITE(reg
, temp
);
3853 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3855 struct intel_crtc
*crtc
;
3857 /* Note that we don't need to be called with mode_config.lock here
3858 * as our list of CRTC objects is static for the lifetime of the
3859 * device and so cannot disappear as we iterate. Similarly, we can
3860 * happily treat the predicates as racy, atomic checks as userspace
3861 * cannot claim and pin a new fb without at least acquring the
3862 * struct_mutex and so serialising with us.
3864 for_each_intel_crtc(dev
, crtc
) {
3865 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3868 if (crtc
->unpin_work
)
3869 intel_wait_for_vblank(dev
, crtc
->pipe
);
3877 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3879 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3880 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3882 /* ensure that the unpin work is consistent wrt ->pending. */
3884 intel_crtc
->unpin_work
= NULL
;
3887 drm_send_vblank_event(intel_crtc
->base
.dev
,
3891 drm_crtc_vblank_put(&intel_crtc
->base
);
3893 wake_up_all(&dev_priv
->pending_flip_queue
);
3894 queue_work(dev_priv
->wq
, &work
->work
);
3896 trace_i915_flip_complete(intel_crtc
->plane
,
3897 work
->pending_flip_obj
);
3900 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3902 struct drm_device
*dev
= crtc
->dev
;
3903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3905 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3906 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3907 !intel_crtc_has_pending_flip(crtc
),
3909 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3911 spin_lock_irq(&dev
->event_lock
);
3912 if (intel_crtc
->unpin_work
) {
3913 WARN_ONCE(1, "Removing stuck page flip\n");
3914 page_flip_completed(intel_crtc
);
3916 spin_unlock_irq(&dev
->event_lock
);
3919 if (crtc
->primary
->fb
) {
3920 mutex_lock(&dev
->struct_mutex
);
3921 intel_finish_fb(crtc
->primary
->fb
);
3922 mutex_unlock(&dev
->struct_mutex
);
3926 /* Program iCLKIP clock to the desired frequency */
3927 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3929 struct drm_device
*dev
= crtc
->dev
;
3930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3931 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3932 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3935 mutex_lock(&dev_priv
->sb_lock
);
3937 /* It is necessary to ungate the pixclk gate prior to programming
3938 * the divisors, and gate it back when it is done.
3940 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3942 /* Disable SSCCTL */
3943 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3944 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3949 if (clock
== 20000) {
3954 /* The iCLK virtual clock root frequency is in MHz,
3955 * but the adjusted_mode->crtc_clock in in KHz. To get the
3956 * divisors, it is necessary to divide one by another, so we
3957 * convert the virtual clock precision to KHz here for higher
3960 u32 iclk_virtual_root_freq
= 172800 * 1000;
3961 u32 iclk_pi_range
= 64;
3962 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3964 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3965 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3966 pi_value
= desired_divisor
% iclk_pi_range
;
3969 divsel
= msb_divisor_value
- 2;
3970 phaseinc
= pi_value
;
3973 /* This should not happen with any sane values */
3974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3986 /* Program SSCDIVINTPHASE6 */
3987 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3988 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3989 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3990 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3991 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3992 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3993 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3994 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3996 /* Program SSCAUXDIV */
3997 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3998 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3999 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4000 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4002 /* Enable modulator and associated divider */
4003 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4004 temp
&= ~SBI_SSCCTL_DISABLE
;
4005 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4007 /* Wait for initialization time */
4010 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4012 mutex_unlock(&dev_priv
->sb_lock
);
4015 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4016 enum pipe pch_transcoder
)
4018 struct drm_device
*dev
= crtc
->base
.dev
;
4019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4020 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4023 I915_READ(HTOTAL(cpu_transcoder
)));
4024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4025 I915_READ(HBLANK(cpu_transcoder
)));
4026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4027 I915_READ(HSYNC(cpu_transcoder
)));
4029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4030 I915_READ(VTOTAL(cpu_transcoder
)));
4031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4032 I915_READ(VBLANK(cpu_transcoder
)));
4033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4034 I915_READ(VSYNC(cpu_transcoder
)));
4035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4036 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4039 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4044 temp
= I915_READ(SOUTH_CHICKEN1
);
4045 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4048 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4049 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4051 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4053 temp
|= FDI_BC_BIFURCATION_SELECT
;
4055 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4056 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4057 POSTING_READ(SOUTH_CHICKEN1
);
4060 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4062 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4064 switch (intel_crtc
->pipe
) {
4068 if (intel_crtc
->config
->fdi_lanes
> 2)
4069 cpt_set_fdi_bc_bifurcation(dev
, false);
4071 cpt_set_fdi_bc_bifurcation(dev
, true);
4075 cpt_set_fdi_bc_bifurcation(dev
, true);
4084 * Enable PCH resources required for PCH ports:
4086 * - FDI training & RX/TX
4087 * - update transcoder timings
4088 * - DP transcoding bits
4091 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4093 struct drm_device
*dev
= crtc
->dev
;
4094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4095 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4096 int pipe
= intel_crtc
->pipe
;
4099 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4101 if (IS_IVYBRIDGE(dev
))
4102 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4104 /* Write the TU size bits before fdi link training, so that error
4105 * detection works. */
4106 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4107 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4109 /* For PCH output, training FDI link */
4110 dev_priv
->display
.fdi_link_train(crtc
);
4112 /* We need to program the right clock selection before writing the pixel
4113 * mutliplier into the DPLL. */
4114 if (HAS_PCH_CPT(dev
)) {
4117 temp
= I915_READ(PCH_DPLL_SEL
);
4118 temp
|= TRANS_DPLL_ENABLE(pipe
);
4119 sel
= TRANS_DPLLB_SEL(pipe
);
4120 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4124 I915_WRITE(PCH_DPLL_SEL
, temp
);
4127 /* XXX: pch pll's can be enabled any time before we enable the PCH
4128 * transcoder, and we actually should do this to not upset any PCH
4129 * transcoder that already use the clock when we share it.
4131 * Note that enable_shared_dpll tries to do the right thing, but
4132 * get_shared_dpll unconditionally resets the pll - we need that to have
4133 * the right LVDS enable sequence. */
4134 intel_enable_shared_dpll(intel_crtc
);
4136 /* set transcoder timing, panel must allow it */
4137 assert_panel_unlocked(dev_priv
, pipe
);
4138 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4140 intel_fdi_normal_train(crtc
);
4142 /* For PCH DP, enable TRANS_DP_CTL */
4143 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4144 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4145 reg
= TRANS_DP_CTL(pipe
);
4146 temp
= I915_READ(reg
);
4147 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4148 TRANS_DP_SYNC_MASK
|
4150 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4151 temp
|= bpc
<< 9; /* same format but at 11:9 */
4153 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4154 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4155 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4156 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4158 switch (intel_trans_dp_port_sel(crtc
)) {
4160 temp
|= TRANS_DP_PORT_SEL_B
;
4163 temp
|= TRANS_DP_PORT_SEL_C
;
4166 temp
|= TRANS_DP_PORT_SEL_D
;
4172 I915_WRITE(reg
, temp
);
4175 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4178 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4180 struct drm_device
*dev
= crtc
->dev
;
4181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4183 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4185 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4187 lpt_program_iclkip(crtc
);
4189 /* Set transcoder timing. */
4190 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4192 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4195 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4196 struct intel_crtc_state
*crtc_state
)
4198 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4199 struct intel_shared_dpll
*pll
;
4200 struct intel_shared_dpll_config
*shared_dpll
;
4201 enum intel_dpll_id i
;
4203 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
4205 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4206 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4207 i
= (enum intel_dpll_id
) crtc
->pipe
;
4208 pll
= &dev_priv
->shared_dplls
[i
];
4210 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4211 crtc
->base
.base
.id
, pll
->name
);
4213 WARN_ON(shared_dpll
[i
].crtc_mask
);
4218 if (IS_BROXTON(dev_priv
->dev
)) {
4219 /* PLL is attached to port in bxt */
4220 struct intel_encoder
*encoder
;
4221 struct intel_digital_port
*intel_dig_port
;
4223 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4224 if (WARN_ON(!encoder
))
4227 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4228 /* 1:1 mapping between ports and PLLs */
4229 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4230 pll
= &dev_priv
->shared_dplls
[i
];
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc
->base
.base
.id
, pll
->name
);
4233 WARN_ON(shared_dpll
[i
].crtc_mask
);
4238 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4239 pll
= &dev_priv
->shared_dplls
[i
];
4241 /* Only want to check enabled timings first */
4242 if (shared_dpll
[i
].crtc_mask
== 0)
4245 if (memcmp(&crtc_state
->dpll_hw_state
,
4246 &shared_dpll
[i
].hw_state
,
4247 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
4248 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4249 crtc
->base
.base
.id
, pll
->name
,
4250 shared_dpll
[i
].crtc_mask
,
4256 /* Ok no matching timings, maybe there's a free one? */
4257 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4258 pll
= &dev_priv
->shared_dplls
[i
];
4259 if (shared_dpll
[i
].crtc_mask
== 0) {
4260 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4261 crtc
->base
.base
.id
, pll
->name
);
4269 if (shared_dpll
[i
].crtc_mask
== 0)
4270 shared_dpll
[i
].hw_state
=
4271 crtc_state
->dpll_hw_state
;
4273 crtc_state
->shared_dpll
= i
;
4274 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4275 pipe_name(crtc
->pipe
));
4277 shared_dpll
[i
].crtc_mask
|= 1 << crtc
->pipe
;
4282 static void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
4284 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4285 struct intel_shared_dpll_config
*shared_dpll
;
4286 struct intel_shared_dpll
*pll
;
4287 enum intel_dpll_id i
;
4289 if (!to_intel_atomic_state(state
)->dpll_set
)
4292 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
4293 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4294 pll
= &dev_priv
->shared_dplls
[i
];
4295 pll
->config
= shared_dpll
[i
];
4299 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4302 int dslreg
= PIPEDSL(pipe
);
4305 temp
= I915_READ(dslreg
);
4307 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4308 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4314 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4315 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4316 int src_w
, int src_h
, int dst_w
, int dst_h
)
4318 struct intel_crtc_scaler_state
*scaler_state
=
4319 &crtc_state
->scaler_state
;
4320 struct intel_crtc
*intel_crtc
=
4321 to_intel_crtc(crtc_state
->base
.crtc
);
4324 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4325 (src_h
!= dst_w
|| src_w
!= dst_h
):
4326 (src_w
!= dst_w
|| src_h
!= dst_h
);
4329 * if plane is being disabled or scaler is no more required or force detach
4330 * - free scaler binded to this plane/crtc
4331 * - in order to do this, update crtc->scaler_usage
4333 * Here scaler state in crtc_state is set free so that
4334 * scaler can be assigned to other user. Actual register
4335 * update to free the scaler is done in plane/panel-fit programming.
4336 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4338 if (force_detach
|| !need_scaling
) {
4339 if (*scaler_id
>= 0) {
4340 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4341 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4343 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4344 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4345 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4346 scaler_state
->scaler_users
);
4353 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4354 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4356 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4357 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4358 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4359 "size is out of scaler range\n",
4360 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4364 /* mark this plane as a scaler user in crtc_state */
4365 scaler_state
->scaler_users
|= (1 << scaler_user
);
4366 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4367 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4368 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4369 scaler_state
->scaler_users
);
4375 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4377 * @state: crtc's scaler state
4378 * @force_detach: whether to forcibly disable scaler
4381 * 0 - scaler_usage updated successfully
4382 * error - requested scaling cannot be supported or other error condition
4384 int skl_update_scaler_crtc(struct intel_crtc_state
*state
, int force_detach
)
4386 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4387 struct drm_display_mode
*adjusted_mode
=
4388 &state
->base
.adjusted_mode
;
4390 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4391 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4393 return skl_update_scaler(state
, force_detach
, SKL_CRTC_INDEX
,
4394 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4395 state
->pipe_src_w
, state
->pipe_src_h
,
4396 adjusted_mode
->hdisplay
, adjusted_mode
->hdisplay
);
4400 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4402 * @state: crtc's scaler state
4403 * @plane_state: atomic plane state to update
4406 * 0 - scaler_usage updated successfully
4407 * error - requested scaling cannot be supported or other error condition
4409 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4410 struct intel_plane_state
*plane_state
)
4413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4414 struct intel_plane
*intel_plane
=
4415 to_intel_plane(plane_state
->base
.plane
);
4416 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4419 bool force_detach
= !fb
|| !plane_state
->visible
;
4421 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4422 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4423 drm_plane_index(&intel_plane
->base
));
4425 ret
= skl_update_scaler(crtc_state
, force_detach
,
4426 drm_plane_index(&intel_plane
->base
),
4427 &plane_state
->scaler_id
,
4428 plane_state
->base
.rotation
,
4429 drm_rect_width(&plane_state
->src
) >> 16,
4430 drm_rect_height(&plane_state
->src
) >> 16,
4431 drm_rect_width(&plane_state
->dst
),
4432 drm_rect_height(&plane_state
->dst
));
4434 if (ret
|| plane_state
->scaler_id
< 0)
4437 /* check colorkey */
4438 if (WARN_ON(intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
)) {
4439 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4440 intel_plane
->base
.base
.id
);
4444 /* Check src format */
4445 switch (fb
->pixel_format
) {
4446 case DRM_FORMAT_RGB565
:
4447 case DRM_FORMAT_XBGR8888
:
4448 case DRM_FORMAT_XRGB8888
:
4449 case DRM_FORMAT_ABGR8888
:
4450 case DRM_FORMAT_ARGB8888
:
4451 case DRM_FORMAT_XRGB2101010
:
4452 case DRM_FORMAT_XBGR2101010
:
4453 case DRM_FORMAT_YUYV
:
4454 case DRM_FORMAT_YVYU
:
4455 case DRM_FORMAT_UYVY
:
4456 case DRM_FORMAT_VYUY
:
4459 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4460 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4467 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4469 struct drm_device
*dev
= crtc
->base
.dev
;
4470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4471 int pipe
= crtc
->pipe
;
4472 struct intel_crtc_scaler_state
*scaler_state
=
4473 &crtc
->config
->scaler_state
;
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4477 /* To update pfit, first update scaler state */
4478 skl_update_scaler_crtc(crtc
->config
, !enable
);
4479 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4480 skl_detach_scalers(crtc
);
4484 if (crtc
->config
->pch_pfit
.enabled
) {
4487 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4488 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4492 id
= scaler_state
->scaler_id
;
4493 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4494 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4495 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4496 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4498 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4502 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4504 struct drm_device
*dev
= crtc
->base
.dev
;
4505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4506 int pipe
= crtc
->pipe
;
4508 if (crtc
->config
->pch_pfit
.enabled
) {
4509 /* Force use of hard-coded filter coefficients
4510 * as some pre-programmed values are broken,
4513 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4514 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4515 PF_PIPE_SEL_IVB(pipe
));
4517 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4518 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4519 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4523 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4525 struct drm_device
*dev
= crtc
->dev
;
4526 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4527 struct drm_plane
*plane
;
4528 struct intel_plane
*intel_plane
;
4530 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4531 intel_plane
= to_intel_plane(plane
);
4532 if (intel_plane
->pipe
== pipe
)
4533 intel_plane_restore(&intel_plane
->base
);
4537 void hsw_enable_ips(struct intel_crtc
*crtc
)
4539 struct drm_device
*dev
= crtc
->base
.dev
;
4540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4542 if (!crtc
->config
->ips_enabled
)
4545 /* We can only enable IPS after we enable a plane and wait for a vblank */
4546 intel_wait_for_vblank(dev
, crtc
->pipe
);
4548 assert_plane_enabled(dev_priv
, crtc
->plane
);
4549 if (IS_BROADWELL(dev
)) {
4550 mutex_lock(&dev_priv
->rps
.hw_lock
);
4551 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4552 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4553 /* Quoting Art Runyan: "its not safe to expect any particular
4554 * value in IPS_CTL bit 31 after enabling IPS through the
4555 * mailbox." Moreover, the mailbox may return a bogus state,
4556 * so we need to just enable it and continue on.
4559 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4560 /* The bit only becomes 1 in the next vblank, so this wait here
4561 * is essentially intel_wait_for_vblank. If we don't have this
4562 * and don't wait for vblanks until the end of crtc_enable, then
4563 * the HW state readout code will complain that the expected
4564 * IPS_CTL value is not the one we read. */
4565 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4566 DRM_ERROR("Timed out waiting for IPS enable\n");
4570 void hsw_disable_ips(struct intel_crtc
*crtc
)
4572 struct drm_device
*dev
= crtc
->base
.dev
;
4573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4575 if (!crtc
->config
->ips_enabled
)
4578 assert_plane_enabled(dev_priv
, crtc
->plane
);
4579 if (IS_BROADWELL(dev
)) {
4580 mutex_lock(&dev_priv
->rps
.hw_lock
);
4581 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4582 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4583 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4584 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4585 DRM_ERROR("Timed out waiting for IPS disable\n");
4587 I915_WRITE(IPS_CTL
, 0);
4588 POSTING_READ(IPS_CTL
);
4591 /* We need to wait for a vblank before we can disable the plane. */
4592 intel_wait_for_vblank(dev
, crtc
->pipe
);
4595 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4596 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4598 struct drm_device
*dev
= crtc
->dev
;
4599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4600 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4601 enum pipe pipe
= intel_crtc
->pipe
;
4602 int palreg
= PALETTE(pipe
);
4604 bool reenable_ips
= false;
4606 /* The clocks have to be on to load the palette. */
4607 if (!crtc
->state
->active
)
4610 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4611 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4612 assert_dsi_pll_enabled(dev_priv
);
4614 assert_pll_enabled(dev_priv
, pipe
);
4617 /* use legacy palette for Ironlake */
4618 if (!HAS_GMCH_DISPLAY(dev
))
4619 palreg
= LGC_PALETTE(pipe
);
4621 /* Workaround : Do not read or write the pipe palette/gamma data while
4622 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4624 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4625 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4626 GAMMA_MODE_MODE_SPLIT
)) {
4627 hsw_disable_ips(intel_crtc
);
4628 reenable_ips
= true;
4631 for (i
= 0; i
< 256; i
++) {
4632 I915_WRITE(palreg
+ 4 * i
,
4633 (intel_crtc
->lut_r
[i
] << 16) |
4634 (intel_crtc
->lut_g
[i
] << 8) |
4635 intel_crtc
->lut_b
[i
]);
4639 hsw_enable_ips(intel_crtc
);
4642 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4644 if (intel_crtc
->overlay
) {
4645 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4648 mutex_lock(&dev
->struct_mutex
);
4649 dev_priv
->mm
.interruptible
= false;
4650 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4651 dev_priv
->mm
.interruptible
= true;
4652 mutex_unlock(&dev
->struct_mutex
);
4655 /* Let userspace switch the overlay on again. In most cases userspace
4656 * has to recompute where to put it anyway.
4661 * intel_post_enable_primary - Perform operations after enabling primary plane
4662 * @crtc: the CRTC whose primary plane was just enabled
4664 * Performs potentially sleeping operations that must be done after the primary
4665 * plane is enabled, such as updating FBC and IPS. Note that this may be
4666 * called due to an explicit primary plane update, or due to an implicit
4667 * re-enable that is caused when a sprite plane is updated to no longer
4668 * completely hide the primary plane.
4671 intel_post_enable_primary(struct drm_crtc
*crtc
)
4673 struct drm_device
*dev
= crtc
->dev
;
4674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4676 int pipe
= intel_crtc
->pipe
;
4679 * BDW signals flip done immediately if the plane
4680 * is disabled, even if the plane enable is already
4681 * armed to occur at the next vblank :(
4683 if (IS_BROADWELL(dev
))
4684 intel_wait_for_vblank(dev
, pipe
);
4687 * FIXME IPS should be fine as long as one plane is
4688 * enabled, but in practice it seems to have problems
4689 * when going from primary only to sprite only and vice
4692 hsw_enable_ips(intel_crtc
);
4694 mutex_lock(&dev
->struct_mutex
);
4695 intel_fbc_update(dev
);
4696 mutex_unlock(&dev
->struct_mutex
);
4699 * Gen2 reports pipe underruns whenever all planes are disabled.
4700 * So don't enable underrun reporting before at least some planes
4702 * FIXME: Need to fix the logic to work when we turn off all planes
4703 * but leave the pipe running.
4706 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4708 /* Underruns don't raise interrupts, so check manually. */
4709 if (HAS_GMCH_DISPLAY(dev
))
4710 i9xx_check_fifo_underruns(dev_priv
);
4714 * intel_pre_disable_primary - Perform operations before disabling primary plane
4715 * @crtc: the CRTC whose primary plane is to be disabled
4717 * Performs potentially sleeping operations that must be done before the
4718 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4719 * be called due to an explicit primary plane update, or due to an implicit
4720 * disable that is caused when a sprite plane completely hides the primary
4724 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4726 struct drm_device
*dev
= crtc
->dev
;
4727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4728 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4729 int pipe
= intel_crtc
->pipe
;
4732 * Gen2 reports pipe underruns whenever all planes are disabled.
4733 * So diasble underrun reporting before all the planes get disabled.
4734 * FIXME: Need to fix the logic to work when we turn off all planes
4735 * but leave the pipe running.
4738 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4741 * Vblank time updates from the shadow to live plane control register
4742 * are blocked if the memory self-refresh mode is active at that
4743 * moment. So to make sure the plane gets truly disabled, disable
4744 * first the self-refresh mode. The self-refresh enable bit in turn
4745 * will be checked/applied by the HW only at the next frame start
4746 * event which is after the vblank start event, so we need to have a
4747 * wait-for-vblank between disabling the plane and the pipe.
4749 if (HAS_GMCH_DISPLAY(dev
))
4750 intel_set_memory_cxsr(dev_priv
, false);
4752 mutex_lock(&dev
->struct_mutex
);
4753 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4754 intel_fbc_disable(dev
);
4755 mutex_unlock(&dev
->struct_mutex
);
4758 * FIXME IPS should be fine as long as one plane is
4759 * enabled, but in practice it seems to have problems
4760 * when going from primary only to sprite only and vice
4763 hsw_disable_ips(intel_crtc
);
4766 static void intel_post_plane_update(struct intel_crtc
*crtc
)
4768 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4769 struct drm_device
*dev
= crtc
->base
.dev
;
4770 struct drm_plane
*plane
;
4772 if (atomic
->wait_vblank
)
4773 intel_wait_for_vblank(dev
, crtc
->pipe
);
4775 intel_frontbuffer_flip(dev
, atomic
->fb_bits
);
4777 if (atomic
->update_fbc
) {
4778 mutex_lock(&dev
->struct_mutex
);
4779 intel_fbc_update(dev
);
4780 mutex_unlock(&dev
->struct_mutex
);
4783 if (atomic
->post_enable_primary
)
4784 intel_post_enable_primary(&crtc
->base
);
4786 drm_for_each_plane_mask(plane
, dev
, atomic
->update_sprite_watermarks
)
4787 intel_update_sprite_watermarks(plane
, &crtc
->base
,
4788 0, 0, 0, false, false);
4790 memset(atomic
, 0, sizeof(*atomic
));
4793 static void intel_pre_plane_update(struct intel_crtc
*crtc
)
4795 struct drm_device
*dev
= crtc
->base
.dev
;
4796 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4797 struct drm_plane
*p
;
4799 /* Track fb's for any planes being disabled */
4801 drm_for_each_plane_mask(p
, dev
, atomic
->disabled_planes
) {
4802 struct intel_plane
*plane
= to_intel_plane(p
);
4803 unsigned fb_bits
= 0;
4806 case DRM_PLANE_TYPE_PRIMARY
:
4807 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(plane
->pipe
);
4809 case DRM_PLANE_TYPE_CURSOR
:
4810 fb_bits
= INTEL_FRONTBUFFER_CURSOR(plane
->pipe
);
4812 case DRM_PLANE_TYPE_OVERLAY
:
4813 fb_bits
= INTEL_FRONTBUFFER_SPRITE(plane
->pipe
);
4817 mutex_lock(&dev
->struct_mutex
);
4818 i915_gem_track_fb(intel_fb_obj(plane
->base
.fb
), NULL
, fb_bits
);
4819 mutex_unlock(&dev
->struct_mutex
);
4822 if (atomic
->wait_for_flips
)
4823 intel_crtc_wait_for_pending_flips(&crtc
->base
);
4825 if (atomic
->disable_fbc
)
4826 intel_fbc_disable(dev
);
4828 if (atomic
->pre_disable_primary
)
4829 intel_pre_disable_primary(&crtc
->base
);
4832 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4834 struct drm_device
*dev
= crtc
->dev
;
4835 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4836 int pipe
= intel_crtc
->pipe
;
4838 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4839 intel_enable_sprite_planes(crtc
);
4840 if (to_intel_plane_state(crtc
->cursor
->state
)->visible
)
4841 intel_crtc_update_cursor(crtc
, true);
4843 intel_post_enable_primary(crtc
);
4846 * FIXME: Once we grow proper nuclear flip support out of this we need
4847 * to compute the mask of flip planes precisely. For the time being
4848 * consider this a flip to a NULL plane.
4850 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4853 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4855 struct drm_device
*dev
= crtc
->dev
;
4856 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4857 struct intel_plane
*intel_plane
;
4858 int pipe
= intel_crtc
->pipe
;
4860 intel_crtc_wait_for_pending_flips(crtc
);
4862 intel_pre_disable_primary(crtc
);
4864 intel_crtc_dpms_overlay_disable(intel_crtc
);
4865 for_each_intel_plane(dev
, intel_plane
) {
4866 if (intel_plane
->pipe
== pipe
) {
4867 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4869 intel_plane
->disable_plane(&intel_plane
->base
,
4875 * FIXME: Once we grow proper nuclear flip support out of this we need
4876 * to compute the mask of flip planes precisely. For the time being
4877 * consider this a flip to a NULL plane.
4879 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4882 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4884 struct drm_device
*dev
= crtc
->dev
;
4885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4887 struct intel_encoder
*encoder
;
4888 int pipe
= intel_crtc
->pipe
;
4890 if (WARN_ON(intel_crtc
->active
))
4893 if (intel_crtc
->config
->has_pch_encoder
)
4894 intel_prepare_shared_dpll(intel_crtc
);
4896 if (intel_crtc
->config
->has_dp_encoder
)
4897 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4899 intel_set_pipe_timings(intel_crtc
);
4901 if (intel_crtc
->config
->has_pch_encoder
) {
4902 intel_cpu_transcoder_set_m_n(intel_crtc
,
4903 &intel_crtc
->config
->fdi_m_n
, NULL
);
4906 ironlake_set_pipeconf(crtc
);
4908 intel_crtc
->active
= true;
4910 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4911 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4913 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4914 if (encoder
->pre_enable
)
4915 encoder
->pre_enable(encoder
);
4917 if (intel_crtc
->config
->has_pch_encoder
) {
4918 /* Note: FDI PLL enabling _must_ be done before we enable the
4919 * cpu pipes, hence this is separate from all the other fdi/pch
4921 ironlake_fdi_pll_enable(intel_crtc
);
4923 assert_fdi_tx_disabled(dev_priv
, pipe
);
4924 assert_fdi_rx_disabled(dev_priv
, pipe
);
4927 ironlake_pfit_enable(intel_crtc
);
4930 * On ILK+ LUT must be loaded before the pipe is running but with
4933 intel_crtc_load_lut(crtc
);
4935 intel_update_watermarks(crtc
);
4936 intel_enable_pipe(intel_crtc
);
4938 if (intel_crtc
->config
->has_pch_encoder
)
4939 ironlake_pch_enable(crtc
);
4941 assert_vblank_disabled(crtc
);
4942 drm_crtc_vblank_on(crtc
);
4944 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4945 encoder
->enable(encoder
);
4947 if (HAS_PCH_CPT(dev
))
4948 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4951 /* IPS only exists on ULT machines and is tied to pipe A. */
4952 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4954 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4957 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4959 struct drm_device
*dev
= crtc
->dev
;
4960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4961 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4962 struct intel_encoder
*encoder
;
4963 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4964 struct intel_crtc_state
*pipe_config
=
4965 to_intel_crtc_state(crtc
->state
);
4967 if (WARN_ON(intel_crtc
->active
))
4970 if (intel_crtc_to_shared_dpll(intel_crtc
))
4971 intel_enable_shared_dpll(intel_crtc
);
4973 if (intel_crtc
->config
->has_dp_encoder
)
4974 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4976 intel_set_pipe_timings(intel_crtc
);
4978 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4979 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4980 intel_crtc
->config
->pixel_multiplier
- 1);
4983 if (intel_crtc
->config
->has_pch_encoder
) {
4984 intel_cpu_transcoder_set_m_n(intel_crtc
,
4985 &intel_crtc
->config
->fdi_m_n
, NULL
);
4988 haswell_set_pipeconf(crtc
);
4990 intel_set_pipe_csc(crtc
);
4992 intel_crtc
->active
= true;
4994 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4995 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4996 if (encoder
->pre_enable
)
4997 encoder
->pre_enable(encoder
);
4999 if (intel_crtc
->config
->has_pch_encoder
) {
5000 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5002 dev_priv
->display
.fdi_link_train(crtc
);
5005 intel_ddi_enable_pipe_clock(intel_crtc
);
5007 if (INTEL_INFO(dev
)->gen
== 9)
5008 skylake_pfit_update(intel_crtc
, 1);
5009 else if (INTEL_INFO(dev
)->gen
< 9)
5010 ironlake_pfit_enable(intel_crtc
);
5012 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5015 * On ILK+ LUT must be loaded before the pipe is running but with
5018 intel_crtc_load_lut(crtc
);
5020 intel_ddi_set_pipe_settings(crtc
);
5021 intel_ddi_enable_transcoder_func(crtc
);
5023 intel_update_watermarks(crtc
);
5024 intel_enable_pipe(intel_crtc
);
5026 if (intel_crtc
->config
->has_pch_encoder
)
5027 lpt_pch_enable(crtc
);
5029 if (intel_crtc
->config
->dp_encoder_is_mst
)
5030 intel_ddi_set_vc_payload_alloc(crtc
, true);
5032 assert_vblank_disabled(crtc
);
5033 drm_crtc_vblank_on(crtc
);
5035 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5036 encoder
->enable(encoder
);
5037 intel_opregion_notify_encoder(encoder
, true);
5040 /* If we change the relative order between pipe/planes enabling, we need
5041 * to change the workaround. */
5042 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5043 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5044 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5045 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5049 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5051 struct drm_device
*dev
= crtc
->base
.dev
;
5052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5053 int pipe
= crtc
->pipe
;
5055 /* To avoid upsetting the power well on haswell only disable the pfit if
5056 * it's in use. The hw state code will make sure we get this right. */
5057 if (crtc
->config
->pch_pfit
.enabled
) {
5058 I915_WRITE(PF_CTL(pipe
), 0);
5059 I915_WRITE(PF_WIN_POS(pipe
), 0);
5060 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5064 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5066 struct drm_device
*dev
= crtc
->dev
;
5067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5068 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5069 struct intel_encoder
*encoder
;
5070 int pipe
= intel_crtc
->pipe
;
5073 if (WARN_ON(!intel_crtc
->active
))
5076 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5077 encoder
->disable(encoder
);
5079 drm_crtc_vblank_off(crtc
);
5080 assert_vblank_disabled(crtc
);
5082 if (intel_crtc
->config
->has_pch_encoder
)
5083 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5085 intel_disable_pipe(intel_crtc
);
5087 ironlake_pfit_disable(intel_crtc
);
5089 if (intel_crtc
->config
->has_pch_encoder
)
5090 ironlake_fdi_disable(crtc
);
5092 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5093 if (encoder
->post_disable
)
5094 encoder
->post_disable(encoder
);
5096 if (intel_crtc
->config
->has_pch_encoder
) {
5097 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5099 if (HAS_PCH_CPT(dev
)) {
5100 /* disable TRANS_DP_CTL */
5101 reg
= TRANS_DP_CTL(pipe
);
5102 temp
= I915_READ(reg
);
5103 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5104 TRANS_DP_PORT_SEL_MASK
);
5105 temp
|= TRANS_DP_PORT_SEL_NONE
;
5106 I915_WRITE(reg
, temp
);
5108 /* disable DPLL_SEL */
5109 temp
= I915_READ(PCH_DPLL_SEL
);
5110 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5111 I915_WRITE(PCH_DPLL_SEL
, temp
);
5114 /* disable PCH DPLL */
5115 intel_disable_shared_dpll(intel_crtc
);
5117 ironlake_fdi_pll_disable(intel_crtc
);
5120 intel_crtc
->active
= false;
5121 intel_update_watermarks(crtc
);
5123 mutex_lock(&dev
->struct_mutex
);
5124 intel_fbc_update(dev
);
5125 mutex_unlock(&dev
->struct_mutex
);
5128 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5130 struct drm_device
*dev
= crtc
->dev
;
5131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5133 struct intel_encoder
*encoder
;
5134 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5136 if (WARN_ON(!intel_crtc
->active
))
5139 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5140 intel_opregion_notify_encoder(encoder
, false);
5141 encoder
->disable(encoder
);
5144 drm_crtc_vblank_off(crtc
);
5145 assert_vblank_disabled(crtc
);
5147 if (intel_crtc
->config
->has_pch_encoder
)
5148 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5150 intel_disable_pipe(intel_crtc
);
5152 if (intel_crtc
->config
->dp_encoder_is_mst
)
5153 intel_ddi_set_vc_payload_alloc(crtc
, false);
5155 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5157 if (INTEL_INFO(dev
)->gen
== 9)
5158 skylake_pfit_update(intel_crtc
, 0);
5159 else if (INTEL_INFO(dev
)->gen
< 9)
5160 ironlake_pfit_disable(intel_crtc
);
5162 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5164 intel_ddi_disable_pipe_clock(intel_crtc
);
5166 if (intel_crtc
->config
->has_pch_encoder
) {
5167 lpt_disable_pch_transcoder(dev_priv
);
5168 intel_ddi_fdi_disable(crtc
);
5171 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5172 if (encoder
->post_disable
)
5173 encoder
->post_disable(encoder
);
5175 intel_crtc
->active
= false;
5176 intel_update_watermarks(crtc
);
5178 mutex_lock(&dev
->struct_mutex
);
5179 intel_fbc_update(dev
);
5180 mutex_unlock(&dev
->struct_mutex
);
5182 if (intel_crtc_to_shared_dpll(intel_crtc
))
5183 intel_disable_shared_dpll(intel_crtc
);
5186 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5188 struct drm_device
*dev
= crtc
->base
.dev
;
5189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5190 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5192 if (!pipe_config
->gmch_pfit
.control
)
5196 * The panel fitter should only be adjusted whilst the pipe is disabled,
5197 * according to register description and PRM.
5199 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5200 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5202 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5203 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5205 /* Border color in case we don't scale up to the full screen. Black by
5206 * default, change to something else for debugging. */
5207 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5210 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5214 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5216 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5218 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5220 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5223 return POWER_DOMAIN_PORT_OTHER
;
5227 #define for_each_power_domain(domain, mask) \
5228 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5229 if ((1 << (domain)) & (mask))
5231 enum intel_display_power_domain
5232 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5234 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5235 struct intel_digital_port
*intel_dig_port
;
5237 switch (intel_encoder
->type
) {
5238 case INTEL_OUTPUT_UNKNOWN
:
5239 /* Only DDI platforms should ever use this output type */
5240 WARN_ON_ONCE(!HAS_DDI(dev
));
5241 case INTEL_OUTPUT_DISPLAYPORT
:
5242 case INTEL_OUTPUT_HDMI
:
5243 case INTEL_OUTPUT_EDP
:
5244 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5245 return port_to_power_domain(intel_dig_port
->port
);
5246 case INTEL_OUTPUT_DP_MST
:
5247 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5248 return port_to_power_domain(intel_dig_port
->port
);
5249 case INTEL_OUTPUT_ANALOG
:
5250 return POWER_DOMAIN_PORT_CRT
;
5251 case INTEL_OUTPUT_DSI
:
5252 return POWER_DOMAIN_PORT_DSI
;
5254 return POWER_DOMAIN_PORT_OTHER
;
5258 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5260 struct drm_device
*dev
= crtc
->dev
;
5261 struct intel_encoder
*intel_encoder
;
5262 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5263 enum pipe pipe
= intel_crtc
->pipe
;
5265 enum transcoder transcoder
;
5267 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5269 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5270 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5271 if (intel_crtc
->config
->pch_pfit
.enabled
||
5272 intel_crtc
->config
->pch_pfit
.force_thru
)
5273 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5275 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5276 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5281 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5283 struct drm_device
*dev
= state
->dev
;
5284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5285 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5286 struct intel_crtc
*crtc
;
5289 * First get all needed power domains, then put all unneeded, to avoid
5290 * any unnecessary toggling of the power wells.
5292 for_each_intel_crtc(dev
, crtc
) {
5293 enum intel_display_power_domain domain
;
5295 if (!crtc
->base
.state
->enable
)
5298 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5300 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5301 intel_display_power_get(dev_priv
, domain
);
5304 if (dev_priv
->display
.modeset_global_resources
)
5305 dev_priv
->display
.modeset_global_resources(state
);
5307 for_each_intel_crtc(dev
, crtc
) {
5308 enum intel_display_power_domain domain
;
5310 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5311 intel_display_power_put(dev_priv
, domain
);
5313 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5316 intel_display_set_init_power(dev_priv
, false);
5319 static void intel_update_max_cdclk(struct drm_device
*dev
)
5321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5323 if (IS_SKYLAKE(dev
)) {
5324 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5326 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5327 dev_priv
->max_cdclk_freq
= 675000;
5328 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5329 dev_priv
->max_cdclk_freq
= 540000;
5330 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5331 dev_priv
->max_cdclk_freq
= 450000;
5333 dev_priv
->max_cdclk_freq
= 337500;
5334 } else if (IS_BROADWELL(dev
)) {
5336 * FIXME with extra cooling we can allow
5337 * 540 MHz for ULX and 675 Mhz for ULT.
5338 * How can we know if extra cooling is
5339 * available? PCI ID, VTB, something else?
5341 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5342 dev_priv
->max_cdclk_freq
= 450000;
5343 else if (IS_BDW_ULX(dev
))
5344 dev_priv
->max_cdclk_freq
= 450000;
5345 else if (IS_BDW_ULT(dev
))
5346 dev_priv
->max_cdclk_freq
= 540000;
5348 dev_priv
->max_cdclk_freq
= 675000;
5349 } else if (IS_CHERRYVIEW(dev
)) {
5350 dev_priv
->max_cdclk_freq
= 320000;
5351 } else if (IS_VALLEYVIEW(dev
)) {
5352 dev_priv
->max_cdclk_freq
= 400000;
5354 /* otherwise assume cdclk is fixed */
5355 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5358 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5359 dev_priv
->max_cdclk_freq
);
5362 static void intel_update_cdclk(struct drm_device
*dev
)
5364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5366 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5367 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5368 dev_priv
->cdclk_freq
);
5371 * Program the gmbus_freq based on the cdclk frequency.
5372 * BSpec erroneously claims we should aim for 4MHz, but
5373 * in fact 1MHz is the correct frequency.
5375 if (IS_VALLEYVIEW(dev
)) {
5377 * Program the gmbus_freq based on the cdclk frequency.
5378 * BSpec erroneously claims we should aim for 4MHz, but
5379 * in fact 1MHz is the correct frequency.
5381 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5384 if (dev_priv
->max_cdclk_freq
== 0)
5385 intel_update_max_cdclk(dev
);
5388 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5393 uint32_t current_freq
;
5396 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5397 switch (frequency
) {
5399 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5400 ratio
= BXT_DE_PLL_RATIO(60);
5403 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5404 ratio
= BXT_DE_PLL_RATIO(60);
5407 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5408 ratio
= BXT_DE_PLL_RATIO(60);
5411 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5412 ratio
= BXT_DE_PLL_RATIO(60);
5415 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5416 ratio
= BXT_DE_PLL_RATIO(65);
5420 * Bypass frequency with DE PLL disabled. Init ratio, divider
5421 * to suppress GCC warning.
5427 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5432 mutex_lock(&dev_priv
->rps
.hw_lock
);
5433 /* Inform power controller of upcoming frequency change */
5434 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5436 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5439 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5444 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5445 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5446 current_freq
= current_freq
* 500 + 1000;
5449 * DE PLL has to be disabled when
5450 * - setting to 19.2MHz (bypass, PLL isn't used)
5451 * - before setting to 624MHz (PLL needs toggling)
5452 * - before setting to any frequency from 624MHz (PLL needs toggling)
5454 if (frequency
== 19200 || frequency
== 624000 ||
5455 current_freq
== 624000) {
5456 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5458 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5460 DRM_ERROR("timout waiting for DE PLL unlock\n");
5463 if (frequency
!= 19200) {
5466 val
= I915_READ(BXT_DE_PLL_CTL
);
5467 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5469 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5471 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5473 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5474 DRM_ERROR("timeout waiting for DE PLL lock\n");
5476 val
= I915_READ(CDCLK_CTL
);
5477 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5480 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5483 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5484 if (frequency
>= 500000)
5485 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5487 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5488 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5489 val
|= (frequency
- 1000) / 500;
5490 I915_WRITE(CDCLK_CTL
, val
);
5493 mutex_lock(&dev_priv
->rps
.hw_lock
);
5494 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5495 DIV_ROUND_UP(frequency
, 25000));
5496 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5499 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5504 intel_update_cdclk(dev
);
5507 void broxton_init_cdclk(struct drm_device
*dev
)
5509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5513 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5514 * or else the reset will hang because there is no PCH to respond.
5515 * Move the handshake programming to initialization sequence.
5516 * Previously was left up to BIOS.
5518 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5519 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5520 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5522 /* Enable PG1 for cdclk */
5523 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5525 /* check if cd clock is enabled */
5526 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5527 DRM_DEBUG_KMS("Display already initialized\n");
5533 * - The initial CDCLK needs to be read from VBT.
5534 * Need to make this change after VBT has changes for BXT.
5535 * - check if setting the max (or any) cdclk freq is really necessary
5536 * here, it belongs to modeset time
5538 broxton_set_cdclk(dev
, 624000);
5540 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5541 POSTING_READ(DBUF_CTL
);
5545 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5546 DRM_ERROR("DBuf power enable timeout!\n");
5549 void broxton_uninit_cdclk(struct drm_device
*dev
)
5551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5553 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5554 POSTING_READ(DBUF_CTL
);
5558 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5559 DRM_ERROR("DBuf power disable timeout!\n");
5561 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5562 broxton_set_cdclk(dev
, 19200);
5564 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5567 static const struct skl_cdclk_entry
{
5570 } skl_cdclk_frequencies
[] = {
5571 { .freq
= 308570, .vco
= 8640 },
5572 { .freq
= 337500, .vco
= 8100 },
5573 { .freq
= 432000, .vco
= 8640 },
5574 { .freq
= 450000, .vco
= 8100 },
5575 { .freq
= 540000, .vco
= 8100 },
5576 { .freq
= 617140, .vco
= 8640 },
5577 { .freq
= 675000, .vco
= 8100 },
5580 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5582 return (freq
- 1000) / 500;
5585 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5589 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5590 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5592 if (e
->freq
== freq
)
5600 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5602 unsigned int min_freq
;
5605 /* select the minimum CDCLK before enabling DPLL 0 */
5606 val
= I915_READ(CDCLK_CTL
);
5607 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5608 val
|= CDCLK_FREQ_337_308
;
5610 if (required_vco
== 8640)
5615 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5617 I915_WRITE(CDCLK_CTL
, val
);
5618 POSTING_READ(CDCLK_CTL
);
5621 * We always enable DPLL0 with the lowest link rate possible, but still
5622 * taking into account the VCO required to operate the eDP panel at the
5623 * desired frequency. The usual DP link rates operate with a VCO of
5624 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5625 * The modeset code is responsible for the selection of the exact link
5626 * rate later on, with the constraint of choosing a frequency that
5627 * works with required_vco.
5629 val
= I915_READ(DPLL_CTRL1
);
5631 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5632 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5633 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5634 if (required_vco
== 8640)
5635 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5638 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5641 I915_WRITE(DPLL_CTRL1
, val
);
5642 POSTING_READ(DPLL_CTRL1
);
5644 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5646 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5647 DRM_ERROR("DPLL0 not locked\n");
5650 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5655 /* inform PCU we want to change CDCLK */
5656 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5657 mutex_lock(&dev_priv
->rps
.hw_lock
);
5658 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5659 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5661 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5664 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5668 for (i
= 0; i
< 15; i
++) {
5669 if (skl_cdclk_pcu_ready(dev_priv
))
5677 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5679 struct drm_device
*dev
= dev_priv
->dev
;
5680 u32 freq_select
, pcu_ack
;
5682 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5684 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5685 DRM_ERROR("failed to inform PCU about cdclk change\n");
5693 freq_select
= CDCLK_FREQ_450_432
;
5697 freq_select
= CDCLK_FREQ_540
;
5703 freq_select
= CDCLK_FREQ_337_308
;
5708 freq_select
= CDCLK_FREQ_675_617
;
5713 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5714 POSTING_READ(CDCLK_CTL
);
5716 /* inform PCU of the change */
5717 mutex_lock(&dev_priv
->rps
.hw_lock
);
5718 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5719 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5721 intel_update_cdclk(dev
);
5724 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5726 /* disable DBUF power */
5727 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5728 POSTING_READ(DBUF_CTL
);
5732 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5733 DRM_ERROR("DBuf power disable timeout\n");
5736 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) & ~LCPLL_PLL_ENABLE
);
5737 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5738 DRM_ERROR("Couldn't disable DPLL0\n");
5740 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5743 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5746 unsigned int required_vco
;
5748 /* enable PCH reset handshake */
5749 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5750 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5752 /* enable PG1 and Misc I/O */
5753 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5755 /* DPLL0 already enabed !? */
5756 if (I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
) {
5757 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5762 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5763 skl_dpll0_enable(dev_priv
, required_vco
);
5765 /* set CDCLK to the frequency the BIOS chose */
5766 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5768 /* enable DBUF power */
5769 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5770 POSTING_READ(DBUF_CTL
);
5774 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5775 DRM_ERROR("DBuf power enable timeout\n");
5778 /* returns HPLL frequency in kHz */
5779 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5781 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5783 /* Obtain SKU information */
5784 mutex_lock(&dev_priv
->sb_lock
);
5785 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5786 CCK_FUSE_HPLL_FREQ_MASK
;
5787 mutex_unlock(&dev_priv
->sb_lock
);
5789 return vco_freq
[hpll_freq
] * 1000;
5792 /* Adjust CDclk dividers to allow high res or save power if possible */
5793 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5798 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5799 != dev_priv
->cdclk_freq
);
5801 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5803 else if (cdclk
== 266667)
5808 mutex_lock(&dev_priv
->rps
.hw_lock
);
5809 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5810 val
&= ~DSPFREQGUAR_MASK
;
5811 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5812 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5813 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5814 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5816 DRM_ERROR("timed out waiting for CDclk change\n");
5818 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5820 mutex_lock(&dev_priv
->sb_lock
);
5822 if (cdclk
== 400000) {
5825 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5827 /* adjust cdclk divider */
5828 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5829 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5831 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5833 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5834 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5836 DRM_ERROR("timed out waiting for CDclk change\n");
5839 /* adjust self-refresh exit latency value */
5840 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5844 * For high bandwidth configs, we set a higher latency in the bunit
5845 * so that the core display fetch happens in time to avoid underruns.
5847 if (cdclk
== 400000)
5848 val
|= 4500 / 250; /* 4.5 usec */
5850 val
|= 3000 / 250; /* 3.0 usec */
5851 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5853 mutex_unlock(&dev_priv
->sb_lock
);
5855 intel_update_cdclk(dev
);
5858 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5863 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5864 != dev_priv
->cdclk_freq
);
5873 MISSING_CASE(cdclk
);
5878 * Specs are full of misinformation, but testing on actual
5879 * hardware has shown that we just need to write the desired
5880 * CCK divider into the Punit register.
5882 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5884 mutex_lock(&dev_priv
->rps
.hw_lock
);
5885 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5886 val
&= ~DSPFREQGUAR_MASK_CHV
;
5887 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5888 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5889 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5890 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5892 DRM_ERROR("timed out waiting for CDclk change\n");
5894 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5896 intel_update_cdclk(dev
);
5899 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5902 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5903 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5906 * Really only a few cases to deal with, as only 4 CDclks are supported:
5909 * 320/333MHz (depends on HPLL freq)
5911 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5912 * of the lower bin and adjust if needed.
5914 * We seem to get an unstable or solid color picture at 200MHz.
5915 * Not sure what's wrong. For now use 200MHz only when all pipes
5918 if (!IS_CHERRYVIEW(dev_priv
) &&
5919 max_pixclk
> freq_320
*limit
/100)
5921 else if (max_pixclk
> 266667*limit
/100)
5923 else if (max_pixclk
> 0)
5929 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5934 * - remove the guardband, it's not needed on BXT
5935 * - set 19.2MHz bypass frequency if there are no active pipes
5937 if (max_pixclk
> 576000*9/10)
5939 else if (max_pixclk
> 384000*9/10)
5941 else if (max_pixclk
> 288000*9/10)
5943 else if (max_pixclk
> 144000*9/10)
5949 /* Compute the max pixel clock for new configuration. Uses atomic state if
5950 * that's non-NULL, look at current state otherwise. */
5951 static int intel_mode_max_pixclk(struct drm_device
*dev
,
5952 struct drm_atomic_state
*state
)
5954 struct intel_crtc
*intel_crtc
;
5955 struct intel_crtc_state
*crtc_state
;
5958 for_each_intel_crtc(dev
, intel_crtc
) {
5961 intel_atomic_get_crtc_state(state
, intel_crtc
);
5963 crtc_state
= intel_crtc
->config
;
5964 if (IS_ERR(crtc_state
))
5965 return PTR_ERR(crtc_state
);
5967 if (!crtc_state
->base
.enable
)
5970 max_pixclk
= max(max_pixclk
,
5971 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5977 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
5979 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5980 struct drm_crtc
*crtc
;
5981 struct drm_crtc_state
*crtc_state
;
5982 int max_pixclk
= intel_mode_max_pixclk(state
->dev
, state
);
5988 if (IS_VALLEYVIEW(dev_priv
))
5989 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5991 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5993 if (cdclk
== dev_priv
->cdclk_freq
)
5996 /* add all active pipes to the state */
5997 for_each_crtc(state
->dev
, crtc
) {
5998 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5999 if (IS_ERR(crtc_state
))
6000 return PTR_ERR(crtc_state
);
6002 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
6005 crtc_state
->mode_changed
= true;
6007 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
6011 ret
= drm_atomic_add_affected_planes(state
, crtc
);
6019 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6021 unsigned int credits
, default_credits
;
6023 if (IS_CHERRYVIEW(dev_priv
))
6024 default_credits
= PFI_CREDIT(12);
6026 default_credits
= PFI_CREDIT(8);
6028 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
6029 /* CHV suggested value is 31 or 63 */
6030 if (IS_CHERRYVIEW(dev_priv
))
6031 credits
= PFI_CREDIT_63
;
6033 credits
= PFI_CREDIT(15);
6035 credits
= default_credits
;
6039 * WA - write default credits before re-programming
6040 * FIXME: should we also set the resend bit here?
6042 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6045 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6046 credits
| PFI_CREDIT_RESEND
);
6049 * FIXME is this guaranteed to clear
6050 * immediately or should we poll for it?
6052 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6055 static void valleyview_modeset_global_resources(struct drm_atomic_state
*old_state
)
6057 struct drm_device
*dev
= old_state
->dev
;
6058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6059 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
6062 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6064 if (WARN_ON(max_pixclk
< 0))
6067 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6069 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
6071 * FIXME: We can end up here with all power domains off, yet
6072 * with a CDCLK frequency other than the minimum. To account
6073 * for this take the PIPE-A power domain, which covers the HW
6074 * blocks needed for the following programming. This can be
6075 * removed once it's guaranteed that we get here either with
6076 * the minimum CDCLK set, or the required power domains
6079 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6081 if (IS_CHERRYVIEW(dev
))
6082 cherryview_set_cdclk(dev
, req_cdclk
);
6084 valleyview_set_cdclk(dev
, req_cdclk
);
6086 vlv_program_pfi_credits(dev_priv
);
6088 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6092 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6094 struct drm_device
*dev
= crtc
->dev
;
6095 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6096 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6097 struct intel_encoder
*encoder
;
6098 int pipe
= intel_crtc
->pipe
;
6101 if (WARN_ON(intel_crtc
->active
))
6104 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6107 if (IS_CHERRYVIEW(dev
))
6108 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6110 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6113 if (intel_crtc
->config
->has_dp_encoder
)
6114 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6116 intel_set_pipe_timings(intel_crtc
);
6118 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6121 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6122 I915_WRITE(CHV_CANVAS(pipe
), 0);
6125 i9xx_set_pipeconf(intel_crtc
);
6127 intel_crtc
->active
= true;
6129 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6131 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6132 if (encoder
->pre_pll_enable
)
6133 encoder
->pre_pll_enable(encoder
);
6136 if (IS_CHERRYVIEW(dev
))
6137 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6139 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6142 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6143 if (encoder
->pre_enable
)
6144 encoder
->pre_enable(encoder
);
6146 i9xx_pfit_enable(intel_crtc
);
6148 intel_crtc_load_lut(crtc
);
6150 intel_update_watermarks(crtc
);
6151 intel_enable_pipe(intel_crtc
);
6153 assert_vblank_disabled(crtc
);
6154 drm_crtc_vblank_on(crtc
);
6156 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6157 encoder
->enable(encoder
);
6160 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6162 struct drm_device
*dev
= crtc
->base
.dev
;
6163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6165 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6166 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6169 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6171 struct drm_device
*dev
= crtc
->dev
;
6172 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6173 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6174 struct intel_encoder
*encoder
;
6175 int pipe
= intel_crtc
->pipe
;
6177 if (WARN_ON(intel_crtc
->active
))
6180 i9xx_set_pll_dividers(intel_crtc
);
6182 if (intel_crtc
->config
->has_dp_encoder
)
6183 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6185 intel_set_pipe_timings(intel_crtc
);
6187 i9xx_set_pipeconf(intel_crtc
);
6189 intel_crtc
->active
= true;
6192 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6194 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6195 if (encoder
->pre_enable
)
6196 encoder
->pre_enable(encoder
);
6198 i9xx_enable_pll(intel_crtc
);
6200 i9xx_pfit_enable(intel_crtc
);
6202 intel_crtc_load_lut(crtc
);
6204 intel_update_watermarks(crtc
);
6205 intel_enable_pipe(intel_crtc
);
6207 assert_vblank_disabled(crtc
);
6208 drm_crtc_vblank_on(crtc
);
6210 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6211 encoder
->enable(encoder
);
6214 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6216 struct drm_device
*dev
= crtc
->base
.dev
;
6217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6219 if (!crtc
->config
->gmch_pfit
.control
)
6222 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6224 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6225 I915_READ(PFIT_CONTROL
));
6226 I915_WRITE(PFIT_CONTROL
, 0);
6229 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6231 struct drm_device
*dev
= crtc
->dev
;
6232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6233 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6234 struct intel_encoder
*encoder
;
6235 int pipe
= intel_crtc
->pipe
;
6237 if (WARN_ON(!intel_crtc
->active
))
6241 * On gen2 planes are double buffered but the pipe isn't, so we must
6242 * wait for planes to fully turn off before disabling the pipe.
6243 * We also need to wait on all gmch platforms because of the
6244 * self-refresh mode constraint explained above.
6246 intel_wait_for_vblank(dev
, pipe
);
6248 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6249 encoder
->disable(encoder
);
6251 drm_crtc_vblank_off(crtc
);
6252 assert_vblank_disabled(crtc
);
6254 intel_disable_pipe(intel_crtc
);
6256 i9xx_pfit_disable(intel_crtc
);
6258 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6259 if (encoder
->post_disable
)
6260 encoder
->post_disable(encoder
);
6262 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6263 if (IS_CHERRYVIEW(dev
))
6264 chv_disable_pll(dev_priv
, pipe
);
6265 else if (IS_VALLEYVIEW(dev
))
6266 vlv_disable_pll(dev_priv
, pipe
);
6268 i9xx_disable_pll(intel_crtc
);
6272 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6274 intel_crtc
->active
= false;
6275 intel_update_watermarks(crtc
);
6277 mutex_lock(&dev
->struct_mutex
);
6278 intel_fbc_update(dev
);
6279 mutex_unlock(&dev
->struct_mutex
);
6282 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6285 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6286 enum intel_display_power_domain domain
;
6287 unsigned long domains
;
6289 if (!intel_crtc
->active
)
6292 intel_crtc_disable_planes(crtc
);
6293 dev_priv
->display
.crtc_disable(crtc
);
6295 domains
= intel_crtc
->enabled_power_domains
;
6296 for_each_power_domain(domain
, domains
)
6297 intel_display_power_put(dev_priv
, domain
);
6298 intel_crtc
->enabled_power_domains
= 0;
6302 * turn all crtc's off, but do not adjust state
6303 * This has to be paired with a call to intel_modeset_setup_hw_state.
6305 void intel_display_suspend(struct drm_device
*dev
)
6307 struct drm_crtc
*crtc
;
6309 for_each_crtc(dev
, crtc
)
6310 intel_crtc_disable_noatomic(crtc
);
6313 /* Master function to enable/disable CRTC and corresponding power wells */
6314 int intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6316 struct drm_device
*dev
= crtc
->dev
;
6317 struct drm_mode_config
*config
= &dev
->mode_config
;
6318 struct drm_modeset_acquire_ctx
*ctx
= config
->acquire_ctx
;
6319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6320 struct intel_crtc_state
*pipe_config
;
6321 struct drm_atomic_state
*state
;
6324 if (enable
== intel_crtc
->active
)
6327 if (enable
&& !crtc
->state
->enable
)
6330 /* this function should be called with drm_modeset_lock_all for now */
6333 lockdep_assert_held(&ctx
->ww_ctx
);
6335 state
= drm_atomic_state_alloc(dev
);
6336 if (WARN_ON(!state
))
6339 state
->acquire_ctx
= ctx
;
6340 state
->allow_modeset
= true;
6342 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6343 if (IS_ERR(pipe_config
)) {
6344 ret
= PTR_ERR(pipe_config
);
6347 pipe_config
->base
.active
= enable
;
6349 ret
= intel_set_mode(state
);
6354 DRM_ERROR("Updating crtc active failed with %i\n", ret
);
6355 drm_atomic_state_free(state
);
6360 * Sets the power management mode of the pipe and plane.
6362 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6364 struct drm_device
*dev
= crtc
->dev
;
6365 struct intel_encoder
*intel_encoder
;
6366 bool enable
= false;
6368 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6369 enable
|= intel_encoder
->connectors_active
;
6371 intel_crtc_control(crtc
, enable
);
6374 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6376 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6378 drm_encoder_cleanup(encoder
);
6379 kfree(intel_encoder
);
6382 /* Simple dpms helper for encoders with just one connector, no cloning and only
6383 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6384 * state of the entire output pipe. */
6385 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6387 if (mode
== DRM_MODE_DPMS_ON
) {
6388 encoder
->connectors_active
= true;
6390 intel_crtc_update_dpms(encoder
->base
.crtc
);
6392 encoder
->connectors_active
= false;
6394 intel_crtc_update_dpms(encoder
->base
.crtc
);
6398 /* Cross check the actual hw state with our own modeset state tracking (and it's
6399 * internal consistency). */
6400 static void intel_connector_check_state(struct intel_connector
*connector
)
6402 if (connector
->get_hw_state(connector
)) {
6403 struct intel_encoder
*encoder
= connector
->encoder
;
6404 struct drm_crtc
*crtc
;
6405 bool encoder_enabled
;
6408 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6409 connector
->base
.base
.id
,
6410 connector
->base
.name
);
6412 /* there is no real hw state for MST connectors */
6413 if (connector
->mst_port
)
6416 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6417 "wrong connector dpms state\n");
6418 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6419 "active connector not linked to encoder\n");
6422 I915_STATE_WARN(!encoder
->connectors_active
,
6423 "encoder->connectors_active not set\n");
6425 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6426 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6427 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6430 crtc
= encoder
->base
.crtc
;
6432 I915_STATE_WARN(!crtc
->state
->enable
,
6433 "crtc not enabled\n");
6434 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6435 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6436 "encoder active on the wrong pipe\n");
6441 int intel_connector_init(struct intel_connector
*connector
)
6443 struct drm_connector_state
*connector_state
;
6445 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6446 if (!connector_state
)
6449 connector
->base
.state
= connector_state
;
6453 struct intel_connector
*intel_connector_alloc(void)
6455 struct intel_connector
*connector
;
6457 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6461 if (intel_connector_init(connector
) < 0) {
6469 /* Even simpler default implementation, if there's really no special case to
6471 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6473 /* All the simple cases only support two dpms states. */
6474 if (mode
!= DRM_MODE_DPMS_ON
)
6475 mode
= DRM_MODE_DPMS_OFF
;
6477 if (mode
== connector
->dpms
)
6480 connector
->dpms
= mode
;
6482 /* Only need to change hw state when actually enabled */
6483 if (connector
->encoder
)
6484 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6486 intel_modeset_check_state(connector
->dev
);
6489 /* Simple connector->get_hw_state implementation for encoders that support only
6490 * one connector and no cloning and hence the encoder state determines the state
6491 * of the connector. */
6492 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6495 struct intel_encoder
*encoder
= connector
->encoder
;
6497 return encoder
->get_hw_state(encoder
, &pipe
);
6500 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6502 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6503 return crtc_state
->fdi_lanes
;
6508 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6509 struct intel_crtc_state
*pipe_config
)
6511 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6512 struct intel_crtc
*other_crtc
;
6513 struct intel_crtc_state
*other_crtc_state
;
6515 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6516 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6517 if (pipe_config
->fdi_lanes
> 4) {
6518 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6519 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6523 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6524 if (pipe_config
->fdi_lanes
> 2) {
6525 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6526 pipe_config
->fdi_lanes
);
6533 if (INTEL_INFO(dev
)->num_pipes
== 2)
6536 /* Ivybridge 3 pipe is really complicated */
6541 if (pipe_config
->fdi_lanes
<= 2)
6544 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6546 intel_atomic_get_crtc_state(state
, other_crtc
);
6547 if (IS_ERR(other_crtc_state
))
6548 return PTR_ERR(other_crtc_state
);
6550 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6551 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6552 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6557 if (pipe_config
->fdi_lanes
> 2) {
6558 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6559 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6563 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6565 intel_atomic_get_crtc_state(state
, other_crtc
);
6566 if (IS_ERR(other_crtc_state
))
6567 return PTR_ERR(other_crtc_state
);
6569 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6570 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6580 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6581 struct intel_crtc_state
*pipe_config
)
6583 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6584 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6585 int lane
, link_bw
, fdi_dotclock
, ret
;
6586 bool needs_recompute
= false;
6589 /* FDI is a binary signal running at ~2.7GHz, encoding
6590 * each output octet as 10 bits. The actual frequency
6591 * is stored as a divider into a 100MHz clock, and the
6592 * mode pixel clock is stored in units of 1KHz.
6593 * Hence the bw of each lane in terms of the mode signal
6596 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6598 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6600 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6601 pipe_config
->pipe_bpp
);
6603 pipe_config
->fdi_lanes
= lane
;
6605 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6606 link_bw
, &pipe_config
->fdi_m_n
);
6608 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6609 intel_crtc
->pipe
, pipe_config
);
6610 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6611 pipe_config
->pipe_bpp
-= 2*3;
6612 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6613 pipe_config
->pipe_bpp
);
6614 needs_recompute
= true;
6615 pipe_config
->bw_constrained
= true;
6620 if (needs_recompute
)
6626 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6627 struct intel_crtc_state
*pipe_config
)
6629 if (pipe_config
->pipe_bpp
> 24)
6632 /* HSW can handle pixel rate up to cdclk? */
6633 if (IS_HASWELL(dev_priv
->dev
))
6637 * We compare against max which means we must take
6638 * the increased cdclk requirement into account when
6639 * calculating the new cdclk.
6641 * Should measure whether using a lower cdclk w/o IPS
6643 return ilk_pipe_pixel_rate(pipe_config
) <=
6644 dev_priv
->max_cdclk_freq
* 95 / 100;
6647 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6648 struct intel_crtc_state
*pipe_config
)
6650 struct drm_device
*dev
= crtc
->base
.dev
;
6651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6653 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6654 hsw_crtc_supports_ips(crtc
) &&
6655 pipe_config_supports_ips(dev_priv
, pipe_config
);
6658 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6659 struct intel_crtc_state
*pipe_config
)
6661 struct drm_device
*dev
= crtc
->base
.dev
;
6662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6663 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6665 /* FIXME should check pixel clock limits on all platforms */
6666 if (INTEL_INFO(dev
)->gen
< 4) {
6667 int clock_limit
= dev_priv
->max_cdclk_freq
;
6670 * Enable pixel doubling when the dot clock
6671 * is > 90% of the (display) core speed.
6673 * GDG double wide on either pipe,
6674 * otherwise pipe A only.
6676 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6677 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6679 pipe_config
->double_wide
= true;
6682 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6687 * Pipe horizontal size must be even in:
6689 * - LVDS dual channel mode
6690 * - Double wide pipe
6692 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6693 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6694 pipe_config
->pipe_src_w
&= ~1;
6696 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6697 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6699 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6700 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6704 hsw_compute_ips_config(crtc
, pipe_config
);
6706 if (pipe_config
->has_pch_encoder
)
6707 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6712 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6714 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6715 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6716 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6719 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6720 return 24000; /* 24MHz is the cd freq with NSSC ref */
6722 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6725 linkrate
= (I915_READ(DPLL_CTRL1
) &
6726 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6728 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6729 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6731 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6732 case CDCLK_FREQ_450_432
:
6734 case CDCLK_FREQ_337_308
:
6736 case CDCLK_FREQ_675_617
:
6739 WARN(1, "Unknown cd freq selection\n");
6743 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6744 case CDCLK_FREQ_450_432
:
6746 case CDCLK_FREQ_337_308
:
6748 case CDCLK_FREQ_675_617
:
6751 WARN(1, "Unknown cd freq selection\n");
6755 /* error case, do as if DPLL0 isn't enabled */
6759 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6762 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6763 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6765 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6767 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6769 else if (freq
== LCPLL_CLK_FREQ_450
)
6771 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6773 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6779 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6782 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6783 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6785 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6787 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6789 else if (freq
== LCPLL_CLK_FREQ_450
)
6791 else if (IS_HSW_ULT(dev
))
6797 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6803 if (dev_priv
->hpll_freq
== 0)
6804 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6806 mutex_lock(&dev_priv
->sb_lock
);
6807 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6808 mutex_unlock(&dev_priv
->sb_lock
);
6810 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6812 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6813 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6814 "cdclk change in progress\n");
6816 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6819 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6824 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6829 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6834 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6839 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6843 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6845 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6846 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6848 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6850 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6852 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6855 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6856 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6858 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6863 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6867 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6869 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6872 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6873 case GC_DISPLAY_CLOCK_333_MHZ
:
6876 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6882 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6887 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6892 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6893 * encoding is different :(
6894 * FIXME is this the right way to detect 852GM/852GMV?
6896 if (dev
->pdev
->revision
== 0x1)
6899 pci_bus_read_config_word(dev
->pdev
->bus
,
6900 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6902 /* Assume that the hardware is in the high speed state. This
6903 * should be the default.
6905 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6906 case GC_CLOCK_133_200
:
6907 case GC_CLOCK_133_200_2
:
6908 case GC_CLOCK_100_200
:
6910 case GC_CLOCK_166_250
:
6912 case GC_CLOCK_100_133
:
6914 case GC_CLOCK_133_266
:
6915 case GC_CLOCK_133_266_2
:
6916 case GC_CLOCK_166_266
:
6920 /* Shouldn't happen */
6924 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6929 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6932 static const unsigned int blb_vco
[8] = {
6939 static const unsigned int pnv_vco
[8] = {
6946 static const unsigned int cl_vco
[8] = {
6955 static const unsigned int elk_vco
[8] = {
6961 static const unsigned int ctg_vco
[8] = {
6969 const unsigned int *vco_table
;
6973 /* FIXME other chipsets? */
6975 vco_table
= ctg_vco
;
6976 else if (IS_G4X(dev
))
6977 vco_table
= elk_vco
;
6978 else if (IS_CRESTLINE(dev
))
6980 else if (IS_PINEVIEW(dev
))
6981 vco_table
= pnv_vco
;
6982 else if (IS_G33(dev
))
6983 vco_table
= blb_vco
;
6987 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6989 vco
= vco_table
[tmp
& 0x7];
6991 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6993 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6998 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
7000 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7003 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7005 cdclk_sel
= (tmp
>> 12) & 0x1;
7011 return cdclk_sel
? 333333 : 222222;
7013 return cdclk_sel
? 320000 : 228571;
7015 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7020 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
7022 static const uint8_t div_3200
[] = { 16, 10, 8 };
7023 static const uint8_t div_4000
[] = { 20, 12, 10 };
7024 static const uint8_t div_5333
[] = { 24, 16, 14 };
7025 const uint8_t *div_table
;
7026 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7029 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7031 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7033 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7038 div_table
= div_3200
;
7041 div_table
= div_4000
;
7044 div_table
= div_5333
;
7050 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7053 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7057 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7059 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7060 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7061 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7062 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7063 const uint8_t *div_table
;
7064 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7067 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7069 cdclk_sel
= (tmp
>> 4) & 0x7;
7071 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7076 div_table
= div_3200
;
7079 div_table
= div_4000
;
7082 div_table
= div_4800
;
7085 div_table
= div_5333
;
7091 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7094 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7099 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7101 while (*num
> DATA_LINK_M_N_MASK
||
7102 *den
> DATA_LINK_M_N_MASK
) {
7108 static void compute_m_n(unsigned int m
, unsigned int n
,
7109 uint32_t *ret_m
, uint32_t *ret_n
)
7111 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7112 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7113 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7117 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7118 int pixel_clock
, int link_clock
,
7119 struct intel_link_m_n
*m_n
)
7123 compute_m_n(bits_per_pixel
* pixel_clock
,
7124 link_clock
* nlanes
* 8,
7125 &m_n
->gmch_m
, &m_n
->gmch_n
);
7127 compute_m_n(pixel_clock
, link_clock
,
7128 &m_n
->link_m
, &m_n
->link_n
);
7131 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7133 if (i915
.panel_use_ssc
>= 0)
7134 return i915
.panel_use_ssc
!= 0;
7135 return dev_priv
->vbt
.lvds_use_ssc
7136 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7139 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
7142 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7146 WARN_ON(!crtc_state
->base
.state
);
7148 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
7150 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7151 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7152 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7153 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7154 } else if (!IS_GEN2(dev
)) {
7163 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7165 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7168 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7170 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7173 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7174 struct intel_crtc_state
*crtc_state
,
7175 intel_clock_t
*reduced_clock
)
7177 struct drm_device
*dev
= crtc
->base
.dev
;
7180 if (IS_PINEVIEW(dev
)) {
7181 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7183 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7185 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7187 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7190 crtc_state
->dpll_hw_state
.fp0
= fp
;
7192 crtc
->lowfreq_avail
= false;
7193 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7195 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7196 crtc
->lowfreq_avail
= true;
7198 crtc_state
->dpll_hw_state
.fp1
= fp
;
7202 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7208 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7209 * and set it to a reasonable value instead.
7211 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7212 reg_val
&= 0xffffff00;
7213 reg_val
|= 0x00000030;
7214 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7216 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7217 reg_val
&= 0x8cffffff;
7218 reg_val
= 0x8c000000;
7219 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7221 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7222 reg_val
&= 0xffffff00;
7223 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7225 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7226 reg_val
&= 0x00ffffff;
7227 reg_val
|= 0xb0000000;
7228 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7231 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7232 struct intel_link_m_n
*m_n
)
7234 struct drm_device
*dev
= crtc
->base
.dev
;
7235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7236 int pipe
= crtc
->pipe
;
7238 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7239 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7240 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7241 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7244 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7245 struct intel_link_m_n
*m_n
,
7246 struct intel_link_m_n
*m2_n2
)
7248 struct drm_device
*dev
= crtc
->base
.dev
;
7249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7250 int pipe
= crtc
->pipe
;
7251 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7253 if (INTEL_INFO(dev
)->gen
>= 5) {
7254 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7255 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7256 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7257 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7258 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7259 * for gen < 8) and if DRRS is supported (to make sure the
7260 * registers are not unnecessarily accessed).
7262 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7263 crtc
->config
->has_drrs
) {
7264 I915_WRITE(PIPE_DATA_M2(transcoder
),
7265 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7266 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7267 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7268 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7271 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7272 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7273 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7274 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7278 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7280 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7283 dp_m_n
= &crtc
->config
->dp_m_n
;
7284 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7285 } else if (m_n
== M2_N2
) {
7288 * M2_N2 registers are not supported. Hence m2_n2 divider value
7289 * needs to be programmed into M1_N1.
7291 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7293 DRM_ERROR("Unsupported divider value\n");
7297 if (crtc
->config
->has_pch_encoder
)
7298 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7300 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7303 static void vlv_update_pll(struct intel_crtc
*crtc
,
7304 struct intel_crtc_state
*pipe_config
)
7309 * Enable DPIO clock input. We should never disable the reference
7310 * clock for pipe B, since VGA hotplug / manual detection depends
7313 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
7314 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
7315 /* We should never disable this, set it here for state tracking */
7316 if (crtc
->pipe
== PIPE_B
)
7317 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7318 dpll
|= DPLL_VCO_ENABLE
;
7319 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7321 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7322 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7323 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7326 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7327 const struct intel_crtc_state
*pipe_config
)
7329 struct drm_device
*dev
= crtc
->base
.dev
;
7330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7331 int pipe
= crtc
->pipe
;
7333 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7334 u32 coreclk
, reg_val
;
7336 mutex_lock(&dev_priv
->sb_lock
);
7338 bestn
= pipe_config
->dpll
.n
;
7339 bestm1
= pipe_config
->dpll
.m1
;
7340 bestm2
= pipe_config
->dpll
.m2
;
7341 bestp1
= pipe_config
->dpll
.p1
;
7342 bestp2
= pipe_config
->dpll
.p2
;
7344 /* See eDP HDMI DPIO driver vbios notes doc */
7346 /* PLL B needs special handling */
7348 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7350 /* Set up Tx target for periodic Rcomp update */
7351 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7353 /* Disable target IRef on PLL */
7354 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7355 reg_val
&= 0x00ffffff;
7356 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7358 /* Disable fast lock */
7359 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7361 /* Set idtafcrecal before PLL is enabled */
7362 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7363 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7364 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7365 mdiv
|= (1 << DPIO_K_SHIFT
);
7368 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7369 * but we don't support that).
7370 * Note: don't use the DAC post divider as it seems unstable.
7372 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7373 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7375 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7376 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7378 /* Set HBR and RBR LPF coefficients */
7379 if (pipe_config
->port_clock
== 162000 ||
7380 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7381 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7382 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7385 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7388 if (pipe_config
->has_dp_encoder
) {
7389 /* Use SSC source */
7391 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7394 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7396 } else { /* HDMI or VGA */
7397 /* Use bend source */
7399 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7402 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7406 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7407 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7409 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7410 coreclk
|= 0x01000000;
7411 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7413 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7414 mutex_unlock(&dev_priv
->sb_lock
);
7417 static void chv_update_pll(struct intel_crtc
*crtc
,
7418 struct intel_crtc_state
*pipe_config
)
7420 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
7421 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7423 if (crtc
->pipe
!= PIPE_A
)
7424 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7426 pipe_config
->dpll_hw_state
.dpll_md
=
7427 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7430 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7431 const struct intel_crtc_state
*pipe_config
)
7433 struct drm_device
*dev
= crtc
->base
.dev
;
7434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7435 int pipe
= crtc
->pipe
;
7436 int dpll_reg
= DPLL(crtc
->pipe
);
7437 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7438 u32 loopfilter
, tribuf_calcntr
;
7439 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7443 bestn
= pipe_config
->dpll
.n
;
7444 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7445 bestm1
= pipe_config
->dpll
.m1
;
7446 bestm2
= pipe_config
->dpll
.m2
>> 22;
7447 bestp1
= pipe_config
->dpll
.p1
;
7448 bestp2
= pipe_config
->dpll
.p2
;
7449 vco
= pipe_config
->dpll
.vco
;
7454 * Enable Refclk and SSC
7456 I915_WRITE(dpll_reg
,
7457 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7459 mutex_lock(&dev_priv
->sb_lock
);
7461 /* p1 and p2 divider */
7462 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7463 5 << DPIO_CHV_S1_DIV_SHIFT
|
7464 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7465 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7466 1 << DPIO_CHV_K_DIV_SHIFT
);
7468 /* Feedback post-divider - m2 */
7469 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7471 /* Feedback refclk divider - n and m1 */
7472 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7473 DPIO_CHV_M1_DIV_BY_2
|
7474 1 << DPIO_CHV_N_DIV_SHIFT
);
7476 /* M2 fraction division */
7478 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7480 /* M2 fraction division enable */
7481 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7482 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7483 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7485 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7486 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7488 /* Program digital lock detect threshold */
7489 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7490 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7491 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7492 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7494 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7495 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7498 if (vco
== 5400000) {
7499 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7500 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7501 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7502 tribuf_calcntr
= 0x9;
7503 } else if (vco
<= 6200000) {
7504 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7505 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7506 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7507 tribuf_calcntr
= 0x9;
7508 } else if (vco
<= 6480000) {
7509 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7510 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7511 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7512 tribuf_calcntr
= 0x8;
7514 /* Not supported. Apply the same limits as in the max case */
7515 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7516 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7517 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7520 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7522 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7523 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7524 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7525 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7528 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7529 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7532 mutex_unlock(&dev_priv
->sb_lock
);
7536 * vlv_force_pll_on - forcibly enable just the PLL
7537 * @dev_priv: i915 private structure
7538 * @pipe: pipe PLL to enable
7539 * @dpll: PLL configuration
7541 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7542 * in cases where we need the PLL enabled even when @pipe is not going to
7545 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7546 const struct dpll
*dpll
)
7548 struct intel_crtc
*crtc
=
7549 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7550 struct intel_crtc_state pipe_config
= {
7551 .base
.crtc
= &crtc
->base
,
7552 .pixel_multiplier
= 1,
7556 if (IS_CHERRYVIEW(dev
)) {
7557 chv_update_pll(crtc
, &pipe_config
);
7558 chv_prepare_pll(crtc
, &pipe_config
);
7559 chv_enable_pll(crtc
, &pipe_config
);
7561 vlv_update_pll(crtc
, &pipe_config
);
7562 vlv_prepare_pll(crtc
, &pipe_config
);
7563 vlv_enable_pll(crtc
, &pipe_config
);
7568 * vlv_force_pll_off - forcibly disable just the PLL
7569 * @dev_priv: i915 private structure
7570 * @pipe: pipe PLL to disable
7572 * Disable the PLL for @pipe. To be used in cases where we need
7573 * the PLL enabled even when @pipe is not going to be enabled.
7575 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7577 if (IS_CHERRYVIEW(dev
))
7578 chv_disable_pll(to_i915(dev
), pipe
);
7580 vlv_disable_pll(to_i915(dev
), pipe
);
7583 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7584 struct intel_crtc_state
*crtc_state
,
7585 intel_clock_t
*reduced_clock
,
7588 struct drm_device
*dev
= crtc
->base
.dev
;
7589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7592 struct dpll
*clock
= &crtc_state
->dpll
;
7594 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7596 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7597 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7599 dpll
= DPLL_VGA_MODE_DIS
;
7601 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7602 dpll
|= DPLLB_MODE_LVDS
;
7604 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7606 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7607 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7608 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7612 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7614 if (crtc_state
->has_dp_encoder
)
7615 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7617 /* compute bitmask from p1 value */
7618 if (IS_PINEVIEW(dev
))
7619 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7621 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7622 if (IS_G4X(dev
) && reduced_clock
)
7623 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7625 switch (clock
->p2
) {
7627 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7630 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7633 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7636 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7639 if (INTEL_INFO(dev
)->gen
>= 4)
7640 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7642 if (crtc_state
->sdvo_tv_clock
)
7643 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7644 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7645 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7646 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7648 dpll
|= PLL_REF_INPUT_DREFCLK
;
7650 dpll
|= DPLL_VCO_ENABLE
;
7651 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7653 if (INTEL_INFO(dev
)->gen
>= 4) {
7654 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7655 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7656 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7660 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7661 struct intel_crtc_state
*crtc_state
,
7662 intel_clock_t
*reduced_clock
,
7665 struct drm_device
*dev
= crtc
->base
.dev
;
7666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7668 struct dpll
*clock
= &crtc_state
->dpll
;
7670 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7672 dpll
= DPLL_VGA_MODE_DIS
;
7674 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7675 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7678 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7680 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7682 dpll
|= PLL_P2_DIVIDE_BY_4
;
7685 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7686 dpll
|= DPLL_DVO_2X_MODE
;
7688 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7689 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7690 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7692 dpll
|= PLL_REF_INPUT_DREFCLK
;
7694 dpll
|= DPLL_VCO_ENABLE
;
7695 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7698 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7700 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7702 enum pipe pipe
= intel_crtc
->pipe
;
7703 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7704 struct drm_display_mode
*adjusted_mode
=
7705 &intel_crtc
->config
->base
.adjusted_mode
;
7706 uint32_t crtc_vtotal
, crtc_vblank_end
;
7709 /* We need to be careful not to changed the adjusted mode, for otherwise
7710 * the hw state checker will get angry at the mismatch. */
7711 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7712 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7714 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7715 /* the chip adds 2 halflines automatically */
7717 crtc_vblank_end
-= 1;
7719 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7720 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7722 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7723 adjusted_mode
->crtc_htotal
/ 2;
7725 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7728 if (INTEL_INFO(dev
)->gen
> 3)
7729 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7731 I915_WRITE(HTOTAL(cpu_transcoder
),
7732 (adjusted_mode
->crtc_hdisplay
- 1) |
7733 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7734 I915_WRITE(HBLANK(cpu_transcoder
),
7735 (adjusted_mode
->crtc_hblank_start
- 1) |
7736 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7737 I915_WRITE(HSYNC(cpu_transcoder
),
7738 (adjusted_mode
->crtc_hsync_start
- 1) |
7739 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7741 I915_WRITE(VTOTAL(cpu_transcoder
),
7742 (adjusted_mode
->crtc_vdisplay
- 1) |
7743 ((crtc_vtotal
- 1) << 16));
7744 I915_WRITE(VBLANK(cpu_transcoder
),
7745 (adjusted_mode
->crtc_vblank_start
- 1) |
7746 ((crtc_vblank_end
- 1) << 16));
7747 I915_WRITE(VSYNC(cpu_transcoder
),
7748 (adjusted_mode
->crtc_vsync_start
- 1) |
7749 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7751 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7752 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7753 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7755 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7756 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7757 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7759 /* pipesrc controls the size that is scaled from, which should
7760 * always be the user's requested size.
7762 I915_WRITE(PIPESRC(pipe
),
7763 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7764 (intel_crtc
->config
->pipe_src_h
- 1));
7767 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7768 struct intel_crtc_state
*pipe_config
)
7770 struct drm_device
*dev
= crtc
->base
.dev
;
7771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7772 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7775 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7776 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7777 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7778 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7779 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7780 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7781 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7782 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7783 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7785 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7786 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7787 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7788 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7789 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7790 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7791 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7792 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7793 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7795 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7796 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7797 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7798 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7801 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7802 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7803 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7805 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7806 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7809 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7810 struct intel_crtc_state
*pipe_config
)
7812 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7813 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7814 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7815 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7817 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7818 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7819 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7820 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7822 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7824 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7825 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7828 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7830 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7836 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7837 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7838 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7840 if (intel_crtc
->config
->double_wide
)
7841 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7843 /* only g4x and later have fancy bpc/dither controls */
7844 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7845 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7846 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7847 pipeconf
|= PIPECONF_DITHER_EN
|
7848 PIPECONF_DITHER_TYPE_SP
;
7850 switch (intel_crtc
->config
->pipe_bpp
) {
7852 pipeconf
|= PIPECONF_6BPC
;
7855 pipeconf
|= PIPECONF_8BPC
;
7858 pipeconf
|= PIPECONF_10BPC
;
7861 /* Case prevented by intel_choose_pipe_bpp_dither. */
7866 if (HAS_PIPE_CXSR(dev
)) {
7867 if (intel_crtc
->lowfreq_avail
) {
7868 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7869 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7871 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7875 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7876 if (INTEL_INFO(dev
)->gen
< 4 ||
7877 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7878 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7880 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7882 pipeconf
|= PIPECONF_PROGRESSIVE
;
7884 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7885 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7887 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7888 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7891 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7892 struct intel_crtc_state
*crtc_state
)
7894 struct drm_device
*dev
= crtc
->base
.dev
;
7895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7896 int refclk
, num_connectors
= 0;
7897 intel_clock_t clock
, reduced_clock
;
7898 bool ok
, has_reduced_clock
= false;
7899 bool is_lvds
= false, is_dsi
= false;
7900 struct intel_encoder
*encoder
;
7901 const intel_limit_t
*limit
;
7902 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7903 struct drm_connector
*connector
;
7904 struct drm_connector_state
*connector_state
;
7907 memset(&crtc_state
->dpll_hw_state
, 0,
7908 sizeof(crtc_state
->dpll_hw_state
));
7910 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7911 if (connector_state
->crtc
!= &crtc
->base
)
7914 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7916 switch (encoder
->type
) {
7917 case INTEL_OUTPUT_LVDS
:
7920 case INTEL_OUTPUT_DSI
:
7933 if (!crtc_state
->clock_set
) {
7934 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7937 * Returns a set of divisors for the desired target clock with
7938 * the given refclk, or FALSE. The returned values represent
7939 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7942 limit
= intel_limit(crtc_state
, refclk
);
7943 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7944 crtc_state
->port_clock
,
7945 refclk
, NULL
, &clock
);
7947 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7951 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7953 * Ensure we match the reduced clock's P to the target
7954 * clock. If the clocks don't match, we can't switch
7955 * the display clock by using the FP0/FP1. In such case
7956 * we will disable the LVDS downclock feature.
7959 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7960 dev_priv
->lvds_downclock
,
7964 /* Compat-code for transition, will disappear. */
7965 crtc_state
->dpll
.n
= clock
.n
;
7966 crtc_state
->dpll
.m1
= clock
.m1
;
7967 crtc_state
->dpll
.m2
= clock
.m2
;
7968 crtc_state
->dpll
.p1
= clock
.p1
;
7969 crtc_state
->dpll
.p2
= clock
.p2
;
7973 i8xx_update_pll(crtc
, crtc_state
,
7974 has_reduced_clock
? &reduced_clock
: NULL
,
7976 } else if (IS_CHERRYVIEW(dev
)) {
7977 chv_update_pll(crtc
, crtc_state
);
7978 } else if (IS_VALLEYVIEW(dev
)) {
7979 vlv_update_pll(crtc
, crtc_state
);
7981 i9xx_update_pll(crtc
, crtc_state
,
7982 has_reduced_clock
? &reduced_clock
: NULL
,
7989 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7990 struct intel_crtc_state
*pipe_config
)
7992 struct drm_device
*dev
= crtc
->base
.dev
;
7993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7996 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7999 tmp
= I915_READ(PFIT_CONTROL
);
8000 if (!(tmp
& PFIT_ENABLE
))
8003 /* Check whether the pfit is attached to our pipe. */
8004 if (INTEL_INFO(dev
)->gen
< 4) {
8005 if (crtc
->pipe
!= PIPE_B
)
8008 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
8012 pipe_config
->gmch_pfit
.control
= tmp
;
8013 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
8014 if (INTEL_INFO(dev
)->gen
< 5)
8015 pipe_config
->gmch_pfit
.lvds_border_bits
=
8016 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
8019 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
8020 struct intel_crtc_state
*pipe_config
)
8022 struct drm_device
*dev
= crtc
->base
.dev
;
8023 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8024 int pipe
= pipe_config
->cpu_transcoder
;
8025 intel_clock_t clock
;
8027 int refclk
= 100000;
8029 /* In case of MIPI DPLL will not even be used */
8030 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
8033 mutex_lock(&dev_priv
->sb_lock
);
8034 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8035 mutex_unlock(&dev_priv
->sb_lock
);
8037 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8038 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8039 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8040 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8041 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8043 vlv_clock(refclk
, &clock
);
8045 /* clock.dot is the fast clock */
8046 pipe_config
->port_clock
= clock
.dot
/ 5;
8050 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8051 struct intel_initial_plane_config
*plane_config
)
8053 struct drm_device
*dev
= crtc
->base
.dev
;
8054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8055 u32 val
, base
, offset
;
8056 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8057 int fourcc
, pixel_format
;
8058 unsigned int aligned_height
;
8059 struct drm_framebuffer
*fb
;
8060 struct intel_framebuffer
*intel_fb
;
8062 val
= I915_READ(DSPCNTR(plane
));
8063 if (!(val
& DISPLAY_PLANE_ENABLE
))
8066 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8068 DRM_DEBUG_KMS("failed to alloc fb\n");
8072 fb
= &intel_fb
->base
;
8074 if (INTEL_INFO(dev
)->gen
>= 4) {
8075 if (val
& DISPPLANE_TILED
) {
8076 plane_config
->tiling
= I915_TILING_X
;
8077 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8081 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8082 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8083 fb
->pixel_format
= fourcc
;
8084 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8086 if (INTEL_INFO(dev
)->gen
>= 4) {
8087 if (plane_config
->tiling
)
8088 offset
= I915_READ(DSPTILEOFF(plane
));
8090 offset
= I915_READ(DSPLINOFF(plane
));
8091 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8093 base
= I915_READ(DSPADDR(plane
));
8095 plane_config
->base
= base
;
8097 val
= I915_READ(PIPESRC(pipe
));
8098 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8099 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8101 val
= I915_READ(DSPSTRIDE(pipe
));
8102 fb
->pitches
[0] = val
& 0xffffffc0;
8104 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8108 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8110 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8111 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8112 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8113 plane_config
->size
);
8115 plane_config
->fb
= intel_fb
;
8118 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8119 struct intel_crtc_state
*pipe_config
)
8121 struct drm_device
*dev
= crtc
->base
.dev
;
8122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8123 int pipe
= pipe_config
->cpu_transcoder
;
8124 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8125 intel_clock_t clock
;
8126 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
8127 int refclk
= 100000;
8129 mutex_lock(&dev_priv
->sb_lock
);
8130 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8131 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8132 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8133 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8134 mutex_unlock(&dev_priv
->sb_lock
);
8136 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8137 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
8138 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8139 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8140 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8142 chv_clock(refclk
, &clock
);
8144 /* clock.dot is the fast clock */
8145 pipe_config
->port_clock
= clock
.dot
/ 5;
8148 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8149 struct intel_crtc_state
*pipe_config
)
8151 struct drm_device
*dev
= crtc
->base
.dev
;
8152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8155 if (!intel_display_power_is_enabled(dev_priv
,
8156 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8159 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8160 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8162 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8163 if (!(tmp
& PIPECONF_ENABLE
))
8166 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
8167 switch (tmp
& PIPECONF_BPC_MASK
) {
8169 pipe_config
->pipe_bpp
= 18;
8172 pipe_config
->pipe_bpp
= 24;
8174 case PIPECONF_10BPC
:
8175 pipe_config
->pipe_bpp
= 30;
8182 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8183 pipe_config
->limited_color_range
= true;
8185 if (INTEL_INFO(dev
)->gen
< 4)
8186 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8188 intel_get_pipe_timings(crtc
, pipe_config
);
8190 i9xx_get_pfit_config(crtc
, pipe_config
);
8192 if (INTEL_INFO(dev
)->gen
>= 4) {
8193 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8194 pipe_config
->pixel_multiplier
=
8195 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8196 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8197 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8198 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8199 tmp
= I915_READ(DPLL(crtc
->pipe
));
8200 pipe_config
->pixel_multiplier
=
8201 ((tmp
& SDVO_MULTIPLIER_MASK
)
8202 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8204 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8205 * port and will be fixed up in the encoder->get_config
8207 pipe_config
->pixel_multiplier
= 1;
8209 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8210 if (!IS_VALLEYVIEW(dev
)) {
8212 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8213 * on 830. Filter it out here so that we don't
8214 * report errors due to that.
8217 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8219 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8220 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8222 /* Mask out read-only status bits. */
8223 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8224 DPLL_PORTC_READY_MASK
|
8225 DPLL_PORTB_READY_MASK
);
8228 if (IS_CHERRYVIEW(dev
))
8229 chv_crtc_clock_get(crtc
, pipe_config
);
8230 else if (IS_VALLEYVIEW(dev
))
8231 vlv_crtc_clock_get(crtc
, pipe_config
);
8233 i9xx_crtc_clock_get(crtc
, pipe_config
);
8238 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8241 struct intel_encoder
*encoder
;
8243 bool has_lvds
= false;
8244 bool has_cpu_edp
= false;
8245 bool has_panel
= false;
8246 bool has_ck505
= false;
8247 bool can_ssc
= false;
8249 /* We need to take the global config into account */
8250 for_each_intel_encoder(dev
, encoder
) {
8251 switch (encoder
->type
) {
8252 case INTEL_OUTPUT_LVDS
:
8256 case INTEL_OUTPUT_EDP
:
8258 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8266 if (HAS_PCH_IBX(dev
)) {
8267 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8268 can_ssc
= has_ck505
;
8274 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8275 has_panel
, has_lvds
, has_ck505
);
8277 /* Ironlake: try to setup display ref clock before DPLL
8278 * enabling. This is only under driver's control after
8279 * PCH B stepping, previous chipset stepping should be
8280 * ignoring this setting.
8282 val
= I915_READ(PCH_DREF_CONTROL
);
8284 /* As we must carefully and slowly disable/enable each source in turn,
8285 * compute the final state we want first and check if we need to
8286 * make any changes at all.
8289 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8291 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8293 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8295 final
&= ~DREF_SSC_SOURCE_MASK
;
8296 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8297 final
&= ~DREF_SSC1_ENABLE
;
8300 final
|= DREF_SSC_SOURCE_ENABLE
;
8302 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8303 final
|= DREF_SSC1_ENABLE
;
8306 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8307 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8309 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8311 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8313 final
|= DREF_SSC_SOURCE_DISABLE
;
8314 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8320 /* Always enable nonspread source */
8321 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8324 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8326 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8329 val
&= ~DREF_SSC_SOURCE_MASK
;
8330 val
|= DREF_SSC_SOURCE_ENABLE
;
8332 /* SSC must be turned on before enabling the CPU output */
8333 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8334 DRM_DEBUG_KMS("Using SSC on panel\n");
8335 val
|= DREF_SSC1_ENABLE
;
8337 val
&= ~DREF_SSC1_ENABLE
;
8339 /* Get SSC going before enabling the outputs */
8340 I915_WRITE(PCH_DREF_CONTROL
, val
);
8341 POSTING_READ(PCH_DREF_CONTROL
);
8344 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8346 /* Enable CPU source on CPU attached eDP */
8348 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8349 DRM_DEBUG_KMS("Using SSC on eDP\n");
8350 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8352 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8354 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8356 I915_WRITE(PCH_DREF_CONTROL
, val
);
8357 POSTING_READ(PCH_DREF_CONTROL
);
8360 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8362 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8364 /* Turn off CPU output */
8365 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8367 I915_WRITE(PCH_DREF_CONTROL
, val
);
8368 POSTING_READ(PCH_DREF_CONTROL
);
8371 /* Turn off the SSC source */
8372 val
&= ~DREF_SSC_SOURCE_MASK
;
8373 val
|= DREF_SSC_SOURCE_DISABLE
;
8376 val
&= ~DREF_SSC1_ENABLE
;
8378 I915_WRITE(PCH_DREF_CONTROL
, val
);
8379 POSTING_READ(PCH_DREF_CONTROL
);
8383 BUG_ON(val
!= final
);
8386 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8390 tmp
= I915_READ(SOUTH_CHICKEN2
);
8391 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8392 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8394 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8395 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8396 DRM_ERROR("FDI mPHY reset assert timeout\n");
8398 tmp
= I915_READ(SOUTH_CHICKEN2
);
8399 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8400 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8402 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8403 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8404 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8407 /* WaMPhyProgramming:hsw */
8408 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8412 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8413 tmp
&= ~(0xFF << 24);
8414 tmp
|= (0x12 << 24);
8415 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8417 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8419 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8421 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8423 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8425 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8426 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8427 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8429 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8430 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8431 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8433 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8436 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8438 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8441 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8443 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8446 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8448 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8451 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8453 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8454 tmp
&= ~(0xFF << 16);
8455 tmp
|= (0x1C << 16);
8456 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8458 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8459 tmp
&= ~(0xFF << 16);
8460 tmp
|= (0x1C << 16);
8461 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8463 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8465 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8467 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8469 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8471 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8472 tmp
&= ~(0xF << 28);
8474 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8476 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8477 tmp
&= ~(0xF << 28);
8479 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8482 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8483 * Programming" based on the parameters passed:
8484 * - Sequence to enable CLKOUT_DP
8485 * - Sequence to enable CLKOUT_DP without spread
8486 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8488 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8494 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8496 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8497 with_fdi
, "LP PCH doesn't have FDI\n"))
8500 mutex_lock(&dev_priv
->sb_lock
);
8502 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8503 tmp
&= ~SBI_SSCCTL_DISABLE
;
8504 tmp
|= SBI_SSCCTL_PATHALT
;
8505 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8510 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8511 tmp
&= ~SBI_SSCCTL_PATHALT
;
8512 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8515 lpt_reset_fdi_mphy(dev_priv
);
8516 lpt_program_fdi_mphy(dev_priv
);
8520 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8521 SBI_GEN0
: SBI_DBUFF0
;
8522 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8523 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8524 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8526 mutex_unlock(&dev_priv
->sb_lock
);
8529 /* Sequence to disable CLKOUT_DP */
8530 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8535 mutex_lock(&dev_priv
->sb_lock
);
8537 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8538 SBI_GEN0
: SBI_DBUFF0
;
8539 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8540 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8541 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8543 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8544 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8545 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8546 tmp
|= SBI_SSCCTL_PATHALT
;
8547 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8550 tmp
|= SBI_SSCCTL_DISABLE
;
8551 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8554 mutex_unlock(&dev_priv
->sb_lock
);
8557 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8559 struct intel_encoder
*encoder
;
8560 bool has_vga
= false;
8562 for_each_intel_encoder(dev
, encoder
) {
8563 switch (encoder
->type
) {
8564 case INTEL_OUTPUT_ANALOG
:
8573 lpt_enable_clkout_dp(dev
, true, true);
8575 lpt_disable_clkout_dp(dev
);
8579 * Initialize reference clocks when the driver loads
8581 void intel_init_pch_refclk(struct drm_device
*dev
)
8583 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8584 ironlake_init_pch_refclk(dev
);
8585 else if (HAS_PCH_LPT(dev
))
8586 lpt_init_pch_refclk(dev
);
8589 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8591 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8593 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8594 struct drm_connector
*connector
;
8595 struct drm_connector_state
*connector_state
;
8596 struct intel_encoder
*encoder
;
8597 int num_connectors
= 0, i
;
8598 bool is_lvds
= false;
8600 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8601 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8604 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8606 switch (encoder
->type
) {
8607 case INTEL_OUTPUT_LVDS
:
8616 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8617 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8618 dev_priv
->vbt
.lvds_ssc_freq
);
8619 return dev_priv
->vbt
.lvds_ssc_freq
;
8625 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8627 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8629 int pipe
= intel_crtc
->pipe
;
8634 switch (intel_crtc
->config
->pipe_bpp
) {
8636 val
|= PIPECONF_6BPC
;
8639 val
|= PIPECONF_8BPC
;
8642 val
|= PIPECONF_10BPC
;
8645 val
|= PIPECONF_12BPC
;
8648 /* Case prevented by intel_choose_pipe_bpp_dither. */
8652 if (intel_crtc
->config
->dither
)
8653 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8655 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8656 val
|= PIPECONF_INTERLACED_ILK
;
8658 val
|= PIPECONF_PROGRESSIVE
;
8660 if (intel_crtc
->config
->limited_color_range
)
8661 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8663 I915_WRITE(PIPECONF(pipe
), val
);
8664 POSTING_READ(PIPECONF(pipe
));
8668 * Set up the pipe CSC unit.
8670 * Currently only full range RGB to limited range RGB conversion
8671 * is supported, but eventually this should handle various
8672 * RGB<->YCbCr scenarios as well.
8674 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8676 struct drm_device
*dev
= crtc
->dev
;
8677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8678 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8679 int pipe
= intel_crtc
->pipe
;
8680 uint16_t coeff
= 0x7800; /* 1.0 */
8683 * TODO: Check what kind of values actually come out of the pipe
8684 * with these coeff/postoff values and adjust to get the best
8685 * accuracy. Perhaps we even need to take the bpc value into
8689 if (intel_crtc
->config
->limited_color_range
)
8690 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8693 * GY/GU and RY/RU should be the other way around according
8694 * to BSpec, but reality doesn't agree. Just set them up in
8695 * a way that results in the correct picture.
8697 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8698 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8700 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8701 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8703 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8704 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8706 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8707 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8708 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8710 if (INTEL_INFO(dev
)->gen
> 6) {
8711 uint16_t postoff
= 0;
8713 if (intel_crtc
->config
->limited_color_range
)
8714 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8716 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8717 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8718 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8720 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8722 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8724 if (intel_crtc
->config
->limited_color_range
)
8725 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8727 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8731 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8733 struct drm_device
*dev
= crtc
->dev
;
8734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8736 enum pipe pipe
= intel_crtc
->pipe
;
8737 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8742 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8743 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8745 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8746 val
|= PIPECONF_INTERLACED_ILK
;
8748 val
|= PIPECONF_PROGRESSIVE
;
8750 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8751 POSTING_READ(PIPECONF(cpu_transcoder
));
8753 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8754 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8756 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8759 switch (intel_crtc
->config
->pipe_bpp
) {
8761 val
|= PIPEMISC_DITHER_6_BPC
;
8764 val
|= PIPEMISC_DITHER_8_BPC
;
8767 val
|= PIPEMISC_DITHER_10_BPC
;
8770 val
|= PIPEMISC_DITHER_12_BPC
;
8773 /* Case prevented by pipe_config_set_bpp. */
8777 if (intel_crtc
->config
->dither
)
8778 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8780 I915_WRITE(PIPEMISC(pipe
), val
);
8784 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8785 struct intel_crtc_state
*crtc_state
,
8786 intel_clock_t
*clock
,
8787 bool *has_reduced_clock
,
8788 intel_clock_t
*reduced_clock
)
8790 struct drm_device
*dev
= crtc
->dev
;
8791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8793 const intel_limit_t
*limit
;
8794 bool ret
, is_lvds
= false;
8796 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8798 refclk
= ironlake_get_refclk(crtc_state
);
8801 * Returns a set of divisors for the desired target clock with the given
8802 * refclk, or FALSE. The returned values represent the clock equation:
8803 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8805 limit
= intel_limit(crtc_state
, refclk
);
8806 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8807 crtc_state
->port_clock
,
8808 refclk
, NULL
, clock
);
8812 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8814 * Ensure we match the reduced clock's P to the target clock.
8815 * If the clocks don't match, we can't switch the display clock
8816 * by using the FP0/FP1. In such case we will disable the LVDS
8817 * downclock feature.
8819 *has_reduced_clock
=
8820 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8821 dev_priv
->lvds_downclock
,
8829 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8832 * Account for spread spectrum to avoid
8833 * oversubscribing the link. Max center spread
8834 * is 2.5%; use 5% for safety's sake.
8836 u32 bps
= target_clock
* bpp
* 21 / 20;
8837 return DIV_ROUND_UP(bps
, link_bw
* 8);
8840 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8842 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8845 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8846 struct intel_crtc_state
*crtc_state
,
8848 intel_clock_t
*reduced_clock
, u32
*fp2
)
8850 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8851 struct drm_device
*dev
= crtc
->dev
;
8852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8853 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8854 struct drm_connector
*connector
;
8855 struct drm_connector_state
*connector_state
;
8856 struct intel_encoder
*encoder
;
8858 int factor
, num_connectors
= 0, i
;
8859 bool is_lvds
= false, is_sdvo
= false;
8861 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8862 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8865 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8867 switch (encoder
->type
) {
8868 case INTEL_OUTPUT_LVDS
:
8871 case INTEL_OUTPUT_SDVO
:
8872 case INTEL_OUTPUT_HDMI
:
8882 /* Enable autotuning of the PLL clock (if permissible) */
8885 if ((intel_panel_use_ssc(dev_priv
) &&
8886 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8887 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8889 } else if (crtc_state
->sdvo_tv_clock
)
8892 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8895 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8901 dpll
|= DPLLB_MODE_LVDS
;
8903 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8905 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8906 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8909 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8910 if (crtc_state
->has_dp_encoder
)
8911 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8913 /* compute bitmask from p1 value */
8914 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8916 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8918 switch (crtc_state
->dpll
.p2
) {
8920 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8923 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8926 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8929 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8933 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8934 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8936 dpll
|= PLL_REF_INPUT_DREFCLK
;
8938 return dpll
| DPLL_VCO_ENABLE
;
8941 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8942 struct intel_crtc_state
*crtc_state
)
8944 struct drm_device
*dev
= crtc
->base
.dev
;
8945 intel_clock_t clock
, reduced_clock
;
8946 u32 dpll
= 0, fp
= 0, fp2
= 0;
8947 bool ok
, has_reduced_clock
= false;
8948 bool is_lvds
= false;
8949 struct intel_shared_dpll
*pll
;
8951 memset(&crtc_state
->dpll_hw_state
, 0,
8952 sizeof(crtc_state
->dpll_hw_state
));
8954 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8956 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8957 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8959 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8960 &has_reduced_clock
, &reduced_clock
);
8961 if (!ok
&& !crtc_state
->clock_set
) {
8962 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8965 /* Compat-code for transition, will disappear. */
8966 if (!crtc_state
->clock_set
) {
8967 crtc_state
->dpll
.n
= clock
.n
;
8968 crtc_state
->dpll
.m1
= clock
.m1
;
8969 crtc_state
->dpll
.m2
= clock
.m2
;
8970 crtc_state
->dpll
.p1
= clock
.p1
;
8971 crtc_state
->dpll
.p2
= clock
.p2
;
8974 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8975 if (crtc_state
->has_pch_encoder
) {
8976 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8977 if (has_reduced_clock
)
8978 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8980 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8981 &fp
, &reduced_clock
,
8982 has_reduced_clock
? &fp2
: NULL
);
8984 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8985 crtc_state
->dpll_hw_state
.fp0
= fp
;
8986 if (has_reduced_clock
)
8987 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8989 crtc_state
->dpll_hw_state
.fp1
= fp
;
8991 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8993 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8994 pipe_name(crtc
->pipe
));
8999 if (is_lvds
&& has_reduced_clock
)
9000 crtc
->lowfreq_avail
= true;
9002 crtc
->lowfreq_avail
= false;
9007 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
9008 struct intel_link_m_n
*m_n
)
9010 struct drm_device
*dev
= crtc
->base
.dev
;
9011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9012 enum pipe pipe
= crtc
->pipe
;
9014 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
9015 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
9016 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
9018 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
9019 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
9020 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9023 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
9024 enum transcoder transcoder
,
9025 struct intel_link_m_n
*m_n
,
9026 struct intel_link_m_n
*m2_n2
)
9028 struct drm_device
*dev
= crtc
->base
.dev
;
9029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9030 enum pipe pipe
= crtc
->pipe
;
9032 if (INTEL_INFO(dev
)->gen
>= 5) {
9033 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
9034 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
9035 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
9037 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
9038 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
9039 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9040 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9041 * gen < 8) and if DRRS is supported (to make sure the
9042 * registers are not unnecessarily read).
9044 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9045 crtc
->config
->has_drrs
) {
9046 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9047 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9048 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9050 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9051 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9052 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9055 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9056 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9057 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9059 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9060 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9061 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9065 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9066 struct intel_crtc_state
*pipe_config
)
9068 if (pipe_config
->has_pch_encoder
)
9069 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9071 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9072 &pipe_config
->dp_m_n
,
9073 &pipe_config
->dp_m2_n2
);
9076 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9077 struct intel_crtc_state
*pipe_config
)
9079 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9080 &pipe_config
->fdi_m_n
, NULL
);
9083 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9084 struct intel_crtc_state
*pipe_config
)
9086 struct drm_device
*dev
= crtc
->base
.dev
;
9087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9088 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9089 uint32_t ps_ctrl
= 0;
9093 /* find scaler attached to this pipe */
9094 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9095 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9096 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9098 pipe_config
->pch_pfit
.enabled
= true;
9099 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9100 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9105 scaler_state
->scaler_id
= id
;
9107 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9109 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9114 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9115 struct intel_initial_plane_config
*plane_config
)
9117 struct drm_device
*dev
= crtc
->base
.dev
;
9118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9119 u32 val
, base
, offset
, stride_mult
, tiling
;
9120 int pipe
= crtc
->pipe
;
9121 int fourcc
, pixel_format
;
9122 unsigned int aligned_height
;
9123 struct drm_framebuffer
*fb
;
9124 struct intel_framebuffer
*intel_fb
;
9126 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9128 DRM_DEBUG_KMS("failed to alloc fb\n");
9132 fb
= &intel_fb
->base
;
9134 val
= I915_READ(PLANE_CTL(pipe
, 0));
9135 if (!(val
& PLANE_CTL_ENABLE
))
9138 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9139 fourcc
= skl_format_to_fourcc(pixel_format
,
9140 val
& PLANE_CTL_ORDER_RGBX
,
9141 val
& PLANE_CTL_ALPHA_MASK
);
9142 fb
->pixel_format
= fourcc
;
9143 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9145 tiling
= val
& PLANE_CTL_TILED_MASK
;
9147 case PLANE_CTL_TILED_LINEAR
:
9148 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9150 case PLANE_CTL_TILED_X
:
9151 plane_config
->tiling
= I915_TILING_X
;
9152 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9154 case PLANE_CTL_TILED_Y
:
9155 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9157 case PLANE_CTL_TILED_YF
:
9158 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9161 MISSING_CASE(tiling
);
9165 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9166 plane_config
->base
= base
;
9168 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9170 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9171 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9172 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9174 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9175 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
9177 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9179 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9183 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9185 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9186 pipe_name(pipe
), fb
->width
, fb
->height
,
9187 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9188 plane_config
->size
);
9190 plane_config
->fb
= intel_fb
;
9197 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9198 struct intel_crtc_state
*pipe_config
)
9200 struct drm_device
*dev
= crtc
->base
.dev
;
9201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9204 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9206 if (tmp
& PF_ENABLE
) {
9207 pipe_config
->pch_pfit
.enabled
= true;
9208 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9209 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9211 /* We currently do not free assignements of panel fitters on
9212 * ivb/hsw (since we don't use the higher upscaling modes which
9213 * differentiates them) so just WARN about this case for now. */
9215 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9216 PF_PIPE_SEL_IVB(crtc
->pipe
));
9222 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9223 struct intel_initial_plane_config
*plane_config
)
9225 struct drm_device
*dev
= crtc
->base
.dev
;
9226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9227 u32 val
, base
, offset
;
9228 int pipe
= crtc
->pipe
;
9229 int fourcc
, pixel_format
;
9230 unsigned int aligned_height
;
9231 struct drm_framebuffer
*fb
;
9232 struct intel_framebuffer
*intel_fb
;
9234 val
= I915_READ(DSPCNTR(pipe
));
9235 if (!(val
& DISPLAY_PLANE_ENABLE
))
9238 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9240 DRM_DEBUG_KMS("failed to alloc fb\n");
9244 fb
= &intel_fb
->base
;
9246 if (INTEL_INFO(dev
)->gen
>= 4) {
9247 if (val
& DISPPLANE_TILED
) {
9248 plane_config
->tiling
= I915_TILING_X
;
9249 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9253 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9254 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9255 fb
->pixel_format
= fourcc
;
9256 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9258 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9259 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9260 offset
= I915_READ(DSPOFFSET(pipe
));
9262 if (plane_config
->tiling
)
9263 offset
= I915_READ(DSPTILEOFF(pipe
));
9265 offset
= I915_READ(DSPLINOFF(pipe
));
9267 plane_config
->base
= base
;
9269 val
= I915_READ(PIPESRC(pipe
));
9270 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9271 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9273 val
= I915_READ(DSPSTRIDE(pipe
));
9274 fb
->pitches
[0] = val
& 0xffffffc0;
9276 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9280 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9282 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9283 pipe_name(pipe
), fb
->width
, fb
->height
,
9284 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9285 plane_config
->size
);
9287 plane_config
->fb
= intel_fb
;
9290 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9291 struct intel_crtc_state
*pipe_config
)
9293 struct drm_device
*dev
= crtc
->base
.dev
;
9294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9297 if (!intel_display_power_is_enabled(dev_priv
,
9298 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9301 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9302 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9304 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9305 if (!(tmp
& PIPECONF_ENABLE
))
9308 switch (tmp
& PIPECONF_BPC_MASK
) {
9310 pipe_config
->pipe_bpp
= 18;
9313 pipe_config
->pipe_bpp
= 24;
9315 case PIPECONF_10BPC
:
9316 pipe_config
->pipe_bpp
= 30;
9318 case PIPECONF_12BPC
:
9319 pipe_config
->pipe_bpp
= 36;
9325 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9326 pipe_config
->limited_color_range
= true;
9328 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9329 struct intel_shared_dpll
*pll
;
9331 pipe_config
->has_pch_encoder
= true;
9333 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9334 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9335 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9337 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9339 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9340 pipe_config
->shared_dpll
=
9341 (enum intel_dpll_id
) crtc
->pipe
;
9343 tmp
= I915_READ(PCH_DPLL_SEL
);
9344 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9345 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9347 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9350 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9352 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9353 &pipe_config
->dpll_hw_state
));
9355 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9356 pipe_config
->pixel_multiplier
=
9357 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9358 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9360 ironlake_pch_clock_get(crtc
, pipe_config
);
9362 pipe_config
->pixel_multiplier
= 1;
9365 intel_get_pipe_timings(crtc
, pipe_config
);
9367 ironlake_get_pfit_config(crtc
, pipe_config
);
9372 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9374 struct drm_device
*dev
= dev_priv
->dev
;
9375 struct intel_crtc
*crtc
;
9377 for_each_intel_crtc(dev
, crtc
)
9378 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9379 pipe_name(crtc
->pipe
));
9381 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9382 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9383 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9384 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9385 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9386 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9387 "CPU PWM1 enabled\n");
9388 if (IS_HASWELL(dev
))
9389 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9390 "CPU PWM2 enabled\n");
9391 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9392 "PCH PWM1 enabled\n");
9393 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9394 "Utility pin enabled\n");
9395 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9398 * In theory we can still leave IRQs enabled, as long as only the HPD
9399 * interrupts remain enabled. We used to check for that, but since it's
9400 * gen-specific and since we only disable LCPLL after we fully disable
9401 * the interrupts, the check below should be enough.
9403 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9406 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9408 struct drm_device
*dev
= dev_priv
->dev
;
9410 if (IS_HASWELL(dev
))
9411 return I915_READ(D_COMP_HSW
);
9413 return I915_READ(D_COMP_BDW
);
9416 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9418 struct drm_device
*dev
= dev_priv
->dev
;
9420 if (IS_HASWELL(dev
)) {
9421 mutex_lock(&dev_priv
->rps
.hw_lock
);
9422 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9424 DRM_ERROR("Failed to write to D_COMP\n");
9425 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9427 I915_WRITE(D_COMP_BDW
, val
);
9428 POSTING_READ(D_COMP_BDW
);
9433 * This function implements pieces of two sequences from BSpec:
9434 * - Sequence for display software to disable LCPLL
9435 * - Sequence for display software to allow package C8+
9436 * The steps implemented here are just the steps that actually touch the LCPLL
9437 * register. Callers should take care of disabling all the display engine
9438 * functions, doing the mode unset, fixing interrupts, etc.
9440 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9441 bool switch_to_fclk
, bool allow_power_down
)
9445 assert_can_disable_lcpll(dev_priv
);
9447 val
= I915_READ(LCPLL_CTL
);
9449 if (switch_to_fclk
) {
9450 val
|= LCPLL_CD_SOURCE_FCLK
;
9451 I915_WRITE(LCPLL_CTL
, val
);
9453 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9454 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9455 DRM_ERROR("Switching to FCLK failed\n");
9457 val
= I915_READ(LCPLL_CTL
);
9460 val
|= LCPLL_PLL_DISABLE
;
9461 I915_WRITE(LCPLL_CTL
, val
);
9462 POSTING_READ(LCPLL_CTL
);
9464 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9465 DRM_ERROR("LCPLL still locked\n");
9467 val
= hsw_read_dcomp(dev_priv
);
9468 val
|= D_COMP_COMP_DISABLE
;
9469 hsw_write_dcomp(dev_priv
, val
);
9472 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9474 DRM_ERROR("D_COMP RCOMP still in progress\n");
9476 if (allow_power_down
) {
9477 val
= I915_READ(LCPLL_CTL
);
9478 val
|= LCPLL_POWER_DOWN_ALLOW
;
9479 I915_WRITE(LCPLL_CTL
, val
);
9480 POSTING_READ(LCPLL_CTL
);
9485 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9488 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9492 val
= I915_READ(LCPLL_CTL
);
9494 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9495 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9499 * Make sure we're not on PC8 state before disabling PC8, otherwise
9500 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9502 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9504 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9505 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9506 I915_WRITE(LCPLL_CTL
, val
);
9507 POSTING_READ(LCPLL_CTL
);
9510 val
= hsw_read_dcomp(dev_priv
);
9511 val
|= D_COMP_COMP_FORCE
;
9512 val
&= ~D_COMP_COMP_DISABLE
;
9513 hsw_write_dcomp(dev_priv
, val
);
9515 val
= I915_READ(LCPLL_CTL
);
9516 val
&= ~LCPLL_PLL_DISABLE
;
9517 I915_WRITE(LCPLL_CTL
, val
);
9519 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9520 DRM_ERROR("LCPLL not locked yet\n");
9522 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9523 val
= I915_READ(LCPLL_CTL
);
9524 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9525 I915_WRITE(LCPLL_CTL
, val
);
9527 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9528 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9529 DRM_ERROR("Switching back to LCPLL failed\n");
9532 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9533 intel_update_cdclk(dev_priv
->dev
);
9537 * Package states C8 and deeper are really deep PC states that can only be
9538 * reached when all the devices on the system allow it, so even if the graphics
9539 * device allows PC8+, it doesn't mean the system will actually get to these
9540 * states. Our driver only allows PC8+ when going into runtime PM.
9542 * The requirements for PC8+ are that all the outputs are disabled, the power
9543 * well is disabled and most interrupts are disabled, and these are also
9544 * requirements for runtime PM. When these conditions are met, we manually do
9545 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9546 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9549 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9550 * the state of some registers, so when we come back from PC8+ we need to
9551 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9552 * need to take care of the registers kept by RC6. Notice that this happens even
9553 * if we don't put the device in PCI D3 state (which is what currently happens
9554 * because of the runtime PM support).
9556 * For more, read "Display Sequences for Package C8" on the hardware
9559 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9561 struct drm_device
*dev
= dev_priv
->dev
;
9564 DRM_DEBUG_KMS("Enabling package C8+\n");
9566 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9567 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9568 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9569 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9572 lpt_disable_clkout_dp(dev
);
9573 hsw_disable_lcpll(dev_priv
, true, true);
9576 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9578 struct drm_device
*dev
= dev_priv
->dev
;
9581 DRM_DEBUG_KMS("Disabling package C8+\n");
9583 hsw_restore_lcpll(dev_priv
);
9584 lpt_init_pch_refclk(dev
);
9586 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9587 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9588 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9589 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9592 intel_prepare_ddi(dev
);
9595 static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state
)
9597 struct drm_device
*dev
= old_state
->dev
;
9598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9599 int max_pixclk
= intel_mode_max_pixclk(dev
, NULL
);
9602 /* see the comment in valleyview_modeset_global_resources */
9603 if (WARN_ON(max_pixclk
< 0))
9606 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9608 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9609 broxton_set_cdclk(dev
, req_cdclk
);
9612 /* compute the max rate for new configuration */
9613 static int ilk_max_pixel_rate(struct drm_i915_private
*dev_priv
)
9615 struct drm_device
*dev
= dev_priv
->dev
;
9616 struct intel_crtc
*intel_crtc
;
9617 struct drm_crtc
*crtc
;
9618 int max_pixel_rate
= 0;
9621 for_each_crtc(dev
, crtc
) {
9622 if (!crtc
->state
->enable
)
9625 intel_crtc
= to_intel_crtc(crtc
);
9626 pixel_rate
= ilk_pipe_pixel_rate(intel_crtc
->config
);
9628 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9629 if (IS_BROADWELL(dev
) && intel_crtc
->config
->ips_enabled
)
9630 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9632 max_pixel_rate
= max(max_pixel_rate
, pixel_rate
);
9635 return max_pixel_rate
;
9638 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9644 if (WARN((I915_READ(LCPLL_CTL
) &
9645 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9646 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9647 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9648 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9649 "trying to change cdclk frequency with cdclk not enabled\n"))
9652 mutex_lock(&dev_priv
->rps
.hw_lock
);
9653 ret
= sandybridge_pcode_write(dev_priv
,
9654 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9655 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9657 DRM_ERROR("failed to inform pcode about cdclk change\n");
9661 val
= I915_READ(LCPLL_CTL
);
9662 val
|= LCPLL_CD_SOURCE_FCLK
;
9663 I915_WRITE(LCPLL_CTL
, val
);
9665 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9666 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9667 DRM_ERROR("Switching to FCLK failed\n");
9669 val
= I915_READ(LCPLL_CTL
);
9670 val
&= ~LCPLL_CLK_FREQ_MASK
;
9674 val
|= LCPLL_CLK_FREQ_450
;
9678 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9682 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9686 val
|= LCPLL_CLK_FREQ_675_BDW
;
9690 WARN(1, "invalid cdclk frequency\n");
9694 I915_WRITE(LCPLL_CTL
, val
);
9696 val
= I915_READ(LCPLL_CTL
);
9697 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9698 I915_WRITE(LCPLL_CTL
, val
);
9700 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9701 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9702 DRM_ERROR("Switching back to LCPLL failed\n");
9704 mutex_lock(&dev_priv
->rps
.hw_lock
);
9705 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9706 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9708 intel_update_cdclk(dev
);
9710 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9711 "cdclk requested %d kHz but got %d kHz\n",
9712 cdclk
, dev_priv
->cdclk_freq
);
9715 static int broadwell_calc_cdclk(struct drm_i915_private
*dev_priv
,
9721 * FIXME should also account for plane ratio
9722 * once 64bpp pixel formats are supported.
9724 if (max_pixel_rate
> 540000)
9726 else if (max_pixel_rate
> 450000)
9728 else if (max_pixel_rate
> 337500)
9734 * FIXME move the cdclk caclulation to
9735 * compute_config() so we can fail gracegully.
9737 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9738 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9739 cdclk
, dev_priv
->max_cdclk_freq
);
9740 cdclk
= dev_priv
->max_cdclk_freq
;
9746 static int broadwell_modeset_global_pipes(struct drm_atomic_state
*state
)
9748 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9749 struct drm_crtc
*crtc
;
9750 struct drm_crtc_state
*crtc_state
;
9751 int max_pixclk
= ilk_max_pixel_rate(dev_priv
);
9754 cdclk
= broadwell_calc_cdclk(dev_priv
, max_pixclk
);
9756 if (cdclk
== dev_priv
->cdclk_freq
)
9759 /* add all active pipes to the state */
9760 for_each_crtc(state
->dev
, crtc
) {
9761 if (!crtc
->state
->enable
)
9764 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
9765 if (IS_ERR(crtc_state
))
9766 return PTR_ERR(crtc_state
);
9769 /* disable/enable all currently active pipes while we change cdclk */
9770 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
9771 if (crtc_state
->enable
)
9772 crtc_state
->mode_changed
= true;
9777 static void broadwell_modeset_global_resources(struct drm_atomic_state
*state
)
9779 struct drm_device
*dev
= state
->dev
;
9780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9781 int max_pixel_rate
= ilk_max_pixel_rate(dev_priv
);
9782 int req_cdclk
= broadwell_calc_cdclk(dev_priv
, max_pixel_rate
);
9784 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9785 broadwell_set_cdclk(dev
, req_cdclk
);
9788 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9789 struct intel_crtc_state
*crtc_state
)
9791 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9794 crtc
->lowfreq_avail
= false;
9799 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9801 struct intel_crtc_state
*pipe_config
)
9805 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9806 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9809 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9810 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9813 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9814 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9817 DRM_ERROR("Incorrect port type\n");
9821 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9823 struct intel_crtc_state
*pipe_config
)
9825 u32 temp
, dpll_ctl1
;
9827 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9828 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9830 switch (pipe_config
->ddi_pll_sel
) {
9833 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9834 * of the shared DPLL framework and thus needs to be read out
9837 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9838 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9841 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9844 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9847 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9852 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9854 struct intel_crtc_state
*pipe_config
)
9856 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9858 switch (pipe_config
->ddi_pll_sel
) {
9859 case PORT_CLK_SEL_WRPLL1
:
9860 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9862 case PORT_CLK_SEL_WRPLL2
:
9863 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9868 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9869 struct intel_crtc_state
*pipe_config
)
9871 struct drm_device
*dev
= crtc
->base
.dev
;
9872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9873 struct intel_shared_dpll
*pll
;
9877 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9879 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9881 if (IS_SKYLAKE(dev
))
9882 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9883 else if (IS_BROXTON(dev
))
9884 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9886 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9888 if (pipe_config
->shared_dpll
>= 0) {
9889 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9891 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9892 &pipe_config
->dpll_hw_state
));
9896 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9897 * DDI E. So just check whether this pipe is wired to DDI E and whether
9898 * the PCH transcoder is on.
9900 if (INTEL_INFO(dev
)->gen
< 9 &&
9901 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9902 pipe_config
->has_pch_encoder
= true;
9904 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9905 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9906 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9908 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9912 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9913 struct intel_crtc_state
*pipe_config
)
9915 struct drm_device
*dev
= crtc
->base
.dev
;
9916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9917 enum intel_display_power_domain pfit_domain
;
9920 if (!intel_display_power_is_enabled(dev_priv
,
9921 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9924 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9925 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9927 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9928 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9929 enum pipe trans_edp_pipe
;
9930 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9932 WARN(1, "unknown pipe linked to edp transcoder\n");
9933 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9934 case TRANS_DDI_EDP_INPUT_A_ON
:
9935 trans_edp_pipe
= PIPE_A
;
9937 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9938 trans_edp_pipe
= PIPE_B
;
9940 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9941 trans_edp_pipe
= PIPE_C
;
9945 if (trans_edp_pipe
== crtc
->pipe
)
9946 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9949 if (!intel_display_power_is_enabled(dev_priv
,
9950 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9953 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9954 if (!(tmp
& PIPECONF_ENABLE
))
9957 haswell_get_ddi_port_state(crtc
, pipe_config
);
9959 intel_get_pipe_timings(crtc
, pipe_config
);
9961 if (INTEL_INFO(dev
)->gen
>= 9) {
9962 skl_init_scalers(dev
, crtc
, pipe_config
);
9965 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9967 if (INTEL_INFO(dev
)->gen
>= 9) {
9968 pipe_config
->scaler_state
.scaler_id
= -1;
9969 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9972 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9973 if (INTEL_INFO(dev
)->gen
== 9)
9974 skylake_get_pfit_config(crtc
, pipe_config
);
9975 else if (INTEL_INFO(dev
)->gen
< 9)
9976 ironlake_get_pfit_config(crtc
, pipe_config
);
9978 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9981 if (IS_HASWELL(dev
))
9982 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9983 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9985 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9986 pipe_config
->pixel_multiplier
=
9987 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9989 pipe_config
->pixel_multiplier
= 1;
9995 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9997 struct drm_device
*dev
= crtc
->dev
;
9998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9999 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10000 uint32_t cntl
= 0, size
= 0;
10003 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
10004 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
10005 unsigned int stride
= roundup_pow_of_two(width
) * 4;
10009 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10020 cntl
|= CURSOR_ENABLE
|
10021 CURSOR_GAMMA_ENABLE
|
10022 CURSOR_FORMAT_ARGB
|
10023 CURSOR_STRIDE(stride
);
10025 size
= (height
<< 12) | width
;
10028 if (intel_crtc
->cursor_cntl
!= 0 &&
10029 (intel_crtc
->cursor_base
!= base
||
10030 intel_crtc
->cursor_size
!= size
||
10031 intel_crtc
->cursor_cntl
!= cntl
)) {
10032 /* On these chipsets we can only modify the base/size/stride
10033 * whilst the cursor is disabled.
10035 I915_WRITE(_CURACNTR
, 0);
10036 POSTING_READ(_CURACNTR
);
10037 intel_crtc
->cursor_cntl
= 0;
10040 if (intel_crtc
->cursor_base
!= base
) {
10041 I915_WRITE(_CURABASE
, base
);
10042 intel_crtc
->cursor_base
= base
;
10045 if (intel_crtc
->cursor_size
!= size
) {
10046 I915_WRITE(CURSIZE
, size
);
10047 intel_crtc
->cursor_size
= size
;
10050 if (intel_crtc
->cursor_cntl
!= cntl
) {
10051 I915_WRITE(_CURACNTR
, cntl
);
10052 POSTING_READ(_CURACNTR
);
10053 intel_crtc
->cursor_cntl
= cntl
;
10057 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
10059 struct drm_device
*dev
= crtc
->dev
;
10060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10062 int pipe
= intel_crtc
->pipe
;
10067 cntl
= MCURSOR_GAMMA_ENABLE
;
10068 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
10070 cntl
|= CURSOR_MODE_64_ARGB_AX
;
10073 cntl
|= CURSOR_MODE_128_ARGB_AX
;
10076 cntl
|= CURSOR_MODE_256_ARGB_AX
;
10079 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
10082 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10084 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
10085 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10088 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
10089 cntl
|= CURSOR_ROTATE_180
;
10091 if (intel_crtc
->cursor_cntl
!= cntl
) {
10092 I915_WRITE(CURCNTR(pipe
), cntl
);
10093 POSTING_READ(CURCNTR(pipe
));
10094 intel_crtc
->cursor_cntl
= cntl
;
10097 /* and commit changes on next vblank */
10098 I915_WRITE(CURBASE(pipe
), base
);
10099 POSTING_READ(CURBASE(pipe
));
10101 intel_crtc
->cursor_base
= base
;
10104 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10105 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10108 struct drm_device
*dev
= crtc
->dev
;
10109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10110 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10111 int pipe
= intel_crtc
->pipe
;
10112 int x
= crtc
->cursor_x
;
10113 int y
= crtc
->cursor_y
;
10114 u32 base
= 0, pos
= 0;
10117 base
= intel_crtc
->cursor_addr
;
10119 if (x
>= intel_crtc
->config
->pipe_src_w
)
10122 if (y
>= intel_crtc
->config
->pipe_src_h
)
10126 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
10129 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10132 pos
|= x
<< CURSOR_X_SHIFT
;
10135 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
10138 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10141 pos
|= y
<< CURSOR_Y_SHIFT
;
10143 if (base
== 0 && intel_crtc
->cursor_base
== 0)
10146 I915_WRITE(CURPOS(pipe
), pos
);
10148 /* ILK+ do this automagically */
10149 if (HAS_GMCH_DISPLAY(dev
) &&
10150 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
10151 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
10152 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
10155 if (IS_845G(dev
) || IS_I865G(dev
))
10156 i845_update_cursor(crtc
, base
);
10158 i9xx_update_cursor(crtc
, base
);
10161 static bool cursor_size_ok(struct drm_device
*dev
,
10162 uint32_t width
, uint32_t height
)
10164 if (width
== 0 || height
== 0)
10168 * 845g/865g are special in that they are only limited by
10169 * the width of their cursors, the height is arbitrary up to
10170 * the precision of the register. Everything else requires
10171 * square cursors, limited to a few power-of-two sizes.
10173 if (IS_845G(dev
) || IS_I865G(dev
)) {
10174 if ((width
& 63) != 0)
10177 if (width
> (IS_845G(dev
) ? 64 : 512))
10183 switch (width
| height
) {
10198 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
10199 u16
*blue
, uint32_t start
, uint32_t size
)
10201 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
10202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10204 for (i
= start
; i
< end
; i
++) {
10205 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
10206 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
10207 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
10210 intel_crtc_load_lut(crtc
);
10213 /* VESA 640x480x72Hz mode to set on the pipe */
10214 static struct drm_display_mode load_detect_mode
= {
10215 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10216 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10219 struct drm_framebuffer
*
10220 __intel_framebuffer_create(struct drm_device
*dev
,
10221 struct drm_mode_fb_cmd2
*mode_cmd
,
10222 struct drm_i915_gem_object
*obj
)
10224 struct intel_framebuffer
*intel_fb
;
10227 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10229 drm_gem_object_unreference(&obj
->base
);
10230 return ERR_PTR(-ENOMEM
);
10233 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10237 return &intel_fb
->base
;
10239 drm_gem_object_unreference(&obj
->base
);
10242 return ERR_PTR(ret
);
10245 static struct drm_framebuffer
*
10246 intel_framebuffer_create(struct drm_device
*dev
,
10247 struct drm_mode_fb_cmd2
*mode_cmd
,
10248 struct drm_i915_gem_object
*obj
)
10250 struct drm_framebuffer
*fb
;
10253 ret
= i915_mutex_lock_interruptible(dev
);
10255 return ERR_PTR(ret
);
10256 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10257 mutex_unlock(&dev
->struct_mutex
);
10263 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10265 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10266 return ALIGN(pitch
, 64);
10270 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10272 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10273 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10276 static struct drm_framebuffer
*
10277 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10278 struct drm_display_mode
*mode
,
10279 int depth
, int bpp
)
10281 struct drm_i915_gem_object
*obj
;
10282 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10284 obj
= i915_gem_alloc_object(dev
,
10285 intel_framebuffer_size_for_mode(mode
, bpp
));
10287 return ERR_PTR(-ENOMEM
);
10289 mode_cmd
.width
= mode
->hdisplay
;
10290 mode_cmd
.height
= mode
->vdisplay
;
10291 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10293 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10295 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10298 static struct drm_framebuffer
*
10299 mode_fits_in_fbdev(struct drm_device
*dev
,
10300 struct drm_display_mode
*mode
)
10302 #ifdef CONFIG_DRM_I915_FBDEV
10303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10304 struct drm_i915_gem_object
*obj
;
10305 struct drm_framebuffer
*fb
;
10307 if (!dev_priv
->fbdev
)
10310 if (!dev_priv
->fbdev
->fb
)
10313 obj
= dev_priv
->fbdev
->fb
->obj
;
10316 fb
= &dev_priv
->fbdev
->fb
->base
;
10317 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10318 fb
->bits_per_pixel
))
10321 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10330 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10331 struct drm_crtc
*crtc
,
10332 struct drm_display_mode
*mode
,
10333 struct drm_framebuffer
*fb
,
10336 struct drm_plane_state
*plane_state
;
10337 int hdisplay
, vdisplay
;
10340 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10341 if (IS_ERR(plane_state
))
10342 return PTR_ERR(plane_state
);
10345 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10347 hdisplay
= vdisplay
= 0;
10349 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10352 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10353 plane_state
->crtc_x
= 0;
10354 plane_state
->crtc_y
= 0;
10355 plane_state
->crtc_w
= hdisplay
;
10356 plane_state
->crtc_h
= vdisplay
;
10357 plane_state
->src_x
= x
<< 16;
10358 plane_state
->src_y
= y
<< 16;
10359 plane_state
->src_w
= hdisplay
<< 16;
10360 plane_state
->src_h
= vdisplay
<< 16;
10365 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10366 struct drm_display_mode
*mode
,
10367 struct intel_load_detect_pipe
*old
,
10368 struct drm_modeset_acquire_ctx
*ctx
)
10370 struct intel_crtc
*intel_crtc
;
10371 struct intel_encoder
*intel_encoder
=
10372 intel_attached_encoder(connector
);
10373 struct drm_crtc
*possible_crtc
;
10374 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10375 struct drm_crtc
*crtc
= NULL
;
10376 struct drm_device
*dev
= encoder
->dev
;
10377 struct drm_framebuffer
*fb
;
10378 struct drm_mode_config
*config
= &dev
->mode_config
;
10379 struct drm_atomic_state
*state
= NULL
;
10380 struct drm_connector_state
*connector_state
;
10381 struct intel_crtc_state
*crtc_state
;
10384 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10385 connector
->base
.id
, connector
->name
,
10386 encoder
->base
.id
, encoder
->name
);
10389 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10394 * Algorithm gets a little messy:
10396 * - if the connector already has an assigned crtc, use it (but make
10397 * sure it's on first)
10399 * - try to find the first unused crtc that can drive this connector,
10400 * and use that if we find one
10403 /* See if we already have a CRTC for this connector */
10404 if (encoder
->crtc
) {
10405 crtc
= encoder
->crtc
;
10407 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10410 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10414 old
->dpms_mode
= connector
->dpms
;
10415 old
->load_detect_temp
= false;
10417 /* Make sure the crtc and connector are running */
10418 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
10419 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
10424 /* Find an unused one (if possible) */
10425 for_each_crtc(dev
, possible_crtc
) {
10427 if (!(encoder
->possible_crtcs
& (1 << i
)))
10429 if (possible_crtc
->state
->enable
)
10431 /* This can occur when applying the pipe A quirk on resume. */
10432 if (to_intel_crtc(possible_crtc
)->new_enabled
)
10435 crtc
= possible_crtc
;
10440 * If we didn't find an unused CRTC, don't use any.
10443 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10447 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10450 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10453 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
10454 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
10456 intel_crtc
= to_intel_crtc(crtc
);
10457 intel_crtc
->new_enabled
= true;
10458 old
->dpms_mode
= connector
->dpms
;
10459 old
->load_detect_temp
= true;
10460 old
->release_fb
= NULL
;
10462 state
= drm_atomic_state_alloc(dev
);
10466 state
->acquire_ctx
= ctx
;
10468 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10469 if (IS_ERR(connector_state
)) {
10470 ret
= PTR_ERR(connector_state
);
10474 connector_state
->crtc
= crtc
;
10475 connector_state
->best_encoder
= &intel_encoder
->base
;
10477 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10478 if (IS_ERR(crtc_state
)) {
10479 ret
= PTR_ERR(crtc_state
);
10483 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10486 mode
= &load_detect_mode
;
10488 /* We need a framebuffer large enough to accommodate all accesses
10489 * that the plane may generate whilst we perform load detection.
10490 * We can not rely on the fbcon either being present (we get called
10491 * during its initialisation to detect all boot displays, or it may
10492 * not even exist) or that it is large enough to satisfy the
10495 fb
= mode_fits_in_fbdev(dev
, mode
);
10497 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10498 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10499 old
->release_fb
= fb
;
10501 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10503 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10507 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10511 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10513 if (intel_set_mode(state
)) {
10514 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10515 if (old
->release_fb
)
10516 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10519 crtc
->primary
->crtc
= crtc
;
10521 /* let the connector get through one full cycle before testing */
10522 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10526 intel_crtc
->new_enabled
= crtc
->state
->enable
;
10528 drm_atomic_state_free(state
);
10531 if (ret
== -EDEADLK
) {
10532 drm_modeset_backoff(ctx
);
10539 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10540 struct intel_load_detect_pipe
*old
,
10541 struct drm_modeset_acquire_ctx
*ctx
)
10543 struct drm_device
*dev
= connector
->dev
;
10544 struct intel_encoder
*intel_encoder
=
10545 intel_attached_encoder(connector
);
10546 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10547 struct drm_crtc
*crtc
= encoder
->crtc
;
10548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10549 struct drm_atomic_state
*state
;
10550 struct drm_connector_state
*connector_state
;
10551 struct intel_crtc_state
*crtc_state
;
10554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10555 connector
->base
.id
, connector
->name
,
10556 encoder
->base
.id
, encoder
->name
);
10558 if (old
->load_detect_temp
) {
10559 state
= drm_atomic_state_alloc(dev
);
10563 state
->acquire_ctx
= ctx
;
10565 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10566 if (IS_ERR(connector_state
))
10569 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10570 if (IS_ERR(crtc_state
))
10573 to_intel_connector(connector
)->new_encoder
= NULL
;
10574 intel_encoder
->new_crtc
= NULL
;
10575 intel_crtc
->new_enabled
= false;
10577 connector_state
->best_encoder
= NULL
;
10578 connector_state
->crtc
= NULL
;
10580 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10582 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10587 ret
= intel_set_mode(state
);
10591 if (old
->release_fb
) {
10592 drm_framebuffer_unregister_private(old
->release_fb
);
10593 drm_framebuffer_unreference(old
->release_fb
);
10599 /* Switch crtc and encoder back off if necessary */
10600 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10601 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10605 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10606 drm_atomic_state_free(state
);
10609 static int i9xx_pll_refclk(struct drm_device
*dev
,
10610 const struct intel_crtc_state
*pipe_config
)
10612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10613 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10615 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10616 return dev_priv
->vbt
.lvds_ssc_freq
;
10617 else if (HAS_PCH_SPLIT(dev
))
10619 else if (!IS_GEN2(dev
))
10625 /* Returns the clock of the currently programmed mode of the given pipe. */
10626 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10627 struct intel_crtc_state
*pipe_config
)
10629 struct drm_device
*dev
= crtc
->base
.dev
;
10630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10631 int pipe
= pipe_config
->cpu_transcoder
;
10632 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10634 intel_clock_t clock
;
10635 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10637 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10638 fp
= pipe_config
->dpll_hw_state
.fp0
;
10640 fp
= pipe_config
->dpll_hw_state
.fp1
;
10642 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10643 if (IS_PINEVIEW(dev
)) {
10644 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10645 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10647 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10648 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10651 if (!IS_GEN2(dev
)) {
10652 if (IS_PINEVIEW(dev
))
10653 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10654 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10656 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10657 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10659 switch (dpll
& DPLL_MODE_MASK
) {
10660 case DPLLB_MODE_DAC_SERIAL
:
10661 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10664 case DPLLB_MODE_LVDS
:
10665 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10669 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10670 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10674 if (IS_PINEVIEW(dev
))
10675 pineview_clock(refclk
, &clock
);
10677 i9xx_clock(refclk
, &clock
);
10679 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10680 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10683 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10684 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10686 if (lvds
& LVDS_CLKB_POWER_UP
)
10691 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10694 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10695 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10697 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10703 i9xx_clock(refclk
, &clock
);
10707 * This value includes pixel_multiplier. We will use
10708 * port_clock to compute adjusted_mode.crtc_clock in the
10709 * encoder's get_config() function.
10711 pipe_config
->port_clock
= clock
.dot
;
10714 int intel_dotclock_calculate(int link_freq
,
10715 const struct intel_link_m_n
*m_n
)
10718 * The calculation for the data clock is:
10719 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10720 * But we want to avoid losing precison if possible, so:
10721 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10723 * and the link clock is simpler:
10724 * link_clock = (m * link_clock) / n
10730 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10733 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10734 struct intel_crtc_state
*pipe_config
)
10736 struct drm_device
*dev
= crtc
->base
.dev
;
10738 /* read out port_clock from the DPLL */
10739 i9xx_crtc_clock_get(crtc
, pipe_config
);
10742 * This value does not include pixel_multiplier.
10743 * We will check that port_clock and adjusted_mode.crtc_clock
10744 * agree once we know their relationship in the encoder's
10745 * get_config() function.
10747 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10748 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10749 &pipe_config
->fdi_m_n
);
10752 /** Returns the currently programmed mode of the given pipe. */
10753 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10754 struct drm_crtc
*crtc
)
10756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10758 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10759 struct drm_display_mode
*mode
;
10760 struct intel_crtc_state pipe_config
;
10761 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10762 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10763 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10764 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10765 enum pipe pipe
= intel_crtc
->pipe
;
10767 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10772 * Construct a pipe_config sufficient for getting the clock info
10773 * back out of crtc_clock_get.
10775 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10776 * to use a real value here instead.
10778 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10779 pipe_config
.pixel_multiplier
= 1;
10780 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10781 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10782 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10783 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10785 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10786 mode
->hdisplay
= (htot
& 0xffff) + 1;
10787 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10788 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10789 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10790 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10791 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10792 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10793 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10795 drm_mode_set_name(mode
);
10800 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10802 struct drm_device
*dev
= crtc
->dev
;
10803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10806 if (!HAS_GMCH_DISPLAY(dev
))
10809 if (!dev_priv
->lvds_downclock_avail
)
10813 * Since this is called by a timer, we should never get here in
10816 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10817 int pipe
= intel_crtc
->pipe
;
10818 int dpll_reg
= DPLL(pipe
);
10821 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10823 assert_panel_unlocked(dev_priv
, pipe
);
10825 dpll
= I915_READ(dpll_reg
);
10826 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10827 I915_WRITE(dpll_reg
, dpll
);
10828 intel_wait_for_vblank(dev
, pipe
);
10829 dpll
= I915_READ(dpll_reg
);
10830 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10831 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10836 void intel_mark_busy(struct drm_device
*dev
)
10838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10840 if (dev_priv
->mm
.busy
)
10843 intel_runtime_pm_get(dev_priv
);
10844 i915_update_gfx_val(dev_priv
);
10845 if (INTEL_INFO(dev
)->gen
>= 6)
10846 gen6_rps_busy(dev_priv
);
10847 dev_priv
->mm
.busy
= true;
10850 void intel_mark_idle(struct drm_device
*dev
)
10852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10853 struct drm_crtc
*crtc
;
10855 if (!dev_priv
->mm
.busy
)
10858 dev_priv
->mm
.busy
= false;
10860 for_each_crtc(dev
, crtc
) {
10861 if (!crtc
->primary
->fb
)
10864 intel_decrease_pllclock(crtc
);
10867 if (INTEL_INFO(dev
)->gen
>= 6)
10868 gen6_rps_idle(dev
->dev_private
);
10870 intel_runtime_pm_put(dev_priv
);
10873 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10875 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10876 struct drm_device
*dev
= crtc
->dev
;
10877 struct intel_unpin_work
*work
;
10879 spin_lock_irq(&dev
->event_lock
);
10880 work
= intel_crtc
->unpin_work
;
10881 intel_crtc
->unpin_work
= NULL
;
10882 spin_unlock_irq(&dev
->event_lock
);
10885 cancel_work_sync(&work
->work
);
10889 drm_crtc_cleanup(crtc
);
10894 static void intel_unpin_work_fn(struct work_struct
*__work
)
10896 struct intel_unpin_work
*work
=
10897 container_of(__work
, struct intel_unpin_work
, work
);
10898 struct drm_device
*dev
= work
->crtc
->dev
;
10899 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10901 mutex_lock(&dev
->struct_mutex
);
10902 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10903 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10905 intel_fbc_update(dev
);
10907 if (work
->flip_queued_req
)
10908 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10909 mutex_unlock(&dev
->struct_mutex
);
10911 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10912 drm_framebuffer_unreference(work
->old_fb
);
10914 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10915 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10920 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10921 struct drm_crtc
*crtc
)
10923 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10924 struct intel_unpin_work
*work
;
10925 unsigned long flags
;
10927 /* Ignore early vblank irqs */
10928 if (intel_crtc
== NULL
)
10932 * This is called both by irq handlers and the reset code (to complete
10933 * lost pageflips) so needs the full irqsave spinlocks.
10935 spin_lock_irqsave(&dev
->event_lock
, flags
);
10936 work
= intel_crtc
->unpin_work
;
10938 /* Ensure we don't miss a work->pending update ... */
10941 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10942 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10946 page_flip_completed(intel_crtc
);
10948 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10951 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10954 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10956 do_intel_finish_page_flip(dev
, crtc
);
10959 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10962 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10964 do_intel_finish_page_flip(dev
, crtc
);
10967 /* Is 'a' after or equal to 'b'? */
10968 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10970 return !((a
- b
) & 0x80000000);
10973 static bool page_flip_finished(struct intel_crtc
*crtc
)
10975 struct drm_device
*dev
= crtc
->base
.dev
;
10976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10978 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10979 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10983 * The relevant registers doen't exist on pre-ctg.
10984 * As the flip done interrupt doesn't trigger for mmio
10985 * flips on gmch platforms, a flip count check isn't
10986 * really needed there. But since ctg has the registers,
10987 * include it in the check anyway.
10989 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10993 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10994 * used the same base address. In that case the mmio flip might
10995 * have completed, but the CS hasn't even executed the flip yet.
10997 * A flip count check isn't enough as the CS might have updated
10998 * the base address just after start of vblank, but before we
10999 * managed to process the interrupt. This means we'd complete the
11000 * CS flip too soon.
11002 * Combining both checks should get us a good enough result. It may
11003 * still happen that the CS flip has been executed, but has not
11004 * yet actually completed. But in case the base address is the same
11005 * anyway, we don't really care.
11007 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
11008 crtc
->unpin_work
->gtt_offset
&&
11009 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
11010 crtc
->unpin_work
->flip_count
);
11013 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
11015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11016 struct intel_crtc
*intel_crtc
=
11017 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
11018 unsigned long flags
;
11022 * This is called both by irq handlers and the reset code (to complete
11023 * lost pageflips) so needs the full irqsave spinlocks.
11025 * NB: An MMIO update of the plane base pointer will also
11026 * generate a page-flip completion irq, i.e. every modeset
11027 * is also accompanied by a spurious intel_prepare_page_flip().
11029 spin_lock_irqsave(&dev
->event_lock
, flags
);
11030 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
11031 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
11032 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
11035 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
11037 /* Ensure that the work item is consistent when activating it ... */
11039 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
11040 /* and that it is marked active as soon as the irq could fire. */
11044 static int intel_gen2_queue_flip(struct drm_device
*dev
,
11045 struct drm_crtc
*crtc
,
11046 struct drm_framebuffer
*fb
,
11047 struct drm_i915_gem_object
*obj
,
11048 struct intel_engine_cs
*ring
,
11051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11055 ret
= intel_ring_begin(ring
, 6);
11059 /* Can't queue multiple flips, so wait for the previous
11060 * one to finish before executing the next.
11062 if (intel_crtc
->plane
)
11063 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11065 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11066 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11067 intel_ring_emit(ring
, MI_NOOP
);
11068 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11069 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11070 intel_ring_emit(ring
, fb
->pitches
[0]);
11071 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11072 intel_ring_emit(ring
, 0); /* aux display base address, unused */
11074 intel_mark_page_flip_active(intel_crtc
);
11075 __intel_ring_advance(ring
);
11079 static int intel_gen3_queue_flip(struct drm_device
*dev
,
11080 struct drm_crtc
*crtc
,
11081 struct drm_framebuffer
*fb
,
11082 struct drm_i915_gem_object
*obj
,
11083 struct intel_engine_cs
*ring
,
11086 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11090 ret
= intel_ring_begin(ring
, 6);
11094 if (intel_crtc
->plane
)
11095 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
11097 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
11098 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
11099 intel_ring_emit(ring
, MI_NOOP
);
11100 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
11101 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11102 intel_ring_emit(ring
, fb
->pitches
[0]);
11103 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11104 intel_ring_emit(ring
, MI_NOOP
);
11106 intel_mark_page_flip_active(intel_crtc
);
11107 __intel_ring_advance(ring
);
11111 static int intel_gen4_queue_flip(struct drm_device
*dev
,
11112 struct drm_crtc
*crtc
,
11113 struct drm_framebuffer
*fb
,
11114 struct drm_i915_gem_object
*obj
,
11115 struct intel_engine_cs
*ring
,
11118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11120 uint32_t pf
, pipesrc
;
11123 ret
= intel_ring_begin(ring
, 4);
11127 /* i965+ uses the linear or tiled offsets from the
11128 * Display Registers (which do not change across a page-flip)
11129 * so we need only reprogram the base address.
11131 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11132 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11133 intel_ring_emit(ring
, fb
->pitches
[0]);
11134 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
11137 /* XXX Enabling the panel-fitter across page-flip is so far
11138 * untested on non-native modes, so ignore it for now.
11139 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11142 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11143 intel_ring_emit(ring
, pf
| pipesrc
);
11145 intel_mark_page_flip_active(intel_crtc
);
11146 __intel_ring_advance(ring
);
11150 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11151 struct drm_crtc
*crtc
,
11152 struct drm_framebuffer
*fb
,
11153 struct drm_i915_gem_object
*obj
,
11154 struct intel_engine_cs
*ring
,
11157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11159 uint32_t pf
, pipesrc
;
11162 ret
= intel_ring_begin(ring
, 4);
11166 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11167 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11168 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
11169 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11171 /* Contrary to the suggestions in the documentation,
11172 * "Enable Panel Fitter" does not seem to be required when page
11173 * flipping with a non-native mode, and worse causes a normal
11175 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11178 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11179 intel_ring_emit(ring
, pf
| pipesrc
);
11181 intel_mark_page_flip_active(intel_crtc
);
11182 __intel_ring_advance(ring
);
11186 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11187 struct drm_crtc
*crtc
,
11188 struct drm_framebuffer
*fb
,
11189 struct drm_i915_gem_object
*obj
,
11190 struct intel_engine_cs
*ring
,
11193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11194 uint32_t plane_bit
= 0;
11197 switch (intel_crtc
->plane
) {
11199 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11202 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11205 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11208 WARN_ONCE(1, "unknown plane in flip command\n");
11213 if (ring
->id
== RCS
) {
11216 * On Gen 8, SRM is now taking an extra dword to accommodate
11217 * 48bits addresses, and we need a NOOP for the batch size to
11225 * BSpec MI_DISPLAY_FLIP for IVB:
11226 * "The full packet must be contained within the same cache line."
11228 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11229 * cacheline, if we ever start emitting more commands before
11230 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11231 * then do the cacheline alignment, and finally emit the
11234 ret
= intel_ring_cacheline_align(ring
);
11238 ret
= intel_ring_begin(ring
, len
);
11242 /* Unmask the flip-done completion message. Note that the bspec says that
11243 * we should do this for both the BCS and RCS, and that we must not unmask
11244 * more than one flip event at any time (or ensure that one flip message
11245 * can be sent by waiting for flip-done prior to queueing new flips).
11246 * Experimentation says that BCS works despite DERRMR masking all
11247 * flip-done completion events and that unmasking all planes at once
11248 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11249 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11251 if (ring
->id
== RCS
) {
11252 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11253 intel_ring_emit(ring
, DERRMR
);
11254 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11255 DERRMR_PIPEB_PRI_FLIP_DONE
|
11256 DERRMR_PIPEC_PRI_FLIP_DONE
));
11258 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
11259 MI_SRM_LRM_GLOBAL_GTT
);
11261 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
11262 MI_SRM_LRM_GLOBAL_GTT
);
11263 intel_ring_emit(ring
, DERRMR
);
11264 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
11265 if (IS_GEN8(dev
)) {
11266 intel_ring_emit(ring
, 0);
11267 intel_ring_emit(ring
, MI_NOOP
);
11271 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11272 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
11273 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11274 intel_ring_emit(ring
, (MI_NOOP
));
11276 intel_mark_page_flip_active(intel_crtc
);
11277 __intel_ring_advance(ring
);
11281 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
11282 struct drm_i915_gem_object
*obj
)
11285 * This is not being used for older platforms, because
11286 * non-availability of flip done interrupt forces us to use
11287 * CS flips. Older platforms derive flip done using some clever
11288 * tricks involving the flip_pending status bits and vblank irqs.
11289 * So using MMIO flips there would disrupt this mechanism.
11295 if (INTEL_INFO(ring
->dev
)->gen
< 5)
11298 if (i915
.use_mmio_flip
< 0)
11300 else if (i915
.use_mmio_flip
> 0)
11302 else if (i915
.enable_execlists
)
11305 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
11308 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11310 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11312 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11313 const enum pipe pipe
= intel_crtc
->pipe
;
11316 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11317 ctl
&= ~PLANE_CTL_TILED_MASK
;
11318 switch (fb
->modifier
[0]) {
11319 case DRM_FORMAT_MOD_NONE
:
11321 case I915_FORMAT_MOD_X_TILED
:
11322 ctl
|= PLANE_CTL_TILED_X
;
11324 case I915_FORMAT_MOD_Y_TILED
:
11325 ctl
|= PLANE_CTL_TILED_Y
;
11327 case I915_FORMAT_MOD_Yf_TILED
:
11328 ctl
|= PLANE_CTL_TILED_YF
;
11331 MISSING_CASE(fb
->modifier
[0]);
11335 * The stride is either expressed as a multiple of 64 bytes chunks for
11336 * linear buffers or in number of tiles for tiled buffers.
11338 stride
= fb
->pitches
[0] /
11339 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
11343 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11344 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11346 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11347 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11349 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
11350 POSTING_READ(PLANE_SURF(pipe
, 0));
11353 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11355 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11357 struct intel_framebuffer
*intel_fb
=
11358 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11359 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11363 reg
= DSPCNTR(intel_crtc
->plane
);
11364 dspcntr
= I915_READ(reg
);
11366 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11367 dspcntr
|= DISPPLANE_TILED
;
11369 dspcntr
&= ~DISPPLANE_TILED
;
11371 I915_WRITE(reg
, dspcntr
);
11373 I915_WRITE(DSPSURF(intel_crtc
->plane
),
11374 intel_crtc
->unpin_work
->gtt_offset
);
11375 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11380 * XXX: This is the temporary way to update the plane registers until we get
11381 * around to using the usual plane update functions for MMIO flips
11383 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
11385 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11386 bool atomic_update
;
11387 u32 start_vbl_count
;
11389 intel_mark_page_flip_active(intel_crtc
);
11391 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
11393 if (INTEL_INFO(dev
)->gen
>= 9)
11394 skl_do_mmio_flip(intel_crtc
);
11396 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11397 ilk_do_mmio_flip(intel_crtc
);
11400 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
11403 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11405 struct intel_mmio_flip
*mmio_flip
=
11406 container_of(work
, struct intel_mmio_flip
, work
);
11408 if (mmio_flip
->req
)
11409 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11410 mmio_flip
->crtc
->reset_counter
,
11412 &mmio_flip
->i915
->rps
.mmioflips
));
11414 intel_do_mmio_flip(mmio_flip
->crtc
);
11416 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11420 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11421 struct drm_crtc
*crtc
,
11422 struct drm_framebuffer
*fb
,
11423 struct drm_i915_gem_object
*obj
,
11424 struct intel_engine_cs
*ring
,
11427 struct intel_mmio_flip
*mmio_flip
;
11429 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11430 if (mmio_flip
== NULL
)
11433 mmio_flip
->i915
= to_i915(dev
);
11434 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11435 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11437 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11438 schedule_work(&mmio_flip
->work
);
11443 static int intel_default_queue_flip(struct drm_device
*dev
,
11444 struct drm_crtc
*crtc
,
11445 struct drm_framebuffer
*fb
,
11446 struct drm_i915_gem_object
*obj
,
11447 struct intel_engine_cs
*ring
,
11453 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11454 struct drm_crtc
*crtc
)
11456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11457 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11458 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11461 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11464 if (!work
->enable_stall_check
)
11467 if (work
->flip_ready_vblank
== 0) {
11468 if (work
->flip_queued_req
&&
11469 !i915_gem_request_completed(work
->flip_queued_req
, true))
11472 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11475 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11478 /* Potential stall - if we see that the flip has happened,
11479 * assume a missed interrupt. */
11480 if (INTEL_INFO(dev
)->gen
>= 4)
11481 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11483 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11485 /* There is a potential issue here with a false positive after a flip
11486 * to the same address. We could address this by checking for a
11487 * non-incrementing frame counter.
11489 return addr
== work
->gtt_offset
;
11492 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11495 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11496 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11497 struct intel_unpin_work
*work
;
11499 WARN_ON(!in_interrupt());
11504 spin_lock(&dev
->event_lock
);
11505 work
= intel_crtc
->unpin_work
;
11506 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11507 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11508 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11509 page_flip_completed(intel_crtc
);
11512 if (work
!= NULL
&&
11513 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11514 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11515 spin_unlock(&dev
->event_lock
);
11518 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11519 struct drm_framebuffer
*fb
,
11520 struct drm_pending_vblank_event
*event
,
11521 uint32_t page_flip_flags
)
11523 struct drm_device
*dev
= crtc
->dev
;
11524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11525 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11526 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11528 struct drm_plane
*primary
= crtc
->primary
;
11529 enum pipe pipe
= intel_crtc
->pipe
;
11530 struct intel_unpin_work
*work
;
11531 struct intel_engine_cs
*ring
;
11536 * drm_mode_page_flip_ioctl() should already catch this, but double
11537 * check to be safe. In the future we may enable pageflipping from
11538 * a disabled primary plane.
11540 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11543 /* Can't change pixel format via MI display flips. */
11544 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11548 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11549 * Note that pitch changes could also affect these register.
11551 if (INTEL_INFO(dev
)->gen
> 3 &&
11552 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11553 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11556 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11559 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11563 work
->event
= event
;
11565 work
->old_fb
= old_fb
;
11566 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11568 ret
= drm_crtc_vblank_get(crtc
);
11572 /* We borrow the event spin lock for protecting unpin_work */
11573 spin_lock_irq(&dev
->event_lock
);
11574 if (intel_crtc
->unpin_work
) {
11575 /* Before declaring the flip queue wedged, check if
11576 * the hardware completed the operation behind our backs.
11578 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11579 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11580 page_flip_completed(intel_crtc
);
11582 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11583 spin_unlock_irq(&dev
->event_lock
);
11585 drm_crtc_vblank_put(crtc
);
11590 intel_crtc
->unpin_work
= work
;
11591 spin_unlock_irq(&dev
->event_lock
);
11593 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11594 flush_workqueue(dev_priv
->wq
);
11596 /* Reference the objects for the scheduled work. */
11597 drm_framebuffer_reference(work
->old_fb
);
11598 drm_gem_object_reference(&obj
->base
);
11600 crtc
->primary
->fb
= fb
;
11601 update_state_fb(crtc
->primary
);
11603 work
->pending_flip_obj
= obj
;
11605 ret
= i915_mutex_lock_interruptible(dev
);
11609 atomic_inc(&intel_crtc
->unpin_work_count
);
11610 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11612 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11613 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
11615 if (IS_VALLEYVIEW(dev
)) {
11616 ring
= &dev_priv
->ring
[BCS
];
11617 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11618 /* vlv: DISPLAY_FLIP fails to change tiling */
11620 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11621 ring
= &dev_priv
->ring
[BCS
];
11622 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11623 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11624 if (ring
== NULL
|| ring
->id
!= RCS
)
11625 ring
= &dev_priv
->ring
[BCS
];
11627 ring
= &dev_priv
->ring
[RCS
];
11630 mmio_flip
= use_mmio_flip(ring
, obj
);
11632 /* When using CS flips, we want to emit semaphores between rings.
11633 * However, when using mmio flips we will create a task to do the
11634 * synchronisation, so all we want here is to pin the framebuffer
11635 * into the display plane and skip any waits.
11637 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11638 crtc
->primary
->state
,
11639 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
);
11641 goto cleanup_pending
;
11643 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
11644 + intel_crtc
->dspaddr_offset
;
11647 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11650 goto cleanup_unpin
;
11652 i915_gem_request_assign(&work
->flip_queued_req
,
11653 obj
->last_write_req
);
11655 if (obj
->last_write_req
) {
11656 ret
= i915_gem_check_olr(obj
->last_write_req
);
11658 goto cleanup_unpin
;
11661 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11664 goto cleanup_unpin
;
11666 i915_gem_request_assign(&work
->flip_queued_req
,
11667 intel_ring_get_request(ring
));
11670 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11671 work
->enable_stall_check
= true;
11673 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11674 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11676 intel_fbc_disable(dev
);
11677 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11678 mutex_unlock(&dev
->struct_mutex
);
11680 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11685 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11687 atomic_dec(&intel_crtc
->unpin_work_count
);
11688 mutex_unlock(&dev
->struct_mutex
);
11690 crtc
->primary
->fb
= old_fb
;
11691 update_state_fb(crtc
->primary
);
11693 drm_gem_object_unreference_unlocked(&obj
->base
);
11694 drm_framebuffer_unreference(work
->old_fb
);
11696 spin_lock_irq(&dev
->event_lock
);
11697 intel_crtc
->unpin_work
= NULL
;
11698 spin_unlock_irq(&dev
->event_lock
);
11700 drm_crtc_vblank_put(crtc
);
11705 struct drm_atomic_state
*state
;
11706 struct drm_plane_state
*plane_state
;
11709 state
= drm_atomic_state_alloc(dev
);
11712 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11715 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11716 ret
= PTR_ERR_OR_ZERO(plane_state
);
11718 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11720 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11722 ret
= drm_atomic_commit(state
);
11725 if (ret
== -EDEADLK
) {
11726 drm_modeset_backoff(state
->acquire_ctx
);
11727 drm_atomic_state_clear(state
);
11732 drm_atomic_state_free(state
);
11734 if (ret
== 0 && event
) {
11735 spin_lock_irq(&dev
->event_lock
);
11736 drm_send_vblank_event(dev
, pipe
, event
);
11737 spin_unlock_irq(&dev
->event_lock
);
11745 * intel_wm_need_update - Check whether watermarks need updating
11746 * @plane: drm plane
11747 * @state: new plane state
11749 * Check current plane state versus the new one to determine whether
11750 * watermarks need to be recalculated.
11752 * Returns true or false.
11754 static bool intel_wm_need_update(struct drm_plane
*plane
,
11755 struct drm_plane_state
*state
)
11757 /* Update watermarks on tiling changes. */
11758 if (!plane
->state
->fb
|| !state
->fb
||
11759 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
11760 plane
->state
->rotation
!= state
->rotation
)
11763 if (plane
->state
->crtc_w
!= state
->crtc_w
)
11769 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11770 struct drm_plane_state
*plane_state
)
11772 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11773 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11774 struct drm_plane
*plane
= plane_state
->plane
;
11775 struct drm_device
*dev
= crtc
->dev
;
11776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11777 struct intel_plane_state
*old_plane_state
=
11778 to_intel_plane_state(plane
->state
);
11779 int idx
= intel_crtc
->base
.base
.id
, ret
;
11780 int i
= drm_plane_index(plane
);
11781 bool mode_changed
= needs_modeset(crtc_state
);
11782 bool was_crtc_enabled
= crtc
->state
->active
;
11783 bool is_crtc_enabled
= crtc_state
->active
;
11785 bool turn_off
, turn_on
, visible
, was_visible
;
11786 struct drm_framebuffer
*fb
= plane_state
->fb
;
11788 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11789 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11790 ret
= skl_update_scaler_plane(
11791 to_intel_crtc_state(crtc_state
),
11792 to_intel_plane_state(plane_state
));
11798 * Disabling a plane is always okay; we just need to update
11799 * fb tracking in a special way since cleanup_fb() won't
11800 * get called by the plane helpers.
11802 if (old_plane_state
->base
.fb
&& !fb
)
11803 intel_crtc
->atomic
.disabled_planes
|= 1 << i
;
11805 /* don't run rest during modeset yet */
11806 if (!intel_crtc
->active
|| mode_changed
)
11809 was_visible
= old_plane_state
->visible
;
11810 visible
= to_intel_plane_state(plane_state
)->visible
;
11812 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11813 was_visible
= false;
11815 if (!is_crtc_enabled
&& WARN_ON(visible
))
11818 if (!was_visible
&& !visible
)
11821 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11822 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11824 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11825 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11827 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11828 plane
->base
.id
, was_visible
, visible
,
11829 turn_off
, turn_on
, mode_changed
);
11831 if (intel_wm_need_update(plane
, plane_state
))
11832 intel_crtc
->atomic
.update_wm
= true;
11834 switch (plane
->type
) {
11835 case DRM_PLANE_TYPE_PRIMARY
:
11837 intel_crtc
->atomic
.fb_bits
|=
11838 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
11840 intel_crtc
->atomic
.wait_for_flips
= true;
11841 intel_crtc
->atomic
.pre_disable_primary
= turn_off
;
11842 intel_crtc
->atomic
.post_enable_primary
= turn_on
;
11845 intel_crtc
->atomic
.disable_fbc
= true;
11848 * FBC does not work on some platforms for rotated
11849 * planes, so disable it when rotation is not 0 and
11850 * update it when rotation is set back to 0.
11852 * FIXME: This is redundant with the fbc update done in
11853 * the primary plane enable function except that that
11854 * one is done too late. We eventually need to unify
11859 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11860 dev_priv
->fbc
.crtc
== intel_crtc
&&
11861 plane_state
->rotation
!= BIT(DRM_ROTATE_0
))
11862 intel_crtc
->atomic
.disable_fbc
= true;
11865 * BDW signals flip done immediately if the plane
11866 * is disabled, even if the plane enable is already
11867 * armed to occur at the next vblank :(
11869 if (turn_on
&& IS_BROADWELL(dev
))
11870 intel_crtc
->atomic
.wait_vblank
= true;
11872 intel_crtc
->atomic
.update_fbc
|= visible
|| mode_changed
;
11874 case DRM_PLANE_TYPE_CURSOR
:
11876 intel_crtc
->atomic
.fb_bits
|=
11877 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
11879 case DRM_PLANE_TYPE_OVERLAY
:
11881 * 'prepare' is never called when plane is being disabled, so
11882 * we need to handle frontbuffer tracking as a special case
11885 intel_crtc
->atomic
.fb_bits
|=
11886 INTEL_FRONTBUFFER_SPRITE(intel_crtc
->pipe
);
11888 if (turn_off
&& is_crtc_enabled
) {
11889 intel_crtc
->atomic
.wait_vblank
= true;
11890 intel_crtc
->atomic
.update_sprite_watermarks
|=
11898 static bool encoders_cloneable(const struct intel_encoder
*a
,
11899 const struct intel_encoder
*b
)
11901 /* masks could be asymmetric, so check both ways */
11902 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11903 b
->cloneable
& (1 << a
->type
));
11906 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11907 struct intel_crtc
*crtc
,
11908 struct intel_encoder
*encoder
)
11910 struct intel_encoder
*source_encoder
;
11911 struct drm_connector
*connector
;
11912 struct drm_connector_state
*connector_state
;
11915 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11916 if (connector_state
->crtc
!= &crtc
->base
)
11920 to_intel_encoder(connector_state
->best_encoder
);
11921 if (!encoders_cloneable(encoder
, source_encoder
))
11928 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11929 struct intel_crtc
*crtc
)
11931 struct intel_encoder
*encoder
;
11932 struct drm_connector
*connector
;
11933 struct drm_connector_state
*connector_state
;
11936 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11937 if (connector_state
->crtc
!= &crtc
->base
)
11940 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11941 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11948 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11949 struct drm_crtc_state
*crtc_state
)
11951 struct drm_device
*dev
= crtc
->dev
;
11952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11953 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11954 struct intel_crtc_state
*pipe_config
=
11955 to_intel_crtc_state(crtc_state
);
11956 struct drm_atomic_state
*state
= crtc_state
->state
;
11957 int ret
, idx
= crtc
->base
.id
;
11958 bool mode_changed
= needs_modeset(crtc_state
);
11960 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11961 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11965 I915_STATE_WARN(crtc
->state
->active
!= intel_crtc
->active
,
11966 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11967 idx
, crtc
->state
->active
, intel_crtc
->active
);
11969 if (mode_changed
&& crtc_state
->enable
&&
11970 dev_priv
->display
.crtc_compute_clock
&&
11971 !WARN_ON(pipe_config
->shared_dpll
!= DPLL_ID_PRIVATE
)) {
11972 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11978 return intel_atomic_setup_scalers(dev
, intel_crtc
, pipe_config
);
11981 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11982 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11983 .load_lut
= intel_crtc_load_lut
,
11984 .atomic_begin
= intel_begin_crtc_commit
,
11985 .atomic_flush
= intel_finish_crtc_commit
,
11986 .atomic_check
= intel_crtc_atomic_check
,
11990 * intel_modeset_update_staged_output_state
11992 * Updates the staged output configuration state, e.g. after we've read out the
11993 * current hw state.
11995 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11997 struct intel_crtc
*crtc
;
11998 struct intel_encoder
*encoder
;
11999 struct intel_connector
*connector
;
12001 for_each_intel_connector(dev
, connector
) {
12002 connector
->new_encoder
=
12003 to_intel_encoder(connector
->base
.encoder
);
12006 for_each_intel_encoder(dev
, encoder
) {
12007 encoder
->new_crtc
=
12008 to_intel_crtc(encoder
->base
.crtc
);
12011 for_each_intel_crtc(dev
, crtc
) {
12012 crtc
->new_enabled
= crtc
->base
.state
->enable
;
12016 /* Transitional helper to copy current connector/encoder state to
12017 * connector->state. This is needed so that code that is partially
12018 * converted to atomic does the right thing.
12020 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
12022 struct intel_connector
*connector
;
12024 for_each_intel_connector(dev
, connector
) {
12025 if (connector
->base
.encoder
) {
12026 connector
->base
.state
->best_encoder
=
12027 connector
->base
.encoder
;
12028 connector
->base
.state
->crtc
=
12029 connector
->base
.encoder
->crtc
;
12031 connector
->base
.state
->best_encoder
= NULL
;
12032 connector
->base
.state
->crtc
= NULL
;
12038 connected_sink_compute_bpp(struct intel_connector
*connector
,
12039 struct intel_crtc_state
*pipe_config
)
12041 int bpp
= pipe_config
->pipe_bpp
;
12043 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12044 connector
->base
.base
.id
,
12045 connector
->base
.name
);
12047 /* Don't use an invalid EDID bpc value */
12048 if (connector
->base
.display_info
.bpc
&&
12049 connector
->base
.display_info
.bpc
* 3 < bpp
) {
12050 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12051 bpp
, connector
->base
.display_info
.bpc
*3);
12052 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
12055 /* Clamp bpp to 8 on screens without EDID 1.4 */
12056 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
12057 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12059 pipe_config
->pipe_bpp
= 24;
12064 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
12065 struct intel_crtc_state
*pipe_config
)
12067 struct drm_device
*dev
= crtc
->base
.dev
;
12068 struct drm_atomic_state
*state
;
12069 struct drm_connector
*connector
;
12070 struct drm_connector_state
*connector_state
;
12073 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
12075 else if (INTEL_INFO(dev
)->gen
>= 5)
12081 pipe_config
->pipe_bpp
= bpp
;
12083 state
= pipe_config
->base
.state
;
12085 /* Clamp display bpp to EDID value */
12086 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12087 if (connector_state
->crtc
!= &crtc
->base
)
12090 connected_sink_compute_bpp(to_intel_connector(connector
),
12097 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
12099 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12100 "type: 0x%x flags: 0x%x\n",
12102 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
12103 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
12104 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
12105 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
12108 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
12109 struct intel_crtc_state
*pipe_config
,
12110 const char *context
)
12112 struct drm_device
*dev
= crtc
->base
.dev
;
12113 struct drm_plane
*plane
;
12114 struct intel_plane
*intel_plane
;
12115 struct intel_plane_state
*state
;
12116 struct drm_framebuffer
*fb
;
12118 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
12119 context
, pipe_config
, pipe_name(crtc
->pipe
));
12121 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
12122 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12123 pipe_config
->pipe_bpp
, pipe_config
->dither
);
12124 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12125 pipe_config
->has_pch_encoder
,
12126 pipe_config
->fdi_lanes
,
12127 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
12128 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
12129 pipe_config
->fdi_m_n
.tu
);
12130 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12131 pipe_config
->has_dp_encoder
,
12132 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12133 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12134 pipe_config
->dp_m_n
.tu
);
12136 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12137 pipe_config
->has_dp_encoder
,
12138 pipe_config
->dp_m2_n2
.gmch_m
,
12139 pipe_config
->dp_m2_n2
.gmch_n
,
12140 pipe_config
->dp_m2_n2
.link_m
,
12141 pipe_config
->dp_m2_n2
.link_n
,
12142 pipe_config
->dp_m2_n2
.tu
);
12144 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12145 pipe_config
->has_audio
,
12146 pipe_config
->has_infoframe
);
12148 DRM_DEBUG_KMS("requested mode:\n");
12149 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12150 DRM_DEBUG_KMS("adjusted mode:\n");
12151 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12152 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12153 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12154 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12155 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12156 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12158 pipe_config
->scaler_state
.scaler_users
,
12159 pipe_config
->scaler_state
.scaler_id
);
12160 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12161 pipe_config
->gmch_pfit
.control
,
12162 pipe_config
->gmch_pfit
.pgm_ratios
,
12163 pipe_config
->gmch_pfit
.lvds_border_bits
);
12164 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12165 pipe_config
->pch_pfit
.pos
,
12166 pipe_config
->pch_pfit
.size
,
12167 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12168 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12169 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12171 if (IS_BROXTON(dev
)) {
12172 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12173 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12174 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12175 pipe_config
->ddi_pll_sel
,
12176 pipe_config
->dpll_hw_state
.ebb0
,
12177 pipe_config
->dpll_hw_state
.pll0
,
12178 pipe_config
->dpll_hw_state
.pll1
,
12179 pipe_config
->dpll_hw_state
.pll2
,
12180 pipe_config
->dpll_hw_state
.pll3
,
12181 pipe_config
->dpll_hw_state
.pll6
,
12182 pipe_config
->dpll_hw_state
.pll8
,
12183 pipe_config
->dpll_hw_state
.pcsdw12
);
12184 } else if (IS_SKYLAKE(dev
)) {
12185 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12186 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12187 pipe_config
->ddi_pll_sel
,
12188 pipe_config
->dpll_hw_state
.ctrl1
,
12189 pipe_config
->dpll_hw_state
.cfgcr1
,
12190 pipe_config
->dpll_hw_state
.cfgcr2
);
12191 } else if (HAS_DDI(dev
)) {
12192 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12193 pipe_config
->ddi_pll_sel
,
12194 pipe_config
->dpll_hw_state
.wrpll
);
12196 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12197 "fp0: 0x%x, fp1: 0x%x\n",
12198 pipe_config
->dpll_hw_state
.dpll
,
12199 pipe_config
->dpll_hw_state
.dpll_md
,
12200 pipe_config
->dpll_hw_state
.fp0
,
12201 pipe_config
->dpll_hw_state
.fp1
);
12204 DRM_DEBUG_KMS("planes on this crtc\n");
12205 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12206 intel_plane
= to_intel_plane(plane
);
12207 if (intel_plane
->pipe
!= crtc
->pipe
)
12210 state
= to_intel_plane_state(plane
->state
);
12211 fb
= state
->base
.fb
;
12213 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12214 "disabled, scaler_id = %d\n",
12215 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12216 plane
->base
.id
, intel_plane
->pipe
,
12217 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12218 drm_plane_index(plane
), state
->scaler_id
);
12222 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12223 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12224 plane
->base
.id
, intel_plane
->pipe
,
12225 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12226 drm_plane_index(plane
));
12227 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12228 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12229 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12231 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12232 drm_rect_width(&state
->src
) >> 16,
12233 drm_rect_height(&state
->src
) >> 16,
12234 state
->dst
.x1
, state
->dst
.y1
,
12235 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12239 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12241 struct drm_device
*dev
= state
->dev
;
12242 struct intel_encoder
*encoder
;
12243 struct drm_connector
*connector
;
12244 struct drm_connector_state
*connector_state
;
12245 unsigned int used_ports
= 0;
12249 * Walk the connector list instead of the encoder
12250 * list to detect the problem on ddi platforms
12251 * where there's just one encoder per digital port.
12253 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12254 if (!connector_state
->best_encoder
)
12257 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12259 WARN_ON(!connector_state
->crtc
);
12261 switch (encoder
->type
) {
12262 unsigned int port_mask
;
12263 case INTEL_OUTPUT_UNKNOWN
:
12264 if (WARN_ON(!HAS_DDI(dev
)))
12266 case INTEL_OUTPUT_DISPLAYPORT
:
12267 case INTEL_OUTPUT_HDMI
:
12268 case INTEL_OUTPUT_EDP
:
12269 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12271 /* the same port mustn't appear more than once */
12272 if (used_ports
& port_mask
)
12275 used_ports
|= port_mask
;
12285 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12287 struct drm_crtc_state tmp_state
;
12288 struct intel_crtc_scaler_state scaler_state
;
12289 struct intel_dpll_hw_state dpll_hw_state
;
12290 enum intel_dpll_id shared_dpll
;
12291 uint32_t ddi_pll_sel
;
12293 /* FIXME: before the switch to atomic started, a new pipe_config was
12294 * kzalloc'd. Code that depends on any field being zero should be
12295 * fixed, so that the crtc_state can be safely duplicated. For now,
12296 * only fields that are know to not cause problems are preserved. */
12298 tmp_state
= crtc_state
->base
;
12299 scaler_state
= crtc_state
->scaler_state
;
12300 shared_dpll
= crtc_state
->shared_dpll
;
12301 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12302 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12304 memset(crtc_state
, 0, sizeof *crtc_state
);
12306 crtc_state
->base
= tmp_state
;
12307 crtc_state
->scaler_state
= scaler_state
;
12308 crtc_state
->shared_dpll
= shared_dpll
;
12309 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12310 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12314 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12315 struct intel_crtc_state
*pipe_config
)
12317 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12318 struct intel_encoder
*encoder
;
12319 struct drm_connector
*connector
;
12320 struct drm_connector_state
*connector_state
;
12321 int base_bpp
, ret
= -EINVAL
;
12325 clear_intel_crtc_state(pipe_config
);
12327 pipe_config
->cpu_transcoder
=
12328 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12331 * Sanitize sync polarity flags based on requested ones. If neither
12332 * positive or negative polarity is requested, treat this as meaning
12333 * negative polarity.
12335 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12336 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12337 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12339 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12340 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12341 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12343 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12344 * plane pixel format and any sink constraints into account. Returns the
12345 * source plane bpp so that dithering can be selected on mismatches
12346 * after encoders and crtc also have had their say. */
12347 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12353 * Determine the real pipe dimensions. Note that stereo modes can
12354 * increase the actual pipe size due to the frame doubling and
12355 * insertion of additional space for blanks between the frame. This
12356 * is stored in the crtc timings. We use the requested mode to do this
12357 * computation to clearly distinguish it from the adjusted mode, which
12358 * can be changed by the connectors in the below retry loop.
12360 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12361 &pipe_config
->pipe_src_w
,
12362 &pipe_config
->pipe_src_h
);
12365 /* Ensure the port clock defaults are reset when retrying. */
12366 pipe_config
->port_clock
= 0;
12367 pipe_config
->pixel_multiplier
= 1;
12369 /* Fill in default crtc timings, allow encoders to overwrite them. */
12370 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12371 CRTC_STEREO_DOUBLE
);
12373 /* Pass our mode to the connectors and the CRTC to give them a chance to
12374 * adjust it according to limitations or connector properties, and also
12375 * a chance to reject the mode entirely.
12377 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12378 if (connector_state
->crtc
!= crtc
)
12381 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12383 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12384 DRM_DEBUG_KMS("Encoder config failure\n");
12389 /* Set default port clock if not overwritten by the encoder. Needs to be
12390 * done afterwards in case the encoder adjusts the mode. */
12391 if (!pipe_config
->port_clock
)
12392 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12393 * pipe_config
->pixel_multiplier
;
12395 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12397 DRM_DEBUG_KMS("CRTC fixup failed\n");
12401 if (ret
== RETRY
) {
12402 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12407 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12409 goto encoder_retry
;
12412 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
12413 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12414 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12416 /* Check if we need to force a modeset */
12417 if (pipe_config
->has_audio
!=
12418 to_intel_crtc_state(crtc
->state
)->has_audio
) {
12419 pipe_config
->base
.mode_changed
= true;
12420 ret
= drm_atomic_add_affected_planes(state
, crtc
);
12424 * Note we have an issue here with infoframes: current code
12425 * only updates them on the full mode set path per hw
12426 * requirements. So here we should be checking for any
12427 * required changes and forcing a mode set.
12433 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
12435 struct drm_encoder
*encoder
;
12436 struct drm_device
*dev
= crtc
->dev
;
12438 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
12439 if (encoder
->crtc
== crtc
)
12446 intel_modeset_update_state(struct drm_atomic_state
*state
)
12448 struct drm_device
*dev
= state
->dev
;
12449 struct intel_encoder
*intel_encoder
;
12450 struct drm_crtc
*crtc
;
12451 struct drm_crtc_state
*crtc_state
;
12452 struct drm_connector
*connector
;
12454 intel_shared_dpll_commit(state
);
12456 for_each_intel_encoder(dev
, intel_encoder
) {
12457 if (!intel_encoder
->base
.crtc
)
12460 crtc
= intel_encoder
->base
.crtc
;
12461 crtc_state
= drm_atomic_get_existing_crtc_state(state
, crtc
);
12462 if (!crtc_state
|| !needs_modeset(crtc
->state
))
12465 intel_encoder
->connectors_active
= false;
12468 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
12469 intel_modeset_update_staged_output_state(state
->dev
);
12471 /* Double check state. */
12472 for_each_crtc(dev
, crtc
) {
12473 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
12475 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12477 /* Update hwmode for vblank functions */
12478 if (crtc
->state
->active
)
12479 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12481 crtc
->hwmode
.crtc_clock
= 0;
12484 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
12485 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
12488 crtc
= connector
->encoder
->crtc
;
12489 crtc_state
= drm_atomic_get_existing_crtc_state(state
, crtc
);
12490 if (!crtc_state
|| !needs_modeset(crtc
->state
))
12493 if (crtc
->state
->active
) {
12494 struct drm_property
*dpms_property
=
12495 dev
->mode_config
.dpms_property
;
12497 connector
->dpms
= DRM_MODE_DPMS_ON
;
12498 drm_object_property_set_value(&connector
->base
, dpms_property
, DRM_MODE_DPMS_ON
);
12500 intel_encoder
= to_intel_encoder(connector
->encoder
);
12501 intel_encoder
->connectors_active
= true;
12503 connector
->dpms
= DRM_MODE_DPMS_OFF
;
12507 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12511 if (clock1
== clock2
)
12514 if (!clock1
|| !clock2
)
12517 diff
= abs(clock1
- clock2
);
12519 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12525 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12526 list_for_each_entry((intel_crtc), \
12527 &(dev)->mode_config.crtc_list, \
12529 if (mask & (1 <<(intel_crtc)->pipe))
12532 intel_pipe_config_compare(struct drm_device
*dev
,
12533 struct intel_crtc_state
*current_config
,
12534 struct intel_crtc_state
*pipe_config
)
12536 #define PIPE_CONF_CHECK_X(name) \
12537 if (current_config->name != pipe_config->name) { \
12538 DRM_ERROR("mismatch in " #name " " \
12539 "(expected 0x%08x, found 0x%08x)\n", \
12540 current_config->name, \
12541 pipe_config->name); \
12545 #define PIPE_CONF_CHECK_I(name) \
12546 if (current_config->name != pipe_config->name) { \
12547 DRM_ERROR("mismatch in " #name " " \
12548 "(expected %i, found %i)\n", \
12549 current_config->name, \
12550 pipe_config->name); \
12554 /* This is required for BDW+ where there is only one set of registers for
12555 * switching between high and low RR.
12556 * This macro can be used whenever a comparison has to be made between one
12557 * hw state and multiple sw state variables.
12559 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12560 if ((current_config->name != pipe_config->name) && \
12561 (current_config->alt_name != pipe_config->name)) { \
12562 DRM_ERROR("mismatch in " #name " " \
12563 "(expected %i or %i, found %i)\n", \
12564 current_config->name, \
12565 current_config->alt_name, \
12566 pipe_config->name); \
12570 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12571 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12572 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12573 "(expected %i, found %i)\n", \
12574 current_config->name & (mask), \
12575 pipe_config->name & (mask)); \
12579 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12580 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12581 DRM_ERROR("mismatch in " #name " " \
12582 "(expected %i, found %i)\n", \
12583 current_config->name, \
12584 pipe_config->name); \
12588 #define PIPE_CONF_QUIRK(quirk) \
12589 ((current_config->quirks | pipe_config->quirks) & (quirk))
12591 PIPE_CONF_CHECK_I(cpu_transcoder
);
12593 PIPE_CONF_CHECK_I(has_pch_encoder
);
12594 PIPE_CONF_CHECK_I(fdi_lanes
);
12595 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
12596 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
12597 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
12598 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
12599 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
12601 PIPE_CONF_CHECK_I(has_dp_encoder
);
12603 if (INTEL_INFO(dev
)->gen
< 8) {
12604 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
12605 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
12606 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
12607 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
12608 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
12610 if (current_config
->has_drrs
) {
12611 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
12612 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
12613 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
12614 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
12615 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
12618 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
12619 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
12620 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
12621 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
12622 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
12625 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12626 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12627 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12628 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12629 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12630 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12632 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12633 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12634 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12635 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12636 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12637 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12639 PIPE_CONF_CHECK_I(pixel_multiplier
);
12640 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12641 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12642 IS_VALLEYVIEW(dev
))
12643 PIPE_CONF_CHECK_I(limited_color_range
);
12644 PIPE_CONF_CHECK_I(has_infoframe
);
12646 PIPE_CONF_CHECK_I(has_audio
);
12648 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12649 DRM_MODE_FLAG_INTERLACE
);
12651 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12652 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12653 DRM_MODE_FLAG_PHSYNC
);
12654 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12655 DRM_MODE_FLAG_NHSYNC
);
12656 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12657 DRM_MODE_FLAG_PVSYNC
);
12658 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12659 DRM_MODE_FLAG_NVSYNC
);
12662 PIPE_CONF_CHECK_I(pipe_src_w
);
12663 PIPE_CONF_CHECK_I(pipe_src_h
);
12666 * FIXME: BIOS likes to set up a cloned config with lvds+external
12667 * screen. Since we don't yet re-compute the pipe config when moving
12668 * just the lvds port away to another pipe the sw tracking won't match.
12670 * Proper atomic modesets with recomputed global state will fix this.
12671 * Until then just don't check gmch state for inherited modes.
12673 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
12674 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
12675 /* pfit ratios are autocomputed by the hw on gen4+ */
12676 if (INTEL_INFO(dev
)->gen
< 4)
12677 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12678 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
12681 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12682 if (current_config
->pch_pfit
.enabled
) {
12683 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
12684 PIPE_CONF_CHECK_I(pch_pfit
.size
);
12687 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12689 /* BDW+ don't expose a synchronous way to read the state */
12690 if (IS_HASWELL(dev
))
12691 PIPE_CONF_CHECK_I(ips_enabled
);
12693 PIPE_CONF_CHECK_I(double_wide
);
12695 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12697 PIPE_CONF_CHECK_I(shared_dpll
);
12698 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12699 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12700 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12701 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12702 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12703 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12704 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12705 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12707 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12708 PIPE_CONF_CHECK_I(pipe_bpp
);
12710 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12711 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12713 #undef PIPE_CONF_CHECK_X
12714 #undef PIPE_CONF_CHECK_I
12715 #undef PIPE_CONF_CHECK_I_ALT
12716 #undef PIPE_CONF_CHECK_FLAGS
12717 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12718 #undef PIPE_CONF_QUIRK
12723 static void check_wm_state(struct drm_device
*dev
)
12725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12726 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12727 struct intel_crtc
*intel_crtc
;
12730 if (INTEL_INFO(dev
)->gen
< 9)
12733 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12734 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12736 for_each_intel_crtc(dev
, intel_crtc
) {
12737 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12738 const enum pipe pipe
= intel_crtc
->pipe
;
12740 if (!intel_crtc
->active
)
12744 for_each_plane(dev_priv
, pipe
, plane
) {
12745 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12746 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12748 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12751 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12752 "(expected (%u,%u), found (%u,%u))\n",
12753 pipe_name(pipe
), plane
+ 1,
12754 sw_entry
->start
, sw_entry
->end
,
12755 hw_entry
->start
, hw_entry
->end
);
12759 hw_entry
= &hw_ddb
.cursor
[pipe
];
12760 sw_entry
= &sw_ddb
->cursor
[pipe
];
12762 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12765 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12766 "(expected (%u,%u), found (%u,%u))\n",
12768 sw_entry
->start
, sw_entry
->end
,
12769 hw_entry
->start
, hw_entry
->end
);
12774 check_connector_state(struct drm_device
*dev
)
12776 struct intel_connector
*connector
;
12778 for_each_intel_connector(dev
, connector
) {
12779 /* This also checks the encoder/connector hw state with the
12780 * ->get_hw_state callbacks. */
12781 intel_connector_check_state(connector
);
12783 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
12784 "connector's staged encoder doesn't match current encoder\n");
12789 check_encoder_state(struct drm_device
*dev
)
12791 struct intel_encoder
*encoder
;
12792 struct intel_connector
*connector
;
12794 for_each_intel_encoder(dev
, encoder
) {
12795 bool enabled
= false;
12796 bool active
= false;
12797 enum pipe pipe
, tracked_pipe
;
12799 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12800 encoder
->base
.base
.id
,
12801 encoder
->base
.name
);
12803 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
12804 "encoder's stage crtc doesn't match current crtc\n");
12805 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
12806 "encoder's active_connectors set, but no crtc\n");
12808 for_each_intel_connector(dev
, connector
) {
12809 if (connector
->base
.encoder
!= &encoder
->base
)
12812 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
12816 * for MST connectors if we unplug the connector is gone
12817 * away but the encoder is still connected to a crtc
12818 * until a modeset happens in response to the hotplug.
12820 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
12823 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12824 "encoder's enabled state mismatch "
12825 "(expected %i, found %i)\n",
12826 !!encoder
->base
.crtc
, enabled
);
12827 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
12828 "active encoder with no crtc\n");
12830 I915_STATE_WARN(encoder
->connectors_active
!= active
,
12831 "encoder's computed active state doesn't match tracked active state "
12832 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
12834 active
= encoder
->get_hw_state(encoder
, &pipe
);
12835 I915_STATE_WARN(active
!= encoder
->connectors_active
,
12836 "encoder's hw state doesn't match sw tracking "
12837 "(expected %i, found %i)\n",
12838 encoder
->connectors_active
, active
);
12840 if (!encoder
->base
.crtc
)
12843 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
12844 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
12845 "active encoder's pipe doesn't match"
12846 "(expected %i, found %i)\n",
12847 tracked_pipe
, pipe
);
12853 check_crtc_state(struct drm_device
*dev
)
12855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12856 struct intel_crtc
*crtc
;
12857 struct intel_encoder
*encoder
;
12858 struct intel_crtc_state pipe_config
;
12860 for_each_intel_crtc(dev
, crtc
) {
12861 bool enabled
= false;
12862 bool active
= false;
12864 memset(&pipe_config
, 0, sizeof(pipe_config
));
12866 DRM_DEBUG_KMS("[CRTC:%d]\n",
12867 crtc
->base
.base
.id
);
12869 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
12870 "active crtc, but not enabled in sw tracking\n");
12872 for_each_intel_encoder(dev
, encoder
) {
12873 if (encoder
->base
.crtc
!= &crtc
->base
)
12876 if (encoder
->connectors_active
)
12880 I915_STATE_WARN(active
!= crtc
->active
,
12881 "crtc's computed active state doesn't match tracked active state "
12882 "(expected %i, found %i)\n", active
, crtc
->active
);
12883 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
12884 "crtc's computed enabled state doesn't match tracked enabled state "
12885 "(expected %i, found %i)\n", enabled
,
12886 crtc
->base
.state
->enable
);
12888 active
= dev_priv
->display
.get_pipe_config(crtc
,
12891 /* hw state is inconsistent with the pipe quirk */
12892 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12893 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12894 active
= crtc
->active
;
12896 for_each_intel_encoder(dev
, encoder
) {
12898 if (encoder
->base
.crtc
!= &crtc
->base
)
12900 if (encoder
->get_hw_state(encoder
, &pipe
))
12901 encoder
->get_config(encoder
, &pipe_config
);
12904 I915_STATE_WARN(crtc
->active
!= active
,
12905 "crtc active state doesn't match with hw state "
12906 "(expected %i, found %i)\n", crtc
->active
, active
);
12908 I915_STATE_WARN(crtc
->active
!= crtc
->base
.state
->active
,
12909 "transitional active state does not match atomic hw state "
12910 "(expected %i, found %i)\n", crtc
->base
.state
->active
, crtc
->active
);
12913 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12914 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12915 intel_dump_pipe_config(crtc
, &pipe_config
,
12917 intel_dump_pipe_config(crtc
, crtc
->config
,
12924 check_shared_dpll_state(struct drm_device
*dev
)
12926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12927 struct intel_crtc
*crtc
;
12928 struct intel_dpll_hw_state dpll_hw_state
;
12931 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12932 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12933 int enabled_crtcs
= 0, active_crtcs
= 0;
12936 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12938 DRM_DEBUG_KMS("%s\n", pll
->name
);
12940 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12942 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12943 "more active pll users than references: %i vs %i\n",
12944 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12945 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12946 "pll in active use but not on in sw tracking\n");
12947 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12948 "pll in on but not on in use in sw tracking\n");
12949 I915_STATE_WARN(pll
->on
!= active
,
12950 "pll on state mismatch (expected %i, found %i)\n",
12953 for_each_intel_crtc(dev
, crtc
) {
12954 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12956 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12959 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12960 "pll active crtcs mismatch (expected %i, found %i)\n",
12961 pll
->active
, active_crtcs
);
12962 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12963 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12964 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12966 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12967 sizeof(dpll_hw_state
)),
12968 "pll hw state mismatch\n");
12973 intel_modeset_check_state(struct drm_device
*dev
)
12975 check_wm_state(dev
);
12976 check_connector_state(dev
);
12977 check_encoder_state(dev
);
12978 check_crtc_state(dev
);
12979 check_shared_dpll_state(dev
);
12982 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12986 * FDI already provided one idea for the dotclock.
12987 * Yell if the encoder disagrees.
12989 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12990 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12991 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12994 static void update_scanline_offset(struct intel_crtc
*crtc
)
12996 struct drm_device
*dev
= crtc
->base
.dev
;
12999 * The scanline counter increments at the leading edge of hsync.
13001 * On most platforms it starts counting from vtotal-1 on the
13002 * first active line. That means the scanline counter value is
13003 * always one less than what we would expect. Ie. just after
13004 * start of vblank, which also occurs at start of hsync (on the
13005 * last active line), the scanline counter will read vblank_start-1.
13007 * On gen2 the scanline counter starts counting from 1 instead
13008 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13009 * to keep the value positive), instead of adding one.
13011 * On HSW+ the behaviour of the scanline counter depends on the output
13012 * type. For DP ports it behaves like most other platforms, but on HDMI
13013 * there's an extra 1 line difference. So we need to add two instead of
13014 * one to the value.
13016 if (IS_GEN2(dev
)) {
13017 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
13020 vtotal
= mode
->crtc_vtotal
;
13021 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
13024 crtc
->scanline_offset
= vtotal
- 1;
13025 } else if (HAS_DDI(dev
) &&
13026 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
13027 crtc
->scanline_offset
= 2;
13029 crtc
->scanline_offset
= 1;
13032 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
13034 struct drm_device
*dev
= state
->dev
;
13035 struct drm_i915_private
*dev_priv
= to_i915(dev
);
13036 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
13037 struct intel_crtc
*intel_crtc
;
13038 struct intel_crtc_state
*intel_crtc_state
;
13039 struct drm_crtc
*crtc
;
13040 struct drm_crtc_state
*crtc_state
;
13043 if (!dev_priv
->display
.crtc_compute_clock
)
13046 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13049 intel_crtc
= to_intel_crtc(crtc
);
13050 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
13051 dpll
= intel_crtc_state
->shared_dpll
;
13053 if (!needs_modeset(crtc_state
) || dpll
== DPLL_ID_PRIVATE
)
13056 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
13059 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
13061 shared_dpll
[dpll
].crtc_mask
&= ~(1 << intel_crtc
->pipe
);
13066 * This implements the workaround described in the "notes" section of the mode
13067 * set sequence documentation. When going from no pipes or single pipe to
13068 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13069 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13071 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
13073 struct drm_crtc_state
*crtc_state
;
13074 struct intel_crtc
*intel_crtc
;
13075 struct drm_crtc
*crtc
;
13076 struct intel_crtc_state
*first_crtc_state
= NULL
;
13077 struct intel_crtc_state
*other_crtc_state
= NULL
;
13078 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
13081 /* look at all crtc's that are going to be enabled in during modeset */
13082 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13083 intel_crtc
= to_intel_crtc(crtc
);
13085 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
13088 if (first_crtc_state
) {
13089 other_crtc_state
= to_intel_crtc_state(crtc_state
);
13092 first_crtc_state
= to_intel_crtc_state(crtc_state
);
13093 first_pipe
= intel_crtc
->pipe
;
13097 /* No workaround needed? */
13098 if (!first_crtc_state
)
13101 /* w/a possibly needed, check how many crtc's are already enabled. */
13102 for_each_intel_crtc(state
->dev
, intel_crtc
) {
13103 struct intel_crtc_state
*pipe_config
;
13105 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13106 if (IS_ERR(pipe_config
))
13107 return PTR_ERR(pipe_config
);
13109 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
13111 if (!pipe_config
->base
.active
||
13112 needs_modeset(&pipe_config
->base
))
13115 /* 2 or more enabled crtcs means no need for w/a */
13116 if (enabled_pipe
!= INVALID_PIPE
)
13119 enabled_pipe
= intel_crtc
->pipe
;
13122 if (enabled_pipe
!= INVALID_PIPE
)
13123 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
13124 else if (other_crtc_state
)
13125 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13130 /* Code that should eventually be part of atomic_check() */
13131 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13133 struct drm_device
*dev
= state
->dev
;
13136 if (!check_digital_port_conflicts(state
)) {
13137 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13142 * See if the config requires any additional preparation, e.g.
13143 * to adjust global state with pipes off. We need to do this
13144 * here so we can get the modeset_pipe updated config for the new
13145 * mode set on this crtc. For other crtcs we need to use the
13146 * adjusted_mode bits in the crtc directly.
13148 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
) || IS_BROADWELL(dev
)) {
13149 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
))
13150 ret
= valleyview_modeset_global_pipes(state
);
13152 ret
= broadwell_modeset_global_pipes(state
);
13158 intel_modeset_clear_plls(state
);
13160 if (IS_HASWELL(dev
))
13161 return haswell_mode_set_planes_workaround(state
);
13167 intel_modeset_compute_config(struct drm_atomic_state
*state
)
13169 struct drm_crtc
*crtc
;
13170 struct drm_crtc_state
*crtc_state
;
13173 ret
= drm_atomic_helper_check_modeset(state
->dev
, state
);
13177 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13178 if (!crtc_state
->enable
&&
13179 WARN_ON(crtc_state
->active
))
13180 crtc_state
->active
= false;
13182 if (!crtc_state
->enable
)
13185 if (!needs_modeset(crtc_state
)) {
13186 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13191 ret
= intel_modeset_pipe_config(crtc
,
13192 to_intel_crtc_state(crtc_state
));
13196 intel_dump_pipe_config(to_intel_crtc(crtc
),
13197 to_intel_crtc_state(crtc_state
),
13201 ret
= intel_modeset_checks(state
);
13205 return drm_atomic_helper_check_planes(state
->dev
, state
);
13208 static int __intel_set_mode(struct drm_atomic_state
*state
)
13210 struct drm_device
*dev
= state
->dev
;
13211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13212 struct drm_crtc
*crtc
;
13213 struct drm_crtc_state
*crtc_state
;
13217 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13221 drm_atomic_helper_swap_state(dev
, state
);
13223 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13224 if (!needs_modeset(crtc
->state
) || !crtc_state
->active
)
13227 intel_crtc_disable_planes(crtc
);
13228 dev_priv
->display
.crtc_disable(crtc
);
13231 /* Only after disabling all output pipelines that will be changed can we
13232 * update the the output configuration. */
13233 intel_modeset_update_state(state
);
13235 /* The state has been swaped above, so state actually contains the
13236 * old state now. */
13238 modeset_update_crtc_power_domains(state
);
13240 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13241 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13242 drm_atomic_helper_commit_planes_on_crtc(crtc_state
);
13244 if (!needs_modeset(crtc
->state
) || !crtc
->state
->active
)
13247 update_scanline_offset(to_intel_crtc(crtc
));
13249 dev_priv
->display
.crtc_enable(crtc
);
13250 intel_crtc_enable_planes(crtc
);
13253 /* FIXME: add subpixel order */
13255 drm_atomic_helper_cleanup_planes(dev
, state
);
13257 drm_atomic_state_free(state
);
13262 static int intel_set_mode_checked(struct drm_atomic_state
*state
)
13264 struct drm_device
*dev
= state
->dev
;
13267 ret
= __intel_set_mode(state
);
13269 intel_modeset_check_state(dev
);
13274 static int intel_set_mode(struct drm_atomic_state
*state
)
13278 ret
= intel_modeset_compute_config(state
);
13282 return intel_set_mode_checked(state
);
13285 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13287 struct drm_device
*dev
= crtc
->dev
;
13288 struct drm_atomic_state
*state
;
13289 struct intel_crtc
*intel_crtc
;
13290 struct intel_encoder
*encoder
;
13291 struct intel_connector
*connector
;
13292 struct drm_connector_state
*connector_state
;
13293 struct intel_crtc_state
*crtc_state
;
13296 state
= drm_atomic_state_alloc(dev
);
13298 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13303 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
13305 /* The force restore path in the HW readout code relies on the staged
13306 * config still keeping the user requested config while the actual
13307 * state has been overwritten by the configuration read from HW. We
13308 * need to copy the staged config to the atomic state, otherwise the
13309 * mode set will just reapply the state the HW is already in. */
13310 for_each_intel_encoder(dev
, encoder
) {
13311 if (&encoder
->new_crtc
->base
!= crtc
)
13314 for_each_intel_connector(dev
, connector
) {
13315 if (connector
->new_encoder
!= encoder
)
13318 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
13319 if (IS_ERR(connector_state
)) {
13320 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13321 connector
->base
.base
.id
,
13322 connector
->base
.name
,
13323 PTR_ERR(connector_state
));
13327 connector_state
->crtc
= crtc
;
13328 connector_state
->best_encoder
= &encoder
->base
;
13332 for_each_intel_crtc(dev
, intel_crtc
) {
13333 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
13336 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
13337 if (IS_ERR(crtc_state
)) {
13338 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13339 intel_crtc
->base
.base
.id
,
13340 PTR_ERR(crtc_state
));
13344 crtc_state
->base
.active
= crtc_state
->base
.enable
=
13345 intel_crtc
->new_enabled
;
13347 if (&intel_crtc
->base
== crtc
)
13348 drm_mode_copy(&crtc_state
->base
.mode
, &crtc
->mode
);
13351 intel_modeset_setup_plane_state(state
, crtc
, &crtc
->mode
,
13352 crtc
->primary
->fb
, crtc
->x
, crtc
->y
);
13354 ret
= intel_set_mode(state
);
13356 drm_atomic_state_free(state
);
13359 #undef for_each_intel_crtc_masked
13361 static bool intel_connector_in_mode_set(struct intel_connector
*connector
,
13362 struct drm_mode_set
*set
)
13366 for (ro
= 0; ro
< set
->num_connectors
; ro
++)
13367 if (set
->connectors
[ro
] == &connector
->base
)
13374 intel_modeset_stage_output_state(struct drm_device
*dev
,
13375 struct drm_mode_set
*set
,
13376 struct drm_atomic_state
*state
)
13378 struct intel_connector
*connector
;
13379 struct drm_connector
*drm_connector
;
13380 struct drm_connector_state
*connector_state
;
13381 struct drm_crtc
*crtc
;
13382 struct drm_crtc_state
*crtc_state
;
13385 /* The upper layers ensure that we either disable a crtc or have a list
13386 * of connectors. For paranoia, double-check this. */
13387 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
13388 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
13390 for_each_intel_connector(dev
, connector
) {
13391 bool in_mode_set
= intel_connector_in_mode_set(connector
, set
);
13393 if (!in_mode_set
&& connector
->base
.state
->crtc
!= set
->crtc
)
13397 drm_atomic_get_connector_state(state
, &connector
->base
);
13398 if (IS_ERR(connector_state
))
13399 return PTR_ERR(connector_state
);
13402 int pipe
= to_intel_crtc(set
->crtc
)->pipe
;
13403 connector_state
->best_encoder
=
13404 &intel_find_encoder(connector
, pipe
)->base
;
13407 if (connector
->base
.state
->crtc
!= set
->crtc
)
13410 /* If we disable the crtc, disable all its connectors. Also, if
13411 * the connector is on the changing crtc but not on the new
13412 * connector list, disable it. */
13413 if (!set
->fb
|| !in_mode_set
) {
13414 connector_state
->best_encoder
= NULL
;
13416 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13417 connector
->base
.base
.id
,
13418 connector
->base
.name
);
13421 /* connector->new_encoder is now updated for all connectors. */
13423 for_each_connector_in_state(state
, drm_connector
, connector_state
, i
) {
13424 connector
= to_intel_connector(drm_connector
);
13426 if (!connector_state
->best_encoder
) {
13427 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
13435 if (intel_connector_in_mode_set(connector
, set
)) {
13436 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
13438 /* If this connector was in a previous crtc, add it
13439 * to the state. We might need to disable it. */
13442 drm_atomic_get_crtc_state(state
, crtc
);
13443 if (IS_ERR(crtc_state
))
13444 return PTR_ERR(crtc_state
);
13447 ret
= drm_atomic_set_crtc_for_connector(connector_state
,
13453 /* Make sure the new CRTC will work with the encoder */
13454 if (!drm_encoder_crtc_ok(connector_state
->best_encoder
,
13455 connector_state
->crtc
)) {
13459 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13460 connector
->base
.base
.id
,
13461 connector
->base
.name
,
13462 connector_state
->crtc
->base
.id
);
13464 if (connector_state
->best_encoder
!= &connector
->encoder
->base
)
13465 connector
->encoder
=
13466 to_intel_encoder(connector_state
->best_encoder
);
13469 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13470 bool has_connectors
;
13472 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13476 has_connectors
= !!drm_atomic_connectors_for_crtc(state
, crtc
);
13477 if (has_connectors
!= crtc_state
->enable
)
13478 crtc_state
->enable
=
13479 crtc_state
->active
= has_connectors
;
13482 ret
= intel_modeset_setup_plane_state(state
, set
->crtc
, set
->mode
,
13483 set
->fb
, set
->x
, set
->y
);
13487 crtc_state
= drm_atomic_get_crtc_state(state
, set
->crtc
);
13488 if (IS_ERR(crtc_state
))
13489 return PTR_ERR(crtc_state
);
13491 ret
= drm_atomic_set_mode_for_crtc(crtc_state
, set
->mode
);
13495 if (set
->num_connectors
)
13496 crtc_state
->active
= true;
13501 static int intel_crtc_set_config(struct drm_mode_set
*set
)
13503 struct drm_device
*dev
;
13504 struct drm_atomic_state
*state
= NULL
;
13508 BUG_ON(!set
->crtc
);
13509 BUG_ON(!set
->crtc
->helper_private
);
13511 /* Enforce sane interface api - has been abused by the fb helper. */
13512 BUG_ON(!set
->mode
&& set
->fb
);
13513 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
13516 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13517 set
->crtc
->base
.id
, set
->fb
->base
.id
,
13518 (int)set
->num_connectors
, set
->x
, set
->y
);
13520 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
13523 dev
= set
->crtc
->dev
;
13525 state
= drm_atomic_state_alloc(dev
);
13529 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
13531 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
13535 ret
= intel_modeset_compute_config(state
);
13539 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
13541 ret
= intel_set_mode_checked(state
);
13543 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13544 set
->crtc
->base
.id
, ret
);
13549 drm_atomic_state_free(state
);
13553 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13554 .gamma_set
= intel_crtc_gamma_set
,
13555 .set_config
= intel_crtc_set_config
,
13556 .destroy
= intel_crtc_destroy
,
13557 .page_flip
= intel_crtc_page_flip
,
13558 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13559 .atomic_destroy_state
= intel_crtc_destroy_state
,
13562 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13563 struct intel_shared_dpll
*pll
,
13564 struct intel_dpll_hw_state
*hw_state
)
13568 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13571 val
= I915_READ(PCH_DPLL(pll
->id
));
13572 hw_state
->dpll
= val
;
13573 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13574 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13576 return val
& DPLL_VCO_ENABLE
;
13579 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13580 struct intel_shared_dpll
*pll
)
13582 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13583 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13586 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13587 struct intel_shared_dpll
*pll
)
13589 /* PCH refclock must be enabled first */
13590 ibx_assert_pch_refclk_enabled(dev_priv
);
13592 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13594 /* Wait for the clocks to stabilize. */
13595 POSTING_READ(PCH_DPLL(pll
->id
));
13598 /* The pixel multiplier can only be updated once the
13599 * DPLL is enabled and the clocks are stable.
13601 * So write it again.
13603 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13604 POSTING_READ(PCH_DPLL(pll
->id
));
13608 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13609 struct intel_shared_dpll
*pll
)
13611 struct drm_device
*dev
= dev_priv
->dev
;
13612 struct intel_crtc
*crtc
;
13614 /* Make sure no transcoder isn't still depending on us. */
13615 for_each_intel_crtc(dev
, crtc
) {
13616 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13617 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13620 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13621 POSTING_READ(PCH_DPLL(pll
->id
));
13625 static char *ibx_pch_dpll_names
[] = {
13630 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13635 dev_priv
->num_shared_dpll
= 2;
13637 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13638 dev_priv
->shared_dplls
[i
].id
= i
;
13639 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13640 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13641 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13642 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13643 dev_priv
->shared_dplls
[i
].get_hw_state
=
13644 ibx_pch_dpll_get_hw_state
;
13648 static void intel_shared_dpll_init(struct drm_device
*dev
)
13650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13652 intel_update_cdclk(dev
);
13655 intel_ddi_pll_init(dev
);
13656 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13657 ibx_pch_dpll_init(dev
);
13659 dev_priv
->num_shared_dpll
= 0;
13661 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13665 * intel_prepare_plane_fb - Prepare fb for usage on plane
13666 * @plane: drm plane to prepare for
13667 * @fb: framebuffer to prepare for presentation
13669 * Prepares a framebuffer for usage on a display plane. Generally this
13670 * involves pinning the underlying object and updating the frontbuffer tracking
13671 * bits. Some older platforms need special physical address handling for
13674 * Returns 0 on success, negative error code on failure.
13677 intel_prepare_plane_fb(struct drm_plane
*plane
,
13678 struct drm_framebuffer
*fb
,
13679 const struct drm_plane_state
*new_state
)
13681 struct drm_device
*dev
= plane
->dev
;
13682 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13683 enum pipe pipe
= intel_plane
->pipe
;
13684 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13685 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13686 unsigned frontbuffer_bits
= 0;
13692 switch (plane
->type
) {
13693 case DRM_PLANE_TYPE_PRIMARY
:
13694 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13696 case DRM_PLANE_TYPE_CURSOR
:
13697 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13699 case DRM_PLANE_TYPE_OVERLAY
:
13700 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
13704 mutex_lock(&dev
->struct_mutex
);
13706 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13707 INTEL_INFO(dev
)->cursor_needs_physical
) {
13708 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13709 ret
= i915_gem_object_attach_phys(obj
, align
);
13711 DRM_DEBUG_KMS("failed to attach phys object\n");
13713 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
13717 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
13719 mutex_unlock(&dev
->struct_mutex
);
13725 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13726 * @plane: drm plane to clean up for
13727 * @fb: old framebuffer that was on plane
13729 * Cleans up a framebuffer that has just been removed from a plane.
13732 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13733 struct drm_framebuffer
*fb
,
13734 const struct drm_plane_state
*old_state
)
13736 struct drm_device
*dev
= plane
->dev
;
13737 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13742 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13743 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13744 mutex_lock(&dev
->struct_mutex
);
13745 intel_unpin_fb_obj(fb
, old_state
);
13746 mutex_unlock(&dev
->struct_mutex
);
13751 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13754 struct drm_device
*dev
;
13755 struct drm_i915_private
*dev_priv
;
13756 int crtc_clock
, cdclk
;
13758 if (!intel_crtc
|| !crtc_state
)
13759 return DRM_PLANE_HELPER_NO_SCALING
;
13761 dev
= intel_crtc
->base
.dev
;
13762 dev_priv
= dev
->dev_private
;
13763 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13764 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13766 if (!crtc_clock
|| !cdclk
)
13767 return DRM_PLANE_HELPER_NO_SCALING
;
13770 * skl max scale is lower of:
13771 * close to 3 but not 3, -1 is for that purpose
13775 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13781 intel_check_primary_plane(struct drm_plane
*plane
,
13782 struct intel_crtc_state
*crtc_state
,
13783 struct intel_plane_state
*state
)
13785 struct drm_crtc
*crtc
= state
->base
.crtc
;
13786 struct drm_framebuffer
*fb
= state
->base
.fb
;
13787 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13788 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13789 bool can_position
= false;
13791 /* use scaler when colorkey is not required */
13792 if (INTEL_INFO(plane
->dev
)->gen
>= 9 &&
13793 to_intel_plane(plane
)->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13795 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13796 can_position
= true;
13799 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13800 &state
->dst
, &state
->clip
,
13801 min_scale
, max_scale
,
13802 can_position
, true,
13807 intel_commit_primary_plane(struct drm_plane
*plane
,
13808 struct intel_plane_state
*state
)
13810 struct drm_crtc
*crtc
= state
->base
.crtc
;
13811 struct drm_framebuffer
*fb
= state
->base
.fb
;
13812 struct drm_device
*dev
= plane
->dev
;
13813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13814 struct intel_crtc
*intel_crtc
;
13815 struct drm_rect
*src
= &state
->src
;
13817 crtc
= crtc
? crtc
: plane
->crtc
;
13818 intel_crtc
= to_intel_crtc(crtc
);
13821 crtc
->x
= src
->x1
>> 16;
13822 crtc
->y
= src
->y1
>> 16;
13824 if (!intel_crtc
->active
)
13827 if (state
->visible
)
13828 /* FIXME: kill this fastboot hack */
13829 intel_update_pipe_size(intel_crtc
);
13831 dev_priv
->display
.update_primary_plane(crtc
, fb
, crtc
->x
, crtc
->y
);
13835 intel_disable_primary_plane(struct drm_plane
*plane
,
13836 struct drm_crtc
*crtc
)
13838 struct drm_device
*dev
= plane
->dev
;
13839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13841 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13844 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13846 struct drm_device
*dev
= crtc
->dev
;
13847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13850 intel_pre_plane_update(intel_crtc
);
13852 if (intel_crtc
->atomic
.update_wm
)
13853 intel_update_watermarks(crtc
);
13855 intel_runtime_pm_get(dev_priv
);
13857 /* Perform vblank evasion around commit operation */
13858 if (crtc
->state
->active
&& !needs_modeset(crtc
->state
))
13859 intel_crtc
->atomic
.evade
=
13860 intel_pipe_update_start(intel_crtc
,
13861 &intel_crtc
->atomic
.start_vbl_count
);
13863 if (!needs_modeset(crtc
->state
) && INTEL_INFO(dev
)->gen
>= 9)
13864 skl_detach_scalers(intel_crtc
);
13867 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13869 struct drm_device
*dev
= crtc
->dev
;
13870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13873 if (intel_crtc
->atomic
.evade
)
13874 intel_pipe_update_end(intel_crtc
,
13875 intel_crtc
->atomic
.start_vbl_count
);
13877 intel_runtime_pm_put(dev_priv
);
13879 intel_post_plane_update(intel_crtc
);
13883 * intel_plane_destroy - destroy a plane
13884 * @plane: plane to destroy
13886 * Common destruction function for all types of planes (primary, cursor,
13889 void intel_plane_destroy(struct drm_plane
*plane
)
13891 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13892 drm_plane_cleanup(plane
);
13893 kfree(intel_plane
);
13896 const struct drm_plane_funcs intel_plane_funcs
= {
13897 .update_plane
= drm_atomic_helper_update_plane
,
13898 .disable_plane
= drm_atomic_helper_disable_plane
,
13899 .destroy
= intel_plane_destroy
,
13900 .set_property
= drm_atomic_helper_plane_set_property
,
13901 .atomic_get_property
= intel_plane_atomic_get_property
,
13902 .atomic_set_property
= intel_plane_atomic_set_property
,
13903 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13904 .atomic_destroy_state
= intel_plane_destroy_state
,
13908 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13911 struct intel_plane
*primary
;
13912 struct intel_plane_state
*state
;
13913 const uint32_t *intel_primary_formats
;
13916 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13917 if (primary
== NULL
)
13920 state
= intel_create_plane_state(&primary
->base
);
13925 primary
->base
.state
= &state
->base
;
13927 primary
->can_scale
= false;
13928 primary
->max_downscale
= 1;
13929 if (INTEL_INFO(dev
)->gen
>= 9) {
13930 primary
->can_scale
= true;
13931 state
->scaler_id
= -1;
13933 primary
->pipe
= pipe
;
13934 primary
->plane
= pipe
;
13935 primary
->check_plane
= intel_check_primary_plane
;
13936 primary
->commit_plane
= intel_commit_primary_plane
;
13937 primary
->disable_plane
= intel_disable_primary_plane
;
13938 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13939 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13940 primary
->plane
= !pipe
;
13942 if (INTEL_INFO(dev
)->gen
>= 9) {
13943 intel_primary_formats
= skl_primary_formats
;
13944 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13945 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13946 intel_primary_formats
= i965_primary_formats
;
13947 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13949 intel_primary_formats
= i8xx_primary_formats
;
13950 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13953 drm_universal_plane_init(dev
, &primary
->base
, 0,
13954 &intel_plane_funcs
,
13955 intel_primary_formats
, num_formats
,
13956 DRM_PLANE_TYPE_PRIMARY
);
13958 if (INTEL_INFO(dev
)->gen
>= 4)
13959 intel_create_rotation_property(dev
, primary
);
13961 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13963 return &primary
->base
;
13966 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13968 if (!dev
->mode_config
.rotation_property
) {
13969 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13970 BIT(DRM_ROTATE_180
);
13972 if (INTEL_INFO(dev
)->gen
>= 9)
13973 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13975 dev
->mode_config
.rotation_property
=
13976 drm_mode_create_rotation_property(dev
, flags
);
13978 if (dev
->mode_config
.rotation_property
)
13979 drm_object_attach_property(&plane
->base
.base
,
13980 dev
->mode_config
.rotation_property
,
13981 plane
->base
.state
->rotation
);
13985 intel_check_cursor_plane(struct drm_plane
*plane
,
13986 struct intel_crtc_state
*crtc_state
,
13987 struct intel_plane_state
*state
)
13989 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
13990 struct drm_framebuffer
*fb
= state
->base
.fb
;
13991 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13995 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13996 &state
->dst
, &state
->clip
,
13997 DRM_PLANE_HELPER_NO_SCALING
,
13998 DRM_PLANE_HELPER_NO_SCALING
,
13999 true, true, &state
->visible
);
14003 /* if we want to turn off the cursor ignore width and height */
14007 /* Check for which cursor types we support */
14008 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
14009 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14010 state
->base
.crtc_w
, state
->base
.crtc_h
);
14014 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
14015 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
14016 DRM_DEBUG_KMS("buffer is too small\n");
14020 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
14021 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14029 intel_disable_cursor_plane(struct drm_plane
*plane
,
14030 struct drm_crtc
*crtc
)
14032 intel_crtc_update_cursor(crtc
, false);
14036 intel_commit_cursor_plane(struct drm_plane
*plane
,
14037 struct intel_plane_state
*state
)
14039 struct drm_crtc
*crtc
= state
->base
.crtc
;
14040 struct drm_device
*dev
= plane
->dev
;
14041 struct intel_crtc
*intel_crtc
;
14042 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
14045 crtc
= crtc
? crtc
: plane
->crtc
;
14046 intel_crtc
= to_intel_crtc(crtc
);
14048 plane
->fb
= state
->base
.fb
;
14049 crtc
->cursor_x
= state
->base
.crtc_x
;
14050 crtc
->cursor_y
= state
->base
.crtc_y
;
14052 if (intel_crtc
->cursor_bo
== obj
)
14057 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
14058 addr
= i915_gem_obj_ggtt_offset(obj
);
14060 addr
= obj
->phys_handle
->busaddr
;
14062 intel_crtc
->cursor_addr
= addr
;
14063 intel_crtc
->cursor_bo
= obj
;
14066 if (intel_crtc
->active
)
14067 intel_crtc_update_cursor(crtc
, state
->visible
);
14070 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
14073 struct intel_plane
*cursor
;
14074 struct intel_plane_state
*state
;
14076 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
14077 if (cursor
== NULL
)
14080 state
= intel_create_plane_state(&cursor
->base
);
14085 cursor
->base
.state
= &state
->base
;
14087 cursor
->can_scale
= false;
14088 cursor
->max_downscale
= 1;
14089 cursor
->pipe
= pipe
;
14090 cursor
->plane
= pipe
;
14091 cursor
->check_plane
= intel_check_cursor_plane
;
14092 cursor
->commit_plane
= intel_commit_cursor_plane
;
14093 cursor
->disable_plane
= intel_disable_cursor_plane
;
14095 drm_universal_plane_init(dev
, &cursor
->base
, 0,
14096 &intel_plane_funcs
,
14097 intel_cursor_formats
,
14098 ARRAY_SIZE(intel_cursor_formats
),
14099 DRM_PLANE_TYPE_CURSOR
);
14101 if (INTEL_INFO(dev
)->gen
>= 4) {
14102 if (!dev
->mode_config
.rotation_property
)
14103 dev
->mode_config
.rotation_property
=
14104 drm_mode_create_rotation_property(dev
,
14105 BIT(DRM_ROTATE_0
) |
14106 BIT(DRM_ROTATE_180
));
14107 if (dev
->mode_config
.rotation_property
)
14108 drm_object_attach_property(&cursor
->base
.base
,
14109 dev
->mode_config
.rotation_property
,
14110 state
->base
.rotation
);
14113 if (INTEL_INFO(dev
)->gen
>=9)
14114 state
->scaler_id
= -1;
14116 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
14118 return &cursor
->base
;
14121 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
14122 struct intel_crtc_state
*crtc_state
)
14125 struct intel_scaler
*intel_scaler
;
14126 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
14128 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
14129 intel_scaler
= &scaler_state
->scalers
[i
];
14130 intel_scaler
->in_use
= 0;
14131 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
14134 scaler_state
->scaler_id
= -1;
14137 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
14139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14140 struct intel_crtc
*intel_crtc
;
14141 struct intel_crtc_state
*crtc_state
= NULL
;
14142 struct drm_plane
*primary
= NULL
;
14143 struct drm_plane
*cursor
= NULL
;
14146 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
14147 if (intel_crtc
== NULL
)
14150 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
14153 intel_crtc
->config
= crtc_state
;
14154 intel_crtc
->base
.state
= &crtc_state
->base
;
14155 crtc_state
->base
.crtc
= &intel_crtc
->base
;
14157 /* initialize shared scalers */
14158 if (INTEL_INFO(dev
)->gen
>= 9) {
14159 if (pipe
== PIPE_C
)
14160 intel_crtc
->num_scalers
= 1;
14162 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
14164 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
14167 primary
= intel_primary_plane_create(dev
, pipe
);
14171 cursor
= intel_cursor_plane_create(dev
, pipe
);
14175 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
14176 cursor
, &intel_crtc_funcs
);
14180 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
14181 for (i
= 0; i
< 256; i
++) {
14182 intel_crtc
->lut_r
[i
] = i
;
14183 intel_crtc
->lut_g
[i
] = i
;
14184 intel_crtc
->lut_b
[i
] = i
;
14188 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14189 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14191 intel_crtc
->pipe
= pipe
;
14192 intel_crtc
->plane
= pipe
;
14193 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
14194 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14195 intel_crtc
->plane
= !pipe
;
14198 intel_crtc
->cursor_base
= ~0;
14199 intel_crtc
->cursor_cntl
= ~0;
14200 intel_crtc
->cursor_size
= ~0;
14202 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
14203 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
14204 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
14205 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
14207 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
14209 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
14214 drm_plane_cleanup(primary
);
14216 drm_plane_cleanup(cursor
);
14221 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
14223 struct drm_encoder
*encoder
= connector
->base
.encoder
;
14224 struct drm_device
*dev
= connector
->base
.dev
;
14226 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
14228 if (!encoder
|| WARN_ON(!encoder
->crtc
))
14229 return INVALID_PIPE
;
14231 return to_intel_crtc(encoder
->crtc
)->pipe
;
14234 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
14235 struct drm_file
*file
)
14237 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
14238 struct drm_crtc
*drmmode_crtc
;
14239 struct intel_crtc
*crtc
;
14241 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
14243 if (!drmmode_crtc
) {
14244 DRM_ERROR("no such CRTC id\n");
14248 crtc
= to_intel_crtc(drmmode_crtc
);
14249 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
14254 static int intel_encoder_clones(struct intel_encoder
*encoder
)
14256 struct drm_device
*dev
= encoder
->base
.dev
;
14257 struct intel_encoder
*source_encoder
;
14258 int index_mask
= 0;
14261 for_each_intel_encoder(dev
, source_encoder
) {
14262 if (encoders_cloneable(encoder
, source_encoder
))
14263 index_mask
|= (1 << entry
);
14271 static bool has_edp_a(struct drm_device
*dev
)
14273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14275 if (!IS_MOBILE(dev
))
14278 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14281 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14287 static bool intel_crt_present(struct drm_device
*dev
)
14289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14291 if (INTEL_INFO(dev
)->gen
>= 9)
14294 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14297 if (IS_CHERRYVIEW(dev
))
14300 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
14306 static void intel_setup_outputs(struct drm_device
*dev
)
14308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14309 struct intel_encoder
*encoder
;
14310 bool dpd_is_edp
= false;
14312 intel_lvds_init(dev
);
14314 if (intel_crt_present(dev
))
14315 intel_crt_init(dev
);
14317 if (IS_BROXTON(dev
)) {
14319 * FIXME: Broxton doesn't support port detection via the
14320 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14321 * detect the ports.
14323 intel_ddi_init(dev
, PORT_A
);
14324 intel_ddi_init(dev
, PORT_B
);
14325 intel_ddi_init(dev
, PORT_C
);
14326 } else if (HAS_DDI(dev
)) {
14330 * Haswell uses DDI functions to detect digital outputs.
14331 * On SKL pre-D0 the strap isn't connected, so we assume
14334 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
14335 /* WaIgnoreDDIAStrap: skl */
14337 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
14338 intel_ddi_init(dev
, PORT_A
);
14340 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14342 found
= I915_READ(SFUSE_STRAP
);
14344 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14345 intel_ddi_init(dev
, PORT_B
);
14346 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14347 intel_ddi_init(dev
, PORT_C
);
14348 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14349 intel_ddi_init(dev
, PORT_D
);
14350 } else if (HAS_PCH_SPLIT(dev
)) {
14352 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14354 if (has_edp_a(dev
))
14355 intel_dp_init(dev
, DP_A
, PORT_A
);
14357 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14358 /* PCH SDVOB multiplex with HDMIB */
14359 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
14361 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14362 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14363 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14366 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14367 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14369 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14370 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14372 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14373 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14375 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14376 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14377 } else if (IS_VALLEYVIEW(dev
)) {
14379 * The DP_DETECTED bit is the latched state of the DDC
14380 * SDA pin at boot. However since eDP doesn't require DDC
14381 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14382 * eDP ports may have been muxed to an alternate function.
14383 * Thus we can't rely on the DP_DETECTED bit alone to detect
14384 * eDP ports. Consult the VBT as well as DP_DETECTED to
14385 * detect eDP ports.
14387 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
14388 !intel_dp_is_edp(dev
, PORT_B
))
14389 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
14391 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
14392 intel_dp_is_edp(dev
, PORT_B
))
14393 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
14395 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
14396 !intel_dp_is_edp(dev
, PORT_C
))
14397 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
14399 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
14400 intel_dp_is_edp(dev
, PORT_C
))
14401 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
14403 if (IS_CHERRYVIEW(dev
)) {
14404 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
14405 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
14407 /* eDP not supported on port D, so don't check VBT */
14408 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
14409 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
14412 intel_dsi_init(dev
);
14413 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
14414 bool found
= false;
14416 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14417 DRM_DEBUG_KMS("probing SDVOB\n");
14418 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14419 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
14420 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14421 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14424 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
14425 intel_dp_init(dev
, DP_B
, PORT_B
);
14428 /* Before G4X SDVOC doesn't have its own detect register */
14430 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14431 DRM_DEBUG_KMS("probing SDVOC\n");
14432 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14435 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14437 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
14438 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14439 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14441 if (SUPPORTS_INTEGRATED_DP(dev
))
14442 intel_dp_init(dev
, DP_C
, PORT_C
);
14445 if (SUPPORTS_INTEGRATED_DP(dev
) &&
14446 (I915_READ(DP_D
) & DP_DETECTED
))
14447 intel_dp_init(dev
, DP_D
, PORT_D
);
14448 } else if (IS_GEN2(dev
))
14449 intel_dvo_init(dev
);
14451 if (SUPPORTS_TV(dev
))
14452 intel_tv_init(dev
);
14454 intel_psr_init(dev
);
14456 for_each_intel_encoder(dev
, encoder
) {
14457 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14458 encoder
->base
.possible_clones
=
14459 intel_encoder_clones(encoder
);
14462 intel_init_pch_refclk(dev
);
14464 drm_helper_move_panel_connectors_to_head(dev
);
14467 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14469 struct drm_device
*dev
= fb
->dev
;
14470 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14472 drm_framebuffer_cleanup(fb
);
14473 mutex_lock(&dev
->struct_mutex
);
14474 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14475 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14476 mutex_unlock(&dev
->struct_mutex
);
14480 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14481 struct drm_file
*file
,
14482 unsigned int *handle
)
14484 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14485 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14487 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14490 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14491 .destroy
= intel_user_framebuffer_destroy
,
14492 .create_handle
= intel_user_framebuffer_create_handle
,
14496 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14497 uint32_t pixel_format
)
14499 u32 gen
= INTEL_INFO(dev
)->gen
;
14502 /* "The stride in bytes must not exceed the of the size of 8K
14503 * pixels and 32K bytes."
14505 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14506 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14508 } else if (gen
>= 4) {
14509 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14513 } else if (gen
>= 3) {
14514 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14519 /* XXX DSPC is limited to 4k tiled */
14524 static int intel_framebuffer_init(struct drm_device
*dev
,
14525 struct intel_framebuffer
*intel_fb
,
14526 struct drm_mode_fb_cmd2
*mode_cmd
,
14527 struct drm_i915_gem_object
*obj
)
14529 unsigned int aligned_height
;
14531 u32 pitch_limit
, stride_alignment
;
14533 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14535 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14536 /* Enforce that fb modifier and tiling mode match, but only for
14537 * X-tiled. This is needed for FBC. */
14538 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14539 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14540 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14544 if (obj
->tiling_mode
== I915_TILING_X
)
14545 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14546 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14547 DRM_DEBUG("No Y tiling for legacy addfb\n");
14552 /* Passed in modifier sanity checking. */
14553 switch (mode_cmd
->modifier
[0]) {
14554 case I915_FORMAT_MOD_Y_TILED
:
14555 case I915_FORMAT_MOD_Yf_TILED
:
14556 if (INTEL_INFO(dev
)->gen
< 9) {
14557 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14558 mode_cmd
->modifier
[0]);
14561 case DRM_FORMAT_MOD_NONE
:
14562 case I915_FORMAT_MOD_X_TILED
:
14565 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14566 mode_cmd
->modifier
[0]);
14570 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14571 mode_cmd
->pixel_format
);
14572 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14573 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14574 mode_cmd
->pitches
[0], stride_alignment
);
14578 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14579 mode_cmd
->pixel_format
);
14580 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14581 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14582 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14583 "tiled" : "linear",
14584 mode_cmd
->pitches
[0], pitch_limit
);
14588 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14589 mode_cmd
->pitches
[0] != obj
->stride
) {
14590 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14591 mode_cmd
->pitches
[0], obj
->stride
);
14595 /* Reject formats not supported by any plane early. */
14596 switch (mode_cmd
->pixel_format
) {
14597 case DRM_FORMAT_C8
:
14598 case DRM_FORMAT_RGB565
:
14599 case DRM_FORMAT_XRGB8888
:
14600 case DRM_FORMAT_ARGB8888
:
14602 case DRM_FORMAT_XRGB1555
:
14603 if (INTEL_INFO(dev
)->gen
> 3) {
14604 DRM_DEBUG("unsupported pixel format: %s\n",
14605 drm_get_format_name(mode_cmd
->pixel_format
));
14609 case DRM_FORMAT_ABGR8888
:
14610 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14611 DRM_DEBUG("unsupported pixel format: %s\n",
14612 drm_get_format_name(mode_cmd
->pixel_format
));
14616 case DRM_FORMAT_XBGR8888
:
14617 case DRM_FORMAT_XRGB2101010
:
14618 case DRM_FORMAT_XBGR2101010
:
14619 if (INTEL_INFO(dev
)->gen
< 4) {
14620 DRM_DEBUG("unsupported pixel format: %s\n",
14621 drm_get_format_name(mode_cmd
->pixel_format
));
14625 case DRM_FORMAT_ABGR2101010
:
14626 if (!IS_VALLEYVIEW(dev
)) {
14627 DRM_DEBUG("unsupported pixel format: %s\n",
14628 drm_get_format_name(mode_cmd
->pixel_format
));
14632 case DRM_FORMAT_YUYV
:
14633 case DRM_FORMAT_UYVY
:
14634 case DRM_FORMAT_YVYU
:
14635 case DRM_FORMAT_VYUY
:
14636 if (INTEL_INFO(dev
)->gen
< 5) {
14637 DRM_DEBUG("unsupported pixel format: %s\n",
14638 drm_get_format_name(mode_cmd
->pixel_format
));
14643 DRM_DEBUG("unsupported pixel format: %s\n",
14644 drm_get_format_name(mode_cmd
->pixel_format
));
14648 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14649 if (mode_cmd
->offsets
[0] != 0)
14652 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14653 mode_cmd
->pixel_format
,
14654 mode_cmd
->modifier
[0]);
14655 /* FIXME drm helper for size checks (especially planar formats)? */
14656 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14659 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14660 intel_fb
->obj
= obj
;
14661 intel_fb
->obj
->framebuffer_references
++;
14663 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14665 DRM_ERROR("framebuffer init failed %d\n", ret
);
14672 static struct drm_framebuffer
*
14673 intel_user_framebuffer_create(struct drm_device
*dev
,
14674 struct drm_file
*filp
,
14675 struct drm_mode_fb_cmd2
*mode_cmd
)
14677 struct drm_i915_gem_object
*obj
;
14679 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14680 mode_cmd
->handles
[0]));
14681 if (&obj
->base
== NULL
)
14682 return ERR_PTR(-ENOENT
);
14684 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14687 #ifndef CONFIG_DRM_I915_FBDEV
14688 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14693 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14694 .fb_create
= intel_user_framebuffer_create
,
14695 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14696 .atomic_check
= intel_atomic_check
,
14697 .atomic_commit
= intel_atomic_commit
,
14698 .atomic_state_alloc
= intel_atomic_state_alloc
,
14699 .atomic_state_clear
= intel_atomic_state_clear
,
14702 /* Set up chip specific display functions */
14703 static void intel_init_display(struct drm_device
*dev
)
14705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14707 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14708 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14709 else if (IS_CHERRYVIEW(dev
))
14710 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14711 else if (IS_VALLEYVIEW(dev
))
14712 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14713 else if (IS_PINEVIEW(dev
))
14714 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14716 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14718 if (INTEL_INFO(dev
)->gen
>= 9) {
14719 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14720 dev_priv
->display
.get_initial_plane_config
=
14721 skylake_get_initial_plane_config
;
14722 dev_priv
->display
.crtc_compute_clock
=
14723 haswell_crtc_compute_clock
;
14724 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14725 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14726 dev_priv
->display
.update_primary_plane
=
14727 skylake_update_primary_plane
;
14728 } else if (HAS_DDI(dev
)) {
14729 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14730 dev_priv
->display
.get_initial_plane_config
=
14731 ironlake_get_initial_plane_config
;
14732 dev_priv
->display
.crtc_compute_clock
=
14733 haswell_crtc_compute_clock
;
14734 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14735 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14736 dev_priv
->display
.update_primary_plane
=
14737 ironlake_update_primary_plane
;
14738 } else if (HAS_PCH_SPLIT(dev
)) {
14739 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14740 dev_priv
->display
.get_initial_plane_config
=
14741 ironlake_get_initial_plane_config
;
14742 dev_priv
->display
.crtc_compute_clock
=
14743 ironlake_crtc_compute_clock
;
14744 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14745 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14746 dev_priv
->display
.update_primary_plane
=
14747 ironlake_update_primary_plane
;
14748 } else if (IS_VALLEYVIEW(dev
)) {
14749 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14750 dev_priv
->display
.get_initial_plane_config
=
14751 i9xx_get_initial_plane_config
;
14752 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14753 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14754 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14755 dev_priv
->display
.update_primary_plane
=
14756 i9xx_update_primary_plane
;
14758 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14759 dev_priv
->display
.get_initial_plane_config
=
14760 i9xx_get_initial_plane_config
;
14761 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14762 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14763 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14764 dev_priv
->display
.update_primary_plane
=
14765 i9xx_update_primary_plane
;
14768 /* Returns the core display clock speed */
14769 if (IS_SKYLAKE(dev
))
14770 dev_priv
->display
.get_display_clock_speed
=
14771 skylake_get_display_clock_speed
;
14772 else if (IS_BROADWELL(dev
))
14773 dev_priv
->display
.get_display_clock_speed
=
14774 broadwell_get_display_clock_speed
;
14775 else if (IS_HASWELL(dev
))
14776 dev_priv
->display
.get_display_clock_speed
=
14777 haswell_get_display_clock_speed
;
14778 else if (IS_VALLEYVIEW(dev
))
14779 dev_priv
->display
.get_display_clock_speed
=
14780 valleyview_get_display_clock_speed
;
14781 else if (IS_GEN5(dev
))
14782 dev_priv
->display
.get_display_clock_speed
=
14783 ilk_get_display_clock_speed
;
14784 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14785 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
14786 dev_priv
->display
.get_display_clock_speed
=
14787 i945_get_display_clock_speed
;
14788 else if (IS_GM45(dev
))
14789 dev_priv
->display
.get_display_clock_speed
=
14790 gm45_get_display_clock_speed
;
14791 else if (IS_CRESTLINE(dev
))
14792 dev_priv
->display
.get_display_clock_speed
=
14793 i965gm_get_display_clock_speed
;
14794 else if (IS_PINEVIEW(dev
))
14795 dev_priv
->display
.get_display_clock_speed
=
14796 pnv_get_display_clock_speed
;
14797 else if (IS_G33(dev
) || IS_G4X(dev
))
14798 dev_priv
->display
.get_display_clock_speed
=
14799 g33_get_display_clock_speed
;
14800 else if (IS_I915G(dev
))
14801 dev_priv
->display
.get_display_clock_speed
=
14802 i915_get_display_clock_speed
;
14803 else if (IS_I945GM(dev
) || IS_845G(dev
))
14804 dev_priv
->display
.get_display_clock_speed
=
14805 i9xx_misc_get_display_clock_speed
;
14806 else if (IS_PINEVIEW(dev
))
14807 dev_priv
->display
.get_display_clock_speed
=
14808 pnv_get_display_clock_speed
;
14809 else if (IS_I915GM(dev
))
14810 dev_priv
->display
.get_display_clock_speed
=
14811 i915gm_get_display_clock_speed
;
14812 else if (IS_I865G(dev
))
14813 dev_priv
->display
.get_display_clock_speed
=
14814 i865_get_display_clock_speed
;
14815 else if (IS_I85X(dev
))
14816 dev_priv
->display
.get_display_clock_speed
=
14817 i85x_get_display_clock_speed
;
14819 WARN(!IS_I830(dev
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14820 dev_priv
->display
.get_display_clock_speed
=
14821 i830_get_display_clock_speed
;
14824 if (IS_GEN5(dev
)) {
14825 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14826 } else if (IS_GEN6(dev
)) {
14827 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14828 } else if (IS_IVYBRIDGE(dev
)) {
14829 /* FIXME: detect B0+ stepping and use auto training */
14830 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14831 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14832 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14833 if (IS_BROADWELL(dev
))
14834 dev_priv
->display
.modeset_global_resources
=
14835 broadwell_modeset_global_resources
;
14836 } else if (IS_VALLEYVIEW(dev
)) {
14837 dev_priv
->display
.modeset_global_resources
=
14838 valleyview_modeset_global_resources
;
14839 } else if (IS_BROXTON(dev
)) {
14840 dev_priv
->display
.modeset_global_resources
=
14841 broxton_modeset_global_resources
;
14844 switch (INTEL_INFO(dev
)->gen
) {
14846 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14850 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14855 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14859 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14862 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14863 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14866 /* Drop through - unsupported since execlist only. */
14868 /* Default just returns -ENODEV to indicate unsupported */
14869 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14872 intel_panel_init_backlight_funcs(dev
);
14874 mutex_init(&dev_priv
->pps_mutex
);
14878 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14879 * resume, or other times. This quirk makes sure that's the case for
14880 * affected systems.
14882 static void quirk_pipea_force(struct drm_device
*dev
)
14884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14886 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14887 DRM_INFO("applying pipe a force quirk\n");
14890 static void quirk_pipeb_force(struct drm_device
*dev
)
14892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14894 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14895 DRM_INFO("applying pipe b force quirk\n");
14899 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14901 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14904 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14905 DRM_INFO("applying lvds SSC disable quirk\n");
14909 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14912 static void quirk_invert_brightness(struct drm_device
*dev
)
14914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14915 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14916 DRM_INFO("applying inverted panel brightness quirk\n");
14919 /* Some VBT's incorrectly indicate no backlight is present */
14920 static void quirk_backlight_present(struct drm_device
*dev
)
14922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14923 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14924 DRM_INFO("applying backlight present quirk\n");
14927 struct intel_quirk
{
14929 int subsystem_vendor
;
14930 int subsystem_device
;
14931 void (*hook
)(struct drm_device
*dev
);
14934 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14935 struct intel_dmi_quirk
{
14936 void (*hook
)(struct drm_device
*dev
);
14937 const struct dmi_system_id (*dmi_id_list
)[];
14940 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14942 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14946 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14948 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14950 .callback
= intel_dmi_reverse_brightness
,
14951 .ident
= "NCR Corporation",
14952 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14953 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14956 { } /* terminating entry */
14958 .hook
= quirk_invert_brightness
,
14962 static struct intel_quirk intel_quirks
[] = {
14963 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14964 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14966 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14967 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14969 /* 830 needs to leave pipe A & dpll A up */
14970 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14972 /* 830 needs to leave pipe B & dpll B up */
14973 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14975 /* Lenovo U160 cannot use SSC on LVDS */
14976 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14978 /* Sony Vaio Y cannot use SSC on LVDS */
14979 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14981 /* Acer Aspire 5734Z must invert backlight brightness */
14982 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14984 /* Acer/eMachines G725 */
14985 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14987 /* Acer/eMachines e725 */
14988 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14990 /* Acer/Packard Bell NCL20 */
14991 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14993 /* Acer Aspire 4736Z */
14994 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14996 /* Acer Aspire 5336 */
14997 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14999 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15000 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
15002 /* Acer C720 Chromebook (Core i3 4005U) */
15003 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
15005 /* Apple Macbook 2,1 (Core 2 T7400) */
15006 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
15008 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15009 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
15011 /* HP Chromebook 14 (Celeron 2955U) */
15012 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
15014 /* Dell Chromebook 11 */
15015 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
15018 static void intel_init_quirks(struct drm_device
*dev
)
15020 struct pci_dev
*d
= dev
->pdev
;
15023 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
15024 struct intel_quirk
*q
= &intel_quirks
[i
];
15026 if (d
->device
== q
->device
&&
15027 (d
->subsystem_vendor
== q
->subsystem_vendor
||
15028 q
->subsystem_vendor
== PCI_ANY_ID
) &&
15029 (d
->subsystem_device
== q
->subsystem_device
||
15030 q
->subsystem_device
== PCI_ANY_ID
))
15033 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
15034 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
15035 intel_dmi_quirks
[i
].hook(dev
);
15039 /* Disable the VGA plane that we never use */
15040 static void i915_disable_vga(struct drm_device
*dev
)
15042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15044 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15046 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15047 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15048 outb(SR01
, VGA_SR_INDEX
);
15049 sr1
= inb(VGA_SR_DATA
);
15050 outb(sr1
| 1<<5, VGA_SR_DATA
);
15051 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
15054 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
15055 POSTING_READ(vga_reg
);
15058 void intel_modeset_init_hw(struct drm_device
*dev
)
15060 intel_update_cdclk(dev
);
15061 intel_prepare_ddi(dev
);
15062 intel_init_clock_gating(dev
);
15063 intel_enable_gt_powersave(dev
);
15066 void intel_modeset_init(struct drm_device
*dev
)
15068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15071 struct intel_crtc
*crtc
;
15073 drm_mode_config_init(dev
);
15075 dev
->mode_config
.min_width
= 0;
15076 dev
->mode_config
.min_height
= 0;
15078 dev
->mode_config
.preferred_depth
= 24;
15079 dev
->mode_config
.prefer_shadow
= 1;
15081 dev
->mode_config
.allow_fb_modifiers
= true;
15083 dev
->mode_config
.funcs
= &intel_mode_funcs
;
15085 intel_init_quirks(dev
);
15087 intel_init_pm(dev
);
15089 if (INTEL_INFO(dev
)->num_pipes
== 0)
15092 intel_init_display(dev
);
15093 intel_init_audio(dev
);
15095 if (IS_GEN2(dev
)) {
15096 dev
->mode_config
.max_width
= 2048;
15097 dev
->mode_config
.max_height
= 2048;
15098 } else if (IS_GEN3(dev
)) {
15099 dev
->mode_config
.max_width
= 4096;
15100 dev
->mode_config
.max_height
= 4096;
15102 dev
->mode_config
.max_width
= 8192;
15103 dev
->mode_config
.max_height
= 8192;
15106 if (IS_845G(dev
) || IS_I865G(dev
)) {
15107 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
15108 dev
->mode_config
.cursor_height
= 1023;
15109 } else if (IS_GEN2(dev
)) {
15110 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
15111 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
15113 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
15114 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
15117 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
15119 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15120 INTEL_INFO(dev
)->num_pipes
,
15121 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
15123 for_each_pipe(dev_priv
, pipe
) {
15124 intel_crtc_init(dev
, pipe
);
15125 for_each_sprite(dev_priv
, pipe
, sprite
) {
15126 ret
= intel_plane_init(dev
, pipe
, sprite
);
15128 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15129 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
15133 intel_init_dpio(dev
);
15135 intel_shared_dpll_init(dev
);
15137 /* Just disable it once at startup */
15138 i915_disable_vga(dev
);
15139 intel_setup_outputs(dev
);
15141 /* Just in case the BIOS is doing something questionable. */
15142 intel_fbc_disable(dev
);
15144 drm_modeset_lock_all(dev
);
15145 intel_modeset_setup_hw_state(dev
, false);
15146 drm_modeset_unlock_all(dev
);
15148 for_each_intel_crtc(dev
, crtc
) {
15153 * Note that reserving the BIOS fb up front prevents us
15154 * from stuffing other stolen allocations like the ring
15155 * on top. This prevents some ugliness at boot time, and
15156 * can even allow for smooth boot transitions if the BIOS
15157 * fb is large enough for the active pipe configuration.
15159 if (dev_priv
->display
.get_initial_plane_config
) {
15160 dev_priv
->display
.get_initial_plane_config(crtc
,
15161 &crtc
->plane_config
);
15163 * If the fb is shared between multiple heads, we'll
15164 * just get the first one.
15166 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
15171 static void intel_enable_pipe_a(struct drm_device
*dev
)
15173 struct intel_connector
*connector
;
15174 struct drm_connector
*crt
= NULL
;
15175 struct intel_load_detect_pipe load_detect_temp
;
15176 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
15178 /* We can't just switch on the pipe A, we need to set things up with a
15179 * proper mode and output configuration. As a gross hack, enable pipe A
15180 * by enabling the load detect pipe once. */
15181 for_each_intel_connector(dev
, connector
) {
15182 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
15183 crt
= &connector
->base
;
15191 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
15192 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
15196 intel_check_plane_mapping(struct intel_crtc
*crtc
)
15198 struct drm_device
*dev
= crtc
->base
.dev
;
15199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15202 if (INTEL_INFO(dev
)->num_pipes
== 1)
15205 reg
= DSPCNTR(!crtc
->plane
);
15206 val
= I915_READ(reg
);
15208 if ((val
& DISPLAY_PLANE_ENABLE
) &&
15209 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15215 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15217 struct drm_device
*dev
= crtc
->base
.dev
;
15218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15219 struct intel_encoder
*encoder
;
15223 /* Clear any frame start delays used for debugging left by the BIOS */
15224 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
15225 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15227 /* restore vblank interrupts to correct state */
15228 drm_crtc_vblank_reset(&crtc
->base
);
15229 if (crtc
->active
) {
15230 update_scanline_offset(crtc
);
15231 drm_crtc_vblank_on(&crtc
->base
);
15234 /* We need to sanitize the plane -> pipe mapping first because this will
15235 * disable the crtc (and hence change the state) if it is wrong. Note
15236 * that gen4+ has a fixed plane -> pipe mapping. */
15237 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15240 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15241 crtc
->base
.base
.id
);
15243 /* Pipe has the wrong plane attached and the plane is active.
15244 * Temporarily change the plane mapping and disable everything
15246 plane
= crtc
->plane
;
15247 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15248 crtc
->plane
= !plane
;
15249 intel_crtc_disable_noatomic(&crtc
->base
);
15250 crtc
->plane
= plane
;
15253 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15254 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15255 /* BIOS forgot to enable pipe A, this mostly happens after
15256 * resume. Force-enable the pipe to fix this, the update_dpms
15257 * call below we restore the pipe to the right state, but leave
15258 * the required bits on. */
15259 intel_enable_pipe_a(dev
);
15262 /* Adjust the state of the output pipe according to whether we
15263 * have active connectors/encoders. */
15265 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15266 enable
|= encoder
->connectors_active
;
15269 intel_crtc_disable_noatomic(&crtc
->base
);
15271 if (crtc
->active
!= crtc
->base
.state
->active
) {
15273 /* This can happen either due to bugs in the get_hw_state
15274 * functions or because of calls to intel_crtc_disable_noatomic,
15275 * or because the pipe is force-enabled due to the
15277 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15278 crtc
->base
.base
.id
,
15279 crtc
->base
.state
->enable
? "enabled" : "disabled",
15280 crtc
->active
? "enabled" : "disabled");
15282 crtc
->base
.state
->enable
= crtc
->active
;
15283 crtc
->base
.state
->active
= crtc
->active
;
15284 crtc
->base
.enabled
= crtc
->active
;
15286 /* Because we only establish the connector -> encoder ->
15287 * crtc links if something is active, this means the
15288 * crtc is now deactivated. Break the links. connector
15289 * -> encoder links are only establish when things are
15290 * actually up, hence no need to break them. */
15291 WARN_ON(crtc
->active
);
15293 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
15294 WARN_ON(encoder
->connectors_active
);
15295 encoder
->base
.crtc
= NULL
;
15299 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15301 * We start out with underrun reporting disabled to avoid races.
15302 * For correct bookkeeping mark this on active crtcs.
15304 * Also on gmch platforms we dont have any hardware bits to
15305 * disable the underrun reporting. Which means we need to start
15306 * out with underrun reporting disabled also on inactive pipes,
15307 * since otherwise we'll complain about the garbage we read when
15308 * e.g. coming up after runtime pm.
15310 * No protection against concurrent access is required - at
15311 * worst a fifo underrun happens which also sets this to false.
15313 crtc
->cpu_fifo_underrun_disabled
= true;
15314 crtc
->pch_fifo_underrun_disabled
= true;
15318 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15320 struct intel_connector
*connector
;
15321 struct drm_device
*dev
= encoder
->base
.dev
;
15323 /* We need to check both for a crtc link (meaning that the
15324 * encoder is active and trying to read from a pipe) and the
15325 * pipe itself being active. */
15326 bool has_active_crtc
= encoder
->base
.crtc
&&
15327 to_intel_crtc(encoder
->base
.crtc
)->active
;
15329 if (encoder
->connectors_active
&& !has_active_crtc
) {
15330 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15331 encoder
->base
.base
.id
,
15332 encoder
->base
.name
);
15334 /* Connector is active, but has no active pipe. This is
15335 * fallout from our resume register restoring. Disable
15336 * the encoder manually again. */
15337 if (encoder
->base
.crtc
) {
15338 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15339 encoder
->base
.base
.id
,
15340 encoder
->base
.name
);
15341 encoder
->disable(encoder
);
15342 if (encoder
->post_disable
)
15343 encoder
->post_disable(encoder
);
15345 encoder
->base
.crtc
= NULL
;
15346 encoder
->connectors_active
= false;
15348 /* Inconsistent output/port/pipe state happens presumably due to
15349 * a bug in one of the get_hw_state functions. Or someplace else
15350 * in our code, like the register restore mess on resume. Clamp
15351 * things to off as a safer default. */
15352 for_each_intel_connector(dev
, connector
) {
15353 if (connector
->encoder
!= encoder
)
15355 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15356 connector
->base
.encoder
= NULL
;
15359 /* Enabled encoders without active connectors will be fixed in
15360 * the crtc fixup. */
15363 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15366 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15368 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15369 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15370 i915_disable_vga(dev
);
15374 void i915_redisable_vga(struct drm_device
*dev
)
15376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15378 /* This function can be called both from intel_modeset_setup_hw_state or
15379 * at a very early point in our resume sequence, where the power well
15380 * structures are not yet restored. Since this function is at a very
15381 * paranoid "someone might have enabled VGA while we were not looking"
15382 * level, just check if the power well is enabled instead of trying to
15383 * follow the "don't touch the power well if we don't need it" policy
15384 * the rest of the driver uses. */
15385 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15388 i915_redisable_vga_power_on(dev
);
15391 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
15393 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
15398 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
15401 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15405 struct intel_crtc
*crtc
;
15406 struct intel_encoder
*encoder
;
15407 struct intel_connector
*connector
;
15410 for_each_intel_crtc(dev
, crtc
) {
15411 struct drm_plane
*primary
= crtc
->base
.primary
;
15412 struct intel_plane_state
*plane_state
;
15414 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15415 crtc
->config
->base
.crtc
= &crtc
->base
;
15417 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
15419 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15422 crtc
->base
.state
->enable
= crtc
->active
;
15423 crtc
->base
.state
->active
= crtc
->active
;
15424 crtc
->base
.enabled
= crtc
->active
;
15425 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15427 plane_state
= to_intel_plane_state(primary
->state
);
15428 plane_state
->visible
= primary_get_hw_state(crtc
);
15430 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15431 crtc
->base
.base
.id
,
15432 crtc
->active
? "enabled" : "disabled");
15435 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15436 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15438 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15439 &pll
->config
.hw_state
);
15441 pll
->config
.crtc_mask
= 0;
15442 for_each_intel_crtc(dev
, crtc
) {
15443 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15445 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15449 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15450 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15452 if (pll
->config
.crtc_mask
)
15453 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15456 for_each_intel_encoder(dev
, encoder
) {
15459 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15460 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15461 encoder
->base
.crtc
= &crtc
->base
;
15462 encoder
->get_config(encoder
, crtc
->config
);
15464 encoder
->base
.crtc
= NULL
;
15467 encoder
->connectors_active
= false;
15468 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15469 encoder
->base
.base
.id
,
15470 encoder
->base
.name
,
15471 encoder
->base
.crtc
? "enabled" : "disabled",
15475 for_each_intel_connector(dev
, connector
) {
15476 if (connector
->get_hw_state(connector
)) {
15477 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15478 connector
->encoder
->connectors_active
= true;
15479 connector
->base
.encoder
= &connector
->encoder
->base
;
15481 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15482 connector
->base
.encoder
= NULL
;
15484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15485 connector
->base
.base
.id
,
15486 connector
->base
.name
,
15487 connector
->base
.encoder
? "enabled" : "disabled");
15491 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15492 * and i915 state tracking structures. */
15493 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
15494 bool force_restore
)
15496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15498 struct intel_crtc
*crtc
;
15499 struct intel_encoder
*encoder
;
15502 intel_modeset_readout_hw_state(dev
);
15505 * Now that we have the config, copy it to each CRTC struct
15506 * Note that this could go away if we move to using crtc_config
15507 * checking everywhere.
15509 for_each_intel_crtc(dev
, crtc
) {
15510 if (crtc
->active
&& i915
.fastboot
) {
15511 intel_mode_from_pipe_config(&crtc
->base
.mode
,
15513 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15514 crtc
->base
.base
.id
);
15515 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
15519 /* HW state is read out, now we need to sanitize this mess. */
15520 for_each_intel_encoder(dev
, encoder
) {
15521 intel_sanitize_encoder(encoder
);
15524 for_each_pipe(dev_priv
, pipe
) {
15525 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15526 intel_sanitize_crtc(crtc
);
15527 intel_dump_pipe_config(crtc
, crtc
->config
,
15528 "[setup_hw_state]");
15531 intel_modeset_update_connector_atomic_state(dev
);
15533 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15534 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15536 if (!pll
->on
|| pll
->active
)
15539 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15541 pll
->disable(dev_priv
, pll
);
15546 skl_wm_get_hw_state(dev
);
15547 else if (HAS_PCH_SPLIT(dev
))
15548 ilk_wm_get_hw_state(dev
);
15550 if (force_restore
) {
15551 i915_redisable_vga(dev
);
15554 * We need to use raw interfaces for restoring state to avoid
15555 * checking (bogus) intermediate states.
15557 for_each_pipe(dev_priv
, pipe
) {
15558 struct drm_crtc
*crtc
=
15559 dev_priv
->pipe_to_crtc_mapping
[pipe
];
15561 intel_crtc_restore_mode(crtc
);
15564 intel_modeset_update_staged_output_state(dev
);
15567 intel_modeset_check_state(dev
);
15570 void intel_modeset_gem_init(struct drm_device
*dev
)
15572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15573 struct drm_crtc
*c
;
15574 struct drm_i915_gem_object
*obj
;
15577 mutex_lock(&dev
->struct_mutex
);
15578 intel_init_gt_powersave(dev
);
15579 mutex_unlock(&dev
->struct_mutex
);
15582 * There may be no VBT; and if the BIOS enabled SSC we can
15583 * just keep using it to avoid unnecessary flicker. Whereas if the
15584 * BIOS isn't using it, don't assume it will work even if the VBT
15585 * indicates as much.
15587 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
15588 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15591 intel_modeset_init_hw(dev
);
15593 intel_setup_overlay(dev
);
15596 * Make sure any fbs we allocated at startup are properly
15597 * pinned & fenced. When we do the allocation it's too early
15600 for_each_crtc(dev
, c
) {
15601 obj
= intel_fb_obj(c
->primary
->fb
);
15605 mutex_lock(&dev
->struct_mutex
);
15606 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15610 mutex_unlock(&dev
->struct_mutex
);
15612 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15613 to_intel_crtc(c
)->pipe
);
15614 drm_framebuffer_unreference(c
->primary
->fb
);
15615 c
->primary
->fb
= NULL
;
15616 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
15617 update_state_fb(c
->primary
);
15618 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
15622 intel_backlight_register(dev
);
15625 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15627 struct drm_connector
*connector
= &intel_connector
->base
;
15629 intel_panel_destroy_backlight(connector
);
15630 drm_connector_unregister(connector
);
15633 void intel_modeset_cleanup(struct drm_device
*dev
)
15635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15636 struct drm_connector
*connector
;
15638 intel_disable_gt_powersave(dev
);
15640 intel_backlight_unregister(dev
);
15643 * Interrupts and polling as the first thing to avoid creating havoc.
15644 * Too much stuff here (turning of connectors, ...) would
15645 * experience fancy races otherwise.
15647 intel_irq_uninstall(dev_priv
);
15650 * Due to the hpd irq storm handling the hotplug work can re-arm the
15651 * poll handlers. Hence disable polling after hpd handling is shut down.
15653 drm_kms_helper_poll_fini(dev
);
15655 mutex_lock(&dev
->struct_mutex
);
15657 intel_unregister_dsm_handler();
15659 intel_fbc_disable(dev
);
15661 mutex_unlock(&dev
->struct_mutex
);
15663 /* flush any delayed tasks or pending work */
15664 flush_scheduled_work();
15666 /* destroy the backlight and sysfs files before encoders/connectors */
15667 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15668 struct intel_connector
*intel_connector
;
15670 intel_connector
= to_intel_connector(connector
);
15671 intel_connector
->unregister(intel_connector
);
15674 drm_mode_config_cleanup(dev
);
15676 intel_cleanup_overlay(dev
);
15678 mutex_lock(&dev
->struct_mutex
);
15679 intel_cleanup_gt_powersave(dev
);
15680 mutex_unlock(&dev
->struct_mutex
);
15684 * Return which encoder is currently attached for connector.
15686 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15688 return &intel_attached_encoder(connector
)->base
;
15691 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15692 struct intel_encoder
*encoder
)
15694 connector
->encoder
= encoder
;
15695 drm_mode_connector_attach_encoder(&connector
->base
,
15700 * set vga decode state - true == enable VGA decode
15702 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15705 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15708 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15709 DRM_ERROR("failed to read control word\n");
15713 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15717 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15719 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15721 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15722 DRM_ERROR("failed to write control word\n");
15729 struct intel_display_error_state
{
15731 u32 power_well_driver
;
15733 int num_transcoders
;
15735 struct intel_cursor_error_state
{
15740 } cursor
[I915_MAX_PIPES
];
15742 struct intel_pipe_error_state
{
15743 bool power_domain_on
;
15746 } pipe
[I915_MAX_PIPES
];
15748 struct intel_plane_error_state
{
15756 } plane
[I915_MAX_PIPES
];
15758 struct intel_transcoder_error_state
{
15759 bool power_domain_on
;
15760 enum transcoder cpu_transcoder
;
15773 struct intel_display_error_state
*
15774 intel_display_capture_error_state(struct drm_device
*dev
)
15776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15777 struct intel_display_error_state
*error
;
15778 int transcoders
[] = {
15786 if (INTEL_INFO(dev
)->num_pipes
== 0)
15789 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15793 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15794 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15796 for_each_pipe(dev_priv
, i
) {
15797 error
->pipe
[i
].power_domain_on
=
15798 __intel_display_power_is_enabled(dev_priv
,
15799 POWER_DOMAIN_PIPE(i
));
15800 if (!error
->pipe
[i
].power_domain_on
)
15803 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15804 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15805 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15807 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15808 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15809 if (INTEL_INFO(dev
)->gen
<= 3) {
15810 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15811 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15813 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15814 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15815 if (INTEL_INFO(dev
)->gen
>= 4) {
15816 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15817 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15820 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15822 if (HAS_GMCH_DISPLAY(dev
))
15823 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15826 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15827 if (HAS_DDI(dev_priv
->dev
))
15828 error
->num_transcoders
++; /* Account for eDP. */
15830 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15831 enum transcoder cpu_transcoder
= transcoders
[i
];
15833 error
->transcoder
[i
].power_domain_on
=
15834 __intel_display_power_is_enabled(dev_priv
,
15835 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15836 if (!error
->transcoder
[i
].power_domain_on
)
15839 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15841 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15842 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15843 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15844 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15845 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15846 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15847 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15853 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15856 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15857 struct drm_device
*dev
,
15858 struct intel_display_error_state
*error
)
15860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15866 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15867 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15868 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15869 error
->power_well_driver
);
15870 for_each_pipe(dev_priv
, i
) {
15871 err_printf(m
, "Pipe [%d]:\n", i
);
15872 err_printf(m
, " Power: %s\n",
15873 error
->pipe
[i
].power_domain_on
? "on" : "off");
15874 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15875 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15877 err_printf(m
, "Plane [%d]:\n", i
);
15878 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15879 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15880 if (INTEL_INFO(dev
)->gen
<= 3) {
15881 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15882 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15884 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15885 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15886 if (INTEL_INFO(dev
)->gen
>= 4) {
15887 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15888 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15891 err_printf(m
, "Cursor [%d]:\n", i
);
15892 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15893 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15894 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15897 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15898 err_printf(m
, "CPU transcoder: %c\n",
15899 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15900 err_printf(m
, " Power: %s\n",
15901 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15902 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15903 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15904 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15905 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15906 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15907 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15908 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15912 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15914 struct intel_crtc
*crtc
;
15916 for_each_intel_crtc(dev
, crtc
) {
15917 struct intel_unpin_work
*work
;
15919 spin_lock_irq(&dev
->event_lock
);
15921 work
= crtc
->unpin_work
;
15923 if (work
&& work
->event
&&
15924 work
->event
->base
.file_priv
== file
) {
15925 kfree(work
->event
);
15926 work
->event
= NULL
;
15929 spin_unlock_irq(&dev
->event_lock
);