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drm/i915: Rename hw state checker to hw state verifier.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
189 CCK_DISPLAY_REF_CLOCK_CONTROL);
190 }
191
192 static int
193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
194 {
195 uint32_t clkcfg;
196
197 /* hrawclock is 1/4 the FSB frequency */
198 clkcfg = I915_READ(CLKCFG);
199 switch (clkcfg & CLKCFG_FSB_MASK) {
200 case CLKCFG_FSB_400:
201 return 100000;
202 case CLKCFG_FSB_533:
203 return 133333;
204 case CLKCFG_FSB_667:
205 return 166667;
206 case CLKCFG_FSB_800:
207 return 200000;
208 case CLKCFG_FSB_1067:
209 return 266667;
210 case CLKCFG_FSB_1333:
211 return 333333;
212 /* these two are just a guess; one of them might be right */
213 case CLKCFG_FSB_1600:
214 case CLKCFG_FSB_1600_ALT:
215 return 400000;
216 default:
217 return 133333;
218 }
219 }
220
221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
222 {
223 if (HAS_PCH_SPLIT(dev_priv))
224 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
225 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
226 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
227 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
228 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
229 else
230 return; /* no rawclk on other platforms, or no need to know it */
231
232 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
233 }
234
235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
236 {
237 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
238 return;
239
240 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
241 CCK_CZ_CLOCK_CONTROL);
242
243 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
244 }
245
246 static inline u32 /* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
248 const struct intel_crtc_state *pipe_config)
249 {
250 if (HAS_DDI(dev_priv))
251 return pipe_config->port_clock; /* SPLL */
252 else if (IS_GEN5(dev_priv))
253 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
254 else
255 return 270000;
256 }
257
258 static const intel_limit_t intel_limits_i8xx_dac = {
259 .dot = { .min = 25000, .max = 350000 },
260 .vco = { .min = 908000, .max = 1512000 },
261 .n = { .min = 2, .max = 16 },
262 .m = { .min = 96, .max = 140 },
263 .m1 = { .min = 18, .max = 26 },
264 .m2 = { .min = 6, .max = 16 },
265 .p = { .min = 4, .max = 128 },
266 .p1 = { .min = 2, .max = 33 },
267 .p2 = { .dot_limit = 165000,
268 .p2_slow = 4, .p2_fast = 2 },
269 };
270
271 static const intel_limit_t intel_limits_i8xx_dvo = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 908000, .max = 1512000 },
274 .n = { .min = 2, .max = 16 },
275 .m = { .min = 96, .max = 140 },
276 .m1 = { .min = 18, .max = 26 },
277 .m2 = { .min = 6, .max = 16 },
278 .p = { .min = 4, .max = 128 },
279 .p1 = { .min = 2, .max = 33 },
280 .p2 = { .dot_limit = 165000,
281 .p2_slow = 4, .p2_fast = 4 },
282 };
283
284 static const intel_limit_t intel_limits_i8xx_lvds = {
285 .dot = { .min = 25000, .max = 350000 },
286 .vco = { .min = 908000, .max = 1512000 },
287 .n = { .min = 2, .max = 16 },
288 .m = { .min = 96, .max = 140 },
289 .m1 = { .min = 18, .max = 26 },
290 .m2 = { .min = 6, .max = 16 },
291 .p = { .min = 4, .max = 128 },
292 .p1 = { .min = 1, .max = 6 },
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 14, .p2_fast = 7 },
295 };
296
297 static const intel_limit_t intel_limits_i9xx_sdvo = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1400000, .max = 2800000 },
300 .n = { .min = 1, .max = 6 },
301 .m = { .min = 70, .max = 120 },
302 .m1 = { .min = 8, .max = 18 },
303 .m2 = { .min = 3, .max = 7 },
304 .p = { .min = 5, .max = 80 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 200000,
307 .p2_slow = 10, .p2_fast = 5 },
308 };
309
310 static const intel_limit_t intel_limits_i9xx_lvds = {
311 .dot = { .min = 20000, .max = 400000 },
312 .vco = { .min = 1400000, .max = 2800000 },
313 .n = { .min = 1, .max = 6 },
314 .m = { .min = 70, .max = 120 },
315 .m1 = { .min = 8, .max = 18 },
316 .m2 = { .min = 3, .max = 7 },
317 .p = { .min = 7, .max = 98 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 112000,
320 .p2_slow = 14, .p2_fast = 7 },
321 };
322
323
324 static const intel_limit_t intel_limits_g4x_sdvo = {
325 .dot = { .min = 25000, .max = 270000 },
326 .vco = { .min = 1750000, .max = 3500000},
327 .n = { .min = 1, .max = 4 },
328 .m = { .min = 104, .max = 138 },
329 .m1 = { .min = 17, .max = 23 },
330 .m2 = { .min = 5, .max = 11 },
331 .p = { .min = 10, .max = 30 },
332 .p1 = { .min = 1, .max = 3},
333 .p2 = { .dot_limit = 270000,
334 .p2_slow = 10,
335 .p2_fast = 10
336 },
337 };
338
339 static const intel_limit_t intel_limits_g4x_hdmi = {
340 .dot = { .min = 22000, .max = 400000 },
341 .vco = { .min = 1750000, .max = 3500000},
342 .n = { .min = 1, .max = 4 },
343 .m = { .min = 104, .max = 138 },
344 .m1 = { .min = 16, .max = 23 },
345 .m2 = { .min = 5, .max = 11 },
346 .p = { .min = 5, .max = 80 },
347 .p1 = { .min = 1, .max = 8},
348 .p2 = { .dot_limit = 165000,
349 .p2_slow = 10, .p2_fast = 5 },
350 };
351
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
353 .dot = { .min = 20000, .max = 115000 },
354 .vco = { .min = 1750000, .max = 3500000 },
355 .n = { .min = 1, .max = 3 },
356 .m = { .min = 104, .max = 138 },
357 .m1 = { .min = 17, .max = 23 },
358 .m2 = { .min = 5, .max = 11 },
359 .p = { .min = 28, .max = 112 },
360 .p1 = { .min = 2, .max = 8 },
361 .p2 = { .dot_limit = 0,
362 .p2_slow = 14, .p2_fast = 14
363 },
364 };
365
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
367 .dot = { .min = 80000, .max = 224000 },
368 .vco = { .min = 1750000, .max = 3500000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 104, .max = 138 },
371 .m1 = { .min = 17, .max = 23 },
372 .m2 = { .min = 5, .max = 11 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 0,
376 .p2_slow = 7, .p2_fast = 7
377 },
378 };
379
380 static const intel_limit_t intel_limits_pineview_sdvo = {
381 .dot = { .min = 20000, .max = 400000},
382 .vco = { .min = 1700000, .max = 3500000 },
383 /* Pineview's Ncounter is a ring counter */
384 .n = { .min = 3, .max = 6 },
385 .m = { .min = 2, .max = 256 },
386 /* Pineview only has one combined m divider, which we treat as m2. */
387 .m1 = { .min = 0, .max = 0 },
388 .m2 = { .min = 0, .max = 254 },
389 .p = { .min = 5, .max = 80 },
390 .p1 = { .min = 1, .max = 8 },
391 .p2 = { .dot_limit = 200000,
392 .p2_slow = 10, .p2_fast = 5 },
393 };
394
395 static const intel_limit_t intel_limits_pineview_lvds = {
396 .dot = { .min = 20000, .max = 400000 },
397 .vco = { .min = 1700000, .max = 3500000 },
398 .n = { .min = 3, .max = 6 },
399 .m = { .min = 2, .max = 256 },
400 .m1 = { .min = 0, .max = 0 },
401 .m2 = { .min = 0, .max = 254 },
402 .p = { .min = 7, .max = 112 },
403 .p1 = { .min = 1, .max = 8 },
404 .p2 = { .dot_limit = 112000,
405 .p2_slow = 14, .p2_fast = 14 },
406 };
407
408 /* Ironlake / Sandybridge
409 *
410 * We calculate clock using (register_value + 2) for N/M1/M2, so here
411 * the range value for them is (actual_value - 2).
412 */
413 static const intel_limit_t intel_limits_ironlake_dac = {
414 .dot = { .min = 25000, .max = 350000 },
415 .vco = { .min = 1760000, .max = 3510000 },
416 .n = { .min = 1, .max = 5 },
417 .m = { .min = 79, .max = 127 },
418 .m1 = { .min = 12, .max = 22 },
419 .m2 = { .min = 5, .max = 9 },
420 .p = { .min = 5, .max = 80 },
421 .p1 = { .min = 1, .max = 8 },
422 .p2 = { .dot_limit = 225000,
423 .p2_slow = 10, .p2_fast = 5 },
424 };
425
426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
427 .dot = { .min = 25000, .max = 350000 },
428 .vco = { .min = 1760000, .max = 3510000 },
429 .n = { .min = 1, .max = 3 },
430 .m = { .min = 79, .max = 118 },
431 .m1 = { .min = 12, .max = 22 },
432 .m2 = { .min = 5, .max = 9 },
433 .p = { .min = 28, .max = 112 },
434 .p1 = { .min = 2, .max = 8 },
435 .p2 = { .dot_limit = 225000,
436 .p2_slow = 14, .p2_fast = 14 },
437 };
438
439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
440 .dot = { .min = 25000, .max = 350000 },
441 .vco = { .min = 1760000, .max = 3510000 },
442 .n = { .min = 1, .max = 3 },
443 .m = { .min = 79, .max = 127 },
444 .m1 = { .min = 12, .max = 22 },
445 .m2 = { .min = 5, .max = 9 },
446 .p = { .min = 14, .max = 56 },
447 .p1 = { .min = 2, .max = 8 },
448 .p2 = { .dot_limit = 225000,
449 .p2_slow = 7, .p2_fast = 7 },
450 };
451
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
454 .dot = { .min = 25000, .max = 350000 },
455 .vco = { .min = 1760000, .max = 3510000 },
456 .n = { .min = 1, .max = 2 },
457 .m = { .min = 79, .max = 126 },
458 .m1 = { .min = 12, .max = 22 },
459 .m2 = { .min = 5, .max = 9 },
460 .p = { .min = 28, .max = 112 },
461 .p1 = { .min = 2, .max = 8 },
462 .p2 = { .dot_limit = 225000,
463 .p2_slow = 14, .p2_fast = 14 },
464 };
465
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
467 .dot = { .min = 25000, .max = 350000 },
468 .vco = { .min = 1760000, .max = 3510000 },
469 .n = { .min = 1, .max = 3 },
470 .m = { .min = 79, .max = 126 },
471 .m1 = { .min = 12, .max = 22 },
472 .m2 = { .min = 5, .max = 9 },
473 .p = { .min = 14, .max = 42 },
474 .p1 = { .min = 2, .max = 6 },
475 .p2 = { .dot_limit = 225000,
476 .p2_slow = 7, .p2_fast = 7 },
477 };
478
479 static const intel_limit_t intel_limits_vlv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
487 .vco = { .min = 4000000, .max = 6000000 },
488 .n = { .min = 1, .max = 7 },
489 .m1 = { .min = 2, .max = 3 },
490 .m2 = { .min = 11, .max = 156 },
491 .p1 = { .min = 2, .max = 3 },
492 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
493 };
494
495 static const intel_limit_t intel_limits_chv = {
496 /*
497 * These are the data rate limits (measured in fast clocks)
498 * since those are the strictest limits we have. The fast
499 * clock and actual rate limits are more relaxed, so checking
500 * them would make no difference.
501 */
502 .dot = { .min = 25000 * 5, .max = 540000 * 5},
503 .vco = { .min = 4800000, .max = 6480000 },
504 .n = { .min = 1, .max = 1 },
505 .m1 = { .min = 2, .max = 2 },
506 .m2 = { .min = 24 << 22, .max = 175 << 22 },
507 .p1 = { .min = 2, .max = 4 },
508 .p2 = { .p2_slow = 1, .p2_fast = 14 },
509 };
510
511 static const intel_limit_t intel_limits_bxt = {
512 /* FIXME: find real dot limits */
513 .dot = { .min = 0, .max = INT_MAX },
514 .vco = { .min = 4800000, .max = 6700000 },
515 .n = { .min = 1, .max = 1 },
516 .m1 = { .min = 2, .max = 2 },
517 /* FIXME: find real m2 limits */
518 .m2 = { .min = 2 << 22, .max = 255 << 22 },
519 .p1 = { .min = 2, .max = 4 },
520 .p2 = { .p2_slow = 1, .p2_fast = 20 },
521 };
522
523 static bool
524 needs_modeset(struct drm_crtc_state *state)
525 {
526 return drm_atomic_crtc_needs_modeset(state);
527 }
528
529 /**
530 * Returns whether any output on the specified pipe is of the specified type
531 */
532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
533 {
534 struct drm_device *dev = crtc->base.dev;
535 struct intel_encoder *encoder;
536
537 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
538 if (encoder->type == type)
539 return true;
540
541 return false;
542 }
543
544 /**
545 * Returns whether any output on the specified pipe will have the specified
546 * type after a staged modeset is complete, i.e., the same as
547 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
548 * encoder->crtc.
549 */
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
551 int type)
552 {
553 struct drm_atomic_state *state = crtc_state->base.state;
554 struct drm_connector *connector;
555 struct drm_connector_state *connector_state;
556 struct intel_encoder *encoder;
557 int i, num_connectors = 0;
558
559 for_each_connector_in_state(state, connector, connector_state, i) {
560 if (connector_state->crtc != crtc_state->base.crtc)
561 continue;
562
563 num_connectors++;
564
565 encoder = to_intel_encoder(connector_state->best_encoder);
566 if (encoder->type == type)
567 return true;
568 }
569
570 WARN_ON(num_connectors == 0);
571
572 return false;
573 }
574
575 /*
576 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579 * The helpers' return value is the rate of the clock that is fed to the
580 * display engine's pipe which can be the above fast dot clock rate or a
581 * divided-down version of it.
582 */
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592
593 return clock->dot;
594 }
595
596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
597 {
598 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
599 }
600
601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
602 {
603 clock->m = i9xx_dpll_compute_m(clock);
604 clock->p = clock->p1 * clock->p2;
605 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
606 return 0;
607 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
608 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609
610 return clock->dot;
611 }
612
613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
614 {
615 clock->m = clock->m1 * clock->m2;
616 clock->p = clock->p1 * clock->p2;
617 if (WARN_ON(clock->n == 0 || clock->p == 0))
618 return 0;
619 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
620 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
621
622 return clock->dot / 5;
623 }
624
625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
626 {
627 clock->m = clock->m1 * clock->m2;
628 clock->p = clock->p1 * clock->p2;
629 if (WARN_ON(clock->n == 0 || clock->p == 0))
630 return 0;
631 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
632 clock->n << 22);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634
635 return clock->dot / 5;
636 }
637
638 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
639 /**
640 * Returns whether the given set of divisors are valid for a given refclk with
641 * the given connectors.
642 */
643
644 static bool intel_PLL_is_valid(struct drm_device *dev,
645 const intel_limit_t *limit,
646 const intel_clock_t *clock)
647 {
648 if (clock->n < limit->n.min || limit->n.max < clock->n)
649 INTELPllInvalid("n out of range\n");
650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
653 INTELPllInvalid("m2 out of range\n");
654 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
655 INTELPllInvalid("m1 out of range\n");
656
657 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
658 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
659 if (clock->m1 <= clock->m2)
660 INTELPllInvalid("m1 <= m2\n");
661
662 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
663 if (clock->p < limit->p.min || limit->p.max < clock->p)
664 INTELPllInvalid("p out of range\n");
665 if (clock->m < limit->m.min || limit->m.max < clock->m)
666 INTELPllInvalid("m out of range\n");
667 }
668
669 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
670 INTELPllInvalid("vco out of range\n");
671 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672 * connector, etc., rather than just a single range.
673 */
674 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
675 INTELPllInvalid("dot out of range\n");
676
677 return true;
678 }
679
680 static int
681 i9xx_select_p2_div(const intel_limit_t *limit,
682 const struct intel_crtc_state *crtc_state,
683 int target)
684 {
685 struct drm_device *dev = crtc_state->base.crtc->dev;
686
687 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
688 /*
689 * For LVDS just rely on its current settings for dual-channel.
690 * We haven't figured out how to reliably set up different
691 * single/dual channel state, if we even can.
692 */
693 if (intel_is_dual_link_lvds(dev))
694 return limit->p2.p2_fast;
695 else
696 return limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 return limit->p2.p2_slow;
700 else
701 return limit->p2.p2_fast;
702 }
703 }
704
705 /*
706 * Returns a set of divisors for the desired target clock with the given
707 * refclk, or FALSE. The returned values represent the clock equation:
708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
709 *
710 * Target and reference clocks are specified in kHz.
711 *
712 * If match_clock is provided, then best_clock P divider must match the P
713 * divider from @match_clock used for LVDS downclocking.
714 */
715 static bool
716 i9xx_find_best_dpll(const intel_limit_t *limit,
717 struct intel_crtc_state *crtc_state,
718 int target, int refclk, intel_clock_t *match_clock,
719 intel_clock_t *best_clock)
720 {
721 struct drm_device *dev = crtc_state->base.crtc->dev;
722 intel_clock_t clock;
723 int err = target;
724
725 memset(best_clock, 0, sizeof(*best_clock));
726
727 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
728
729 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730 clock.m1++) {
731 for (clock.m2 = limit->m2.min;
732 clock.m2 <= limit->m2.max; clock.m2++) {
733 if (clock.m2 >= clock.m1)
734 break;
735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
739 int this_err;
740
741 i9xx_calc_dpll_params(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760 }
761
762 /*
763 * Returns a set of divisors for the desired target clock with the given
764 * refclk, or FALSE. The returned values represent the clock equation:
765 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
766 *
767 * Target and reference clocks are specified in kHz.
768 *
769 * If match_clock is provided, then best_clock P divider must match the P
770 * divider from @match_clock used for LVDS downclocking.
771 */
772 static bool
773 pnv_find_best_dpll(const intel_limit_t *limit,
774 struct intel_crtc_state *crtc_state,
775 int target, int refclk, intel_clock_t *match_clock,
776 intel_clock_t *best_clock)
777 {
778 struct drm_device *dev = crtc_state->base.crtc->dev;
779 intel_clock_t clock;
780 int err = target;
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
787 clock.m1++) {
788 for (clock.m2 = limit->m2.min;
789 clock.m2 <= limit->m2.max; clock.m2++) {
790 for (clock.n = limit->n.min;
791 clock.n <= limit->n.max; clock.n++) {
792 for (clock.p1 = limit->p1.min;
793 clock.p1 <= limit->p1.max; clock.p1++) {
794 int this_err;
795
796 pnv_calc_dpll_params(refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err) {
806 *best_clock = clock;
807 err = this_err;
808 }
809 }
810 }
811 }
812 }
813
814 return (err != target);
815 }
816
817 /*
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821 *
822 * Target and reference clocks are specified in kHz.
823 *
824 * If match_clock is provided, then best_clock P divider must match the P
825 * divider from @match_clock used for LVDS downclocking.
826 */
827 static bool
828 g4x_find_best_dpll(const intel_limit_t *limit,
829 struct intel_crtc_state *crtc_state,
830 int target, int refclk, intel_clock_t *match_clock,
831 intel_clock_t *best_clock)
832 {
833 struct drm_device *dev = crtc_state->base.crtc->dev;
834 intel_clock_t clock;
835 int max_n;
836 bool found = false;
837 /* approximately equals target * 0.00585 */
838 int err_most = (target >> 8) + (target >> 9);
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843
844 max_n = limit->n.max;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847 /* based on hardware requirement, prefere larger m1,m2 */
848 for (clock.m1 = limit->m1.max;
849 clock.m1 >= limit->m1.min; clock.m1--) {
850 for (clock.m2 = limit->m2.max;
851 clock.m2 >= limit->m2.min; clock.m2--) {
852 for (clock.p1 = limit->p1.max;
853 clock.p1 >= limit->p1.min; clock.p1--) {
854 int this_err;
855
856 i9xx_calc_dpll_params(refclk, &clock);
857 if (!intel_PLL_is_valid(dev, limit,
858 &clock))
859 continue;
860
861 this_err = abs(clock.dot - target);
862 if (this_err < err_most) {
863 *best_clock = clock;
864 err_most = this_err;
865 max_n = clock.n;
866 found = true;
867 }
868 }
869 }
870 }
871 }
872 return found;
873 }
874
875 /*
876 * Check if the calculated PLL configuration is more optimal compared to the
877 * best configuration and error found so far. Return the calculated error.
878 */
879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
880 const intel_clock_t *calculated_clock,
881 const intel_clock_t *best_clock,
882 unsigned int best_error_ppm,
883 unsigned int *error_ppm)
884 {
885 /*
886 * For CHV ignore the error and consider only the P value.
887 * Prefer a bigger P value based on HW requirements.
888 */
889 if (IS_CHERRYVIEW(dev)) {
890 *error_ppm = 0;
891
892 return calculated_clock->p > best_clock->p;
893 }
894
895 if (WARN_ON_ONCE(!target_freq))
896 return false;
897
898 *error_ppm = div_u64(1000000ULL *
899 abs(target_freq - calculated_clock->dot),
900 target_freq);
901 /*
902 * Prefer a better P value over a better (smaller) error if the error
903 * is small. Ensure this preference for future configurations too by
904 * setting the error to 0.
905 */
906 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
907 *error_ppm = 0;
908
909 return true;
910 }
911
912 return *error_ppm + 10 < best_error_ppm;
913 }
914
915 /*
916 * Returns a set of divisors for the desired target clock with the given
917 * refclk, or FALSE. The returned values represent the clock equation:
918 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
919 */
920 static bool
921 vlv_find_best_dpll(const intel_limit_t *limit,
922 struct intel_crtc_state *crtc_state,
923 int target, int refclk, intel_clock_t *match_clock,
924 intel_clock_t *best_clock)
925 {
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
927 struct drm_device *dev = crtc->base.dev;
928 intel_clock_t clock;
929 unsigned int bestppm = 1000000;
930 /* min update 19.2 MHz */
931 int max_n = min(limit->n.max, refclk / 19200);
932 bool found = false;
933
934 target *= 5; /* fast clock */
935
936 memset(best_clock, 0, sizeof(*best_clock));
937
938 /* based on hardware requirement, prefer smaller n to precision */
939 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943 clock.p = clock.p1 * clock.p2;
944 /* based on hardware requirement, prefer bigger m1,m2 values */
945 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
946 unsigned int ppm;
947
948 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
949 refclk * clock.m1);
950
951 vlv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit,
954 &clock))
955 continue;
956
957 if (!vlv_PLL_is_optimal(dev, target,
958 &clock,
959 best_clock,
960 bestppm, &ppm))
961 continue;
962
963 *best_clock = clock;
964 bestppm = ppm;
965 found = true;
966 }
967 }
968 }
969 }
970
971 return found;
972 }
973
974 /*
975 * Returns a set of divisors for the desired target clock with the given
976 * refclk, or FALSE. The returned values represent the clock equation:
977 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
978 */
979 static bool
980 chv_find_best_dpll(const intel_limit_t *limit,
981 struct intel_crtc_state *crtc_state,
982 int target, int refclk, intel_clock_t *match_clock,
983 intel_clock_t *best_clock)
984 {
985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986 struct drm_device *dev = crtc->base.dev;
987 unsigned int best_error_ppm;
988 intel_clock_t clock;
989 uint64_t m2;
990 int found = false;
991
992 memset(best_clock, 0, sizeof(*best_clock));
993 best_error_ppm = 1000000;
994
995 /*
996 * Based on hardware doc, the n always set to 1, and m1 always
997 * set to 2. If requires to support 200Mhz refclk, we need to
998 * revisit this because n may not 1 anymore.
999 */
1000 clock.n = 1, clock.m1 = 2;
1001 target *= 5; /* fast clock */
1002
1003 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004 for (clock.p2 = limit->p2.p2_fast;
1005 clock.p2 >= limit->p2.p2_slow;
1006 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007 unsigned int error_ppm;
1008
1009 clock.p = clock.p1 * clock.p2;
1010
1011 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012 clock.n) << 22, refclk * clock.m1);
1013
1014 if (m2 > INT_MAX/clock.m1)
1015 continue;
1016
1017 clock.m2 = m2;
1018
1019 chv_calc_dpll_params(refclk, &clock);
1020
1021 if (!intel_PLL_is_valid(dev, limit, &clock))
1022 continue;
1023
1024 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025 best_error_ppm, &error_ppm))
1026 continue;
1027
1028 *best_clock = clock;
1029 best_error_ppm = error_ppm;
1030 found = true;
1031 }
1032 }
1033
1034 return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038 intel_clock_t *best_clock)
1039 {
1040 int refclk = 100000;
1041 const intel_limit_t *limit = &intel_limits_bxt;
1042
1043 return chv_find_best_dpll(limit, crtc_state,
1044 target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051 /* Be paranoid as we can arrive here with only partial
1052 * state retrieved from the hardware during setup.
1053 *
1054 * We can ditch the adjusted_mode.crtc_clock check as soon
1055 * as Haswell has gained clock readout/fastboot support.
1056 *
1057 * We can ditch the crtc->primary->fb check as soon as we can
1058 * properly reconstruct framebuffers.
1059 *
1060 * FIXME: The intel_crtc->active here should be switched to
1061 * crtc->state->active once we have proper CRTC states wired up
1062 * for atomic.
1063 */
1064 return intel_crtc->active && crtc->primary->state->fb &&
1065 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069 enum pipe pipe)
1070 {
1071 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074 return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 i915_reg_t reg = PIPEDSL(pipe);
1081 u32 line1, line2;
1082 u32 line_mask;
1083
1084 if (IS_GEN2(dev))
1085 line_mask = DSL_LINEMASK_GEN2;
1086 else
1087 line_mask = DSL_LINEMASK_GEN3;
1088
1089 line1 = I915_READ(reg) & line_mask;
1090 msleep(5);
1091 line2 = I915_READ(reg) & line_mask;
1092
1093 return line1 == line2;
1094 }
1095
1096 /*
1097 * intel_wait_for_pipe_off - wait for pipe to turn off
1098 * @crtc: crtc whose pipe to wait for
1099 *
1100 * After disabling a pipe, we can't wait for vblank in the usual way,
1101 * spinning on the vblank interrupt status bit, since we won't actually
1102 * see an interrupt when the pipe is disabled.
1103 *
1104 * On Gen4 and above:
1105 * wait for the pipe register state bit to turn off
1106 *
1107 * Otherwise:
1108 * wait for the display line value to settle (it usually
1109 * ends up stopping at the start of the next frame).
1110 *
1111 */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114 struct drm_device *dev = crtc->base.dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117 enum pipe pipe = crtc->pipe;
1118
1119 if (INTEL_INFO(dev)->gen >= 4) {
1120 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122 /* Wait for the Pipe State to go off */
1123 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124 100))
1125 WARN(1, "pipe_off wait timed out\n");
1126 } else {
1127 /* Wait for the display line to settle */
1128 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 u32 val;
1138 bool cur_state;
1139
1140 val = I915_READ(DPLL(pipe));
1141 cur_state = !!(val & DPLL_VCO_ENABLE);
1142 I915_STATE_WARN(cur_state != state,
1143 "PLL state assertion failure (expected %s, current %s)\n",
1144 onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150 u32 val;
1151 bool cur_state;
1152
1153 mutex_lock(&dev_priv->sb_lock);
1154 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155 mutex_unlock(&dev_priv->sb_lock);
1156
1157 cur_state = val & DSI_PLL_VCO_EN;
1158 I915_STATE_WARN(cur_state != state,
1159 "DSI PLL state assertion failure (expected %s, current %s)\n",
1160 onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1165 {
1166 bool cur_state;
1167 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168 pipe);
1169
1170 if (HAS_DDI(dev_priv)) {
1171 /* DDI does not have a specific FDI_TX register */
1172 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174 } else {
1175 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176 cur_state = !!(val & FDI_TX_ENABLE);
1177 }
1178 I915_STATE_WARN(cur_state != state,
1179 "FDI TX state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 u32 val;
1189 bool cur_state;
1190
1191 val = I915_READ(FDI_RX_CTL(pipe));
1192 cur_state = !!(val & FDI_RX_ENABLE);
1193 I915_STATE_WARN(cur_state != state,
1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202 {
1203 u32 val;
1204
1205 /* ILK FDI PLL is always enabled */
1206 if (INTEL_INFO(dev_priv)->gen == 5)
1207 return;
1208
1209 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210 if (HAS_DDI(dev_priv))
1211 return;
1212
1213 val = I915_READ(FDI_TX_CTL(pipe));
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 u32 val;
1221 bool cur_state;
1222
1223 val = I915_READ(FDI_RX_CTL(pipe));
1224 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227 onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 struct drm_device *dev = dev_priv->dev;
1234 i915_reg_t pp_reg;
1235 u32 val;
1236 enum pipe panel_pipe = PIPE_A;
1237 bool locked = true;
1238
1239 if (WARN_ON(HAS_DDI(dev)))
1240 return;
1241
1242 if (HAS_PCH_SPLIT(dev)) {
1243 u32 port_sel;
1244
1245 pp_reg = PCH_PP_CONTROL;
1246 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250 panel_pipe = PIPE_B;
1251 /* XXX: else fix for eDP */
1252 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253 /* presumably write lock depends on pipe, not port select */
1254 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255 panel_pipe = pipe;
1256 } else {
1257 pp_reg = PP_CONTROL;
1258 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259 panel_pipe = PIPE_B;
1260 }
1261
1262 val = I915_READ(pp_reg);
1263 if (!(val & PANEL_POWER_ON) ||
1264 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265 locked = false;
1266
1267 I915_STATE_WARN(panel_pipe == pipe && locked,
1268 "panel assertion failure, pipe %c regs locked\n",
1269 pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273 enum pipe pipe, bool state)
1274 {
1275 struct drm_device *dev = dev_priv->dev;
1276 bool cur_state;
1277
1278 if (IS_845G(dev) || IS_I865G(dev))
1279 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280 else
1281 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283 I915_STATE_WARN(cur_state != state,
1284 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285 pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291 enum pipe pipe, bool state)
1292 {
1293 bool cur_state;
1294 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295 pipe);
1296 enum intel_display_power_domain power_domain;
1297
1298 /* if we need the pipe quirk it must be always on */
1299 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301 state = true;
1302
1303 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308 intel_display_power_put(dev_priv, power_domain);
1309 } else {
1310 cur_state = false;
1311 }
1312
1313 I915_STATE_WARN(cur_state != state,
1314 "pipe %c assertion failure (expected %s, current %s)\n",
1315 pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319 enum plane plane, bool state)
1320 {
1321 u32 val;
1322 bool cur_state;
1323
1324 val = I915_READ(DSPCNTR(plane));
1325 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326 I915_STATE_WARN(cur_state != state,
1327 "plane %c assertion failure (expected %s, current %s)\n",
1328 plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335 enum pipe pipe)
1336 {
1337 struct drm_device *dev = dev_priv->dev;
1338 int i;
1339
1340 /* Primary planes are fixed to pipes on gen4+ */
1341 if (INTEL_INFO(dev)->gen >= 4) {
1342 u32 val = I915_READ(DSPCNTR(pipe));
1343 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344 "plane %c assertion failure, should be disabled but not\n",
1345 plane_name(pipe));
1346 return;
1347 }
1348
1349 /* Need to check both planes against the pipe */
1350 for_each_pipe(dev_priv, i) {
1351 u32 val = I915_READ(DSPCNTR(i));
1352 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353 DISPPLANE_SEL_PIPE_SHIFT;
1354 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(i), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int sprite;
1365
1366 if (INTEL_INFO(dev)->gen >= 9) {
1367 for_each_sprite(dev_priv, pipe, sprite) {
1368 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371 sprite, pipe_name(pipe));
1372 }
1373 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374 for_each_sprite(dev_priv, pipe, sprite) {
1375 u32 val = I915_READ(SPCNTR(pipe, sprite));
1376 I915_STATE_WARN(val & SP_ENABLE,
1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378 sprite_name(pipe, sprite), pipe_name(pipe));
1379 }
1380 } else if (INTEL_INFO(dev)->gen >= 7) {
1381 u32 val = I915_READ(SPRCTL(pipe));
1382 I915_STATE_WARN(val & SPRITE_ENABLE,
1383 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384 plane_name(pipe), pipe_name(pipe));
1385 } else if (INTEL_INFO(dev)->gen >= 5) {
1386 u32 val = I915_READ(DVSCNTR(pipe));
1387 I915_STATE_WARN(val & DVS_ENABLE,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403 bool enabled;
1404
1405 val = I915_READ(PCH_TRANSCONF(pipe));
1406 enabled = !!(val & TRANS_ENABLE);
1407 I915_STATE_WARN(enabled,
1408 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409 pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415 if ((val & DP_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv)) {
1419 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv)) {
1423 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & SDVO_ENABLE) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 return false;
1441 } else if (IS_CHERRYVIEW(dev_priv)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443 return false;
1444 } else {
1445 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & LVDS_PORT_EN) == 0)
1455 return false;
1456
1457 if (HAS_PCH_CPT(dev_priv)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, u32 val)
1469 {
1470 if ((val & ADPA_DAC_ENABLE) == 0)
1471 return false;
1472 if (HAS_PCH_CPT(dev_priv)) {
1473 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474 return false;
1475 } else {
1476 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, i915_reg_t reg,
1484 u32 port_sel)
1485 {
1486 u32 val = I915_READ(reg);
1487 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489 i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1492 && (val & DP_PIPEB_SELECT),
1493 "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, i915_reg_t reg)
1498 {
1499 u32 val = I915_READ(reg);
1500 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502 i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1505 && (val & SDVO_PIPE_B_SELECT),
1506 "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe)
1511 {
1512 u32 val;
1513
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518 val = I915_READ(PCH_ADPA);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 val = I915_READ(PCH_LVDS);
1524 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526 pipe_name(pipe));
1527
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc,
1534 const struct intel_crtc_state *pipe_config)
1535 {
1536 struct drm_device *dev = crtc->base.dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 enum pipe pipe = crtc->pipe;
1539 i915_reg_t reg = DPLL(pipe);
1540 u32 dpll = pipe_config->dpll_hw_state.dpll;
1541
1542 assert_pipe_disabled(dev_priv, pipe);
1543
1544 /* PLL is protected by panel, make sure we can write it */
1545 assert_panel_unlocked(dev_priv, pipe);
1546
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1553
1554 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(pipe));
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559 const struct intel_crtc_state *pipe_config)
1560 {
1561 struct drm_device *dev = crtc->base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 enum pipe pipe = crtc->pipe;
1564 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1565 u32 tmp;
1566
1567 assert_pipe_disabled(dev_priv, pipe);
1568
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv, pipe);
1571
1572 mutex_lock(&dev_priv->sb_lock);
1573
1574 /* Enable back the 10bit clock to display controller */
1575 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576 tmp |= DPIO_DCLKP_EN;
1577 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579 mutex_unlock(&dev_priv->sb_lock);
1580
1581 /*
1582 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583 */
1584 udelay(1);
1585
1586 /* Enable PLL */
1587 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589 /* Check PLL is locked */
1590 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592
1593 if (pipe != PIPE_A) {
1594 /*
1595 * WaPixelRepeatModeFixForC0:chv
1596 *
1597 * DPLLCMD is AWOL. Use chicken bits to propagate
1598 * the value from DPLLBMD to either pipe B or C.
1599 */
1600 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1601 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1602 I915_WRITE(CBR4_VLV, 0);
1603 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1604
1605 /*
1606 * DPLLB VGA mode also seems to cause problems.
1607 * We should always have it disabled.
1608 */
1609 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1610 } else {
1611 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613 }
1614 }
1615
1616 static int intel_num_dvo_pipes(struct drm_device *dev)
1617 {
1618 struct intel_crtc *crtc;
1619 int count = 0;
1620
1621 for_each_intel_crtc(dev, crtc)
1622 count += crtc->base.state->active &&
1623 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1624
1625 return count;
1626 }
1627
1628 static void i9xx_enable_pll(struct intel_crtc *crtc)
1629 {
1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 i915_reg_t reg = DPLL(crtc->pipe);
1633 u32 dpll = crtc->config->dpll_hw_state.dpll;
1634
1635 assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637 /* PLL is protected by panel, make sure we can write it */
1638 if (IS_MOBILE(dev) && !IS_I830(dev))
1639 assert_panel_unlocked(dev_priv, crtc->pipe);
1640
1641 /* Enable DVO 2x clock on both PLLs if necessary */
1642 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1643 /*
1644 * It appears to be important that we don't enable this
1645 * for the current pipe before otherwise configuring the
1646 * PLL. No idea how this should be handled if multiple
1647 * DVO outputs are enabled simultaneosly.
1648 */
1649 dpll |= DPLL_DVO_2X_MODE;
1650 I915_WRITE(DPLL(!crtc->pipe),
1651 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1652 }
1653
1654 /*
1655 * Apparently we need to have VGA mode enabled prior to changing
1656 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657 * dividers, even though the register value does change.
1658 */
1659 I915_WRITE(reg, 0);
1660
1661 I915_WRITE(reg, dpll);
1662
1663 /* Wait for the clocks to stabilize. */
1664 POSTING_READ(reg);
1665 udelay(150);
1666
1667 if (INTEL_INFO(dev)->gen >= 4) {
1668 I915_WRITE(DPLL_MD(crtc->pipe),
1669 crtc->config->dpll_hw_state.dpll_md);
1670 } else {
1671 /* The pixel multiplier can only be updated once the
1672 * DPLL is enabled and the clocks are stable.
1673 *
1674 * So write it again.
1675 */
1676 I915_WRITE(reg, dpll);
1677 }
1678
1679 /* We do this three times for luck */
1680 I915_WRITE(reg, dpll);
1681 POSTING_READ(reg);
1682 udelay(150); /* wait for warmup */
1683 I915_WRITE(reg, dpll);
1684 POSTING_READ(reg);
1685 udelay(150); /* wait for warmup */
1686 I915_WRITE(reg, dpll);
1687 POSTING_READ(reg);
1688 udelay(150); /* wait for warmup */
1689 }
1690
1691 /**
1692 * i9xx_disable_pll - disable a PLL
1693 * @dev_priv: i915 private structure
1694 * @pipe: pipe PLL to disable
1695 *
1696 * Disable the PLL for @pipe, making sure the pipe is off first.
1697 *
1698 * Note! This is for pre-ILK only.
1699 */
1700 static void i9xx_disable_pll(struct intel_crtc *crtc)
1701 {
1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 enum pipe pipe = crtc->pipe;
1705
1706 /* Disable DVO 2x clock on both PLLs if necessary */
1707 if (IS_I830(dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1709 !intel_num_dvo_pipes(dev)) {
1710 I915_WRITE(DPLL(PIPE_B),
1711 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1712 I915_WRITE(DPLL(PIPE_A),
1713 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Don't disable pipe or pipe PLLs if needed */
1717 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1718 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1719 return;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 u32 val;
1731
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv, pipe);
1734
1735 val = DPLL_INTEGRATED_REF_CLK_VLV |
1736 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737 if (pipe != PIPE_A)
1738 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740 I915_WRITE(DPLL(pipe), val);
1741 POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1747 u32 val;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
1752 val = DPLL_SSC_REF_CLK_CHV |
1753 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754 if (pipe != PIPE_A)
1755 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757 I915_WRITE(DPLL(pipe), val);
1758 POSTING_READ(DPLL(pipe));
1759
1760 mutex_lock(&dev_priv->sb_lock);
1761
1762 /* Disable 10bit clock to display controller */
1763 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1764 val &= ~DPIO_DCLKP_EN;
1765 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1766
1767 mutex_unlock(&dev_priv->sb_lock);
1768 }
1769
1770 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1771 struct intel_digital_port *dport,
1772 unsigned int expected_mask)
1773 {
1774 u32 port_mask;
1775 i915_reg_t dpll_reg;
1776
1777 switch (dport->port) {
1778 case PORT_B:
1779 port_mask = DPLL_PORTB_READY_MASK;
1780 dpll_reg = DPLL(0);
1781 break;
1782 case PORT_C:
1783 port_mask = DPLL_PORTC_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 expected_mask <<= 4;
1786 break;
1787 case PORT_D:
1788 port_mask = DPLL_PORTD_READY_MASK;
1789 dpll_reg = DPIO_PHY_STATUS;
1790 break;
1791 default:
1792 BUG();
1793 }
1794
1795 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1796 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1798 }
1799
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1801 enum pipe pipe)
1802 {
1803 struct drm_device *dev = dev_priv->dev;
1804 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 i915_reg_t reg;
1807 uint32_t val, pipeconf_val;
1808
1809 /* Make sure PCH DPLL is enabled */
1810 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1811
1812 /* FDI must be feeding us bits for PCH ports */
1813 assert_fdi_tx_enabled(dev_priv, pipe);
1814 assert_fdi_rx_enabled(dev_priv, pipe);
1815
1816 if (HAS_PCH_CPT(dev)) {
1817 /* Workaround: Set the timing override bit before enabling the
1818 * pch transcoder. */
1819 reg = TRANS_CHICKEN2(pipe);
1820 val = I915_READ(reg);
1821 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1822 I915_WRITE(reg, val);
1823 }
1824
1825 reg = PCH_TRANSCONF(pipe);
1826 val = I915_READ(reg);
1827 pipeconf_val = I915_READ(PIPECONF(pipe));
1828
1829 if (HAS_PCH_IBX(dev_priv)) {
1830 /*
1831 * Make the BPC in transcoder be consistent with
1832 * that in pipeconf reg. For HDMI we must use 8bpc
1833 * here for both 8bpc and 12bpc.
1834 */
1835 val &= ~PIPECONF_BPC_MASK;
1836 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1837 val |= PIPECONF_8BPC;
1838 else
1839 val |= pipeconf_val & PIPECONF_BPC_MASK;
1840 }
1841
1842 val &= ~TRANS_INTERLACE_MASK;
1843 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1844 if (HAS_PCH_IBX(dev_priv) &&
1845 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1846 val |= TRANS_LEGACY_INTERLACED_ILK;
1847 else
1848 val |= TRANS_INTERLACED;
1849 else
1850 val |= TRANS_PROGRESSIVE;
1851
1852 I915_WRITE(reg, val | TRANS_ENABLE);
1853 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1854 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1855 }
1856
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858 enum transcoder cpu_transcoder)
1859 {
1860 u32 val, pipeconf_val;
1861
1862 /* FDI must be feeding us bits for PCH ports */
1863 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1864 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1865
1866 /* Workaround: set timing override bit. */
1867 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870
1871 val = TRANS_ENABLE;
1872 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873
1874 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1875 PIPECONF_INTERLACED_ILK)
1876 val |= TRANS_INTERLACED;
1877 else
1878 val |= TRANS_PROGRESSIVE;
1879
1880 I915_WRITE(LPT_TRANSCONF, val);
1881 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1882 DRM_ERROR("Failed to enable PCH transcoder\n");
1883 }
1884
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 struct drm_device *dev = dev_priv->dev;
1889 i915_reg_t reg;
1890 uint32_t val;
1891
1892 /* FDI relies on the transcoder */
1893 assert_fdi_tx_disabled(dev_priv, pipe);
1894 assert_fdi_rx_disabled(dev_priv, pipe);
1895
1896 /* Ports must be off as well */
1897 assert_pch_ports_disabled(dev_priv, pipe);
1898
1899 reg = PCH_TRANSCONF(pipe);
1900 val = I915_READ(reg);
1901 val &= ~TRANS_ENABLE;
1902 I915_WRITE(reg, val);
1903 /* wait for PCH transcoder off, transcoder state */
1904 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1905 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1906
1907 if (HAS_PCH_CPT(dev)) {
1908 /* Workaround: Clear the timing override chicken bit again. */
1909 reg = TRANS_CHICKEN2(pipe);
1910 val = I915_READ(reg);
1911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(reg, val);
1913 }
1914 }
1915
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1917 {
1918 u32 val;
1919
1920 val = I915_READ(LPT_TRANSCONF);
1921 val &= ~TRANS_ENABLE;
1922 I915_WRITE(LPT_TRANSCONF, val);
1923 /* wait for PCH transcoder off, transcoder state */
1924 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1925 DRM_ERROR("Failed to disable PCH transcoder\n");
1926
1927 /* Workaround: clear timing override bit. */
1928 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1929 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1931 }
1932
1933 /**
1934 * intel_enable_pipe - enable a pipe, asserting requirements
1935 * @crtc: crtc responsible for the pipe
1936 *
1937 * Enable @crtc's pipe, making sure that various hardware specific requirements
1938 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939 */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 enum pipe pipe = crtc->pipe;
1945 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946 enum pipe pch_transcoder;
1947 i915_reg_t reg;
1948 u32 val;
1949
1950 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1951
1952 assert_planes_disabled(dev_priv, pipe);
1953 assert_cursor_disabled(dev_priv, pipe);
1954 assert_sprites_disabled(dev_priv, pipe);
1955
1956 if (HAS_PCH_LPT(dev_priv))
1957 pch_transcoder = TRANSCODER_A;
1958 else
1959 pch_transcoder = pipe;
1960
1961 /*
1962 * A pipe without a PLL won't actually be able to drive bits from
1963 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1964 * need the check.
1965 */
1966 if (HAS_GMCH_DISPLAY(dev_priv))
1967 if (crtc->config->has_dsi_encoder)
1968 assert_dsi_pll_enabled(dev_priv);
1969 else
1970 assert_pll_enabled(dev_priv, pipe);
1971 else {
1972 if (crtc->config->has_pch_encoder) {
1973 /* if driving the PCH, we need FDI enabled */
1974 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1975 assert_fdi_tx_pll_enabled(dev_priv,
1976 (enum pipe) cpu_transcoder);
1977 }
1978 /* FIXME: assert CPU port conditions for SNB+ */
1979 }
1980
1981 reg = PIPECONF(cpu_transcoder);
1982 val = I915_READ(reg);
1983 if (val & PIPECONF_ENABLE) {
1984 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1985 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1986 return;
1987 }
1988
1989 I915_WRITE(reg, val | PIPECONF_ENABLE);
1990 POSTING_READ(reg);
1991
1992 /*
1993 * Until the pipe starts DSL will read as 0, which would cause
1994 * an apparent vblank timestamp jump, which messes up also the
1995 * frame count when it's derived from the timestamps. So let's
1996 * wait for the pipe to start properly before we call
1997 * drm_crtc_vblank_on()
1998 */
1999 if (dev->max_vblank_count == 0 &&
2000 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2001 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2002 }
2003
2004 /**
2005 * intel_disable_pipe - disable a pipe, asserting requirements
2006 * @crtc: crtc whose pipes is to be disabled
2007 *
2008 * Disable the pipe of @crtc, making sure that various hardware
2009 * specific requirements are met, if applicable, e.g. plane
2010 * disabled, panel fitter off, etc.
2011 *
2012 * Will wait until the pipe has shut down before returning.
2013 */
2014 static void intel_disable_pipe(struct intel_crtc *crtc)
2015 {
2016 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2018 enum pipe pipe = crtc->pipe;
2019 i915_reg_t reg;
2020 u32 val;
2021
2022 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2023
2024 /*
2025 * Make sure planes won't keep trying to pump pixels to us,
2026 * or we might hang the display.
2027 */
2028 assert_planes_disabled(dev_priv, pipe);
2029 assert_cursor_disabled(dev_priv, pipe);
2030 assert_sprites_disabled(dev_priv, pipe);
2031
2032 reg = PIPECONF(cpu_transcoder);
2033 val = I915_READ(reg);
2034 if ((val & PIPECONF_ENABLE) == 0)
2035 return;
2036
2037 /*
2038 * Double wide has implications for planes
2039 * so best keep it disabled when not needed.
2040 */
2041 if (crtc->config->double_wide)
2042 val &= ~PIPECONF_DOUBLE_WIDE;
2043
2044 /* Don't disable pipe or pipe PLLs if needed */
2045 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2046 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2047 val &= ~PIPECONF_ENABLE;
2048
2049 I915_WRITE(reg, val);
2050 if ((val & PIPECONF_ENABLE) == 0)
2051 intel_wait_for_pipe_off(crtc);
2052 }
2053
2054 static bool need_vtd_wa(struct drm_device *dev)
2055 {
2056 #ifdef CONFIG_INTEL_IOMMU
2057 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2058 return true;
2059 #endif
2060 return false;
2061 }
2062
2063 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2064 {
2065 return IS_GEN2(dev_priv) ? 2048 : 4096;
2066 }
2067
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2069 uint64_t fb_modifier, unsigned int cpp)
2070 {
2071 switch (fb_modifier) {
2072 case DRM_FORMAT_MOD_NONE:
2073 return cpp;
2074 case I915_FORMAT_MOD_X_TILED:
2075 if (IS_GEN2(dev_priv))
2076 return 128;
2077 else
2078 return 512;
2079 case I915_FORMAT_MOD_Y_TILED:
2080 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2081 return 128;
2082 else
2083 return 512;
2084 case I915_FORMAT_MOD_Yf_TILED:
2085 switch (cpp) {
2086 case 1:
2087 return 64;
2088 case 2:
2089 case 4:
2090 return 128;
2091 case 8:
2092 case 16:
2093 return 256;
2094 default:
2095 MISSING_CASE(cpp);
2096 return cpp;
2097 }
2098 break;
2099 default:
2100 MISSING_CASE(fb_modifier);
2101 return cpp;
2102 }
2103 }
2104
2105 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2106 uint64_t fb_modifier, unsigned int cpp)
2107 {
2108 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2109 return 1;
2110 else
2111 return intel_tile_size(dev_priv) /
2112 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2113 }
2114
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2117 unsigned int *tile_width,
2118 unsigned int *tile_height,
2119 uint64_t fb_modifier,
2120 unsigned int cpp)
2121 {
2122 unsigned int tile_width_bytes =
2123 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2124
2125 *tile_width = tile_width_bytes / cpp;
2126 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2127 }
2128
2129 unsigned int
2130 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2131 uint32_t pixel_format, uint64_t fb_modifier)
2132 {
2133 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2134 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2135
2136 return ALIGN(height, tile_height);
2137 }
2138
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2140 {
2141 unsigned int size = 0;
2142 int i;
2143
2144 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2145 size += rot_info->plane[i].width * rot_info->plane[i].height;
2146
2147 return size;
2148 }
2149
2150 static void
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2152 const struct drm_framebuffer *fb,
2153 unsigned int rotation)
2154 {
2155 if (intel_rotation_90_or_270(rotation)) {
2156 *view = i915_ggtt_view_rotated;
2157 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2158 } else {
2159 *view = i915_ggtt_view_normal;
2160 }
2161 }
2162
2163 static void
2164 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2165 struct drm_framebuffer *fb)
2166 {
2167 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2168 unsigned int tile_size, tile_width, tile_height, cpp;
2169
2170 tile_size = intel_tile_size(dev_priv);
2171
2172 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2173 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2174 fb->modifier[0], cpp);
2175
2176 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2177 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2178
2179 if (info->pixel_format == DRM_FORMAT_NV12) {
2180 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2181 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2182 fb->modifier[1], cpp);
2183
2184 info->uv_offset = fb->offsets[1];
2185 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2186 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2187 }
2188 }
2189
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2191 {
2192 if (INTEL_INFO(dev_priv)->gen >= 9)
2193 return 256 * 1024;
2194 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2195 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2196 return 128 * 1024;
2197 else if (INTEL_INFO(dev_priv)->gen >= 4)
2198 return 4 * 1024;
2199 else
2200 return 0;
2201 }
2202
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2204 uint64_t fb_modifier)
2205 {
2206 switch (fb_modifier) {
2207 case DRM_FORMAT_MOD_NONE:
2208 return intel_linear_alignment(dev_priv);
2209 case I915_FORMAT_MOD_X_TILED:
2210 if (INTEL_INFO(dev_priv)->gen >= 9)
2211 return 256 * 1024;
2212 return 0;
2213 case I915_FORMAT_MOD_Y_TILED:
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 return 1 * 1024 * 1024;
2216 default:
2217 MISSING_CASE(fb_modifier);
2218 return 0;
2219 }
2220 }
2221
2222 int
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2224 unsigned int rotation)
2225 {
2226 struct drm_device *dev = fb->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2229 struct i915_ggtt_view view;
2230 u32 alignment;
2231 int ret;
2232
2233 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2234
2235 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2236
2237 intel_fill_fb_ggtt_view(&view, fb, rotation);
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 intel_runtime_pm_get(dev_priv);
2255
2256 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2257 &view);
2258 if (ret)
2259 goto err_pm;
2260
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2265 */
2266 if (view.type == I915_GGTT_VIEW_NORMAL) {
2267 ret = i915_gem_object_get_fence(obj);
2268 if (ret == -EDEADLK) {
2269 /*
2270 * -EDEADLK means there are no free fences
2271 * no pending flips.
2272 *
2273 * This is propagated to atomic, but it uses
2274 * -EDEADLK to force a locking recovery, so
2275 * change the returned error to -EBUSY.
2276 */
2277 ret = -EBUSY;
2278 goto err_unpin;
2279 } else if (ret)
2280 goto err_unpin;
2281
2282 i915_gem_object_pin_fence(obj);
2283 }
2284
2285 intel_runtime_pm_put(dev_priv);
2286 return 0;
2287
2288 err_unpin:
2289 i915_gem_object_unpin_from_display_plane(obj, &view);
2290 err_pm:
2291 intel_runtime_pm_put(dev_priv);
2292 return ret;
2293 }
2294
2295 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2296 {
2297 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2298 struct i915_ggtt_view view;
2299
2300 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2301
2302 intel_fill_fb_ggtt_view(&view, fb, rotation);
2303
2304 if (view.type == I915_GGTT_VIEW_NORMAL)
2305 i915_gem_object_unpin_fence(obj);
2306
2307 i915_gem_object_unpin_from_display_plane(obj, &view);
2308 }
2309
2310 /*
2311 * Adjust the tile offset by moving the difference into
2312 * the x/y offsets.
2313 *
2314 * Input tile dimensions and pitch must already be
2315 * rotated to match x and y, and in pixel units.
2316 */
2317 static u32 intel_adjust_tile_offset(int *x, int *y,
2318 unsigned int tile_width,
2319 unsigned int tile_height,
2320 unsigned int tile_size,
2321 unsigned int pitch_tiles,
2322 u32 old_offset,
2323 u32 new_offset)
2324 {
2325 unsigned int tiles;
2326
2327 WARN_ON(old_offset & (tile_size - 1));
2328 WARN_ON(new_offset & (tile_size - 1));
2329 WARN_ON(new_offset > old_offset);
2330
2331 tiles = (old_offset - new_offset) / tile_size;
2332
2333 *y += tiles / pitch_tiles * tile_height;
2334 *x += tiles % pitch_tiles * tile_width;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Computes the linear offset to the base tile and adjusts
2341 * x, y. bytes per pixel is assumed to be a power-of-two.
2342 *
2343 * In the 90/270 rotated case, x and y are assumed
2344 * to be already rotated to match the rotated GTT view, and
2345 * pitch is the tile_height aligned framebuffer height.
2346 */
2347 u32 intel_compute_tile_offset(int *x, int *y,
2348 const struct drm_framebuffer *fb, int plane,
2349 unsigned int pitch,
2350 unsigned int rotation)
2351 {
2352 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2353 uint64_t fb_modifier = fb->modifier[plane];
2354 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2355 u32 offset, offset_aligned, alignment;
2356
2357 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2358 if (alignment)
2359 alignment--;
2360
2361 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2362 unsigned int tile_size, tile_width, tile_height;
2363 unsigned int tile_rows, tiles, pitch_tiles;
2364
2365 tile_size = intel_tile_size(dev_priv);
2366 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2367 fb_modifier, cpp);
2368
2369 if (intel_rotation_90_or_270(rotation)) {
2370 pitch_tiles = pitch / tile_height;
2371 swap(tile_width, tile_height);
2372 } else {
2373 pitch_tiles = pitch / (tile_width * cpp);
2374 }
2375
2376 tile_rows = *y / tile_height;
2377 *y %= tile_height;
2378
2379 tiles = *x / tile_width;
2380 *x %= tile_width;
2381
2382 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2383 offset_aligned = offset & ~alignment;
2384
2385 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2386 tile_size, pitch_tiles,
2387 offset, offset_aligned);
2388 } else {
2389 offset = *y * pitch + *x * cpp;
2390 offset_aligned = offset & ~alignment;
2391
2392 *y = (offset & alignment) / pitch;
2393 *x = ((offset & alignment) - *y * pitch) / cpp;
2394 }
2395
2396 return offset_aligned;
2397 }
2398
2399 static int i9xx_format_to_fourcc(int format)
2400 {
2401 switch (format) {
2402 case DISPPLANE_8BPP:
2403 return DRM_FORMAT_C8;
2404 case DISPPLANE_BGRX555:
2405 return DRM_FORMAT_XRGB1555;
2406 case DISPPLANE_BGRX565:
2407 return DRM_FORMAT_RGB565;
2408 default:
2409 case DISPPLANE_BGRX888:
2410 return DRM_FORMAT_XRGB8888;
2411 case DISPPLANE_RGBX888:
2412 return DRM_FORMAT_XBGR8888;
2413 case DISPPLANE_BGRX101010:
2414 return DRM_FORMAT_XRGB2101010;
2415 case DISPPLANE_RGBX101010:
2416 return DRM_FORMAT_XBGR2101010;
2417 }
2418 }
2419
2420 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2421 {
2422 switch (format) {
2423 case PLANE_CTL_FORMAT_RGB_565:
2424 return DRM_FORMAT_RGB565;
2425 default:
2426 case PLANE_CTL_FORMAT_XRGB_8888:
2427 if (rgb_order) {
2428 if (alpha)
2429 return DRM_FORMAT_ABGR8888;
2430 else
2431 return DRM_FORMAT_XBGR8888;
2432 } else {
2433 if (alpha)
2434 return DRM_FORMAT_ARGB8888;
2435 else
2436 return DRM_FORMAT_XRGB8888;
2437 }
2438 case PLANE_CTL_FORMAT_XRGB_2101010:
2439 if (rgb_order)
2440 return DRM_FORMAT_XBGR2101010;
2441 else
2442 return DRM_FORMAT_XRGB2101010;
2443 }
2444 }
2445
2446 static bool
2447 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2448 struct intel_initial_plane_config *plane_config)
2449 {
2450 struct drm_device *dev = crtc->base.dev;
2451 struct drm_i915_private *dev_priv = to_i915(dev);
2452 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2453 struct drm_i915_gem_object *obj = NULL;
2454 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2455 struct drm_framebuffer *fb = &plane_config->fb->base;
2456 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2457 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2458 PAGE_SIZE);
2459
2460 size_aligned -= base_aligned;
2461
2462 if (plane_config->size == 0)
2463 return false;
2464
2465 /* If the FB is too big, just don't use it since fbdev is not very
2466 * important and we should probably use that space with FBC or other
2467 * features. */
2468 if (size_aligned * 2 > ggtt->stolen_usable_size)
2469 return false;
2470
2471 mutex_lock(&dev->struct_mutex);
2472
2473 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2474 base_aligned,
2475 base_aligned,
2476 size_aligned);
2477 if (!obj) {
2478 mutex_unlock(&dev->struct_mutex);
2479 return false;
2480 }
2481
2482 obj->tiling_mode = plane_config->tiling;
2483 if (obj->tiling_mode == I915_TILING_X)
2484 obj->stride = fb->pitches[0];
2485
2486 mode_cmd.pixel_format = fb->pixel_format;
2487 mode_cmd.width = fb->width;
2488 mode_cmd.height = fb->height;
2489 mode_cmd.pitches[0] = fb->pitches[0];
2490 mode_cmd.modifier[0] = fb->modifier[0];
2491 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2492
2493 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2494 &mode_cmd, obj)) {
2495 DRM_DEBUG_KMS("intel fb init failed\n");
2496 goto out_unref_obj;
2497 }
2498
2499 mutex_unlock(&dev->struct_mutex);
2500
2501 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2502 return true;
2503
2504 out_unref_obj:
2505 drm_gem_object_unreference(&obj->base);
2506 mutex_unlock(&dev->struct_mutex);
2507 return false;
2508 }
2509
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2511 static void
2512 update_state_fb(struct drm_plane *plane)
2513 {
2514 if (plane->fb == plane->state->fb)
2515 return;
2516
2517 if (plane->state->fb)
2518 drm_framebuffer_unreference(plane->state->fb);
2519 plane->state->fb = plane->fb;
2520 if (plane->state->fb)
2521 drm_framebuffer_reference(plane->state->fb);
2522 }
2523
2524 static void
2525 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2526 struct intel_initial_plane_config *plane_config)
2527 {
2528 struct drm_device *dev = intel_crtc->base.dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct drm_crtc *c;
2531 struct intel_crtc *i;
2532 struct drm_i915_gem_object *obj;
2533 struct drm_plane *primary = intel_crtc->base.primary;
2534 struct drm_plane_state *plane_state = primary->state;
2535 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2536 struct intel_plane *intel_plane = to_intel_plane(primary);
2537 struct intel_plane_state *intel_state =
2538 to_intel_plane_state(plane_state);
2539 struct drm_framebuffer *fb;
2540
2541 if (!plane_config->fb)
2542 return;
2543
2544 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2545 fb = &plane_config->fb->base;
2546 goto valid_fb;
2547 }
2548
2549 kfree(plane_config->fb);
2550
2551 /*
2552 * Failed to alloc the obj, check to see if we should share
2553 * an fb with another CRTC instead
2554 */
2555 for_each_crtc(dev, c) {
2556 i = to_intel_crtc(c);
2557
2558 if (c == &intel_crtc->base)
2559 continue;
2560
2561 if (!i->active)
2562 continue;
2563
2564 fb = c->primary->fb;
2565 if (!fb)
2566 continue;
2567
2568 obj = intel_fb_obj(fb);
2569 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2570 drm_framebuffer_reference(fb);
2571 goto valid_fb;
2572 }
2573 }
2574
2575 /*
2576 * We've failed to reconstruct the BIOS FB. Current display state
2577 * indicates that the primary plane is visible, but has a NULL FB,
2578 * which will lead to problems later if we don't fix it up. The
2579 * simplest solution is to just disable the primary plane now and
2580 * pretend the BIOS never had it enabled.
2581 */
2582 to_intel_plane_state(plane_state)->visible = false;
2583 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2584 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2585 intel_plane->disable_plane(primary, &intel_crtc->base);
2586
2587 return;
2588
2589 valid_fb:
2590 plane_state->src_x = 0;
2591 plane_state->src_y = 0;
2592 plane_state->src_w = fb->width << 16;
2593 plane_state->src_h = fb->height << 16;
2594
2595 plane_state->crtc_x = 0;
2596 plane_state->crtc_y = 0;
2597 plane_state->crtc_w = fb->width;
2598 plane_state->crtc_h = fb->height;
2599
2600 intel_state->src.x1 = plane_state->src_x;
2601 intel_state->src.y1 = plane_state->src_y;
2602 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2603 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2604 intel_state->dst.x1 = plane_state->crtc_x;
2605 intel_state->dst.y1 = plane_state->crtc_y;
2606 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2607 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2608
2609 obj = intel_fb_obj(fb);
2610 if (obj->tiling_mode != I915_TILING_NONE)
2611 dev_priv->preserve_bios_swizzle = true;
2612
2613 drm_framebuffer_reference(fb);
2614 primary->fb = primary->state->fb = fb;
2615 primary->crtc = primary->state->crtc = &intel_crtc->base;
2616 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2617 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2618 }
2619
2620 static void i9xx_update_primary_plane(struct drm_plane *primary,
2621 const struct intel_crtc_state *crtc_state,
2622 const struct intel_plane_state *plane_state)
2623 {
2624 struct drm_device *dev = primary->dev;
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2627 struct drm_framebuffer *fb = plane_state->base.fb;
2628 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2629 int plane = intel_crtc->plane;
2630 u32 linear_offset;
2631 u32 dspcntr;
2632 i915_reg_t reg = DSPCNTR(plane);
2633 unsigned int rotation = plane_state->base.rotation;
2634 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2635 int x = plane_state->src.x1 >> 16;
2636 int y = plane_state->src.y1 >> 16;
2637
2638 dspcntr = DISPPLANE_GAMMA_ENABLE;
2639
2640 dspcntr |= DISPLAY_PLANE_ENABLE;
2641
2642 if (INTEL_INFO(dev)->gen < 4) {
2643 if (intel_crtc->pipe == PIPE_B)
2644 dspcntr |= DISPPLANE_SEL_PIPE_B;
2645
2646 /* pipesrc and dspsize control the size that is scaled from,
2647 * which should always be the user's requested size.
2648 */
2649 I915_WRITE(DSPSIZE(plane),
2650 ((crtc_state->pipe_src_h - 1) << 16) |
2651 (crtc_state->pipe_src_w - 1));
2652 I915_WRITE(DSPPOS(plane), 0);
2653 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2654 I915_WRITE(PRIMSIZE(plane),
2655 ((crtc_state->pipe_src_h - 1) << 16) |
2656 (crtc_state->pipe_src_w - 1));
2657 I915_WRITE(PRIMPOS(plane), 0);
2658 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2659 }
2660
2661 switch (fb->pixel_format) {
2662 case DRM_FORMAT_C8:
2663 dspcntr |= DISPPLANE_8BPP;
2664 break;
2665 case DRM_FORMAT_XRGB1555:
2666 dspcntr |= DISPPLANE_BGRX555;
2667 break;
2668 case DRM_FORMAT_RGB565:
2669 dspcntr |= DISPPLANE_BGRX565;
2670 break;
2671 case DRM_FORMAT_XRGB8888:
2672 dspcntr |= DISPPLANE_BGRX888;
2673 break;
2674 case DRM_FORMAT_XBGR8888:
2675 dspcntr |= DISPPLANE_RGBX888;
2676 break;
2677 case DRM_FORMAT_XRGB2101010:
2678 dspcntr |= DISPPLANE_BGRX101010;
2679 break;
2680 case DRM_FORMAT_XBGR2101010:
2681 dspcntr |= DISPPLANE_RGBX101010;
2682 break;
2683 default:
2684 BUG();
2685 }
2686
2687 if (INTEL_INFO(dev)->gen >= 4 &&
2688 obj->tiling_mode != I915_TILING_NONE)
2689 dspcntr |= DISPPLANE_TILED;
2690
2691 if (IS_G4X(dev))
2692 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2693
2694 linear_offset = y * fb->pitches[0] + x * cpp;
2695
2696 if (INTEL_INFO(dev)->gen >= 4) {
2697 intel_crtc->dspaddr_offset =
2698 intel_compute_tile_offset(&x, &y, fb, 0,
2699 fb->pitches[0], rotation);
2700 linear_offset -= intel_crtc->dspaddr_offset;
2701 } else {
2702 intel_crtc->dspaddr_offset = linear_offset;
2703 }
2704
2705 if (rotation == BIT(DRM_ROTATE_180)) {
2706 dspcntr |= DISPPLANE_ROTATE_180;
2707
2708 x += (crtc_state->pipe_src_w - 1);
2709 y += (crtc_state->pipe_src_h - 1);
2710
2711 /* Finding the last pixel of the last line of the display
2712 data and adding to linear_offset*/
2713 linear_offset +=
2714 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2715 (crtc_state->pipe_src_w - 1) * cpp;
2716 }
2717
2718 intel_crtc->adjusted_x = x;
2719 intel_crtc->adjusted_y = y;
2720
2721 I915_WRITE(reg, dspcntr);
2722
2723 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2724 if (INTEL_INFO(dev)->gen >= 4) {
2725 I915_WRITE(DSPSURF(plane),
2726 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2727 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2728 I915_WRITE(DSPLINOFF(plane), linear_offset);
2729 } else
2730 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2731 POSTING_READ(reg);
2732 }
2733
2734 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2735 struct drm_crtc *crtc)
2736 {
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int plane = intel_crtc->plane;
2741
2742 I915_WRITE(DSPCNTR(plane), 0);
2743 if (INTEL_INFO(dev_priv)->gen >= 4)
2744 I915_WRITE(DSPSURF(plane), 0);
2745 else
2746 I915_WRITE(DSPADDR(plane), 0);
2747 POSTING_READ(DSPCNTR(plane));
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_plane *primary,
2751 const struct intel_crtc_state *crtc_state,
2752 const struct intel_plane_state *plane_state)
2753 {
2754 struct drm_device *dev = primary->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2757 struct drm_framebuffer *fb = plane_state->base.fb;
2758 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2759 int plane = intel_crtc->plane;
2760 u32 linear_offset;
2761 u32 dspcntr;
2762 i915_reg_t reg = DSPCNTR(plane);
2763 unsigned int rotation = plane_state->base.rotation;
2764 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2765 int x = plane_state->src.x1 >> 16;
2766 int y = plane_state->src.y1 >> 16;
2767
2768 dspcntr = DISPPLANE_GAMMA_ENABLE;
2769 dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774 switch (fb->pixel_format) {
2775 case DRM_FORMAT_C8:
2776 dspcntr |= DISPPLANE_8BPP;
2777 break;
2778 case DRM_FORMAT_RGB565:
2779 dspcntr |= DISPPLANE_BGRX565;
2780 break;
2781 case DRM_FORMAT_XRGB8888:
2782 dspcntr |= DISPPLANE_BGRX888;
2783 break;
2784 case DRM_FORMAT_XBGR8888:
2785 dspcntr |= DISPPLANE_RGBX888;
2786 break;
2787 case DRM_FORMAT_XRGB2101010:
2788 dspcntr |= DISPPLANE_BGRX101010;
2789 break;
2790 case DRM_FORMAT_XBGR2101010:
2791 dspcntr |= DISPPLANE_RGBX101010;
2792 break;
2793 default:
2794 BUG();
2795 }
2796
2797 if (obj->tiling_mode != I915_TILING_NONE)
2798 dspcntr |= DISPPLANE_TILED;
2799
2800 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803 linear_offset = y * fb->pitches[0] + x * cpp;
2804 intel_crtc->dspaddr_offset =
2805 intel_compute_tile_offset(&x, &y, fb, 0,
2806 fb->pitches[0], rotation);
2807 linear_offset -= intel_crtc->dspaddr_offset;
2808 if (rotation == BIT(DRM_ROTATE_180)) {
2809 dspcntr |= DISPPLANE_ROTATE_180;
2810
2811 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2812 x += (crtc_state->pipe_src_w - 1);
2813 y += (crtc_state->pipe_src_h - 1);
2814
2815 /* Finding the last pixel of the last line of the display
2816 data and adding to linear_offset*/
2817 linear_offset +=
2818 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2819 (crtc_state->pipe_src_w - 1) * cpp;
2820 }
2821 }
2822
2823 intel_crtc->adjusted_x = x;
2824 intel_crtc->adjusted_y = y;
2825
2826 I915_WRITE(reg, dspcntr);
2827
2828 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2829 I915_WRITE(DSPSURF(plane),
2830 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2831 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2832 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833 } else {
2834 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836 }
2837 POSTING_READ(reg);
2838 }
2839
2840 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2841 uint64_t fb_modifier, uint32_t pixel_format)
2842 {
2843 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2844 return 64;
2845 } else {
2846 int cpp = drm_format_plane_cpp(pixel_format, 0);
2847
2848 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2849 }
2850 }
2851
2852 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2853 struct drm_i915_gem_object *obj,
2854 unsigned int plane)
2855 {
2856 struct i915_ggtt_view view;
2857 struct i915_vma *vma;
2858 u64 offset;
2859
2860 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2861 intel_plane->base.state->rotation);
2862
2863 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2864 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2865 view.type))
2866 return -1;
2867
2868 offset = vma->node.start;
2869
2870 if (plane == 1) {
2871 offset += vma->ggtt_view.params.rotated.uv_start_page *
2872 PAGE_SIZE;
2873 }
2874
2875 WARN_ON(upper_32_bits(offset));
2876
2877 return lower_32_bits(offset);
2878 }
2879
2880 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2881 {
2882 struct drm_device *dev = intel_crtc->base.dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884
2885 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2886 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2887 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2888 }
2889
2890 /*
2891 * This function detaches (aka. unbinds) unused scalers in hardware
2892 */
2893 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2894 {
2895 struct intel_crtc_scaler_state *scaler_state;
2896 int i;
2897
2898 scaler_state = &intel_crtc->config->scaler_state;
2899
2900 /* loop through and disable scalers that aren't in use */
2901 for (i = 0; i < intel_crtc->num_scalers; i++) {
2902 if (!scaler_state->scalers[i].in_use)
2903 skl_detach_scaler(intel_crtc, i);
2904 }
2905 }
2906
2907 u32 skl_plane_ctl_format(uint32_t pixel_format)
2908 {
2909 switch (pixel_format) {
2910 case DRM_FORMAT_C8:
2911 return PLANE_CTL_FORMAT_INDEXED;
2912 case DRM_FORMAT_RGB565:
2913 return PLANE_CTL_FORMAT_RGB_565;
2914 case DRM_FORMAT_XBGR8888:
2915 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2916 case DRM_FORMAT_XRGB8888:
2917 return PLANE_CTL_FORMAT_XRGB_8888;
2918 /*
2919 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920 * to be already pre-multiplied. We need to add a knob (or a different
2921 * DRM_FORMAT) for user-space to configure that.
2922 */
2923 case DRM_FORMAT_ABGR8888:
2924 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2925 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2926 case DRM_FORMAT_ARGB8888:
2927 return PLANE_CTL_FORMAT_XRGB_8888 |
2928 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929 case DRM_FORMAT_XRGB2101010:
2930 return PLANE_CTL_FORMAT_XRGB_2101010;
2931 case DRM_FORMAT_XBGR2101010:
2932 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2933 case DRM_FORMAT_YUYV:
2934 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2935 case DRM_FORMAT_YVYU:
2936 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2937 case DRM_FORMAT_UYVY:
2938 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2939 case DRM_FORMAT_VYUY:
2940 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2941 default:
2942 MISSING_CASE(pixel_format);
2943 }
2944
2945 return 0;
2946 }
2947
2948 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2949 {
2950 switch (fb_modifier) {
2951 case DRM_FORMAT_MOD_NONE:
2952 break;
2953 case I915_FORMAT_MOD_X_TILED:
2954 return PLANE_CTL_TILED_X;
2955 case I915_FORMAT_MOD_Y_TILED:
2956 return PLANE_CTL_TILED_Y;
2957 case I915_FORMAT_MOD_Yf_TILED:
2958 return PLANE_CTL_TILED_YF;
2959 default:
2960 MISSING_CASE(fb_modifier);
2961 }
2962
2963 return 0;
2964 }
2965
2966 u32 skl_plane_ctl_rotation(unsigned int rotation)
2967 {
2968 switch (rotation) {
2969 case BIT(DRM_ROTATE_0):
2970 break;
2971 /*
2972 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973 * while i915 HW rotation is clockwise, thats why this swapping.
2974 */
2975 case BIT(DRM_ROTATE_90):
2976 return PLANE_CTL_ROTATE_270;
2977 case BIT(DRM_ROTATE_180):
2978 return PLANE_CTL_ROTATE_180;
2979 case BIT(DRM_ROTATE_270):
2980 return PLANE_CTL_ROTATE_90;
2981 default:
2982 MISSING_CASE(rotation);
2983 }
2984
2985 return 0;
2986 }
2987
2988 static void skylake_update_primary_plane(struct drm_plane *plane,
2989 const struct intel_crtc_state *crtc_state,
2990 const struct intel_plane_state *plane_state)
2991 {
2992 struct drm_device *dev = plane->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2995 struct drm_framebuffer *fb = plane_state->base.fb;
2996 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2997 int pipe = intel_crtc->pipe;
2998 u32 plane_ctl, stride_div, stride;
2999 u32 tile_height, plane_offset, plane_size;
3000 unsigned int rotation = plane_state->base.rotation;
3001 int x_offset, y_offset;
3002 u32 surf_addr;
3003 int scaler_id = plane_state->scaler_id;
3004 int src_x = plane_state->src.x1 >> 16;
3005 int src_y = plane_state->src.y1 >> 16;
3006 int src_w = drm_rect_width(&plane_state->src) >> 16;
3007 int src_h = drm_rect_height(&plane_state->src) >> 16;
3008 int dst_x = plane_state->dst.x1;
3009 int dst_y = plane_state->dst.y1;
3010 int dst_w = drm_rect_width(&plane_state->dst);
3011 int dst_h = drm_rect_height(&plane_state->dst);
3012
3013 plane_ctl = PLANE_CTL_ENABLE |
3014 PLANE_CTL_PIPE_GAMMA_ENABLE |
3015 PLANE_CTL_PIPE_CSC_ENABLE;
3016
3017 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3018 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3019 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3020 plane_ctl |= skl_plane_ctl_rotation(rotation);
3021
3022 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3023 fb->pixel_format);
3024 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3025
3026 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3027
3028 if (intel_rotation_90_or_270(rotation)) {
3029 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3030
3031 /* stride = Surface height in tiles */
3032 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3033 stride = DIV_ROUND_UP(fb->height, tile_height);
3034 x_offset = stride * tile_height - src_y - src_h;
3035 y_offset = src_x;
3036 plane_size = (src_w - 1) << 16 | (src_h - 1);
3037 } else {
3038 stride = fb->pitches[0] / stride_div;
3039 x_offset = src_x;
3040 y_offset = src_y;
3041 plane_size = (src_h - 1) << 16 | (src_w - 1);
3042 }
3043 plane_offset = y_offset << 16 | x_offset;
3044
3045 intel_crtc->adjusted_x = x_offset;
3046 intel_crtc->adjusted_y = y_offset;
3047
3048 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3049 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3050 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3051 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3052
3053 if (scaler_id >= 0) {
3054 uint32_t ps_ctrl = 0;
3055
3056 WARN_ON(!dst_w || !dst_h);
3057 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3058 crtc_state->scaler_state.scalers[scaler_id].mode;
3059 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3060 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3061 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3062 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3063 I915_WRITE(PLANE_POS(pipe, 0), 0);
3064 } else {
3065 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3066 }
3067
3068 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3069
3070 POSTING_READ(PLANE_SURF(pipe, 0));
3071 }
3072
3073 static void skylake_disable_primary_plane(struct drm_plane *primary,
3074 struct drm_crtc *crtc)
3075 {
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int pipe = to_intel_crtc(crtc)->pipe;
3079
3080 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082 POSTING_READ(PLANE_SURF(pipe, 0));
3083 }
3084
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3086 static int
3087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3088 int x, int y, enum mode_set_atomic state)
3089 {
3090 /* Support for kgdboc is disabled, this needs a major rework. */
3091 DRM_ERROR("legacy panic handler not supported any more.\n");
3092
3093 return -ENODEV;
3094 }
3095
3096 static void intel_complete_page_flips(struct drm_device *dev)
3097 {
3098 struct drm_crtc *crtc;
3099
3100 for_each_crtc(dev, crtc) {
3101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102 enum plane plane = intel_crtc->plane;
3103
3104 intel_prepare_page_flip(dev, plane);
3105 intel_finish_page_flip_plane(dev, plane);
3106 }
3107 }
3108
3109 static void intel_update_primary_planes(struct drm_device *dev)
3110 {
3111 struct drm_crtc *crtc;
3112
3113 for_each_crtc(dev, crtc) {
3114 struct intel_plane *plane = to_intel_plane(crtc->primary);
3115 struct intel_plane_state *plane_state;
3116
3117 drm_modeset_lock_crtc(crtc, &plane->base);
3118 plane_state = to_intel_plane_state(plane->base.state);
3119
3120 if (plane_state->visible)
3121 plane->update_plane(&plane->base,
3122 to_intel_crtc_state(crtc->state),
3123 plane_state);
3124
3125 drm_modeset_unlock_crtc(crtc);
3126 }
3127 }
3128
3129 void intel_prepare_reset(struct drm_device *dev)
3130 {
3131 /* no reset support for gen2 */
3132 if (IS_GEN2(dev))
3133 return;
3134
3135 /* reset doesn't touch the display */
3136 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3137 return;
3138
3139 drm_modeset_lock_all(dev);
3140 /*
3141 * Disabling the crtcs gracefully seems nicer. Also the
3142 * g33 docs say we should at least disable all the planes.
3143 */
3144 intel_display_suspend(dev);
3145 }
3146
3147 void intel_finish_reset(struct drm_device *dev)
3148 {
3149 struct drm_i915_private *dev_priv = to_i915(dev);
3150
3151 /*
3152 * Flips in the rings will be nuked by the reset,
3153 * so complete all pending flips so that user space
3154 * will get its events and not get stuck.
3155 */
3156 intel_complete_page_flips(dev);
3157
3158 /* no reset support for gen2 */
3159 if (IS_GEN2(dev))
3160 return;
3161
3162 /* reset doesn't touch the display */
3163 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3164 /*
3165 * Flips in the rings have been nuked by the reset,
3166 * so update the base address of all primary
3167 * planes to the the last fb to make sure we're
3168 * showing the correct fb after a reset.
3169 *
3170 * FIXME: Atomic will make this obsolete since we won't schedule
3171 * CS-based flips (which might get lost in gpu resets) any more.
3172 */
3173 intel_update_primary_planes(dev);
3174 return;
3175 }
3176
3177 /*
3178 * The display has been reset as well,
3179 * so need a full re-initialization.
3180 */
3181 intel_runtime_pm_disable_interrupts(dev_priv);
3182 intel_runtime_pm_enable_interrupts(dev_priv);
3183
3184 intel_modeset_init_hw(dev);
3185
3186 spin_lock_irq(&dev_priv->irq_lock);
3187 if (dev_priv->display.hpd_irq_setup)
3188 dev_priv->display.hpd_irq_setup(dev);
3189 spin_unlock_irq(&dev_priv->irq_lock);
3190
3191 intel_display_resume(dev);
3192
3193 intel_hpd_init(dev_priv);
3194
3195 drm_modeset_unlock_all(dev);
3196 }
3197
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3199 {
3200 struct drm_device *dev = crtc->dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203 bool pending;
3204
3205 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3206 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3207 return false;
3208
3209 spin_lock_irq(&dev->event_lock);
3210 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3211 spin_unlock_irq(&dev->event_lock);
3212
3213 return pending;
3214 }
3215
3216 static void intel_update_pipe_config(struct intel_crtc *crtc,
3217 struct intel_crtc_state *old_crtc_state)
3218 {
3219 struct drm_device *dev = crtc->base.dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc_state *pipe_config =
3222 to_intel_crtc_state(crtc->base.state);
3223
3224 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225 crtc->base.mode = crtc->base.state->mode;
3226
3227 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3229 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3230
3231 /*
3232 * Update pipe size and adjust fitter if needed: the reason for this is
3233 * that in compute_mode_changes we check the native mode (not the pfit
3234 * mode) to see if we can flip rather than do a full mode set. In the
3235 * fastboot case, we'll flip, but if we don't update the pipesrc and
3236 * pfit state, we'll end up with a big fb scanned out into the wrong
3237 * sized surface.
3238 */
3239
3240 I915_WRITE(PIPESRC(crtc->pipe),
3241 ((pipe_config->pipe_src_w - 1) << 16) |
3242 (pipe_config->pipe_src_h - 1));
3243
3244 /* on skylake this is done by detaching scalers */
3245 if (INTEL_INFO(dev)->gen >= 9) {
3246 skl_detach_scalers(crtc);
3247
3248 if (pipe_config->pch_pfit.enabled)
3249 skylake_pfit_enable(crtc);
3250 } else if (HAS_PCH_SPLIT(dev)) {
3251 if (pipe_config->pch_pfit.enabled)
3252 ironlake_pfit_enable(crtc);
3253 else if (old_crtc_state->pch_pfit.enabled)
3254 ironlake_pfit_disable(crtc, true);
3255 }
3256 }
3257
3258 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3259 {
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263 int pipe = intel_crtc->pipe;
3264 i915_reg_t reg;
3265 u32 temp;
3266
3267 /* enable normal train */
3268 reg = FDI_TX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 if (IS_IVYBRIDGE(dev)) {
3271 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3272 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3273 } else {
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3276 }
3277 I915_WRITE(reg, temp);
3278
3279 reg = FDI_RX_CTL(pipe);
3280 temp = I915_READ(reg);
3281 if (HAS_PCH_CPT(dev)) {
3282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3284 } else {
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_NONE;
3287 }
3288 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3289
3290 /* wait one idle pattern time */
3291 POSTING_READ(reg);
3292 udelay(1000);
3293
3294 /* IVB wants error correction enabled */
3295 if (IS_IVYBRIDGE(dev))
3296 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3297 FDI_FE_ERRC_ENABLE);
3298 }
3299
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 int pipe = intel_crtc->pipe;
3307 i915_reg_t reg;
3308 u32 temp, tries;
3309
3310 /* FDI needs bits from pipe first */
3311 assert_pipe_enabled(dev_priv, pipe);
3312
3313 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3314 for train result */
3315 reg = FDI_RX_IMR(pipe);
3316 temp = I915_READ(reg);
3317 temp &= ~FDI_RX_SYMBOL_LOCK;
3318 temp &= ~FDI_RX_BIT_LOCK;
3319 I915_WRITE(reg, temp);
3320 I915_READ(reg);
3321 udelay(150);
3322
3323 /* enable CPU FDI TX and PCH FDI RX */
3324 reg = FDI_TX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3327 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3331
3332 reg = FDI_RX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_NONE;
3335 temp |= FDI_LINK_TRAIN_PATTERN_1;
3336 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3337
3338 POSTING_READ(reg);
3339 udelay(150);
3340
3341 /* Ironlake workaround, enable clock pointer after FDI enable*/
3342 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3344 FDI_RX_PHASE_SYNC_POINTER_EN);
3345
3346 reg = FDI_RX_IIR(pipe);
3347 for (tries = 0; tries < 5; tries++) {
3348 temp = I915_READ(reg);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350
3351 if ((temp & FDI_RX_BIT_LOCK)) {
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3354 break;
3355 }
3356 }
3357 if (tries == 5)
3358 DRM_ERROR("FDI train 1 fail!\n");
3359
3360 /* Train 2 */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_PATTERN_2;
3365 I915_WRITE(reg, temp);
3366
3367 reg = FDI_RX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_PATTERN_2;
3371 I915_WRITE(reg, temp);
3372
3373 POSTING_READ(reg);
3374 udelay(150);
3375
3376 reg = FDI_RX_IIR(pipe);
3377 for (tries = 0; tries < 5; tries++) {
3378 temp = I915_READ(reg);
3379 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3380
3381 if (temp & FDI_RX_SYMBOL_LOCK) {
3382 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3383 DRM_DEBUG_KMS("FDI train 2 done.\n");
3384 break;
3385 }
3386 }
3387 if (tries == 5)
3388 DRM_ERROR("FDI train 2 fail!\n");
3389
3390 DRM_DEBUG_KMS("FDI train done\n");
3391
3392 }
3393
3394 static const int snb_b_fdi_train_param[] = {
3395 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3396 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3397 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3398 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3399 };
3400
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 int pipe = intel_crtc->pipe;
3408 i915_reg_t reg;
3409 u32 temp, i, retry;
3410
3411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3412 for train result */
3413 reg = FDI_RX_IMR(pipe);
3414 temp = I915_READ(reg);
3415 temp &= ~FDI_RX_SYMBOL_LOCK;
3416 temp &= ~FDI_RX_BIT_LOCK;
3417 I915_WRITE(reg, temp);
3418
3419 POSTING_READ(reg);
3420 udelay(150);
3421
3422 /* enable CPU FDI TX and PCH FDI RX */
3423 reg = FDI_TX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3426 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3427 temp &= ~FDI_LINK_TRAIN_NONE;
3428 temp |= FDI_LINK_TRAIN_PATTERN_1;
3429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3430 /* SNB-B */
3431 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3433
3434 I915_WRITE(FDI_RX_MISC(pipe),
3435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3436
3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 if (HAS_PCH_CPT(dev)) {
3440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3442 } else {
3443 temp &= ~FDI_LINK_TRAIN_NONE;
3444 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445 }
3446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448 POSTING_READ(reg);
3449 udelay(150);
3450
3451 for (i = 0; i < 4; i++) {
3452 reg = FDI_TX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455 temp |= snb_b_fdi_train_param[i];
3456 I915_WRITE(reg, temp);
3457
3458 POSTING_READ(reg);
3459 udelay(500);
3460
3461 for (retry = 0; retry < 5; retry++) {
3462 reg = FDI_RX_IIR(pipe);
3463 temp = I915_READ(reg);
3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465 if (temp & FDI_RX_BIT_LOCK) {
3466 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3467 DRM_DEBUG_KMS("FDI train 1 done.\n");
3468 break;
3469 }
3470 udelay(50);
3471 }
3472 if (retry < 5)
3473 break;
3474 }
3475 if (i == 4)
3476 DRM_ERROR("FDI train 1 fail!\n");
3477
3478 /* Train 2 */
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_NONE;
3482 temp |= FDI_LINK_TRAIN_PATTERN_2;
3483 if (IS_GEN6(dev)) {
3484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485 /* SNB-B */
3486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3487 }
3488 I915_WRITE(reg, temp);
3489
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 if (HAS_PCH_CPT(dev)) {
3493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3495 } else {
3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_2;
3498 }
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
3502 udelay(150);
3503
3504 for (i = 0; i < 4; i++) {
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508 temp |= snb_b_fdi_train_param[i];
3509 I915_WRITE(reg, temp);
3510
3511 POSTING_READ(reg);
3512 udelay(500);
3513
3514 for (retry = 0; retry < 5; retry++) {
3515 reg = FDI_RX_IIR(pipe);
3516 temp = I915_READ(reg);
3517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518 if (temp & FDI_RX_SYMBOL_LOCK) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done.\n");
3521 break;
3522 }
3523 udelay(50);
3524 }
3525 if (retry < 5)
3526 break;
3527 }
3528 if (i == 4)
3529 DRM_ERROR("FDI train 2 fail!\n");
3530
3531 DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3536 {
3537 struct drm_device *dev = crtc->dev;
3538 struct drm_i915_private *dev_priv = dev->dev_private;
3539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540 int pipe = intel_crtc->pipe;
3541 i915_reg_t reg;
3542 u32 temp, i, j;
3543
3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3545 for train result */
3546 reg = FDI_RX_IMR(pipe);
3547 temp = I915_READ(reg);
3548 temp &= ~FDI_RX_SYMBOL_LOCK;
3549 temp &= ~FDI_RX_BIT_LOCK;
3550 I915_WRITE(reg, temp);
3551
3552 POSTING_READ(reg);
3553 udelay(150);
3554
3555 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556 I915_READ(FDI_RX_IIR(pipe)));
3557
3558 /* Try each vswing and preemphasis setting twice before moving on */
3559 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3560 /* disable first in case we need to retry */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3564 temp &= ~FDI_TX_ENABLE;
3565 I915_WRITE(reg, temp);
3566
3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_AUTO;
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp &= ~FDI_RX_ENABLE;
3572 I915_WRITE(reg, temp);
3573
3574 /* enable CPU FDI TX and PCH FDI RX */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3578 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3581 temp |= snb_b_fdi_train_param[j/2];
3582 temp |= FDI_COMPOSITE_SYNC;
3583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3584
3585 I915_WRITE(FDI_RX_MISC(pipe),
3586 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3587
3588 reg = FDI_RX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3591 temp |= FDI_COMPOSITE_SYNC;
3592 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3593
3594 POSTING_READ(reg);
3595 udelay(1); /* should be 0.5us */
3596
3597 for (i = 0; i < 4; i++) {
3598 reg = FDI_RX_IIR(pipe);
3599 temp = I915_READ(reg);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601
3602 if (temp & FDI_RX_BIT_LOCK ||
3603 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3606 i);
3607 break;
3608 }
3609 udelay(1); /* should be 0.5us */
3610 }
3611 if (i == 4) {
3612 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3613 continue;
3614 }
3615
3616 /* Train 2 */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3621 I915_WRITE(reg, temp);
3622
3623 reg = FDI_RX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3626 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3627 I915_WRITE(reg, temp);
3628
3629 POSTING_READ(reg);
3630 udelay(2); /* should be 1.5us */
3631
3632 for (i = 0; i < 4; i++) {
3633 reg = FDI_RX_IIR(pipe);
3634 temp = I915_READ(reg);
3635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3636
3637 if (temp & FDI_RX_SYMBOL_LOCK ||
3638 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3641 i);
3642 goto train_done;
3643 }
3644 udelay(2); /* should be 1.5us */
3645 }
3646 if (i == 4)
3647 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3648 }
3649
3650 train_done:
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3655 {
3656 struct drm_device *dev = intel_crtc->base.dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 int pipe = intel_crtc->pipe;
3659 i915_reg_t reg;
3660 u32 temp;
3661
3662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663 reg = FDI_RX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3669
3670 POSTING_READ(reg);
3671 udelay(200);
3672
3673 /* Switch from Rawclk to PCDclk */
3674 temp = I915_READ(reg);
3675 I915_WRITE(reg, temp | FDI_PCDCLK);
3676
3677 POSTING_READ(reg);
3678 udelay(200);
3679
3680 /* Enable CPU FDI TX PLL, always on for Ironlake */
3681 reg = FDI_TX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3685
3686 POSTING_READ(reg);
3687 udelay(100);
3688 }
3689 }
3690
3691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3692 {
3693 struct drm_device *dev = intel_crtc->base.dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 int pipe = intel_crtc->pipe;
3696 i915_reg_t reg;
3697 u32 temp;
3698
3699 /* Switch from PCDclk to Rawclk */
3700 reg = FDI_RX_CTL(pipe);
3701 temp = I915_READ(reg);
3702 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3703
3704 /* Disable CPU FDI TX PLL */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(100);
3711
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3715
3716 /* Wait for the clocks to turn off. */
3717 POSTING_READ(reg);
3718 udelay(100);
3719 }
3720
3721 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726 int pipe = intel_crtc->pipe;
3727 i915_reg_t reg;
3728 u32 temp;
3729
3730 /* disable CPU FDI tx and PCH FDI rx */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734 POSTING_READ(reg);
3735
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~(0x7 << 16);
3739 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3740 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742 POSTING_READ(reg);
3743 udelay(100);
3744
3745 /* Ironlake workaround, disable clock pointer after downing FDI */
3746 if (HAS_PCH_IBX(dev))
3747 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3748
3749 /* still set train pattern 1 */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_LINK_TRAIN_NONE;
3753 temp |= FDI_LINK_TRAIN_PATTERN_1;
3754 I915_WRITE(reg, temp);
3755
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if (HAS_PCH_CPT(dev)) {
3759 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761 } else {
3762 temp &= ~FDI_LINK_TRAIN_NONE;
3763 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764 }
3765 /* BPC in FDI rx is consistent with that in PIPECONF */
3766 temp &= ~(0x07 << 16);
3767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3768 I915_WRITE(reg, temp);
3769
3770 POSTING_READ(reg);
3771 udelay(100);
3772 }
3773
3774 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775 {
3776 struct intel_crtc *crtc;
3777
3778 /* Note that we don't need to be called with mode_config.lock here
3779 * as our list of CRTC objects is static for the lifetime of the
3780 * device and so cannot disappear as we iterate. Similarly, we can
3781 * happily treat the predicates as racy, atomic checks as userspace
3782 * cannot claim and pin a new fb without at least acquring the
3783 * struct_mutex and so serialising with us.
3784 */
3785 for_each_intel_crtc(dev, crtc) {
3786 if (atomic_read(&crtc->unpin_work_count) == 0)
3787 continue;
3788
3789 if (crtc->unpin_work)
3790 intel_wait_for_vblank(dev, crtc->pipe);
3791
3792 return true;
3793 }
3794
3795 return false;
3796 }
3797
3798 static void page_flip_completed(struct intel_crtc *intel_crtc)
3799 {
3800 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801 struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803 /* ensure that the unpin work is consistent wrt ->pending. */
3804 smp_rmb();
3805 intel_crtc->unpin_work = NULL;
3806
3807 if (work->event)
3808 drm_send_vblank_event(intel_crtc->base.dev,
3809 intel_crtc->pipe,
3810 work->event);
3811
3812 drm_crtc_vblank_put(&intel_crtc->base);
3813
3814 wake_up_all(&dev_priv->pending_flip_queue);
3815 queue_work(dev_priv->wq, &work->work);
3816
3817 trace_i915_flip_complete(intel_crtc->plane,
3818 work->pending_flip_obj);
3819 }
3820
3821 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3822 {
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 long ret;
3826
3827 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3828
3829 ret = wait_event_interruptible_timeout(
3830 dev_priv->pending_flip_queue,
3831 !intel_crtc_has_pending_flip(crtc),
3832 60*HZ);
3833
3834 if (ret < 0)
3835 return ret;
3836
3837 if (ret == 0) {
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839
3840 spin_lock_irq(&dev->event_lock);
3841 if (intel_crtc->unpin_work) {
3842 WARN_ONCE(1, "Removing stuck page flip\n");
3843 page_flip_completed(intel_crtc);
3844 }
3845 spin_unlock_irq(&dev->event_lock);
3846 }
3847
3848 return 0;
3849 }
3850
3851 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3852 {
3853 u32 temp;
3854
3855 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3856
3857 mutex_lock(&dev_priv->sb_lock);
3858
3859 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3860 temp |= SBI_SSCCTL_DISABLE;
3861 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3862
3863 mutex_unlock(&dev_priv->sb_lock);
3864 }
3865
3866 /* Program iCLKIP clock to the desired frequency */
3867 static void lpt_program_iclkip(struct drm_crtc *crtc)
3868 {
3869 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3870 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3871 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3872 u32 temp;
3873
3874 lpt_disable_iclkip(dev_priv);
3875
3876 /* The iCLK virtual clock root frequency is in MHz,
3877 * but the adjusted_mode->crtc_clock in in KHz. To get the
3878 * divisors, it is necessary to divide one by another, so we
3879 * convert the virtual clock precision to KHz here for higher
3880 * precision.
3881 */
3882 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3883 u32 iclk_virtual_root_freq = 172800 * 1000;
3884 u32 iclk_pi_range = 64;
3885 u32 desired_divisor;
3886
3887 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3888 clock << auxdiv);
3889 divsel = (desired_divisor / iclk_pi_range) - 2;
3890 phaseinc = desired_divisor % iclk_pi_range;
3891
3892 /*
3893 * Near 20MHz is a corner case which is
3894 * out of range for the 7-bit divisor
3895 */
3896 if (divsel <= 0x7f)
3897 break;
3898 }
3899
3900 /* This should not happen with any sane values */
3901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3905
3906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3907 clock,
3908 auxdiv,
3909 divsel,
3910 phasedir,
3911 phaseinc);
3912
3913 mutex_lock(&dev_priv->sb_lock);
3914
3915 /* Program SSCDIVINTPHASE6 */
3916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3923 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3924
3925 /* Program SSCAUXDIV */
3926 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3927 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3928 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3929 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3930
3931 /* Enable modulator and associated divider */
3932 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3933 temp &= ~SBI_SSCCTL_DISABLE;
3934 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3935
3936 mutex_unlock(&dev_priv->sb_lock);
3937
3938 /* Wait for initialization time */
3939 udelay(24);
3940
3941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3942 }
3943
3944 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3945 {
3946 u32 divsel, phaseinc, auxdiv;
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor;
3950 u32 temp;
3951
3952 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3953 return 0;
3954
3955 mutex_lock(&dev_priv->sb_lock);
3956
3957 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3958 if (temp & SBI_SSCCTL_DISABLE) {
3959 mutex_unlock(&dev_priv->sb_lock);
3960 return 0;
3961 }
3962
3963 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3964 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3965 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3966 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3967 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3970 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3971 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3972
3973 mutex_unlock(&dev_priv->sb_lock);
3974
3975 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3976
3977 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3978 desired_divisor << auxdiv);
3979 }
3980
3981 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3982 enum pipe pch_transcoder)
3983 {
3984 struct drm_device *dev = crtc->base.dev;
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3987
3988 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3989 I915_READ(HTOTAL(cpu_transcoder)));
3990 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3991 I915_READ(HBLANK(cpu_transcoder)));
3992 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3993 I915_READ(HSYNC(cpu_transcoder)));
3994
3995 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3996 I915_READ(VTOTAL(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3998 I915_READ(VBLANK(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4000 I915_READ(VSYNC(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4002 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4003 }
4004
4005 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4006 {
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 uint32_t temp;
4009
4010 temp = I915_READ(SOUTH_CHICKEN1);
4011 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4012 return;
4013
4014 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4016
4017 temp &= ~FDI_BC_BIFURCATION_SELECT;
4018 if (enable)
4019 temp |= FDI_BC_BIFURCATION_SELECT;
4020
4021 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4022 I915_WRITE(SOUTH_CHICKEN1, temp);
4023 POSTING_READ(SOUTH_CHICKEN1);
4024 }
4025
4026 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4027 {
4028 struct drm_device *dev = intel_crtc->base.dev;
4029
4030 switch (intel_crtc->pipe) {
4031 case PIPE_A:
4032 break;
4033 case PIPE_B:
4034 if (intel_crtc->config->fdi_lanes > 2)
4035 cpt_set_fdi_bc_bifurcation(dev, false);
4036 else
4037 cpt_set_fdi_bc_bifurcation(dev, true);
4038
4039 break;
4040 case PIPE_C:
4041 cpt_set_fdi_bc_bifurcation(dev, true);
4042
4043 break;
4044 default:
4045 BUG();
4046 }
4047 }
4048
4049 /* Return which DP Port should be selected for Transcoder DP control */
4050 static enum port
4051 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4052 {
4053 struct drm_device *dev = crtc->dev;
4054 struct intel_encoder *encoder;
4055
4056 for_each_encoder_on_crtc(dev, crtc, encoder) {
4057 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4058 encoder->type == INTEL_OUTPUT_EDP)
4059 return enc_to_dig_port(&encoder->base)->port;
4060 }
4061
4062 return -1;
4063 }
4064
4065 /*
4066 * Enable PCH resources required for PCH ports:
4067 * - PCH PLLs
4068 * - FDI training & RX/TX
4069 * - update transcoder timings
4070 * - DP transcoding bits
4071 * - transcoder
4072 */
4073 static void ironlake_pch_enable(struct drm_crtc *crtc)
4074 {
4075 struct drm_device *dev = crtc->dev;
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4078 int pipe = intel_crtc->pipe;
4079 u32 temp;
4080
4081 assert_pch_transcoder_disabled(dev_priv, pipe);
4082
4083 if (IS_IVYBRIDGE(dev))
4084 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4085
4086 /* Write the TU size bits before fdi link training, so that error
4087 * detection works. */
4088 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4089 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4090
4091 /*
4092 * Sometimes spurious CPU pipe underruns happen during FDI
4093 * training, at least with VGA+HDMI cloning. Suppress them.
4094 */
4095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4096
4097 /* For PCH output, training FDI link */
4098 dev_priv->display.fdi_link_train(crtc);
4099
4100 /* We need to program the right clock selection before writing the pixel
4101 * mutliplier into the DPLL. */
4102 if (HAS_PCH_CPT(dev)) {
4103 u32 sel;
4104
4105 temp = I915_READ(PCH_DPLL_SEL);
4106 temp |= TRANS_DPLL_ENABLE(pipe);
4107 sel = TRANS_DPLLB_SEL(pipe);
4108 if (intel_crtc->config->shared_dpll ==
4109 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4110 temp |= sel;
4111 else
4112 temp &= ~sel;
4113 I915_WRITE(PCH_DPLL_SEL, temp);
4114 }
4115
4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
4123 intel_enable_shared_dpll(intel_crtc);
4124
4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129 intel_fdi_normal_train(crtc);
4130
4131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4132
4133 /* For PCH DP, enable TRANS_DP_CTL */
4134 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4135 const struct drm_display_mode *adjusted_mode =
4136 &intel_crtc->config->base.adjusted_mode;
4137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4138 i915_reg_t reg = TRANS_DP_CTL(pipe);
4139 temp = I915_READ(reg);
4140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4141 TRANS_DP_SYNC_MASK |
4142 TRANS_DP_BPC_MASK);
4143 temp |= TRANS_DP_OUTPUT_ENABLE;
4144 temp |= bpc << 9; /* same format but at 11:9 */
4145
4146 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4148 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4150
4151 switch (intel_trans_dp_port_sel(crtc)) {
4152 case PORT_B:
4153 temp |= TRANS_DP_PORT_SEL_B;
4154 break;
4155 case PORT_C:
4156 temp |= TRANS_DP_PORT_SEL_C;
4157 break;
4158 case PORT_D:
4159 temp |= TRANS_DP_PORT_SEL_D;
4160 break;
4161 default:
4162 BUG();
4163 }
4164
4165 I915_WRITE(reg, temp);
4166 }
4167
4168 ironlake_enable_pch_transcoder(dev_priv, pipe);
4169 }
4170
4171 static void lpt_pch_enable(struct drm_crtc *crtc)
4172 {
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4177
4178 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4179
4180 lpt_program_iclkip(crtc);
4181
4182 /* Set transcoder timing. */
4183 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4184
4185 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4186 }
4187
4188 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4189 {
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 i915_reg_t dslreg = PIPEDSL(pipe);
4192 u32 temp;
4193
4194 temp = I915_READ(dslreg);
4195 udelay(500);
4196 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4197 if (wait_for(I915_READ(dslreg) != temp, 5))
4198 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4199 }
4200 }
4201
4202 static int
4203 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4204 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4205 int src_w, int src_h, int dst_w, int dst_h)
4206 {
4207 struct intel_crtc_scaler_state *scaler_state =
4208 &crtc_state->scaler_state;
4209 struct intel_crtc *intel_crtc =
4210 to_intel_crtc(crtc_state->base.crtc);
4211 int need_scaling;
4212
4213 need_scaling = intel_rotation_90_or_270(rotation) ?
4214 (src_h != dst_w || src_w != dst_h):
4215 (src_w != dst_w || src_h != dst_h);
4216
4217 /*
4218 * if plane is being disabled or scaler is no more required or force detach
4219 * - free scaler binded to this plane/crtc
4220 * - in order to do this, update crtc->scaler_usage
4221 *
4222 * Here scaler state in crtc_state is set free so that
4223 * scaler can be assigned to other user. Actual register
4224 * update to free the scaler is done in plane/panel-fit programming.
4225 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4226 */
4227 if (force_detach || !need_scaling) {
4228 if (*scaler_id >= 0) {
4229 scaler_state->scaler_users &= ~(1 << scaler_user);
4230 scaler_state->scalers[*scaler_id].in_use = 0;
4231
4232 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4233 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4234 intel_crtc->pipe, scaler_user, *scaler_id,
4235 scaler_state->scaler_users);
4236 *scaler_id = -1;
4237 }
4238 return 0;
4239 }
4240
4241 /* range checks */
4242 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4243 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4244
4245 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4246 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4247 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4248 "size is out of scaler range\n",
4249 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4250 return -EINVAL;
4251 }
4252
4253 /* mark this plane as a scaler user in crtc_state */
4254 scaler_state->scaler_users |= (1 << scaler_user);
4255 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4256 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4257 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4258 scaler_state->scaler_users);
4259
4260 return 0;
4261 }
4262
4263 /**
4264 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4265 *
4266 * @state: crtc's scaler state
4267 *
4268 * Return
4269 * 0 - scaler_usage updated successfully
4270 * error - requested scaling cannot be supported or other error condition
4271 */
4272 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4273 {
4274 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4275 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4276
4277 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4278 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4279
4280 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4281 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4282 state->pipe_src_w, state->pipe_src_h,
4283 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4284 }
4285
4286 /**
4287 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4288 *
4289 * @state: crtc's scaler state
4290 * @plane_state: atomic plane state to update
4291 *
4292 * Return
4293 * 0 - scaler_usage updated successfully
4294 * error - requested scaling cannot be supported or other error condition
4295 */
4296 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4297 struct intel_plane_state *plane_state)
4298 {
4299
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4301 struct intel_plane *intel_plane =
4302 to_intel_plane(plane_state->base.plane);
4303 struct drm_framebuffer *fb = plane_state->base.fb;
4304 int ret;
4305
4306 bool force_detach = !fb || !plane_state->visible;
4307
4308 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4309 intel_plane->base.base.id, intel_crtc->pipe,
4310 drm_plane_index(&intel_plane->base));
4311
4312 ret = skl_update_scaler(crtc_state, force_detach,
4313 drm_plane_index(&intel_plane->base),
4314 &plane_state->scaler_id,
4315 plane_state->base.rotation,
4316 drm_rect_width(&plane_state->src) >> 16,
4317 drm_rect_height(&plane_state->src) >> 16,
4318 drm_rect_width(&plane_state->dst),
4319 drm_rect_height(&plane_state->dst));
4320
4321 if (ret || plane_state->scaler_id < 0)
4322 return ret;
4323
4324 /* check colorkey */
4325 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4326 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4327 intel_plane->base.base.id);
4328 return -EINVAL;
4329 }
4330
4331 /* Check src format */
4332 switch (fb->pixel_format) {
4333 case DRM_FORMAT_RGB565:
4334 case DRM_FORMAT_XBGR8888:
4335 case DRM_FORMAT_XRGB8888:
4336 case DRM_FORMAT_ABGR8888:
4337 case DRM_FORMAT_ARGB8888:
4338 case DRM_FORMAT_XRGB2101010:
4339 case DRM_FORMAT_XBGR2101010:
4340 case DRM_FORMAT_YUYV:
4341 case DRM_FORMAT_YVYU:
4342 case DRM_FORMAT_UYVY:
4343 case DRM_FORMAT_VYUY:
4344 break;
4345 default:
4346 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4347 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4348 return -EINVAL;
4349 }
4350
4351 return 0;
4352 }
4353
4354 static void skylake_scaler_disable(struct intel_crtc *crtc)
4355 {
4356 int i;
4357
4358 for (i = 0; i < crtc->num_scalers; i++)
4359 skl_detach_scaler(crtc, i);
4360 }
4361
4362 static void skylake_pfit_enable(struct intel_crtc *crtc)
4363 {
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 int pipe = crtc->pipe;
4367 struct intel_crtc_scaler_state *scaler_state =
4368 &crtc->config->scaler_state;
4369
4370 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4371
4372 if (crtc->config->pch_pfit.enabled) {
4373 int id;
4374
4375 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4376 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4377 return;
4378 }
4379
4380 id = scaler_state->scaler_id;
4381 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4382 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4383 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4384 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4385
4386 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4387 }
4388 }
4389
4390 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4391 {
4392 struct drm_device *dev = crtc->base.dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 int pipe = crtc->pipe;
4395
4396 if (crtc->config->pch_pfit.enabled) {
4397 /* Force use of hard-coded filter coefficients
4398 * as some pre-programmed values are broken,
4399 * e.g. x201.
4400 */
4401 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4402 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4403 PF_PIPE_SEL_IVB(pipe));
4404 else
4405 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4406 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4407 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4408 }
4409 }
4410
4411 void hsw_enable_ips(struct intel_crtc *crtc)
4412 {
4413 struct drm_device *dev = crtc->base.dev;
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415
4416 if (!crtc->config->ips_enabled)
4417 return;
4418
4419 /*
4420 * We can only enable IPS after we enable a plane and wait for a vblank
4421 * This function is called from post_plane_update, which is run after
4422 * a vblank wait.
4423 */
4424
4425 assert_plane_enabled(dev_priv, crtc->plane);
4426 if (IS_BROADWELL(dev)) {
4427 mutex_lock(&dev_priv->rps.hw_lock);
4428 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4429 mutex_unlock(&dev_priv->rps.hw_lock);
4430 /* Quoting Art Runyan: "its not safe to expect any particular
4431 * value in IPS_CTL bit 31 after enabling IPS through the
4432 * mailbox." Moreover, the mailbox may return a bogus state,
4433 * so we need to just enable it and continue on.
4434 */
4435 } else {
4436 I915_WRITE(IPS_CTL, IPS_ENABLE);
4437 /* The bit only becomes 1 in the next vblank, so this wait here
4438 * is essentially intel_wait_for_vblank. If we don't have this
4439 * and don't wait for vblanks until the end of crtc_enable, then
4440 * the HW state readout code will complain that the expected
4441 * IPS_CTL value is not the one we read. */
4442 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4443 DRM_ERROR("Timed out waiting for IPS enable\n");
4444 }
4445 }
4446
4447 void hsw_disable_ips(struct intel_crtc *crtc)
4448 {
4449 struct drm_device *dev = crtc->base.dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451
4452 if (!crtc->config->ips_enabled)
4453 return;
4454
4455 assert_plane_enabled(dev_priv, crtc->plane);
4456 if (IS_BROADWELL(dev)) {
4457 mutex_lock(&dev_priv->rps.hw_lock);
4458 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4459 mutex_unlock(&dev_priv->rps.hw_lock);
4460 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4461 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4462 DRM_ERROR("Timed out waiting for IPS disable\n");
4463 } else {
4464 I915_WRITE(IPS_CTL, 0);
4465 POSTING_READ(IPS_CTL);
4466 }
4467
4468 /* We need to wait for a vblank before we can disable the plane. */
4469 intel_wait_for_vblank(dev, crtc->pipe);
4470 }
4471
4472 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4473 {
4474 if (intel_crtc->overlay) {
4475 struct drm_device *dev = intel_crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
4478 mutex_lock(&dev->struct_mutex);
4479 dev_priv->mm.interruptible = false;
4480 (void) intel_overlay_switch_off(intel_crtc->overlay);
4481 dev_priv->mm.interruptible = true;
4482 mutex_unlock(&dev->struct_mutex);
4483 }
4484
4485 /* Let userspace switch the overlay on again. In most cases userspace
4486 * has to recompute where to put it anyway.
4487 */
4488 }
4489
4490 /**
4491 * intel_post_enable_primary - Perform operations after enabling primary plane
4492 * @crtc: the CRTC whose primary plane was just enabled
4493 *
4494 * Performs potentially sleeping operations that must be done after the primary
4495 * plane is enabled, such as updating FBC and IPS. Note that this may be
4496 * called due to an explicit primary plane update, or due to an implicit
4497 * re-enable that is caused when a sprite plane is updated to no longer
4498 * completely hide the primary plane.
4499 */
4500 static void
4501 intel_post_enable_primary(struct drm_crtc *crtc)
4502 {
4503 struct drm_device *dev = crtc->dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4506 int pipe = intel_crtc->pipe;
4507
4508 /*
4509 * FIXME IPS should be fine as long as one plane is
4510 * enabled, but in practice it seems to have problems
4511 * when going from primary only to sprite only and vice
4512 * versa.
4513 */
4514 hsw_enable_ips(intel_crtc);
4515
4516 /*
4517 * Gen2 reports pipe underruns whenever all planes are disabled.
4518 * So don't enable underrun reporting before at least some planes
4519 * are enabled.
4520 * FIXME: Need to fix the logic to work when we turn off all planes
4521 * but leave the pipe running.
4522 */
4523 if (IS_GEN2(dev))
4524 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4525
4526 /* Underruns don't always raise interrupts, so check manually. */
4527 intel_check_cpu_fifo_underruns(dev_priv);
4528 intel_check_pch_fifo_underruns(dev_priv);
4529 }
4530
4531 /* FIXME move all this to pre_plane_update() with proper state tracking */
4532 static void
4533 intel_pre_disable_primary(struct drm_crtc *crtc)
4534 {
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 int pipe = intel_crtc->pipe;
4539
4540 /*
4541 * Gen2 reports pipe underruns whenever all planes are disabled.
4542 * So diasble underrun reporting before all the planes get disabled.
4543 * FIXME: Need to fix the logic to work when we turn off all planes
4544 * but leave the pipe running.
4545 */
4546 if (IS_GEN2(dev))
4547 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4548
4549 /*
4550 * FIXME IPS should be fine as long as one plane is
4551 * enabled, but in practice it seems to have problems
4552 * when going from primary only to sprite only and vice
4553 * versa.
4554 */
4555 hsw_disable_ips(intel_crtc);
4556 }
4557
4558 /* FIXME get rid of this and use pre_plane_update */
4559 static void
4560 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4561 {
4562 struct drm_device *dev = crtc->dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565 int pipe = intel_crtc->pipe;
4566
4567 intel_pre_disable_primary(crtc);
4568
4569 /*
4570 * Vblank time updates from the shadow to live plane control register
4571 * are blocked if the memory self-refresh mode is active at that
4572 * moment. So to make sure the plane gets truly disabled, disable
4573 * first the self-refresh mode. The self-refresh enable bit in turn
4574 * will be checked/applied by the HW only at the next frame start
4575 * event which is after the vblank start event, so we need to have a
4576 * wait-for-vblank between disabling the plane and the pipe.
4577 */
4578 if (HAS_GMCH_DISPLAY(dev)) {
4579 intel_set_memory_cxsr(dev_priv, false);
4580 dev_priv->wm.vlv.cxsr = false;
4581 intel_wait_for_vblank(dev, pipe);
4582 }
4583 }
4584
4585 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4586 {
4587 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4588 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4589 struct intel_crtc_state *pipe_config =
4590 to_intel_crtc_state(crtc->base.state);
4591 struct drm_device *dev = crtc->base.dev;
4592 struct drm_plane *primary = crtc->base.primary;
4593 struct drm_plane_state *old_pri_state =
4594 drm_atomic_get_existing_plane_state(old_state, primary);
4595
4596 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4597
4598 crtc->wm.cxsr_allowed = true;
4599
4600 if (pipe_config->update_wm_post && pipe_config->base.active)
4601 intel_update_watermarks(&crtc->base);
4602
4603 if (old_pri_state) {
4604 struct intel_plane_state *primary_state =
4605 to_intel_plane_state(primary->state);
4606 struct intel_plane_state *old_primary_state =
4607 to_intel_plane_state(old_pri_state);
4608
4609 intel_fbc_post_update(crtc);
4610
4611 if (primary_state->visible &&
4612 (needs_modeset(&pipe_config->base) ||
4613 !old_primary_state->visible))
4614 intel_post_enable_primary(&crtc->base);
4615 }
4616 }
4617
4618 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4619 {
4620 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4621 struct drm_device *dev = crtc->base.dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc_state *pipe_config =
4624 to_intel_crtc_state(crtc->base.state);
4625 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4626 struct drm_plane *primary = crtc->base.primary;
4627 struct drm_plane_state *old_pri_state =
4628 drm_atomic_get_existing_plane_state(old_state, primary);
4629 bool modeset = needs_modeset(&pipe_config->base);
4630
4631 if (old_pri_state) {
4632 struct intel_plane_state *primary_state =
4633 to_intel_plane_state(primary->state);
4634 struct intel_plane_state *old_primary_state =
4635 to_intel_plane_state(old_pri_state);
4636
4637 intel_fbc_pre_update(crtc);
4638
4639 if (old_primary_state->visible &&
4640 (modeset || !primary_state->visible))
4641 intel_pre_disable_primary(&crtc->base);
4642 }
4643
4644 if (pipe_config->disable_cxsr) {
4645 crtc->wm.cxsr_allowed = false;
4646
4647 /*
4648 * Vblank time updates from the shadow to live plane control register
4649 * are blocked if the memory self-refresh mode is active at that
4650 * moment. So to make sure the plane gets truly disabled, disable
4651 * first the self-refresh mode. The self-refresh enable bit in turn
4652 * will be checked/applied by the HW only at the next frame start
4653 * event which is after the vblank start event, so we need to have a
4654 * wait-for-vblank between disabling the plane and the pipe.
4655 */
4656 if (old_crtc_state->base.active) {
4657 intel_set_memory_cxsr(dev_priv, false);
4658 dev_priv->wm.vlv.cxsr = false;
4659 intel_wait_for_vblank(dev, crtc->pipe);
4660 }
4661 }
4662
4663 /*
4664 * IVB workaround: must disable low power watermarks for at least
4665 * one frame before enabling scaling. LP watermarks can be re-enabled
4666 * when scaling is disabled.
4667 *
4668 * WaCxSRDisabledForSpriteScaling:ivb
4669 */
4670 if (pipe_config->disable_lp_wm) {
4671 ilk_disable_lp_wm(dev);
4672 intel_wait_for_vblank(dev, crtc->pipe);
4673 }
4674
4675 /*
4676 * If we're doing a modeset, we're done. No need to do any pre-vblank
4677 * watermark programming here.
4678 */
4679 if (needs_modeset(&pipe_config->base))
4680 return;
4681
4682 /*
4683 * For platforms that support atomic watermarks, program the
4684 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4685 * will be the intermediate values that are safe for both pre- and
4686 * post- vblank; when vblank happens, the 'active' values will be set
4687 * to the final 'target' values and we'll do this again to get the
4688 * optimal watermarks. For gen9+ platforms, the values we program here
4689 * will be the final target values which will get automatically latched
4690 * at vblank time; no further programming will be necessary.
4691 *
4692 * If a platform hasn't been transitioned to atomic watermarks yet,
4693 * we'll continue to update watermarks the old way, if flags tell
4694 * us to.
4695 */
4696 if (dev_priv->display.initial_watermarks != NULL)
4697 dev_priv->display.initial_watermarks(pipe_config);
4698 else if (pipe_config->update_wm_pre)
4699 intel_update_watermarks(&crtc->base);
4700 }
4701
4702 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4703 {
4704 struct drm_device *dev = crtc->dev;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 struct drm_plane *p;
4707 int pipe = intel_crtc->pipe;
4708
4709 intel_crtc_dpms_overlay_disable(intel_crtc);
4710
4711 drm_for_each_plane_mask(p, dev, plane_mask)
4712 to_intel_plane(p)->disable_plane(p, crtc);
4713
4714 /*
4715 * FIXME: Once we grow proper nuclear flip support out of this we need
4716 * to compute the mask of flip planes precisely. For the time being
4717 * consider this a flip to a NULL plane.
4718 */
4719 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4720 }
4721
4722 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4723 {
4724 struct drm_device *dev = crtc->dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4727 struct intel_encoder *encoder;
4728 int pipe = intel_crtc->pipe;
4729 struct intel_crtc_state *pipe_config =
4730 to_intel_crtc_state(crtc->state);
4731
4732 if (WARN_ON(intel_crtc->active))
4733 return;
4734
4735 if (intel_crtc->config->has_pch_encoder)
4736 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4737
4738 if (intel_crtc->config->has_pch_encoder)
4739 intel_prepare_shared_dpll(intel_crtc);
4740
4741 if (intel_crtc->config->has_dp_encoder)
4742 intel_dp_set_m_n(intel_crtc, M1_N1);
4743
4744 intel_set_pipe_timings(intel_crtc);
4745 intel_set_pipe_src_size(intel_crtc);
4746
4747 if (intel_crtc->config->has_pch_encoder) {
4748 intel_cpu_transcoder_set_m_n(intel_crtc,
4749 &intel_crtc->config->fdi_m_n, NULL);
4750 }
4751
4752 ironlake_set_pipeconf(crtc);
4753
4754 intel_crtc->active = true;
4755
4756 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4757
4758 for_each_encoder_on_crtc(dev, crtc, encoder)
4759 if (encoder->pre_enable)
4760 encoder->pre_enable(encoder);
4761
4762 if (intel_crtc->config->has_pch_encoder) {
4763 /* Note: FDI PLL enabling _must_ be done before we enable the
4764 * cpu pipes, hence this is separate from all the other fdi/pch
4765 * enabling. */
4766 ironlake_fdi_pll_enable(intel_crtc);
4767 } else {
4768 assert_fdi_tx_disabled(dev_priv, pipe);
4769 assert_fdi_rx_disabled(dev_priv, pipe);
4770 }
4771
4772 ironlake_pfit_enable(intel_crtc);
4773
4774 /*
4775 * On ILK+ LUT must be loaded before the pipe is running but with
4776 * clocks enabled
4777 */
4778 intel_color_load_luts(&pipe_config->base);
4779
4780 if (dev_priv->display.initial_watermarks != NULL)
4781 dev_priv->display.initial_watermarks(intel_crtc->config);
4782 intel_enable_pipe(intel_crtc);
4783
4784 if (intel_crtc->config->has_pch_encoder)
4785 ironlake_pch_enable(crtc);
4786
4787 assert_vblank_disabled(crtc);
4788 drm_crtc_vblank_on(crtc);
4789
4790 for_each_encoder_on_crtc(dev, crtc, encoder)
4791 encoder->enable(encoder);
4792
4793 if (HAS_PCH_CPT(dev))
4794 cpt_verify_modeset(dev, intel_crtc->pipe);
4795
4796 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4797 if (intel_crtc->config->has_pch_encoder)
4798 intel_wait_for_vblank(dev, pipe);
4799 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4800 }
4801
4802 /* IPS only exists on ULT machines and is tied to pipe A. */
4803 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4804 {
4805 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4806 }
4807
4808 static void haswell_crtc_enable(struct drm_crtc *crtc)
4809 {
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813 struct intel_encoder *encoder;
4814 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4815 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4816 struct intel_crtc_state *pipe_config =
4817 to_intel_crtc_state(crtc->state);
4818
4819 if (WARN_ON(intel_crtc->active))
4820 return;
4821
4822 if (intel_crtc->config->has_pch_encoder)
4823 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4824 false);
4825
4826 if (intel_crtc->config->shared_dpll)
4827 intel_enable_shared_dpll(intel_crtc);
4828
4829 if (intel_crtc->config->has_dp_encoder)
4830 intel_dp_set_m_n(intel_crtc, M1_N1);
4831
4832 if (!intel_crtc->config->has_dsi_encoder)
4833 intel_set_pipe_timings(intel_crtc);
4834
4835 intel_set_pipe_src_size(intel_crtc);
4836
4837 if (cpu_transcoder != TRANSCODER_EDP &&
4838 !transcoder_is_dsi(cpu_transcoder)) {
4839 I915_WRITE(PIPE_MULT(cpu_transcoder),
4840 intel_crtc->config->pixel_multiplier - 1);
4841 }
4842
4843 if (intel_crtc->config->has_pch_encoder) {
4844 intel_cpu_transcoder_set_m_n(intel_crtc,
4845 &intel_crtc->config->fdi_m_n, NULL);
4846 }
4847
4848 if (!intel_crtc->config->has_dsi_encoder)
4849 haswell_set_pipeconf(crtc);
4850
4851 haswell_set_pipemisc(crtc);
4852
4853 intel_color_set_csc(&pipe_config->base);
4854
4855 intel_crtc->active = true;
4856
4857 if (intel_crtc->config->has_pch_encoder)
4858 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4859 else
4860 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4861
4862 for_each_encoder_on_crtc(dev, crtc, encoder) {
4863 if (encoder->pre_enable)
4864 encoder->pre_enable(encoder);
4865 }
4866
4867 if (intel_crtc->config->has_pch_encoder)
4868 dev_priv->display.fdi_link_train(crtc);
4869
4870 if (!intel_crtc->config->has_dsi_encoder)
4871 intel_ddi_enable_pipe_clock(intel_crtc);
4872
4873 if (INTEL_INFO(dev)->gen >= 9)
4874 skylake_pfit_enable(intel_crtc);
4875 else
4876 ironlake_pfit_enable(intel_crtc);
4877
4878 /*
4879 * On ILK+ LUT must be loaded before the pipe is running but with
4880 * clocks enabled
4881 */
4882 intel_color_load_luts(&pipe_config->base);
4883
4884 intel_ddi_set_pipe_settings(crtc);
4885 if (!intel_crtc->config->has_dsi_encoder)
4886 intel_ddi_enable_transcoder_func(crtc);
4887
4888 if (dev_priv->display.initial_watermarks != NULL)
4889 dev_priv->display.initial_watermarks(pipe_config);
4890 else
4891 intel_update_watermarks(crtc);
4892
4893 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4894 if (!intel_crtc->config->has_dsi_encoder)
4895 intel_enable_pipe(intel_crtc);
4896
4897 if (intel_crtc->config->has_pch_encoder)
4898 lpt_pch_enable(crtc);
4899
4900 if (intel_crtc->config->dp_encoder_is_mst)
4901 intel_ddi_set_vc_payload_alloc(crtc, true);
4902
4903 assert_vblank_disabled(crtc);
4904 drm_crtc_vblank_on(crtc);
4905
4906 for_each_encoder_on_crtc(dev, crtc, encoder) {
4907 encoder->enable(encoder);
4908 intel_opregion_notify_encoder(encoder, true);
4909 }
4910
4911 if (intel_crtc->config->has_pch_encoder) {
4912 intel_wait_for_vblank(dev, pipe);
4913 intel_wait_for_vblank(dev, pipe);
4914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4915 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4916 true);
4917 }
4918
4919 /* If we change the relative order between pipe/planes enabling, we need
4920 * to change the workaround. */
4921 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4922 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4923 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4924 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4925 }
4926 }
4927
4928 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4929 {
4930 struct drm_device *dev = crtc->base.dev;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 int pipe = crtc->pipe;
4933
4934 /* To avoid upsetting the power well on haswell only disable the pfit if
4935 * it's in use. The hw state code will make sure we get this right. */
4936 if (force || crtc->config->pch_pfit.enabled) {
4937 I915_WRITE(PF_CTL(pipe), 0);
4938 I915_WRITE(PF_WIN_POS(pipe), 0);
4939 I915_WRITE(PF_WIN_SZ(pipe), 0);
4940 }
4941 }
4942
4943 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 struct intel_encoder *encoder;
4949 int pipe = intel_crtc->pipe;
4950
4951 if (intel_crtc->config->has_pch_encoder)
4952 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4953
4954 for_each_encoder_on_crtc(dev, crtc, encoder)
4955 encoder->disable(encoder);
4956
4957 drm_crtc_vblank_off(crtc);
4958 assert_vblank_disabled(crtc);
4959
4960 /*
4961 * Sometimes spurious CPU pipe underruns happen when the
4962 * pipe is already disabled, but FDI RX/TX is still enabled.
4963 * Happens at least with VGA+HDMI cloning. Suppress them.
4964 */
4965 if (intel_crtc->config->has_pch_encoder)
4966 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4967
4968 intel_disable_pipe(intel_crtc);
4969
4970 ironlake_pfit_disable(intel_crtc, false);
4971
4972 if (intel_crtc->config->has_pch_encoder) {
4973 ironlake_fdi_disable(crtc);
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4975 }
4976
4977 for_each_encoder_on_crtc(dev, crtc, encoder)
4978 if (encoder->post_disable)
4979 encoder->post_disable(encoder);
4980
4981 if (intel_crtc->config->has_pch_encoder) {
4982 ironlake_disable_pch_transcoder(dev_priv, pipe);
4983
4984 if (HAS_PCH_CPT(dev)) {
4985 i915_reg_t reg;
4986 u32 temp;
4987
4988 /* disable TRANS_DP_CTL */
4989 reg = TRANS_DP_CTL(pipe);
4990 temp = I915_READ(reg);
4991 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4992 TRANS_DP_PORT_SEL_MASK);
4993 temp |= TRANS_DP_PORT_SEL_NONE;
4994 I915_WRITE(reg, temp);
4995
4996 /* disable DPLL_SEL */
4997 temp = I915_READ(PCH_DPLL_SEL);
4998 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4999 I915_WRITE(PCH_DPLL_SEL, temp);
5000 }
5001
5002 ironlake_fdi_pll_disable(intel_crtc);
5003 }
5004
5005 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5006 }
5007
5008 static void haswell_crtc_disable(struct drm_crtc *crtc)
5009 {
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013 struct intel_encoder *encoder;
5014 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5015
5016 if (intel_crtc->config->has_pch_encoder)
5017 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5018 false);
5019
5020 for_each_encoder_on_crtc(dev, crtc, encoder) {
5021 intel_opregion_notify_encoder(encoder, false);
5022 encoder->disable(encoder);
5023 }
5024
5025 drm_crtc_vblank_off(crtc);
5026 assert_vblank_disabled(crtc);
5027
5028 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5029 if (!intel_crtc->config->has_dsi_encoder)
5030 intel_disable_pipe(intel_crtc);
5031
5032 if (intel_crtc->config->dp_encoder_is_mst)
5033 intel_ddi_set_vc_payload_alloc(crtc, false);
5034
5035 if (!intel_crtc->config->has_dsi_encoder)
5036 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5037
5038 if (INTEL_INFO(dev)->gen >= 9)
5039 skylake_scaler_disable(intel_crtc);
5040 else
5041 ironlake_pfit_disable(intel_crtc, false);
5042
5043 if (!intel_crtc->config->has_dsi_encoder)
5044 intel_ddi_disable_pipe_clock(intel_crtc);
5045
5046 for_each_encoder_on_crtc(dev, crtc, encoder)
5047 if (encoder->post_disable)
5048 encoder->post_disable(encoder);
5049
5050 if (intel_crtc->config->has_pch_encoder) {
5051 lpt_disable_pch_transcoder(dev_priv);
5052 lpt_disable_iclkip(dev_priv);
5053 intel_ddi_fdi_disable(crtc);
5054
5055 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5056 true);
5057 }
5058 }
5059
5060 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5061 {
5062 struct drm_device *dev = crtc->base.dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 struct intel_crtc_state *pipe_config = crtc->config;
5065
5066 if (!pipe_config->gmch_pfit.control)
5067 return;
5068
5069 /*
5070 * The panel fitter should only be adjusted whilst the pipe is disabled,
5071 * according to register description and PRM.
5072 */
5073 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5074 assert_pipe_disabled(dev_priv, crtc->pipe);
5075
5076 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5077 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5078
5079 /* Border color in case we don't scale up to the full screen. Black by
5080 * default, change to something else for debugging. */
5081 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5082 }
5083
5084 static enum intel_display_power_domain port_to_power_domain(enum port port)
5085 {
5086 switch (port) {
5087 case PORT_A:
5088 return POWER_DOMAIN_PORT_DDI_A_LANES;
5089 case PORT_B:
5090 return POWER_DOMAIN_PORT_DDI_B_LANES;
5091 case PORT_C:
5092 return POWER_DOMAIN_PORT_DDI_C_LANES;
5093 case PORT_D:
5094 return POWER_DOMAIN_PORT_DDI_D_LANES;
5095 case PORT_E:
5096 return POWER_DOMAIN_PORT_DDI_E_LANES;
5097 default:
5098 MISSING_CASE(port);
5099 return POWER_DOMAIN_PORT_OTHER;
5100 }
5101 }
5102
5103 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5104 {
5105 switch (port) {
5106 case PORT_A:
5107 return POWER_DOMAIN_AUX_A;
5108 case PORT_B:
5109 return POWER_DOMAIN_AUX_B;
5110 case PORT_C:
5111 return POWER_DOMAIN_AUX_C;
5112 case PORT_D:
5113 return POWER_DOMAIN_AUX_D;
5114 case PORT_E:
5115 /* FIXME: Check VBT for actual wiring of PORT E */
5116 return POWER_DOMAIN_AUX_D;
5117 default:
5118 MISSING_CASE(port);
5119 return POWER_DOMAIN_AUX_A;
5120 }
5121 }
5122
5123 enum intel_display_power_domain
5124 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5125 {
5126 struct drm_device *dev = intel_encoder->base.dev;
5127 struct intel_digital_port *intel_dig_port;
5128
5129 switch (intel_encoder->type) {
5130 case INTEL_OUTPUT_UNKNOWN:
5131 /* Only DDI platforms should ever use this output type */
5132 WARN_ON_ONCE(!HAS_DDI(dev));
5133 case INTEL_OUTPUT_DISPLAYPORT:
5134 case INTEL_OUTPUT_HDMI:
5135 case INTEL_OUTPUT_EDP:
5136 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5137 return port_to_power_domain(intel_dig_port->port);
5138 case INTEL_OUTPUT_DP_MST:
5139 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5140 return port_to_power_domain(intel_dig_port->port);
5141 case INTEL_OUTPUT_ANALOG:
5142 return POWER_DOMAIN_PORT_CRT;
5143 case INTEL_OUTPUT_DSI:
5144 return POWER_DOMAIN_PORT_DSI;
5145 default:
5146 return POWER_DOMAIN_PORT_OTHER;
5147 }
5148 }
5149
5150 enum intel_display_power_domain
5151 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5152 {
5153 struct drm_device *dev = intel_encoder->base.dev;
5154 struct intel_digital_port *intel_dig_port;
5155
5156 switch (intel_encoder->type) {
5157 case INTEL_OUTPUT_UNKNOWN:
5158 case INTEL_OUTPUT_HDMI:
5159 /*
5160 * Only DDI platforms should ever use these output types.
5161 * We can get here after the HDMI detect code has already set
5162 * the type of the shared encoder. Since we can't be sure
5163 * what's the status of the given connectors, play safe and
5164 * run the DP detection too.
5165 */
5166 WARN_ON_ONCE(!HAS_DDI(dev));
5167 case INTEL_OUTPUT_DISPLAYPORT:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_aux_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_aux_power_domain(intel_dig_port->port);
5174 default:
5175 MISSING_CASE(intel_encoder->type);
5176 return POWER_DOMAIN_AUX_A;
5177 }
5178 }
5179
5180 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5181 struct intel_crtc_state *crtc_state)
5182 {
5183 struct drm_device *dev = crtc->dev;
5184 struct drm_encoder *encoder;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 enum pipe pipe = intel_crtc->pipe;
5187 unsigned long mask;
5188 enum transcoder transcoder = crtc_state->cpu_transcoder;
5189
5190 if (!crtc_state->base.active)
5191 return 0;
5192
5193 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5194 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5195 if (crtc_state->pch_pfit.enabled ||
5196 crtc_state->pch_pfit.force_thru)
5197 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5198
5199 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5200 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5201
5202 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5203 }
5204
5205 if (crtc_state->shared_dpll)
5206 mask |= BIT(POWER_DOMAIN_PLLS);
5207
5208 return mask;
5209 }
5210
5211 static unsigned long
5212 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5213 struct intel_crtc_state *crtc_state)
5214 {
5215 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5217 enum intel_display_power_domain domain;
5218 unsigned long domains, new_domains, old_domains;
5219
5220 old_domains = intel_crtc->enabled_power_domains;
5221 intel_crtc->enabled_power_domains = new_domains =
5222 get_crtc_power_domains(crtc, crtc_state);
5223
5224 domains = new_domains & ~old_domains;
5225
5226 for_each_power_domain(domain, domains)
5227 intel_display_power_get(dev_priv, domain);
5228
5229 return old_domains & ~new_domains;
5230 }
5231
5232 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5233 unsigned long domains)
5234 {
5235 enum intel_display_power_domain domain;
5236
5237 for_each_power_domain(domain, domains)
5238 intel_display_power_put(dev_priv, domain);
5239 }
5240
5241 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5242 {
5243 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5244
5245 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5246 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5247 return max_cdclk_freq;
5248 else if (IS_CHERRYVIEW(dev_priv))
5249 return max_cdclk_freq*95/100;
5250 else if (INTEL_INFO(dev_priv)->gen < 4)
5251 return 2*max_cdclk_freq*90/100;
5252 else
5253 return max_cdclk_freq*90/100;
5254 }
5255
5256 static void intel_update_max_cdclk(struct drm_device *dev)
5257 {
5258 struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5261 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5262
5263 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5264 dev_priv->max_cdclk_freq = 675000;
5265 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5266 dev_priv->max_cdclk_freq = 540000;
5267 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5268 dev_priv->max_cdclk_freq = 450000;
5269 else
5270 dev_priv->max_cdclk_freq = 337500;
5271 } else if (IS_BROXTON(dev)) {
5272 dev_priv->max_cdclk_freq = 624000;
5273 } else if (IS_BROADWELL(dev)) {
5274 /*
5275 * FIXME with extra cooling we can allow
5276 * 540 MHz for ULX and 675 Mhz for ULT.
5277 * How can we know if extra cooling is
5278 * available? PCI ID, VTB, something else?
5279 */
5280 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5281 dev_priv->max_cdclk_freq = 450000;
5282 else if (IS_BDW_ULX(dev))
5283 dev_priv->max_cdclk_freq = 450000;
5284 else if (IS_BDW_ULT(dev))
5285 dev_priv->max_cdclk_freq = 540000;
5286 else
5287 dev_priv->max_cdclk_freq = 675000;
5288 } else if (IS_CHERRYVIEW(dev)) {
5289 dev_priv->max_cdclk_freq = 320000;
5290 } else if (IS_VALLEYVIEW(dev)) {
5291 dev_priv->max_cdclk_freq = 400000;
5292 } else {
5293 /* otherwise assume cdclk is fixed */
5294 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5295 }
5296
5297 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5298
5299 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5300 dev_priv->max_cdclk_freq);
5301
5302 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5303 dev_priv->max_dotclk_freq);
5304 }
5305
5306 static void intel_update_cdclk(struct drm_device *dev)
5307 {
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309
5310 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5311 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5312 dev_priv->cdclk_freq);
5313
5314 /*
5315 * Program the gmbus_freq based on the cdclk frequency.
5316 * BSpec erroneously claims we should aim for 4MHz, but
5317 * in fact 1MHz is the correct frequency.
5318 */
5319 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5320 /*
5321 * Program the gmbus_freq based on the cdclk frequency.
5322 * BSpec erroneously claims we should aim for 4MHz, but
5323 * in fact 1MHz is the correct frequency.
5324 */
5325 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5326 }
5327
5328 if (dev_priv->max_cdclk_freq == 0)
5329 intel_update_max_cdclk(dev);
5330 }
5331
5332 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5333 {
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335 uint32_t divider;
5336 uint32_t ratio;
5337 uint32_t current_freq;
5338 int ret;
5339
5340 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5341 switch (frequency) {
5342 case 144000:
5343 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5344 ratio = BXT_DE_PLL_RATIO(60);
5345 break;
5346 case 288000:
5347 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5348 ratio = BXT_DE_PLL_RATIO(60);
5349 break;
5350 case 384000:
5351 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5352 ratio = BXT_DE_PLL_RATIO(60);
5353 break;
5354 case 576000:
5355 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5356 ratio = BXT_DE_PLL_RATIO(60);
5357 break;
5358 case 624000:
5359 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5360 ratio = BXT_DE_PLL_RATIO(65);
5361 break;
5362 case 19200:
5363 /*
5364 * Bypass frequency with DE PLL disabled. Init ratio, divider
5365 * to suppress GCC warning.
5366 */
5367 ratio = 0;
5368 divider = 0;
5369 break;
5370 default:
5371 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5372
5373 return;
5374 }
5375
5376 mutex_lock(&dev_priv->rps.hw_lock);
5377 /* Inform power controller of upcoming frequency change */
5378 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5379 0x80000000);
5380 mutex_unlock(&dev_priv->rps.hw_lock);
5381
5382 if (ret) {
5383 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5384 ret, frequency);
5385 return;
5386 }
5387
5388 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5389 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5390 current_freq = current_freq * 500 + 1000;
5391
5392 /*
5393 * DE PLL has to be disabled when
5394 * - setting to 19.2MHz (bypass, PLL isn't used)
5395 * - before setting to 624MHz (PLL needs toggling)
5396 * - before setting to any frequency from 624MHz (PLL needs toggling)
5397 */
5398 if (frequency == 19200 || frequency == 624000 ||
5399 current_freq == 624000) {
5400 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5401 /* Timeout 200us */
5402 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5403 1))
5404 DRM_ERROR("timout waiting for DE PLL unlock\n");
5405 }
5406
5407 if (frequency != 19200) {
5408 uint32_t val;
5409
5410 val = I915_READ(BXT_DE_PLL_CTL);
5411 val &= ~BXT_DE_PLL_RATIO_MASK;
5412 val |= ratio;
5413 I915_WRITE(BXT_DE_PLL_CTL, val);
5414
5415 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5416 /* Timeout 200us */
5417 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5418 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419
5420 val = I915_READ(CDCLK_CTL);
5421 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5422 val |= divider;
5423 /*
5424 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5425 * enable otherwise.
5426 */
5427 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5428 if (frequency >= 500000)
5429 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5430
5431 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5432 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5433 val |= (frequency - 1000) / 500;
5434 I915_WRITE(CDCLK_CTL, val);
5435 }
5436
5437 mutex_lock(&dev_priv->rps.hw_lock);
5438 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5439 DIV_ROUND_UP(frequency, 25000));
5440 mutex_unlock(&dev_priv->rps.hw_lock);
5441
5442 if (ret) {
5443 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5444 ret, frequency);
5445 return;
5446 }
5447
5448 intel_update_cdclk(dev);
5449 }
5450
5451 void broxton_init_cdclk(struct drm_device *dev)
5452 {
5453 struct drm_i915_private *dev_priv = dev->dev_private;
5454 uint32_t val;
5455
5456 /*
5457 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5458 * or else the reset will hang because there is no PCH to respond.
5459 * Move the handshake programming to initialization sequence.
5460 * Previously was left up to BIOS.
5461 */
5462 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5463 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5464 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5465
5466 /* Enable PG1 for cdclk */
5467 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5468
5469 /* check if cd clock is enabled */
5470 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5471 DRM_DEBUG_KMS("Display already initialized\n");
5472 return;
5473 }
5474
5475 /*
5476 * FIXME:
5477 * - The initial CDCLK needs to be read from VBT.
5478 * Need to make this change after VBT has changes for BXT.
5479 * - check if setting the max (or any) cdclk freq is really necessary
5480 * here, it belongs to modeset time
5481 */
5482 broxton_set_cdclk(dev, 624000);
5483
5484 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5485 POSTING_READ(DBUF_CTL);
5486
5487 udelay(10);
5488
5489 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5490 DRM_ERROR("DBuf power enable timeout!\n");
5491 }
5492
5493 void broxton_uninit_cdclk(struct drm_device *dev)
5494 {
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496
5497 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5498 POSTING_READ(DBUF_CTL);
5499
5500 udelay(10);
5501
5502 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5503 DRM_ERROR("DBuf power disable timeout!\n");
5504
5505 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5506 broxton_set_cdclk(dev, 19200);
5507
5508 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5509 }
5510
5511 static const struct skl_cdclk_entry {
5512 unsigned int freq;
5513 unsigned int vco;
5514 } skl_cdclk_frequencies[] = {
5515 { .freq = 308570, .vco = 8640 },
5516 { .freq = 337500, .vco = 8100 },
5517 { .freq = 432000, .vco = 8640 },
5518 { .freq = 450000, .vco = 8100 },
5519 { .freq = 540000, .vco = 8100 },
5520 { .freq = 617140, .vco = 8640 },
5521 { .freq = 675000, .vco = 8100 },
5522 };
5523
5524 static unsigned int skl_cdclk_decimal(unsigned int freq)
5525 {
5526 return (freq - 1000) / 500;
5527 }
5528
5529 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5530 {
5531 unsigned int i;
5532
5533 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5534 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5535
5536 if (e->freq == freq)
5537 return e->vco;
5538 }
5539
5540 return 8100;
5541 }
5542
5543 static void
5544 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5545 {
5546 unsigned int min_freq;
5547 u32 val;
5548
5549 /* select the minimum CDCLK before enabling DPLL 0 */
5550 val = I915_READ(CDCLK_CTL);
5551 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5552 val |= CDCLK_FREQ_337_308;
5553
5554 if (required_vco == 8640)
5555 min_freq = 308570;
5556 else
5557 min_freq = 337500;
5558
5559 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5560
5561 I915_WRITE(CDCLK_CTL, val);
5562 POSTING_READ(CDCLK_CTL);
5563
5564 /*
5565 * We always enable DPLL0 with the lowest link rate possible, but still
5566 * taking into account the VCO required to operate the eDP panel at the
5567 * desired frequency. The usual DP link rates operate with a VCO of
5568 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5569 * The modeset code is responsible for the selection of the exact link
5570 * rate later on, with the constraint of choosing a frequency that
5571 * works with required_vco.
5572 */
5573 val = I915_READ(DPLL_CTRL1);
5574
5575 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5576 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5577 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5578 if (required_vco == 8640)
5579 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5580 SKL_DPLL0);
5581 else
5582 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5583 SKL_DPLL0);
5584
5585 I915_WRITE(DPLL_CTRL1, val);
5586 POSTING_READ(DPLL_CTRL1);
5587
5588 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5589
5590 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5591 DRM_ERROR("DPLL0 not locked\n");
5592 }
5593
5594 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5595 {
5596 int ret;
5597 u32 val;
5598
5599 /* inform PCU we want to change CDCLK */
5600 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5601 mutex_lock(&dev_priv->rps.hw_lock);
5602 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5603 mutex_unlock(&dev_priv->rps.hw_lock);
5604
5605 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5606 }
5607
5608 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5609 {
5610 unsigned int i;
5611
5612 for (i = 0; i < 15; i++) {
5613 if (skl_cdclk_pcu_ready(dev_priv))
5614 return true;
5615 udelay(10);
5616 }
5617
5618 return false;
5619 }
5620
5621 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5622 {
5623 struct drm_device *dev = dev_priv->dev;
5624 u32 freq_select, pcu_ack;
5625
5626 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5627
5628 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5629 DRM_ERROR("failed to inform PCU about cdclk change\n");
5630 return;
5631 }
5632
5633 /* set CDCLK_CTL */
5634 switch(freq) {
5635 case 450000:
5636 case 432000:
5637 freq_select = CDCLK_FREQ_450_432;
5638 pcu_ack = 1;
5639 break;
5640 case 540000:
5641 freq_select = CDCLK_FREQ_540;
5642 pcu_ack = 2;
5643 break;
5644 case 308570:
5645 case 337500:
5646 default:
5647 freq_select = CDCLK_FREQ_337_308;
5648 pcu_ack = 0;
5649 break;
5650 case 617140:
5651 case 675000:
5652 freq_select = CDCLK_FREQ_675_617;
5653 pcu_ack = 3;
5654 break;
5655 }
5656
5657 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5658 POSTING_READ(CDCLK_CTL);
5659
5660 /* inform PCU of the change */
5661 mutex_lock(&dev_priv->rps.hw_lock);
5662 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5663 mutex_unlock(&dev_priv->rps.hw_lock);
5664
5665 intel_update_cdclk(dev);
5666 }
5667
5668 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5669 {
5670 /* disable DBUF power */
5671 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5672 POSTING_READ(DBUF_CTL);
5673
5674 udelay(10);
5675
5676 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5677 DRM_ERROR("DBuf power disable timeout\n");
5678
5679 /* disable DPLL0 */
5680 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5681 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5682 DRM_ERROR("Couldn't disable DPLL0\n");
5683 }
5684
5685 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687 unsigned int required_vco;
5688
5689 /* DPLL0 not enabled (happens on early BIOS versions) */
5690 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5691 /* enable DPLL0 */
5692 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5693 skl_dpll0_enable(dev_priv, required_vco);
5694 }
5695
5696 /* set CDCLK to the frequency the BIOS chose */
5697 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5698
5699 /* enable DBUF power */
5700 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5701 POSTING_READ(DBUF_CTL);
5702
5703 udelay(10);
5704
5705 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5706 DRM_ERROR("DBuf power enable timeout\n");
5707 }
5708
5709 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5710 {
5711 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5712 uint32_t cdctl = I915_READ(CDCLK_CTL);
5713 int freq = dev_priv->skl_boot_cdclk;
5714
5715 /*
5716 * check if the pre-os intialized the display
5717 * There is SWF18 scratchpad register defined which is set by the
5718 * pre-os which can be used by the OS drivers to check the status
5719 */
5720 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5721 goto sanitize;
5722
5723 /* Is PLL enabled and locked ? */
5724 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5725 goto sanitize;
5726
5727 /* DPLL okay; verify the cdclock
5728 *
5729 * Noticed in some instances that the freq selection is correct but
5730 * decimal part is programmed wrong from BIOS where pre-os does not
5731 * enable display. Verify the same as well.
5732 */
5733 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5734 /* All well; nothing to sanitize */
5735 return false;
5736 sanitize:
5737 /*
5738 * As of now initialize with max cdclk till
5739 * we get dynamic cdclk support
5740 * */
5741 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5742 skl_init_cdclk(dev_priv);
5743
5744 /* we did have to sanitize */
5745 return true;
5746 }
5747
5748 /* Adjust CDclk dividers to allow high res or save power if possible */
5749 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5750 {
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 u32 val, cmd;
5753
5754 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5755 != dev_priv->cdclk_freq);
5756
5757 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5758 cmd = 2;
5759 else if (cdclk == 266667)
5760 cmd = 1;
5761 else
5762 cmd = 0;
5763
5764 mutex_lock(&dev_priv->rps.hw_lock);
5765 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5766 val &= ~DSPFREQGUAR_MASK;
5767 val |= (cmd << DSPFREQGUAR_SHIFT);
5768 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5769 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5770 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5771 50)) {
5772 DRM_ERROR("timed out waiting for CDclk change\n");
5773 }
5774 mutex_unlock(&dev_priv->rps.hw_lock);
5775
5776 mutex_lock(&dev_priv->sb_lock);
5777
5778 if (cdclk == 400000) {
5779 u32 divider;
5780
5781 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5782
5783 /* adjust cdclk divider */
5784 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5785 val &= ~CCK_FREQUENCY_VALUES;
5786 val |= divider;
5787 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5788
5789 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5790 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5791 50))
5792 DRM_ERROR("timed out waiting for CDclk change\n");
5793 }
5794
5795 /* adjust self-refresh exit latency value */
5796 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5797 val &= ~0x7f;
5798
5799 /*
5800 * For high bandwidth configs, we set a higher latency in the bunit
5801 * so that the core display fetch happens in time to avoid underruns.
5802 */
5803 if (cdclk == 400000)
5804 val |= 4500 / 250; /* 4.5 usec */
5805 else
5806 val |= 3000 / 250; /* 3.0 usec */
5807 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5808
5809 mutex_unlock(&dev_priv->sb_lock);
5810
5811 intel_update_cdclk(dev);
5812 }
5813
5814 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5815 {
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 u32 val, cmd;
5818
5819 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5820 != dev_priv->cdclk_freq);
5821
5822 switch (cdclk) {
5823 case 333333:
5824 case 320000:
5825 case 266667:
5826 case 200000:
5827 break;
5828 default:
5829 MISSING_CASE(cdclk);
5830 return;
5831 }
5832
5833 /*
5834 * Specs are full of misinformation, but testing on actual
5835 * hardware has shown that we just need to write the desired
5836 * CCK divider into the Punit register.
5837 */
5838 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5839
5840 mutex_lock(&dev_priv->rps.hw_lock);
5841 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5842 val &= ~DSPFREQGUAR_MASK_CHV;
5843 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5844 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5845 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5846 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5847 50)) {
5848 DRM_ERROR("timed out waiting for CDclk change\n");
5849 }
5850 mutex_unlock(&dev_priv->rps.hw_lock);
5851
5852 intel_update_cdclk(dev);
5853 }
5854
5855 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5856 int max_pixclk)
5857 {
5858 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5859 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5860
5861 /*
5862 * Really only a few cases to deal with, as only 4 CDclks are supported:
5863 * 200MHz
5864 * 267MHz
5865 * 320/333MHz (depends on HPLL freq)
5866 * 400MHz (VLV only)
5867 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5868 * of the lower bin and adjust if needed.
5869 *
5870 * We seem to get an unstable or solid color picture at 200MHz.
5871 * Not sure what's wrong. For now use 200MHz only when all pipes
5872 * are off.
5873 */
5874 if (!IS_CHERRYVIEW(dev_priv) &&
5875 max_pixclk > freq_320*limit/100)
5876 return 400000;
5877 else if (max_pixclk > 266667*limit/100)
5878 return freq_320;
5879 else if (max_pixclk > 0)
5880 return 266667;
5881 else
5882 return 200000;
5883 }
5884
5885 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5886 int max_pixclk)
5887 {
5888 /*
5889 * FIXME:
5890 * - remove the guardband, it's not needed on BXT
5891 * - set 19.2MHz bypass frequency if there are no active pipes
5892 */
5893 if (max_pixclk > 576000*9/10)
5894 return 624000;
5895 else if (max_pixclk > 384000*9/10)
5896 return 576000;
5897 else if (max_pixclk > 288000*9/10)
5898 return 384000;
5899 else if (max_pixclk > 144000*9/10)
5900 return 288000;
5901 else
5902 return 144000;
5903 }
5904
5905 /* Compute the max pixel clock for new configuration. */
5906 static int intel_mode_max_pixclk(struct drm_device *dev,
5907 struct drm_atomic_state *state)
5908 {
5909 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911 struct drm_crtc *crtc;
5912 struct drm_crtc_state *crtc_state;
5913 unsigned max_pixclk = 0, i;
5914 enum pipe pipe;
5915
5916 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5917 sizeof(intel_state->min_pixclk));
5918
5919 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5920 int pixclk = 0;
5921
5922 if (crtc_state->enable)
5923 pixclk = crtc_state->adjusted_mode.crtc_clock;
5924
5925 intel_state->min_pixclk[i] = pixclk;
5926 }
5927
5928 for_each_pipe(dev_priv, pipe)
5929 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5930
5931 return max_pixclk;
5932 }
5933
5934 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5935 {
5936 struct drm_device *dev = state->dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 int max_pixclk = intel_mode_max_pixclk(dev, state);
5939 struct intel_atomic_state *intel_state =
5940 to_intel_atomic_state(state);
5941
5942 if (max_pixclk < 0)
5943 return max_pixclk;
5944
5945 intel_state->cdclk = intel_state->dev_cdclk =
5946 valleyview_calc_cdclk(dev_priv, max_pixclk);
5947
5948 if (!intel_state->active_crtcs)
5949 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5950
5951 return 0;
5952 }
5953
5954 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5955 {
5956 struct drm_device *dev = state->dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958 int max_pixclk = intel_mode_max_pixclk(dev, state);
5959 struct intel_atomic_state *intel_state =
5960 to_intel_atomic_state(state);
5961
5962 if (max_pixclk < 0)
5963 return max_pixclk;
5964
5965 intel_state->cdclk = intel_state->dev_cdclk =
5966 broxton_calc_cdclk(dev_priv, max_pixclk);
5967
5968 if (!intel_state->active_crtcs)
5969 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5970
5971 return 0;
5972 }
5973
5974 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5975 {
5976 unsigned int credits, default_credits;
5977
5978 if (IS_CHERRYVIEW(dev_priv))
5979 default_credits = PFI_CREDIT(12);
5980 else
5981 default_credits = PFI_CREDIT(8);
5982
5983 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5984 /* CHV suggested value is 31 or 63 */
5985 if (IS_CHERRYVIEW(dev_priv))
5986 credits = PFI_CREDIT_63;
5987 else
5988 credits = PFI_CREDIT(15);
5989 } else {
5990 credits = default_credits;
5991 }
5992
5993 /*
5994 * WA - write default credits before re-programming
5995 * FIXME: should we also set the resend bit here?
5996 */
5997 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5998 default_credits);
5999
6000 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6001 credits | PFI_CREDIT_RESEND);
6002
6003 /*
6004 * FIXME is this guaranteed to clear
6005 * immediately or should we poll for it?
6006 */
6007 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6008 }
6009
6010 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6011 {
6012 struct drm_device *dev = old_state->dev;
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 struct intel_atomic_state *old_intel_state =
6015 to_intel_atomic_state(old_state);
6016 unsigned req_cdclk = old_intel_state->dev_cdclk;
6017
6018 /*
6019 * FIXME: We can end up here with all power domains off, yet
6020 * with a CDCLK frequency other than the minimum. To account
6021 * for this take the PIPE-A power domain, which covers the HW
6022 * blocks needed for the following programming. This can be
6023 * removed once it's guaranteed that we get here either with
6024 * the minimum CDCLK set, or the required power domains
6025 * enabled.
6026 */
6027 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6028
6029 if (IS_CHERRYVIEW(dev))
6030 cherryview_set_cdclk(dev, req_cdclk);
6031 else
6032 valleyview_set_cdclk(dev, req_cdclk);
6033
6034 vlv_program_pfi_credits(dev_priv);
6035
6036 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6037 }
6038
6039 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6040 {
6041 struct drm_device *dev = crtc->dev;
6042 struct drm_i915_private *dev_priv = to_i915(dev);
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6044 struct intel_encoder *encoder;
6045 struct intel_crtc_state *pipe_config =
6046 to_intel_crtc_state(crtc->state);
6047 int pipe = intel_crtc->pipe;
6048
6049 if (WARN_ON(intel_crtc->active))
6050 return;
6051
6052 if (intel_crtc->config->has_dp_encoder)
6053 intel_dp_set_m_n(intel_crtc, M1_N1);
6054
6055 intel_set_pipe_timings(intel_crtc);
6056 intel_set_pipe_src_size(intel_crtc);
6057
6058 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060
6061 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6062 I915_WRITE(CHV_CANVAS(pipe), 0);
6063 }
6064
6065 i9xx_set_pipeconf(intel_crtc);
6066
6067 intel_crtc->active = true;
6068
6069 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6070
6071 for_each_encoder_on_crtc(dev, crtc, encoder)
6072 if (encoder->pre_pll_enable)
6073 encoder->pre_pll_enable(encoder);
6074
6075 if (!intel_crtc->config->has_dsi_encoder) {
6076 if (IS_CHERRYVIEW(dev)) {
6077 chv_prepare_pll(intel_crtc, intel_crtc->config);
6078 chv_enable_pll(intel_crtc, intel_crtc->config);
6079 } else {
6080 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6081 vlv_enable_pll(intel_crtc, intel_crtc->config);
6082 }
6083 }
6084
6085 for_each_encoder_on_crtc(dev, crtc, encoder)
6086 if (encoder->pre_enable)
6087 encoder->pre_enable(encoder);
6088
6089 i9xx_pfit_enable(intel_crtc);
6090
6091 intel_color_load_luts(&pipe_config->base);
6092
6093 intel_update_watermarks(crtc);
6094 intel_enable_pipe(intel_crtc);
6095
6096 assert_vblank_disabled(crtc);
6097 drm_crtc_vblank_on(crtc);
6098
6099 for_each_encoder_on_crtc(dev, crtc, encoder)
6100 encoder->enable(encoder);
6101 }
6102
6103 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6104 {
6105 struct drm_device *dev = crtc->base.dev;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6109 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6110 }
6111
6112 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6113 {
6114 struct drm_device *dev = crtc->dev;
6115 struct drm_i915_private *dev_priv = to_i915(dev);
6116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117 struct intel_encoder *encoder;
6118 struct intel_crtc_state *pipe_config =
6119 to_intel_crtc_state(crtc->state);
6120 int pipe = intel_crtc->pipe;
6121
6122 if (WARN_ON(intel_crtc->active))
6123 return;
6124
6125 i9xx_set_pll_dividers(intel_crtc);
6126
6127 if (intel_crtc->config->has_dp_encoder)
6128 intel_dp_set_m_n(intel_crtc, M1_N1);
6129
6130 intel_set_pipe_timings(intel_crtc);
6131 intel_set_pipe_src_size(intel_crtc);
6132
6133 i9xx_set_pipeconf(intel_crtc);
6134
6135 intel_crtc->active = true;
6136
6137 if (!IS_GEN2(dev))
6138 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6139
6140 for_each_encoder_on_crtc(dev, crtc, encoder)
6141 if (encoder->pre_enable)
6142 encoder->pre_enable(encoder);
6143
6144 i9xx_enable_pll(intel_crtc);
6145
6146 i9xx_pfit_enable(intel_crtc);
6147
6148 intel_color_load_luts(&pipe_config->base);
6149
6150 intel_update_watermarks(crtc);
6151 intel_enable_pipe(intel_crtc);
6152
6153 assert_vblank_disabled(crtc);
6154 drm_crtc_vblank_on(crtc);
6155
6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 encoder->enable(encoder);
6158 }
6159
6160 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164
6165 if (!crtc->config->gmch_pfit.control)
6166 return;
6167
6168 assert_pipe_disabled(dev_priv, crtc->pipe);
6169
6170 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6171 I915_READ(PFIT_CONTROL));
6172 I915_WRITE(PFIT_CONTROL, 0);
6173 }
6174
6175 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6176 {
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 struct intel_encoder *encoder;
6181 int pipe = intel_crtc->pipe;
6182
6183 /*
6184 * On gen2 planes are double buffered but the pipe isn't, so we must
6185 * wait for planes to fully turn off before disabling the pipe.
6186 */
6187 if (IS_GEN2(dev))
6188 intel_wait_for_vblank(dev, pipe);
6189
6190 for_each_encoder_on_crtc(dev, crtc, encoder)
6191 encoder->disable(encoder);
6192
6193 drm_crtc_vblank_off(crtc);
6194 assert_vblank_disabled(crtc);
6195
6196 intel_disable_pipe(intel_crtc);
6197
6198 i9xx_pfit_disable(intel_crtc);
6199
6200 for_each_encoder_on_crtc(dev, crtc, encoder)
6201 if (encoder->post_disable)
6202 encoder->post_disable(encoder);
6203
6204 if (!intel_crtc->config->has_dsi_encoder) {
6205 if (IS_CHERRYVIEW(dev))
6206 chv_disable_pll(dev_priv, pipe);
6207 else if (IS_VALLEYVIEW(dev))
6208 vlv_disable_pll(dev_priv, pipe);
6209 else
6210 i9xx_disable_pll(intel_crtc);
6211 }
6212
6213 for_each_encoder_on_crtc(dev, crtc, encoder)
6214 if (encoder->post_pll_disable)
6215 encoder->post_pll_disable(encoder);
6216
6217 if (!IS_GEN2(dev))
6218 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6219 }
6220
6221 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6222 {
6223 struct intel_encoder *encoder;
6224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6226 enum intel_display_power_domain domain;
6227 unsigned long domains;
6228
6229 if (!intel_crtc->active)
6230 return;
6231
6232 if (to_intel_plane_state(crtc->primary->state)->visible) {
6233 WARN_ON(intel_crtc->unpin_work);
6234
6235 intel_pre_disable_primary_noatomic(crtc);
6236
6237 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6238 to_intel_plane_state(crtc->primary->state)->visible = false;
6239 }
6240
6241 dev_priv->display.crtc_disable(crtc);
6242
6243 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6244 crtc->base.id);
6245
6246 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6247 crtc->state->active = false;
6248 intel_crtc->active = false;
6249 crtc->enabled = false;
6250 crtc->state->connector_mask = 0;
6251 crtc->state->encoder_mask = 0;
6252
6253 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6254 encoder->base.crtc = NULL;
6255
6256 intel_fbc_disable(intel_crtc);
6257 intel_update_watermarks(crtc);
6258 intel_disable_shared_dpll(intel_crtc);
6259
6260 domains = intel_crtc->enabled_power_domains;
6261 for_each_power_domain(domain, domains)
6262 intel_display_power_put(dev_priv, domain);
6263 intel_crtc->enabled_power_domains = 0;
6264
6265 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6266 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6267 }
6268
6269 /*
6270 * turn all crtc's off, but do not adjust state
6271 * This has to be paired with a call to intel_modeset_setup_hw_state.
6272 */
6273 int intel_display_suspend(struct drm_device *dev)
6274 {
6275 struct drm_i915_private *dev_priv = to_i915(dev);
6276 struct drm_atomic_state *state;
6277 int ret;
6278
6279 state = drm_atomic_helper_suspend(dev);
6280 ret = PTR_ERR_OR_ZERO(state);
6281 if (ret)
6282 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6283 else
6284 dev_priv->modeset_restore_state = state;
6285 return ret;
6286 }
6287
6288 void intel_encoder_destroy(struct drm_encoder *encoder)
6289 {
6290 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6291
6292 drm_encoder_cleanup(encoder);
6293 kfree(intel_encoder);
6294 }
6295
6296 /* Cross check the actual hw state with our own modeset state tracking (and it's
6297 * internal consistency). */
6298 static void intel_connector_verify_state(struct intel_connector *connector)
6299 {
6300 struct drm_crtc *crtc = connector->base.state->crtc;
6301
6302 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6303 connector->base.base.id,
6304 connector->base.name);
6305
6306 if (connector->get_hw_state(connector)) {
6307 struct intel_encoder *encoder = connector->encoder;
6308 struct drm_connector_state *conn_state = connector->base.state;
6309
6310 I915_STATE_WARN(!crtc,
6311 "connector enabled without attached crtc\n");
6312
6313 if (!crtc)
6314 return;
6315
6316 I915_STATE_WARN(!crtc->state->active,
6317 "connector is active, but attached crtc isn't\n");
6318
6319 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6320 return;
6321
6322 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6323 "atomic encoder doesn't match attached encoder\n");
6324
6325 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6326 "attached encoder crtc differs from connector crtc\n");
6327 } else {
6328 I915_STATE_WARN(crtc && crtc->state->active,
6329 "attached crtc is active, but connector isn't\n");
6330 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6331 "best encoder set without crtc!\n");
6332 }
6333 }
6334
6335 int intel_connector_init(struct intel_connector *connector)
6336 {
6337 drm_atomic_helper_connector_reset(&connector->base);
6338
6339 if (!connector->base.state)
6340 return -ENOMEM;
6341
6342 return 0;
6343 }
6344
6345 struct intel_connector *intel_connector_alloc(void)
6346 {
6347 struct intel_connector *connector;
6348
6349 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6350 if (!connector)
6351 return NULL;
6352
6353 if (intel_connector_init(connector) < 0) {
6354 kfree(connector);
6355 return NULL;
6356 }
6357
6358 return connector;
6359 }
6360
6361 /* Simple connector->get_hw_state implementation for encoders that support only
6362 * one connector and no cloning and hence the encoder state determines the state
6363 * of the connector. */
6364 bool intel_connector_get_hw_state(struct intel_connector *connector)
6365 {
6366 enum pipe pipe = 0;
6367 struct intel_encoder *encoder = connector->encoder;
6368
6369 return encoder->get_hw_state(encoder, &pipe);
6370 }
6371
6372 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6373 {
6374 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6375 return crtc_state->fdi_lanes;
6376
6377 return 0;
6378 }
6379
6380 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6381 struct intel_crtc_state *pipe_config)
6382 {
6383 struct drm_atomic_state *state = pipe_config->base.state;
6384 struct intel_crtc *other_crtc;
6385 struct intel_crtc_state *other_crtc_state;
6386
6387 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6388 pipe_name(pipe), pipe_config->fdi_lanes);
6389 if (pipe_config->fdi_lanes > 4) {
6390 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6391 pipe_name(pipe), pipe_config->fdi_lanes);
6392 return -EINVAL;
6393 }
6394
6395 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6396 if (pipe_config->fdi_lanes > 2) {
6397 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6398 pipe_config->fdi_lanes);
6399 return -EINVAL;
6400 } else {
6401 return 0;
6402 }
6403 }
6404
6405 if (INTEL_INFO(dev)->num_pipes == 2)
6406 return 0;
6407
6408 /* Ivybridge 3 pipe is really complicated */
6409 switch (pipe) {
6410 case PIPE_A:
6411 return 0;
6412 case PIPE_B:
6413 if (pipe_config->fdi_lanes <= 2)
6414 return 0;
6415
6416 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6417 other_crtc_state =
6418 intel_atomic_get_crtc_state(state, other_crtc);
6419 if (IS_ERR(other_crtc_state))
6420 return PTR_ERR(other_crtc_state);
6421
6422 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6423 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6424 pipe_name(pipe), pipe_config->fdi_lanes);
6425 return -EINVAL;
6426 }
6427 return 0;
6428 case PIPE_C:
6429 if (pipe_config->fdi_lanes > 2) {
6430 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6431 pipe_name(pipe), pipe_config->fdi_lanes);
6432 return -EINVAL;
6433 }
6434
6435 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6436 other_crtc_state =
6437 intel_atomic_get_crtc_state(state, other_crtc);
6438 if (IS_ERR(other_crtc_state))
6439 return PTR_ERR(other_crtc_state);
6440
6441 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6442 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6443 return -EINVAL;
6444 }
6445 return 0;
6446 default:
6447 BUG();
6448 }
6449 }
6450
6451 #define RETRY 1
6452 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6453 struct intel_crtc_state *pipe_config)
6454 {
6455 struct drm_device *dev = intel_crtc->base.dev;
6456 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6457 int lane, link_bw, fdi_dotclock, ret;
6458 bool needs_recompute = false;
6459
6460 retry:
6461 /* FDI is a binary signal running at ~2.7GHz, encoding
6462 * each output octet as 10 bits. The actual frequency
6463 * is stored as a divider into a 100MHz clock, and the
6464 * mode pixel clock is stored in units of 1KHz.
6465 * Hence the bw of each lane in terms of the mode signal
6466 * is:
6467 */
6468 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6469
6470 fdi_dotclock = adjusted_mode->crtc_clock;
6471
6472 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6473 pipe_config->pipe_bpp);
6474
6475 pipe_config->fdi_lanes = lane;
6476
6477 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6478 link_bw, &pipe_config->fdi_m_n);
6479
6480 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6481 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6482 pipe_config->pipe_bpp -= 2*3;
6483 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6484 pipe_config->pipe_bpp);
6485 needs_recompute = true;
6486 pipe_config->bw_constrained = true;
6487
6488 goto retry;
6489 }
6490
6491 if (needs_recompute)
6492 return RETRY;
6493
6494 return ret;
6495 }
6496
6497 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6498 struct intel_crtc_state *pipe_config)
6499 {
6500 if (pipe_config->pipe_bpp > 24)
6501 return false;
6502
6503 /* HSW can handle pixel rate up to cdclk? */
6504 if (IS_HASWELL(dev_priv))
6505 return true;
6506
6507 /*
6508 * We compare against max which means we must take
6509 * the increased cdclk requirement into account when
6510 * calculating the new cdclk.
6511 *
6512 * Should measure whether using a lower cdclk w/o IPS
6513 */
6514 return ilk_pipe_pixel_rate(pipe_config) <=
6515 dev_priv->max_cdclk_freq * 95 / 100;
6516 }
6517
6518 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6519 struct intel_crtc_state *pipe_config)
6520 {
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523
6524 pipe_config->ips_enabled = i915.enable_ips &&
6525 hsw_crtc_supports_ips(crtc) &&
6526 pipe_config_supports_ips(dev_priv, pipe_config);
6527 }
6528
6529 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6530 {
6531 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6532
6533 /* GDG double wide on either pipe, otherwise pipe A only */
6534 return INTEL_INFO(dev_priv)->gen < 4 &&
6535 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6536 }
6537
6538 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6539 struct intel_crtc_state *pipe_config)
6540 {
6541 struct drm_device *dev = crtc->base.dev;
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6544
6545 /* FIXME should check pixel clock limits on all platforms */
6546 if (INTEL_INFO(dev)->gen < 4) {
6547 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6548
6549 /*
6550 * Enable double wide mode when the dot clock
6551 * is > 90% of the (display) core speed.
6552 */
6553 if (intel_crtc_supports_double_wide(crtc) &&
6554 adjusted_mode->crtc_clock > clock_limit) {
6555 clock_limit *= 2;
6556 pipe_config->double_wide = true;
6557 }
6558
6559 if (adjusted_mode->crtc_clock > clock_limit) {
6560 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6561 adjusted_mode->crtc_clock, clock_limit,
6562 yesno(pipe_config->double_wide));
6563 return -EINVAL;
6564 }
6565 }
6566
6567 /*
6568 * Pipe horizontal size must be even in:
6569 * - DVO ganged mode
6570 * - LVDS dual channel mode
6571 * - Double wide pipe
6572 */
6573 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6574 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6575 pipe_config->pipe_src_w &= ~1;
6576
6577 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6578 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6579 */
6580 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6581 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6582 return -EINVAL;
6583
6584 if (HAS_IPS(dev))
6585 hsw_compute_ips_config(crtc, pipe_config);
6586
6587 if (pipe_config->has_pch_encoder)
6588 return ironlake_fdi_compute_config(crtc, pipe_config);
6589
6590 return 0;
6591 }
6592
6593 static int skylake_get_display_clock_speed(struct drm_device *dev)
6594 {
6595 struct drm_i915_private *dev_priv = to_i915(dev);
6596 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6597 uint32_t cdctl = I915_READ(CDCLK_CTL);
6598 uint32_t linkrate;
6599
6600 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6601 return 24000; /* 24MHz is the cd freq with NSSC ref */
6602
6603 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6604 return 540000;
6605
6606 linkrate = (I915_READ(DPLL_CTRL1) &
6607 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6608
6609 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6610 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6611 /* vco 8640 */
6612 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6613 case CDCLK_FREQ_450_432:
6614 return 432000;
6615 case CDCLK_FREQ_337_308:
6616 return 308570;
6617 case CDCLK_FREQ_675_617:
6618 return 617140;
6619 default:
6620 WARN(1, "Unknown cd freq selection\n");
6621 }
6622 } else {
6623 /* vco 8100 */
6624 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6625 case CDCLK_FREQ_450_432:
6626 return 450000;
6627 case CDCLK_FREQ_337_308:
6628 return 337500;
6629 case CDCLK_FREQ_675_617:
6630 return 675000;
6631 default:
6632 WARN(1, "Unknown cd freq selection\n");
6633 }
6634 }
6635
6636 /* error case, do as if DPLL0 isn't enabled */
6637 return 24000;
6638 }
6639
6640 static int broxton_get_display_clock_speed(struct drm_device *dev)
6641 {
6642 struct drm_i915_private *dev_priv = to_i915(dev);
6643 uint32_t cdctl = I915_READ(CDCLK_CTL);
6644 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6645 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6646 int cdclk;
6647
6648 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6649 return 19200;
6650
6651 cdclk = 19200 * pll_ratio / 2;
6652
6653 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6654 case BXT_CDCLK_CD2X_DIV_SEL_1:
6655 return cdclk; /* 576MHz or 624MHz */
6656 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6657 return cdclk * 2 / 3; /* 384MHz */
6658 case BXT_CDCLK_CD2X_DIV_SEL_2:
6659 return cdclk / 2; /* 288MHz */
6660 case BXT_CDCLK_CD2X_DIV_SEL_4:
6661 return cdclk / 4; /* 144MHz */
6662 }
6663
6664 /* error case, do as if DE PLL isn't enabled */
6665 return 19200;
6666 }
6667
6668 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6669 {
6670 struct drm_i915_private *dev_priv = dev->dev_private;
6671 uint32_t lcpll = I915_READ(LCPLL_CTL);
6672 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6673
6674 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6675 return 800000;
6676 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6677 return 450000;
6678 else if (freq == LCPLL_CLK_FREQ_450)
6679 return 450000;
6680 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6681 return 540000;
6682 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6683 return 337500;
6684 else
6685 return 675000;
6686 }
6687
6688 static int haswell_get_display_clock_speed(struct drm_device *dev)
6689 {
6690 struct drm_i915_private *dev_priv = dev->dev_private;
6691 uint32_t lcpll = I915_READ(LCPLL_CTL);
6692 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6693
6694 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6695 return 800000;
6696 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6697 return 450000;
6698 else if (freq == LCPLL_CLK_FREQ_450)
6699 return 450000;
6700 else if (IS_HSW_ULT(dev))
6701 return 337500;
6702 else
6703 return 540000;
6704 }
6705
6706 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6707 {
6708 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6709 CCK_DISPLAY_CLOCK_CONTROL);
6710 }
6711
6712 static int ilk_get_display_clock_speed(struct drm_device *dev)
6713 {
6714 return 450000;
6715 }
6716
6717 static int i945_get_display_clock_speed(struct drm_device *dev)
6718 {
6719 return 400000;
6720 }
6721
6722 static int i915_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 return 333333;
6725 }
6726
6727 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6728 {
6729 return 200000;
6730 }
6731
6732 static int pnv_get_display_clock_speed(struct drm_device *dev)
6733 {
6734 u16 gcfgc = 0;
6735
6736 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6737
6738 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6739 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6740 return 266667;
6741 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6742 return 333333;
6743 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6744 return 444444;
6745 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6746 return 200000;
6747 default:
6748 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6749 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6750 return 133333;
6751 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6752 return 166667;
6753 }
6754 }
6755
6756 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6757 {
6758 u16 gcfgc = 0;
6759
6760 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6761
6762 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6763 return 133333;
6764 else {
6765 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6766 case GC_DISPLAY_CLOCK_333_MHZ:
6767 return 333333;
6768 default:
6769 case GC_DISPLAY_CLOCK_190_200_MHZ:
6770 return 190000;
6771 }
6772 }
6773 }
6774
6775 static int i865_get_display_clock_speed(struct drm_device *dev)
6776 {
6777 return 266667;
6778 }
6779
6780 static int i85x_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 u16 hpllcc = 0;
6783
6784 /*
6785 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6786 * encoding is different :(
6787 * FIXME is this the right way to detect 852GM/852GMV?
6788 */
6789 if (dev->pdev->revision == 0x1)
6790 return 133333;
6791
6792 pci_bus_read_config_word(dev->pdev->bus,
6793 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6794
6795 /* Assume that the hardware is in the high speed state. This
6796 * should be the default.
6797 */
6798 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6799 case GC_CLOCK_133_200:
6800 case GC_CLOCK_133_200_2:
6801 case GC_CLOCK_100_200:
6802 return 200000;
6803 case GC_CLOCK_166_250:
6804 return 250000;
6805 case GC_CLOCK_100_133:
6806 return 133333;
6807 case GC_CLOCK_133_266:
6808 case GC_CLOCK_133_266_2:
6809 case GC_CLOCK_166_266:
6810 return 266667;
6811 }
6812
6813 /* Shouldn't happen */
6814 return 0;
6815 }
6816
6817 static int i830_get_display_clock_speed(struct drm_device *dev)
6818 {
6819 return 133333;
6820 }
6821
6822 static unsigned int intel_hpll_vco(struct drm_device *dev)
6823 {
6824 struct drm_i915_private *dev_priv = dev->dev_private;
6825 static const unsigned int blb_vco[8] = {
6826 [0] = 3200000,
6827 [1] = 4000000,
6828 [2] = 5333333,
6829 [3] = 4800000,
6830 [4] = 6400000,
6831 };
6832 static const unsigned int pnv_vco[8] = {
6833 [0] = 3200000,
6834 [1] = 4000000,
6835 [2] = 5333333,
6836 [3] = 4800000,
6837 [4] = 2666667,
6838 };
6839 static const unsigned int cl_vco[8] = {
6840 [0] = 3200000,
6841 [1] = 4000000,
6842 [2] = 5333333,
6843 [3] = 6400000,
6844 [4] = 3333333,
6845 [5] = 3566667,
6846 [6] = 4266667,
6847 };
6848 static const unsigned int elk_vco[8] = {
6849 [0] = 3200000,
6850 [1] = 4000000,
6851 [2] = 5333333,
6852 [3] = 4800000,
6853 };
6854 static const unsigned int ctg_vco[8] = {
6855 [0] = 3200000,
6856 [1] = 4000000,
6857 [2] = 5333333,
6858 [3] = 6400000,
6859 [4] = 2666667,
6860 [5] = 4266667,
6861 };
6862 const unsigned int *vco_table;
6863 unsigned int vco;
6864 uint8_t tmp = 0;
6865
6866 /* FIXME other chipsets? */
6867 if (IS_GM45(dev))
6868 vco_table = ctg_vco;
6869 else if (IS_G4X(dev))
6870 vco_table = elk_vco;
6871 else if (IS_CRESTLINE(dev))
6872 vco_table = cl_vco;
6873 else if (IS_PINEVIEW(dev))
6874 vco_table = pnv_vco;
6875 else if (IS_G33(dev))
6876 vco_table = blb_vco;
6877 else
6878 return 0;
6879
6880 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6881
6882 vco = vco_table[tmp & 0x7];
6883 if (vco == 0)
6884 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6885 else
6886 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6887
6888 return vco;
6889 }
6890
6891 static int gm45_get_display_clock_speed(struct drm_device *dev)
6892 {
6893 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6894 uint16_t tmp = 0;
6895
6896 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6897
6898 cdclk_sel = (tmp >> 12) & 0x1;
6899
6900 switch (vco) {
6901 case 2666667:
6902 case 4000000:
6903 case 5333333:
6904 return cdclk_sel ? 333333 : 222222;
6905 case 3200000:
6906 return cdclk_sel ? 320000 : 228571;
6907 default:
6908 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6909 return 222222;
6910 }
6911 }
6912
6913 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6914 {
6915 static const uint8_t div_3200[] = { 16, 10, 8 };
6916 static const uint8_t div_4000[] = { 20, 12, 10 };
6917 static const uint8_t div_5333[] = { 24, 16, 14 };
6918 const uint8_t *div_table;
6919 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6920 uint16_t tmp = 0;
6921
6922 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6923
6924 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6925
6926 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6927 goto fail;
6928
6929 switch (vco) {
6930 case 3200000:
6931 div_table = div_3200;
6932 break;
6933 case 4000000:
6934 div_table = div_4000;
6935 break;
6936 case 5333333:
6937 div_table = div_5333;
6938 break;
6939 default:
6940 goto fail;
6941 }
6942
6943 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6944
6945 fail:
6946 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6947 return 200000;
6948 }
6949
6950 static int g33_get_display_clock_speed(struct drm_device *dev)
6951 {
6952 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6953 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6954 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6955 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6956 const uint8_t *div_table;
6957 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6958 uint16_t tmp = 0;
6959
6960 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6961
6962 cdclk_sel = (tmp >> 4) & 0x7;
6963
6964 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6965 goto fail;
6966
6967 switch (vco) {
6968 case 3200000:
6969 div_table = div_3200;
6970 break;
6971 case 4000000:
6972 div_table = div_4000;
6973 break;
6974 case 4800000:
6975 div_table = div_4800;
6976 break;
6977 case 5333333:
6978 div_table = div_5333;
6979 break;
6980 default:
6981 goto fail;
6982 }
6983
6984 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6985
6986 fail:
6987 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6988 return 190476;
6989 }
6990
6991 static void
6992 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6993 {
6994 while (*num > DATA_LINK_M_N_MASK ||
6995 *den > DATA_LINK_M_N_MASK) {
6996 *num >>= 1;
6997 *den >>= 1;
6998 }
6999 }
7000
7001 static void compute_m_n(unsigned int m, unsigned int n,
7002 uint32_t *ret_m, uint32_t *ret_n)
7003 {
7004 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7005 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7006 intel_reduce_m_n_ratio(ret_m, ret_n);
7007 }
7008
7009 void
7010 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7011 int pixel_clock, int link_clock,
7012 struct intel_link_m_n *m_n)
7013 {
7014 m_n->tu = 64;
7015
7016 compute_m_n(bits_per_pixel * pixel_clock,
7017 link_clock * nlanes * 8,
7018 &m_n->gmch_m, &m_n->gmch_n);
7019
7020 compute_m_n(pixel_clock, link_clock,
7021 &m_n->link_m, &m_n->link_n);
7022 }
7023
7024 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7025 {
7026 if (i915.panel_use_ssc >= 0)
7027 return i915.panel_use_ssc != 0;
7028 return dev_priv->vbt.lvds_use_ssc
7029 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7030 }
7031
7032 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7033 {
7034 return (1 << dpll->n) << 16 | dpll->m2;
7035 }
7036
7037 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7038 {
7039 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7040 }
7041
7042 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7043 struct intel_crtc_state *crtc_state,
7044 intel_clock_t *reduced_clock)
7045 {
7046 struct drm_device *dev = crtc->base.dev;
7047 u32 fp, fp2 = 0;
7048
7049 if (IS_PINEVIEW(dev)) {
7050 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7051 if (reduced_clock)
7052 fp2 = pnv_dpll_compute_fp(reduced_clock);
7053 } else {
7054 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7055 if (reduced_clock)
7056 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7057 }
7058
7059 crtc_state->dpll_hw_state.fp0 = fp;
7060
7061 crtc->lowfreq_avail = false;
7062 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7063 reduced_clock) {
7064 crtc_state->dpll_hw_state.fp1 = fp2;
7065 crtc->lowfreq_avail = true;
7066 } else {
7067 crtc_state->dpll_hw_state.fp1 = fp;
7068 }
7069 }
7070
7071 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7072 pipe)
7073 {
7074 u32 reg_val;
7075
7076 /*
7077 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7078 * and set it to a reasonable value instead.
7079 */
7080 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7081 reg_val &= 0xffffff00;
7082 reg_val |= 0x00000030;
7083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7084
7085 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7086 reg_val &= 0x8cffffff;
7087 reg_val = 0x8c000000;
7088 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7089
7090 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7091 reg_val &= 0xffffff00;
7092 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7093
7094 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7095 reg_val &= 0x00ffffff;
7096 reg_val |= 0xb0000000;
7097 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7098 }
7099
7100 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7101 struct intel_link_m_n *m_n)
7102 {
7103 struct drm_device *dev = crtc->base.dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 int pipe = crtc->pipe;
7106
7107 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7108 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7109 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7110 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7111 }
7112
7113 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7114 struct intel_link_m_n *m_n,
7115 struct intel_link_m_n *m2_n2)
7116 {
7117 struct drm_device *dev = crtc->base.dev;
7118 struct drm_i915_private *dev_priv = dev->dev_private;
7119 int pipe = crtc->pipe;
7120 enum transcoder transcoder = crtc->config->cpu_transcoder;
7121
7122 if (INTEL_INFO(dev)->gen >= 5) {
7123 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7124 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7125 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7126 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7127 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7128 * for gen < 8) and if DRRS is supported (to make sure the
7129 * registers are not unnecessarily accessed).
7130 */
7131 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7132 crtc->config->has_drrs) {
7133 I915_WRITE(PIPE_DATA_M2(transcoder),
7134 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7135 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7136 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7137 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7138 }
7139 } else {
7140 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7141 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7142 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7143 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7144 }
7145 }
7146
7147 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7148 {
7149 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7150
7151 if (m_n == M1_N1) {
7152 dp_m_n = &crtc->config->dp_m_n;
7153 dp_m2_n2 = &crtc->config->dp_m2_n2;
7154 } else if (m_n == M2_N2) {
7155
7156 /*
7157 * M2_N2 registers are not supported. Hence m2_n2 divider value
7158 * needs to be programmed into M1_N1.
7159 */
7160 dp_m_n = &crtc->config->dp_m2_n2;
7161 } else {
7162 DRM_ERROR("Unsupported divider value\n");
7163 return;
7164 }
7165
7166 if (crtc->config->has_pch_encoder)
7167 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7168 else
7169 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7170 }
7171
7172 static void vlv_compute_dpll(struct intel_crtc *crtc,
7173 struct intel_crtc_state *pipe_config)
7174 {
7175 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7176 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7177 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7178 if (crtc->pipe != PIPE_A)
7179 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7180
7181 pipe_config->dpll_hw_state.dpll_md =
7182 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7183 }
7184
7185 static void chv_compute_dpll(struct intel_crtc *crtc,
7186 struct intel_crtc_state *pipe_config)
7187 {
7188 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7189 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7190 DPLL_VCO_ENABLE;
7191 if (crtc->pipe != PIPE_A)
7192 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7193
7194 pipe_config->dpll_hw_state.dpll_md =
7195 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7196 }
7197
7198 static void vlv_prepare_pll(struct intel_crtc *crtc,
7199 const struct intel_crtc_state *pipe_config)
7200 {
7201 struct drm_device *dev = crtc->base.dev;
7202 struct drm_i915_private *dev_priv = dev->dev_private;
7203 int pipe = crtc->pipe;
7204 u32 mdiv;
7205 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7206 u32 coreclk, reg_val;
7207
7208 mutex_lock(&dev_priv->sb_lock);
7209
7210 bestn = pipe_config->dpll.n;
7211 bestm1 = pipe_config->dpll.m1;
7212 bestm2 = pipe_config->dpll.m2;
7213 bestp1 = pipe_config->dpll.p1;
7214 bestp2 = pipe_config->dpll.p2;
7215
7216 /* See eDP HDMI DPIO driver vbios notes doc */
7217
7218 /* PLL B needs special handling */
7219 if (pipe == PIPE_B)
7220 vlv_pllb_recal_opamp(dev_priv, pipe);
7221
7222 /* Set up Tx target for periodic Rcomp update */
7223 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7224
7225 /* Disable target IRef on PLL */
7226 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7227 reg_val &= 0x00ffffff;
7228 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7229
7230 /* Disable fast lock */
7231 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7232
7233 /* Set idtafcrecal before PLL is enabled */
7234 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7235 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7236 mdiv |= ((bestn << DPIO_N_SHIFT));
7237 mdiv |= (1 << DPIO_K_SHIFT);
7238
7239 /*
7240 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7241 * but we don't support that).
7242 * Note: don't use the DAC post divider as it seems unstable.
7243 */
7244 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7245 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7246
7247 mdiv |= DPIO_ENABLE_CALIBRATION;
7248 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7249
7250 /* Set HBR and RBR LPF coefficients */
7251 if (pipe_config->port_clock == 162000 ||
7252 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7253 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7255 0x009f0003);
7256 else
7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7258 0x00d0000f);
7259
7260 if (pipe_config->has_dp_encoder) {
7261 /* Use SSC source */
7262 if (pipe == PIPE_A)
7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7264 0x0df40000);
7265 else
7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7267 0x0df70000);
7268 } else { /* HDMI or VGA */
7269 /* Use bend source */
7270 if (pipe == PIPE_A)
7271 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7272 0x0df70000);
7273 else
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7275 0x0df40000);
7276 }
7277
7278 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7279 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7282 coreclk |= 0x01000000;
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7284
7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7286 mutex_unlock(&dev_priv->sb_lock);
7287 }
7288
7289 static void chv_prepare_pll(struct intel_crtc *crtc,
7290 const struct intel_crtc_state *pipe_config)
7291 {
7292 struct drm_device *dev = crtc->base.dev;
7293 struct drm_i915_private *dev_priv = dev->dev_private;
7294 int pipe = crtc->pipe;
7295 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7296 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7297 u32 loopfilter, tribuf_calcntr;
7298 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7299 u32 dpio_val;
7300 int vco;
7301
7302 bestn = pipe_config->dpll.n;
7303 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7304 bestm1 = pipe_config->dpll.m1;
7305 bestm2 = pipe_config->dpll.m2 >> 22;
7306 bestp1 = pipe_config->dpll.p1;
7307 bestp2 = pipe_config->dpll.p2;
7308 vco = pipe_config->dpll.vco;
7309 dpio_val = 0;
7310 loopfilter = 0;
7311
7312 /*
7313 * Enable Refclk and SSC
7314 */
7315 I915_WRITE(dpll_reg,
7316 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7317
7318 mutex_lock(&dev_priv->sb_lock);
7319
7320 /* p1 and p2 divider */
7321 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7322 5 << DPIO_CHV_S1_DIV_SHIFT |
7323 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7324 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7325 1 << DPIO_CHV_K_DIV_SHIFT);
7326
7327 /* Feedback post-divider - m2 */
7328 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7329
7330 /* Feedback refclk divider - n and m1 */
7331 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7332 DPIO_CHV_M1_DIV_BY_2 |
7333 1 << DPIO_CHV_N_DIV_SHIFT);
7334
7335 /* M2 fraction division */
7336 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7337
7338 /* M2 fraction division enable */
7339 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7340 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7341 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7342 if (bestm2_frac)
7343 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7344 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7345
7346 /* Program digital lock detect threshold */
7347 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7348 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7349 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7350 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7351 if (!bestm2_frac)
7352 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7353 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7354
7355 /* Loop filter */
7356 if (vco == 5400000) {
7357 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7358 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7359 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7360 tribuf_calcntr = 0x9;
7361 } else if (vco <= 6200000) {
7362 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7363 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7364 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7365 tribuf_calcntr = 0x9;
7366 } else if (vco <= 6480000) {
7367 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7368 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7369 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7370 tribuf_calcntr = 0x8;
7371 } else {
7372 /* Not supported. Apply the same limits as in the max case */
7373 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7374 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7375 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7376 tribuf_calcntr = 0;
7377 }
7378 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7379
7380 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7381 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7382 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7384
7385 /* AFC Recal */
7386 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7387 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7388 DPIO_AFC_RECAL);
7389
7390 mutex_unlock(&dev_priv->sb_lock);
7391 }
7392
7393 /**
7394 * vlv_force_pll_on - forcibly enable just the PLL
7395 * @dev_priv: i915 private structure
7396 * @pipe: pipe PLL to enable
7397 * @dpll: PLL configuration
7398 *
7399 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7400 * in cases where we need the PLL enabled even when @pipe is not going to
7401 * be enabled.
7402 */
7403 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7404 const struct dpll *dpll)
7405 {
7406 struct intel_crtc *crtc =
7407 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7408 struct intel_crtc_state *pipe_config;
7409
7410 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7411 if (!pipe_config)
7412 return -ENOMEM;
7413
7414 pipe_config->base.crtc = &crtc->base;
7415 pipe_config->pixel_multiplier = 1;
7416 pipe_config->dpll = *dpll;
7417
7418 if (IS_CHERRYVIEW(dev)) {
7419 chv_compute_dpll(crtc, pipe_config);
7420 chv_prepare_pll(crtc, pipe_config);
7421 chv_enable_pll(crtc, pipe_config);
7422 } else {
7423 vlv_compute_dpll(crtc, pipe_config);
7424 vlv_prepare_pll(crtc, pipe_config);
7425 vlv_enable_pll(crtc, pipe_config);
7426 }
7427
7428 kfree(pipe_config);
7429
7430 return 0;
7431 }
7432
7433 /**
7434 * vlv_force_pll_off - forcibly disable just the PLL
7435 * @dev_priv: i915 private structure
7436 * @pipe: pipe PLL to disable
7437 *
7438 * Disable the PLL for @pipe. To be used in cases where we need
7439 * the PLL enabled even when @pipe is not going to be enabled.
7440 */
7441 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7442 {
7443 if (IS_CHERRYVIEW(dev))
7444 chv_disable_pll(to_i915(dev), pipe);
7445 else
7446 vlv_disable_pll(to_i915(dev), pipe);
7447 }
7448
7449 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7450 struct intel_crtc_state *crtc_state,
7451 intel_clock_t *reduced_clock)
7452 {
7453 struct drm_device *dev = crtc->base.dev;
7454 struct drm_i915_private *dev_priv = dev->dev_private;
7455 u32 dpll;
7456 bool is_sdvo;
7457 struct dpll *clock = &crtc_state->dpll;
7458
7459 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7460
7461 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7462 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7463
7464 dpll = DPLL_VGA_MODE_DIS;
7465
7466 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7467 dpll |= DPLLB_MODE_LVDS;
7468 else
7469 dpll |= DPLLB_MODE_DAC_SERIAL;
7470
7471 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7472 dpll |= (crtc_state->pixel_multiplier - 1)
7473 << SDVO_MULTIPLIER_SHIFT_HIRES;
7474 }
7475
7476 if (is_sdvo)
7477 dpll |= DPLL_SDVO_HIGH_SPEED;
7478
7479 if (crtc_state->has_dp_encoder)
7480 dpll |= DPLL_SDVO_HIGH_SPEED;
7481
7482 /* compute bitmask from p1 value */
7483 if (IS_PINEVIEW(dev))
7484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7485 else {
7486 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7487 if (IS_G4X(dev) && reduced_clock)
7488 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7489 }
7490 switch (clock->p2) {
7491 case 5:
7492 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7493 break;
7494 case 7:
7495 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7496 break;
7497 case 10:
7498 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7499 break;
7500 case 14:
7501 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7502 break;
7503 }
7504 if (INTEL_INFO(dev)->gen >= 4)
7505 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7506
7507 if (crtc_state->sdvo_tv_clock)
7508 dpll |= PLL_REF_INPUT_TVCLKINBC;
7509 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7510 intel_panel_use_ssc(dev_priv))
7511 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7512 else
7513 dpll |= PLL_REF_INPUT_DREFCLK;
7514
7515 dpll |= DPLL_VCO_ENABLE;
7516 crtc_state->dpll_hw_state.dpll = dpll;
7517
7518 if (INTEL_INFO(dev)->gen >= 4) {
7519 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7520 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7521 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7522 }
7523 }
7524
7525 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7526 struct intel_crtc_state *crtc_state,
7527 intel_clock_t *reduced_clock)
7528 {
7529 struct drm_device *dev = crtc->base.dev;
7530 struct drm_i915_private *dev_priv = dev->dev_private;
7531 u32 dpll;
7532 struct dpll *clock = &crtc_state->dpll;
7533
7534 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7535
7536 dpll = DPLL_VGA_MODE_DIS;
7537
7538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7539 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7540 } else {
7541 if (clock->p1 == 2)
7542 dpll |= PLL_P1_DIVIDE_BY_TWO;
7543 else
7544 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7545 if (clock->p2 == 4)
7546 dpll |= PLL_P2_DIVIDE_BY_4;
7547 }
7548
7549 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7550 dpll |= DPLL_DVO_2X_MODE;
7551
7552 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7553 intel_panel_use_ssc(dev_priv))
7554 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7555 else
7556 dpll |= PLL_REF_INPUT_DREFCLK;
7557
7558 dpll |= DPLL_VCO_ENABLE;
7559 crtc_state->dpll_hw_state.dpll = dpll;
7560 }
7561
7562 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7563 {
7564 struct drm_device *dev = intel_crtc->base.dev;
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7566 enum pipe pipe = intel_crtc->pipe;
7567 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7568 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7569 uint32_t crtc_vtotal, crtc_vblank_end;
7570 int vsyncshift = 0;
7571
7572 /* We need to be careful not to changed the adjusted mode, for otherwise
7573 * the hw state checker will get angry at the mismatch. */
7574 crtc_vtotal = adjusted_mode->crtc_vtotal;
7575 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7576
7577 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7578 /* the chip adds 2 halflines automatically */
7579 crtc_vtotal -= 1;
7580 crtc_vblank_end -= 1;
7581
7582 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7583 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7584 else
7585 vsyncshift = adjusted_mode->crtc_hsync_start -
7586 adjusted_mode->crtc_htotal / 2;
7587 if (vsyncshift < 0)
7588 vsyncshift += adjusted_mode->crtc_htotal;
7589 }
7590
7591 if (INTEL_INFO(dev)->gen > 3)
7592 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7593
7594 I915_WRITE(HTOTAL(cpu_transcoder),
7595 (adjusted_mode->crtc_hdisplay - 1) |
7596 ((adjusted_mode->crtc_htotal - 1) << 16));
7597 I915_WRITE(HBLANK(cpu_transcoder),
7598 (adjusted_mode->crtc_hblank_start - 1) |
7599 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7600 I915_WRITE(HSYNC(cpu_transcoder),
7601 (adjusted_mode->crtc_hsync_start - 1) |
7602 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7603
7604 I915_WRITE(VTOTAL(cpu_transcoder),
7605 (adjusted_mode->crtc_vdisplay - 1) |
7606 ((crtc_vtotal - 1) << 16));
7607 I915_WRITE(VBLANK(cpu_transcoder),
7608 (adjusted_mode->crtc_vblank_start - 1) |
7609 ((crtc_vblank_end - 1) << 16));
7610 I915_WRITE(VSYNC(cpu_transcoder),
7611 (adjusted_mode->crtc_vsync_start - 1) |
7612 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7613
7614 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7615 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7616 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7617 * bits. */
7618 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7619 (pipe == PIPE_B || pipe == PIPE_C))
7620 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7621
7622 }
7623
7624 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7625 {
7626 struct drm_device *dev = intel_crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 enum pipe pipe = intel_crtc->pipe;
7629
7630 /* pipesrc controls the size that is scaled from, which should
7631 * always be the user's requested size.
7632 */
7633 I915_WRITE(PIPESRC(pipe),
7634 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7635 (intel_crtc->config->pipe_src_h - 1));
7636 }
7637
7638 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7639 struct intel_crtc_state *pipe_config)
7640 {
7641 struct drm_device *dev = crtc->base.dev;
7642 struct drm_i915_private *dev_priv = dev->dev_private;
7643 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7644 uint32_t tmp;
7645
7646 tmp = I915_READ(HTOTAL(cpu_transcoder));
7647 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7648 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7649 tmp = I915_READ(HBLANK(cpu_transcoder));
7650 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7651 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7652 tmp = I915_READ(HSYNC(cpu_transcoder));
7653 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7654 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7655
7656 tmp = I915_READ(VTOTAL(cpu_transcoder));
7657 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7658 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7659 tmp = I915_READ(VBLANK(cpu_transcoder));
7660 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7661 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7662 tmp = I915_READ(VSYNC(cpu_transcoder));
7663 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7664 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7665
7666 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7667 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7668 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7669 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7670 }
7671 }
7672
7673 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7674 struct intel_crtc_state *pipe_config)
7675 {
7676 struct drm_device *dev = crtc->base.dev;
7677 struct drm_i915_private *dev_priv = dev->dev_private;
7678 u32 tmp;
7679
7680 tmp = I915_READ(PIPESRC(crtc->pipe));
7681 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7682 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7683
7684 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7685 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7686 }
7687
7688 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7689 struct intel_crtc_state *pipe_config)
7690 {
7691 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7692 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7693 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7694 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7695
7696 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7697 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7698 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7699 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7700
7701 mode->flags = pipe_config->base.adjusted_mode.flags;
7702 mode->type = DRM_MODE_TYPE_DRIVER;
7703
7704 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7705 mode->flags |= pipe_config->base.adjusted_mode.flags;
7706
7707 mode->hsync = drm_mode_hsync(mode);
7708 mode->vrefresh = drm_mode_vrefresh(mode);
7709 drm_mode_set_name(mode);
7710 }
7711
7712 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7713 {
7714 struct drm_device *dev = intel_crtc->base.dev;
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716 uint32_t pipeconf;
7717
7718 pipeconf = 0;
7719
7720 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7721 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7722 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7723
7724 if (intel_crtc->config->double_wide)
7725 pipeconf |= PIPECONF_DOUBLE_WIDE;
7726
7727 /* only g4x and later have fancy bpc/dither controls */
7728 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7729 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7730 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7731 pipeconf |= PIPECONF_DITHER_EN |
7732 PIPECONF_DITHER_TYPE_SP;
7733
7734 switch (intel_crtc->config->pipe_bpp) {
7735 case 18:
7736 pipeconf |= PIPECONF_6BPC;
7737 break;
7738 case 24:
7739 pipeconf |= PIPECONF_8BPC;
7740 break;
7741 case 30:
7742 pipeconf |= PIPECONF_10BPC;
7743 break;
7744 default:
7745 /* Case prevented by intel_choose_pipe_bpp_dither. */
7746 BUG();
7747 }
7748 }
7749
7750 if (HAS_PIPE_CXSR(dev)) {
7751 if (intel_crtc->lowfreq_avail) {
7752 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7753 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7754 } else {
7755 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7756 }
7757 }
7758
7759 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7760 if (INTEL_INFO(dev)->gen < 4 ||
7761 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7762 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7763 else
7764 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7765 } else
7766 pipeconf |= PIPECONF_PROGRESSIVE;
7767
7768 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7769 intel_crtc->config->limited_color_range)
7770 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7771
7772 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7773 POSTING_READ(PIPECONF(intel_crtc->pipe));
7774 }
7775
7776 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7777 struct intel_crtc_state *crtc_state)
7778 {
7779 struct drm_device *dev = crtc->base.dev;
7780 struct drm_i915_private *dev_priv = dev->dev_private;
7781 const intel_limit_t *limit;
7782 int refclk = 48000;
7783
7784 memset(&crtc_state->dpll_hw_state, 0,
7785 sizeof(crtc_state->dpll_hw_state));
7786
7787 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7788 if (intel_panel_use_ssc(dev_priv)) {
7789 refclk = dev_priv->vbt.lvds_ssc_freq;
7790 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7791 }
7792
7793 limit = &intel_limits_i8xx_lvds;
7794 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7795 limit = &intel_limits_i8xx_dvo;
7796 } else {
7797 limit = &intel_limits_i8xx_dac;
7798 }
7799
7800 if (!crtc_state->clock_set &&
7801 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7802 refclk, NULL, &crtc_state->dpll)) {
7803 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7804 return -EINVAL;
7805 }
7806
7807 i8xx_compute_dpll(crtc, crtc_state, NULL);
7808
7809 return 0;
7810 }
7811
7812 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7813 struct intel_crtc_state *crtc_state)
7814 {
7815 struct drm_device *dev = crtc->base.dev;
7816 struct drm_i915_private *dev_priv = dev->dev_private;
7817 const intel_limit_t *limit;
7818 int refclk = 96000;
7819
7820 memset(&crtc_state->dpll_hw_state, 0,
7821 sizeof(crtc_state->dpll_hw_state));
7822
7823 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7824 if (intel_panel_use_ssc(dev_priv)) {
7825 refclk = dev_priv->vbt.lvds_ssc_freq;
7826 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7827 }
7828
7829 if (intel_is_dual_link_lvds(dev))
7830 limit = &intel_limits_g4x_dual_channel_lvds;
7831 else
7832 limit = &intel_limits_g4x_single_channel_lvds;
7833 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7834 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7835 limit = &intel_limits_g4x_hdmi;
7836 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7837 limit = &intel_limits_g4x_sdvo;
7838 } else {
7839 /* The option is for other outputs */
7840 limit = &intel_limits_i9xx_sdvo;
7841 }
7842
7843 if (!crtc_state->clock_set &&
7844 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7845 refclk, NULL, &crtc_state->dpll)) {
7846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7847 return -EINVAL;
7848 }
7849
7850 i9xx_compute_dpll(crtc, crtc_state, NULL);
7851
7852 return 0;
7853 }
7854
7855 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7856 struct intel_crtc_state *crtc_state)
7857 {
7858 struct drm_device *dev = crtc->base.dev;
7859 struct drm_i915_private *dev_priv = dev->dev_private;
7860 const intel_limit_t *limit;
7861 int refclk = 96000;
7862
7863 memset(&crtc_state->dpll_hw_state, 0,
7864 sizeof(crtc_state->dpll_hw_state));
7865
7866 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7867 if (intel_panel_use_ssc(dev_priv)) {
7868 refclk = dev_priv->vbt.lvds_ssc_freq;
7869 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7870 }
7871
7872 limit = &intel_limits_pineview_lvds;
7873 } else {
7874 limit = &intel_limits_pineview_sdvo;
7875 }
7876
7877 if (!crtc_state->clock_set &&
7878 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7879 refclk, NULL, &crtc_state->dpll)) {
7880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7881 return -EINVAL;
7882 }
7883
7884 i9xx_compute_dpll(crtc, crtc_state, NULL);
7885
7886 return 0;
7887 }
7888
7889 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7890 struct intel_crtc_state *crtc_state)
7891 {
7892 struct drm_device *dev = crtc->base.dev;
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894 const intel_limit_t *limit;
7895 int refclk = 96000;
7896
7897 memset(&crtc_state->dpll_hw_state, 0,
7898 sizeof(crtc_state->dpll_hw_state));
7899
7900 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7901 if (intel_panel_use_ssc(dev_priv)) {
7902 refclk = dev_priv->vbt.lvds_ssc_freq;
7903 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7904 }
7905
7906 limit = &intel_limits_i9xx_lvds;
7907 } else {
7908 limit = &intel_limits_i9xx_sdvo;
7909 }
7910
7911 if (!crtc_state->clock_set &&
7912 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7913 refclk, NULL, &crtc_state->dpll)) {
7914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7915 return -EINVAL;
7916 }
7917
7918 i9xx_compute_dpll(crtc, crtc_state, NULL);
7919
7920 return 0;
7921 }
7922
7923 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7924 struct intel_crtc_state *crtc_state)
7925 {
7926 int refclk = 100000;
7927 const intel_limit_t *limit = &intel_limits_chv;
7928
7929 memset(&crtc_state->dpll_hw_state, 0,
7930 sizeof(crtc_state->dpll_hw_state));
7931
7932 if (crtc_state->has_dsi_encoder)
7933 return 0;
7934
7935 if (!crtc_state->clock_set &&
7936 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7937 refclk, NULL, &crtc_state->dpll)) {
7938 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939 return -EINVAL;
7940 }
7941
7942 chv_compute_dpll(crtc, crtc_state);
7943
7944 return 0;
7945 }
7946
7947 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7948 struct intel_crtc_state *crtc_state)
7949 {
7950 int refclk = 100000;
7951 const intel_limit_t *limit = &intel_limits_vlv;
7952
7953 memset(&crtc_state->dpll_hw_state, 0,
7954 sizeof(crtc_state->dpll_hw_state));
7955
7956 if (crtc_state->has_dsi_encoder)
7957 return 0;
7958
7959 if (!crtc_state->clock_set &&
7960 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7961 refclk, NULL, &crtc_state->dpll)) {
7962 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7963 return -EINVAL;
7964 }
7965
7966 vlv_compute_dpll(crtc, crtc_state);
7967
7968 return 0;
7969 }
7970
7971 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7972 struct intel_crtc_state *pipe_config)
7973 {
7974 struct drm_device *dev = crtc->base.dev;
7975 struct drm_i915_private *dev_priv = dev->dev_private;
7976 uint32_t tmp;
7977
7978 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7979 return;
7980
7981 tmp = I915_READ(PFIT_CONTROL);
7982 if (!(tmp & PFIT_ENABLE))
7983 return;
7984
7985 /* Check whether the pfit is attached to our pipe. */
7986 if (INTEL_INFO(dev)->gen < 4) {
7987 if (crtc->pipe != PIPE_B)
7988 return;
7989 } else {
7990 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7991 return;
7992 }
7993
7994 pipe_config->gmch_pfit.control = tmp;
7995 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7996 if (INTEL_INFO(dev)->gen < 5)
7997 pipe_config->gmch_pfit.lvds_border_bits =
7998 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7999 }
8000
8001 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8002 struct intel_crtc_state *pipe_config)
8003 {
8004 struct drm_device *dev = crtc->base.dev;
8005 struct drm_i915_private *dev_priv = dev->dev_private;
8006 int pipe = pipe_config->cpu_transcoder;
8007 intel_clock_t clock;
8008 u32 mdiv;
8009 int refclk = 100000;
8010
8011 /* In case of MIPI DPLL will not even be used */
8012 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8013 return;
8014
8015 mutex_lock(&dev_priv->sb_lock);
8016 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8017 mutex_unlock(&dev_priv->sb_lock);
8018
8019 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8020 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8021 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8022 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8023 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8024
8025 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8026 }
8027
8028 static void
8029 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8030 struct intel_initial_plane_config *plane_config)
8031 {
8032 struct drm_device *dev = crtc->base.dev;
8033 struct drm_i915_private *dev_priv = dev->dev_private;
8034 u32 val, base, offset;
8035 int pipe = crtc->pipe, plane = crtc->plane;
8036 int fourcc, pixel_format;
8037 unsigned int aligned_height;
8038 struct drm_framebuffer *fb;
8039 struct intel_framebuffer *intel_fb;
8040
8041 val = I915_READ(DSPCNTR(plane));
8042 if (!(val & DISPLAY_PLANE_ENABLE))
8043 return;
8044
8045 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8046 if (!intel_fb) {
8047 DRM_DEBUG_KMS("failed to alloc fb\n");
8048 return;
8049 }
8050
8051 fb = &intel_fb->base;
8052
8053 if (INTEL_INFO(dev)->gen >= 4) {
8054 if (val & DISPPLANE_TILED) {
8055 plane_config->tiling = I915_TILING_X;
8056 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8057 }
8058 }
8059
8060 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8061 fourcc = i9xx_format_to_fourcc(pixel_format);
8062 fb->pixel_format = fourcc;
8063 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8064
8065 if (INTEL_INFO(dev)->gen >= 4) {
8066 if (plane_config->tiling)
8067 offset = I915_READ(DSPTILEOFF(plane));
8068 else
8069 offset = I915_READ(DSPLINOFF(plane));
8070 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8071 } else {
8072 base = I915_READ(DSPADDR(plane));
8073 }
8074 plane_config->base = base;
8075
8076 val = I915_READ(PIPESRC(pipe));
8077 fb->width = ((val >> 16) & 0xfff) + 1;
8078 fb->height = ((val >> 0) & 0xfff) + 1;
8079
8080 val = I915_READ(DSPSTRIDE(pipe));
8081 fb->pitches[0] = val & 0xffffffc0;
8082
8083 aligned_height = intel_fb_align_height(dev, fb->height,
8084 fb->pixel_format,
8085 fb->modifier[0]);
8086
8087 plane_config->size = fb->pitches[0] * aligned_height;
8088
8089 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8090 pipe_name(pipe), plane, fb->width, fb->height,
8091 fb->bits_per_pixel, base, fb->pitches[0],
8092 plane_config->size);
8093
8094 plane_config->fb = intel_fb;
8095 }
8096
8097 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8098 struct intel_crtc_state *pipe_config)
8099 {
8100 struct drm_device *dev = crtc->base.dev;
8101 struct drm_i915_private *dev_priv = dev->dev_private;
8102 int pipe = pipe_config->cpu_transcoder;
8103 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8104 intel_clock_t clock;
8105 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8106 int refclk = 100000;
8107
8108 mutex_lock(&dev_priv->sb_lock);
8109 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8110 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8111 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8112 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8113 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8114 mutex_unlock(&dev_priv->sb_lock);
8115
8116 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8117 clock.m2 = (pll_dw0 & 0xff) << 22;
8118 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8119 clock.m2 |= pll_dw2 & 0x3fffff;
8120 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8121 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8122 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8123
8124 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8125 }
8126
8127 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8128 struct intel_crtc_state *pipe_config)
8129 {
8130 struct drm_device *dev = crtc->base.dev;
8131 struct drm_i915_private *dev_priv = dev->dev_private;
8132 enum intel_display_power_domain power_domain;
8133 uint32_t tmp;
8134 bool ret;
8135
8136 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8137 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8138 return false;
8139
8140 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8141 pipe_config->shared_dpll = NULL;
8142
8143 ret = false;
8144
8145 tmp = I915_READ(PIPECONF(crtc->pipe));
8146 if (!(tmp & PIPECONF_ENABLE))
8147 goto out;
8148
8149 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8150 switch (tmp & PIPECONF_BPC_MASK) {
8151 case PIPECONF_6BPC:
8152 pipe_config->pipe_bpp = 18;
8153 break;
8154 case PIPECONF_8BPC:
8155 pipe_config->pipe_bpp = 24;
8156 break;
8157 case PIPECONF_10BPC:
8158 pipe_config->pipe_bpp = 30;
8159 break;
8160 default:
8161 break;
8162 }
8163 }
8164
8165 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8166 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8167 pipe_config->limited_color_range = true;
8168
8169 if (INTEL_INFO(dev)->gen < 4)
8170 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8171
8172 intel_get_pipe_timings(crtc, pipe_config);
8173 intel_get_pipe_src_size(crtc, pipe_config);
8174
8175 i9xx_get_pfit_config(crtc, pipe_config);
8176
8177 if (INTEL_INFO(dev)->gen >= 4) {
8178 /* No way to read it out on pipes B and C */
8179 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8180 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8181 else
8182 tmp = I915_READ(DPLL_MD(crtc->pipe));
8183 pipe_config->pixel_multiplier =
8184 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8185 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8186 pipe_config->dpll_hw_state.dpll_md = tmp;
8187 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8188 tmp = I915_READ(DPLL(crtc->pipe));
8189 pipe_config->pixel_multiplier =
8190 ((tmp & SDVO_MULTIPLIER_MASK)
8191 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8192 } else {
8193 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8194 * port and will be fixed up in the encoder->get_config
8195 * function. */
8196 pipe_config->pixel_multiplier = 1;
8197 }
8198 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8199 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8200 /*
8201 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8202 * on 830. Filter it out here so that we don't
8203 * report errors due to that.
8204 */
8205 if (IS_I830(dev))
8206 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8207
8208 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8209 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8210 } else {
8211 /* Mask out read-only status bits. */
8212 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8213 DPLL_PORTC_READY_MASK |
8214 DPLL_PORTB_READY_MASK);
8215 }
8216
8217 if (IS_CHERRYVIEW(dev))
8218 chv_crtc_clock_get(crtc, pipe_config);
8219 else if (IS_VALLEYVIEW(dev))
8220 vlv_crtc_clock_get(crtc, pipe_config);
8221 else
8222 i9xx_crtc_clock_get(crtc, pipe_config);
8223
8224 /*
8225 * Normally the dotclock is filled in by the encoder .get_config()
8226 * but in case the pipe is enabled w/o any ports we need a sane
8227 * default.
8228 */
8229 pipe_config->base.adjusted_mode.crtc_clock =
8230 pipe_config->port_clock / pipe_config->pixel_multiplier;
8231
8232 ret = true;
8233
8234 out:
8235 intel_display_power_put(dev_priv, power_domain);
8236
8237 return ret;
8238 }
8239
8240 static void ironlake_init_pch_refclk(struct drm_device *dev)
8241 {
8242 struct drm_i915_private *dev_priv = dev->dev_private;
8243 struct intel_encoder *encoder;
8244 u32 val, final;
8245 bool has_lvds = false;
8246 bool has_cpu_edp = false;
8247 bool has_panel = false;
8248 bool has_ck505 = false;
8249 bool can_ssc = false;
8250
8251 /* We need to take the global config into account */
8252 for_each_intel_encoder(dev, encoder) {
8253 switch (encoder->type) {
8254 case INTEL_OUTPUT_LVDS:
8255 has_panel = true;
8256 has_lvds = true;
8257 break;
8258 case INTEL_OUTPUT_EDP:
8259 has_panel = true;
8260 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8261 has_cpu_edp = true;
8262 break;
8263 default:
8264 break;
8265 }
8266 }
8267
8268 if (HAS_PCH_IBX(dev)) {
8269 has_ck505 = dev_priv->vbt.display_clock_mode;
8270 can_ssc = has_ck505;
8271 } else {
8272 has_ck505 = false;
8273 can_ssc = true;
8274 }
8275
8276 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8277 has_panel, has_lvds, has_ck505);
8278
8279 /* Ironlake: try to setup display ref clock before DPLL
8280 * enabling. This is only under driver's control after
8281 * PCH B stepping, previous chipset stepping should be
8282 * ignoring this setting.
8283 */
8284 val = I915_READ(PCH_DREF_CONTROL);
8285
8286 /* As we must carefully and slowly disable/enable each source in turn,
8287 * compute the final state we want first and check if we need to
8288 * make any changes at all.
8289 */
8290 final = val;
8291 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8292 if (has_ck505)
8293 final |= DREF_NONSPREAD_CK505_ENABLE;
8294 else
8295 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8296
8297 final &= ~DREF_SSC_SOURCE_MASK;
8298 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8299 final &= ~DREF_SSC1_ENABLE;
8300
8301 if (has_panel) {
8302 final |= DREF_SSC_SOURCE_ENABLE;
8303
8304 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8305 final |= DREF_SSC1_ENABLE;
8306
8307 if (has_cpu_edp) {
8308 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8309 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8310 else
8311 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8312 } else
8313 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8314 } else {
8315 final |= DREF_SSC_SOURCE_DISABLE;
8316 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8317 }
8318
8319 if (final == val)
8320 return;
8321
8322 /* Always enable nonspread source */
8323 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8324
8325 if (has_ck505)
8326 val |= DREF_NONSPREAD_CK505_ENABLE;
8327 else
8328 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8329
8330 if (has_panel) {
8331 val &= ~DREF_SSC_SOURCE_MASK;
8332 val |= DREF_SSC_SOURCE_ENABLE;
8333
8334 /* SSC must be turned on before enabling the CPU output */
8335 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8336 DRM_DEBUG_KMS("Using SSC on panel\n");
8337 val |= DREF_SSC1_ENABLE;
8338 } else
8339 val &= ~DREF_SSC1_ENABLE;
8340
8341 /* Get SSC going before enabling the outputs */
8342 I915_WRITE(PCH_DREF_CONTROL, val);
8343 POSTING_READ(PCH_DREF_CONTROL);
8344 udelay(200);
8345
8346 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8347
8348 /* Enable CPU source on CPU attached eDP */
8349 if (has_cpu_edp) {
8350 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8351 DRM_DEBUG_KMS("Using SSC on eDP\n");
8352 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8353 } else
8354 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8355 } else
8356 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8357
8358 I915_WRITE(PCH_DREF_CONTROL, val);
8359 POSTING_READ(PCH_DREF_CONTROL);
8360 udelay(200);
8361 } else {
8362 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8363
8364 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8365
8366 /* Turn off CPU output */
8367 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8368
8369 I915_WRITE(PCH_DREF_CONTROL, val);
8370 POSTING_READ(PCH_DREF_CONTROL);
8371 udelay(200);
8372
8373 /* Turn off the SSC source */
8374 val &= ~DREF_SSC_SOURCE_MASK;
8375 val |= DREF_SSC_SOURCE_DISABLE;
8376
8377 /* Turn off SSC1 */
8378 val &= ~DREF_SSC1_ENABLE;
8379
8380 I915_WRITE(PCH_DREF_CONTROL, val);
8381 POSTING_READ(PCH_DREF_CONTROL);
8382 udelay(200);
8383 }
8384
8385 BUG_ON(val != final);
8386 }
8387
8388 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8389 {
8390 uint32_t tmp;
8391
8392 tmp = I915_READ(SOUTH_CHICKEN2);
8393 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8394 I915_WRITE(SOUTH_CHICKEN2, tmp);
8395
8396 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8397 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8398 DRM_ERROR("FDI mPHY reset assert timeout\n");
8399
8400 tmp = I915_READ(SOUTH_CHICKEN2);
8401 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8402 I915_WRITE(SOUTH_CHICKEN2, tmp);
8403
8404 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8405 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8406 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8407 }
8408
8409 /* WaMPhyProgramming:hsw */
8410 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8411 {
8412 uint32_t tmp;
8413
8414 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8415 tmp &= ~(0xFF << 24);
8416 tmp |= (0x12 << 24);
8417 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8418
8419 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8420 tmp |= (1 << 11);
8421 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8422
8423 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8424 tmp |= (1 << 11);
8425 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8426
8427 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8428 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8429 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8430
8431 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8432 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8433 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8434
8435 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8436 tmp &= ~(7 << 13);
8437 tmp |= (5 << 13);
8438 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8439
8440 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8441 tmp &= ~(7 << 13);
8442 tmp |= (5 << 13);
8443 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8444
8445 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8446 tmp &= ~0xFF;
8447 tmp |= 0x1C;
8448 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8449
8450 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8451 tmp &= ~0xFF;
8452 tmp |= 0x1C;
8453 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8454
8455 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8456 tmp &= ~(0xFF << 16);
8457 tmp |= (0x1C << 16);
8458 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8459
8460 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8461 tmp &= ~(0xFF << 16);
8462 tmp |= (0x1C << 16);
8463 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8464
8465 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8466 tmp |= (1 << 27);
8467 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8468
8469 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8470 tmp |= (1 << 27);
8471 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8472
8473 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8474 tmp &= ~(0xF << 28);
8475 tmp |= (4 << 28);
8476 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8477
8478 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8479 tmp &= ~(0xF << 28);
8480 tmp |= (4 << 28);
8481 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8482 }
8483
8484 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8485 * Programming" based on the parameters passed:
8486 * - Sequence to enable CLKOUT_DP
8487 * - Sequence to enable CLKOUT_DP without spread
8488 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8489 */
8490 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8491 bool with_fdi)
8492 {
8493 struct drm_i915_private *dev_priv = dev->dev_private;
8494 uint32_t reg, tmp;
8495
8496 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8497 with_spread = true;
8498 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8499 with_fdi = false;
8500
8501 mutex_lock(&dev_priv->sb_lock);
8502
8503 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8504 tmp &= ~SBI_SSCCTL_DISABLE;
8505 tmp |= SBI_SSCCTL_PATHALT;
8506 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8507
8508 udelay(24);
8509
8510 if (with_spread) {
8511 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8512 tmp &= ~SBI_SSCCTL_PATHALT;
8513 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8514
8515 if (with_fdi) {
8516 lpt_reset_fdi_mphy(dev_priv);
8517 lpt_program_fdi_mphy(dev_priv);
8518 }
8519 }
8520
8521 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8522 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8523 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8524 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8525
8526 mutex_unlock(&dev_priv->sb_lock);
8527 }
8528
8529 /* Sequence to disable CLKOUT_DP */
8530 static void lpt_disable_clkout_dp(struct drm_device *dev)
8531 {
8532 struct drm_i915_private *dev_priv = dev->dev_private;
8533 uint32_t reg, tmp;
8534
8535 mutex_lock(&dev_priv->sb_lock);
8536
8537 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8538 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8539 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8540 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8541
8542 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8543 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8544 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8545 tmp |= SBI_SSCCTL_PATHALT;
8546 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8547 udelay(32);
8548 }
8549 tmp |= SBI_SSCCTL_DISABLE;
8550 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8551 }
8552
8553 mutex_unlock(&dev_priv->sb_lock);
8554 }
8555
8556 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8557
8558 static const uint16_t sscdivintphase[] = {
8559 [BEND_IDX( 50)] = 0x3B23,
8560 [BEND_IDX( 45)] = 0x3B23,
8561 [BEND_IDX( 40)] = 0x3C23,
8562 [BEND_IDX( 35)] = 0x3C23,
8563 [BEND_IDX( 30)] = 0x3D23,
8564 [BEND_IDX( 25)] = 0x3D23,
8565 [BEND_IDX( 20)] = 0x3E23,
8566 [BEND_IDX( 15)] = 0x3E23,
8567 [BEND_IDX( 10)] = 0x3F23,
8568 [BEND_IDX( 5)] = 0x3F23,
8569 [BEND_IDX( 0)] = 0x0025,
8570 [BEND_IDX( -5)] = 0x0025,
8571 [BEND_IDX(-10)] = 0x0125,
8572 [BEND_IDX(-15)] = 0x0125,
8573 [BEND_IDX(-20)] = 0x0225,
8574 [BEND_IDX(-25)] = 0x0225,
8575 [BEND_IDX(-30)] = 0x0325,
8576 [BEND_IDX(-35)] = 0x0325,
8577 [BEND_IDX(-40)] = 0x0425,
8578 [BEND_IDX(-45)] = 0x0425,
8579 [BEND_IDX(-50)] = 0x0525,
8580 };
8581
8582 /*
8583 * Bend CLKOUT_DP
8584 * steps -50 to 50 inclusive, in steps of 5
8585 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8586 * change in clock period = -(steps / 10) * 5.787 ps
8587 */
8588 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8589 {
8590 uint32_t tmp;
8591 int idx = BEND_IDX(steps);
8592
8593 if (WARN_ON(steps % 5 != 0))
8594 return;
8595
8596 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8597 return;
8598
8599 mutex_lock(&dev_priv->sb_lock);
8600
8601 if (steps % 10 != 0)
8602 tmp = 0xAAAAAAAB;
8603 else
8604 tmp = 0x00000000;
8605 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8606
8607 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8608 tmp &= 0xffff0000;
8609 tmp |= sscdivintphase[idx];
8610 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8611
8612 mutex_unlock(&dev_priv->sb_lock);
8613 }
8614
8615 #undef BEND_IDX
8616
8617 static void lpt_init_pch_refclk(struct drm_device *dev)
8618 {
8619 struct intel_encoder *encoder;
8620 bool has_vga = false;
8621
8622 for_each_intel_encoder(dev, encoder) {
8623 switch (encoder->type) {
8624 case INTEL_OUTPUT_ANALOG:
8625 has_vga = true;
8626 break;
8627 default:
8628 break;
8629 }
8630 }
8631
8632 if (has_vga) {
8633 lpt_bend_clkout_dp(to_i915(dev), 0);
8634 lpt_enable_clkout_dp(dev, true, true);
8635 } else {
8636 lpt_disable_clkout_dp(dev);
8637 }
8638 }
8639
8640 /*
8641 * Initialize reference clocks when the driver loads
8642 */
8643 void intel_init_pch_refclk(struct drm_device *dev)
8644 {
8645 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8646 ironlake_init_pch_refclk(dev);
8647 else if (HAS_PCH_LPT(dev))
8648 lpt_init_pch_refclk(dev);
8649 }
8650
8651 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8652 {
8653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8655 int pipe = intel_crtc->pipe;
8656 uint32_t val;
8657
8658 val = 0;
8659
8660 switch (intel_crtc->config->pipe_bpp) {
8661 case 18:
8662 val |= PIPECONF_6BPC;
8663 break;
8664 case 24:
8665 val |= PIPECONF_8BPC;
8666 break;
8667 case 30:
8668 val |= PIPECONF_10BPC;
8669 break;
8670 case 36:
8671 val |= PIPECONF_12BPC;
8672 break;
8673 default:
8674 /* Case prevented by intel_choose_pipe_bpp_dither. */
8675 BUG();
8676 }
8677
8678 if (intel_crtc->config->dither)
8679 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8680
8681 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8682 val |= PIPECONF_INTERLACED_ILK;
8683 else
8684 val |= PIPECONF_PROGRESSIVE;
8685
8686 if (intel_crtc->config->limited_color_range)
8687 val |= PIPECONF_COLOR_RANGE_SELECT;
8688
8689 I915_WRITE(PIPECONF(pipe), val);
8690 POSTING_READ(PIPECONF(pipe));
8691 }
8692
8693 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8694 {
8695 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8697 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8698 u32 val = 0;
8699
8700 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8701 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8702
8703 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8704 val |= PIPECONF_INTERLACED_ILK;
8705 else
8706 val |= PIPECONF_PROGRESSIVE;
8707
8708 I915_WRITE(PIPECONF(cpu_transcoder), val);
8709 POSTING_READ(PIPECONF(cpu_transcoder));
8710 }
8711
8712 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8713 {
8714 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8716
8717 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8718 u32 val = 0;
8719
8720 switch (intel_crtc->config->pipe_bpp) {
8721 case 18:
8722 val |= PIPEMISC_DITHER_6_BPC;
8723 break;
8724 case 24:
8725 val |= PIPEMISC_DITHER_8_BPC;
8726 break;
8727 case 30:
8728 val |= PIPEMISC_DITHER_10_BPC;
8729 break;
8730 case 36:
8731 val |= PIPEMISC_DITHER_12_BPC;
8732 break;
8733 default:
8734 /* Case prevented by pipe_config_set_bpp. */
8735 BUG();
8736 }
8737
8738 if (intel_crtc->config->dither)
8739 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8740
8741 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8742 }
8743 }
8744
8745 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8746 {
8747 /*
8748 * Account for spread spectrum to avoid
8749 * oversubscribing the link. Max center spread
8750 * is 2.5%; use 5% for safety's sake.
8751 */
8752 u32 bps = target_clock * bpp * 21 / 20;
8753 return DIV_ROUND_UP(bps, link_bw * 8);
8754 }
8755
8756 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8757 {
8758 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8759 }
8760
8761 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8762 struct intel_crtc_state *crtc_state,
8763 intel_clock_t *reduced_clock)
8764 {
8765 struct drm_crtc *crtc = &intel_crtc->base;
8766 struct drm_device *dev = crtc->dev;
8767 struct drm_i915_private *dev_priv = dev->dev_private;
8768 struct drm_atomic_state *state = crtc_state->base.state;
8769 struct drm_connector *connector;
8770 struct drm_connector_state *connector_state;
8771 struct intel_encoder *encoder;
8772 u32 dpll, fp, fp2;
8773 int factor, i;
8774 bool is_lvds = false, is_sdvo = false;
8775
8776 for_each_connector_in_state(state, connector, connector_state, i) {
8777 if (connector_state->crtc != crtc_state->base.crtc)
8778 continue;
8779
8780 encoder = to_intel_encoder(connector_state->best_encoder);
8781
8782 switch (encoder->type) {
8783 case INTEL_OUTPUT_LVDS:
8784 is_lvds = true;
8785 break;
8786 case INTEL_OUTPUT_SDVO:
8787 case INTEL_OUTPUT_HDMI:
8788 is_sdvo = true;
8789 break;
8790 default:
8791 break;
8792 }
8793 }
8794
8795 /* Enable autotuning of the PLL clock (if permissible) */
8796 factor = 21;
8797 if (is_lvds) {
8798 if ((intel_panel_use_ssc(dev_priv) &&
8799 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8800 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8801 factor = 25;
8802 } else if (crtc_state->sdvo_tv_clock)
8803 factor = 20;
8804
8805 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8806
8807 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8808 fp |= FP_CB_TUNE;
8809
8810 if (reduced_clock) {
8811 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8812
8813 if (reduced_clock->m < factor * reduced_clock->n)
8814 fp2 |= FP_CB_TUNE;
8815 } else {
8816 fp2 = fp;
8817 }
8818
8819 dpll = 0;
8820
8821 if (is_lvds)
8822 dpll |= DPLLB_MODE_LVDS;
8823 else
8824 dpll |= DPLLB_MODE_DAC_SERIAL;
8825
8826 dpll |= (crtc_state->pixel_multiplier - 1)
8827 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8828
8829 if (is_sdvo)
8830 dpll |= DPLL_SDVO_HIGH_SPEED;
8831 if (crtc_state->has_dp_encoder)
8832 dpll |= DPLL_SDVO_HIGH_SPEED;
8833
8834 /* compute bitmask from p1 value */
8835 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8836 /* also FPA1 */
8837 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8838
8839 switch (crtc_state->dpll.p2) {
8840 case 5:
8841 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8842 break;
8843 case 7:
8844 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8845 break;
8846 case 10:
8847 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8848 break;
8849 case 14:
8850 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8851 break;
8852 }
8853
8854 if (is_lvds && intel_panel_use_ssc(dev_priv))
8855 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8856 else
8857 dpll |= PLL_REF_INPUT_DREFCLK;
8858
8859 dpll |= DPLL_VCO_ENABLE;
8860
8861 crtc_state->dpll_hw_state.dpll = dpll;
8862 crtc_state->dpll_hw_state.fp0 = fp;
8863 crtc_state->dpll_hw_state.fp1 = fp2;
8864 }
8865
8866 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8867 struct intel_crtc_state *crtc_state)
8868 {
8869 struct drm_device *dev = crtc->base.dev;
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 intel_clock_t reduced_clock;
8872 bool has_reduced_clock = false;
8873 struct intel_shared_dpll *pll;
8874 const intel_limit_t *limit;
8875 int refclk = 120000;
8876
8877 memset(&crtc_state->dpll_hw_state, 0,
8878 sizeof(crtc_state->dpll_hw_state));
8879
8880 crtc->lowfreq_avail = false;
8881
8882 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8883 if (!crtc_state->has_pch_encoder)
8884 return 0;
8885
8886 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8887 if (intel_panel_use_ssc(dev_priv)) {
8888 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8889 dev_priv->vbt.lvds_ssc_freq);
8890 refclk = dev_priv->vbt.lvds_ssc_freq;
8891 }
8892
8893 if (intel_is_dual_link_lvds(dev)) {
8894 if (refclk == 100000)
8895 limit = &intel_limits_ironlake_dual_lvds_100m;
8896 else
8897 limit = &intel_limits_ironlake_dual_lvds;
8898 } else {
8899 if (refclk == 100000)
8900 limit = &intel_limits_ironlake_single_lvds_100m;
8901 else
8902 limit = &intel_limits_ironlake_single_lvds;
8903 }
8904 } else {
8905 limit = &intel_limits_ironlake_dac;
8906 }
8907
8908 if (!crtc_state->clock_set &&
8909 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8910 refclk, NULL, &crtc_state->dpll)) {
8911 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8912 return -EINVAL;
8913 }
8914
8915 ironlake_compute_dpll(crtc, crtc_state,
8916 has_reduced_clock ? &reduced_clock : NULL);
8917
8918 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8919 if (pll == NULL) {
8920 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8921 pipe_name(crtc->pipe));
8922 return -EINVAL;
8923 }
8924
8925 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8926 has_reduced_clock)
8927 crtc->lowfreq_avail = true;
8928
8929 return 0;
8930 }
8931
8932 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8933 struct intel_link_m_n *m_n)
8934 {
8935 struct drm_device *dev = crtc->base.dev;
8936 struct drm_i915_private *dev_priv = dev->dev_private;
8937 enum pipe pipe = crtc->pipe;
8938
8939 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8940 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8941 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8942 & ~TU_SIZE_MASK;
8943 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8944 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8945 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8946 }
8947
8948 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8949 enum transcoder transcoder,
8950 struct intel_link_m_n *m_n,
8951 struct intel_link_m_n *m2_n2)
8952 {
8953 struct drm_device *dev = crtc->base.dev;
8954 struct drm_i915_private *dev_priv = dev->dev_private;
8955 enum pipe pipe = crtc->pipe;
8956
8957 if (INTEL_INFO(dev)->gen >= 5) {
8958 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8959 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8960 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8961 & ~TU_SIZE_MASK;
8962 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8963 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8964 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8965 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8966 * gen < 8) and if DRRS is supported (to make sure the
8967 * registers are not unnecessarily read).
8968 */
8969 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8970 crtc->config->has_drrs) {
8971 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8972 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8973 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8974 & ~TU_SIZE_MASK;
8975 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8976 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8977 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8978 }
8979 } else {
8980 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8981 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8982 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8983 & ~TU_SIZE_MASK;
8984 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8985 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8986 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8987 }
8988 }
8989
8990 void intel_dp_get_m_n(struct intel_crtc *crtc,
8991 struct intel_crtc_state *pipe_config)
8992 {
8993 if (pipe_config->has_pch_encoder)
8994 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8995 else
8996 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8997 &pipe_config->dp_m_n,
8998 &pipe_config->dp_m2_n2);
8999 }
9000
9001 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9002 struct intel_crtc_state *pipe_config)
9003 {
9004 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9005 &pipe_config->fdi_m_n, NULL);
9006 }
9007
9008 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9009 struct intel_crtc_state *pipe_config)
9010 {
9011 struct drm_device *dev = crtc->base.dev;
9012 struct drm_i915_private *dev_priv = dev->dev_private;
9013 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9014 uint32_t ps_ctrl = 0;
9015 int id = -1;
9016 int i;
9017
9018 /* find scaler attached to this pipe */
9019 for (i = 0; i < crtc->num_scalers; i++) {
9020 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9021 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9022 id = i;
9023 pipe_config->pch_pfit.enabled = true;
9024 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9025 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9026 break;
9027 }
9028 }
9029
9030 scaler_state->scaler_id = id;
9031 if (id >= 0) {
9032 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9033 } else {
9034 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9035 }
9036 }
9037
9038 static void
9039 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9040 struct intel_initial_plane_config *plane_config)
9041 {
9042 struct drm_device *dev = crtc->base.dev;
9043 struct drm_i915_private *dev_priv = dev->dev_private;
9044 u32 val, base, offset, stride_mult, tiling;
9045 int pipe = crtc->pipe;
9046 int fourcc, pixel_format;
9047 unsigned int aligned_height;
9048 struct drm_framebuffer *fb;
9049 struct intel_framebuffer *intel_fb;
9050
9051 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9052 if (!intel_fb) {
9053 DRM_DEBUG_KMS("failed to alloc fb\n");
9054 return;
9055 }
9056
9057 fb = &intel_fb->base;
9058
9059 val = I915_READ(PLANE_CTL(pipe, 0));
9060 if (!(val & PLANE_CTL_ENABLE))
9061 goto error;
9062
9063 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9064 fourcc = skl_format_to_fourcc(pixel_format,
9065 val & PLANE_CTL_ORDER_RGBX,
9066 val & PLANE_CTL_ALPHA_MASK);
9067 fb->pixel_format = fourcc;
9068 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9069
9070 tiling = val & PLANE_CTL_TILED_MASK;
9071 switch (tiling) {
9072 case PLANE_CTL_TILED_LINEAR:
9073 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9074 break;
9075 case PLANE_CTL_TILED_X:
9076 plane_config->tiling = I915_TILING_X;
9077 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9078 break;
9079 case PLANE_CTL_TILED_Y:
9080 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9081 break;
9082 case PLANE_CTL_TILED_YF:
9083 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9084 break;
9085 default:
9086 MISSING_CASE(tiling);
9087 goto error;
9088 }
9089
9090 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9091 plane_config->base = base;
9092
9093 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9094
9095 val = I915_READ(PLANE_SIZE(pipe, 0));
9096 fb->height = ((val >> 16) & 0xfff) + 1;
9097 fb->width = ((val >> 0) & 0x1fff) + 1;
9098
9099 val = I915_READ(PLANE_STRIDE(pipe, 0));
9100 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9101 fb->pixel_format);
9102 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9103
9104 aligned_height = intel_fb_align_height(dev, fb->height,
9105 fb->pixel_format,
9106 fb->modifier[0]);
9107
9108 plane_config->size = fb->pitches[0] * aligned_height;
9109
9110 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9111 pipe_name(pipe), fb->width, fb->height,
9112 fb->bits_per_pixel, base, fb->pitches[0],
9113 plane_config->size);
9114
9115 plane_config->fb = intel_fb;
9116 return;
9117
9118 error:
9119 kfree(fb);
9120 }
9121
9122 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9123 struct intel_crtc_state *pipe_config)
9124 {
9125 struct drm_device *dev = crtc->base.dev;
9126 struct drm_i915_private *dev_priv = dev->dev_private;
9127 uint32_t tmp;
9128
9129 tmp = I915_READ(PF_CTL(crtc->pipe));
9130
9131 if (tmp & PF_ENABLE) {
9132 pipe_config->pch_pfit.enabled = true;
9133 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9134 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9135
9136 /* We currently do not free assignements of panel fitters on
9137 * ivb/hsw (since we don't use the higher upscaling modes which
9138 * differentiates them) so just WARN about this case for now. */
9139 if (IS_GEN7(dev)) {
9140 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9141 PF_PIPE_SEL_IVB(crtc->pipe));
9142 }
9143 }
9144 }
9145
9146 static void
9147 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9148 struct intel_initial_plane_config *plane_config)
9149 {
9150 struct drm_device *dev = crtc->base.dev;
9151 struct drm_i915_private *dev_priv = dev->dev_private;
9152 u32 val, base, offset;
9153 int pipe = crtc->pipe;
9154 int fourcc, pixel_format;
9155 unsigned int aligned_height;
9156 struct drm_framebuffer *fb;
9157 struct intel_framebuffer *intel_fb;
9158
9159 val = I915_READ(DSPCNTR(pipe));
9160 if (!(val & DISPLAY_PLANE_ENABLE))
9161 return;
9162
9163 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9164 if (!intel_fb) {
9165 DRM_DEBUG_KMS("failed to alloc fb\n");
9166 return;
9167 }
9168
9169 fb = &intel_fb->base;
9170
9171 if (INTEL_INFO(dev)->gen >= 4) {
9172 if (val & DISPPLANE_TILED) {
9173 plane_config->tiling = I915_TILING_X;
9174 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9175 }
9176 }
9177
9178 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9179 fourcc = i9xx_format_to_fourcc(pixel_format);
9180 fb->pixel_format = fourcc;
9181 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9182
9183 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9184 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9185 offset = I915_READ(DSPOFFSET(pipe));
9186 } else {
9187 if (plane_config->tiling)
9188 offset = I915_READ(DSPTILEOFF(pipe));
9189 else
9190 offset = I915_READ(DSPLINOFF(pipe));
9191 }
9192 plane_config->base = base;
9193
9194 val = I915_READ(PIPESRC(pipe));
9195 fb->width = ((val >> 16) & 0xfff) + 1;
9196 fb->height = ((val >> 0) & 0xfff) + 1;
9197
9198 val = I915_READ(DSPSTRIDE(pipe));
9199 fb->pitches[0] = val & 0xffffffc0;
9200
9201 aligned_height = intel_fb_align_height(dev, fb->height,
9202 fb->pixel_format,
9203 fb->modifier[0]);
9204
9205 plane_config->size = fb->pitches[0] * aligned_height;
9206
9207 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9208 pipe_name(pipe), fb->width, fb->height,
9209 fb->bits_per_pixel, base, fb->pitches[0],
9210 plane_config->size);
9211
9212 plane_config->fb = intel_fb;
9213 }
9214
9215 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9216 struct intel_crtc_state *pipe_config)
9217 {
9218 struct drm_device *dev = crtc->base.dev;
9219 struct drm_i915_private *dev_priv = dev->dev_private;
9220 enum intel_display_power_domain power_domain;
9221 uint32_t tmp;
9222 bool ret;
9223
9224 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9225 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9226 return false;
9227
9228 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9229 pipe_config->shared_dpll = NULL;
9230
9231 ret = false;
9232 tmp = I915_READ(PIPECONF(crtc->pipe));
9233 if (!(tmp & PIPECONF_ENABLE))
9234 goto out;
9235
9236 switch (tmp & PIPECONF_BPC_MASK) {
9237 case PIPECONF_6BPC:
9238 pipe_config->pipe_bpp = 18;
9239 break;
9240 case PIPECONF_8BPC:
9241 pipe_config->pipe_bpp = 24;
9242 break;
9243 case PIPECONF_10BPC:
9244 pipe_config->pipe_bpp = 30;
9245 break;
9246 case PIPECONF_12BPC:
9247 pipe_config->pipe_bpp = 36;
9248 break;
9249 default:
9250 break;
9251 }
9252
9253 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9254 pipe_config->limited_color_range = true;
9255
9256 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9257 struct intel_shared_dpll *pll;
9258 enum intel_dpll_id pll_id;
9259
9260 pipe_config->has_pch_encoder = true;
9261
9262 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9263 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9264 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9265
9266 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9267
9268 if (HAS_PCH_IBX(dev_priv)) {
9269 pll_id = (enum intel_dpll_id) crtc->pipe;
9270 } else {
9271 tmp = I915_READ(PCH_DPLL_SEL);
9272 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9273 pll_id = DPLL_ID_PCH_PLL_B;
9274 else
9275 pll_id= DPLL_ID_PCH_PLL_A;
9276 }
9277
9278 pipe_config->shared_dpll =
9279 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9280 pll = pipe_config->shared_dpll;
9281
9282 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9283 &pipe_config->dpll_hw_state));
9284
9285 tmp = pipe_config->dpll_hw_state.dpll;
9286 pipe_config->pixel_multiplier =
9287 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9288 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9289
9290 ironlake_pch_clock_get(crtc, pipe_config);
9291 } else {
9292 pipe_config->pixel_multiplier = 1;
9293 }
9294
9295 intel_get_pipe_timings(crtc, pipe_config);
9296 intel_get_pipe_src_size(crtc, pipe_config);
9297
9298 ironlake_get_pfit_config(crtc, pipe_config);
9299
9300 ret = true;
9301
9302 out:
9303 intel_display_power_put(dev_priv, power_domain);
9304
9305 return ret;
9306 }
9307
9308 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9309 {
9310 struct drm_device *dev = dev_priv->dev;
9311 struct intel_crtc *crtc;
9312
9313 for_each_intel_crtc(dev, crtc)
9314 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9315 pipe_name(crtc->pipe));
9316
9317 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9318 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9319 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9320 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9321 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9322 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9323 "CPU PWM1 enabled\n");
9324 if (IS_HASWELL(dev))
9325 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9326 "CPU PWM2 enabled\n");
9327 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9328 "PCH PWM1 enabled\n");
9329 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9330 "Utility pin enabled\n");
9331 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9332
9333 /*
9334 * In theory we can still leave IRQs enabled, as long as only the HPD
9335 * interrupts remain enabled. We used to check for that, but since it's
9336 * gen-specific and since we only disable LCPLL after we fully disable
9337 * the interrupts, the check below should be enough.
9338 */
9339 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9340 }
9341
9342 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9343 {
9344 struct drm_device *dev = dev_priv->dev;
9345
9346 if (IS_HASWELL(dev))
9347 return I915_READ(D_COMP_HSW);
9348 else
9349 return I915_READ(D_COMP_BDW);
9350 }
9351
9352 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9353 {
9354 struct drm_device *dev = dev_priv->dev;
9355
9356 if (IS_HASWELL(dev)) {
9357 mutex_lock(&dev_priv->rps.hw_lock);
9358 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9359 val))
9360 DRM_ERROR("Failed to write to D_COMP\n");
9361 mutex_unlock(&dev_priv->rps.hw_lock);
9362 } else {
9363 I915_WRITE(D_COMP_BDW, val);
9364 POSTING_READ(D_COMP_BDW);
9365 }
9366 }
9367
9368 /*
9369 * This function implements pieces of two sequences from BSpec:
9370 * - Sequence for display software to disable LCPLL
9371 * - Sequence for display software to allow package C8+
9372 * The steps implemented here are just the steps that actually touch the LCPLL
9373 * register. Callers should take care of disabling all the display engine
9374 * functions, doing the mode unset, fixing interrupts, etc.
9375 */
9376 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9377 bool switch_to_fclk, bool allow_power_down)
9378 {
9379 uint32_t val;
9380
9381 assert_can_disable_lcpll(dev_priv);
9382
9383 val = I915_READ(LCPLL_CTL);
9384
9385 if (switch_to_fclk) {
9386 val |= LCPLL_CD_SOURCE_FCLK;
9387 I915_WRITE(LCPLL_CTL, val);
9388
9389 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9390 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9391 DRM_ERROR("Switching to FCLK failed\n");
9392
9393 val = I915_READ(LCPLL_CTL);
9394 }
9395
9396 val |= LCPLL_PLL_DISABLE;
9397 I915_WRITE(LCPLL_CTL, val);
9398 POSTING_READ(LCPLL_CTL);
9399
9400 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9401 DRM_ERROR("LCPLL still locked\n");
9402
9403 val = hsw_read_dcomp(dev_priv);
9404 val |= D_COMP_COMP_DISABLE;
9405 hsw_write_dcomp(dev_priv, val);
9406 ndelay(100);
9407
9408 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9409 1))
9410 DRM_ERROR("D_COMP RCOMP still in progress\n");
9411
9412 if (allow_power_down) {
9413 val = I915_READ(LCPLL_CTL);
9414 val |= LCPLL_POWER_DOWN_ALLOW;
9415 I915_WRITE(LCPLL_CTL, val);
9416 POSTING_READ(LCPLL_CTL);
9417 }
9418 }
9419
9420 /*
9421 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9422 * source.
9423 */
9424 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9425 {
9426 uint32_t val;
9427
9428 val = I915_READ(LCPLL_CTL);
9429
9430 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9431 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9432 return;
9433
9434 /*
9435 * Make sure we're not on PC8 state before disabling PC8, otherwise
9436 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9437 */
9438 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9439
9440 if (val & LCPLL_POWER_DOWN_ALLOW) {
9441 val &= ~LCPLL_POWER_DOWN_ALLOW;
9442 I915_WRITE(LCPLL_CTL, val);
9443 POSTING_READ(LCPLL_CTL);
9444 }
9445
9446 val = hsw_read_dcomp(dev_priv);
9447 val |= D_COMP_COMP_FORCE;
9448 val &= ~D_COMP_COMP_DISABLE;
9449 hsw_write_dcomp(dev_priv, val);
9450
9451 val = I915_READ(LCPLL_CTL);
9452 val &= ~LCPLL_PLL_DISABLE;
9453 I915_WRITE(LCPLL_CTL, val);
9454
9455 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9456 DRM_ERROR("LCPLL not locked yet\n");
9457
9458 if (val & LCPLL_CD_SOURCE_FCLK) {
9459 val = I915_READ(LCPLL_CTL);
9460 val &= ~LCPLL_CD_SOURCE_FCLK;
9461 I915_WRITE(LCPLL_CTL, val);
9462
9463 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9464 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9465 DRM_ERROR("Switching back to LCPLL failed\n");
9466 }
9467
9468 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9469 intel_update_cdclk(dev_priv->dev);
9470 }
9471
9472 /*
9473 * Package states C8 and deeper are really deep PC states that can only be
9474 * reached when all the devices on the system allow it, so even if the graphics
9475 * device allows PC8+, it doesn't mean the system will actually get to these
9476 * states. Our driver only allows PC8+ when going into runtime PM.
9477 *
9478 * The requirements for PC8+ are that all the outputs are disabled, the power
9479 * well is disabled and most interrupts are disabled, and these are also
9480 * requirements for runtime PM. When these conditions are met, we manually do
9481 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9482 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9483 * hang the machine.
9484 *
9485 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9486 * the state of some registers, so when we come back from PC8+ we need to
9487 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9488 * need to take care of the registers kept by RC6. Notice that this happens even
9489 * if we don't put the device in PCI D3 state (which is what currently happens
9490 * because of the runtime PM support).
9491 *
9492 * For more, read "Display Sequences for Package C8" on the hardware
9493 * documentation.
9494 */
9495 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9496 {
9497 struct drm_device *dev = dev_priv->dev;
9498 uint32_t val;
9499
9500 DRM_DEBUG_KMS("Enabling package C8+\n");
9501
9502 if (HAS_PCH_LPT_LP(dev)) {
9503 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9504 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9505 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9506 }
9507
9508 lpt_disable_clkout_dp(dev);
9509 hsw_disable_lcpll(dev_priv, true, true);
9510 }
9511
9512 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9513 {
9514 struct drm_device *dev = dev_priv->dev;
9515 uint32_t val;
9516
9517 DRM_DEBUG_KMS("Disabling package C8+\n");
9518
9519 hsw_restore_lcpll(dev_priv);
9520 lpt_init_pch_refclk(dev);
9521
9522 if (HAS_PCH_LPT_LP(dev)) {
9523 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9524 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9525 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9526 }
9527 }
9528
9529 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9530 {
9531 struct drm_device *dev = old_state->dev;
9532 struct intel_atomic_state *old_intel_state =
9533 to_intel_atomic_state(old_state);
9534 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9535
9536 broxton_set_cdclk(dev, req_cdclk);
9537 }
9538
9539 /* compute the max rate for new configuration */
9540 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9541 {
9542 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9543 struct drm_i915_private *dev_priv = state->dev->dev_private;
9544 struct drm_crtc *crtc;
9545 struct drm_crtc_state *cstate;
9546 struct intel_crtc_state *crtc_state;
9547 unsigned max_pixel_rate = 0, i;
9548 enum pipe pipe;
9549
9550 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9551 sizeof(intel_state->min_pixclk));
9552
9553 for_each_crtc_in_state(state, crtc, cstate, i) {
9554 int pixel_rate;
9555
9556 crtc_state = to_intel_crtc_state(cstate);
9557 if (!crtc_state->base.enable) {
9558 intel_state->min_pixclk[i] = 0;
9559 continue;
9560 }
9561
9562 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9563
9564 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9565 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9566 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9567
9568 intel_state->min_pixclk[i] = pixel_rate;
9569 }
9570
9571 for_each_pipe(dev_priv, pipe)
9572 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9573
9574 return max_pixel_rate;
9575 }
9576
9577 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9578 {
9579 struct drm_i915_private *dev_priv = dev->dev_private;
9580 uint32_t val, data;
9581 int ret;
9582
9583 if (WARN((I915_READ(LCPLL_CTL) &
9584 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9585 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9586 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9587 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9588 "trying to change cdclk frequency with cdclk not enabled\n"))
9589 return;
9590
9591 mutex_lock(&dev_priv->rps.hw_lock);
9592 ret = sandybridge_pcode_write(dev_priv,
9593 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9594 mutex_unlock(&dev_priv->rps.hw_lock);
9595 if (ret) {
9596 DRM_ERROR("failed to inform pcode about cdclk change\n");
9597 return;
9598 }
9599
9600 val = I915_READ(LCPLL_CTL);
9601 val |= LCPLL_CD_SOURCE_FCLK;
9602 I915_WRITE(LCPLL_CTL, val);
9603
9604 if (wait_for_us(I915_READ(LCPLL_CTL) &
9605 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9606 DRM_ERROR("Switching to FCLK failed\n");
9607
9608 val = I915_READ(LCPLL_CTL);
9609 val &= ~LCPLL_CLK_FREQ_MASK;
9610
9611 switch (cdclk) {
9612 case 450000:
9613 val |= LCPLL_CLK_FREQ_450;
9614 data = 0;
9615 break;
9616 case 540000:
9617 val |= LCPLL_CLK_FREQ_54O_BDW;
9618 data = 1;
9619 break;
9620 case 337500:
9621 val |= LCPLL_CLK_FREQ_337_5_BDW;
9622 data = 2;
9623 break;
9624 case 675000:
9625 val |= LCPLL_CLK_FREQ_675_BDW;
9626 data = 3;
9627 break;
9628 default:
9629 WARN(1, "invalid cdclk frequency\n");
9630 return;
9631 }
9632
9633 I915_WRITE(LCPLL_CTL, val);
9634
9635 val = I915_READ(LCPLL_CTL);
9636 val &= ~LCPLL_CD_SOURCE_FCLK;
9637 I915_WRITE(LCPLL_CTL, val);
9638
9639 if (wait_for_us((I915_READ(LCPLL_CTL) &
9640 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9641 DRM_ERROR("Switching back to LCPLL failed\n");
9642
9643 mutex_lock(&dev_priv->rps.hw_lock);
9644 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9645 mutex_unlock(&dev_priv->rps.hw_lock);
9646
9647 intel_update_cdclk(dev);
9648
9649 WARN(cdclk != dev_priv->cdclk_freq,
9650 "cdclk requested %d kHz but got %d kHz\n",
9651 cdclk, dev_priv->cdclk_freq);
9652 }
9653
9654 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9655 {
9656 struct drm_i915_private *dev_priv = to_i915(state->dev);
9657 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9658 int max_pixclk = ilk_max_pixel_rate(state);
9659 int cdclk;
9660
9661 /*
9662 * FIXME should also account for plane ratio
9663 * once 64bpp pixel formats are supported.
9664 */
9665 if (max_pixclk > 540000)
9666 cdclk = 675000;
9667 else if (max_pixclk > 450000)
9668 cdclk = 540000;
9669 else if (max_pixclk > 337500)
9670 cdclk = 450000;
9671 else
9672 cdclk = 337500;
9673
9674 if (cdclk > dev_priv->max_cdclk_freq) {
9675 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9676 cdclk, dev_priv->max_cdclk_freq);
9677 return -EINVAL;
9678 }
9679
9680 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9681 if (!intel_state->active_crtcs)
9682 intel_state->dev_cdclk = 337500;
9683
9684 return 0;
9685 }
9686
9687 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9688 {
9689 struct drm_device *dev = old_state->dev;
9690 struct intel_atomic_state *old_intel_state =
9691 to_intel_atomic_state(old_state);
9692 unsigned req_cdclk = old_intel_state->dev_cdclk;
9693
9694 broadwell_set_cdclk(dev, req_cdclk);
9695 }
9696
9697 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9698 struct intel_crtc_state *crtc_state)
9699 {
9700 struct intel_encoder *intel_encoder =
9701 intel_ddi_get_crtc_new_encoder(crtc_state);
9702
9703 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9704 if (!intel_ddi_pll_select(crtc, crtc_state))
9705 return -EINVAL;
9706 }
9707
9708 crtc->lowfreq_avail = false;
9709
9710 return 0;
9711 }
9712
9713 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9714 enum port port,
9715 struct intel_crtc_state *pipe_config)
9716 {
9717 enum intel_dpll_id id;
9718
9719 switch (port) {
9720 case PORT_A:
9721 pipe_config->ddi_pll_sel = SKL_DPLL0;
9722 id = DPLL_ID_SKL_DPLL0;
9723 break;
9724 case PORT_B:
9725 pipe_config->ddi_pll_sel = SKL_DPLL1;
9726 id = DPLL_ID_SKL_DPLL1;
9727 break;
9728 case PORT_C:
9729 pipe_config->ddi_pll_sel = SKL_DPLL2;
9730 id = DPLL_ID_SKL_DPLL2;
9731 break;
9732 default:
9733 DRM_ERROR("Incorrect port type\n");
9734 return;
9735 }
9736
9737 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9738 }
9739
9740 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9741 enum port port,
9742 struct intel_crtc_state *pipe_config)
9743 {
9744 enum intel_dpll_id id;
9745 u32 temp;
9746
9747 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9748 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9749
9750 switch (pipe_config->ddi_pll_sel) {
9751 case SKL_DPLL0:
9752 id = DPLL_ID_SKL_DPLL0;
9753 break;
9754 case SKL_DPLL1:
9755 id = DPLL_ID_SKL_DPLL1;
9756 break;
9757 case SKL_DPLL2:
9758 id = DPLL_ID_SKL_DPLL2;
9759 break;
9760 case SKL_DPLL3:
9761 id = DPLL_ID_SKL_DPLL3;
9762 break;
9763 default:
9764 MISSING_CASE(pipe_config->ddi_pll_sel);
9765 return;
9766 }
9767
9768 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9769 }
9770
9771 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9772 enum port port,
9773 struct intel_crtc_state *pipe_config)
9774 {
9775 enum intel_dpll_id id;
9776
9777 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9778
9779 switch (pipe_config->ddi_pll_sel) {
9780 case PORT_CLK_SEL_WRPLL1:
9781 id = DPLL_ID_WRPLL1;
9782 break;
9783 case PORT_CLK_SEL_WRPLL2:
9784 id = DPLL_ID_WRPLL2;
9785 break;
9786 case PORT_CLK_SEL_SPLL:
9787 id = DPLL_ID_SPLL;
9788 break;
9789 case PORT_CLK_SEL_LCPLL_810:
9790 id = DPLL_ID_LCPLL_810;
9791 break;
9792 case PORT_CLK_SEL_LCPLL_1350:
9793 id = DPLL_ID_LCPLL_1350;
9794 break;
9795 case PORT_CLK_SEL_LCPLL_2700:
9796 id = DPLL_ID_LCPLL_2700;
9797 break;
9798 default:
9799 MISSING_CASE(pipe_config->ddi_pll_sel);
9800 /* fall through */
9801 case PORT_CLK_SEL_NONE:
9802 return;
9803 }
9804
9805 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9806 }
9807
9808 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9809 struct intel_crtc_state *pipe_config,
9810 unsigned long *power_domain_mask)
9811 {
9812 struct drm_device *dev = crtc->base.dev;
9813 struct drm_i915_private *dev_priv = dev->dev_private;
9814 enum intel_display_power_domain power_domain;
9815 u32 tmp;
9816
9817 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9818
9819 /*
9820 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9821 * consistency and less surprising code; it's in always on power).
9822 */
9823 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9824 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9825 enum pipe trans_edp_pipe;
9826 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9827 default:
9828 WARN(1, "unknown pipe linked to edp transcoder\n");
9829 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9830 case TRANS_DDI_EDP_INPUT_A_ON:
9831 trans_edp_pipe = PIPE_A;
9832 break;
9833 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9834 trans_edp_pipe = PIPE_B;
9835 break;
9836 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9837 trans_edp_pipe = PIPE_C;
9838 break;
9839 }
9840
9841 if (trans_edp_pipe == crtc->pipe)
9842 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9843 }
9844
9845 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9846 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9847 return false;
9848 *power_domain_mask |= BIT(power_domain);
9849
9850 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9851
9852 return tmp & PIPECONF_ENABLE;
9853 }
9854
9855 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9856 struct intel_crtc_state *pipe_config,
9857 unsigned long *power_domain_mask)
9858 {
9859 struct drm_device *dev = crtc->base.dev;
9860 struct drm_i915_private *dev_priv = dev->dev_private;
9861 enum intel_display_power_domain power_domain;
9862 enum port port;
9863 enum transcoder cpu_transcoder;
9864 u32 tmp;
9865
9866 pipe_config->has_dsi_encoder = false;
9867
9868 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9869 if (port == PORT_A)
9870 cpu_transcoder = TRANSCODER_DSI_A;
9871 else
9872 cpu_transcoder = TRANSCODER_DSI_C;
9873
9874 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9875 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9876 continue;
9877 *power_domain_mask |= BIT(power_domain);
9878
9879 /*
9880 * The PLL needs to be enabled with a valid divider
9881 * configuration, otherwise accessing DSI registers will hang
9882 * the machine. See BSpec North Display Engine
9883 * registers/MIPI[BXT]. We can break out here early, since we
9884 * need the same DSI PLL to be enabled for both DSI ports.
9885 */
9886 if (!intel_dsi_pll_is_enabled(dev_priv))
9887 break;
9888
9889 /* XXX: this works for video mode only */
9890 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9891 if (!(tmp & DPI_ENABLE))
9892 continue;
9893
9894 tmp = I915_READ(MIPI_CTRL(port));
9895 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9896 continue;
9897
9898 pipe_config->cpu_transcoder = cpu_transcoder;
9899 pipe_config->has_dsi_encoder = true;
9900 break;
9901 }
9902
9903 return pipe_config->has_dsi_encoder;
9904 }
9905
9906 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9907 struct intel_crtc_state *pipe_config)
9908 {
9909 struct drm_device *dev = crtc->base.dev;
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911 struct intel_shared_dpll *pll;
9912 enum port port;
9913 uint32_t tmp;
9914
9915 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9916
9917 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9918
9919 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9920 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9921 else if (IS_BROXTON(dev))
9922 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9923 else
9924 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9925
9926 pll = pipe_config->shared_dpll;
9927 if (pll) {
9928 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9929 &pipe_config->dpll_hw_state));
9930 }
9931
9932 /*
9933 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9934 * DDI E. So just check whether this pipe is wired to DDI E and whether
9935 * the PCH transcoder is on.
9936 */
9937 if (INTEL_INFO(dev)->gen < 9 &&
9938 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9939 pipe_config->has_pch_encoder = true;
9940
9941 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9942 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9943 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9944
9945 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9946 }
9947 }
9948
9949 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9950 struct intel_crtc_state *pipe_config)
9951 {
9952 struct drm_device *dev = crtc->base.dev;
9953 struct drm_i915_private *dev_priv = dev->dev_private;
9954 enum intel_display_power_domain power_domain;
9955 unsigned long power_domain_mask;
9956 bool active;
9957
9958 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9959 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9960 return false;
9961 power_domain_mask = BIT(power_domain);
9962
9963 pipe_config->shared_dpll = NULL;
9964
9965 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9966
9967 if (IS_BROXTON(dev_priv)) {
9968 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9969 &power_domain_mask);
9970 WARN_ON(active && pipe_config->has_dsi_encoder);
9971 if (pipe_config->has_dsi_encoder)
9972 active = true;
9973 }
9974
9975 if (!active)
9976 goto out;
9977
9978 if (!pipe_config->has_dsi_encoder) {
9979 haswell_get_ddi_port_state(crtc, pipe_config);
9980 intel_get_pipe_timings(crtc, pipe_config);
9981 }
9982
9983 intel_get_pipe_src_size(crtc, pipe_config);
9984
9985 pipe_config->gamma_mode =
9986 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9987
9988 if (INTEL_INFO(dev)->gen >= 9) {
9989 skl_init_scalers(dev, crtc, pipe_config);
9990 }
9991
9992 if (INTEL_INFO(dev)->gen >= 9) {
9993 pipe_config->scaler_state.scaler_id = -1;
9994 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9995 }
9996
9997 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9998 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9999 power_domain_mask |= BIT(power_domain);
10000 if (INTEL_INFO(dev)->gen >= 9)
10001 skylake_get_pfit_config(crtc, pipe_config);
10002 else
10003 ironlake_get_pfit_config(crtc, pipe_config);
10004 }
10005
10006 if (IS_HASWELL(dev))
10007 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10008 (I915_READ(IPS_CTL) & IPS_ENABLE);
10009
10010 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10011 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10012 pipe_config->pixel_multiplier =
10013 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10014 } else {
10015 pipe_config->pixel_multiplier = 1;
10016 }
10017
10018 out:
10019 for_each_power_domain(power_domain, power_domain_mask)
10020 intel_display_power_put(dev_priv, power_domain);
10021
10022 return active;
10023 }
10024
10025 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10026 const struct intel_plane_state *plane_state)
10027 {
10028 struct drm_device *dev = crtc->dev;
10029 struct drm_i915_private *dev_priv = dev->dev_private;
10030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10031 uint32_t cntl = 0, size = 0;
10032
10033 if (plane_state && plane_state->visible) {
10034 unsigned int width = plane_state->base.crtc_w;
10035 unsigned int height = plane_state->base.crtc_h;
10036 unsigned int stride = roundup_pow_of_two(width) * 4;
10037
10038 switch (stride) {
10039 default:
10040 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10041 width, stride);
10042 stride = 256;
10043 /* fallthrough */
10044 case 256:
10045 case 512:
10046 case 1024:
10047 case 2048:
10048 break;
10049 }
10050
10051 cntl |= CURSOR_ENABLE |
10052 CURSOR_GAMMA_ENABLE |
10053 CURSOR_FORMAT_ARGB |
10054 CURSOR_STRIDE(stride);
10055
10056 size = (height << 12) | width;
10057 }
10058
10059 if (intel_crtc->cursor_cntl != 0 &&
10060 (intel_crtc->cursor_base != base ||
10061 intel_crtc->cursor_size != size ||
10062 intel_crtc->cursor_cntl != cntl)) {
10063 /* On these chipsets we can only modify the base/size/stride
10064 * whilst the cursor is disabled.
10065 */
10066 I915_WRITE(CURCNTR(PIPE_A), 0);
10067 POSTING_READ(CURCNTR(PIPE_A));
10068 intel_crtc->cursor_cntl = 0;
10069 }
10070
10071 if (intel_crtc->cursor_base != base) {
10072 I915_WRITE(CURBASE(PIPE_A), base);
10073 intel_crtc->cursor_base = base;
10074 }
10075
10076 if (intel_crtc->cursor_size != size) {
10077 I915_WRITE(CURSIZE, size);
10078 intel_crtc->cursor_size = size;
10079 }
10080
10081 if (intel_crtc->cursor_cntl != cntl) {
10082 I915_WRITE(CURCNTR(PIPE_A), cntl);
10083 POSTING_READ(CURCNTR(PIPE_A));
10084 intel_crtc->cursor_cntl = cntl;
10085 }
10086 }
10087
10088 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10089 const struct intel_plane_state *plane_state)
10090 {
10091 struct drm_device *dev = crtc->dev;
10092 struct drm_i915_private *dev_priv = dev->dev_private;
10093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10094 int pipe = intel_crtc->pipe;
10095 uint32_t cntl = 0;
10096
10097 if (plane_state && plane_state->visible) {
10098 cntl = MCURSOR_GAMMA_ENABLE;
10099 switch (plane_state->base.crtc_w) {
10100 case 64:
10101 cntl |= CURSOR_MODE_64_ARGB_AX;
10102 break;
10103 case 128:
10104 cntl |= CURSOR_MODE_128_ARGB_AX;
10105 break;
10106 case 256:
10107 cntl |= CURSOR_MODE_256_ARGB_AX;
10108 break;
10109 default:
10110 MISSING_CASE(plane_state->base.crtc_w);
10111 return;
10112 }
10113 cntl |= pipe << 28; /* Connect to correct pipe */
10114
10115 if (HAS_DDI(dev))
10116 cntl |= CURSOR_PIPE_CSC_ENABLE;
10117
10118 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10119 cntl |= CURSOR_ROTATE_180;
10120 }
10121
10122 if (intel_crtc->cursor_cntl != cntl) {
10123 I915_WRITE(CURCNTR(pipe), cntl);
10124 POSTING_READ(CURCNTR(pipe));
10125 intel_crtc->cursor_cntl = cntl;
10126 }
10127
10128 /* and commit changes on next vblank */
10129 I915_WRITE(CURBASE(pipe), base);
10130 POSTING_READ(CURBASE(pipe));
10131
10132 intel_crtc->cursor_base = base;
10133 }
10134
10135 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10136 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10137 const struct intel_plane_state *plane_state)
10138 {
10139 struct drm_device *dev = crtc->dev;
10140 struct drm_i915_private *dev_priv = dev->dev_private;
10141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10142 int pipe = intel_crtc->pipe;
10143 u32 base = intel_crtc->cursor_addr;
10144 u32 pos = 0;
10145
10146 if (plane_state) {
10147 int x = plane_state->base.crtc_x;
10148 int y = plane_state->base.crtc_y;
10149
10150 if (x < 0) {
10151 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10152 x = -x;
10153 }
10154 pos |= x << CURSOR_X_SHIFT;
10155
10156 if (y < 0) {
10157 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10158 y = -y;
10159 }
10160 pos |= y << CURSOR_Y_SHIFT;
10161
10162 /* ILK+ do this automagically */
10163 if (HAS_GMCH_DISPLAY(dev) &&
10164 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10165 base += (plane_state->base.crtc_h *
10166 plane_state->base.crtc_w - 1) * 4;
10167 }
10168 }
10169
10170 I915_WRITE(CURPOS(pipe), pos);
10171
10172 if (IS_845G(dev) || IS_I865G(dev))
10173 i845_update_cursor(crtc, base, plane_state);
10174 else
10175 i9xx_update_cursor(crtc, base, plane_state);
10176 }
10177
10178 static bool cursor_size_ok(struct drm_device *dev,
10179 uint32_t width, uint32_t height)
10180 {
10181 if (width == 0 || height == 0)
10182 return false;
10183
10184 /*
10185 * 845g/865g are special in that they are only limited by
10186 * the width of their cursors, the height is arbitrary up to
10187 * the precision of the register. Everything else requires
10188 * square cursors, limited to a few power-of-two sizes.
10189 */
10190 if (IS_845G(dev) || IS_I865G(dev)) {
10191 if ((width & 63) != 0)
10192 return false;
10193
10194 if (width > (IS_845G(dev) ? 64 : 512))
10195 return false;
10196
10197 if (height > 1023)
10198 return false;
10199 } else {
10200 switch (width | height) {
10201 case 256:
10202 case 128:
10203 if (IS_GEN2(dev))
10204 return false;
10205 case 64:
10206 break;
10207 default:
10208 return false;
10209 }
10210 }
10211
10212 return true;
10213 }
10214
10215 /* VESA 640x480x72Hz mode to set on the pipe */
10216 static struct drm_display_mode load_detect_mode = {
10217 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10218 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10219 };
10220
10221 struct drm_framebuffer *
10222 __intel_framebuffer_create(struct drm_device *dev,
10223 struct drm_mode_fb_cmd2 *mode_cmd,
10224 struct drm_i915_gem_object *obj)
10225 {
10226 struct intel_framebuffer *intel_fb;
10227 int ret;
10228
10229 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10230 if (!intel_fb)
10231 return ERR_PTR(-ENOMEM);
10232
10233 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10234 if (ret)
10235 goto err;
10236
10237 return &intel_fb->base;
10238
10239 err:
10240 kfree(intel_fb);
10241 return ERR_PTR(ret);
10242 }
10243
10244 static struct drm_framebuffer *
10245 intel_framebuffer_create(struct drm_device *dev,
10246 struct drm_mode_fb_cmd2 *mode_cmd,
10247 struct drm_i915_gem_object *obj)
10248 {
10249 struct drm_framebuffer *fb;
10250 int ret;
10251
10252 ret = i915_mutex_lock_interruptible(dev);
10253 if (ret)
10254 return ERR_PTR(ret);
10255 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10256 mutex_unlock(&dev->struct_mutex);
10257
10258 return fb;
10259 }
10260
10261 static u32
10262 intel_framebuffer_pitch_for_width(int width, int bpp)
10263 {
10264 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10265 return ALIGN(pitch, 64);
10266 }
10267
10268 static u32
10269 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10270 {
10271 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10272 return PAGE_ALIGN(pitch * mode->vdisplay);
10273 }
10274
10275 static struct drm_framebuffer *
10276 intel_framebuffer_create_for_mode(struct drm_device *dev,
10277 struct drm_display_mode *mode,
10278 int depth, int bpp)
10279 {
10280 struct drm_framebuffer *fb;
10281 struct drm_i915_gem_object *obj;
10282 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10283
10284 obj = i915_gem_alloc_object(dev,
10285 intel_framebuffer_size_for_mode(mode, bpp));
10286 if (obj == NULL)
10287 return ERR_PTR(-ENOMEM);
10288
10289 mode_cmd.width = mode->hdisplay;
10290 mode_cmd.height = mode->vdisplay;
10291 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10292 bpp);
10293 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10294
10295 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10296 if (IS_ERR(fb))
10297 drm_gem_object_unreference_unlocked(&obj->base);
10298
10299 return fb;
10300 }
10301
10302 static struct drm_framebuffer *
10303 mode_fits_in_fbdev(struct drm_device *dev,
10304 struct drm_display_mode *mode)
10305 {
10306 #ifdef CONFIG_DRM_FBDEV_EMULATION
10307 struct drm_i915_private *dev_priv = dev->dev_private;
10308 struct drm_i915_gem_object *obj;
10309 struct drm_framebuffer *fb;
10310
10311 if (!dev_priv->fbdev)
10312 return NULL;
10313
10314 if (!dev_priv->fbdev->fb)
10315 return NULL;
10316
10317 obj = dev_priv->fbdev->fb->obj;
10318 BUG_ON(!obj);
10319
10320 fb = &dev_priv->fbdev->fb->base;
10321 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10322 fb->bits_per_pixel))
10323 return NULL;
10324
10325 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10326 return NULL;
10327
10328 drm_framebuffer_reference(fb);
10329 return fb;
10330 #else
10331 return NULL;
10332 #endif
10333 }
10334
10335 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10336 struct drm_crtc *crtc,
10337 struct drm_display_mode *mode,
10338 struct drm_framebuffer *fb,
10339 int x, int y)
10340 {
10341 struct drm_plane_state *plane_state;
10342 int hdisplay, vdisplay;
10343 int ret;
10344
10345 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10346 if (IS_ERR(plane_state))
10347 return PTR_ERR(plane_state);
10348
10349 if (mode)
10350 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10351 else
10352 hdisplay = vdisplay = 0;
10353
10354 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10355 if (ret)
10356 return ret;
10357 drm_atomic_set_fb_for_plane(plane_state, fb);
10358 plane_state->crtc_x = 0;
10359 plane_state->crtc_y = 0;
10360 plane_state->crtc_w = hdisplay;
10361 plane_state->crtc_h = vdisplay;
10362 plane_state->src_x = x << 16;
10363 plane_state->src_y = y << 16;
10364 plane_state->src_w = hdisplay << 16;
10365 plane_state->src_h = vdisplay << 16;
10366
10367 return 0;
10368 }
10369
10370 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10371 struct drm_display_mode *mode,
10372 struct intel_load_detect_pipe *old,
10373 struct drm_modeset_acquire_ctx *ctx)
10374 {
10375 struct intel_crtc *intel_crtc;
10376 struct intel_encoder *intel_encoder =
10377 intel_attached_encoder(connector);
10378 struct drm_crtc *possible_crtc;
10379 struct drm_encoder *encoder = &intel_encoder->base;
10380 struct drm_crtc *crtc = NULL;
10381 struct drm_device *dev = encoder->dev;
10382 struct drm_framebuffer *fb;
10383 struct drm_mode_config *config = &dev->mode_config;
10384 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10385 struct drm_connector_state *connector_state;
10386 struct intel_crtc_state *crtc_state;
10387 int ret, i = -1;
10388
10389 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10390 connector->base.id, connector->name,
10391 encoder->base.id, encoder->name);
10392
10393 old->restore_state = NULL;
10394
10395 retry:
10396 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10397 if (ret)
10398 goto fail;
10399
10400 /*
10401 * Algorithm gets a little messy:
10402 *
10403 * - if the connector already has an assigned crtc, use it (but make
10404 * sure it's on first)
10405 *
10406 * - try to find the first unused crtc that can drive this connector,
10407 * and use that if we find one
10408 */
10409
10410 /* See if we already have a CRTC for this connector */
10411 if (connector->state->crtc) {
10412 crtc = connector->state->crtc;
10413
10414 ret = drm_modeset_lock(&crtc->mutex, ctx);
10415 if (ret)
10416 goto fail;
10417
10418 /* Make sure the crtc and connector are running */
10419 goto found;
10420 }
10421
10422 /* Find an unused one (if possible) */
10423 for_each_crtc(dev, possible_crtc) {
10424 i++;
10425 if (!(encoder->possible_crtcs & (1 << i)))
10426 continue;
10427
10428 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10429 if (ret)
10430 goto fail;
10431
10432 if (possible_crtc->state->enable) {
10433 drm_modeset_unlock(&possible_crtc->mutex);
10434 continue;
10435 }
10436
10437 crtc = possible_crtc;
10438 break;
10439 }
10440
10441 /*
10442 * If we didn't find an unused CRTC, don't use any.
10443 */
10444 if (!crtc) {
10445 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10446 goto fail;
10447 }
10448
10449 found:
10450 intel_crtc = to_intel_crtc(crtc);
10451
10452 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10453 if (ret)
10454 goto fail;
10455
10456 state = drm_atomic_state_alloc(dev);
10457 restore_state = drm_atomic_state_alloc(dev);
10458 if (!state || !restore_state) {
10459 ret = -ENOMEM;
10460 goto fail;
10461 }
10462
10463 state->acquire_ctx = ctx;
10464 restore_state->acquire_ctx = ctx;
10465
10466 connector_state = drm_atomic_get_connector_state(state, connector);
10467 if (IS_ERR(connector_state)) {
10468 ret = PTR_ERR(connector_state);
10469 goto fail;
10470 }
10471
10472 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10473 if (ret)
10474 goto fail;
10475
10476 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10477 if (IS_ERR(crtc_state)) {
10478 ret = PTR_ERR(crtc_state);
10479 goto fail;
10480 }
10481
10482 crtc_state->base.active = crtc_state->base.enable = true;
10483
10484 if (!mode)
10485 mode = &load_detect_mode;
10486
10487 /* We need a framebuffer large enough to accommodate all accesses
10488 * that the plane may generate whilst we perform load detection.
10489 * We can not rely on the fbcon either being present (we get called
10490 * during its initialisation to detect all boot displays, or it may
10491 * not even exist) or that it is large enough to satisfy the
10492 * requested mode.
10493 */
10494 fb = mode_fits_in_fbdev(dev, mode);
10495 if (fb == NULL) {
10496 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10497 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10498 } else
10499 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10500 if (IS_ERR(fb)) {
10501 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10502 goto fail;
10503 }
10504
10505 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10506 if (ret)
10507 goto fail;
10508
10509 drm_framebuffer_unreference(fb);
10510
10511 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10512 if (ret)
10513 goto fail;
10514
10515 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10516 if (!ret)
10517 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10518 if (!ret)
10519 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10520 if (ret) {
10521 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10522 goto fail;
10523 }
10524
10525 ret = drm_atomic_commit(state);
10526 if (ret) {
10527 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10528 goto fail;
10529 }
10530
10531 old->restore_state = restore_state;
10532
10533 /* let the connector get through one full cycle before testing */
10534 intel_wait_for_vblank(dev, intel_crtc->pipe);
10535 return true;
10536
10537 fail:
10538 drm_atomic_state_free(state);
10539 drm_atomic_state_free(restore_state);
10540 restore_state = state = NULL;
10541
10542 if (ret == -EDEADLK) {
10543 drm_modeset_backoff(ctx);
10544 goto retry;
10545 }
10546
10547 return false;
10548 }
10549
10550 void intel_release_load_detect_pipe(struct drm_connector *connector,
10551 struct intel_load_detect_pipe *old,
10552 struct drm_modeset_acquire_ctx *ctx)
10553 {
10554 struct intel_encoder *intel_encoder =
10555 intel_attached_encoder(connector);
10556 struct drm_encoder *encoder = &intel_encoder->base;
10557 struct drm_atomic_state *state = old->restore_state;
10558 int ret;
10559
10560 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10561 connector->base.id, connector->name,
10562 encoder->base.id, encoder->name);
10563
10564 if (!state)
10565 return;
10566
10567 ret = drm_atomic_commit(state);
10568 if (ret) {
10569 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10570 drm_atomic_state_free(state);
10571 }
10572 }
10573
10574 static int i9xx_pll_refclk(struct drm_device *dev,
10575 const struct intel_crtc_state *pipe_config)
10576 {
10577 struct drm_i915_private *dev_priv = dev->dev_private;
10578 u32 dpll = pipe_config->dpll_hw_state.dpll;
10579
10580 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10581 return dev_priv->vbt.lvds_ssc_freq;
10582 else if (HAS_PCH_SPLIT(dev))
10583 return 120000;
10584 else if (!IS_GEN2(dev))
10585 return 96000;
10586 else
10587 return 48000;
10588 }
10589
10590 /* Returns the clock of the currently programmed mode of the given pipe. */
10591 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10592 struct intel_crtc_state *pipe_config)
10593 {
10594 struct drm_device *dev = crtc->base.dev;
10595 struct drm_i915_private *dev_priv = dev->dev_private;
10596 int pipe = pipe_config->cpu_transcoder;
10597 u32 dpll = pipe_config->dpll_hw_state.dpll;
10598 u32 fp;
10599 intel_clock_t clock;
10600 int port_clock;
10601 int refclk = i9xx_pll_refclk(dev, pipe_config);
10602
10603 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10604 fp = pipe_config->dpll_hw_state.fp0;
10605 else
10606 fp = pipe_config->dpll_hw_state.fp1;
10607
10608 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10609 if (IS_PINEVIEW(dev)) {
10610 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10611 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10612 } else {
10613 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10614 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10615 }
10616
10617 if (!IS_GEN2(dev)) {
10618 if (IS_PINEVIEW(dev))
10619 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10620 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10621 else
10622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10623 DPLL_FPA01_P1_POST_DIV_SHIFT);
10624
10625 switch (dpll & DPLL_MODE_MASK) {
10626 case DPLLB_MODE_DAC_SERIAL:
10627 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10628 5 : 10;
10629 break;
10630 case DPLLB_MODE_LVDS:
10631 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10632 7 : 14;
10633 break;
10634 default:
10635 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10636 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10637 return;
10638 }
10639
10640 if (IS_PINEVIEW(dev))
10641 port_clock = pnv_calc_dpll_params(refclk, &clock);
10642 else
10643 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10644 } else {
10645 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10646 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10647
10648 if (is_lvds) {
10649 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10650 DPLL_FPA01_P1_POST_DIV_SHIFT);
10651
10652 if (lvds & LVDS_CLKB_POWER_UP)
10653 clock.p2 = 7;
10654 else
10655 clock.p2 = 14;
10656 } else {
10657 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10658 clock.p1 = 2;
10659 else {
10660 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10661 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10662 }
10663 if (dpll & PLL_P2_DIVIDE_BY_4)
10664 clock.p2 = 4;
10665 else
10666 clock.p2 = 2;
10667 }
10668
10669 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10670 }
10671
10672 /*
10673 * This value includes pixel_multiplier. We will use
10674 * port_clock to compute adjusted_mode.crtc_clock in the
10675 * encoder's get_config() function.
10676 */
10677 pipe_config->port_clock = port_clock;
10678 }
10679
10680 int intel_dotclock_calculate(int link_freq,
10681 const struct intel_link_m_n *m_n)
10682 {
10683 /*
10684 * The calculation for the data clock is:
10685 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10686 * But we want to avoid losing precison if possible, so:
10687 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10688 *
10689 * and the link clock is simpler:
10690 * link_clock = (m * link_clock) / n
10691 */
10692
10693 if (!m_n->link_n)
10694 return 0;
10695
10696 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10697 }
10698
10699 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10700 struct intel_crtc_state *pipe_config)
10701 {
10702 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10703
10704 /* read out port_clock from the DPLL */
10705 i9xx_crtc_clock_get(crtc, pipe_config);
10706
10707 /*
10708 * In case there is an active pipe without active ports,
10709 * we may need some idea for the dotclock anyway.
10710 * Calculate one based on the FDI configuration.
10711 */
10712 pipe_config->base.adjusted_mode.crtc_clock =
10713 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10714 &pipe_config->fdi_m_n);
10715 }
10716
10717 /** Returns the currently programmed mode of the given pipe. */
10718 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10719 struct drm_crtc *crtc)
10720 {
10721 struct drm_i915_private *dev_priv = dev->dev_private;
10722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10723 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10724 struct drm_display_mode *mode;
10725 struct intel_crtc_state *pipe_config;
10726 int htot = I915_READ(HTOTAL(cpu_transcoder));
10727 int hsync = I915_READ(HSYNC(cpu_transcoder));
10728 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10729 int vsync = I915_READ(VSYNC(cpu_transcoder));
10730 enum pipe pipe = intel_crtc->pipe;
10731
10732 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10733 if (!mode)
10734 return NULL;
10735
10736 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10737 if (!pipe_config) {
10738 kfree(mode);
10739 return NULL;
10740 }
10741
10742 /*
10743 * Construct a pipe_config sufficient for getting the clock info
10744 * back out of crtc_clock_get.
10745 *
10746 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10747 * to use a real value here instead.
10748 */
10749 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10750 pipe_config->pixel_multiplier = 1;
10751 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10752 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10753 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10754 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10755
10756 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10757 mode->hdisplay = (htot & 0xffff) + 1;
10758 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10759 mode->hsync_start = (hsync & 0xffff) + 1;
10760 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10761 mode->vdisplay = (vtot & 0xffff) + 1;
10762 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10763 mode->vsync_start = (vsync & 0xffff) + 1;
10764 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10765
10766 drm_mode_set_name(mode);
10767
10768 kfree(pipe_config);
10769
10770 return mode;
10771 }
10772
10773 void intel_mark_busy(struct drm_device *dev)
10774 {
10775 struct drm_i915_private *dev_priv = dev->dev_private;
10776
10777 if (dev_priv->mm.busy)
10778 return;
10779
10780 intel_runtime_pm_get(dev_priv);
10781 i915_update_gfx_val(dev_priv);
10782 if (INTEL_INFO(dev)->gen >= 6)
10783 gen6_rps_busy(dev_priv);
10784 dev_priv->mm.busy = true;
10785 }
10786
10787 void intel_mark_idle(struct drm_device *dev)
10788 {
10789 struct drm_i915_private *dev_priv = dev->dev_private;
10790
10791 if (!dev_priv->mm.busy)
10792 return;
10793
10794 dev_priv->mm.busy = false;
10795
10796 if (INTEL_INFO(dev)->gen >= 6)
10797 gen6_rps_idle(dev->dev_private);
10798
10799 intel_runtime_pm_put(dev_priv);
10800 }
10801
10802 static void intel_crtc_destroy(struct drm_crtc *crtc)
10803 {
10804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10805 struct drm_device *dev = crtc->dev;
10806 struct intel_unpin_work *work;
10807
10808 spin_lock_irq(&dev->event_lock);
10809 work = intel_crtc->unpin_work;
10810 intel_crtc->unpin_work = NULL;
10811 spin_unlock_irq(&dev->event_lock);
10812
10813 if (work) {
10814 cancel_work_sync(&work->work);
10815 kfree(work);
10816 }
10817
10818 drm_crtc_cleanup(crtc);
10819
10820 kfree(intel_crtc);
10821 }
10822
10823 static void intel_unpin_work_fn(struct work_struct *__work)
10824 {
10825 struct intel_unpin_work *work =
10826 container_of(__work, struct intel_unpin_work, work);
10827 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10828 struct drm_device *dev = crtc->base.dev;
10829 struct drm_plane *primary = crtc->base.primary;
10830
10831 mutex_lock(&dev->struct_mutex);
10832 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10833 drm_gem_object_unreference(&work->pending_flip_obj->base);
10834
10835 if (work->flip_queued_req)
10836 i915_gem_request_assign(&work->flip_queued_req, NULL);
10837 mutex_unlock(&dev->struct_mutex);
10838
10839 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10840 intel_fbc_post_update(crtc);
10841 drm_framebuffer_unreference(work->old_fb);
10842
10843 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10844 atomic_dec(&crtc->unpin_work_count);
10845
10846 kfree(work);
10847 }
10848
10849 static void do_intel_finish_page_flip(struct drm_device *dev,
10850 struct drm_crtc *crtc)
10851 {
10852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10853 struct intel_unpin_work *work;
10854 unsigned long flags;
10855
10856 /* Ignore early vblank irqs */
10857 if (intel_crtc == NULL)
10858 return;
10859
10860 /*
10861 * This is called both by irq handlers and the reset code (to complete
10862 * lost pageflips) so needs the full irqsave spinlocks.
10863 */
10864 spin_lock_irqsave(&dev->event_lock, flags);
10865 work = intel_crtc->unpin_work;
10866
10867 /* Ensure we don't miss a work->pending update ... */
10868 smp_rmb();
10869
10870 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10871 spin_unlock_irqrestore(&dev->event_lock, flags);
10872 return;
10873 }
10874
10875 page_flip_completed(intel_crtc);
10876
10877 spin_unlock_irqrestore(&dev->event_lock, flags);
10878 }
10879
10880 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10881 {
10882 struct drm_i915_private *dev_priv = dev->dev_private;
10883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10884
10885 do_intel_finish_page_flip(dev, crtc);
10886 }
10887
10888 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10889 {
10890 struct drm_i915_private *dev_priv = dev->dev_private;
10891 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10892
10893 do_intel_finish_page_flip(dev, crtc);
10894 }
10895
10896 /* Is 'a' after or equal to 'b'? */
10897 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10898 {
10899 return !((a - b) & 0x80000000);
10900 }
10901
10902 static bool page_flip_finished(struct intel_crtc *crtc)
10903 {
10904 struct drm_device *dev = crtc->base.dev;
10905 struct drm_i915_private *dev_priv = dev->dev_private;
10906
10907 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10908 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10909 return true;
10910
10911 /*
10912 * The relevant registers doen't exist on pre-ctg.
10913 * As the flip done interrupt doesn't trigger for mmio
10914 * flips on gmch platforms, a flip count check isn't
10915 * really needed there. But since ctg has the registers,
10916 * include it in the check anyway.
10917 */
10918 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10919 return true;
10920
10921 /*
10922 * BDW signals flip done immediately if the plane
10923 * is disabled, even if the plane enable is already
10924 * armed to occur at the next vblank :(
10925 */
10926
10927 /*
10928 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10929 * used the same base address. In that case the mmio flip might
10930 * have completed, but the CS hasn't even executed the flip yet.
10931 *
10932 * A flip count check isn't enough as the CS might have updated
10933 * the base address just after start of vblank, but before we
10934 * managed to process the interrupt. This means we'd complete the
10935 * CS flip too soon.
10936 *
10937 * Combining both checks should get us a good enough result. It may
10938 * still happen that the CS flip has been executed, but has not
10939 * yet actually completed. But in case the base address is the same
10940 * anyway, we don't really care.
10941 */
10942 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10943 crtc->unpin_work->gtt_offset &&
10944 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10945 crtc->unpin_work->flip_count);
10946 }
10947
10948 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10949 {
10950 struct drm_i915_private *dev_priv = dev->dev_private;
10951 struct intel_crtc *intel_crtc =
10952 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10953 unsigned long flags;
10954
10955
10956 /*
10957 * This is called both by irq handlers and the reset code (to complete
10958 * lost pageflips) so needs the full irqsave spinlocks.
10959 *
10960 * NB: An MMIO update of the plane base pointer will also
10961 * generate a page-flip completion irq, i.e. every modeset
10962 * is also accompanied by a spurious intel_prepare_page_flip().
10963 */
10964 spin_lock_irqsave(&dev->event_lock, flags);
10965 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10966 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10967 spin_unlock_irqrestore(&dev->event_lock, flags);
10968 }
10969
10970 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10971 {
10972 /* Ensure that the work item is consistent when activating it ... */
10973 smp_wmb();
10974 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10975 /* and that it is marked active as soon as the irq could fire. */
10976 smp_wmb();
10977 }
10978
10979 static int intel_gen2_queue_flip(struct drm_device *dev,
10980 struct drm_crtc *crtc,
10981 struct drm_framebuffer *fb,
10982 struct drm_i915_gem_object *obj,
10983 struct drm_i915_gem_request *req,
10984 uint32_t flags)
10985 {
10986 struct intel_engine_cs *engine = req->engine;
10987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10988 u32 flip_mask;
10989 int ret;
10990
10991 ret = intel_ring_begin(req, 6);
10992 if (ret)
10993 return ret;
10994
10995 /* Can't queue multiple flips, so wait for the previous
10996 * one to finish before executing the next.
10997 */
10998 if (intel_crtc->plane)
10999 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11000 else
11001 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11002 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11003 intel_ring_emit(engine, MI_NOOP);
11004 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11005 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11006 intel_ring_emit(engine, fb->pitches[0]);
11007 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11008 intel_ring_emit(engine, 0); /* aux display base address, unused */
11009
11010 intel_mark_page_flip_active(intel_crtc->unpin_work);
11011 return 0;
11012 }
11013
11014 static int intel_gen3_queue_flip(struct drm_device *dev,
11015 struct drm_crtc *crtc,
11016 struct drm_framebuffer *fb,
11017 struct drm_i915_gem_object *obj,
11018 struct drm_i915_gem_request *req,
11019 uint32_t flags)
11020 {
11021 struct intel_engine_cs *engine = req->engine;
11022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11023 u32 flip_mask;
11024 int ret;
11025
11026 ret = intel_ring_begin(req, 6);
11027 if (ret)
11028 return ret;
11029
11030 if (intel_crtc->plane)
11031 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11032 else
11033 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11034 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11035 intel_ring_emit(engine, MI_NOOP);
11036 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11037 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11038 intel_ring_emit(engine, fb->pitches[0]);
11039 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11040 intel_ring_emit(engine, MI_NOOP);
11041
11042 intel_mark_page_flip_active(intel_crtc->unpin_work);
11043 return 0;
11044 }
11045
11046 static int intel_gen4_queue_flip(struct drm_device *dev,
11047 struct drm_crtc *crtc,
11048 struct drm_framebuffer *fb,
11049 struct drm_i915_gem_object *obj,
11050 struct drm_i915_gem_request *req,
11051 uint32_t flags)
11052 {
11053 struct intel_engine_cs *engine = req->engine;
11054 struct drm_i915_private *dev_priv = dev->dev_private;
11055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11056 uint32_t pf, pipesrc;
11057 int ret;
11058
11059 ret = intel_ring_begin(req, 4);
11060 if (ret)
11061 return ret;
11062
11063 /* i965+ uses the linear or tiled offsets from the
11064 * Display Registers (which do not change across a page-flip)
11065 * so we need only reprogram the base address.
11066 */
11067 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11069 intel_ring_emit(engine, fb->pitches[0]);
11070 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11071 obj->tiling_mode);
11072
11073 /* XXX Enabling the panel-fitter across page-flip is so far
11074 * untested on non-native modes, so ignore it for now.
11075 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11076 */
11077 pf = 0;
11078 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11079 intel_ring_emit(engine, pf | pipesrc);
11080
11081 intel_mark_page_flip_active(intel_crtc->unpin_work);
11082 return 0;
11083 }
11084
11085 static int intel_gen6_queue_flip(struct drm_device *dev,
11086 struct drm_crtc *crtc,
11087 struct drm_framebuffer *fb,
11088 struct drm_i915_gem_object *obj,
11089 struct drm_i915_gem_request *req,
11090 uint32_t flags)
11091 {
11092 struct intel_engine_cs *engine = req->engine;
11093 struct drm_i915_private *dev_priv = dev->dev_private;
11094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11095 uint32_t pf, pipesrc;
11096 int ret;
11097
11098 ret = intel_ring_begin(req, 4);
11099 if (ret)
11100 return ret;
11101
11102 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11104 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11105 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11106
11107 /* Contrary to the suggestions in the documentation,
11108 * "Enable Panel Fitter" does not seem to be required when page
11109 * flipping with a non-native mode, and worse causes a normal
11110 * modeset to fail.
11111 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11112 */
11113 pf = 0;
11114 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11115 intel_ring_emit(engine, pf | pipesrc);
11116
11117 intel_mark_page_flip_active(intel_crtc->unpin_work);
11118 return 0;
11119 }
11120
11121 static int intel_gen7_queue_flip(struct drm_device *dev,
11122 struct drm_crtc *crtc,
11123 struct drm_framebuffer *fb,
11124 struct drm_i915_gem_object *obj,
11125 struct drm_i915_gem_request *req,
11126 uint32_t flags)
11127 {
11128 struct intel_engine_cs *engine = req->engine;
11129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11130 uint32_t plane_bit = 0;
11131 int len, ret;
11132
11133 switch (intel_crtc->plane) {
11134 case PLANE_A:
11135 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11136 break;
11137 case PLANE_B:
11138 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11139 break;
11140 case PLANE_C:
11141 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11142 break;
11143 default:
11144 WARN_ONCE(1, "unknown plane in flip command\n");
11145 return -ENODEV;
11146 }
11147
11148 len = 4;
11149 if (engine->id == RCS) {
11150 len += 6;
11151 /*
11152 * On Gen 8, SRM is now taking an extra dword to accommodate
11153 * 48bits addresses, and we need a NOOP for the batch size to
11154 * stay even.
11155 */
11156 if (IS_GEN8(dev))
11157 len += 2;
11158 }
11159
11160 /*
11161 * BSpec MI_DISPLAY_FLIP for IVB:
11162 * "The full packet must be contained within the same cache line."
11163 *
11164 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11165 * cacheline, if we ever start emitting more commands before
11166 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11167 * then do the cacheline alignment, and finally emit the
11168 * MI_DISPLAY_FLIP.
11169 */
11170 ret = intel_ring_cacheline_align(req);
11171 if (ret)
11172 return ret;
11173
11174 ret = intel_ring_begin(req, len);
11175 if (ret)
11176 return ret;
11177
11178 /* Unmask the flip-done completion message. Note that the bspec says that
11179 * we should do this for both the BCS and RCS, and that we must not unmask
11180 * more than one flip event at any time (or ensure that one flip message
11181 * can be sent by waiting for flip-done prior to queueing new flips).
11182 * Experimentation says that BCS works despite DERRMR masking all
11183 * flip-done completion events and that unmasking all planes at once
11184 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11185 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11186 */
11187 if (engine->id == RCS) {
11188 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11189 intel_ring_emit_reg(engine, DERRMR);
11190 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11191 DERRMR_PIPEB_PRI_FLIP_DONE |
11192 DERRMR_PIPEC_PRI_FLIP_DONE));
11193 if (IS_GEN8(dev))
11194 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11195 MI_SRM_LRM_GLOBAL_GTT);
11196 else
11197 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11198 MI_SRM_LRM_GLOBAL_GTT);
11199 intel_ring_emit_reg(engine, DERRMR);
11200 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11201 if (IS_GEN8(dev)) {
11202 intel_ring_emit(engine, 0);
11203 intel_ring_emit(engine, MI_NOOP);
11204 }
11205 }
11206
11207 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11208 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11209 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11210 intel_ring_emit(engine, (MI_NOOP));
11211
11212 intel_mark_page_flip_active(intel_crtc->unpin_work);
11213 return 0;
11214 }
11215
11216 static bool use_mmio_flip(struct intel_engine_cs *engine,
11217 struct drm_i915_gem_object *obj)
11218 {
11219 /*
11220 * This is not being used for older platforms, because
11221 * non-availability of flip done interrupt forces us to use
11222 * CS flips. Older platforms derive flip done using some clever
11223 * tricks involving the flip_pending status bits and vblank irqs.
11224 * So using MMIO flips there would disrupt this mechanism.
11225 */
11226
11227 if (engine == NULL)
11228 return true;
11229
11230 if (INTEL_INFO(engine->dev)->gen < 5)
11231 return false;
11232
11233 if (i915.use_mmio_flip < 0)
11234 return false;
11235 else if (i915.use_mmio_flip > 0)
11236 return true;
11237 else if (i915.enable_execlists)
11238 return true;
11239 else if (obj->base.dma_buf &&
11240 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11241 false))
11242 return true;
11243 else
11244 return engine != i915_gem_request_get_engine(obj->last_write_req);
11245 }
11246
11247 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11248 unsigned int rotation,
11249 struct intel_unpin_work *work)
11250 {
11251 struct drm_device *dev = intel_crtc->base.dev;
11252 struct drm_i915_private *dev_priv = dev->dev_private;
11253 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11254 const enum pipe pipe = intel_crtc->pipe;
11255 u32 ctl, stride, tile_height;
11256
11257 ctl = I915_READ(PLANE_CTL(pipe, 0));
11258 ctl &= ~PLANE_CTL_TILED_MASK;
11259 switch (fb->modifier[0]) {
11260 case DRM_FORMAT_MOD_NONE:
11261 break;
11262 case I915_FORMAT_MOD_X_TILED:
11263 ctl |= PLANE_CTL_TILED_X;
11264 break;
11265 case I915_FORMAT_MOD_Y_TILED:
11266 ctl |= PLANE_CTL_TILED_Y;
11267 break;
11268 case I915_FORMAT_MOD_Yf_TILED:
11269 ctl |= PLANE_CTL_TILED_YF;
11270 break;
11271 default:
11272 MISSING_CASE(fb->modifier[0]);
11273 }
11274
11275 /*
11276 * The stride is either expressed as a multiple of 64 bytes chunks for
11277 * linear buffers or in number of tiles for tiled buffers.
11278 */
11279 if (intel_rotation_90_or_270(rotation)) {
11280 /* stride = Surface height in tiles */
11281 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11282 stride = DIV_ROUND_UP(fb->height, tile_height);
11283 } else {
11284 stride = fb->pitches[0] /
11285 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11286 fb->pixel_format);
11287 }
11288
11289 /*
11290 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11291 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11292 */
11293 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11294 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11295
11296 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11297 POSTING_READ(PLANE_SURF(pipe, 0));
11298 }
11299
11300 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11301 struct intel_unpin_work *work)
11302 {
11303 struct drm_device *dev = intel_crtc->base.dev;
11304 struct drm_i915_private *dev_priv = dev->dev_private;
11305 struct intel_framebuffer *intel_fb =
11306 to_intel_framebuffer(intel_crtc->base.primary->fb);
11307 struct drm_i915_gem_object *obj = intel_fb->obj;
11308 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11309 u32 dspcntr;
11310
11311 dspcntr = I915_READ(reg);
11312
11313 if (obj->tiling_mode != I915_TILING_NONE)
11314 dspcntr |= DISPPLANE_TILED;
11315 else
11316 dspcntr &= ~DISPPLANE_TILED;
11317
11318 I915_WRITE(reg, dspcntr);
11319
11320 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11321 POSTING_READ(DSPSURF(intel_crtc->plane));
11322 }
11323
11324 /*
11325 * XXX: This is the temporary way to update the plane registers until we get
11326 * around to using the usual plane update functions for MMIO flips
11327 */
11328 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11329 {
11330 struct intel_crtc *crtc = mmio_flip->crtc;
11331 struct intel_unpin_work *work;
11332
11333 spin_lock_irq(&crtc->base.dev->event_lock);
11334 work = crtc->unpin_work;
11335 spin_unlock_irq(&crtc->base.dev->event_lock);
11336 if (work == NULL)
11337 return;
11338
11339 intel_mark_page_flip_active(work);
11340
11341 intel_pipe_update_start(crtc);
11342
11343 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11344 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11345 else
11346 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11347 ilk_do_mmio_flip(crtc, work);
11348
11349 intel_pipe_update_end(crtc);
11350 }
11351
11352 static void intel_mmio_flip_work_func(struct work_struct *work)
11353 {
11354 struct intel_mmio_flip *mmio_flip =
11355 container_of(work, struct intel_mmio_flip, work);
11356 struct intel_framebuffer *intel_fb =
11357 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11358 struct drm_i915_gem_object *obj = intel_fb->obj;
11359
11360 if (mmio_flip->req) {
11361 WARN_ON(__i915_wait_request(mmio_flip->req,
11362 mmio_flip->crtc->reset_counter,
11363 false, NULL,
11364 &mmio_flip->i915->rps.mmioflips));
11365 i915_gem_request_unreference__unlocked(mmio_flip->req);
11366 }
11367
11368 /* For framebuffer backed by dmabuf, wait for fence */
11369 if (obj->base.dma_buf)
11370 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11371 false, false,
11372 MAX_SCHEDULE_TIMEOUT) < 0);
11373
11374 intel_do_mmio_flip(mmio_flip);
11375 kfree(mmio_flip);
11376 }
11377
11378 static int intel_queue_mmio_flip(struct drm_device *dev,
11379 struct drm_crtc *crtc,
11380 struct drm_i915_gem_object *obj)
11381 {
11382 struct intel_mmio_flip *mmio_flip;
11383
11384 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11385 if (mmio_flip == NULL)
11386 return -ENOMEM;
11387
11388 mmio_flip->i915 = to_i915(dev);
11389 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11390 mmio_flip->crtc = to_intel_crtc(crtc);
11391 mmio_flip->rotation = crtc->primary->state->rotation;
11392
11393 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11394 schedule_work(&mmio_flip->work);
11395
11396 return 0;
11397 }
11398
11399 static int intel_default_queue_flip(struct drm_device *dev,
11400 struct drm_crtc *crtc,
11401 struct drm_framebuffer *fb,
11402 struct drm_i915_gem_object *obj,
11403 struct drm_i915_gem_request *req,
11404 uint32_t flags)
11405 {
11406 return -ENODEV;
11407 }
11408
11409 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11410 struct drm_crtc *crtc)
11411 {
11412 struct drm_i915_private *dev_priv = dev->dev_private;
11413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11414 struct intel_unpin_work *work = intel_crtc->unpin_work;
11415 u32 addr;
11416
11417 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11418 return true;
11419
11420 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11421 return false;
11422
11423 if (!work->enable_stall_check)
11424 return false;
11425
11426 if (work->flip_ready_vblank == 0) {
11427 if (work->flip_queued_req &&
11428 !i915_gem_request_completed(work->flip_queued_req, true))
11429 return false;
11430
11431 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11432 }
11433
11434 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11435 return false;
11436
11437 /* Potential stall - if we see that the flip has happened,
11438 * assume a missed interrupt. */
11439 if (INTEL_INFO(dev)->gen >= 4)
11440 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11441 else
11442 addr = I915_READ(DSPADDR(intel_crtc->plane));
11443
11444 /* There is a potential issue here with a false positive after a flip
11445 * to the same address. We could address this by checking for a
11446 * non-incrementing frame counter.
11447 */
11448 return addr == work->gtt_offset;
11449 }
11450
11451 void intel_check_page_flip(struct drm_device *dev, int pipe)
11452 {
11453 struct drm_i915_private *dev_priv = dev->dev_private;
11454 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11456 struct intel_unpin_work *work;
11457
11458 WARN_ON(!in_interrupt());
11459
11460 if (crtc == NULL)
11461 return;
11462
11463 spin_lock(&dev->event_lock);
11464 work = intel_crtc->unpin_work;
11465 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11466 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11467 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11468 page_flip_completed(intel_crtc);
11469 work = NULL;
11470 }
11471 if (work != NULL &&
11472 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11473 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11474 spin_unlock(&dev->event_lock);
11475 }
11476
11477 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11478 struct drm_framebuffer *fb,
11479 struct drm_pending_vblank_event *event,
11480 uint32_t page_flip_flags)
11481 {
11482 struct drm_device *dev = crtc->dev;
11483 struct drm_i915_private *dev_priv = dev->dev_private;
11484 struct drm_framebuffer *old_fb = crtc->primary->fb;
11485 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11487 struct drm_plane *primary = crtc->primary;
11488 enum pipe pipe = intel_crtc->pipe;
11489 struct intel_unpin_work *work;
11490 struct intel_engine_cs *engine;
11491 bool mmio_flip;
11492 struct drm_i915_gem_request *request = NULL;
11493 int ret;
11494
11495 /*
11496 * drm_mode_page_flip_ioctl() should already catch this, but double
11497 * check to be safe. In the future we may enable pageflipping from
11498 * a disabled primary plane.
11499 */
11500 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11501 return -EBUSY;
11502
11503 /* Can't change pixel format via MI display flips. */
11504 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11505 return -EINVAL;
11506
11507 /*
11508 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11509 * Note that pitch changes could also affect these register.
11510 */
11511 if (INTEL_INFO(dev)->gen > 3 &&
11512 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11513 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11514 return -EINVAL;
11515
11516 if (i915_terminally_wedged(&dev_priv->gpu_error))
11517 goto out_hang;
11518
11519 work = kzalloc(sizeof(*work), GFP_KERNEL);
11520 if (work == NULL)
11521 return -ENOMEM;
11522
11523 work->event = event;
11524 work->crtc = crtc;
11525 work->old_fb = old_fb;
11526 INIT_WORK(&work->work, intel_unpin_work_fn);
11527
11528 ret = drm_crtc_vblank_get(crtc);
11529 if (ret)
11530 goto free_work;
11531
11532 /* We borrow the event spin lock for protecting unpin_work */
11533 spin_lock_irq(&dev->event_lock);
11534 if (intel_crtc->unpin_work) {
11535 /* Before declaring the flip queue wedged, check if
11536 * the hardware completed the operation behind our backs.
11537 */
11538 if (__intel_pageflip_stall_check(dev, crtc)) {
11539 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11540 page_flip_completed(intel_crtc);
11541 } else {
11542 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11543 spin_unlock_irq(&dev->event_lock);
11544
11545 drm_crtc_vblank_put(crtc);
11546 kfree(work);
11547 return -EBUSY;
11548 }
11549 }
11550 intel_crtc->unpin_work = work;
11551 spin_unlock_irq(&dev->event_lock);
11552
11553 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11554 flush_workqueue(dev_priv->wq);
11555
11556 /* Reference the objects for the scheduled work. */
11557 drm_framebuffer_reference(work->old_fb);
11558 drm_gem_object_reference(&obj->base);
11559
11560 crtc->primary->fb = fb;
11561 update_state_fb(crtc->primary);
11562 intel_fbc_pre_update(intel_crtc);
11563
11564 work->pending_flip_obj = obj;
11565
11566 ret = i915_mutex_lock_interruptible(dev);
11567 if (ret)
11568 goto cleanup;
11569
11570 atomic_inc(&intel_crtc->unpin_work_count);
11571 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11572
11573 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11574 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11575
11576 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11577 engine = &dev_priv->engine[BCS];
11578 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11579 /* vlv: DISPLAY_FLIP fails to change tiling */
11580 engine = NULL;
11581 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11582 engine = &dev_priv->engine[BCS];
11583 } else if (INTEL_INFO(dev)->gen >= 7) {
11584 engine = i915_gem_request_get_engine(obj->last_write_req);
11585 if (engine == NULL || engine->id != RCS)
11586 engine = &dev_priv->engine[BCS];
11587 } else {
11588 engine = &dev_priv->engine[RCS];
11589 }
11590
11591 mmio_flip = use_mmio_flip(engine, obj);
11592
11593 /* When using CS flips, we want to emit semaphores between rings.
11594 * However, when using mmio flips we will create a task to do the
11595 * synchronisation, so all we want here is to pin the framebuffer
11596 * into the display plane and skip any waits.
11597 */
11598 if (!mmio_flip) {
11599 ret = i915_gem_object_sync(obj, engine, &request);
11600 if (ret)
11601 goto cleanup_pending;
11602 }
11603
11604 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11605 if (ret)
11606 goto cleanup_pending;
11607
11608 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11609 obj, 0);
11610 work->gtt_offset += intel_crtc->dspaddr_offset;
11611
11612 if (mmio_flip) {
11613 ret = intel_queue_mmio_flip(dev, crtc, obj);
11614 if (ret)
11615 goto cleanup_unpin;
11616
11617 i915_gem_request_assign(&work->flip_queued_req,
11618 obj->last_write_req);
11619 } else {
11620 if (!request) {
11621 request = i915_gem_request_alloc(engine, NULL);
11622 if (IS_ERR(request)) {
11623 ret = PTR_ERR(request);
11624 goto cleanup_unpin;
11625 }
11626 }
11627
11628 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11629 page_flip_flags);
11630 if (ret)
11631 goto cleanup_unpin;
11632
11633 i915_gem_request_assign(&work->flip_queued_req, request);
11634 }
11635
11636 if (request)
11637 i915_add_request_no_flush(request);
11638
11639 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11640 work->enable_stall_check = true;
11641
11642 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11643 to_intel_plane(primary)->frontbuffer_bit);
11644 mutex_unlock(&dev->struct_mutex);
11645
11646 intel_frontbuffer_flip_prepare(dev,
11647 to_intel_plane(primary)->frontbuffer_bit);
11648
11649 trace_i915_flip_request(intel_crtc->plane, obj);
11650
11651 return 0;
11652
11653 cleanup_unpin:
11654 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11655 cleanup_pending:
11656 if (!IS_ERR_OR_NULL(request))
11657 i915_gem_request_cancel(request);
11658 atomic_dec(&intel_crtc->unpin_work_count);
11659 mutex_unlock(&dev->struct_mutex);
11660 cleanup:
11661 crtc->primary->fb = old_fb;
11662 update_state_fb(crtc->primary);
11663
11664 drm_gem_object_unreference_unlocked(&obj->base);
11665 drm_framebuffer_unreference(work->old_fb);
11666
11667 spin_lock_irq(&dev->event_lock);
11668 intel_crtc->unpin_work = NULL;
11669 spin_unlock_irq(&dev->event_lock);
11670
11671 drm_crtc_vblank_put(crtc);
11672 free_work:
11673 kfree(work);
11674
11675 if (ret == -EIO) {
11676 struct drm_atomic_state *state;
11677 struct drm_plane_state *plane_state;
11678
11679 out_hang:
11680 state = drm_atomic_state_alloc(dev);
11681 if (!state)
11682 return -ENOMEM;
11683 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11684
11685 retry:
11686 plane_state = drm_atomic_get_plane_state(state, primary);
11687 ret = PTR_ERR_OR_ZERO(plane_state);
11688 if (!ret) {
11689 drm_atomic_set_fb_for_plane(plane_state, fb);
11690
11691 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11692 if (!ret)
11693 ret = drm_atomic_commit(state);
11694 }
11695
11696 if (ret == -EDEADLK) {
11697 drm_modeset_backoff(state->acquire_ctx);
11698 drm_atomic_state_clear(state);
11699 goto retry;
11700 }
11701
11702 if (ret)
11703 drm_atomic_state_free(state);
11704
11705 if (ret == 0 && event) {
11706 spin_lock_irq(&dev->event_lock);
11707 drm_send_vblank_event(dev, pipe, event);
11708 spin_unlock_irq(&dev->event_lock);
11709 }
11710 }
11711 return ret;
11712 }
11713
11714
11715 /**
11716 * intel_wm_need_update - Check whether watermarks need updating
11717 * @plane: drm plane
11718 * @state: new plane state
11719 *
11720 * Check current plane state versus the new one to determine whether
11721 * watermarks need to be recalculated.
11722 *
11723 * Returns true or false.
11724 */
11725 static bool intel_wm_need_update(struct drm_plane *plane,
11726 struct drm_plane_state *state)
11727 {
11728 struct intel_plane_state *new = to_intel_plane_state(state);
11729 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11730
11731 /* Update watermarks on tiling or size changes. */
11732 if (new->visible != cur->visible)
11733 return true;
11734
11735 if (!cur->base.fb || !new->base.fb)
11736 return false;
11737
11738 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11739 cur->base.rotation != new->base.rotation ||
11740 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11741 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11742 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11743 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11744 return true;
11745
11746 return false;
11747 }
11748
11749 static bool needs_scaling(struct intel_plane_state *state)
11750 {
11751 int src_w = drm_rect_width(&state->src) >> 16;
11752 int src_h = drm_rect_height(&state->src) >> 16;
11753 int dst_w = drm_rect_width(&state->dst);
11754 int dst_h = drm_rect_height(&state->dst);
11755
11756 return (src_w != dst_w || src_h != dst_h);
11757 }
11758
11759 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11760 struct drm_plane_state *plane_state)
11761 {
11762 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11763 struct drm_crtc *crtc = crtc_state->crtc;
11764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11765 struct drm_plane *plane = plane_state->plane;
11766 struct drm_device *dev = crtc->dev;
11767 struct drm_i915_private *dev_priv = to_i915(dev);
11768 struct intel_plane_state *old_plane_state =
11769 to_intel_plane_state(plane->state);
11770 int idx = intel_crtc->base.base.id, ret;
11771 bool mode_changed = needs_modeset(crtc_state);
11772 bool was_crtc_enabled = crtc->state->active;
11773 bool is_crtc_enabled = crtc_state->active;
11774 bool turn_off, turn_on, visible, was_visible;
11775 struct drm_framebuffer *fb = plane_state->fb;
11776
11777 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11778 plane->type != DRM_PLANE_TYPE_CURSOR) {
11779 ret = skl_update_scaler_plane(
11780 to_intel_crtc_state(crtc_state),
11781 to_intel_plane_state(plane_state));
11782 if (ret)
11783 return ret;
11784 }
11785
11786 was_visible = old_plane_state->visible;
11787 visible = to_intel_plane_state(plane_state)->visible;
11788
11789 if (!was_crtc_enabled && WARN_ON(was_visible))
11790 was_visible = false;
11791
11792 /*
11793 * Visibility is calculated as if the crtc was on, but
11794 * after scaler setup everything depends on it being off
11795 * when the crtc isn't active.
11796 */
11797 if (!is_crtc_enabled)
11798 to_intel_plane_state(plane_state)->visible = visible = false;
11799
11800 if (!was_visible && !visible)
11801 return 0;
11802
11803 if (fb != old_plane_state->base.fb)
11804 pipe_config->fb_changed = true;
11805
11806 turn_off = was_visible && (!visible || mode_changed);
11807 turn_on = visible && (!was_visible || mode_changed);
11808
11809 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11810 plane->base.id, fb ? fb->base.id : -1);
11811
11812 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11813 plane->base.id, was_visible, visible,
11814 turn_off, turn_on, mode_changed);
11815
11816 if (turn_on) {
11817 pipe_config->update_wm_pre = true;
11818
11819 /* must disable cxsr around plane enable/disable */
11820 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11821 pipe_config->disable_cxsr = true;
11822 } else if (turn_off) {
11823 pipe_config->update_wm_post = true;
11824
11825 /* must disable cxsr around plane enable/disable */
11826 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11827 pipe_config->disable_cxsr = true;
11828 } else if (intel_wm_need_update(plane, plane_state)) {
11829 /* FIXME bollocks */
11830 pipe_config->update_wm_pre = true;
11831 pipe_config->update_wm_post = true;
11832 }
11833
11834 /* Pre-gen9 platforms need two-step watermark updates */
11835 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11836 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11837 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11838
11839 if (visible || was_visible)
11840 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11841
11842 /*
11843 * WaCxSRDisabledForSpriteScaling:ivb
11844 *
11845 * cstate->update_wm was already set above, so this flag will
11846 * take effect when we commit and program watermarks.
11847 */
11848 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11849 needs_scaling(to_intel_plane_state(plane_state)) &&
11850 !needs_scaling(old_plane_state))
11851 pipe_config->disable_lp_wm = true;
11852
11853 return 0;
11854 }
11855
11856 static bool encoders_cloneable(const struct intel_encoder *a,
11857 const struct intel_encoder *b)
11858 {
11859 /* masks could be asymmetric, so check both ways */
11860 return a == b || (a->cloneable & (1 << b->type) &&
11861 b->cloneable & (1 << a->type));
11862 }
11863
11864 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11865 struct intel_crtc *crtc,
11866 struct intel_encoder *encoder)
11867 {
11868 struct intel_encoder *source_encoder;
11869 struct drm_connector *connector;
11870 struct drm_connector_state *connector_state;
11871 int i;
11872
11873 for_each_connector_in_state(state, connector, connector_state, i) {
11874 if (connector_state->crtc != &crtc->base)
11875 continue;
11876
11877 source_encoder =
11878 to_intel_encoder(connector_state->best_encoder);
11879 if (!encoders_cloneable(encoder, source_encoder))
11880 return false;
11881 }
11882
11883 return true;
11884 }
11885
11886 static bool check_encoder_cloning(struct drm_atomic_state *state,
11887 struct intel_crtc *crtc)
11888 {
11889 struct intel_encoder *encoder;
11890 struct drm_connector *connector;
11891 struct drm_connector_state *connector_state;
11892 int i;
11893
11894 for_each_connector_in_state(state, connector, connector_state, i) {
11895 if (connector_state->crtc != &crtc->base)
11896 continue;
11897
11898 encoder = to_intel_encoder(connector_state->best_encoder);
11899 if (!check_single_encoder_cloning(state, crtc, encoder))
11900 return false;
11901 }
11902
11903 return true;
11904 }
11905
11906 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11907 struct drm_crtc_state *crtc_state)
11908 {
11909 struct drm_device *dev = crtc->dev;
11910 struct drm_i915_private *dev_priv = dev->dev_private;
11911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11912 struct intel_crtc_state *pipe_config =
11913 to_intel_crtc_state(crtc_state);
11914 struct drm_atomic_state *state = crtc_state->state;
11915 int ret;
11916 bool mode_changed = needs_modeset(crtc_state);
11917
11918 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11919 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11920 return -EINVAL;
11921 }
11922
11923 if (mode_changed && !crtc_state->active)
11924 pipe_config->update_wm_post = true;
11925
11926 if (mode_changed && crtc_state->enable &&
11927 dev_priv->display.crtc_compute_clock &&
11928 !WARN_ON(pipe_config->shared_dpll)) {
11929 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11930 pipe_config);
11931 if (ret)
11932 return ret;
11933 }
11934
11935 if (crtc_state->color_mgmt_changed) {
11936 ret = intel_color_check(crtc, crtc_state);
11937 if (ret)
11938 return ret;
11939 }
11940
11941 ret = 0;
11942 if (dev_priv->display.compute_pipe_wm) {
11943 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11944 if (ret) {
11945 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11946 return ret;
11947 }
11948 }
11949
11950 if (dev_priv->display.compute_intermediate_wm &&
11951 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11952 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11953 return 0;
11954
11955 /*
11956 * Calculate 'intermediate' watermarks that satisfy both the
11957 * old state and the new state. We can program these
11958 * immediately.
11959 */
11960 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11961 intel_crtc,
11962 pipe_config);
11963 if (ret) {
11964 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11965 return ret;
11966 }
11967 }
11968
11969 if (INTEL_INFO(dev)->gen >= 9) {
11970 if (mode_changed)
11971 ret = skl_update_scaler_crtc(pipe_config);
11972
11973 if (!ret)
11974 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11975 pipe_config);
11976 }
11977
11978 return ret;
11979 }
11980
11981 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11982 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11983 .atomic_begin = intel_begin_crtc_commit,
11984 .atomic_flush = intel_finish_crtc_commit,
11985 .atomic_check = intel_crtc_atomic_check,
11986 };
11987
11988 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11989 {
11990 struct intel_connector *connector;
11991
11992 for_each_intel_connector(dev, connector) {
11993 if (connector->base.encoder) {
11994 connector->base.state->best_encoder =
11995 connector->base.encoder;
11996 connector->base.state->crtc =
11997 connector->base.encoder->crtc;
11998 } else {
11999 connector->base.state->best_encoder = NULL;
12000 connector->base.state->crtc = NULL;
12001 }
12002 }
12003 }
12004
12005 static void
12006 connected_sink_compute_bpp(struct intel_connector *connector,
12007 struct intel_crtc_state *pipe_config)
12008 {
12009 int bpp = pipe_config->pipe_bpp;
12010
12011 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12012 connector->base.base.id,
12013 connector->base.name);
12014
12015 /* Don't use an invalid EDID bpc value */
12016 if (connector->base.display_info.bpc &&
12017 connector->base.display_info.bpc * 3 < bpp) {
12018 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12019 bpp, connector->base.display_info.bpc*3);
12020 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12021 }
12022
12023 /* Clamp bpp to default limit on screens without EDID 1.4 */
12024 if (connector->base.display_info.bpc == 0) {
12025 int type = connector->base.connector_type;
12026 int clamp_bpp = 24;
12027
12028 /* Fall back to 18 bpp when DP sink capability is unknown. */
12029 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12030 type == DRM_MODE_CONNECTOR_eDP)
12031 clamp_bpp = 18;
12032
12033 if (bpp > clamp_bpp) {
12034 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12035 bpp, clamp_bpp);
12036 pipe_config->pipe_bpp = clamp_bpp;
12037 }
12038 }
12039 }
12040
12041 static int
12042 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12043 struct intel_crtc_state *pipe_config)
12044 {
12045 struct drm_device *dev = crtc->base.dev;
12046 struct drm_atomic_state *state;
12047 struct drm_connector *connector;
12048 struct drm_connector_state *connector_state;
12049 int bpp, i;
12050
12051 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12052 bpp = 10*3;
12053 else if (INTEL_INFO(dev)->gen >= 5)
12054 bpp = 12*3;
12055 else
12056 bpp = 8*3;
12057
12058
12059 pipe_config->pipe_bpp = bpp;
12060
12061 state = pipe_config->base.state;
12062
12063 /* Clamp display bpp to EDID value */
12064 for_each_connector_in_state(state, connector, connector_state, i) {
12065 if (connector_state->crtc != &crtc->base)
12066 continue;
12067
12068 connected_sink_compute_bpp(to_intel_connector(connector),
12069 pipe_config);
12070 }
12071
12072 return bpp;
12073 }
12074
12075 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12076 {
12077 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12078 "type: 0x%x flags: 0x%x\n",
12079 mode->crtc_clock,
12080 mode->crtc_hdisplay, mode->crtc_hsync_start,
12081 mode->crtc_hsync_end, mode->crtc_htotal,
12082 mode->crtc_vdisplay, mode->crtc_vsync_start,
12083 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12084 }
12085
12086 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12087 struct intel_crtc_state *pipe_config,
12088 const char *context)
12089 {
12090 struct drm_device *dev = crtc->base.dev;
12091 struct drm_plane *plane;
12092 struct intel_plane *intel_plane;
12093 struct intel_plane_state *state;
12094 struct drm_framebuffer *fb;
12095
12096 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12097 context, pipe_config, pipe_name(crtc->pipe));
12098
12099 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12100 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12101 pipe_config->pipe_bpp, pipe_config->dither);
12102 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12103 pipe_config->has_pch_encoder,
12104 pipe_config->fdi_lanes,
12105 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12106 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12107 pipe_config->fdi_m_n.tu);
12108 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12109 pipe_config->has_dp_encoder,
12110 pipe_config->lane_count,
12111 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12112 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12113 pipe_config->dp_m_n.tu);
12114
12115 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12116 pipe_config->has_dp_encoder,
12117 pipe_config->lane_count,
12118 pipe_config->dp_m2_n2.gmch_m,
12119 pipe_config->dp_m2_n2.gmch_n,
12120 pipe_config->dp_m2_n2.link_m,
12121 pipe_config->dp_m2_n2.link_n,
12122 pipe_config->dp_m2_n2.tu);
12123
12124 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12125 pipe_config->has_audio,
12126 pipe_config->has_infoframe);
12127
12128 DRM_DEBUG_KMS("requested mode:\n");
12129 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12130 DRM_DEBUG_KMS("adjusted mode:\n");
12131 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12132 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12133 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12134 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12135 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12136 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12137 crtc->num_scalers,
12138 pipe_config->scaler_state.scaler_users,
12139 pipe_config->scaler_state.scaler_id);
12140 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12141 pipe_config->gmch_pfit.control,
12142 pipe_config->gmch_pfit.pgm_ratios,
12143 pipe_config->gmch_pfit.lvds_border_bits);
12144 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12145 pipe_config->pch_pfit.pos,
12146 pipe_config->pch_pfit.size,
12147 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12148 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12149 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12150
12151 if (IS_BROXTON(dev)) {
12152 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12153 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12154 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12155 pipe_config->ddi_pll_sel,
12156 pipe_config->dpll_hw_state.ebb0,
12157 pipe_config->dpll_hw_state.ebb4,
12158 pipe_config->dpll_hw_state.pll0,
12159 pipe_config->dpll_hw_state.pll1,
12160 pipe_config->dpll_hw_state.pll2,
12161 pipe_config->dpll_hw_state.pll3,
12162 pipe_config->dpll_hw_state.pll6,
12163 pipe_config->dpll_hw_state.pll8,
12164 pipe_config->dpll_hw_state.pll9,
12165 pipe_config->dpll_hw_state.pll10,
12166 pipe_config->dpll_hw_state.pcsdw12);
12167 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12168 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12169 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12170 pipe_config->ddi_pll_sel,
12171 pipe_config->dpll_hw_state.ctrl1,
12172 pipe_config->dpll_hw_state.cfgcr1,
12173 pipe_config->dpll_hw_state.cfgcr2);
12174 } else if (HAS_DDI(dev)) {
12175 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12176 pipe_config->ddi_pll_sel,
12177 pipe_config->dpll_hw_state.wrpll,
12178 pipe_config->dpll_hw_state.spll);
12179 } else {
12180 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12181 "fp0: 0x%x, fp1: 0x%x\n",
12182 pipe_config->dpll_hw_state.dpll,
12183 pipe_config->dpll_hw_state.dpll_md,
12184 pipe_config->dpll_hw_state.fp0,
12185 pipe_config->dpll_hw_state.fp1);
12186 }
12187
12188 DRM_DEBUG_KMS("planes on this crtc\n");
12189 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12190 intel_plane = to_intel_plane(plane);
12191 if (intel_plane->pipe != crtc->pipe)
12192 continue;
12193
12194 state = to_intel_plane_state(plane->state);
12195 fb = state->base.fb;
12196 if (!fb) {
12197 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12198 "disabled, scaler_id = %d\n",
12199 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12200 plane->base.id, intel_plane->pipe,
12201 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12202 drm_plane_index(plane), state->scaler_id);
12203 continue;
12204 }
12205
12206 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12207 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12208 plane->base.id, intel_plane->pipe,
12209 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12210 drm_plane_index(plane));
12211 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12212 fb->base.id, fb->width, fb->height, fb->pixel_format);
12213 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12214 state->scaler_id,
12215 state->src.x1 >> 16, state->src.y1 >> 16,
12216 drm_rect_width(&state->src) >> 16,
12217 drm_rect_height(&state->src) >> 16,
12218 state->dst.x1, state->dst.y1,
12219 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12220 }
12221 }
12222
12223 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12224 {
12225 struct drm_device *dev = state->dev;
12226 struct drm_connector *connector;
12227 unsigned int used_ports = 0;
12228
12229 /*
12230 * Walk the connector list instead of the encoder
12231 * list to detect the problem on ddi platforms
12232 * where there's just one encoder per digital port.
12233 */
12234 drm_for_each_connector(connector, dev) {
12235 struct drm_connector_state *connector_state;
12236 struct intel_encoder *encoder;
12237
12238 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12239 if (!connector_state)
12240 connector_state = connector->state;
12241
12242 if (!connector_state->best_encoder)
12243 continue;
12244
12245 encoder = to_intel_encoder(connector_state->best_encoder);
12246
12247 WARN_ON(!connector_state->crtc);
12248
12249 switch (encoder->type) {
12250 unsigned int port_mask;
12251 case INTEL_OUTPUT_UNKNOWN:
12252 if (WARN_ON(!HAS_DDI(dev)))
12253 break;
12254 case INTEL_OUTPUT_DISPLAYPORT:
12255 case INTEL_OUTPUT_HDMI:
12256 case INTEL_OUTPUT_EDP:
12257 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12258
12259 /* the same port mustn't appear more than once */
12260 if (used_ports & port_mask)
12261 return false;
12262
12263 used_ports |= port_mask;
12264 default:
12265 break;
12266 }
12267 }
12268
12269 return true;
12270 }
12271
12272 static void
12273 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12274 {
12275 struct drm_crtc_state tmp_state;
12276 struct intel_crtc_scaler_state scaler_state;
12277 struct intel_dpll_hw_state dpll_hw_state;
12278 struct intel_shared_dpll *shared_dpll;
12279 uint32_t ddi_pll_sel;
12280 bool force_thru;
12281
12282 /* FIXME: before the switch to atomic started, a new pipe_config was
12283 * kzalloc'd. Code that depends on any field being zero should be
12284 * fixed, so that the crtc_state can be safely duplicated. For now,
12285 * only fields that are know to not cause problems are preserved. */
12286
12287 tmp_state = crtc_state->base;
12288 scaler_state = crtc_state->scaler_state;
12289 shared_dpll = crtc_state->shared_dpll;
12290 dpll_hw_state = crtc_state->dpll_hw_state;
12291 ddi_pll_sel = crtc_state->ddi_pll_sel;
12292 force_thru = crtc_state->pch_pfit.force_thru;
12293
12294 memset(crtc_state, 0, sizeof *crtc_state);
12295
12296 crtc_state->base = tmp_state;
12297 crtc_state->scaler_state = scaler_state;
12298 crtc_state->shared_dpll = shared_dpll;
12299 crtc_state->dpll_hw_state = dpll_hw_state;
12300 crtc_state->ddi_pll_sel = ddi_pll_sel;
12301 crtc_state->pch_pfit.force_thru = force_thru;
12302 }
12303
12304 static int
12305 intel_modeset_pipe_config(struct drm_crtc *crtc,
12306 struct intel_crtc_state *pipe_config)
12307 {
12308 struct drm_atomic_state *state = pipe_config->base.state;
12309 struct intel_encoder *encoder;
12310 struct drm_connector *connector;
12311 struct drm_connector_state *connector_state;
12312 int base_bpp, ret = -EINVAL;
12313 int i;
12314 bool retry = true;
12315
12316 clear_intel_crtc_state(pipe_config);
12317
12318 pipe_config->cpu_transcoder =
12319 (enum transcoder) to_intel_crtc(crtc)->pipe;
12320
12321 /*
12322 * Sanitize sync polarity flags based on requested ones. If neither
12323 * positive or negative polarity is requested, treat this as meaning
12324 * negative polarity.
12325 */
12326 if (!(pipe_config->base.adjusted_mode.flags &
12327 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12328 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12329
12330 if (!(pipe_config->base.adjusted_mode.flags &
12331 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12332 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12333
12334 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12335 pipe_config);
12336 if (base_bpp < 0)
12337 goto fail;
12338
12339 /*
12340 * Determine the real pipe dimensions. Note that stereo modes can
12341 * increase the actual pipe size due to the frame doubling and
12342 * insertion of additional space for blanks between the frame. This
12343 * is stored in the crtc timings. We use the requested mode to do this
12344 * computation to clearly distinguish it from the adjusted mode, which
12345 * can be changed by the connectors in the below retry loop.
12346 */
12347 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12348 &pipe_config->pipe_src_w,
12349 &pipe_config->pipe_src_h);
12350
12351 encoder_retry:
12352 /* Ensure the port clock defaults are reset when retrying. */
12353 pipe_config->port_clock = 0;
12354 pipe_config->pixel_multiplier = 1;
12355
12356 /* Fill in default crtc timings, allow encoders to overwrite them. */
12357 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12358 CRTC_STEREO_DOUBLE);
12359
12360 /* Pass our mode to the connectors and the CRTC to give them a chance to
12361 * adjust it according to limitations or connector properties, and also
12362 * a chance to reject the mode entirely.
12363 */
12364 for_each_connector_in_state(state, connector, connector_state, i) {
12365 if (connector_state->crtc != crtc)
12366 continue;
12367
12368 encoder = to_intel_encoder(connector_state->best_encoder);
12369
12370 if (!(encoder->compute_config(encoder, pipe_config))) {
12371 DRM_DEBUG_KMS("Encoder config failure\n");
12372 goto fail;
12373 }
12374 }
12375
12376 /* Set default port clock if not overwritten by the encoder. Needs to be
12377 * done afterwards in case the encoder adjusts the mode. */
12378 if (!pipe_config->port_clock)
12379 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12380 * pipe_config->pixel_multiplier;
12381
12382 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12383 if (ret < 0) {
12384 DRM_DEBUG_KMS("CRTC fixup failed\n");
12385 goto fail;
12386 }
12387
12388 if (ret == RETRY) {
12389 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12390 ret = -EINVAL;
12391 goto fail;
12392 }
12393
12394 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12395 retry = false;
12396 goto encoder_retry;
12397 }
12398
12399 /* Dithering seems to not pass-through bits correctly when it should, so
12400 * only enable it on 6bpc panels. */
12401 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12402 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12403 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12404
12405 fail:
12406 return ret;
12407 }
12408
12409 static void
12410 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12411 {
12412 struct drm_crtc *crtc;
12413 struct drm_crtc_state *crtc_state;
12414 int i;
12415
12416 /* Double check state. */
12417 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12418 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12419
12420 /* Update hwmode for vblank functions */
12421 if (crtc->state->active)
12422 crtc->hwmode = crtc->state->adjusted_mode;
12423 else
12424 crtc->hwmode.crtc_clock = 0;
12425
12426 /*
12427 * Update legacy state to satisfy fbc code. This can
12428 * be removed when fbc uses the atomic state.
12429 */
12430 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12431 struct drm_plane_state *plane_state = crtc->primary->state;
12432
12433 crtc->primary->fb = plane_state->fb;
12434 crtc->x = plane_state->src_x >> 16;
12435 crtc->y = plane_state->src_y >> 16;
12436 }
12437 }
12438 }
12439
12440 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12441 {
12442 int diff;
12443
12444 if (clock1 == clock2)
12445 return true;
12446
12447 if (!clock1 || !clock2)
12448 return false;
12449
12450 diff = abs(clock1 - clock2);
12451
12452 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12453 return true;
12454
12455 return false;
12456 }
12457
12458 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12459 list_for_each_entry((intel_crtc), \
12460 &(dev)->mode_config.crtc_list, \
12461 base.head) \
12462 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12463
12464 static bool
12465 intel_compare_m_n(unsigned int m, unsigned int n,
12466 unsigned int m2, unsigned int n2,
12467 bool exact)
12468 {
12469 if (m == m2 && n == n2)
12470 return true;
12471
12472 if (exact || !m || !n || !m2 || !n2)
12473 return false;
12474
12475 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12476
12477 if (n > n2) {
12478 while (n > n2) {
12479 m2 <<= 1;
12480 n2 <<= 1;
12481 }
12482 } else if (n < n2) {
12483 while (n < n2) {
12484 m <<= 1;
12485 n <<= 1;
12486 }
12487 }
12488
12489 if (n != n2)
12490 return false;
12491
12492 return intel_fuzzy_clock_check(m, m2);
12493 }
12494
12495 static bool
12496 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12497 struct intel_link_m_n *m2_n2,
12498 bool adjust)
12499 {
12500 if (m_n->tu == m2_n2->tu &&
12501 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12502 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12503 intel_compare_m_n(m_n->link_m, m_n->link_n,
12504 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12505 if (adjust)
12506 *m2_n2 = *m_n;
12507
12508 return true;
12509 }
12510
12511 return false;
12512 }
12513
12514 static bool
12515 intel_pipe_config_compare(struct drm_device *dev,
12516 struct intel_crtc_state *current_config,
12517 struct intel_crtc_state *pipe_config,
12518 bool adjust)
12519 {
12520 bool ret = true;
12521
12522 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12523 do { \
12524 if (!adjust) \
12525 DRM_ERROR(fmt, ##__VA_ARGS__); \
12526 else \
12527 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12528 } while (0)
12529
12530 #define PIPE_CONF_CHECK_X(name) \
12531 if (current_config->name != pipe_config->name) { \
12532 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12533 "(expected 0x%08x, found 0x%08x)\n", \
12534 current_config->name, \
12535 pipe_config->name); \
12536 ret = false; \
12537 }
12538
12539 #define PIPE_CONF_CHECK_I(name) \
12540 if (current_config->name != pipe_config->name) { \
12541 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12542 "(expected %i, found %i)\n", \
12543 current_config->name, \
12544 pipe_config->name); \
12545 ret = false; \
12546 }
12547
12548 #define PIPE_CONF_CHECK_P(name) \
12549 if (current_config->name != pipe_config->name) { \
12550 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12551 "(expected %p, found %p)\n", \
12552 current_config->name, \
12553 pipe_config->name); \
12554 ret = false; \
12555 }
12556
12557 #define PIPE_CONF_CHECK_M_N(name) \
12558 if (!intel_compare_link_m_n(&current_config->name, \
12559 &pipe_config->name,\
12560 adjust)) { \
12561 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12562 "(expected tu %i gmch %i/%i link %i/%i, " \
12563 "found tu %i, gmch %i/%i link %i/%i)\n", \
12564 current_config->name.tu, \
12565 current_config->name.gmch_m, \
12566 current_config->name.gmch_n, \
12567 current_config->name.link_m, \
12568 current_config->name.link_n, \
12569 pipe_config->name.tu, \
12570 pipe_config->name.gmch_m, \
12571 pipe_config->name.gmch_n, \
12572 pipe_config->name.link_m, \
12573 pipe_config->name.link_n); \
12574 ret = false; \
12575 }
12576
12577 /* This is required for BDW+ where there is only one set of registers for
12578 * switching between high and low RR.
12579 * This macro can be used whenever a comparison has to be made between one
12580 * hw state and multiple sw state variables.
12581 */
12582 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12583 if (!intel_compare_link_m_n(&current_config->name, \
12584 &pipe_config->name, adjust) && \
12585 !intel_compare_link_m_n(&current_config->alt_name, \
12586 &pipe_config->name, adjust)) { \
12587 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12588 "(expected tu %i gmch %i/%i link %i/%i, " \
12589 "or tu %i gmch %i/%i link %i/%i, " \
12590 "found tu %i, gmch %i/%i link %i/%i)\n", \
12591 current_config->name.tu, \
12592 current_config->name.gmch_m, \
12593 current_config->name.gmch_n, \
12594 current_config->name.link_m, \
12595 current_config->name.link_n, \
12596 current_config->alt_name.tu, \
12597 current_config->alt_name.gmch_m, \
12598 current_config->alt_name.gmch_n, \
12599 current_config->alt_name.link_m, \
12600 current_config->alt_name.link_n, \
12601 pipe_config->name.tu, \
12602 pipe_config->name.gmch_m, \
12603 pipe_config->name.gmch_n, \
12604 pipe_config->name.link_m, \
12605 pipe_config->name.link_n); \
12606 ret = false; \
12607 }
12608
12609 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12610 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12611 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12612 "(expected %i, found %i)\n", \
12613 current_config->name & (mask), \
12614 pipe_config->name & (mask)); \
12615 ret = false; \
12616 }
12617
12618 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12619 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12620 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12621 "(expected %i, found %i)\n", \
12622 current_config->name, \
12623 pipe_config->name); \
12624 ret = false; \
12625 }
12626
12627 #define PIPE_CONF_QUIRK(quirk) \
12628 ((current_config->quirks | pipe_config->quirks) & (quirk))
12629
12630 PIPE_CONF_CHECK_I(cpu_transcoder);
12631
12632 PIPE_CONF_CHECK_I(has_pch_encoder);
12633 PIPE_CONF_CHECK_I(fdi_lanes);
12634 PIPE_CONF_CHECK_M_N(fdi_m_n);
12635
12636 PIPE_CONF_CHECK_I(has_dp_encoder);
12637 PIPE_CONF_CHECK_I(lane_count);
12638
12639 if (INTEL_INFO(dev)->gen < 8) {
12640 PIPE_CONF_CHECK_M_N(dp_m_n);
12641
12642 if (current_config->has_drrs)
12643 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12644 } else
12645 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12646
12647 PIPE_CONF_CHECK_I(has_dsi_encoder);
12648
12649 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12650 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12651 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12652 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12653 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12654 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12655
12656 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12657 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12658 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12659 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12660 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12661 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12662
12663 PIPE_CONF_CHECK_I(pixel_multiplier);
12664 PIPE_CONF_CHECK_I(has_hdmi_sink);
12665 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12666 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12667 PIPE_CONF_CHECK_I(limited_color_range);
12668 PIPE_CONF_CHECK_I(has_infoframe);
12669
12670 PIPE_CONF_CHECK_I(has_audio);
12671
12672 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12673 DRM_MODE_FLAG_INTERLACE);
12674
12675 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12676 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12677 DRM_MODE_FLAG_PHSYNC);
12678 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12679 DRM_MODE_FLAG_NHSYNC);
12680 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12681 DRM_MODE_FLAG_PVSYNC);
12682 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12683 DRM_MODE_FLAG_NVSYNC);
12684 }
12685
12686 PIPE_CONF_CHECK_X(gmch_pfit.control);
12687 /* pfit ratios are autocomputed by the hw on gen4+ */
12688 if (INTEL_INFO(dev)->gen < 4)
12689 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12690 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12691
12692 if (!adjust) {
12693 PIPE_CONF_CHECK_I(pipe_src_w);
12694 PIPE_CONF_CHECK_I(pipe_src_h);
12695
12696 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12697 if (current_config->pch_pfit.enabled) {
12698 PIPE_CONF_CHECK_X(pch_pfit.pos);
12699 PIPE_CONF_CHECK_X(pch_pfit.size);
12700 }
12701
12702 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12703 }
12704
12705 /* BDW+ don't expose a synchronous way to read the state */
12706 if (IS_HASWELL(dev))
12707 PIPE_CONF_CHECK_I(ips_enabled);
12708
12709 PIPE_CONF_CHECK_I(double_wide);
12710
12711 PIPE_CONF_CHECK_X(ddi_pll_sel);
12712
12713 PIPE_CONF_CHECK_P(shared_dpll);
12714 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12715 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12716 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12717 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12718 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12719 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12720 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12721 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12722 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12723
12724 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12725 PIPE_CONF_CHECK_I(pipe_bpp);
12726
12727 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12728 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12729
12730 #undef PIPE_CONF_CHECK_X
12731 #undef PIPE_CONF_CHECK_I
12732 #undef PIPE_CONF_CHECK_P
12733 #undef PIPE_CONF_CHECK_FLAGS
12734 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12735 #undef PIPE_CONF_QUIRK
12736 #undef INTEL_ERR_OR_DBG_KMS
12737
12738 return ret;
12739 }
12740
12741 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12742 const struct intel_crtc_state *pipe_config)
12743 {
12744 if (pipe_config->has_pch_encoder) {
12745 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12746 &pipe_config->fdi_m_n);
12747 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12748
12749 /*
12750 * FDI already provided one idea for the dotclock.
12751 * Yell if the encoder disagrees.
12752 */
12753 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12754 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12755 fdi_dotclock, dotclock);
12756 }
12757 }
12758
12759 static void verify_wm_state(struct drm_crtc *crtc,
12760 struct drm_crtc_state *new_state)
12761 {
12762 struct drm_device *dev = crtc->dev;
12763 struct drm_i915_private *dev_priv = dev->dev_private;
12764 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12765 struct skl_ddb_entry *hw_entry, *sw_entry;
12766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12767 const enum pipe pipe = intel_crtc->pipe;
12768 int plane;
12769
12770 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12771 return;
12772
12773 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12774 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12775
12776 /* planes */
12777 for_each_plane(dev_priv, pipe, plane) {
12778 hw_entry = &hw_ddb.plane[pipe][plane];
12779 sw_entry = &sw_ddb->plane[pipe][plane];
12780
12781 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12782 continue;
12783
12784 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12785 "(expected (%u,%u), found (%u,%u))\n",
12786 pipe_name(pipe), plane + 1,
12787 sw_entry->start, sw_entry->end,
12788 hw_entry->start, hw_entry->end);
12789 }
12790
12791 /* cursor */
12792 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12793 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12794
12795 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12796 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12797 "(expected (%u,%u), found (%u,%u))\n",
12798 pipe_name(pipe),
12799 sw_entry->start, sw_entry->end,
12800 hw_entry->start, hw_entry->end);
12801 }
12802 }
12803
12804 static void
12805 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12806 {
12807 struct drm_connector *connector;
12808
12809 drm_for_each_connector(connector, dev) {
12810 struct drm_encoder *encoder = connector->encoder;
12811 struct drm_connector_state *state = connector->state;
12812
12813 if (state->crtc != crtc)
12814 continue;
12815
12816 intel_connector_verify_state(to_intel_connector(connector));
12817
12818 I915_STATE_WARN(state->best_encoder != encoder,
12819 "connector's atomic encoder doesn't match legacy encoder\n");
12820 }
12821 }
12822
12823 static void
12824 verify_encoder_state(struct drm_device *dev)
12825 {
12826 struct intel_encoder *encoder;
12827 struct intel_connector *connector;
12828
12829 for_each_intel_encoder(dev, encoder) {
12830 bool enabled = false;
12831 enum pipe pipe;
12832
12833 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12834 encoder->base.base.id,
12835 encoder->base.name);
12836
12837 for_each_intel_connector(dev, connector) {
12838 if (connector->base.state->best_encoder != &encoder->base)
12839 continue;
12840 enabled = true;
12841
12842 I915_STATE_WARN(connector->base.state->crtc !=
12843 encoder->base.crtc,
12844 "connector's crtc doesn't match encoder crtc\n");
12845 }
12846
12847 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12848 "encoder's enabled state mismatch "
12849 "(expected %i, found %i)\n",
12850 !!encoder->base.crtc, enabled);
12851
12852 if (!encoder->base.crtc) {
12853 bool active;
12854
12855 active = encoder->get_hw_state(encoder, &pipe);
12856 I915_STATE_WARN(active,
12857 "encoder detached but still enabled on pipe %c.\n",
12858 pipe_name(pipe));
12859 }
12860 }
12861 }
12862
12863 static void
12864 verify_crtc_state(struct drm_crtc *crtc,
12865 struct drm_crtc_state *old_crtc_state,
12866 struct drm_crtc_state *new_crtc_state)
12867 {
12868 struct drm_device *dev = crtc->dev;
12869 struct drm_i915_private *dev_priv = dev->dev_private;
12870 struct intel_encoder *encoder;
12871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12872 struct intel_crtc_state *pipe_config, *sw_config;
12873 struct drm_atomic_state *old_state;
12874 bool active;
12875
12876 old_state = old_crtc_state->state;
12877 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12878 pipe_config = to_intel_crtc_state(old_crtc_state);
12879 memset(pipe_config, 0, sizeof(*pipe_config));
12880 pipe_config->base.crtc = crtc;
12881 pipe_config->base.state = old_state;
12882
12883 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12884
12885 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12886
12887 /* hw state is inconsistent with the pipe quirk */
12888 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12889 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12890 active = new_crtc_state->active;
12891
12892 I915_STATE_WARN(new_crtc_state->active != active,
12893 "crtc active state doesn't match with hw state "
12894 "(expected %i, found %i)\n", new_crtc_state->active, active);
12895
12896 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12897 "transitional active state does not match atomic hw state "
12898 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12899
12900 for_each_encoder_on_crtc(dev, crtc, encoder) {
12901 enum pipe pipe;
12902
12903 active = encoder->get_hw_state(encoder, &pipe);
12904 I915_STATE_WARN(active != new_crtc_state->active,
12905 "[ENCODER:%i] active %i with crtc active %i\n",
12906 encoder->base.base.id, active, new_crtc_state->active);
12907
12908 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12909 "Encoder connected to wrong pipe %c\n",
12910 pipe_name(pipe));
12911
12912 if (active)
12913 encoder->get_config(encoder, pipe_config);
12914 }
12915
12916 if (!new_crtc_state->active)
12917 return;
12918
12919 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12920
12921 sw_config = to_intel_crtc_state(crtc->state);
12922 if (!intel_pipe_config_compare(dev, sw_config,
12923 pipe_config, false)) {
12924 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12925 intel_dump_pipe_config(intel_crtc, pipe_config,
12926 "[hw state]");
12927 intel_dump_pipe_config(intel_crtc, sw_config,
12928 "[sw state]");
12929 }
12930 }
12931
12932 static void
12933 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12934 struct intel_shared_dpll *pll,
12935 struct drm_crtc *crtc,
12936 struct drm_crtc_state *new_state)
12937 {
12938 struct intel_dpll_hw_state dpll_hw_state;
12939 unsigned crtc_mask;
12940 bool active;
12941
12942 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12943
12944 DRM_DEBUG_KMS("%s\n", pll->name);
12945
12946 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12947
12948 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12949 I915_STATE_WARN(!pll->on && pll->active_mask,
12950 "pll in active use but not on in sw tracking\n");
12951 I915_STATE_WARN(pll->on && !pll->active_mask,
12952 "pll is on but not used by any active crtc\n");
12953 I915_STATE_WARN(pll->on != active,
12954 "pll on state mismatch (expected %i, found %i)\n",
12955 pll->on, active);
12956 }
12957
12958 if (!crtc) {
12959 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12960 "more active pll users than references: %x vs %x\n",
12961 pll->active_mask, pll->config.crtc_mask);
12962
12963 return;
12964 }
12965
12966 crtc_mask = 1 << drm_crtc_index(crtc);
12967
12968 if (new_state->active)
12969 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12970 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12971 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12972 else
12973 I915_STATE_WARN(pll->active_mask & crtc_mask,
12974 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12975 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12976
12977 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12978 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12979 crtc_mask, pll->config.crtc_mask);
12980
12981 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12982 &dpll_hw_state,
12983 sizeof(dpll_hw_state)),
12984 "pll hw state mismatch\n");
12985 }
12986
12987 static void
12988 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12989 struct drm_crtc_state *old_crtc_state,
12990 struct drm_crtc_state *new_crtc_state)
12991 {
12992 struct drm_i915_private *dev_priv = dev->dev_private;
12993 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12994 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12995
12996 if (new_state->shared_dpll)
12997 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12998
12999 if (old_state->shared_dpll &&
13000 old_state->shared_dpll != new_state->shared_dpll) {
13001 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13002 struct intel_shared_dpll *pll = old_state->shared_dpll;
13003
13004 I915_STATE_WARN(pll->active_mask & crtc_mask,
13005 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13006 pipe_name(drm_crtc_index(crtc)));
13007 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13008 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13009 pipe_name(drm_crtc_index(crtc)));
13010 }
13011 }
13012
13013 static void
13014 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13015 struct drm_crtc_state *old_state,
13016 struct drm_crtc_state *new_state)
13017 {
13018 if (!needs_modeset(new_state) &&
13019 !to_intel_crtc_state(new_state)->update_pipe)
13020 return;
13021
13022 verify_wm_state(crtc, new_state);
13023 verify_connector_state(crtc->dev, crtc);
13024 verify_crtc_state(crtc, old_state, new_state);
13025 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13026 }
13027
13028 static void
13029 verify_disabled_dpll_state(struct drm_device *dev)
13030 {
13031 struct drm_i915_private *dev_priv = dev->dev_private;
13032 int i;
13033
13034 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13035 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13036 }
13037
13038 static void
13039 intel_modeset_verify_disabled(struct drm_device *dev)
13040 {
13041 verify_encoder_state(dev);
13042 verify_connector_state(dev, NULL);
13043 verify_disabled_dpll_state(dev);
13044 }
13045
13046 static void update_scanline_offset(struct intel_crtc *crtc)
13047 {
13048 struct drm_device *dev = crtc->base.dev;
13049
13050 /*
13051 * The scanline counter increments at the leading edge of hsync.
13052 *
13053 * On most platforms it starts counting from vtotal-1 on the
13054 * first active line. That means the scanline counter value is
13055 * always one less than what we would expect. Ie. just after
13056 * start of vblank, which also occurs at start of hsync (on the
13057 * last active line), the scanline counter will read vblank_start-1.
13058 *
13059 * On gen2 the scanline counter starts counting from 1 instead
13060 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13061 * to keep the value positive), instead of adding one.
13062 *
13063 * On HSW+ the behaviour of the scanline counter depends on the output
13064 * type. For DP ports it behaves like most other platforms, but on HDMI
13065 * there's an extra 1 line difference. So we need to add two instead of
13066 * one to the value.
13067 */
13068 if (IS_GEN2(dev)) {
13069 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13070 int vtotal;
13071
13072 vtotal = adjusted_mode->crtc_vtotal;
13073 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13074 vtotal /= 2;
13075
13076 crtc->scanline_offset = vtotal - 1;
13077 } else if (HAS_DDI(dev) &&
13078 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13079 crtc->scanline_offset = 2;
13080 } else
13081 crtc->scanline_offset = 1;
13082 }
13083
13084 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13085 {
13086 struct drm_device *dev = state->dev;
13087 struct drm_i915_private *dev_priv = to_i915(dev);
13088 struct intel_shared_dpll_config *shared_dpll = NULL;
13089 struct drm_crtc *crtc;
13090 struct drm_crtc_state *crtc_state;
13091 int i;
13092
13093 if (!dev_priv->display.crtc_compute_clock)
13094 return;
13095
13096 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13098 struct intel_shared_dpll *old_dpll =
13099 to_intel_crtc_state(crtc->state)->shared_dpll;
13100
13101 if (!needs_modeset(crtc_state))
13102 continue;
13103
13104 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13105
13106 if (!old_dpll)
13107 continue;
13108
13109 if (!shared_dpll)
13110 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13111
13112 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13113 }
13114 }
13115
13116 /*
13117 * This implements the workaround described in the "notes" section of the mode
13118 * set sequence documentation. When going from no pipes or single pipe to
13119 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13120 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13121 */
13122 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13123 {
13124 struct drm_crtc_state *crtc_state;
13125 struct intel_crtc *intel_crtc;
13126 struct drm_crtc *crtc;
13127 struct intel_crtc_state *first_crtc_state = NULL;
13128 struct intel_crtc_state *other_crtc_state = NULL;
13129 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13130 int i;
13131
13132 /* look at all crtc's that are going to be enabled in during modeset */
13133 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13134 intel_crtc = to_intel_crtc(crtc);
13135
13136 if (!crtc_state->active || !needs_modeset(crtc_state))
13137 continue;
13138
13139 if (first_crtc_state) {
13140 other_crtc_state = to_intel_crtc_state(crtc_state);
13141 break;
13142 } else {
13143 first_crtc_state = to_intel_crtc_state(crtc_state);
13144 first_pipe = intel_crtc->pipe;
13145 }
13146 }
13147
13148 /* No workaround needed? */
13149 if (!first_crtc_state)
13150 return 0;
13151
13152 /* w/a possibly needed, check how many crtc's are already enabled. */
13153 for_each_intel_crtc(state->dev, intel_crtc) {
13154 struct intel_crtc_state *pipe_config;
13155
13156 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13157 if (IS_ERR(pipe_config))
13158 return PTR_ERR(pipe_config);
13159
13160 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13161
13162 if (!pipe_config->base.active ||
13163 needs_modeset(&pipe_config->base))
13164 continue;
13165
13166 /* 2 or more enabled crtcs means no need for w/a */
13167 if (enabled_pipe != INVALID_PIPE)
13168 return 0;
13169
13170 enabled_pipe = intel_crtc->pipe;
13171 }
13172
13173 if (enabled_pipe != INVALID_PIPE)
13174 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13175 else if (other_crtc_state)
13176 other_crtc_state->hsw_workaround_pipe = first_pipe;
13177
13178 return 0;
13179 }
13180
13181 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13182 {
13183 struct drm_crtc *crtc;
13184 struct drm_crtc_state *crtc_state;
13185 int ret = 0;
13186
13187 /* add all active pipes to the state */
13188 for_each_crtc(state->dev, crtc) {
13189 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13190 if (IS_ERR(crtc_state))
13191 return PTR_ERR(crtc_state);
13192
13193 if (!crtc_state->active || needs_modeset(crtc_state))
13194 continue;
13195
13196 crtc_state->mode_changed = true;
13197
13198 ret = drm_atomic_add_affected_connectors(state, crtc);
13199 if (ret)
13200 break;
13201
13202 ret = drm_atomic_add_affected_planes(state, crtc);
13203 if (ret)
13204 break;
13205 }
13206
13207 return ret;
13208 }
13209
13210 static int intel_modeset_checks(struct drm_atomic_state *state)
13211 {
13212 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13213 struct drm_i915_private *dev_priv = state->dev->dev_private;
13214 struct drm_crtc *crtc;
13215 struct drm_crtc_state *crtc_state;
13216 int ret = 0, i;
13217
13218 if (!check_digital_port_conflicts(state)) {
13219 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13220 return -EINVAL;
13221 }
13222
13223 intel_state->modeset = true;
13224 intel_state->active_crtcs = dev_priv->active_crtcs;
13225
13226 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13227 if (crtc_state->active)
13228 intel_state->active_crtcs |= 1 << i;
13229 else
13230 intel_state->active_crtcs &= ~(1 << i);
13231 }
13232
13233 /*
13234 * See if the config requires any additional preparation, e.g.
13235 * to adjust global state with pipes off. We need to do this
13236 * here so we can get the modeset_pipe updated config for the new
13237 * mode set on this crtc. For other crtcs we need to use the
13238 * adjusted_mode bits in the crtc directly.
13239 */
13240 if (dev_priv->display.modeset_calc_cdclk) {
13241 ret = dev_priv->display.modeset_calc_cdclk(state);
13242
13243 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13244 ret = intel_modeset_all_pipes(state);
13245
13246 if (ret < 0)
13247 return ret;
13248
13249 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13250 intel_state->cdclk, intel_state->dev_cdclk);
13251 } else
13252 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13253
13254 intel_modeset_clear_plls(state);
13255
13256 if (IS_HASWELL(dev_priv))
13257 return haswell_mode_set_planes_workaround(state);
13258
13259 return 0;
13260 }
13261
13262 /*
13263 * Handle calculation of various watermark data at the end of the atomic check
13264 * phase. The code here should be run after the per-crtc and per-plane 'check'
13265 * handlers to ensure that all derived state has been updated.
13266 */
13267 static void calc_watermark_data(struct drm_atomic_state *state)
13268 {
13269 struct drm_device *dev = state->dev;
13270 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13271 struct drm_crtc *crtc;
13272 struct drm_crtc_state *cstate;
13273 struct drm_plane *plane;
13274 struct drm_plane_state *pstate;
13275
13276 /*
13277 * Calculate watermark configuration details now that derived
13278 * plane/crtc state is all properly updated.
13279 */
13280 drm_for_each_crtc(crtc, dev) {
13281 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13282 crtc->state;
13283
13284 if (cstate->active)
13285 intel_state->wm_config.num_pipes_active++;
13286 }
13287 drm_for_each_legacy_plane(plane, dev) {
13288 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13289 plane->state;
13290
13291 if (!to_intel_plane_state(pstate)->visible)
13292 continue;
13293
13294 intel_state->wm_config.sprites_enabled = true;
13295 if (pstate->crtc_w != pstate->src_w >> 16 ||
13296 pstate->crtc_h != pstate->src_h >> 16)
13297 intel_state->wm_config.sprites_scaled = true;
13298 }
13299 }
13300
13301 /**
13302 * intel_atomic_check - validate state object
13303 * @dev: drm device
13304 * @state: state to validate
13305 */
13306 static int intel_atomic_check(struct drm_device *dev,
13307 struct drm_atomic_state *state)
13308 {
13309 struct drm_i915_private *dev_priv = to_i915(dev);
13310 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13311 struct drm_crtc *crtc;
13312 struct drm_crtc_state *crtc_state;
13313 int ret, i;
13314 bool any_ms = false;
13315
13316 ret = drm_atomic_helper_check_modeset(dev, state);
13317 if (ret)
13318 return ret;
13319
13320 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13321 struct intel_crtc_state *pipe_config =
13322 to_intel_crtc_state(crtc_state);
13323
13324 /* Catch I915_MODE_FLAG_INHERITED */
13325 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13326 crtc_state->mode_changed = true;
13327
13328 if (!crtc_state->enable) {
13329 if (needs_modeset(crtc_state))
13330 any_ms = true;
13331 continue;
13332 }
13333
13334 if (!needs_modeset(crtc_state))
13335 continue;
13336
13337 /* FIXME: For only active_changed we shouldn't need to do any
13338 * state recomputation at all. */
13339
13340 ret = drm_atomic_add_affected_connectors(state, crtc);
13341 if (ret)
13342 return ret;
13343
13344 ret = intel_modeset_pipe_config(crtc, pipe_config);
13345 if (ret)
13346 return ret;
13347
13348 if (i915.fastboot &&
13349 intel_pipe_config_compare(dev,
13350 to_intel_crtc_state(crtc->state),
13351 pipe_config, true)) {
13352 crtc_state->mode_changed = false;
13353 to_intel_crtc_state(crtc_state)->update_pipe = true;
13354 }
13355
13356 if (needs_modeset(crtc_state)) {
13357 any_ms = true;
13358
13359 ret = drm_atomic_add_affected_planes(state, crtc);
13360 if (ret)
13361 return ret;
13362 }
13363
13364 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13365 needs_modeset(crtc_state) ?
13366 "[modeset]" : "[fastset]");
13367 }
13368
13369 if (any_ms) {
13370 ret = intel_modeset_checks(state);
13371
13372 if (ret)
13373 return ret;
13374 } else
13375 intel_state->cdclk = dev_priv->cdclk_freq;
13376
13377 ret = drm_atomic_helper_check_planes(dev, state);
13378 if (ret)
13379 return ret;
13380
13381 intel_fbc_choose_crtc(dev_priv, state);
13382 calc_watermark_data(state);
13383
13384 return 0;
13385 }
13386
13387 static int intel_atomic_prepare_commit(struct drm_device *dev,
13388 struct drm_atomic_state *state,
13389 bool async)
13390 {
13391 struct drm_i915_private *dev_priv = dev->dev_private;
13392 struct drm_plane_state *plane_state;
13393 struct drm_crtc_state *crtc_state;
13394 struct drm_plane *plane;
13395 struct drm_crtc *crtc;
13396 int i, ret;
13397
13398 if (async) {
13399 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13400 return -EINVAL;
13401 }
13402
13403 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13404 ret = intel_crtc_wait_for_pending_flips(crtc);
13405 if (ret)
13406 return ret;
13407
13408 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13409 flush_workqueue(dev_priv->wq);
13410 }
13411
13412 ret = mutex_lock_interruptible(&dev->struct_mutex);
13413 if (ret)
13414 return ret;
13415
13416 ret = drm_atomic_helper_prepare_planes(dev, state);
13417 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13418 u32 reset_counter;
13419
13420 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13421 mutex_unlock(&dev->struct_mutex);
13422
13423 for_each_plane_in_state(state, plane, plane_state, i) {
13424 struct intel_plane_state *intel_plane_state =
13425 to_intel_plane_state(plane_state);
13426
13427 if (!intel_plane_state->wait_req)
13428 continue;
13429
13430 ret = __i915_wait_request(intel_plane_state->wait_req,
13431 reset_counter, true,
13432 NULL, NULL);
13433
13434 /* Swallow -EIO errors to allow updates during hw lockup. */
13435 if (ret == -EIO)
13436 ret = 0;
13437
13438 if (ret)
13439 break;
13440 }
13441
13442 if (!ret)
13443 return 0;
13444
13445 mutex_lock(&dev->struct_mutex);
13446 drm_atomic_helper_cleanup_planes(dev, state);
13447 }
13448
13449 mutex_unlock(&dev->struct_mutex);
13450 return ret;
13451 }
13452
13453 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13454 struct drm_i915_private *dev_priv,
13455 unsigned crtc_mask)
13456 {
13457 unsigned last_vblank_count[I915_MAX_PIPES];
13458 enum pipe pipe;
13459 int ret;
13460
13461 if (!crtc_mask)
13462 return;
13463
13464 for_each_pipe(dev_priv, pipe) {
13465 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13466
13467 if (!((1 << pipe) & crtc_mask))
13468 continue;
13469
13470 ret = drm_crtc_vblank_get(crtc);
13471 if (WARN_ON(ret != 0)) {
13472 crtc_mask &= ~(1 << pipe);
13473 continue;
13474 }
13475
13476 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13477 }
13478
13479 for_each_pipe(dev_priv, pipe) {
13480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13481 long lret;
13482
13483 if (!((1 << pipe) & crtc_mask))
13484 continue;
13485
13486 lret = wait_event_timeout(dev->vblank[pipe].queue,
13487 last_vblank_count[pipe] !=
13488 drm_crtc_vblank_count(crtc),
13489 msecs_to_jiffies(50));
13490
13491 WARN_ON(!lret);
13492
13493 drm_crtc_vblank_put(crtc);
13494 }
13495 }
13496
13497 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13498 {
13499 /* fb updated, need to unpin old fb */
13500 if (crtc_state->fb_changed)
13501 return true;
13502
13503 /* wm changes, need vblank before final wm's */
13504 if (crtc_state->update_wm_post)
13505 return true;
13506
13507 /*
13508 * cxsr is re-enabled after vblank.
13509 * This is already handled by crtc_state->update_wm_post,
13510 * but added for clarity.
13511 */
13512 if (crtc_state->disable_cxsr)
13513 return true;
13514
13515 return false;
13516 }
13517
13518 /**
13519 * intel_atomic_commit - commit validated state object
13520 * @dev: DRM device
13521 * @state: the top-level driver state object
13522 * @async: asynchronous commit
13523 *
13524 * This function commits a top-level state object that has been validated
13525 * with drm_atomic_helper_check().
13526 *
13527 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13528 * we can only handle plane-related operations and do not yet support
13529 * asynchronous commit.
13530 *
13531 * RETURNS
13532 * Zero for success or -errno.
13533 */
13534 static int intel_atomic_commit(struct drm_device *dev,
13535 struct drm_atomic_state *state,
13536 bool async)
13537 {
13538 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13539 struct drm_i915_private *dev_priv = dev->dev_private;
13540 struct drm_crtc_state *old_crtc_state;
13541 struct drm_crtc *crtc;
13542 struct intel_crtc_state *intel_cstate;
13543 int ret = 0, i;
13544 bool hw_check = intel_state->modeset;
13545 unsigned long put_domains[I915_MAX_PIPES] = {};
13546 unsigned crtc_vblank_mask = 0;
13547
13548 ret = intel_atomic_prepare_commit(dev, state, async);
13549 if (ret) {
13550 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13551 return ret;
13552 }
13553
13554 drm_atomic_helper_swap_state(dev, state);
13555 dev_priv->wm.config = intel_state->wm_config;
13556 intel_shared_dpll_commit(state);
13557
13558 if (intel_state->modeset) {
13559 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13560 sizeof(intel_state->min_pixclk));
13561 dev_priv->active_crtcs = intel_state->active_crtcs;
13562 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13563
13564 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13565 }
13566
13567 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13569
13570 if (needs_modeset(crtc->state) ||
13571 to_intel_crtc_state(crtc->state)->update_pipe) {
13572 hw_check = true;
13573
13574 put_domains[to_intel_crtc(crtc)->pipe] =
13575 modeset_get_crtc_power_domains(crtc,
13576 to_intel_crtc_state(crtc->state));
13577 }
13578
13579 if (!needs_modeset(crtc->state))
13580 continue;
13581
13582 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13583
13584 if (old_crtc_state->active) {
13585 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13586 dev_priv->display.crtc_disable(crtc);
13587 intel_crtc->active = false;
13588 intel_fbc_disable(intel_crtc);
13589 intel_disable_shared_dpll(intel_crtc);
13590
13591 /*
13592 * Underruns don't always raise
13593 * interrupts, so check manually.
13594 */
13595 intel_check_cpu_fifo_underruns(dev_priv);
13596 intel_check_pch_fifo_underruns(dev_priv);
13597
13598 if (!crtc->state->active)
13599 intel_update_watermarks(crtc);
13600 }
13601 }
13602
13603 /* Only after disabling all output pipelines that will be changed can we
13604 * update the the output configuration. */
13605 intel_modeset_update_crtc_state(state);
13606
13607 if (intel_state->modeset) {
13608 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13609
13610 if (dev_priv->display.modeset_commit_cdclk &&
13611 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13612 dev_priv->display.modeset_commit_cdclk(state);
13613
13614 intel_modeset_verify_disabled(dev);
13615 }
13616
13617 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13618 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13620 bool modeset = needs_modeset(crtc->state);
13621 struct intel_crtc_state *pipe_config =
13622 to_intel_crtc_state(crtc->state);
13623 bool update_pipe = !modeset && pipe_config->update_pipe;
13624
13625 if (modeset && crtc->state->active) {
13626 update_scanline_offset(to_intel_crtc(crtc));
13627 dev_priv->display.crtc_enable(crtc);
13628 }
13629
13630 if (!modeset)
13631 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13632
13633 if (crtc->state->active &&
13634 drm_atomic_get_existing_plane_state(state, crtc->primary))
13635 intel_fbc_enable(intel_crtc);
13636
13637 if (crtc->state->active &&
13638 (crtc->state->planes_changed || update_pipe))
13639 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13640
13641 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13642 crtc_vblank_mask |= 1 << i;
13643 }
13644
13645 /* FIXME: add subpixel order */
13646
13647 if (!state->legacy_cursor_update)
13648 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13649
13650 /*
13651 * Now that the vblank has passed, we can go ahead and program the
13652 * optimal watermarks on platforms that need two-step watermark
13653 * programming.
13654 *
13655 * TODO: Move this (and other cleanup) to an async worker eventually.
13656 */
13657 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13658 intel_cstate = to_intel_crtc_state(crtc->state);
13659
13660 if (dev_priv->display.optimize_watermarks)
13661 dev_priv->display.optimize_watermarks(intel_cstate);
13662 }
13663
13664 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13665 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13666
13667 if (put_domains[i])
13668 modeset_put_power_domains(dev_priv, put_domains[i]);
13669
13670 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13671 }
13672
13673 if (intel_state->modeset)
13674 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13675
13676 mutex_lock(&dev->struct_mutex);
13677 drm_atomic_helper_cleanup_planes(dev, state);
13678 mutex_unlock(&dev->struct_mutex);
13679
13680 drm_atomic_state_free(state);
13681
13682 /* As one of the primary mmio accessors, KMS has a high likelihood
13683 * of triggering bugs in unclaimed access. After we finish
13684 * modesetting, see if an error has been flagged, and if so
13685 * enable debugging for the next modeset - and hope we catch
13686 * the culprit.
13687 *
13688 * XXX note that we assume display power is on at this point.
13689 * This might hold true now but we need to add pm helper to check
13690 * unclaimed only when the hardware is on, as atomic commits
13691 * can happen also when the device is completely off.
13692 */
13693 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13694
13695 return 0;
13696 }
13697
13698 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13699 {
13700 struct drm_device *dev = crtc->dev;
13701 struct drm_atomic_state *state;
13702 struct drm_crtc_state *crtc_state;
13703 int ret;
13704
13705 state = drm_atomic_state_alloc(dev);
13706 if (!state) {
13707 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13708 crtc->base.id);
13709 return;
13710 }
13711
13712 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13713
13714 retry:
13715 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13716 ret = PTR_ERR_OR_ZERO(crtc_state);
13717 if (!ret) {
13718 if (!crtc_state->active)
13719 goto out;
13720
13721 crtc_state->mode_changed = true;
13722 ret = drm_atomic_commit(state);
13723 }
13724
13725 if (ret == -EDEADLK) {
13726 drm_atomic_state_clear(state);
13727 drm_modeset_backoff(state->acquire_ctx);
13728 goto retry;
13729 }
13730
13731 if (ret)
13732 out:
13733 drm_atomic_state_free(state);
13734 }
13735
13736 #undef for_each_intel_crtc_masked
13737
13738 static const struct drm_crtc_funcs intel_crtc_funcs = {
13739 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13740 .set_config = drm_atomic_helper_set_config,
13741 .set_property = drm_atomic_helper_crtc_set_property,
13742 .destroy = intel_crtc_destroy,
13743 .page_flip = intel_crtc_page_flip,
13744 .atomic_duplicate_state = intel_crtc_duplicate_state,
13745 .atomic_destroy_state = intel_crtc_destroy_state,
13746 };
13747
13748 /**
13749 * intel_prepare_plane_fb - Prepare fb for usage on plane
13750 * @plane: drm plane to prepare for
13751 * @fb: framebuffer to prepare for presentation
13752 *
13753 * Prepares a framebuffer for usage on a display plane. Generally this
13754 * involves pinning the underlying object and updating the frontbuffer tracking
13755 * bits. Some older platforms need special physical address handling for
13756 * cursor planes.
13757 *
13758 * Must be called with struct_mutex held.
13759 *
13760 * Returns 0 on success, negative error code on failure.
13761 */
13762 int
13763 intel_prepare_plane_fb(struct drm_plane *plane,
13764 const struct drm_plane_state *new_state)
13765 {
13766 struct drm_device *dev = plane->dev;
13767 struct drm_framebuffer *fb = new_state->fb;
13768 struct intel_plane *intel_plane = to_intel_plane(plane);
13769 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13770 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13771 int ret = 0;
13772
13773 if (!obj && !old_obj)
13774 return 0;
13775
13776 if (old_obj) {
13777 struct drm_crtc_state *crtc_state =
13778 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13779
13780 /* Big Hammer, we also need to ensure that any pending
13781 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13782 * current scanout is retired before unpinning the old
13783 * framebuffer. Note that we rely on userspace rendering
13784 * into the buffer attached to the pipe they are waiting
13785 * on. If not, userspace generates a GPU hang with IPEHR
13786 * point to the MI_WAIT_FOR_EVENT.
13787 *
13788 * This should only fail upon a hung GPU, in which case we
13789 * can safely continue.
13790 */
13791 if (needs_modeset(crtc_state))
13792 ret = i915_gem_object_wait_rendering(old_obj, true);
13793
13794 /* Swallow -EIO errors to allow updates during hw lockup. */
13795 if (ret && ret != -EIO)
13796 return ret;
13797 }
13798
13799 /* For framebuffer backed by dmabuf, wait for fence */
13800 if (obj && obj->base.dma_buf) {
13801 long lret;
13802
13803 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13804 false, true,
13805 MAX_SCHEDULE_TIMEOUT);
13806 if (lret == -ERESTARTSYS)
13807 return lret;
13808
13809 WARN(lret < 0, "waiting returns %li\n", lret);
13810 }
13811
13812 if (!obj) {
13813 ret = 0;
13814 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13815 INTEL_INFO(dev)->cursor_needs_physical) {
13816 int align = IS_I830(dev) ? 16 * 1024 : 256;
13817 ret = i915_gem_object_attach_phys(obj, align);
13818 if (ret)
13819 DRM_DEBUG_KMS("failed to attach phys object\n");
13820 } else {
13821 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13822 }
13823
13824 if (ret == 0) {
13825 if (obj) {
13826 struct intel_plane_state *plane_state =
13827 to_intel_plane_state(new_state);
13828
13829 i915_gem_request_assign(&plane_state->wait_req,
13830 obj->last_write_req);
13831 }
13832
13833 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13834 }
13835
13836 return ret;
13837 }
13838
13839 /**
13840 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13841 * @plane: drm plane to clean up for
13842 * @fb: old framebuffer that was on plane
13843 *
13844 * Cleans up a framebuffer that has just been removed from a plane.
13845 *
13846 * Must be called with struct_mutex held.
13847 */
13848 void
13849 intel_cleanup_plane_fb(struct drm_plane *plane,
13850 const struct drm_plane_state *old_state)
13851 {
13852 struct drm_device *dev = plane->dev;
13853 struct intel_plane *intel_plane = to_intel_plane(plane);
13854 struct intel_plane_state *old_intel_state;
13855 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13856 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13857
13858 old_intel_state = to_intel_plane_state(old_state);
13859
13860 if (!obj && !old_obj)
13861 return;
13862
13863 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13864 !INTEL_INFO(dev)->cursor_needs_physical))
13865 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13866
13867 /* prepare_fb aborted? */
13868 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13869 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13870 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13871
13872 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13873 }
13874
13875 int
13876 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13877 {
13878 int max_scale;
13879 struct drm_device *dev;
13880 struct drm_i915_private *dev_priv;
13881 int crtc_clock, cdclk;
13882
13883 if (!intel_crtc || !crtc_state->base.enable)
13884 return DRM_PLANE_HELPER_NO_SCALING;
13885
13886 dev = intel_crtc->base.dev;
13887 dev_priv = dev->dev_private;
13888 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13889 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13890
13891 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13892 return DRM_PLANE_HELPER_NO_SCALING;
13893
13894 /*
13895 * skl max scale is lower of:
13896 * close to 3 but not 3, -1 is for that purpose
13897 * or
13898 * cdclk/crtc_clock
13899 */
13900 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13901
13902 return max_scale;
13903 }
13904
13905 static int
13906 intel_check_primary_plane(struct drm_plane *plane,
13907 struct intel_crtc_state *crtc_state,
13908 struct intel_plane_state *state)
13909 {
13910 struct drm_crtc *crtc = state->base.crtc;
13911 struct drm_framebuffer *fb = state->base.fb;
13912 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13913 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13914 bool can_position = false;
13915
13916 if (INTEL_INFO(plane->dev)->gen >= 9) {
13917 /* use scaler when colorkey is not required */
13918 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13919 min_scale = 1;
13920 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13921 }
13922 can_position = true;
13923 }
13924
13925 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13926 &state->dst, &state->clip,
13927 min_scale, max_scale,
13928 can_position, true,
13929 &state->visible);
13930 }
13931
13932 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13933 struct drm_crtc_state *old_crtc_state)
13934 {
13935 struct drm_device *dev = crtc->dev;
13936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13937 struct intel_crtc_state *old_intel_state =
13938 to_intel_crtc_state(old_crtc_state);
13939 bool modeset = needs_modeset(crtc->state);
13940
13941 /* Perform vblank evasion around commit operation */
13942 intel_pipe_update_start(intel_crtc);
13943
13944 if (modeset)
13945 return;
13946
13947 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13948 intel_color_set_csc(crtc->state);
13949 intel_color_load_luts(crtc->state);
13950 }
13951
13952 if (to_intel_crtc_state(crtc->state)->update_pipe)
13953 intel_update_pipe_config(intel_crtc, old_intel_state);
13954 else if (INTEL_INFO(dev)->gen >= 9)
13955 skl_detach_scalers(intel_crtc);
13956 }
13957
13958 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13959 struct drm_crtc_state *old_crtc_state)
13960 {
13961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13962
13963 intel_pipe_update_end(intel_crtc);
13964 }
13965
13966 /**
13967 * intel_plane_destroy - destroy a plane
13968 * @plane: plane to destroy
13969 *
13970 * Common destruction function for all types of planes (primary, cursor,
13971 * sprite).
13972 */
13973 void intel_plane_destroy(struct drm_plane *plane)
13974 {
13975 struct intel_plane *intel_plane = to_intel_plane(plane);
13976 drm_plane_cleanup(plane);
13977 kfree(intel_plane);
13978 }
13979
13980 const struct drm_plane_funcs intel_plane_funcs = {
13981 .update_plane = drm_atomic_helper_update_plane,
13982 .disable_plane = drm_atomic_helper_disable_plane,
13983 .destroy = intel_plane_destroy,
13984 .set_property = drm_atomic_helper_plane_set_property,
13985 .atomic_get_property = intel_plane_atomic_get_property,
13986 .atomic_set_property = intel_plane_atomic_set_property,
13987 .atomic_duplicate_state = intel_plane_duplicate_state,
13988 .atomic_destroy_state = intel_plane_destroy_state,
13989
13990 };
13991
13992 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13993 int pipe)
13994 {
13995 struct intel_plane *primary = NULL;
13996 struct intel_plane_state *state = NULL;
13997 const uint32_t *intel_primary_formats;
13998 unsigned int num_formats;
13999 int ret;
14000
14001 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14002 if (!primary)
14003 goto fail;
14004
14005 state = intel_create_plane_state(&primary->base);
14006 if (!state)
14007 goto fail;
14008 primary->base.state = &state->base;
14009
14010 primary->can_scale = false;
14011 primary->max_downscale = 1;
14012 if (INTEL_INFO(dev)->gen >= 9) {
14013 primary->can_scale = true;
14014 state->scaler_id = -1;
14015 }
14016 primary->pipe = pipe;
14017 primary->plane = pipe;
14018 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14019 primary->check_plane = intel_check_primary_plane;
14020 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14021 primary->plane = !pipe;
14022
14023 if (INTEL_INFO(dev)->gen >= 9) {
14024 intel_primary_formats = skl_primary_formats;
14025 num_formats = ARRAY_SIZE(skl_primary_formats);
14026
14027 primary->update_plane = skylake_update_primary_plane;
14028 primary->disable_plane = skylake_disable_primary_plane;
14029 } else if (HAS_PCH_SPLIT(dev)) {
14030 intel_primary_formats = i965_primary_formats;
14031 num_formats = ARRAY_SIZE(i965_primary_formats);
14032
14033 primary->update_plane = ironlake_update_primary_plane;
14034 primary->disable_plane = i9xx_disable_primary_plane;
14035 } else if (INTEL_INFO(dev)->gen >= 4) {
14036 intel_primary_formats = i965_primary_formats;
14037 num_formats = ARRAY_SIZE(i965_primary_formats);
14038
14039 primary->update_plane = i9xx_update_primary_plane;
14040 primary->disable_plane = i9xx_disable_primary_plane;
14041 } else {
14042 intel_primary_formats = i8xx_primary_formats;
14043 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14044
14045 primary->update_plane = i9xx_update_primary_plane;
14046 primary->disable_plane = i9xx_disable_primary_plane;
14047 }
14048
14049 ret = drm_universal_plane_init(dev, &primary->base, 0,
14050 &intel_plane_funcs,
14051 intel_primary_formats, num_formats,
14052 DRM_PLANE_TYPE_PRIMARY, NULL);
14053 if (ret)
14054 goto fail;
14055
14056 if (INTEL_INFO(dev)->gen >= 4)
14057 intel_create_rotation_property(dev, primary);
14058
14059 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14060
14061 return &primary->base;
14062
14063 fail:
14064 kfree(state);
14065 kfree(primary);
14066
14067 return NULL;
14068 }
14069
14070 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14071 {
14072 if (!dev->mode_config.rotation_property) {
14073 unsigned long flags = BIT(DRM_ROTATE_0) |
14074 BIT(DRM_ROTATE_180);
14075
14076 if (INTEL_INFO(dev)->gen >= 9)
14077 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14078
14079 dev->mode_config.rotation_property =
14080 drm_mode_create_rotation_property(dev, flags);
14081 }
14082 if (dev->mode_config.rotation_property)
14083 drm_object_attach_property(&plane->base.base,
14084 dev->mode_config.rotation_property,
14085 plane->base.state->rotation);
14086 }
14087
14088 static int
14089 intel_check_cursor_plane(struct drm_plane *plane,
14090 struct intel_crtc_state *crtc_state,
14091 struct intel_plane_state *state)
14092 {
14093 struct drm_crtc *crtc = crtc_state->base.crtc;
14094 struct drm_framebuffer *fb = state->base.fb;
14095 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14096 enum pipe pipe = to_intel_plane(plane)->pipe;
14097 unsigned stride;
14098 int ret;
14099
14100 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14101 &state->dst, &state->clip,
14102 DRM_PLANE_HELPER_NO_SCALING,
14103 DRM_PLANE_HELPER_NO_SCALING,
14104 true, true, &state->visible);
14105 if (ret)
14106 return ret;
14107
14108 /* if we want to turn off the cursor ignore width and height */
14109 if (!obj)
14110 return 0;
14111
14112 /* Check for which cursor types we support */
14113 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14114 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14115 state->base.crtc_w, state->base.crtc_h);
14116 return -EINVAL;
14117 }
14118
14119 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14120 if (obj->base.size < stride * state->base.crtc_h) {
14121 DRM_DEBUG_KMS("buffer is too small\n");
14122 return -ENOMEM;
14123 }
14124
14125 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14126 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14127 return -EINVAL;
14128 }
14129
14130 /*
14131 * There's something wrong with the cursor on CHV pipe C.
14132 * If it straddles the left edge of the screen then
14133 * moving it away from the edge or disabling it often
14134 * results in a pipe underrun, and often that can lead to
14135 * dead pipe (constant underrun reported, and it scans
14136 * out just a solid color). To recover from that, the
14137 * display power well must be turned off and on again.
14138 * Refuse the put the cursor into that compromised position.
14139 */
14140 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14141 state->visible && state->base.crtc_x < 0) {
14142 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14143 return -EINVAL;
14144 }
14145
14146 return 0;
14147 }
14148
14149 static void
14150 intel_disable_cursor_plane(struct drm_plane *plane,
14151 struct drm_crtc *crtc)
14152 {
14153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14154
14155 intel_crtc->cursor_addr = 0;
14156 intel_crtc_update_cursor(crtc, NULL);
14157 }
14158
14159 static void
14160 intel_update_cursor_plane(struct drm_plane *plane,
14161 const struct intel_crtc_state *crtc_state,
14162 const struct intel_plane_state *state)
14163 {
14164 struct drm_crtc *crtc = crtc_state->base.crtc;
14165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14166 struct drm_device *dev = plane->dev;
14167 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14168 uint32_t addr;
14169
14170 if (!obj)
14171 addr = 0;
14172 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14173 addr = i915_gem_obj_ggtt_offset(obj);
14174 else
14175 addr = obj->phys_handle->busaddr;
14176
14177 intel_crtc->cursor_addr = addr;
14178 intel_crtc_update_cursor(crtc, state);
14179 }
14180
14181 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14182 int pipe)
14183 {
14184 struct intel_plane *cursor = NULL;
14185 struct intel_plane_state *state = NULL;
14186 int ret;
14187
14188 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14189 if (!cursor)
14190 goto fail;
14191
14192 state = intel_create_plane_state(&cursor->base);
14193 if (!state)
14194 goto fail;
14195 cursor->base.state = &state->base;
14196
14197 cursor->can_scale = false;
14198 cursor->max_downscale = 1;
14199 cursor->pipe = pipe;
14200 cursor->plane = pipe;
14201 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14202 cursor->check_plane = intel_check_cursor_plane;
14203 cursor->update_plane = intel_update_cursor_plane;
14204 cursor->disable_plane = intel_disable_cursor_plane;
14205
14206 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14207 &intel_plane_funcs,
14208 intel_cursor_formats,
14209 ARRAY_SIZE(intel_cursor_formats),
14210 DRM_PLANE_TYPE_CURSOR, NULL);
14211 if (ret)
14212 goto fail;
14213
14214 if (INTEL_INFO(dev)->gen >= 4) {
14215 if (!dev->mode_config.rotation_property)
14216 dev->mode_config.rotation_property =
14217 drm_mode_create_rotation_property(dev,
14218 BIT(DRM_ROTATE_0) |
14219 BIT(DRM_ROTATE_180));
14220 if (dev->mode_config.rotation_property)
14221 drm_object_attach_property(&cursor->base.base,
14222 dev->mode_config.rotation_property,
14223 state->base.rotation);
14224 }
14225
14226 if (INTEL_INFO(dev)->gen >=9)
14227 state->scaler_id = -1;
14228
14229 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14230
14231 return &cursor->base;
14232
14233 fail:
14234 kfree(state);
14235 kfree(cursor);
14236
14237 return NULL;
14238 }
14239
14240 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14241 struct intel_crtc_state *crtc_state)
14242 {
14243 int i;
14244 struct intel_scaler *intel_scaler;
14245 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14246
14247 for (i = 0; i < intel_crtc->num_scalers; i++) {
14248 intel_scaler = &scaler_state->scalers[i];
14249 intel_scaler->in_use = 0;
14250 intel_scaler->mode = PS_SCALER_MODE_DYN;
14251 }
14252
14253 scaler_state->scaler_id = -1;
14254 }
14255
14256 static void intel_crtc_init(struct drm_device *dev, int pipe)
14257 {
14258 struct drm_i915_private *dev_priv = dev->dev_private;
14259 struct intel_crtc *intel_crtc;
14260 struct intel_crtc_state *crtc_state = NULL;
14261 struct drm_plane *primary = NULL;
14262 struct drm_plane *cursor = NULL;
14263 int ret;
14264
14265 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14266 if (intel_crtc == NULL)
14267 return;
14268
14269 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14270 if (!crtc_state)
14271 goto fail;
14272 intel_crtc->config = crtc_state;
14273 intel_crtc->base.state = &crtc_state->base;
14274 crtc_state->base.crtc = &intel_crtc->base;
14275
14276 /* initialize shared scalers */
14277 if (INTEL_INFO(dev)->gen >= 9) {
14278 if (pipe == PIPE_C)
14279 intel_crtc->num_scalers = 1;
14280 else
14281 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14282
14283 skl_init_scalers(dev, intel_crtc, crtc_state);
14284 }
14285
14286 primary = intel_primary_plane_create(dev, pipe);
14287 if (!primary)
14288 goto fail;
14289
14290 cursor = intel_cursor_plane_create(dev, pipe);
14291 if (!cursor)
14292 goto fail;
14293
14294 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14295 cursor, &intel_crtc_funcs, NULL);
14296 if (ret)
14297 goto fail;
14298
14299 /*
14300 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14301 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14302 */
14303 intel_crtc->pipe = pipe;
14304 intel_crtc->plane = pipe;
14305 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14306 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14307 intel_crtc->plane = !pipe;
14308 }
14309
14310 intel_crtc->cursor_base = ~0;
14311 intel_crtc->cursor_cntl = ~0;
14312 intel_crtc->cursor_size = ~0;
14313
14314 intel_crtc->wm.cxsr_allowed = true;
14315
14316 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14317 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14318 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14319 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14320
14321 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14322
14323 intel_color_init(&intel_crtc->base);
14324
14325 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14326 return;
14327
14328 fail:
14329 if (primary)
14330 drm_plane_cleanup(primary);
14331 if (cursor)
14332 drm_plane_cleanup(cursor);
14333 kfree(crtc_state);
14334 kfree(intel_crtc);
14335 }
14336
14337 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14338 {
14339 struct drm_encoder *encoder = connector->base.encoder;
14340 struct drm_device *dev = connector->base.dev;
14341
14342 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14343
14344 if (!encoder || WARN_ON(!encoder->crtc))
14345 return INVALID_PIPE;
14346
14347 return to_intel_crtc(encoder->crtc)->pipe;
14348 }
14349
14350 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14351 struct drm_file *file)
14352 {
14353 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14354 struct drm_crtc *drmmode_crtc;
14355 struct intel_crtc *crtc;
14356
14357 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14358
14359 if (!drmmode_crtc) {
14360 DRM_ERROR("no such CRTC id\n");
14361 return -ENOENT;
14362 }
14363
14364 crtc = to_intel_crtc(drmmode_crtc);
14365 pipe_from_crtc_id->pipe = crtc->pipe;
14366
14367 return 0;
14368 }
14369
14370 static int intel_encoder_clones(struct intel_encoder *encoder)
14371 {
14372 struct drm_device *dev = encoder->base.dev;
14373 struct intel_encoder *source_encoder;
14374 int index_mask = 0;
14375 int entry = 0;
14376
14377 for_each_intel_encoder(dev, source_encoder) {
14378 if (encoders_cloneable(encoder, source_encoder))
14379 index_mask |= (1 << entry);
14380
14381 entry++;
14382 }
14383
14384 return index_mask;
14385 }
14386
14387 static bool has_edp_a(struct drm_device *dev)
14388 {
14389 struct drm_i915_private *dev_priv = dev->dev_private;
14390
14391 if (!IS_MOBILE(dev))
14392 return false;
14393
14394 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14395 return false;
14396
14397 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14398 return false;
14399
14400 return true;
14401 }
14402
14403 static bool intel_crt_present(struct drm_device *dev)
14404 {
14405 struct drm_i915_private *dev_priv = dev->dev_private;
14406
14407 if (INTEL_INFO(dev)->gen >= 9)
14408 return false;
14409
14410 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14411 return false;
14412
14413 if (IS_CHERRYVIEW(dev))
14414 return false;
14415
14416 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14417 return false;
14418
14419 /* DDI E can't be used if DDI A requires 4 lanes */
14420 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14421 return false;
14422
14423 if (!dev_priv->vbt.int_crt_support)
14424 return false;
14425
14426 return true;
14427 }
14428
14429 static void intel_setup_outputs(struct drm_device *dev)
14430 {
14431 struct drm_i915_private *dev_priv = dev->dev_private;
14432 struct intel_encoder *encoder;
14433 bool dpd_is_edp = false;
14434
14435 intel_lvds_init(dev);
14436
14437 if (intel_crt_present(dev))
14438 intel_crt_init(dev);
14439
14440 if (IS_BROXTON(dev)) {
14441 /*
14442 * FIXME: Broxton doesn't support port detection via the
14443 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14444 * detect the ports.
14445 */
14446 intel_ddi_init(dev, PORT_A);
14447 intel_ddi_init(dev, PORT_B);
14448 intel_ddi_init(dev, PORT_C);
14449
14450 intel_dsi_init(dev);
14451 } else if (HAS_DDI(dev)) {
14452 int found;
14453
14454 /*
14455 * Haswell uses DDI functions to detect digital outputs.
14456 * On SKL pre-D0 the strap isn't connected, so we assume
14457 * it's there.
14458 */
14459 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14460 /* WaIgnoreDDIAStrap: skl */
14461 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14462 intel_ddi_init(dev, PORT_A);
14463
14464 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14465 * register */
14466 found = I915_READ(SFUSE_STRAP);
14467
14468 if (found & SFUSE_STRAP_DDIB_DETECTED)
14469 intel_ddi_init(dev, PORT_B);
14470 if (found & SFUSE_STRAP_DDIC_DETECTED)
14471 intel_ddi_init(dev, PORT_C);
14472 if (found & SFUSE_STRAP_DDID_DETECTED)
14473 intel_ddi_init(dev, PORT_D);
14474 /*
14475 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14476 */
14477 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14478 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14479 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14480 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14481 intel_ddi_init(dev, PORT_E);
14482
14483 } else if (HAS_PCH_SPLIT(dev)) {
14484 int found;
14485 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14486
14487 if (has_edp_a(dev))
14488 intel_dp_init(dev, DP_A, PORT_A);
14489
14490 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14491 /* PCH SDVOB multiplex with HDMIB */
14492 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14493 if (!found)
14494 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14495 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14496 intel_dp_init(dev, PCH_DP_B, PORT_B);
14497 }
14498
14499 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14500 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14501
14502 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14503 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14504
14505 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14506 intel_dp_init(dev, PCH_DP_C, PORT_C);
14507
14508 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14509 intel_dp_init(dev, PCH_DP_D, PORT_D);
14510 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14511 /*
14512 * The DP_DETECTED bit is the latched state of the DDC
14513 * SDA pin at boot. However since eDP doesn't require DDC
14514 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14515 * eDP ports may have been muxed to an alternate function.
14516 * Thus we can't rely on the DP_DETECTED bit alone to detect
14517 * eDP ports. Consult the VBT as well as DP_DETECTED to
14518 * detect eDP ports.
14519 */
14520 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14521 !intel_dp_is_edp(dev, PORT_B))
14522 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14523 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14524 intel_dp_is_edp(dev, PORT_B))
14525 intel_dp_init(dev, VLV_DP_B, PORT_B);
14526
14527 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14528 !intel_dp_is_edp(dev, PORT_C))
14529 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14530 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14531 intel_dp_is_edp(dev, PORT_C))
14532 intel_dp_init(dev, VLV_DP_C, PORT_C);
14533
14534 if (IS_CHERRYVIEW(dev)) {
14535 /* eDP not supported on port D, so don't check VBT */
14536 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14537 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14538 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14539 intel_dp_init(dev, CHV_DP_D, PORT_D);
14540 }
14541
14542 intel_dsi_init(dev);
14543 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14544 bool found = false;
14545
14546 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14547 DRM_DEBUG_KMS("probing SDVOB\n");
14548 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14549 if (!found && IS_G4X(dev)) {
14550 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14551 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14552 }
14553
14554 if (!found && IS_G4X(dev))
14555 intel_dp_init(dev, DP_B, PORT_B);
14556 }
14557
14558 /* Before G4X SDVOC doesn't have its own detect register */
14559
14560 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14561 DRM_DEBUG_KMS("probing SDVOC\n");
14562 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14563 }
14564
14565 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14566
14567 if (IS_G4X(dev)) {
14568 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14569 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14570 }
14571 if (IS_G4X(dev))
14572 intel_dp_init(dev, DP_C, PORT_C);
14573 }
14574
14575 if (IS_G4X(dev) &&
14576 (I915_READ(DP_D) & DP_DETECTED))
14577 intel_dp_init(dev, DP_D, PORT_D);
14578 } else if (IS_GEN2(dev))
14579 intel_dvo_init(dev);
14580
14581 if (SUPPORTS_TV(dev))
14582 intel_tv_init(dev);
14583
14584 intel_psr_init(dev);
14585
14586 for_each_intel_encoder(dev, encoder) {
14587 encoder->base.possible_crtcs = encoder->crtc_mask;
14588 encoder->base.possible_clones =
14589 intel_encoder_clones(encoder);
14590 }
14591
14592 intel_init_pch_refclk(dev);
14593
14594 drm_helper_move_panel_connectors_to_head(dev);
14595 }
14596
14597 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14598 {
14599 struct drm_device *dev = fb->dev;
14600 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14601
14602 drm_framebuffer_cleanup(fb);
14603 mutex_lock(&dev->struct_mutex);
14604 WARN_ON(!intel_fb->obj->framebuffer_references--);
14605 drm_gem_object_unreference(&intel_fb->obj->base);
14606 mutex_unlock(&dev->struct_mutex);
14607 kfree(intel_fb);
14608 }
14609
14610 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14611 struct drm_file *file,
14612 unsigned int *handle)
14613 {
14614 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14615 struct drm_i915_gem_object *obj = intel_fb->obj;
14616
14617 if (obj->userptr.mm) {
14618 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14619 return -EINVAL;
14620 }
14621
14622 return drm_gem_handle_create(file, &obj->base, handle);
14623 }
14624
14625 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14626 struct drm_file *file,
14627 unsigned flags, unsigned color,
14628 struct drm_clip_rect *clips,
14629 unsigned num_clips)
14630 {
14631 struct drm_device *dev = fb->dev;
14632 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14633 struct drm_i915_gem_object *obj = intel_fb->obj;
14634
14635 mutex_lock(&dev->struct_mutex);
14636 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14637 mutex_unlock(&dev->struct_mutex);
14638
14639 return 0;
14640 }
14641
14642 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14643 .destroy = intel_user_framebuffer_destroy,
14644 .create_handle = intel_user_framebuffer_create_handle,
14645 .dirty = intel_user_framebuffer_dirty,
14646 };
14647
14648 static
14649 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14650 uint32_t pixel_format)
14651 {
14652 u32 gen = INTEL_INFO(dev)->gen;
14653
14654 if (gen >= 9) {
14655 int cpp = drm_format_plane_cpp(pixel_format, 0);
14656
14657 /* "The stride in bytes must not exceed the of the size of 8K
14658 * pixels and 32K bytes."
14659 */
14660 return min(8192 * cpp, 32768);
14661 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14662 return 32*1024;
14663 } else if (gen >= 4) {
14664 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14665 return 16*1024;
14666 else
14667 return 32*1024;
14668 } else if (gen >= 3) {
14669 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14670 return 8*1024;
14671 else
14672 return 16*1024;
14673 } else {
14674 /* XXX DSPC is limited to 4k tiled */
14675 return 8*1024;
14676 }
14677 }
14678
14679 static int intel_framebuffer_init(struct drm_device *dev,
14680 struct intel_framebuffer *intel_fb,
14681 struct drm_mode_fb_cmd2 *mode_cmd,
14682 struct drm_i915_gem_object *obj)
14683 {
14684 struct drm_i915_private *dev_priv = to_i915(dev);
14685 unsigned int aligned_height;
14686 int ret;
14687 u32 pitch_limit, stride_alignment;
14688
14689 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14690
14691 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14692 /* Enforce that fb modifier and tiling mode match, but only for
14693 * X-tiled. This is needed for FBC. */
14694 if (!!(obj->tiling_mode == I915_TILING_X) !=
14695 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14696 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14697 return -EINVAL;
14698 }
14699 } else {
14700 if (obj->tiling_mode == I915_TILING_X)
14701 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14702 else if (obj->tiling_mode == I915_TILING_Y) {
14703 DRM_DEBUG("No Y tiling for legacy addfb\n");
14704 return -EINVAL;
14705 }
14706 }
14707
14708 /* Passed in modifier sanity checking. */
14709 switch (mode_cmd->modifier[0]) {
14710 case I915_FORMAT_MOD_Y_TILED:
14711 case I915_FORMAT_MOD_Yf_TILED:
14712 if (INTEL_INFO(dev)->gen < 9) {
14713 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14714 mode_cmd->modifier[0]);
14715 return -EINVAL;
14716 }
14717 case DRM_FORMAT_MOD_NONE:
14718 case I915_FORMAT_MOD_X_TILED:
14719 break;
14720 default:
14721 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14722 mode_cmd->modifier[0]);
14723 return -EINVAL;
14724 }
14725
14726 stride_alignment = intel_fb_stride_alignment(dev_priv,
14727 mode_cmd->modifier[0],
14728 mode_cmd->pixel_format);
14729 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14730 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14731 mode_cmd->pitches[0], stride_alignment);
14732 return -EINVAL;
14733 }
14734
14735 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14736 mode_cmd->pixel_format);
14737 if (mode_cmd->pitches[0] > pitch_limit) {
14738 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14739 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14740 "tiled" : "linear",
14741 mode_cmd->pitches[0], pitch_limit);
14742 return -EINVAL;
14743 }
14744
14745 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14746 mode_cmd->pitches[0] != obj->stride) {
14747 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14748 mode_cmd->pitches[0], obj->stride);
14749 return -EINVAL;
14750 }
14751
14752 /* Reject formats not supported by any plane early. */
14753 switch (mode_cmd->pixel_format) {
14754 case DRM_FORMAT_C8:
14755 case DRM_FORMAT_RGB565:
14756 case DRM_FORMAT_XRGB8888:
14757 case DRM_FORMAT_ARGB8888:
14758 break;
14759 case DRM_FORMAT_XRGB1555:
14760 if (INTEL_INFO(dev)->gen > 3) {
14761 DRM_DEBUG("unsupported pixel format: %s\n",
14762 drm_get_format_name(mode_cmd->pixel_format));
14763 return -EINVAL;
14764 }
14765 break;
14766 case DRM_FORMAT_ABGR8888:
14767 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14768 INTEL_INFO(dev)->gen < 9) {
14769 DRM_DEBUG("unsupported pixel format: %s\n",
14770 drm_get_format_name(mode_cmd->pixel_format));
14771 return -EINVAL;
14772 }
14773 break;
14774 case DRM_FORMAT_XBGR8888:
14775 case DRM_FORMAT_XRGB2101010:
14776 case DRM_FORMAT_XBGR2101010:
14777 if (INTEL_INFO(dev)->gen < 4) {
14778 DRM_DEBUG("unsupported pixel format: %s\n",
14779 drm_get_format_name(mode_cmd->pixel_format));
14780 return -EINVAL;
14781 }
14782 break;
14783 case DRM_FORMAT_ABGR2101010:
14784 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14785 DRM_DEBUG("unsupported pixel format: %s\n",
14786 drm_get_format_name(mode_cmd->pixel_format));
14787 return -EINVAL;
14788 }
14789 break;
14790 case DRM_FORMAT_YUYV:
14791 case DRM_FORMAT_UYVY:
14792 case DRM_FORMAT_YVYU:
14793 case DRM_FORMAT_VYUY:
14794 if (INTEL_INFO(dev)->gen < 5) {
14795 DRM_DEBUG("unsupported pixel format: %s\n",
14796 drm_get_format_name(mode_cmd->pixel_format));
14797 return -EINVAL;
14798 }
14799 break;
14800 default:
14801 DRM_DEBUG("unsupported pixel format: %s\n",
14802 drm_get_format_name(mode_cmd->pixel_format));
14803 return -EINVAL;
14804 }
14805
14806 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14807 if (mode_cmd->offsets[0] != 0)
14808 return -EINVAL;
14809
14810 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14811 mode_cmd->pixel_format,
14812 mode_cmd->modifier[0]);
14813 /* FIXME drm helper for size checks (especially planar formats)? */
14814 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14815 return -EINVAL;
14816
14817 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14818 intel_fb->obj = obj;
14819
14820 intel_fill_fb_info(dev_priv, &intel_fb->base);
14821
14822 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14823 if (ret) {
14824 DRM_ERROR("framebuffer init failed %d\n", ret);
14825 return ret;
14826 }
14827
14828 intel_fb->obj->framebuffer_references++;
14829
14830 return 0;
14831 }
14832
14833 static struct drm_framebuffer *
14834 intel_user_framebuffer_create(struct drm_device *dev,
14835 struct drm_file *filp,
14836 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14837 {
14838 struct drm_framebuffer *fb;
14839 struct drm_i915_gem_object *obj;
14840 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14841
14842 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14843 mode_cmd.handles[0]));
14844 if (&obj->base == NULL)
14845 return ERR_PTR(-ENOENT);
14846
14847 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14848 if (IS_ERR(fb))
14849 drm_gem_object_unreference_unlocked(&obj->base);
14850
14851 return fb;
14852 }
14853
14854 #ifndef CONFIG_DRM_FBDEV_EMULATION
14855 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14856 {
14857 }
14858 #endif
14859
14860 static const struct drm_mode_config_funcs intel_mode_funcs = {
14861 .fb_create = intel_user_framebuffer_create,
14862 .output_poll_changed = intel_fbdev_output_poll_changed,
14863 .atomic_check = intel_atomic_check,
14864 .atomic_commit = intel_atomic_commit,
14865 .atomic_state_alloc = intel_atomic_state_alloc,
14866 .atomic_state_clear = intel_atomic_state_clear,
14867 };
14868
14869 /**
14870 * intel_init_display_hooks - initialize the display modesetting hooks
14871 * @dev_priv: device private
14872 */
14873 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14874 {
14875 if (INTEL_INFO(dev_priv)->gen >= 9) {
14876 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14877 dev_priv->display.get_initial_plane_config =
14878 skylake_get_initial_plane_config;
14879 dev_priv->display.crtc_compute_clock =
14880 haswell_crtc_compute_clock;
14881 dev_priv->display.crtc_enable = haswell_crtc_enable;
14882 dev_priv->display.crtc_disable = haswell_crtc_disable;
14883 } else if (HAS_DDI(dev_priv)) {
14884 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14885 dev_priv->display.get_initial_plane_config =
14886 ironlake_get_initial_plane_config;
14887 dev_priv->display.crtc_compute_clock =
14888 haswell_crtc_compute_clock;
14889 dev_priv->display.crtc_enable = haswell_crtc_enable;
14890 dev_priv->display.crtc_disable = haswell_crtc_disable;
14891 } else if (HAS_PCH_SPLIT(dev_priv)) {
14892 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14893 dev_priv->display.get_initial_plane_config =
14894 ironlake_get_initial_plane_config;
14895 dev_priv->display.crtc_compute_clock =
14896 ironlake_crtc_compute_clock;
14897 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14898 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14899 } else if (IS_CHERRYVIEW(dev_priv)) {
14900 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14901 dev_priv->display.get_initial_plane_config =
14902 i9xx_get_initial_plane_config;
14903 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14904 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14905 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14906 } else if (IS_VALLEYVIEW(dev_priv)) {
14907 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14908 dev_priv->display.get_initial_plane_config =
14909 i9xx_get_initial_plane_config;
14910 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14911 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14912 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14913 } else if (IS_G4X(dev_priv)) {
14914 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14915 dev_priv->display.get_initial_plane_config =
14916 i9xx_get_initial_plane_config;
14917 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14918 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14919 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14920 } else if (IS_PINEVIEW(dev_priv)) {
14921 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14922 dev_priv->display.get_initial_plane_config =
14923 i9xx_get_initial_plane_config;
14924 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14925 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14926 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14927 } else if (!IS_GEN2(dev_priv)) {
14928 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14929 dev_priv->display.get_initial_plane_config =
14930 i9xx_get_initial_plane_config;
14931 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14932 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14933 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14934 } else {
14935 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14936 dev_priv->display.get_initial_plane_config =
14937 i9xx_get_initial_plane_config;
14938 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14939 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14940 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14941 }
14942
14943 /* Returns the core display clock speed */
14944 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14945 dev_priv->display.get_display_clock_speed =
14946 skylake_get_display_clock_speed;
14947 else if (IS_BROXTON(dev_priv))
14948 dev_priv->display.get_display_clock_speed =
14949 broxton_get_display_clock_speed;
14950 else if (IS_BROADWELL(dev_priv))
14951 dev_priv->display.get_display_clock_speed =
14952 broadwell_get_display_clock_speed;
14953 else if (IS_HASWELL(dev_priv))
14954 dev_priv->display.get_display_clock_speed =
14955 haswell_get_display_clock_speed;
14956 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14957 dev_priv->display.get_display_clock_speed =
14958 valleyview_get_display_clock_speed;
14959 else if (IS_GEN5(dev_priv))
14960 dev_priv->display.get_display_clock_speed =
14961 ilk_get_display_clock_speed;
14962 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14963 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14964 dev_priv->display.get_display_clock_speed =
14965 i945_get_display_clock_speed;
14966 else if (IS_GM45(dev_priv))
14967 dev_priv->display.get_display_clock_speed =
14968 gm45_get_display_clock_speed;
14969 else if (IS_CRESTLINE(dev_priv))
14970 dev_priv->display.get_display_clock_speed =
14971 i965gm_get_display_clock_speed;
14972 else if (IS_PINEVIEW(dev_priv))
14973 dev_priv->display.get_display_clock_speed =
14974 pnv_get_display_clock_speed;
14975 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14976 dev_priv->display.get_display_clock_speed =
14977 g33_get_display_clock_speed;
14978 else if (IS_I915G(dev_priv))
14979 dev_priv->display.get_display_clock_speed =
14980 i915_get_display_clock_speed;
14981 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14982 dev_priv->display.get_display_clock_speed =
14983 i9xx_misc_get_display_clock_speed;
14984 else if (IS_I915GM(dev_priv))
14985 dev_priv->display.get_display_clock_speed =
14986 i915gm_get_display_clock_speed;
14987 else if (IS_I865G(dev_priv))
14988 dev_priv->display.get_display_clock_speed =
14989 i865_get_display_clock_speed;
14990 else if (IS_I85X(dev_priv))
14991 dev_priv->display.get_display_clock_speed =
14992 i85x_get_display_clock_speed;
14993 else { /* 830 */
14994 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14995 dev_priv->display.get_display_clock_speed =
14996 i830_get_display_clock_speed;
14997 }
14998
14999 if (IS_GEN5(dev_priv)) {
15000 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15001 } else if (IS_GEN6(dev_priv)) {
15002 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15003 } else if (IS_IVYBRIDGE(dev_priv)) {
15004 /* FIXME: detect B0+ stepping and use auto training */
15005 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15006 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15007 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15008 if (IS_BROADWELL(dev_priv)) {
15009 dev_priv->display.modeset_commit_cdclk =
15010 broadwell_modeset_commit_cdclk;
15011 dev_priv->display.modeset_calc_cdclk =
15012 broadwell_modeset_calc_cdclk;
15013 }
15014 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15015 dev_priv->display.modeset_commit_cdclk =
15016 valleyview_modeset_commit_cdclk;
15017 dev_priv->display.modeset_calc_cdclk =
15018 valleyview_modeset_calc_cdclk;
15019 } else if (IS_BROXTON(dev_priv)) {
15020 dev_priv->display.modeset_commit_cdclk =
15021 broxton_modeset_commit_cdclk;
15022 dev_priv->display.modeset_calc_cdclk =
15023 broxton_modeset_calc_cdclk;
15024 }
15025
15026 switch (INTEL_INFO(dev_priv)->gen) {
15027 case 2:
15028 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15029 break;
15030
15031 case 3:
15032 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15033 break;
15034
15035 case 4:
15036 case 5:
15037 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15038 break;
15039
15040 case 6:
15041 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15042 break;
15043 case 7:
15044 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15045 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15046 break;
15047 case 9:
15048 /* Drop through - unsupported since execlist only. */
15049 default:
15050 /* Default just returns -ENODEV to indicate unsupported */
15051 dev_priv->display.queue_flip = intel_default_queue_flip;
15052 }
15053 }
15054
15055 /*
15056 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15057 * resume, or other times. This quirk makes sure that's the case for
15058 * affected systems.
15059 */
15060 static void quirk_pipea_force(struct drm_device *dev)
15061 {
15062 struct drm_i915_private *dev_priv = dev->dev_private;
15063
15064 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15065 DRM_INFO("applying pipe a force quirk\n");
15066 }
15067
15068 static void quirk_pipeb_force(struct drm_device *dev)
15069 {
15070 struct drm_i915_private *dev_priv = dev->dev_private;
15071
15072 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15073 DRM_INFO("applying pipe b force quirk\n");
15074 }
15075
15076 /*
15077 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15078 */
15079 static void quirk_ssc_force_disable(struct drm_device *dev)
15080 {
15081 struct drm_i915_private *dev_priv = dev->dev_private;
15082 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15083 DRM_INFO("applying lvds SSC disable quirk\n");
15084 }
15085
15086 /*
15087 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15088 * brightness value
15089 */
15090 static void quirk_invert_brightness(struct drm_device *dev)
15091 {
15092 struct drm_i915_private *dev_priv = dev->dev_private;
15093 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15094 DRM_INFO("applying inverted panel brightness quirk\n");
15095 }
15096
15097 /* Some VBT's incorrectly indicate no backlight is present */
15098 static void quirk_backlight_present(struct drm_device *dev)
15099 {
15100 struct drm_i915_private *dev_priv = dev->dev_private;
15101 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15102 DRM_INFO("applying backlight present quirk\n");
15103 }
15104
15105 struct intel_quirk {
15106 int device;
15107 int subsystem_vendor;
15108 int subsystem_device;
15109 void (*hook)(struct drm_device *dev);
15110 };
15111
15112 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15113 struct intel_dmi_quirk {
15114 void (*hook)(struct drm_device *dev);
15115 const struct dmi_system_id (*dmi_id_list)[];
15116 };
15117
15118 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15119 {
15120 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15121 return 1;
15122 }
15123
15124 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15125 {
15126 .dmi_id_list = &(const struct dmi_system_id[]) {
15127 {
15128 .callback = intel_dmi_reverse_brightness,
15129 .ident = "NCR Corporation",
15130 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15131 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15132 },
15133 },
15134 { } /* terminating entry */
15135 },
15136 .hook = quirk_invert_brightness,
15137 },
15138 };
15139
15140 static struct intel_quirk intel_quirks[] = {
15141 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15142 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15143
15144 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15145 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15146
15147 /* 830 needs to leave pipe A & dpll A up */
15148 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15149
15150 /* 830 needs to leave pipe B & dpll B up */
15151 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15152
15153 /* Lenovo U160 cannot use SSC on LVDS */
15154 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15155
15156 /* Sony Vaio Y cannot use SSC on LVDS */
15157 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15158
15159 /* Acer Aspire 5734Z must invert backlight brightness */
15160 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15161
15162 /* Acer/eMachines G725 */
15163 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15164
15165 /* Acer/eMachines e725 */
15166 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15167
15168 /* Acer/Packard Bell NCL20 */
15169 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15170
15171 /* Acer Aspire 4736Z */
15172 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15173
15174 /* Acer Aspire 5336 */
15175 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15176
15177 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15178 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15179
15180 /* Acer C720 Chromebook (Core i3 4005U) */
15181 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15182
15183 /* Apple Macbook 2,1 (Core 2 T7400) */
15184 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15185
15186 /* Apple Macbook 4,1 */
15187 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15188
15189 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15190 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15191
15192 /* HP Chromebook 14 (Celeron 2955U) */
15193 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15194
15195 /* Dell Chromebook 11 */
15196 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15197
15198 /* Dell Chromebook 11 (2015 version) */
15199 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15200 };
15201
15202 static void intel_init_quirks(struct drm_device *dev)
15203 {
15204 struct pci_dev *d = dev->pdev;
15205 int i;
15206
15207 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15208 struct intel_quirk *q = &intel_quirks[i];
15209
15210 if (d->device == q->device &&
15211 (d->subsystem_vendor == q->subsystem_vendor ||
15212 q->subsystem_vendor == PCI_ANY_ID) &&
15213 (d->subsystem_device == q->subsystem_device ||
15214 q->subsystem_device == PCI_ANY_ID))
15215 q->hook(dev);
15216 }
15217 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15218 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15219 intel_dmi_quirks[i].hook(dev);
15220 }
15221 }
15222
15223 /* Disable the VGA plane that we never use */
15224 static void i915_disable_vga(struct drm_device *dev)
15225 {
15226 struct drm_i915_private *dev_priv = dev->dev_private;
15227 u8 sr1;
15228 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15229
15230 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15231 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15232 outb(SR01, VGA_SR_INDEX);
15233 sr1 = inb(VGA_SR_DATA);
15234 outb(sr1 | 1<<5, VGA_SR_DATA);
15235 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15236 udelay(300);
15237
15238 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15239 POSTING_READ(vga_reg);
15240 }
15241
15242 void intel_modeset_init_hw(struct drm_device *dev)
15243 {
15244 struct drm_i915_private *dev_priv = dev->dev_private;
15245
15246 intel_update_cdclk(dev);
15247
15248 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15249
15250 intel_init_clock_gating(dev);
15251 intel_enable_gt_powersave(dev);
15252 }
15253
15254 /*
15255 * Calculate what we think the watermarks should be for the state we've read
15256 * out of the hardware and then immediately program those watermarks so that
15257 * we ensure the hardware settings match our internal state.
15258 *
15259 * We can calculate what we think WM's should be by creating a duplicate of the
15260 * current state (which was constructed during hardware readout) and running it
15261 * through the atomic check code to calculate new watermark values in the
15262 * state object.
15263 */
15264 static void sanitize_watermarks(struct drm_device *dev)
15265 {
15266 struct drm_i915_private *dev_priv = to_i915(dev);
15267 struct drm_atomic_state *state;
15268 struct drm_crtc *crtc;
15269 struct drm_crtc_state *cstate;
15270 struct drm_modeset_acquire_ctx ctx;
15271 int ret;
15272 int i;
15273
15274 /* Only supported on platforms that use atomic watermark design */
15275 if (!dev_priv->display.optimize_watermarks)
15276 return;
15277
15278 /*
15279 * We need to hold connection_mutex before calling duplicate_state so
15280 * that the connector loop is protected.
15281 */
15282 drm_modeset_acquire_init(&ctx, 0);
15283 retry:
15284 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15285 if (ret == -EDEADLK) {
15286 drm_modeset_backoff(&ctx);
15287 goto retry;
15288 } else if (WARN_ON(ret)) {
15289 goto fail;
15290 }
15291
15292 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15293 if (WARN_ON(IS_ERR(state)))
15294 goto fail;
15295
15296 /*
15297 * Hardware readout is the only time we don't want to calculate
15298 * intermediate watermarks (since we don't trust the current
15299 * watermarks).
15300 */
15301 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15302
15303 ret = intel_atomic_check(dev, state);
15304 if (ret) {
15305 /*
15306 * If we fail here, it means that the hardware appears to be
15307 * programmed in a way that shouldn't be possible, given our
15308 * understanding of watermark requirements. This might mean a
15309 * mistake in the hardware readout code or a mistake in the
15310 * watermark calculations for a given platform. Raise a WARN
15311 * so that this is noticeable.
15312 *
15313 * If this actually happens, we'll have to just leave the
15314 * BIOS-programmed watermarks untouched and hope for the best.
15315 */
15316 WARN(true, "Could not determine valid watermarks for inherited state\n");
15317 goto fail;
15318 }
15319
15320 /* Write calculated watermark values back */
15321 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15322 for_each_crtc_in_state(state, crtc, cstate, i) {
15323 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15324
15325 cs->wm.need_postvbl_update = true;
15326 dev_priv->display.optimize_watermarks(cs);
15327 }
15328
15329 drm_atomic_state_free(state);
15330 fail:
15331 drm_modeset_drop_locks(&ctx);
15332 drm_modeset_acquire_fini(&ctx);
15333 }
15334
15335 void intel_modeset_init(struct drm_device *dev)
15336 {
15337 struct drm_i915_private *dev_priv = to_i915(dev);
15338 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15339 int sprite, ret;
15340 enum pipe pipe;
15341 struct intel_crtc *crtc;
15342
15343 drm_mode_config_init(dev);
15344
15345 dev->mode_config.min_width = 0;
15346 dev->mode_config.min_height = 0;
15347
15348 dev->mode_config.preferred_depth = 24;
15349 dev->mode_config.prefer_shadow = 1;
15350
15351 dev->mode_config.allow_fb_modifiers = true;
15352
15353 dev->mode_config.funcs = &intel_mode_funcs;
15354
15355 intel_init_quirks(dev);
15356
15357 intel_init_pm(dev);
15358
15359 if (INTEL_INFO(dev)->num_pipes == 0)
15360 return;
15361
15362 /*
15363 * There may be no VBT; and if the BIOS enabled SSC we can
15364 * just keep using it to avoid unnecessary flicker. Whereas if the
15365 * BIOS isn't using it, don't assume it will work even if the VBT
15366 * indicates as much.
15367 */
15368 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15369 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15370 DREF_SSC1_ENABLE);
15371
15372 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15373 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15374 bios_lvds_use_ssc ? "en" : "dis",
15375 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15376 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15377 }
15378 }
15379
15380 if (IS_GEN2(dev)) {
15381 dev->mode_config.max_width = 2048;
15382 dev->mode_config.max_height = 2048;
15383 } else if (IS_GEN3(dev)) {
15384 dev->mode_config.max_width = 4096;
15385 dev->mode_config.max_height = 4096;
15386 } else {
15387 dev->mode_config.max_width = 8192;
15388 dev->mode_config.max_height = 8192;
15389 }
15390
15391 if (IS_845G(dev) || IS_I865G(dev)) {
15392 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15393 dev->mode_config.cursor_height = 1023;
15394 } else if (IS_GEN2(dev)) {
15395 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15396 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15397 } else {
15398 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15399 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15400 }
15401
15402 dev->mode_config.fb_base = ggtt->mappable_base;
15403
15404 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15405 INTEL_INFO(dev)->num_pipes,
15406 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15407
15408 for_each_pipe(dev_priv, pipe) {
15409 intel_crtc_init(dev, pipe);
15410 for_each_sprite(dev_priv, pipe, sprite) {
15411 ret = intel_plane_init(dev, pipe, sprite);
15412 if (ret)
15413 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15414 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15415 }
15416 }
15417
15418 intel_update_czclk(dev_priv);
15419 intel_update_rawclk(dev_priv);
15420 intel_update_cdclk(dev);
15421
15422 intel_shared_dpll_init(dev);
15423
15424 /* Just disable it once at startup */
15425 i915_disable_vga(dev);
15426 intel_setup_outputs(dev);
15427
15428 drm_modeset_lock_all(dev);
15429 intel_modeset_setup_hw_state(dev);
15430 drm_modeset_unlock_all(dev);
15431
15432 for_each_intel_crtc(dev, crtc) {
15433 struct intel_initial_plane_config plane_config = {};
15434
15435 if (!crtc->active)
15436 continue;
15437
15438 /*
15439 * Note that reserving the BIOS fb up front prevents us
15440 * from stuffing other stolen allocations like the ring
15441 * on top. This prevents some ugliness at boot time, and
15442 * can even allow for smooth boot transitions if the BIOS
15443 * fb is large enough for the active pipe configuration.
15444 */
15445 dev_priv->display.get_initial_plane_config(crtc,
15446 &plane_config);
15447
15448 /*
15449 * If the fb is shared between multiple heads, we'll
15450 * just get the first one.
15451 */
15452 intel_find_initial_plane_obj(crtc, &plane_config);
15453 }
15454
15455 /*
15456 * Make sure hardware watermarks really match the state we read out.
15457 * Note that we need to do this after reconstructing the BIOS fb's
15458 * since the watermark calculation done here will use pstate->fb.
15459 */
15460 sanitize_watermarks(dev);
15461 }
15462
15463 static void intel_enable_pipe_a(struct drm_device *dev)
15464 {
15465 struct intel_connector *connector;
15466 struct drm_connector *crt = NULL;
15467 struct intel_load_detect_pipe load_detect_temp;
15468 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15469
15470 /* We can't just switch on the pipe A, we need to set things up with a
15471 * proper mode and output configuration. As a gross hack, enable pipe A
15472 * by enabling the load detect pipe once. */
15473 for_each_intel_connector(dev, connector) {
15474 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15475 crt = &connector->base;
15476 break;
15477 }
15478 }
15479
15480 if (!crt)
15481 return;
15482
15483 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15484 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15485 }
15486
15487 static bool
15488 intel_check_plane_mapping(struct intel_crtc *crtc)
15489 {
15490 struct drm_device *dev = crtc->base.dev;
15491 struct drm_i915_private *dev_priv = dev->dev_private;
15492 u32 val;
15493
15494 if (INTEL_INFO(dev)->num_pipes == 1)
15495 return true;
15496
15497 val = I915_READ(DSPCNTR(!crtc->plane));
15498
15499 if ((val & DISPLAY_PLANE_ENABLE) &&
15500 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15501 return false;
15502
15503 return true;
15504 }
15505
15506 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15507 {
15508 struct drm_device *dev = crtc->base.dev;
15509 struct intel_encoder *encoder;
15510
15511 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15512 return true;
15513
15514 return false;
15515 }
15516
15517 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15518 {
15519 struct drm_device *dev = encoder->base.dev;
15520 struct intel_connector *connector;
15521
15522 for_each_connector_on_encoder(dev, &encoder->base, connector)
15523 return true;
15524
15525 return false;
15526 }
15527
15528 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15529 {
15530 struct drm_device *dev = crtc->base.dev;
15531 struct drm_i915_private *dev_priv = dev->dev_private;
15532 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15533
15534 /* Clear any frame start delays used for debugging left by the BIOS */
15535 if (!transcoder_is_dsi(cpu_transcoder)) {
15536 i915_reg_t reg = PIPECONF(cpu_transcoder);
15537
15538 I915_WRITE(reg,
15539 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15540 }
15541
15542 /* restore vblank interrupts to correct state */
15543 drm_crtc_vblank_reset(&crtc->base);
15544 if (crtc->active) {
15545 struct intel_plane *plane;
15546
15547 drm_crtc_vblank_on(&crtc->base);
15548
15549 /* Disable everything but the primary plane */
15550 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15551 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15552 continue;
15553
15554 plane->disable_plane(&plane->base, &crtc->base);
15555 }
15556 }
15557
15558 /* We need to sanitize the plane -> pipe mapping first because this will
15559 * disable the crtc (and hence change the state) if it is wrong. Note
15560 * that gen4+ has a fixed plane -> pipe mapping. */
15561 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15562 bool plane;
15563
15564 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15565 crtc->base.base.id);
15566
15567 /* Pipe has the wrong plane attached and the plane is active.
15568 * Temporarily change the plane mapping and disable everything
15569 * ... */
15570 plane = crtc->plane;
15571 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15572 crtc->plane = !plane;
15573 intel_crtc_disable_noatomic(&crtc->base);
15574 crtc->plane = plane;
15575 }
15576
15577 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15578 crtc->pipe == PIPE_A && !crtc->active) {
15579 /* BIOS forgot to enable pipe A, this mostly happens after
15580 * resume. Force-enable the pipe to fix this, the update_dpms
15581 * call below we restore the pipe to the right state, but leave
15582 * the required bits on. */
15583 intel_enable_pipe_a(dev);
15584 }
15585
15586 /* Adjust the state of the output pipe according to whether we
15587 * have active connectors/encoders. */
15588 if (crtc->active && !intel_crtc_has_encoders(crtc))
15589 intel_crtc_disable_noatomic(&crtc->base);
15590
15591 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15592 /*
15593 * We start out with underrun reporting disabled to avoid races.
15594 * For correct bookkeeping mark this on active crtcs.
15595 *
15596 * Also on gmch platforms we dont have any hardware bits to
15597 * disable the underrun reporting. Which means we need to start
15598 * out with underrun reporting disabled also on inactive pipes,
15599 * since otherwise we'll complain about the garbage we read when
15600 * e.g. coming up after runtime pm.
15601 *
15602 * No protection against concurrent access is required - at
15603 * worst a fifo underrun happens which also sets this to false.
15604 */
15605 crtc->cpu_fifo_underrun_disabled = true;
15606 crtc->pch_fifo_underrun_disabled = true;
15607 }
15608 }
15609
15610 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15611 {
15612 struct intel_connector *connector;
15613 struct drm_device *dev = encoder->base.dev;
15614
15615 /* We need to check both for a crtc link (meaning that the
15616 * encoder is active and trying to read from a pipe) and the
15617 * pipe itself being active. */
15618 bool has_active_crtc = encoder->base.crtc &&
15619 to_intel_crtc(encoder->base.crtc)->active;
15620
15621 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15622 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15623 encoder->base.base.id,
15624 encoder->base.name);
15625
15626 /* Connector is active, but has no active pipe. This is
15627 * fallout from our resume register restoring. Disable
15628 * the encoder manually again. */
15629 if (encoder->base.crtc) {
15630 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15631 encoder->base.base.id,
15632 encoder->base.name);
15633 encoder->disable(encoder);
15634 if (encoder->post_disable)
15635 encoder->post_disable(encoder);
15636 }
15637 encoder->base.crtc = NULL;
15638
15639 /* Inconsistent output/port/pipe state happens presumably due to
15640 * a bug in one of the get_hw_state functions. Or someplace else
15641 * in our code, like the register restore mess on resume. Clamp
15642 * things to off as a safer default. */
15643 for_each_intel_connector(dev, connector) {
15644 if (connector->encoder != encoder)
15645 continue;
15646 connector->base.dpms = DRM_MODE_DPMS_OFF;
15647 connector->base.encoder = NULL;
15648 }
15649 }
15650 /* Enabled encoders without active connectors will be fixed in
15651 * the crtc fixup. */
15652 }
15653
15654 void i915_redisable_vga_power_on(struct drm_device *dev)
15655 {
15656 struct drm_i915_private *dev_priv = dev->dev_private;
15657 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15658
15659 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15660 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15661 i915_disable_vga(dev);
15662 }
15663 }
15664
15665 void i915_redisable_vga(struct drm_device *dev)
15666 {
15667 struct drm_i915_private *dev_priv = dev->dev_private;
15668
15669 /* This function can be called both from intel_modeset_setup_hw_state or
15670 * at a very early point in our resume sequence, where the power well
15671 * structures are not yet restored. Since this function is at a very
15672 * paranoid "someone might have enabled VGA while we were not looking"
15673 * level, just check if the power well is enabled instead of trying to
15674 * follow the "don't touch the power well if we don't need it" policy
15675 * the rest of the driver uses. */
15676 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15677 return;
15678
15679 i915_redisable_vga_power_on(dev);
15680
15681 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15682 }
15683
15684 static bool primary_get_hw_state(struct intel_plane *plane)
15685 {
15686 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15687
15688 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15689 }
15690
15691 /* FIXME read out full plane state for all planes */
15692 static void readout_plane_state(struct intel_crtc *crtc)
15693 {
15694 struct drm_plane *primary = crtc->base.primary;
15695 struct intel_plane_state *plane_state =
15696 to_intel_plane_state(primary->state);
15697
15698 plane_state->visible = crtc->active &&
15699 primary_get_hw_state(to_intel_plane(primary));
15700
15701 if (plane_state->visible)
15702 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15703 }
15704
15705 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15706 {
15707 struct drm_i915_private *dev_priv = dev->dev_private;
15708 enum pipe pipe;
15709 struct intel_crtc *crtc;
15710 struct intel_encoder *encoder;
15711 struct intel_connector *connector;
15712 int i;
15713
15714 dev_priv->active_crtcs = 0;
15715
15716 for_each_intel_crtc(dev, crtc) {
15717 struct intel_crtc_state *crtc_state = crtc->config;
15718 int pixclk = 0;
15719
15720 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15721 memset(crtc_state, 0, sizeof(*crtc_state));
15722 crtc_state->base.crtc = &crtc->base;
15723
15724 crtc_state->base.active = crtc_state->base.enable =
15725 dev_priv->display.get_pipe_config(crtc, crtc_state);
15726
15727 crtc->base.enabled = crtc_state->base.enable;
15728 crtc->active = crtc_state->base.active;
15729
15730 if (crtc_state->base.active) {
15731 dev_priv->active_crtcs |= 1 << crtc->pipe;
15732
15733 if (IS_BROADWELL(dev_priv)) {
15734 pixclk = ilk_pipe_pixel_rate(crtc_state);
15735
15736 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15737 if (crtc_state->ips_enabled)
15738 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15739 } else if (IS_VALLEYVIEW(dev_priv) ||
15740 IS_CHERRYVIEW(dev_priv) ||
15741 IS_BROXTON(dev_priv))
15742 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15743 else
15744 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15745 }
15746
15747 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15748
15749 readout_plane_state(crtc);
15750
15751 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15752 crtc->base.base.id,
15753 crtc->active ? "enabled" : "disabled");
15754 }
15755
15756 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15757 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15758
15759 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15760 &pll->config.hw_state);
15761 pll->config.crtc_mask = 0;
15762 for_each_intel_crtc(dev, crtc) {
15763 if (crtc->active && crtc->config->shared_dpll == pll)
15764 pll->config.crtc_mask |= 1 << crtc->pipe;
15765 }
15766 pll->active_mask = pll->config.crtc_mask;
15767
15768 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15769 pll->name, pll->config.crtc_mask, pll->on);
15770 }
15771
15772 for_each_intel_encoder(dev, encoder) {
15773 pipe = 0;
15774
15775 if (encoder->get_hw_state(encoder, &pipe)) {
15776 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15777 encoder->base.crtc = &crtc->base;
15778 encoder->get_config(encoder, crtc->config);
15779 } else {
15780 encoder->base.crtc = NULL;
15781 }
15782
15783 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15784 encoder->base.base.id,
15785 encoder->base.name,
15786 encoder->base.crtc ? "enabled" : "disabled",
15787 pipe_name(pipe));
15788 }
15789
15790 for_each_intel_connector(dev, connector) {
15791 if (connector->get_hw_state(connector)) {
15792 connector->base.dpms = DRM_MODE_DPMS_ON;
15793
15794 encoder = connector->encoder;
15795 connector->base.encoder = &encoder->base;
15796
15797 if (encoder->base.crtc &&
15798 encoder->base.crtc->state->active) {
15799 /*
15800 * This has to be done during hardware readout
15801 * because anything calling .crtc_disable may
15802 * rely on the connector_mask being accurate.
15803 */
15804 encoder->base.crtc->state->connector_mask |=
15805 1 << drm_connector_index(&connector->base);
15806 encoder->base.crtc->state->encoder_mask |=
15807 1 << drm_encoder_index(&encoder->base);
15808 }
15809
15810 } else {
15811 connector->base.dpms = DRM_MODE_DPMS_OFF;
15812 connector->base.encoder = NULL;
15813 }
15814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15815 connector->base.base.id,
15816 connector->base.name,
15817 connector->base.encoder ? "enabled" : "disabled");
15818 }
15819
15820 for_each_intel_crtc(dev, crtc) {
15821 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15822
15823 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15824 if (crtc->base.state->active) {
15825 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15826 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15827 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15828
15829 /*
15830 * The initial mode needs to be set in order to keep
15831 * the atomic core happy. It wants a valid mode if the
15832 * crtc's enabled, so we do the above call.
15833 *
15834 * At this point some state updated by the connectors
15835 * in their ->detect() callback has not run yet, so
15836 * no recalculation can be done yet.
15837 *
15838 * Even if we could do a recalculation and modeset
15839 * right now it would cause a double modeset if
15840 * fbdev or userspace chooses a different initial mode.
15841 *
15842 * If that happens, someone indicated they wanted a
15843 * mode change, which means it's safe to do a full
15844 * recalculation.
15845 */
15846 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15847
15848 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15849 update_scanline_offset(crtc);
15850 }
15851
15852 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15853 }
15854 }
15855
15856 /* Scan out the current hw modeset state,
15857 * and sanitizes it to the current state
15858 */
15859 static void
15860 intel_modeset_setup_hw_state(struct drm_device *dev)
15861 {
15862 struct drm_i915_private *dev_priv = dev->dev_private;
15863 enum pipe pipe;
15864 struct intel_crtc *crtc;
15865 struct intel_encoder *encoder;
15866 int i;
15867
15868 intel_modeset_readout_hw_state(dev);
15869
15870 /* HW state is read out, now we need to sanitize this mess. */
15871 for_each_intel_encoder(dev, encoder) {
15872 intel_sanitize_encoder(encoder);
15873 }
15874
15875 for_each_pipe(dev_priv, pipe) {
15876 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15877 intel_sanitize_crtc(crtc);
15878 intel_dump_pipe_config(crtc, crtc->config,
15879 "[setup_hw_state]");
15880 }
15881
15882 intel_modeset_update_connector_atomic_state(dev);
15883
15884 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15885 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15886
15887 if (!pll->on || pll->active_mask)
15888 continue;
15889
15890 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15891
15892 pll->funcs.disable(dev_priv, pll);
15893 pll->on = false;
15894 }
15895
15896 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15897 vlv_wm_get_hw_state(dev);
15898 else if (IS_GEN9(dev))
15899 skl_wm_get_hw_state(dev);
15900 else if (HAS_PCH_SPLIT(dev))
15901 ilk_wm_get_hw_state(dev);
15902
15903 for_each_intel_crtc(dev, crtc) {
15904 unsigned long put_domains;
15905
15906 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15907 if (WARN_ON(put_domains))
15908 modeset_put_power_domains(dev_priv, put_domains);
15909 }
15910 intel_display_set_init_power(dev_priv, false);
15911
15912 intel_fbc_init_pipe_state(dev_priv);
15913 }
15914
15915 void intel_display_resume(struct drm_device *dev)
15916 {
15917 struct drm_i915_private *dev_priv = to_i915(dev);
15918 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15919 struct drm_modeset_acquire_ctx ctx;
15920 int ret;
15921 bool setup = false;
15922
15923 dev_priv->modeset_restore_state = NULL;
15924
15925 /*
15926 * This is a cludge because with real atomic modeset mode_config.mutex
15927 * won't be taken. Unfortunately some probed state like
15928 * audio_codec_enable is still protected by mode_config.mutex, so lock
15929 * it here for now.
15930 */
15931 mutex_lock(&dev->mode_config.mutex);
15932 drm_modeset_acquire_init(&ctx, 0);
15933
15934 retry:
15935 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15936
15937 if (ret == 0 && !setup) {
15938 setup = true;
15939
15940 intel_modeset_setup_hw_state(dev);
15941 i915_redisable_vga(dev);
15942 }
15943
15944 if (ret == 0 && state) {
15945 struct drm_crtc_state *crtc_state;
15946 struct drm_crtc *crtc;
15947 int i;
15948
15949 state->acquire_ctx = &ctx;
15950
15951 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15952 /*
15953 * Force recalculation even if we restore
15954 * current state. With fast modeset this may not result
15955 * in a modeset when the state is compatible.
15956 */
15957 crtc_state->mode_changed = true;
15958 }
15959
15960 ret = drm_atomic_commit(state);
15961 }
15962
15963 if (ret == -EDEADLK) {
15964 drm_modeset_backoff(&ctx);
15965 goto retry;
15966 }
15967
15968 drm_modeset_drop_locks(&ctx);
15969 drm_modeset_acquire_fini(&ctx);
15970 mutex_unlock(&dev->mode_config.mutex);
15971
15972 if (ret) {
15973 DRM_ERROR("Restoring old state failed with %i\n", ret);
15974 drm_atomic_state_free(state);
15975 }
15976 }
15977
15978 void intel_modeset_gem_init(struct drm_device *dev)
15979 {
15980 struct drm_crtc *c;
15981 struct drm_i915_gem_object *obj;
15982 int ret;
15983
15984 intel_init_gt_powersave(dev);
15985
15986 intel_modeset_init_hw(dev);
15987
15988 intel_setup_overlay(dev);
15989
15990 /*
15991 * Make sure any fbs we allocated at startup are properly
15992 * pinned & fenced. When we do the allocation it's too early
15993 * for this.
15994 */
15995 for_each_crtc(dev, c) {
15996 obj = intel_fb_obj(c->primary->fb);
15997 if (obj == NULL)
15998 continue;
15999
16000 mutex_lock(&dev->struct_mutex);
16001 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16002 c->primary->state->rotation);
16003 mutex_unlock(&dev->struct_mutex);
16004 if (ret) {
16005 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16006 to_intel_crtc(c)->pipe);
16007 drm_framebuffer_unreference(c->primary->fb);
16008 c->primary->fb = NULL;
16009 c->primary->crtc = c->primary->state->crtc = NULL;
16010 update_state_fb(c->primary);
16011 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16012 }
16013 }
16014
16015 intel_backlight_register(dev);
16016 }
16017
16018 void intel_connector_unregister(struct intel_connector *intel_connector)
16019 {
16020 struct drm_connector *connector = &intel_connector->base;
16021
16022 intel_panel_destroy_backlight(connector);
16023 drm_connector_unregister(connector);
16024 }
16025
16026 void intel_modeset_cleanup(struct drm_device *dev)
16027 {
16028 struct drm_i915_private *dev_priv = dev->dev_private;
16029 struct intel_connector *connector;
16030
16031 intel_disable_gt_powersave(dev);
16032
16033 intel_backlight_unregister(dev);
16034
16035 /*
16036 * Interrupts and polling as the first thing to avoid creating havoc.
16037 * Too much stuff here (turning of connectors, ...) would
16038 * experience fancy races otherwise.
16039 */
16040 intel_irq_uninstall(dev_priv);
16041
16042 /*
16043 * Due to the hpd irq storm handling the hotplug work can re-arm the
16044 * poll handlers. Hence disable polling after hpd handling is shut down.
16045 */
16046 drm_kms_helper_poll_fini(dev);
16047
16048 intel_unregister_dsm_handler();
16049
16050 intel_fbc_global_disable(dev_priv);
16051
16052 /* flush any delayed tasks or pending work */
16053 flush_scheduled_work();
16054
16055 /* destroy the backlight and sysfs files before encoders/connectors */
16056 for_each_intel_connector(dev, connector)
16057 connector->unregister(connector);
16058
16059 drm_mode_config_cleanup(dev);
16060
16061 intel_cleanup_overlay(dev);
16062
16063 intel_cleanup_gt_powersave(dev);
16064
16065 intel_teardown_gmbus(dev);
16066 }
16067
16068 /*
16069 * Return which encoder is currently attached for connector.
16070 */
16071 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16072 {
16073 return &intel_attached_encoder(connector)->base;
16074 }
16075
16076 void intel_connector_attach_encoder(struct intel_connector *connector,
16077 struct intel_encoder *encoder)
16078 {
16079 connector->encoder = encoder;
16080 drm_mode_connector_attach_encoder(&connector->base,
16081 &encoder->base);
16082 }
16083
16084 /*
16085 * set vga decode state - true == enable VGA decode
16086 */
16087 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16088 {
16089 struct drm_i915_private *dev_priv = dev->dev_private;
16090 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16091 u16 gmch_ctrl;
16092
16093 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16094 DRM_ERROR("failed to read control word\n");
16095 return -EIO;
16096 }
16097
16098 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16099 return 0;
16100
16101 if (state)
16102 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16103 else
16104 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16105
16106 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16107 DRM_ERROR("failed to write control word\n");
16108 return -EIO;
16109 }
16110
16111 return 0;
16112 }
16113
16114 struct intel_display_error_state {
16115
16116 u32 power_well_driver;
16117
16118 int num_transcoders;
16119
16120 struct intel_cursor_error_state {
16121 u32 control;
16122 u32 position;
16123 u32 base;
16124 u32 size;
16125 } cursor[I915_MAX_PIPES];
16126
16127 struct intel_pipe_error_state {
16128 bool power_domain_on;
16129 u32 source;
16130 u32 stat;
16131 } pipe[I915_MAX_PIPES];
16132
16133 struct intel_plane_error_state {
16134 u32 control;
16135 u32 stride;
16136 u32 size;
16137 u32 pos;
16138 u32 addr;
16139 u32 surface;
16140 u32 tile_offset;
16141 } plane[I915_MAX_PIPES];
16142
16143 struct intel_transcoder_error_state {
16144 bool power_domain_on;
16145 enum transcoder cpu_transcoder;
16146
16147 u32 conf;
16148
16149 u32 htotal;
16150 u32 hblank;
16151 u32 hsync;
16152 u32 vtotal;
16153 u32 vblank;
16154 u32 vsync;
16155 } transcoder[4];
16156 };
16157
16158 struct intel_display_error_state *
16159 intel_display_capture_error_state(struct drm_device *dev)
16160 {
16161 struct drm_i915_private *dev_priv = dev->dev_private;
16162 struct intel_display_error_state *error;
16163 int transcoders[] = {
16164 TRANSCODER_A,
16165 TRANSCODER_B,
16166 TRANSCODER_C,
16167 TRANSCODER_EDP,
16168 };
16169 int i;
16170
16171 if (INTEL_INFO(dev)->num_pipes == 0)
16172 return NULL;
16173
16174 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16175 if (error == NULL)
16176 return NULL;
16177
16178 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16179 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16180
16181 for_each_pipe(dev_priv, i) {
16182 error->pipe[i].power_domain_on =
16183 __intel_display_power_is_enabled(dev_priv,
16184 POWER_DOMAIN_PIPE(i));
16185 if (!error->pipe[i].power_domain_on)
16186 continue;
16187
16188 error->cursor[i].control = I915_READ(CURCNTR(i));
16189 error->cursor[i].position = I915_READ(CURPOS(i));
16190 error->cursor[i].base = I915_READ(CURBASE(i));
16191
16192 error->plane[i].control = I915_READ(DSPCNTR(i));
16193 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16194 if (INTEL_INFO(dev)->gen <= 3) {
16195 error->plane[i].size = I915_READ(DSPSIZE(i));
16196 error->plane[i].pos = I915_READ(DSPPOS(i));
16197 }
16198 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16199 error->plane[i].addr = I915_READ(DSPADDR(i));
16200 if (INTEL_INFO(dev)->gen >= 4) {
16201 error->plane[i].surface = I915_READ(DSPSURF(i));
16202 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16203 }
16204
16205 error->pipe[i].source = I915_READ(PIPESRC(i));
16206
16207 if (HAS_GMCH_DISPLAY(dev))
16208 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16209 }
16210
16211 /* Note: this does not include DSI transcoders. */
16212 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16213 if (HAS_DDI(dev_priv))
16214 error->num_transcoders++; /* Account for eDP. */
16215
16216 for (i = 0; i < error->num_transcoders; i++) {
16217 enum transcoder cpu_transcoder = transcoders[i];
16218
16219 error->transcoder[i].power_domain_on =
16220 __intel_display_power_is_enabled(dev_priv,
16221 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16222 if (!error->transcoder[i].power_domain_on)
16223 continue;
16224
16225 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16226
16227 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16228 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16229 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16230 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16231 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16232 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16233 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16234 }
16235
16236 return error;
16237 }
16238
16239 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16240
16241 void
16242 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16243 struct drm_device *dev,
16244 struct intel_display_error_state *error)
16245 {
16246 struct drm_i915_private *dev_priv = dev->dev_private;
16247 int i;
16248
16249 if (!error)
16250 return;
16251
16252 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16253 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16254 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16255 error->power_well_driver);
16256 for_each_pipe(dev_priv, i) {
16257 err_printf(m, "Pipe [%d]:\n", i);
16258 err_printf(m, " Power: %s\n",
16259 onoff(error->pipe[i].power_domain_on));
16260 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16261 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16262
16263 err_printf(m, "Plane [%d]:\n", i);
16264 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16265 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16266 if (INTEL_INFO(dev)->gen <= 3) {
16267 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16268 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16269 }
16270 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16271 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16272 if (INTEL_INFO(dev)->gen >= 4) {
16273 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16274 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16275 }
16276
16277 err_printf(m, "Cursor [%d]:\n", i);
16278 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16279 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16280 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16281 }
16282
16283 for (i = 0; i < error->num_transcoders; i++) {
16284 err_printf(m, "CPU transcoder: %s\n",
16285 transcoder_name(error->transcoder[i].cpu_transcoder));
16286 err_printf(m, " Power: %s\n",
16287 onoff(error->transcoder[i].power_domain_on));
16288 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16289 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16290 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16291 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16292 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16293 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16294 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16295 }
16296 }
Linux kernel - Deliverables
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