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drm/i915: Allow fuzzy matching in pipe_config_compare, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112
113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114 {
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119 }
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 int
137 intel_pch_rawclk(struct drm_device *dev)
138 {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144 }
145
146 static inline u32 /* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device *dev)
148 {
149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
154 }
155
156 static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
167 };
168
169 static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180 };
181
182 static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
193 };
194
195 static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
206 };
207
208 static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
219 };
220
221
222 static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
234 },
235 };
236
237 static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
248 };
249
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
261 },
262 };
263
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
275 },
276 };
277
278 static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
304 };
305
306 /* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
311 static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
322 };
323
324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
335 };
336
337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
348 };
349
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
362 };
363
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
375 };
376
377 static const intel_limit_t intel_limits_vlv = {
378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
391 };
392
393 static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407 };
408
409 static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6700000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419 };
420
421 static bool
422 needs_modeset(struct drm_crtc_state *state)
423 {
424 return state->mode_changed || state->active_changed;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe is of the specified type
429 */
430 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
431 {
432 struct drm_device *dev = crtc->base.dev;
433 struct intel_encoder *encoder;
434
435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
436 if (encoder->type == type)
437 return true;
438
439 return false;
440 }
441
442 /**
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
446 * encoder->crtc.
447 */
448 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
449 int type)
450 {
451 struct drm_atomic_state *state = crtc_state->base.state;
452 struct drm_connector *connector;
453 struct drm_connector_state *connector_state;
454 struct intel_encoder *encoder;
455 int i, num_connectors = 0;
456
457 for_each_connector_in_state(state, connector, connector_state, i) {
458 if (connector_state->crtc != crtc_state->base.crtc)
459 continue;
460
461 num_connectors++;
462
463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
465 return true;
466 }
467
468 WARN_ON(num_connectors == 0);
469
470 return false;
471 }
472
473 static const intel_limit_t *
474 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
475 {
476 struct drm_device *dev = crtc_state->base.crtc->dev;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
480 if (intel_is_dual_link_lvds(dev)) {
481 if (refclk == 100000)
482 limit = &intel_limits_ironlake_dual_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_dual_lvds;
485 } else {
486 if (refclk == 100000)
487 limit = &intel_limits_ironlake_single_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_single_lvds;
490 }
491 } else
492 limit = &intel_limits_ironlake_dac;
493
494 return limit;
495 }
496
497 static const intel_limit_t *
498 intel_g4x_limit(struct intel_crtc_state *crtc_state)
499 {
500 struct drm_device *dev = crtc_state->base.crtc->dev;
501 const intel_limit_t *limit;
502
503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
504 if (intel_is_dual_link_lvds(dev))
505 limit = &intel_limits_g4x_dual_channel_lvds;
506 else
507 limit = &intel_limits_g4x_single_channel_lvds;
508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
510 limit = &intel_limits_g4x_hdmi;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
512 limit = &intel_limits_g4x_sdvo;
513 } else /* The option is for other outputs */
514 limit = &intel_limits_i9xx_sdvo;
515
516 return limit;
517 }
518
519 static const intel_limit_t *
520 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
521 {
522 struct drm_device *dev = crtc_state->base.crtc->dev;
523 const intel_limit_t *limit;
524
525 if (IS_BROXTON(dev))
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
528 limit = intel_ironlake_limit(crtc_state, refclk);
529 else if (IS_G4X(dev)) {
530 limit = intel_g4x_limit(crtc_state);
531 } else if (IS_PINEVIEW(dev)) {
532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
533 limit = &intel_limits_pineview_lvds;
534 else
535 limit = &intel_limits_pineview_sdvo;
536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
538 } else if (IS_VALLEYVIEW(dev)) {
539 limit = &intel_limits_vlv;
540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
545 } else {
546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
547 limit = &intel_limits_i8xx_lvds;
548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
549 limit = &intel_limits_i8xx_dvo;
550 else
551 limit = &intel_limits_i8xx_dac;
552 }
553 return limit;
554 }
555
556 /*
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
563 */
564 /* m1 is reserved as 0 in Pineview, n is a ring counter */
565 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
566 {
567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
569 if (WARN_ON(clock->n == 0 || clock->p == 0))
570 return 0;
571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
573
574 return clock->dot;
575 }
576
577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578 {
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580 }
581
582 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
583 {
584 clock->m = i9xx_dpll_compute_m(clock);
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return 0;
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590
591 return clock->dot;
592 }
593
594 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
595 {
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return 0;
600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
602
603 return clock->dot / 5;
604 }
605
606 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
607 {
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
611 return 0;
612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
613 clock->n << 22);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
615
616 return clock->dot / 5;
617 }
618
619 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
620 /**
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
623 */
624
625 static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
628 {
629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
632 INTELPllInvalid("p1 out of range\n");
633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
634 INTELPllInvalid("m2 out of range\n");
635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
636 INTELPllInvalid("m1 out of range\n");
637
638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
641
642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
647 }
648
649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
650 INTELPllInvalid("vco out of range\n");
651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
653 */
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
655 INTELPllInvalid("dot out of range\n");
656
657 return true;
658 }
659
660 static int
661 i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
663 int target)
664 {
665 struct drm_device *dev = crtc_state->base.crtc->dev;
666
667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
668 /*
669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
672 */
673 if (intel_is_dual_link_lvds(dev))
674 return limit->p2.p2_fast;
675 else
676 return limit->p2.p2_slow;
677 } else {
678 if (target < limit->p2.dot_limit)
679 return limit->p2.p2_slow;
680 else
681 return limit->p2.p2_fast;
682 }
683 }
684
685 static bool
686 i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690 {
691 struct drm_device *dev = crtc_state->base.crtc->dev;
692 intel_clock_t clock;
693 int err = target;
694
695 memset(best_clock, 0, sizeof(*best_clock));
696
697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
698
699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
700 clock.m1++) {
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
703 if (clock.m2 >= clock.m1)
704 break;
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
709 int this_err;
710
711 i9xx_calc_dpll_params(refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
721 *best_clock = clock;
722 err = this_err;
723 }
724 }
725 }
726 }
727 }
728
729 return (err != target);
730 }
731
732 static bool
733 pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
737 {
738 struct drm_device *dev = crtc_state->base.crtc->dev;
739 intel_clock_t clock;
740 int err = target;
741
742 memset(best_clock, 0, sizeof(*best_clock));
743
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 clock.m1++) {
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
754 int this_err;
755
756 pnv_calc_dpll_params(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
759 continue;
760 if (match_clock &&
761 clock.p != match_clock->p)
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 }
769 }
770 }
771 }
772 }
773
774 return (err != target);
775 }
776
777 static bool
778 g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc_state->base.crtc->dev;
784 intel_clock_t clock;
785 int max_n;
786 bool found = false;
787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
789
790 memset(best_clock, 0, sizeof(*best_clock));
791
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
793
794 max_n = limit->n.max;
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 /* based on hardware requirement, prefere larger m1,m2 */
798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
806 i9xx_calc_dpll_params(refclk, &clock);
807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
809 continue;
810
811 this_err = abs(clock.dot - target);
812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
822 return found;
823 }
824
825 /*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834 {
835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863 }
864
865 static bool
866 vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
870 {
871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
872 struct drm_device *dev = crtc->base.dev;
873 intel_clock_t clock;
874 unsigned int bestppm = 1000000;
875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
877 bool found = false;
878
879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
888 clock.p = clock.p1 * clock.p2;
889 /* based on hardware requirement, prefer bigger m1,m2 values */
890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
891 unsigned int ppm;
892
893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
896 vlv_calc_dpll_params(refclk, &clock);
897
898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
900 continue;
901
902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
907
908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
911 }
912 }
913 }
914 }
915
916 return found;
917 }
918
919 static bool
920 chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924 {
925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
926 struct drm_device *dev = crtc->base.dev;
927 unsigned int best_error_ppm;
928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
933 best_error_ppm = 1000000;
934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 unsigned int error_ppm;
948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
959 chv_calc_dpll_params(refclk, &clock);
960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
971 }
972 }
973
974 return found;
975 }
976
977 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979 {
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984 }
985
986 bool intel_crtc_active(struct drm_crtc *crtc)
987 {
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
993 * We can ditch the adjusted_mode.crtc_clock check as soon
994 * as Haswell has gained clock readout/fastboot support.
995 *
996 * We can ditch the crtc->primary->fb check as soon as we can
997 * properly reconstruct framebuffers.
998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
1002 */
1003 return intel_crtc->active && crtc->primary->state->fb &&
1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
1005 }
1006
1007 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009 {
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
1013 return intel_crtc->config->cpu_transcoder;
1014 }
1015
1016 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
1029 msleep(5);
1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033 }
1034
1035 /*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
1037 * @crtc: crtc whose pipe to wait for
1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
1049 *
1050 */
1051 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1052 {
1053 struct drm_device *dev = crtc->base.dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1056 enum pipe pipe = crtc->pipe;
1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
1059 int reg = PIPECONF(cpu_transcoder);
1060
1061 /* Wait for the Pipe State to go off */
1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
1064 WARN(1, "pipe_off wait timed out\n");
1065 } else {
1066 /* Wait for the display line to settle */
1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1068 WARN(1, "pipe_off wait timed out\n");
1069 }
1070 }
1071
1072 /*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081 {
1082 u32 bit;
1083
1084 if (HAS_PCH_IBX(dev_priv->dev)) {
1085 switch (port->port) {
1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
1099 switch (port->port) {
1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115 }
1116
1117 static const char *state_string(bool enabled)
1118 {
1119 return enabled ? "on" : "off";
1120 }
1121
1122 /* Only for pre-ILK configs */
1123 void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125 {
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
1133 I915_STATE_WARN(cur_state != state,
1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136 }
1137
1138 /* XXX: the dsi pll is shared between MIPI DSI ports */
1139 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 mutex_lock(&dev_priv->sb_lock);
1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1146 mutex_unlock(&dev_priv->sb_lock);
1147
1148 cur_state = val & DSI_PLL_VCO_EN;
1149 I915_STATE_WARN(cur_state != state,
1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152 }
1153 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
1156 struct intel_shared_dpll *
1157 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158 {
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
1161 if (crtc->config->shared_dpll < 0)
1162 return NULL;
1163
1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1165 }
1166
1167 /* For ILK+ */
1168 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
1171 {
1172 bool cur_state;
1173 struct intel_dpll_hw_state hw_state;
1174
1175 if (WARN (!pll,
1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
1177 return;
1178
1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1180 I915_STATE_WARN(cur_state != state,
1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
1183 }
1184
1185 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 int reg;
1189 u32 val;
1190 bool cur_state;
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
1193
1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
1204 I915_STATE_WARN(cur_state != state,
1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207 }
1208 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213 {
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
1221 I915_STATE_WARN(cur_state != state,
1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224 }
1225 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230 {
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1236 return;
1237
1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1239 if (HAS_DDI(dev_priv->dev))
1240 return;
1241
1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1245 }
1246
1247 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
1260 }
1261
1262 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
1269 bool locked = true;
1270
1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
1277 pp_reg = PCH_PP_CONTROL;
1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
1288 } else {
1289 pp_reg = PP_CONTROL;
1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1297 locked = false;
1298
1299 I915_STATE_WARN(panel_pipe == pipe && locked,
1300 "panel assertion failure, pipe %c regs locked\n",
1301 pipe_name(pipe));
1302 }
1303
1304 static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306 {
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
1310 if (IS_845G(dev) || IS_I865G(dev))
1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1312 else
1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1314
1315 I915_STATE_WARN(cur_state != state,
1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
1322 void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 int reg;
1326 u32 val;
1327 bool cur_state;
1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
1330
1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1334 state = true;
1335
1336 if (!intel_display_power_is_enabled(dev_priv,
1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
1345 I915_STATE_WARN(cur_state != state,
1346 "pipe %c assertion failure (expected %s, current %s)\n",
1347 pipe_name(pipe), state_string(state), state_string(cur_state));
1348 }
1349
1350 static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
1352 {
1353 int reg;
1354 u32 val;
1355 bool cur_state;
1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1360 I915_STATE_WARN(cur_state != state,
1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
1363 }
1364
1365 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
1368 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370 {
1371 struct drm_device *dev = dev_priv->dev;
1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
1383 return;
1384 }
1385
1386 /* Need to check both planes against the pipe */
1387 for_each_pipe(dev_priv, i) {
1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
1395 }
1396 }
1397
1398 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400 {
1401 struct drm_device *dev = dev_priv->dev;
1402 int reg, sprite;
1403 u32 val;
1404
1405 if (INTEL_INFO(dev)->gen >= 9) {
1406 for_each_sprite(dev_priv, pipe, sprite) {
1407 val = I915_READ(PLANE_CTL(pipe, sprite));
1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
1413 for_each_sprite(dev_priv, pipe, sprite) {
1414 reg = SPCNTR(pipe, sprite);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & SP_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 sprite_name(pipe, sprite), pipe_name(pipe));
1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
1422 val = I915_READ(reg);
1423 I915_STATE_WARN(val & SPRITE_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
1428 val = I915_READ(reg);
1429 I915_STATE_WARN(val & DVS_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1432 }
1433 }
1434
1435 static void assert_vblank_disabled(struct drm_crtc *crtc)
1436 {
1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1438 drm_crtc_vblank_put(crtc);
1439 }
1440
1441 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1442 {
1443 u32 val;
1444 bool enabled;
1445
1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1447
1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1452 }
1453
1454 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
1456 {
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
1461 reg = PCH_TRANSCONF(pipe);
1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
1464 I915_STATE_WARN(enabled,
1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
1467 }
1468
1469 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
1471 {
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488 }
1489
1490 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492 {
1493 if ((val & SDVO_ENABLE) == 0)
1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1498 return false;
1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1502 } else {
1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1504 return false;
1505 }
1506 return true;
1507 }
1508
1509 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511 {
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523 }
1524
1525 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527 {
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538 }
1539
1540 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg, u32 port_sel)
1542 {
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1547
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1549 && (val & DP_PIPEB_SELECT),
1550 "IBX PCH dp port still using transcoder B\n");
1551 }
1552
1553 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555 {
1556 u32 val = I915_READ(reg);
1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1559 reg, pipe_name(pipe));
1560
1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1562 && (val & SDVO_PIPE_B_SELECT),
1563 "IBX PCH hdmi port still using transcoder B\n");
1564 }
1565
1566 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568 {
1569 int reg;
1570 u32 val;
1571
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
1580 pipe_name(pipe));
1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586 pipe_name(pipe));
1587
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void intel_init_dpio(struct drm_device *dev)
1594 {
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
1611 }
1612
1613 static void vlv_enable_pll(struct intel_crtc *crtc,
1614 const struct intel_crtc_state *pipe_config)
1615 {
1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
1620
1621 assert_pipe_disabled(dev_priv, crtc->pipe);
1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
1627 if (IS_MOBILE(dev_priv->dev))
1628 assert_panel_unlocked(dev_priv, crtc->pipe);
1629
1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1638 POSTING_READ(DPLL_MD(crtc->pipe));
1639
1640 /* We do this three times for luck */
1641 I915_WRITE(reg, dpll);
1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 }
1651
1652 static void chv_enable_pll(struct intel_crtc *crtc,
1653 const struct intel_crtc_state *pipe_config)
1654 {
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
1665 mutex_lock(&dev_priv->sb_lock);
1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
1672 mutex_unlock(&dev_priv->sb_lock);
1673
1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1681
1682 /* Check PLL is locked */
1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
1686 /* not sure when this should be written */
1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1688 POSTING_READ(DPLL_MD(pipe));
1689 }
1690
1691 static int intel_num_dvo_pipes(struct drm_device *dev)
1692 {
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
1697 count += crtc->base.state->active &&
1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1699
1700 return count;
1701 }
1702
1703 static void i9xx_enable_pll(struct intel_crtc *crtc)
1704 {
1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
1709
1710 assert_pipe_disabled(dev_priv, crtc->pipe);
1711
1712 /* No really, not for ILK+ */
1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1714
1715 /* PLL is protected by panel, make sure we can write it */
1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
1718
1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
1738 crtc->config->dpll_hw_state.dpll_md);
1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
1747
1748 /* We do this three times for luck */
1749 I915_WRITE(reg, dpll);
1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
1752 I915_WRITE(reg, dpll);
1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755 I915_WRITE(reg, dpll);
1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758 }
1759
1760 /**
1761 * i9xx_disable_pll - disable a PLL
1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1769 static void i9xx_disable_pll(struct intel_crtc *crtc)
1770 {
1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1778 !intel_num_dvo_pipes(dev)) {
1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
1793 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1794 POSTING_READ(DPLL(pipe));
1795 }
1796
1797 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798 {
1799 u32 val;
1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
1808 val = DPLL_VGA_MODE_DIS;
1809 if (pipe == PIPE_B)
1810 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
1813
1814 }
1815
1816 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817 {
1818 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1819 u32 val;
1820
1821 /* Make sure the pipe isn't still relying on us */
1822 assert_pipe_disabled(dev_priv, pipe);
1823
1824 /* Set PLL en = 0 */
1825 val = DPLL_SSC_REF_CLK_CHV |
1826 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1827 if (pipe != PIPE_A)
1828 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1829 I915_WRITE(DPLL(pipe), val);
1830 POSTING_READ(DPLL(pipe));
1831
1832 mutex_lock(&dev_priv->sb_lock);
1833
1834 /* Disable 10bit clock to display controller */
1835 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1836 val &= ~DPIO_DCLKP_EN;
1837 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1838
1839 /* disable left/right clock distribution */
1840 if (pipe != PIPE_B) {
1841 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1842 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1843 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1844 } else {
1845 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1846 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1847 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 }
1849
1850 mutex_unlock(&dev_priv->sb_lock);
1851 }
1852
1853 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1854 struct intel_digital_port *dport,
1855 unsigned int expected_mask)
1856 {
1857 u32 port_mask;
1858 int dpll_reg;
1859
1860 switch (dport->port) {
1861 case PORT_B:
1862 port_mask = DPLL_PORTB_READY_MASK;
1863 dpll_reg = DPLL(0);
1864 break;
1865 case PORT_C:
1866 port_mask = DPLL_PORTC_READY_MASK;
1867 dpll_reg = DPLL(0);
1868 expected_mask <<= 4;
1869 break;
1870 case PORT_D:
1871 port_mask = DPLL_PORTD_READY_MASK;
1872 dpll_reg = DPIO_PHY_STATUS;
1873 break;
1874 default:
1875 BUG();
1876 }
1877
1878 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1879 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1880 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1881 }
1882
1883 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 WARN_ON(!pll->config.crtc_mask);
1893 if (pll->active == 0) {
1894 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1895 WARN_ON(pll->on);
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897
1898 pll->mode_set(dev_priv, pll);
1899 }
1900 }
1901
1902 /**
1903 * intel_enable_shared_dpll - enable PCH PLL
1904 * @dev_priv: i915 private structure
1905 * @pipe: pipe PLL to enable
1906 *
1907 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1908 * drives the transcoder clock.
1909 */
1910 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1911 {
1912 struct drm_device *dev = crtc->base.dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1915
1916 if (WARN_ON(pll == NULL))
1917 return;
1918
1919 if (WARN_ON(pll->config.crtc_mask == 0))
1920 return;
1921
1922 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1923 pll->name, pll->active, pll->on,
1924 crtc->base.base.id);
1925
1926 if (pll->active++) {
1927 WARN_ON(!pll->on);
1928 assert_shared_dpll_enabled(dev_priv, pll);
1929 return;
1930 }
1931 WARN_ON(pll->on);
1932
1933 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1934
1935 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1936 pll->enable(dev_priv, pll);
1937 pll->on = true;
1938 }
1939
1940 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1941 {
1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1945
1946 /* PCH only available on ILK+ */
1947 BUG_ON(INTEL_INFO(dev)->gen < 5);
1948 if (pll == NULL)
1949 return;
1950
1951 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1952 return;
1953
1954 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1955 pll->name, pll->active, pll->on,
1956 crtc->base.base.id);
1957
1958 if (WARN_ON(pll->active == 0)) {
1959 assert_shared_dpll_disabled(dev_priv, pll);
1960 return;
1961 }
1962
1963 assert_shared_dpll_enabled(dev_priv, pll);
1964 WARN_ON(!pll->on);
1965 if (--pll->active)
1966 return;
1967
1968 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1969 pll->disable(dev_priv, pll);
1970 pll->on = false;
1971
1972 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1973 }
1974
1975 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 enum pipe pipe)
1977 {
1978 struct drm_device *dev = dev_priv->dev;
1979 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981 uint32_t reg, val, pipeconf_val;
1982
1983 /* PCH only available on ILK+ */
1984 BUG_ON(!HAS_PCH_SPLIT(dev));
1985
1986 /* Make sure PCH DPLL is enabled */
1987 assert_shared_dpll_enabled(dev_priv,
1988 intel_crtc_to_shared_dpll(intel_crtc));
1989
1990 /* FDI must be feeding us bits for PCH ports */
1991 assert_fdi_tx_enabled(dev_priv, pipe);
1992 assert_fdi_rx_enabled(dev_priv, pipe);
1993
1994 if (HAS_PCH_CPT(dev)) {
1995 /* Workaround: Set the timing override bit before enabling the
1996 * pch transcoder. */
1997 reg = TRANS_CHICKEN2(pipe);
1998 val = I915_READ(reg);
1999 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2000 I915_WRITE(reg, val);
2001 }
2002
2003 reg = PCH_TRANSCONF(pipe);
2004 val = I915_READ(reg);
2005 pipeconf_val = I915_READ(PIPECONF(pipe));
2006
2007 if (HAS_PCH_IBX(dev_priv->dev)) {
2008 /*
2009 * Make the BPC in transcoder be consistent with
2010 * that in pipeconf reg. For HDMI we must use 8bpc
2011 * here for both 8bpc and 12bpc.
2012 */
2013 val &= ~PIPECONF_BPC_MASK;
2014 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2015 val |= PIPECONF_8BPC;
2016 else
2017 val |= pipeconf_val & PIPECONF_BPC_MASK;
2018 }
2019
2020 val &= ~TRANS_INTERLACE_MASK;
2021 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2022 if (HAS_PCH_IBX(dev_priv->dev) &&
2023 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2024 val |= TRANS_LEGACY_INTERLACED_ILK;
2025 else
2026 val |= TRANS_INTERLACED;
2027 else
2028 val |= TRANS_PROGRESSIVE;
2029
2030 I915_WRITE(reg, val | TRANS_ENABLE);
2031 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2032 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2033 }
2034
2035 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2036 enum transcoder cpu_transcoder)
2037 {
2038 u32 val, pipeconf_val;
2039
2040 /* PCH only available on ILK+ */
2041 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2042
2043 /* FDI must be feeding us bits for PCH ports */
2044 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2045 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2046
2047 /* Workaround: set timing override bit. */
2048 val = I915_READ(_TRANSA_CHICKEN2);
2049 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2050 I915_WRITE(_TRANSA_CHICKEN2, val);
2051
2052 val = TRANS_ENABLE;
2053 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2054
2055 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2056 PIPECONF_INTERLACED_ILK)
2057 val |= TRANS_INTERLACED;
2058 else
2059 val |= TRANS_PROGRESSIVE;
2060
2061 I915_WRITE(LPT_TRANSCONF, val);
2062 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2063 DRM_ERROR("Failed to enable PCH transcoder\n");
2064 }
2065
2066 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067 enum pipe pipe)
2068 {
2069 struct drm_device *dev = dev_priv->dev;
2070 uint32_t reg, val;
2071
2072 /* FDI relies on the transcoder */
2073 assert_fdi_tx_disabled(dev_priv, pipe);
2074 assert_fdi_rx_disabled(dev_priv, pipe);
2075
2076 /* Ports must be off as well */
2077 assert_pch_ports_disabled(dev_priv, pipe);
2078
2079 reg = PCH_TRANSCONF(pipe);
2080 val = I915_READ(reg);
2081 val &= ~TRANS_ENABLE;
2082 I915_WRITE(reg, val);
2083 /* wait for PCH transcoder off, transcoder state */
2084 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2085 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2086
2087 if (!HAS_PCH_IBX(dev)) {
2088 /* Workaround: Clear the timing override chicken bit again. */
2089 reg = TRANS_CHICKEN2(pipe);
2090 val = I915_READ(reg);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(reg, val);
2093 }
2094 }
2095
2096 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2097 {
2098 u32 val;
2099
2100 val = I915_READ(LPT_TRANSCONF);
2101 val &= ~TRANS_ENABLE;
2102 I915_WRITE(LPT_TRANSCONF, val);
2103 /* wait for PCH transcoder off, transcoder state */
2104 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2105 DRM_ERROR("Failed to disable PCH transcoder\n");
2106
2107 /* Workaround: clear timing override bit. */
2108 val = I915_READ(_TRANSA_CHICKEN2);
2109 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2110 I915_WRITE(_TRANSA_CHICKEN2, val);
2111 }
2112
2113 /**
2114 * intel_enable_pipe - enable a pipe, asserting requirements
2115 * @crtc: crtc responsible for the pipe
2116 *
2117 * Enable @crtc's pipe, making sure that various hardware specific requirements
2118 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2119 */
2120 static void intel_enable_pipe(struct intel_crtc *crtc)
2121 {
2122 struct drm_device *dev = crtc->base.dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 enum pipe pipe = crtc->pipe;
2125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2126 pipe);
2127 enum pipe pch_transcoder;
2128 int reg;
2129 u32 val;
2130
2131 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2132
2133 assert_planes_disabled(dev_priv, pipe);
2134 assert_cursor_disabled(dev_priv, pipe);
2135 assert_sprites_disabled(dev_priv, pipe);
2136
2137 if (HAS_PCH_LPT(dev_priv->dev))
2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
2152 else {
2153 if (crtc->config->has_pch_encoder) {
2154 /* if driving the PCH, we need FDI enabled */
2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
2161
2162 reg = PIPECONF(cpu_transcoder);
2163 val = I915_READ(reg);
2164 if (val & PIPECONF_ENABLE) {
2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167 return;
2168 }
2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
2171 POSTING_READ(reg);
2172 }
2173
2174 /**
2175 * intel_disable_pipe - disable a pipe, asserting requirements
2176 * @crtc: crtc whose pipes is to be disabled
2177 *
2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2185 {
2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188 enum pipe pipe = crtc->pipe;
2189 int reg;
2190 u32 val;
2191
2192 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2193
2194 /*
2195 * Make sure planes won't keep trying to pump pixels to us,
2196 * or we might hang the display.
2197 */
2198 assert_planes_disabled(dev_priv, pipe);
2199 assert_cursor_disabled(dev_priv, pipe);
2200 assert_sprites_disabled(dev_priv, pipe);
2201
2202 reg = PIPECONF(cpu_transcoder);
2203 val = I915_READ(reg);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 return;
2206
2207 /*
2208 * Double wide has implications for planes
2209 * so best keep it disabled when not needed.
2210 */
2211 if (crtc->config->double_wide)
2212 val &= ~PIPECONF_DOUBLE_WIDE;
2213
2214 /* Don't disable pipe or pipe PLLs if needed */
2215 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2216 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2217 val &= ~PIPECONF_ENABLE;
2218
2219 I915_WRITE(reg, val);
2220 if ((val & PIPECONF_ENABLE) == 0)
2221 intel_wait_for_pipe_off(crtc);
2222 }
2223
2224 static bool need_vtd_wa(struct drm_device *dev)
2225 {
2226 #ifdef CONFIG_INTEL_IOMMU
2227 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2228 return true;
2229 #endif
2230 return false;
2231 }
2232
2233 unsigned int
2234 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2235 uint64_t fb_format_modifier)
2236 {
2237 unsigned int tile_height;
2238 uint32_t pixel_bytes;
2239
2240 switch (fb_format_modifier) {
2241 case DRM_FORMAT_MOD_NONE:
2242 tile_height = 1;
2243 break;
2244 case I915_FORMAT_MOD_X_TILED:
2245 tile_height = IS_GEN2(dev) ? 16 : 8;
2246 break;
2247 case I915_FORMAT_MOD_Y_TILED:
2248 tile_height = 32;
2249 break;
2250 case I915_FORMAT_MOD_Yf_TILED:
2251 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2252 switch (pixel_bytes) {
2253 default:
2254 case 1:
2255 tile_height = 64;
2256 break;
2257 case 2:
2258 case 4:
2259 tile_height = 32;
2260 break;
2261 case 8:
2262 tile_height = 16;
2263 break;
2264 case 16:
2265 WARN_ONCE(1,
2266 "128-bit pixels are not supported for display!");
2267 tile_height = 16;
2268 break;
2269 }
2270 break;
2271 default:
2272 MISSING_CASE(fb_format_modifier);
2273 tile_height = 1;
2274 break;
2275 }
2276
2277 return tile_height;
2278 }
2279
2280 unsigned int
2281 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2282 uint32_t pixel_format, uint64_t fb_format_modifier)
2283 {
2284 return ALIGN(height, intel_tile_height(dev, pixel_format,
2285 fb_format_modifier));
2286 }
2287
2288 static int
2289 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2290 const struct drm_plane_state *plane_state)
2291 {
2292 struct intel_rotation_info *info = &view->rotation_info;
2293 unsigned int tile_height, tile_pitch;
2294
2295 *view = i915_ggtt_view_normal;
2296
2297 if (!plane_state)
2298 return 0;
2299
2300 if (!intel_rotation_90_or_270(plane_state->rotation))
2301 return 0;
2302
2303 *view = i915_ggtt_view_rotated;
2304
2305 info->height = fb->height;
2306 info->pixel_format = fb->pixel_format;
2307 info->pitch = fb->pitches[0];
2308 info->fb_modifier = fb->modifier[0];
2309
2310 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2311 fb->modifier[0]);
2312 tile_pitch = PAGE_SIZE / tile_height;
2313 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2314 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2315 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2316
2317 return 0;
2318 }
2319
2320 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2321 {
2322 if (INTEL_INFO(dev_priv)->gen >= 9)
2323 return 256 * 1024;
2324 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2325 IS_VALLEYVIEW(dev_priv))
2326 return 128 * 1024;
2327 else if (INTEL_INFO(dev_priv)->gen >= 4)
2328 return 4 * 1024;
2329 else
2330 return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
2336 const struct drm_plane_state *plane_state,
2337 struct intel_engine_cs *pipelined,
2338 struct drm_i915_gem_request **pipelined_request)
2339 {
2340 struct drm_device *dev = fb->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2343 struct i915_ggtt_view view;
2344 u32 alignment;
2345 int ret;
2346
2347 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2348
2349 switch (fb->modifier[0]) {
2350 case DRM_FORMAT_MOD_NONE:
2351 alignment = intel_linear_alignment(dev_priv);
2352 break;
2353 case I915_FORMAT_MOD_X_TILED:
2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else {
2357 /* pin() will align the object as required by fence */
2358 alignment = 0;
2359 }
2360 break;
2361 case I915_FORMAT_MOD_Y_TILED:
2362 case I915_FORMAT_MOD_Yf_TILED:
2363 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2364 "Y tiling bo slipped through, driver bug!\n"))
2365 return -EINVAL;
2366 alignment = 1 * 1024 * 1024;
2367 break;
2368 default:
2369 MISSING_CASE(fb->modifier[0]);
2370 return -EINVAL;
2371 }
2372
2373 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 if (ret)
2375 return ret;
2376
2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
2394 dev_priv->mm.interruptible = false;
2395 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2396 pipelined_request, &view);
2397 if (ret)
2398 goto err_interruptible;
2399
2400 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2401 * fence, whereas 965+ only requires a fence if using
2402 * framebuffer compression. For simplicity, we always install
2403 * a fence as the cost is not that onerous.
2404 */
2405 ret = i915_gem_object_get_fence(obj);
2406 if (ret)
2407 goto err_unpin;
2408
2409 i915_gem_object_pin_fence(obj);
2410
2411 dev_priv->mm.interruptible = true;
2412 intel_runtime_pm_put(dev_priv);
2413 return 0;
2414
2415 err_unpin:
2416 i915_gem_object_unpin_from_display_plane(obj, &view);
2417 err_interruptible:
2418 dev_priv->mm.interruptible = true;
2419 intel_runtime_pm_put(dev_priv);
2420 return ret;
2421 }
2422
2423 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
2425 {
2426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2427 struct i915_ggtt_view view;
2428 int ret;
2429
2430 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433 WARN_ONCE(ret, "Couldn't get view from plane state!");
2434
2435 i915_gem_object_unpin_fence(obj);
2436 i915_gem_object_unpin_from_display_plane(obj, &view);
2437 }
2438
2439 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
2441 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442 int *x, int *y,
2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
2446 {
2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
2449
2450 tile_rows = *y / 8;
2451 *y %= 8;
2452
2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
2458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
2462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
2465 }
2466 }
2467
2468 static int i9xx_format_to_fourcc(int format)
2469 {
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487 }
2488
2489 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490 {
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513 }
2514
2515 static bool
2516 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
2518 {
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2522 struct drm_framebuffer *fb = &plane_config->fb->base;
2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
2528
2529 if (plane_config->size == 0)
2530 return false;
2531
2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
2536 if (!obj)
2537 return false;
2538
2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
2541 obj->stride = fb->pitches[0];
2542
2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2549
2550 mutex_lock(&dev->struct_mutex);
2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2552 &mode_cmd, obj)) {
2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
2556 mutex_unlock(&dev->struct_mutex);
2557
2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2559 return true;
2560
2561 out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
2564 return false;
2565 }
2566
2567 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2568 static void
2569 update_state_fb(struct drm_plane *plane)
2570 {
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579 }
2580
2581 static void
2582 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
2584 {
2585 struct drm_device *dev = intel_crtc->base.dev;
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2589 struct drm_i915_gem_object *obj;
2590 struct drm_plane *primary = intel_crtc->base.primary;
2591 struct drm_framebuffer *fb;
2592
2593 if (!plane_config->fb)
2594 return;
2595
2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
2599 }
2600
2601 kfree(plane_config->fb);
2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
2607 for_each_crtc(dev, c) {
2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2613 if (!i->active)
2614 continue;
2615
2616 fb = c->primary->fb;
2617 if (!fb)
2618 continue;
2619
2620 obj = intel_fb_obj(fb);
2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
2624 }
2625 }
2626
2627 return;
2628
2629 valid_fb:
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 primary->fb = fb;
2635 primary->crtc = primary->state->crtc = &intel_crtc->base;
2636 update_state_fb(primary);
2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642 struct drm_framebuffer *fb,
2643 int x, int y)
2644 {
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648 struct drm_plane *primary = crtc->primary;
2649 bool visible = to_intel_plane_state(primary->state)->visible;
2650 struct drm_i915_gem_object *obj;
2651 int plane = intel_crtc->plane;
2652 unsigned long linear_offset;
2653 u32 dspcntr;
2654 u32 reg = DSPCNTR(plane);
2655 int pixel_size;
2656
2657 if (!visible || !fb) {
2658 I915_WRITE(reg, 0);
2659 if (INTEL_INFO(dev)->gen >= 4)
2660 I915_WRITE(DSPSURF(plane), 0);
2661 else
2662 I915_WRITE(DSPADDR(plane), 0);
2663 POSTING_READ(reg);
2664 return;
2665 }
2666
2667 obj = intel_fb_obj(fb);
2668 if (WARN_ON(obj == NULL))
2669 return;
2670
2671 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
2673 dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
2675 dspcntr |= DISPLAY_PLANE_ENABLE;
2676
2677 if (INTEL_INFO(dev)->gen < 4) {
2678 if (intel_crtc->pipe == PIPE_B)
2679 dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681 /* pipesrc and dspsize control the size that is scaled from,
2682 * which should always be the user's requested size.
2683 */
2684 I915_WRITE(DSPSIZE(plane),
2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
2687 I915_WRITE(DSPPOS(plane), 0);
2688 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689 I915_WRITE(PRIMSIZE(plane),
2690 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691 (intel_crtc->config->pipe_src_w - 1));
2692 I915_WRITE(PRIMPOS(plane), 0);
2693 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2694 }
2695
2696 switch (fb->pixel_format) {
2697 case DRM_FORMAT_C8:
2698 dspcntr |= DISPPLANE_8BPP;
2699 break;
2700 case DRM_FORMAT_XRGB1555:
2701 dspcntr |= DISPPLANE_BGRX555;
2702 break;
2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
2707 dspcntr |= DISPPLANE_BGRX888;
2708 break;
2709 case DRM_FORMAT_XBGR8888:
2710 dspcntr |= DISPPLANE_RGBX888;
2711 break;
2712 case DRM_FORMAT_XRGB2101010:
2713 dspcntr |= DISPPLANE_BGRX101010;
2714 break;
2715 case DRM_FORMAT_XBGR2101010:
2716 dspcntr |= DISPPLANE_RGBX101010;
2717 break;
2718 default:
2719 BUG();
2720 }
2721
2722 if (INTEL_INFO(dev)->gen >= 4 &&
2723 obj->tiling_mode != I915_TILING_NONE)
2724 dspcntr |= DISPPLANE_TILED;
2725
2726 if (IS_G4X(dev))
2727 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
2729 linear_offset = y * fb->pitches[0] + x * pixel_size;
2730
2731 if (INTEL_INFO(dev)->gen >= 4) {
2732 intel_crtc->dspaddr_offset =
2733 intel_gen4_compute_page_offset(dev_priv,
2734 &x, &y, obj->tiling_mode,
2735 pixel_size,
2736 fb->pitches[0]);
2737 linear_offset -= intel_crtc->dspaddr_offset;
2738 } else {
2739 intel_crtc->dspaddr_offset = linear_offset;
2740 }
2741
2742 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2743 dspcntr |= DISPPLANE_ROTATE_180;
2744
2745 x += (intel_crtc->config->pipe_src_w - 1);
2746 y += (intel_crtc->config->pipe_src_h - 1);
2747
2748 /* Finding the last pixel of the last line of the display
2749 data and adding to linear_offset*/
2750 linear_offset +=
2751 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2752 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2753 }
2754
2755 I915_WRITE(reg, dspcntr);
2756
2757 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2758 if (INTEL_INFO(dev)->gen >= 4) {
2759 I915_WRITE(DSPSURF(plane),
2760 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2761 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2762 I915_WRITE(DSPLINOFF(plane), linear_offset);
2763 } else
2764 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2765 POSTING_READ(reg);
2766 }
2767
2768 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2769 struct drm_framebuffer *fb,
2770 int x, int y)
2771 {
2772 struct drm_device *dev = crtc->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2775 struct drm_plane *primary = crtc->primary;
2776 bool visible = to_intel_plane_state(primary->state)->visible;
2777 struct drm_i915_gem_object *obj;
2778 int plane = intel_crtc->plane;
2779 unsigned long linear_offset;
2780 u32 dspcntr;
2781 u32 reg = DSPCNTR(plane);
2782 int pixel_size;
2783
2784 if (!visible || !fb) {
2785 I915_WRITE(reg, 0);
2786 I915_WRITE(DSPSURF(plane), 0);
2787 POSTING_READ(reg);
2788 return;
2789 }
2790
2791 obj = intel_fb_obj(fb);
2792 if (WARN_ON(obj == NULL))
2793 return;
2794
2795 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2796
2797 dspcntr = DISPPLANE_GAMMA_ENABLE;
2798
2799 dspcntr |= DISPLAY_PLANE_ENABLE;
2800
2801 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2802 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2803
2804 switch (fb->pixel_format) {
2805 case DRM_FORMAT_C8:
2806 dspcntr |= DISPPLANE_8BPP;
2807 break;
2808 case DRM_FORMAT_RGB565:
2809 dspcntr |= DISPPLANE_BGRX565;
2810 break;
2811 case DRM_FORMAT_XRGB8888:
2812 dspcntr |= DISPPLANE_BGRX888;
2813 break;
2814 case DRM_FORMAT_XBGR8888:
2815 dspcntr |= DISPPLANE_RGBX888;
2816 break;
2817 case DRM_FORMAT_XRGB2101010:
2818 dspcntr |= DISPPLANE_BGRX101010;
2819 break;
2820 case DRM_FORMAT_XBGR2101010:
2821 dspcntr |= DISPPLANE_RGBX101010;
2822 break;
2823 default:
2824 BUG();
2825 }
2826
2827 if (obj->tiling_mode != I915_TILING_NONE)
2828 dspcntr |= DISPPLANE_TILED;
2829
2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2831 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2832
2833 linear_offset = y * fb->pitches[0] + x * pixel_size;
2834 intel_crtc->dspaddr_offset =
2835 intel_gen4_compute_page_offset(dev_priv,
2836 &x, &y, obj->tiling_mode,
2837 pixel_size,
2838 fb->pitches[0]);
2839 linear_offset -= intel_crtc->dspaddr_offset;
2840 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2841 dspcntr |= DISPPLANE_ROTATE_180;
2842
2843 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2844 x += (intel_crtc->config->pipe_src_w - 1);
2845 y += (intel_crtc->config->pipe_src_h - 1);
2846
2847 /* Finding the last pixel of the last line of the display
2848 data and adding to linear_offset*/
2849 linear_offset +=
2850 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2851 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2852 }
2853 }
2854
2855 I915_WRITE(reg, dspcntr);
2856
2857 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2858 I915_WRITE(DSPSURF(plane),
2859 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2860 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2861 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2862 } else {
2863 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2864 I915_WRITE(DSPLINOFF(plane), linear_offset);
2865 }
2866 POSTING_READ(reg);
2867 }
2868
2869 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2870 uint32_t pixel_format)
2871 {
2872 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2873
2874 /*
2875 * The stride is either expressed as a multiple of 64 bytes
2876 * chunks for linear buffers or in number of tiles for tiled
2877 * buffers.
2878 */
2879 switch (fb_modifier) {
2880 case DRM_FORMAT_MOD_NONE:
2881 return 64;
2882 case I915_FORMAT_MOD_X_TILED:
2883 if (INTEL_INFO(dev)->gen == 2)
2884 return 128;
2885 return 512;
2886 case I915_FORMAT_MOD_Y_TILED:
2887 /* No need to check for old gens and Y tiling since this is
2888 * about the display engine and those will be blocked before
2889 * we get here.
2890 */
2891 return 128;
2892 case I915_FORMAT_MOD_Yf_TILED:
2893 if (bits_per_pixel == 8)
2894 return 64;
2895 else
2896 return 128;
2897 default:
2898 MISSING_CASE(fb_modifier);
2899 return 64;
2900 }
2901 }
2902
2903 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2904 struct drm_i915_gem_object *obj)
2905 {
2906 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2907
2908 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2909 view = &i915_ggtt_view_rotated;
2910
2911 return i915_gem_obj_ggtt_offset_view(obj, view);
2912 }
2913
2914 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2915 {
2916 struct drm_device *dev = intel_crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918
2919 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2920 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2921 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2922 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2923 intel_crtc->base.base.id, intel_crtc->pipe, id);
2924 }
2925
2926 /*
2927 * This function detaches (aka. unbinds) unused scalers in hardware
2928 */
2929 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2930 {
2931 struct intel_crtc_scaler_state *scaler_state;
2932 int i;
2933
2934 scaler_state = &intel_crtc->config->scaler_state;
2935
2936 /* loop through and disable scalers that aren't in use */
2937 for (i = 0; i < intel_crtc->num_scalers; i++) {
2938 if (!scaler_state->scalers[i].in_use)
2939 skl_detach_scaler(intel_crtc, i);
2940 }
2941 }
2942
2943 u32 skl_plane_ctl_format(uint32_t pixel_format)
2944 {
2945 switch (pixel_format) {
2946 case DRM_FORMAT_C8:
2947 return PLANE_CTL_FORMAT_INDEXED;
2948 case DRM_FORMAT_RGB565:
2949 return PLANE_CTL_FORMAT_RGB_565;
2950 case DRM_FORMAT_XBGR8888:
2951 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2952 case DRM_FORMAT_XRGB8888:
2953 return PLANE_CTL_FORMAT_XRGB_8888;
2954 /*
2955 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2956 * to be already pre-multiplied. We need to add a knob (or a different
2957 * DRM_FORMAT) for user-space to configure that.
2958 */
2959 case DRM_FORMAT_ABGR8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2961 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2962 case DRM_FORMAT_ARGB8888:
2963 return PLANE_CTL_FORMAT_XRGB_8888 |
2964 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2965 case DRM_FORMAT_XRGB2101010:
2966 return PLANE_CTL_FORMAT_XRGB_2101010;
2967 case DRM_FORMAT_XBGR2101010:
2968 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2969 case DRM_FORMAT_YUYV:
2970 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2971 case DRM_FORMAT_YVYU:
2972 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2973 case DRM_FORMAT_UYVY:
2974 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2975 case DRM_FORMAT_VYUY:
2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2977 default:
2978 MISSING_CASE(pixel_format);
2979 }
2980
2981 return 0;
2982 }
2983
2984 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2985 {
2986 switch (fb_modifier) {
2987 case DRM_FORMAT_MOD_NONE:
2988 break;
2989 case I915_FORMAT_MOD_X_TILED:
2990 return PLANE_CTL_TILED_X;
2991 case I915_FORMAT_MOD_Y_TILED:
2992 return PLANE_CTL_TILED_Y;
2993 case I915_FORMAT_MOD_Yf_TILED:
2994 return PLANE_CTL_TILED_YF;
2995 default:
2996 MISSING_CASE(fb_modifier);
2997 }
2998
2999 return 0;
3000 }
3001
3002 u32 skl_plane_ctl_rotation(unsigned int rotation)
3003 {
3004 switch (rotation) {
3005 case BIT(DRM_ROTATE_0):
3006 break;
3007 /*
3008 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3009 * while i915 HW rotation is clockwise, thats why this swapping.
3010 */
3011 case BIT(DRM_ROTATE_90):
3012 return PLANE_CTL_ROTATE_270;
3013 case BIT(DRM_ROTATE_180):
3014 return PLANE_CTL_ROTATE_180;
3015 case BIT(DRM_ROTATE_270):
3016 return PLANE_CTL_ROTATE_90;
3017 default:
3018 MISSING_CASE(rotation);
3019 }
3020
3021 return 0;
3022 }
3023
3024 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3025 struct drm_framebuffer *fb,
3026 int x, int y)
3027 {
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 struct drm_plane *plane = crtc->primary;
3032 bool visible = to_intel_plane_state(plane->state)->visible;
3033 struct drm_i915_gem_object *obj;
3034 int pipe = intel_crtc->pipe;
3035 u32 plane_ctl, stride_div, stride;
3036 u32 tile_height, plane_offset, plane_size;
3037 unsigned int rotation;
3038 int x_offset, y_offset;
3039 unsigned long surf_addr;
3040 struct intel_crtc_state *crtc_state = intel_crtc->config;
3041 struct intel_plane_state *plane_state;
3042 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3043 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3044 int scaler_id = -1;
3045
3046 plane_state = to_intel_plane_state(plane->state);
3047
3048 if (!visible || !fb) {
3049 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3050 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3051 POSTING_READ(PLANE_CTL(pipe, 0));
3052 return;
3053 }
3054
3055 plane_ctl = PLANE_CTL_ENABLE |
3056 PLANE_CTL_PIPE_GAMMA_ENABLE |
3057 PLANE_CTL_PIPE_CSC_ENABLE;
3058
3059 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3060 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3061 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3062
3063 rotation = plane->state->rotation;
3064 plane_ctl |= skl_plane_ctl_rotation(rotation);
3065
3066 obj = intel_fb_obj(fb);
3067 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3068 fb->pixel_format);
3069 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3070
3071 /*
3072 * FIXME: intel_plane_state->src, dst aren't set when transitional
3073 * update_plane helpers are called from legacy paths.
3074 * Once full atomic crtc is available, below check can be avoided.
3075 */
3076 if (drm_rect_width(&plane_state->src)) {
3077 scaler_id = plane_state->scaler_id;
3078 src_x = plane_state->src.x1 >> 16;
3079 src_y = plane_state->src.y1 >> 16;
3080 src_w = drm_rect_width(&plane_state->src) >> 16;
3081 src_h = drm_rect_height(&plane_state->src) >> 16;
3082 dst_x = plane_state->dst.x1;
3083 dst_y = plane_state->dst.y1;
3084 dst_w = drm_rect_width(&plane_state->dst);
3085 dst_h = drm_rect_height(&plane_state->dst);
3086
3087 WARN_ON(x != src_x || y != src_y);
3088 } else {
3089 src_w = intel_crtc->config->pipe_src_w;
3090 src_h = intel_crtc->config->pipe_src_h;
3091 }
3092
3093 if (intel_rotation_90_or_270(rotation)) {
3094 /* stride = Surface height in tiles */
3095 tile_height = intel_tile_height(dev, fb->pixel_format,
3096 fb->modifier[0]);
3097 stride = DIV_ROUND_UP(fb->height, tile_height);
3098 x_offset = stride * tile_height - y - src_h;
3099 y_offset = x;
3100 plane_size = (src_w - 1) << 16 | (src_h - 1);
3101 } else {
3102 stride = fb->pitches[0] / stride_div;
3103 x_offset = x;
3104 y_offset = y;
3105 plane_size = (src_h - 1) << 16 | (src_w - 1);
3106 }
3107 plane_offset = y_offset << 16 | x_offset;
3108
3109 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3110 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3111 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3112 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3113
3114 if (scaler_id >= 0) {
3115 uint32_t ps_ctrl = 0;
3116
3117 WARN_ON(!dst_w || !dst_h);
3118 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3119 crtc_state->scaler_state.scalers[scaler_id].mode;
3120 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3121 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3122 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3123 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3124 I915_WRITE(PLANE_POS(pipe, 0), 0);
3125 } else {
3126 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3127 }
3128
3129 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3130
3131 POSTING_READ(PLANE_SURF(pipe, 0));
3132 }
3133
3134 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3135 static int
3136 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3137 int x, int y, enum mode_set_atomic state)
3138 {
3139 struct drm_device *dev = crtc->dev;
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141
3142 if (dev_priv->fbc.disable_fbc)
3143 dev_priv->fbc.disable_fbc(dev_priv);
3144
3145 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3146
3147 return 0;
3148 }
3149
3150 static void intel_complete_page_flips(struct drm_device *dev)
3151 {
3152 struct drm_crtc *crtc;
3153
3154 for_each_crtc(dev, crtc) {
3155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3156 enum plane plane = intel_crtc->plane;
3157
3158 intel_prepare_page_flip(dev, plane);
3159 intel_finish_page_flip_plane(dev, plane);
3160 }
3161 }
3162
3163 static void intel_update_primary_planes(struct drm_device *dev)
3164 {
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct drm_crtc *crtc;
3167
3168 for_each_crtc(dev, crtc) {
3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170
3171 drm_modeset_lock(&crtc->mutex, NULL);
3172 /*
3173 * FIXME: Once we have proper support for primary planes (and
3174 * disabling them without disabling the entire crtc) allow again
3175 * a NULL crtc->primary->fb.
3176 */
3177 if (intel_crtc->active && crtc->primary->fb)
3178 dev_priv->display.update_primary_plane(crtc,
3179 crtc->primary->fb,
3180 crtc->x,
3181 crtc->y);
3182 drm_modeset_unlock(&crtc->mutex);
3183 }
3184 }
3185
3186 void intel_prepare_reset(struct drm_device *dev)
3187 {
3188 /* no reset support for gen2 */
3189 if (IS_GEN2(dev))
3190 return;
3191
3192 /* reset doesn't touch the display */
3193 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3194 return;
3195
3196 drm_modeset_lock_all(dev);
3197 /*
3198 * Disabling the crtcs gracefully seems nicer. Also the
3199 * g33 docs say we should at least disable all the planes.
3200 */
3201 intel_display_suspend(dev);
3202 }
3203
3204 void intel_finish_reset(struct drm_device *dev)
3205 {
3206 struct drm_i915_private *dev_priv = to_i915(dev);
3207
3208 /*
3209 * Flips in the rings will be nuked by the reset,
3210 * so complete all pending flips so that user space
3211 * will get its events and not get stuck.
3212 */
3213 intel_complete_page_flips(dev);
3214
3215 /* no reset support for gen2 */
3216 if (IS_GEN2(dev))
3217 return;
3218
3219 /* reset doesn't touch the display */
3220 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3221 /*
3222 * Flips in the rings have been nuked by the reset,
3223 * so update the base address of all primary
3224 * planes to the the last fb to make sure we're
3225 * showing the correct fb after a reset.
3226 */
3227 intel_update_primary_planes(dev);
3228 return;
3229 }
3230
3231 /*
3232 * The display has been reset as well,
3233 * so need a full re-initialization.
3234 */
3235 intel_runtime_pm_disable_interrupts(dev_priv);
3236 intel_runtime_pm_enable_interrupts(dev_priv);
3237
3238 intel_modeset_init_hw(dev);
3239
3240 spin_lock_irq(&dev_priv->irq_lock);
3241 if (dev_priv->display.hpd_irq_setup)
3242 dev_priv->display.hpd_irq_setup(dev);
3243 spin_unlock_irq(&dev_priv->irq_lock);
3244
3245 intel_modeset_setup_hw_state(dev, true);
3246
3247 intel_hpd_init(dev_priv);
3248
3249 drm_modeset_unlock_all(dev);
3250 }
3251
3252 static void
3253 intel_finish_fb(struct drm_framebuffer *old_fb)
3254 {
3255 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3256 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3257 bool was_interruptible = dev_priv->mm.interruptible;
3258 int ret;
3259
3260 /* Big Hammer, we also need to ensure that any pending
3261 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3262 * current scanout is retired before unpinning the old
3263 * framebuffer. Note that we rely on userspace rendering
3264 * into the buffer attached to the pipe they are waiting
3265 * on. If not, userspace generates a GPU hang with IPEHR
3266 * point to the MI_WAIT_FOR_EVENT.
3267 *
3268 * This should only fail upon a hung GPU, in which case we
3269 * can safely continue.
3270 */
3271 dev_priv->mm.interruptible = false;
3272 ret = i915_gem_object_wait_rendering(obj, true);
3273 dev_priv->mm.interruptible = was_interruptible;
3274
3275 WARN_ON(ret);
3276 }
3277
3278 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3279 {
3280 struct drm_device *dev = crtc->dev;
3281 struct drm_i915_private *dev_priv = dev->dev_private;
3282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3283 bool pending;
3284
3285 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3286 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3287 return false;
3288
3289 spin_lock_irq(&dev->event_lock);
3290 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3291 spin_unlock_irq(&dev->event_lock);
3292
3293 return pending;
3294 }
3295
3296 static void intel_update_pipe_size(struct intel_crtc *crtc)
3297 {
3298 struct drm_device *dev = crtc->base.dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 const struct drm_display_mode *adjusted_mode;
3301
3302 if (!i915.fastboot)
3303 return;
3304
3305 /*
3306 * Update pipe size and adjust fitter if needed: the reason for this is
3307 * that in compute_mode_changes we check the native mode (not the pfit
3308 * mode) to see if we can flip rather than do a full mode set. In the
3309 * fastboot case, we'll flip, but if we don't update the pipesrc and
3310 * pfit state, we'll end up with a big fb scanned out into the wrong
3311 * sized surface.
3312 *
3313 * To fix this properly, we need to hoist the checks up into
3314 * compute_mode_changes (or above), check the actual pfit state and
3315 * whether the platform allows pfit disable with pipe active, and only
3316 * then update the pipesrc and pfit state, even on the flip path.
3317 */
3318
3319 adjusted_mode = &crtc->config->base.adjusted_mode;
3320
3321 I915_WRITE(PIPESRC(crtc->pipe),
3322 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3323 (adjusted_mode->crtc_vdisplay - 1));
3324 if (!crtc->config->pch_pfit.enabled &&
3325 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3326 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3327 I915_WRITE(PF_CTL(crtc->pipe), 0);
3328 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3329 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3330 }
3331 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3332 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3333 }
3334
3335 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3336 {
3337 struct drm_device *dev = crtc->dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int pipe = intel_crtc->pipe;
3341 u32 reg, temp;
3342
3343 /* enable normal train */
3344 reg = FDI_TX_CTL(pipe);
3345 temp = I915_READ(reg);
3346 if (IS_IVYBRIDGE(dev)) {
3347 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3348 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3349 } else {
3350 temp &= ~FDI_LINK_TRAIN_NONE;
3351 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3352 }
3353 I915_WRITE(reg, temp);
3354
3355 reg = FDI_RX_CTL(pipe);
3356 temp = I915_READ(reg);
3357 if (HAS_PCH_CPT(dev)) {
3358 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3359 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3360 } else {
3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_NONE;
3363 }
3364 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3365
3366 /* wait one idle pattern time */
3367 POSTING_READ(reg);
3368 udelay(1000);
3369
3370 /* IVB wants error correction enabled */
3371 if (IS_IVYBRIDGE(dev))
3372 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3373 FDI_FE_ERRC_ENABLE);
3374 }
3375
3376 /* The FDI link training functions for ILK/Ibexpeak. */
3377 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3378 {
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp, tries;
3384
3385 /* FDI needs bits from pipe first */
3386 assert_pipe_enabled(dev_priv, pipe);
3387
3388 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3389 for train result */
3390 reg = FDI_RX_IMR(pipe);
3391 temp = I915_READ(reg);
3392 temp &= ~FDI_RX_SYMBOL_LOCK;
3393 temp &= ~FDI_RX_BIT_LOCK;
3394 I915_WRITE(reg, temp);
3395 I915_READ(reg);
3396 udelay(150);
3397
3398 /* enable CPU FDI TX and PCH FDI RX */
3399 reg = FDI_TX_CTL(pipe);
3400 temp = I915_READ(reg);
3401 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3402 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_PATTERN_1;
3405 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3406
3407 reg = FDI_RX_CTL(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_LINK_TRAIN_NONE;
3410 temp |= FDI_LINK_TRAIN_PATTERN_1;
3411 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3412
3413 POSTING_READ(reg);
3414 udelay(150);
3415
3416 /* Ironlake workaround, enable clock pointer after FDI enable*/
3417 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3419 FDI_RX_PHASE_SYNC_POINTER_EN);
3420
3421 reg = FDI_RX_IIR(pipe);
3422 for (tries = 0; tries < 5; tries++) {
3423 temp = I915_READ(reg);
3424 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3425
3426 if ((temp & FDI_RX_BIT_LOCK)) {
3427 DRM_DEBUG_KMS("FDI train 1 done.\n");
3428 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3429 break;
3430 }
3431 }
3432 if (tries == 5)
3433 DRM_ERROR("FDI train 1 fail!\n");
3434
3435 /* Train 2 */
3436 reg = FDI_TX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_2;
3440 I915_WRITE(reg, temp);
3441
3442 reg = FDI_RX_CTL(pipe);
3443 temp = I915_READ(reg);
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_2;
3446 I915_WRITE(reg, temp);
3447
3448 POSTING_READ(reg);
3449 udelay(150);
3450
3451 reg = FDI_RX_IIR(pipe);
3452 for (tries = 0; tries < 5; tries++) {
3453 temp = I915_READ(reg);
3454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3455
3456 if (temp & FDI_RX_SYMBOL_LOCK) {
3457 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3458 DRM_DEBUG_KMS("FDI train 2 done.\n");
3459 break;
3460 }
3461 }
3462 if (tries == 5)
3463 DRM_ERROR("FDI train 2 fail!\n");
3464
3465 DRM_DEBUG_KMS("FDI train done\n");
3466
3467 }
3468
3469 static const int snb_b_fdi_train_param[] = {
3470 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3471 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3472 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3473 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3474 };
3475
3476 /* The FDI link training functions for SNB/Cougarpoint. */
3477 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3478 {
3479 struct drm_device *dev = crtc->dev;
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482 int pipe = intel_crtc->pipe;
3483 u32 reg, temp, i, retry;
3484
3485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3486 for train result */
3487 reg = FDI_RX_IMR(pipe);
3488 temp = I915_READ(reg);
3489 temp &= ~FDI_RX_SYMBOL_LOCK;
3490 temp &= ~FDI_RX_BIT_LOCK;
3491 I915_WRITE(reg, temp);
3492
3493 POSTING_READ(reg);
3494 udelay(150);
3495
3496 /* enable CPU FDI TX and PCH FDI RX */
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3500 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3501 temp &= ~FDI_LINK_TRAIN_NONE;
3502 temp |= FDI_LINK_TRAIN_PATTERN_1;
3503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3504 /* SNB-B */
3505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3506 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3507
3508 I915_WRITE(FDI_RX_MISC(pipe),
3509 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3510
3511 reg = FDI_RX_CTL(pipe);
3512 temp = I915_READ(reg);
3513 if (HAS_PCH_CPT(dev)) {
3514 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3515 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3516 } else {
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1;
3519 }
3520 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3521
3522 POSTING_READ(reg);
3523 udelay(150);
3524
3525 for (i = 0; i < 4; i++) {
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3529 temp |= snb_b_fdi_train_param[i];
3530 I915_WRITE(reg, temp);
3531
3532 POSTING_READ(reg);
3533 udelay(500);
3534
3535 for (retry = 0; retry < 5; retry++) {
3536 reg = FDI_RX_IIR(pipe);
3537 temp = I915_READ(reg);
3538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3539 if (temp & FDI_RX_BIT_LOCK) {
3540 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3541 DRM_DEBUG_KMS("FDI train 1 done.\n");
3542 break;
3543 }
3544 udelay(50);
3545 }
3546 if (retry < 5)
3547 break;
3548 }
3549 if (i == 4)
3550 DRM_ERROR("FDI train 1 fail!\n");
3551
3552 /* Train 2 */
3553 reg = FDI_TX_CTL(pipe);
3554 temp = I915_READ(reg);
3555 temp &= ~FDI_LINK_TRAIN_NONE;
3556 temp |= FDI_LINK_TRAIN_PATTERN_2;
3557 if (IS_GEN6(dev)) {
3558 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3559 /* SNB-B */
3560 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3561 }
3562 I915_WRITE(reg, temp);
3563
3564 reg = FDI_RX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 if (HAS_PCH_CPT(dev)) {
3567 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3569 } else {
3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 }
3573 I915_WRITE(reg, temp);
3574
3575 POSTING_READ(reg);
3576 udelay(150);
3577
3578 for (i = 0; i < 4; i++) {
3579 reg = FDI_TX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3582 temp |= snb_b_fdi_train_param[i];
3583 I915_WRITE(reg, temp);
3584
3585 POSTING_READ(reg);
3586 udelay(500);
3587
3588 for (retry = 0; retry < 5; retry++) {
3589 reg = FDI_RX_IIR(pipe);
3590 temp = I915_READ(reg);
3591 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3592 if (temp & FDI_RX_SYMBOL_LOCK) {
3593 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3594 DRM_DEBUG_KMS("FDI train 2 done.\n");
3595 break;
3596 }
3597 udelay(50);
3598 }
3599 if (retry < 5)
3600 break;
3601 }
3602 if (i == 4)
3603 DRM_ERROR("FDI train 2 fail!\n");
3604
3605 DRM_DEBUG_KMS("FDI train done.\n");
3606 }
3607
3608 /* Manual link training for Ivy Bridge A0 parts */
3609 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3610 {
3611 struct drm_device *dev = crtc->dev;
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 int pipe = intel_crtc->pipe;
3615 u32 reg, temp, i, j;
3616
3617 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3618 for train result */
3619 reg = FDI_RX_IMR(pipe);
3620 temp = I915_READ(reg);
3621 temp &= ~FDI_RX_SYMBOL_LOCK;
3622 temp &= ~FDI_RX_BIT_LOCK;
3623 I915_WRITE(reg, temp);
3624
3625 POSTING_READ(reg);
3626 udelay(150);
3627
3628 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3629 I915_READ(FDI_RX_IIR(pipe)));
3630
3631 /* Try each vswing and preemphasis setting twice before moving on */
3632 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3633 /* disable first in case we need to retry */
3634 reg = FDI_TX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3637 temp &= ~FDI_TX_ENABLE;
3638 I915_WRITE(reg, temp);
3639
3640 reg = FDI_RX_CTL(pipe);
3641 temp = I915_READ(reg);
3642 temp &= ~FDI_LINK_TRAIN_AUTO;
3643 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3644 temp &= ~FDI_RX_ENABLE;
3645 I915_WRITE(reg, temp);
3646
3647 /* enable CPU FDI TX and PCH FDI RX */
3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3651 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3652 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3653 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3654 temp |= snb_b_fdi_train_param[j/2];
3655 temp |= FDI_COMPOSITE_SYNC;
3656 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3657
3658 I915_WRITE(FDI_RX_MISC(pipe),
3659 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3660
3661 reg = FDI_RX_CTL(pipe);
3662 temp = I915_READ(reg);
3663 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3664 temp |= FDI_COMPOSITE_SYNC;
3665 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3666
3667 POSTING_READ(reg);
3668 udelay(1); /* should be 0.5us */
3669
3670 for (i = 0; i < 4; i++) {
3671 reg = FDI_RX_IIR(pipe);
3672 temp = I915_READ(reg);
3673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3674
3675 if (temp & FDI_RX_BIT_LOCK ||
3676 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3677 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3678 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3679 i);
3680 break;
3681 }
3682 udelay(1); /* should be 0.5us */
3683 }
3684 if (i == 4) {
3685 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3686 continue;
3687 }
3688
3689 /* Train 2 */
3690 reg = FDI_TX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3693 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3694 I915_WRITE(reg, temp);
3695
3696 reg = FDI_RX_CTL(pipe);
3697 temp = I915_READ(reg);
3698 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3699 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3700 I915_WRITE(reg, temp);
3701
3702 POSTING_READ(reg);
3703 udelay(2); /* should be 1.5us */
3704
3705 for (i = 0; i < 4; i++) {
3706 reg = FDI_RX_IIR(pipe);
3707 temp = I915_READ(reg);
3708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3709
3710 if (temp & FDI_RX_SYMBOL_LOCK ||
3711 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3713 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3714 i);
3715 goto train_done;
3716 }
3717 udelay(2); /* should be 1.5us */
3718 }
3719 if (i == 4)
3720 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3721 }
3722
3723 train_done:
3724 DRM_DEBUG_KMS("FDI train done.\n");
3725 }
3726
3727 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3728 {
3729 struct drm_device *dev = intel_crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 int pipe = intel_crtc->pipe;
3732 u32 reg, temp;
3733
3734
3735 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3739 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3741 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3742
3743 POSTING_READ(reg);
3744 udelay(200);
3745
3746 /* Switch from Rawclk to PCDclk */
3747 temp = I915_READ(reg);
3748 I915_WRITE(reg, temp | FDI_PCDCLK);
3749
3750 POSTING_READ(reg);
3751 udelay(200);
3752
3753 /* Enable CPU FDI TX PLL, always on for Ironlake */
3754 reg = FDI_TX_CTL(pipe);
3755 temp = I915_READ(reg);
3756 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3757 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3758
3759 POSTING_READ(reg);
3760 udelay(100);
3761 }
3762 }
3763
3764 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3765 {
3766 struct drm_device *dev = intel_crtc->base.dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 int pipe = intel_crtc->pipe;
3769 u32 reg, temp;
3770
3771 /* Switch from PCDclk to Rawclk */
3772 reg = FDI_RX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3775
3776 /* Disable CPU FDI TX PLL */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3780
3781 POSTING_READ(reg);
3782 udelay(100);
3783
3784 reg = FDI_RX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3787
3788 /* Wait for the clocks to turn off. */
3789 POSTING_READ(reg);
3790 udelay(100);
3791 }
3792
3793 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3794 {
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
3799 u32 reg, temp;
3800
3801 /* disable CPU FDI tx and PCH FDI rx */
3802 reg = FDI_TX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3805 POSTING_READ(reg);
3806
3807 reg = FDI_RX_CTL(pipe);
3808 temp = I915_READ(reg);
3809 temp &= ~(0x7 << 16);
3810 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3811 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3812
3813 POSTING_READ(reg);
3814 udelay(100);
3815
3816 /* Ironlake workaround, disable clock pointer after downing FDI */
3817 if (HAS_PCH_IBX(dev))
3818 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3819
3820 /* still set train pattern 1 */
3821 reg = FDI_TX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 temp &= ~FDI_LINK_TRAIN_NONE;
3824 temp |= FDI_LINK_TRAIN_PATTERN_1;
3825 I915_WRITE(reg, temp);
3826
3827 reg = FDI_RX_CTL(pipe);
3828 temp = I915_READ(reg);
3829 if (HAS_PCH_CPT(dev)) {
3830 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3832 } else {
3833 temp &= ~FDI_LINK_TRAIN_NONE;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1;
3835 }
3836 /* BPC in FDI rx is consistent with that in PIPECONF */
3837 temp &= ~(0x07 << 16);
3838 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3839 I915_WRITE(reg, temp);
3840
3841 POSTING_READ(reg);
3842 udelay(100);
3843 }
3844
3845 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3846 {
3847 struct intel_crtc *crtc;
3848
3849 /* Note that we don't need to be called with mode_config.lock here
3850 * as our list of CRTC objects is static for the lifetime of the
3851 * device and so cannot disappear as we iterate. Similarly, we can
3852 * happily treat the predicates as racy, atomic checks as userspace
3853 * cannot claim and pin a new fb without at least acquring the
3854 * struct_mutex and so serialising with us.
3855 */
3856 for_each_intel_crtc(dev, crtc) {
3857 if (atomic_read(&crtc->unpin_work_count) == 0)
3858 continue;
3859
3860 if (crtc->unpin_work)
3861 intel_wait_for_vblank(dev, crtc->pipe);
3862
3863 return true;
3864 }
3865
3866 return false;
3867 }
3868
3869 static void page_flip_completed(struct intel_crtc *intel_crtc)
3870 {
3871 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3872 struct intel_unpin_work *work = intel_crtc->unpin_work;
3873
3874 /* ensure that the unpin work is consistent wrt ->pending. */
3875 smp_rmb();
3876 intel_crtc->unpin_work = NULL;
3877
3878 if (work->event)
3879 drm_send_vblank_event(intel_crtc->base.dev,
3880 intel_crtc->pipe,
3881 work->event);
3882
3883 drm_crtc_vblank_put(&intel_crtc->base);
3884
3885 wake_up_all(&dev_priv->pending_flip_queue);
3886 queue_work(dev_priv->wq, &work->work);
3887
3888 trace_i915_flip_complete(intel_crtc->plane,
3889 work->pending_flip_obj);
3890 }
3891
3892 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3893 {
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896
3897 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3898 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3899 !intel_crtc_has_pending_flip(crtc),
3900 60*HZ) == 0)) {
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902
3903 spin_lock_irq(&dev->event_lock);
3904 if (intel_crtc->unpin_work) {
3905 WARN_ONCE(1, "Removing stuck page flip\n");
3906 page_flip_completed(intel_crtc);
3907 }
3908 spin_unlock_irq(&dev->event_lock);
3909 }
3910
3911 if (crtc->primary->fb) {
3912 mutex_lock(&dev->struct_mutex);
3913 intel_finish_fb(crtc->primary->fb);
3914 mutex_unlock(&dev->struct_mutex);
3915 }
3916 }
3917
3918 /* Program iCLKIP clock to the desired frequency */
3919 static void lpt_program_iclkip(struct drm_crtc *crtc)
3920 {
3921 struct drm_device *dev = crtc->dev;
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3924 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3925 u32 temp;
3926
3927 mutex_lock(&dev_priv->sb_lock);
3928
3929 /* It is necessary to ungate the pixclk gate prior to programming
3930 * the divisors, and gate it back when it is done.
3931 */
3932 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3933
3934 /* Disable SSCCTL */
3935 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3936 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3937 SBI_SSCCTL_DISABLE,
3938 SBI_ICLK);
3939
3940 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3941 if (clock == 20000) {
3942 auxdiv = 1;
3943 divsel = 0x41;
3944 phaseinc = 0x20;
3945 } else {
3946 /* The iCLK virtual clock root frequency is in MHz,
3947 * but the adjusted_mode->crtc_clock in in KHz. To get the
3948 * divisors, it is necessary to divide one by another, so we
3949 * convert the virtual clock precision to KHz here for higher
3950 * precision.
3951 */
3952 u32 iclk_virtual_root_freq = 172800 * 1000;
3953 u32 iclk_pi_range = 64;
3954 u32 desired_divisor, msb_divisor_value, pi_value;
3955
3956 desired_divisor = (iclk_virtual_root_freq / clock);
3957 msb_divisor_value = desired_divisor / iclk_pi_range;
3958 pi_value = desired_divisor % iclk_pi_range;
3959
3960 auxdiv = 0;
3961 divsel = msb_divisor_value - 2;
3962 phaseinc = pi_value;
3963 }
3964
3965 /* This should not happen with any sane values */
3966 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3967 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3968 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3969 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3970
3971 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3972 clock,
3973 auxdiv,
3974 divsel,
3975 phasedir,
3976 phaseinc);
3977
3978 /* Program SSCDIVINTPHASE6 */
3979 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3980 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3981 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3982 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3983 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3984 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3985 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3986 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3987
3988 /* Program SSCAUXDIV */
3989 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3990 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3991 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3992 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3993
3994 /* Enable modulator and associated divider */
3995 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3996 temp &= ~SBI_SSCCTL_DISABLE;
3997 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3998
3999 /* Wait for initialization time */
4000 udelay(24);
4001
4002 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4003
4004 mutex_unlock(&dev_priv->sb_lock);
4005 }
4006
4007 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4008 enum pipe pch_transcoder)
4009 {
4010 struct drm_device *dev = crtc->base.dev;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4013
4014 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4015 I915_READ(HTOTAL(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4017 I915_READ(HBLANK(cpu_transcoder)));
4018 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4019 I915_READ(HSYNC(cpu_transcoder)));
4020
4021 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4022 I915_READ(VTOTAL(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4024 I915_READ(VBLANK(cpu_transcoder)));
4025 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4026 I915_READ(VSYNC(cpu_transcoder)));
4027 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4028 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4029 }
4030
4031 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4032 {
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 uint32_t temp;
4035
4036 temp = I915_READ(SOUTH_CHICKEN1);
4037 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4038 return;
4039
4040 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4041 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4042
4043 temp &= ~FDI_BC_BIFURCATION_SELECT;
4044 if (enable)
4045 temp |= FDI_BC_BIFURCATION_SELECT;
4046
4047 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4048 I915_WRITE(SOUTH_CHICKEN1, temp);
4049 POSTING_READ(SOUTH_CHICKEN1);
4050 }
4051
4052 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4053 {
4054 struct drm_device *dev = intel_crtc->base.dev;
4055
4056 switch (intel_crtc->pipe) {
4057 case PIPE_A:
4058 break;
4059 case PIPE_B:
4060 if (intel_crtc->config->fdi_lanes > 2)
4061 cpt_set_fdi_bc_bifurcation(dev, false);
4062 else
4063 cpt_set_fdi_bc_bifurcation(dev, true);
4064
4065 break;
4066 case PIPE_C:
4067 cpt_set_fdi_bc_bifurcation(dev, true);
4068
4069 break;
4070 default:
4071 BUG();
4072 }
4073 }
4074
4075 /*
4076 * Enable PCH resources required for PCH ports:
4077 * - PCH PLLs
4078 * - FDI training & RX/TX
4079 * - update transcoder timings
4080 * - DP transcoding bits
4081 * - transcoder
4082 */
4083 static void ironlake_pch_enable(struct drm_crtc *crtc)
4084 {
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088 int pipe = intel_crtc->pipe;
4089 u32 reg, temp;
4090
4091 assert_pch_transcoder_disabled(dev_priv, pipe);
4092
4093 if (IS_IVYBRIDGE(dev))
4094 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4095
4096 /* Write the TU size bits before fdi link training, so that error
4097 * detection works. */
4098 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4099 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4100
4101 /* For PCH output, training FDI link */
4102 dev_priv->display.fdi_link_train(crtc);
4103
4104 /* We need to program the right clock selection before writing the pixel
4105 * mutliplier into the DPLL. */
4106 if (HAS_PCH_CPT(dev)) {
4107 u32 sel;
4108
4109 temp = I915_READ(PCH_DPLL_SEL);
4110 temp |= TRANS_DPLL_ENABLE(pipe);
4111 sel = TRANS_DPLLB_SEL(pipe);
4112 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4113 temp |= sel;
4114 else
4115 temp &= ~sel;
4116 I915_WRITE(PCH_DPLL_SEL, temp);
4117 }
4118
4119 /* XXX: pch pll's can be enabled any time before we enable the PCH
4120 * transcoder, and we actually should do this to not upset any PCH
4121 * transcoder that already use the clock when we share it.
4122 *
4123 * Note that enable_shared_dpll tries to do the right thing, but
4124 * get_shared_dpll unconditionally resets the pll - we need that to have
4125 * the right LVDS enable sequence. */
4126 intel_enable_shared_dpll(intel_crtc);
4127
4128 /* set transcoder timing, panel must allow it */
4129 assert_panel_unlocked(dev_priv, pipe);
4130 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4131
4132 intel_fdi_normal_train(crtc);
4133
4134 /* For PCH DP, enable TRANS_DP_CTL */
4135 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4136 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4137 reg = TRANS_DP_CTL(pipe);
4138 temp = I915_READ(reg);
4139 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4140 TRANS_DP_SYNC_MASK |
4141 TRANS_DP_BPC_MASK);
4142 temp |= TRANS_DP_OUTPUT_ENABLE;
4143 temp |= bpc << 9; /* same format but at 11:9 */
4144
4145 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4146 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4147 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4148 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4149
4150 switch (intel_trans_dp_port_sel(crtc)) {
4151 case PCH_DP_B:
4152 temp |= TRANS_DP_PORT_SEL_B;
4153 break;
4154 case PCH_DP_C:
4155 temp |= TRANS_DP_PORT_SEL_C;
4156 break;
4157 case PCH_DP_D:
4158 temp |= TRANS_DP_PORT_SEL_D;
4159 break;
4160 default:
4161 BUG();
4162 }
4163
4164 I915_WRITE(reg, temp);
4165 }
4166
4167 ironlake_enable_pch_transcoder(dev_priv, pipe);
4168 }
4169
4170 static void lpt_pch_enable(struct drm_crtc *crtc)
4171 {
4172 struct drm_device *dev = crtc->dev;
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4176
4177 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4178
4179 lpt_program_iclkip(crtc);
4180
4181 /* Set transcoder timing. */
4182 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4183
4184 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4185 }
4186
4187 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4188 struct intel_crtc_state *crtc_state)
4189 {
4190 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4191 struct intel_shared_dpll *pll;
4192 struct intel_shared_dpll_config *shared_dpll;
4193 enum intel_dpll_id i;
4194
4195 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4196
4197 if (HAS_PCH_IBX(dev_priv->dev)) {
4198 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4199 i = (enum intel_dpll_id) crtc->pipe;
4200 pll = &dev_priv->shared_dplls[i];
4201
4202 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4203 crtc->base.base.id, pll->name);
4204
4205 WARN_ON(shared_dpll[i].crtc_mask);
4206
4207 goto found;
4208 }
4209
4210 if (IS_BROXTON(dev_priv->dev)) {
4211 /* PLL is attached to port in bxt */
4212 struct intel_encoder *encoder;
4213 struct intel_digital_port *intel_dig_port;
4214
4215 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4216 if (WARN_ON(!encoder))
4217 return NULL;
4218
4219 intel_dig_port = enc_to_dig_port(&encoder->base);
4220 /* 1:1 mapping between ports and PLLs */
4221 i = (enum intel_dpll_id)intel_dig_port->port;
4222 pll = &dev_priv->shared_dplls[i];
4223 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4224 crtc->base.base.id, pll->name);
4225 WARN_ON(shared_dpll[i].crtc_mask);
4226
4227 goto found;
4228 }
4229
4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
4232
4233 /* Only want to check enabled timings first */
4234 if (shared_dpll[i].crtc_mask == 0)
4235 continue;
4236
4237 if (memcmp(&crtc_state->dpll_hw_state,
4238 &shared_dpll[i].hw_state,
4239 sizeof(crtc_state->dpll_hw_state)) == 0) {
4240 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4241 crtc->base.base.id, pll->name,
4242 shared_dpll[i].crtc_mask,
4243 pll->active);
4244 goto found;
4245 }
4246 }
4247
4248 /* Ok no matching timings, maybe there's a free one? */
4249 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4250 pll = &dev_priv->shared_dplls[i];
4251 if (shared_dpll[i].crtc_mask == 0) {
4252 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4253 crtc->base.base.id, pll->name);
4254 goto found;
4255 }
4256 }
4257
4258 return NULL;
4259
4260 found:
4261 if (shared_dpll[i].crtc_mask == 0)
4262 shared_dpll[i].hw_state =
4263 crtc_state->dpll_hw_state;
4264
4265 crtc_state->shared_dpll = i;
4266 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4267 pipe_name(crtc->pipe));
4268
4269 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4270
4271 return pll;
4272 }
4273
4274 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4275 {
4276 struct drm_i915_private *dev_priv = to_i915(state->dev);
4277 struct intel_shared_dpll_config *shared_dpll;
4278 struct intel_shared_dpll *pll;
4279 enum intel_dpll_id i;
4280
4281 if (!to_intel_atomic_state(state)->dpll_set)
4282 return;
4283
4284 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4285 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4286 pll = &dev_priv->shared_dplls[i];
4287 pll->config = shared_dpll[i];
4288 }
4289 }
4290
4291 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4292 {
4293 struct drm_i915_private *dev_priv = dev->dev_private;
4294 int dslreg = PIPEDSL(pipe);
4295 u32 temp;
4296
4297 temp = I915_READ(dslreg);
4298 udelay(500);
4299 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4300 if (wait_for(I915_READ(dslreg) != temp, 5))
4301 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4302 }
4303 }
4304
4305 static int
4306 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4307 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4308 int src_w, int src_h, int dst_w, int dst_h)
4309 {
4310 struct intel_crtc_scaler_state *scaler_state =
4311 &crtc_state->scaler_state;
4312 struct intel_crtc *intel_crtc =
4313 to_intel_crtc(crtc_state->base.crtc);
4314 int need_scaling;
4315
4316 need_scaling = intel_rotation_90_or_270(rotation) ?
4317 (src_h != dst_w || src_w != dst_h):
4318 (src_w != dst_w || src_h != dst_h);
4319
4320 /*
4321 * if plane is being disabled or scaler is no more required or force detach
4322 * - free scaler binded to this plane/crtc
4323 * - in order to do this, update crtc->scaler_usage
4324 *
4325 * Here scaler state in crtc_state is set free so that
4326 * scaler can be assigned to other user. Actual register
4327 * update to free the scaler is done in plane/panel-fit programming.
4328 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4329 */
4330 if (force_detach || !need_scaling) {
4331 if (*scaler_id >= 0) {
4332 scaler_state->scaler_users &= ~(1 << scaler_user);
4333 scaler_state->scalers[*scaler_id].in_use = 0;
4334
4335 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4336 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4337 intel_crtc->pipe, scaler_user, *scaler_id,
4338 scaler_state->scaler_users);
4339 *scaler_id = -1;
4340 }
4341 return 0;
4342 }
4343
4344 /* range checks */
4345 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4346 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4347
4348 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4349 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4350 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4351 "size is out of scaler range\n",
4352 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4353 return -EINVAL;
4354 }
4355
4356 /* mark this plane as a scaler user in crtc_state */
4357 scaler_state->scaler_users |= (1 << scaler_user);
4358 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4359 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4360 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4361 scaler_state->scaler_users);
4362
4363 return 0;
4364 }
4365
4366 /**
4367 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4368 *
4369 * @state: crtc's scaler state
4370 *
4371 * Return
4372 * 0 - scaler_usage updated successfully
4373 * error - requested scaling cannot be supported or other error condition
4374 */
4375 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4376 {
4377 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4378 struct drm_display_mode *adjusted_mode =
4379 &state->base.adjusted_mode;
4380
4381 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4382 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4383
4384 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4385 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4386 state->pipe_src_w, state->pipe_src_h,
4387 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4388 }
4389
4390 /**
4391 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4392 *
4393 * @state: crtc's scaler state
4394 * @plane_state: atomic plane state to update
4395 *
4396 * Return
4397 * 0 - scaler_usage updated successfully
4398 * error - requested scaling cannot be supported or other error condition
4399 */
4400 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4401 struct intel_plane_state *plane_state)
4402 {
4403
4404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4405 struct intel_plane *intel_plane =
4406 to_intel_plane(plane_state->base.plane);
4407 struct drm_framebuffer *fb = plane_state->base.fb;
4408 int ret;
4409
4410 bool force_detach = !fb || !plane_state->visible;
4411
4412 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4413 intel_plane->base.base.id, intel_crtc->pipe,
4414 drm_plane_index(&intel_plane->base));
4415
4416 ret = skl_update_scaler(crtc_state, force_detach,
4417 drm_plane_index(&intel_plane->base),
4418 &plane_state->scaler_id,
4419 plane_state->base.rotation,
4420 drm_rect_width(&plane_state->src) >> 16,
4421 drm_rect_height(&plane_state->src) >> 16,
4422 drm_rect_width(&plane_state->dst),
4423 drm_rect_height(&plane_state->dst));
4424
4425 if (ret || plane_state->scaler_id < 0)
4426 return ret;
4427
4428 /* check colorkey */
4429 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4430 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4431 intel_plane->base.base.id);
4432 return -EINVAL;
4433 }
4434
4435 /* Check src format */
4436 switch (fb->pixel_format) {
4437 case DRM_FORMAT_RGB565:
4438 case DRM_FORMAT_XBGR8888:
4439 case DRM_FORMAT_XRGB8888:
4440 case DRM_FORMAT_ABGR8888:
4441 case DRM_FORMAT_ARGB8888:
4442 case DRM_FORMAT_XRGB2101010:
4443 case DRM_FORMAT_XBGR2101010:
4444 case DRM_FORMAT_YUYV:
4445 case DRM_FORMAT_YVYU:
4446 case DRM_FORMAT_UYVY:
4447 case DRM_FORMAT_VYUY:
4448 break;
4449 default:
4450 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4451 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4452 return -EINVAL;
4453 }
4454
4455 return 0;
4456 }
4457
4458 static void skylake_scaler_disable(struct intel_crtc *crtc)
4459 {
4460 int i;
4461
4462 for (i = 0; i < crtc->num_scalers; i++)
4463 skl_detach_scaler(crtc, i);
4464 }
4465
4466 static void skylake_pfit_enable(struct intel_crtc *crtc)
4467 {
4468 struct drm_device *dev = crtc->base.dev;
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470 int pipe = crtc->pipe;
4471 struct intel_crtc_scaler_state *scaler_state =
4472 &crtc->config->scaler_state;
4473
4474 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4475
4476 if (crtc->config->pch_pfit.enabled) {
4477 int id;
4478
4479 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4480 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4481 return;
4482 }
4483
4484 id = scaler_state->scaler_id;
4485 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4486 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4487 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4488 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4489
4490 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4491 }
4492 }
4493
4494 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4495 {
4496 struct drm_device *dev = crtc->base.dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 int pipe = crtc->pipe;
4499
4500 if (crtc->config->pch_pfit.enabled) {
4501 /* Force use of hard-coded filter coefficients
4502 * as some pre-programmed values are broken,
4503 * e.g. x201.
4504 */
4505 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4506 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4507 PF_PIPE_SEL_IVB(pipe));
4508 else
4509 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4510 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4511 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4512 }
4513 }
4514
4515 void hsw_enable_ips(struct intel_crtc *crtc)
4516 {
4517 struct drm_device *dev = crtc->base.dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519
4520 if (!crtc->config->ips_enabled)
4521 return;
4522
4523 /* We can only enable IPS after we enable a plane and wait for a vblank */
4524 intel_wait_for_vblank(dev, crtc->pipe);
4525
4526 assert_plane_enabled(dev_priv, crtc->plane);
4527 if (IS_BROADWELL(dev)) {
4528 mutex_lock(&dev_priv->rps.hw_lock);
4529 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4530 mutex_unlock(&dev_priv->rps.hw_lock);
4531 /* Quoting Art Runyan: "its not safe to expect any particular
4532 * value in IPS_CTL bit 31 after enabling IPS through the
4533 * mailbox." Moreover, the mailbox may return a bogus state,
4534 * so we need to just enable it and continue on.
4535 */
4536 } else {
4537 I915_WRITE(IPS_CTL, IPS_ENABLE);
4538 /* The bit only becomes 1 in the next vblank, so this wait here
4539 * is essentially intel_wait_for_vblank. If we don't have this
4540 * and don't wait for vblanks until the end of crtc_enable, then
4541 * the HW state readout code will complain that the expected
4542 * IPS_CTL value is not the one we read. */
4543 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4544 DRM_ERROR("Timed out waiting for IPS enable\n");
4545 }
4546 }
4547
4548 void hsw_disable_ips(struct intel_crtc *crtc)
4549 {
4550 struct drm_device *dev = crtc->base.dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552
4553 if (!crtc->config->ips_enabled)
4554 return;
4555
4556 assert_plane_enabled(dev_priv, crtc->plane);
4557 if (IS_BROADWELL(dev)) {
4558 mutex_lock(&dev_priv->rps.hw_lock);
4559 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4560 mutex_unlock(&dev_priv->rps.hw_lock);
4561 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4562 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4563 DRM_ERROR("Timed out waiting for IPS disable\n");
4564 } else {
4565 I915_WRITE(IPS_CTL, 0);
4566 POSTING_READ(IPS_CTL);
4567 }
4568
4569 /* We need to wait for a vblank before we can disable the plane. */
4570 intel_wait_for_vblank(dev, crtc->pipe);
4571 }
4572
4573 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4574 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4575 {
4576 struct drm_device *dev = crtc->dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579 enum pipe pipe = intel_crtc->pipe;
4580 int palreg = PALETTE(pipe);
4581 int i;
4582 bool reenable_ips = false;
4583
4584 /* The clocks have to be on to load the palette. */
4585 if (!crtc->state->active)
4586 return;
4587
4588 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4589 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4590 assert_dsi_pll_enabled(dev_priv);
4591 else
4592 assert_pll_enabled(dev_priv, pipe);
4593 }
4594
4595 /* use legacy palette for Ironlake */
4596 if (!HAS_GMCH_DISPLAY(dev))
4597 palreg = LGC_PALETTE(pipe);
4598
4599 /* Workaround : Do not read or write the pipe palette/gamma data while
4600 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4601 */
4602 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4603 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4604 GAMMA_MODE_MODE_SPLIT)) {
4605 hsw_disable_ips(intel_crtc);
4606 reenable_ips = true;
4607 }
4608
4609 for (i = 0; i < 256; i++) {
4610 I915_WRITE(palreg + 4 * i,
4611 (intel_crtc->lut_r[i] << 16) |
4612 (intel_crtc->lut_g[i] << 8) |
4613 intel_crtc->lut_b[i]);
4614 }
4615
4616 if (reenable_ips)
4617 hsw_enable_ips(intel_crtc);
4618 }
4619
4620 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4621 {
4622 if (intel_crtc->overlay) {
4623 struct drm_device *dev = intel_crtc->base.dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625
4626 mutex_lock(&dev->struct_mutex);
4627 dev_priv->mm.interruptible = false;
4628 (void) intel_overlay_switch_off(intel_crtc->overlay);
4629 dev_priv->mm.interruptible = true;
4630 mutex_unlock(&dev->struct_mutex);
4631 }
4632
4633 /* Let userspace switch the overlay on again. In most cases userspace
4634 * has to recompute where to put it anyway.
4635 */
4636 }
4637
4638 /**
4639 * intel_post_enable_primary - Perform operations after enabling primary plane
4640 * @crtc: the CRTC whose primary plane was just enabled
4641 *
4642 * Performs potentially sleeping operations that must be done after the primary
4643 * plane is enabled, such as updating FBC and IPS. Note that this may be
4644 * called due to an explicit primary plane update, or due to an implicit
4645 * re-enable that is caused when a sprite plane is updated to no longer
4646 * completely hide the primary plane.
4647 */
4648 static void
4649 intel_post_enable_primary(struct drm_crtc *crtc)
4650 {
4651 struct drm_device *dev = crtc->dev;
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4654 int pipe = intel_crtc->pipe;
4655
4656 /*
4657 * BDW signals flip done immediately if the plane
4658 * is disabled, even if the plane enable is already
4659 * armed to occur at the next vblank :(
4660 */
4661 if (IS_BROADWELL(dev))
4662 intel_wait_for_vblank(dev, pipe);
4663
4664 /*
4665 * FIXME IPS should be fine as long as one plane is
4666 * enabled, but in practice it seems to have problems
4667 * when going from primary only to sprite only and vice
4668 * versa.
4669 */
4670 hsw_enable_ips(intel_crtc);
4671
4672 /*
4673 * Gen2 reports pipe underruns whenever all planes are disabled.
4674 * So don't enable underrun reporting before at least some planes
4675 * are enabled.
4676 * FIXME: Need to fix the logic to work when we turn off all planes
4677 * but leave the pipe running.
4678 */
4679 if (IS_GEN2(dev))
4680 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4681
4682 /* Underruns don't raise interrupts, so check manually. */
4683 if (HAS_GMCH_DISPLAY(dev))
4684 i9xx_check_fifo_underruns(dev_priv);
4685 }
4686
4687 /**
4688 * intel_pre_disable_primary - Perform operations before disabling primary plane
4689 * @crtc: the CRTC whose primary plane is to be disabled
4690 *
4691 * Performs potentially sleeping operations that must be done before the
4692 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4693 * be called due to an explicit primary plane update, or due to an implicit
4694 * disable that is caused when a sprite plane completely hides the primary
4695 * plane.
4696 */
4697 static void
4698 intel_pre_disable_primary(struct drm_crtc *crtc)
4699 {
4700 struct drm_device *dev = crtc->dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int pipe = intel_crtc->pipe;
4704
4705 /*
4706 * Gen2 reports pipe underruns whenever all planes are disabled.
4707 * So diasble underrun reporting before all the planes get disabled.
4708 * FIXME: Need to fix the logic to work when we turn off all planes
4709 * but leave the pipe running.
4710 */
4711 if (IS_GEN2(dev))
4712 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4713
4714 /*
4715 * Vblank time updates from the shadow to live plane control register
4716 * are blocked if the memory self-refresh mode is active at that
4717 * moment. So to make sure the plane gets truly disabled, disable
4718 * first the self-refresh mode. The self-refresh enable bit in turn
4719 * will be checked/applied by the HW only at the next frame start
4720 * event which is after the vblank start event, so we need to have a
4721 * wait-for-vblank between disabling the plane and the pipe.
4722 */
4723 if (HAS_GMCH_DISPLAY(dev)) {
4724 intel_set_memory_cxsr(dev_priv, false);
4725 dev_priv->wm.vlv.cxsr = false;
4726 intel_wait_for_vblank(dev, pipe);
4727 }
4728
4729 /*
4730 * FIXME IPS should be fine as long as one plane is
4731 * enabled, but in practice it seems to have problems
4732 * when going from primary only to sprite only and vice
4733 * versa.
4734 */
4735 hsw_disable_ips(intel_crtc);
4736 }
4737
4738 static void intel_post_plane_update(struct intel_crtc *crtc)
4739 {
4740 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4741 struct drm_device *dev = crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 struct drm_plane *plane;
4744
4745 if (atomic->wait_vblank)
4746 intel_wait_for_vblank(dev, crtc->pipe);
4747
4748 intel_frontbuffer_flip(dev, atomic->fb_bits);
4749
4750 if (atomic->disable_cxsr)
4751 crtc->wm.cxsr_allowed = true;
4752
4753 if (crtc->atomic.update_wm_post)
4754 intel_update_watermarks(&crtc->base);
4755
4756 if (atomic->update_fbc)
4757 intel_fbc_update(dev_priv);
4758
4759 if (atomic->post_enable_primary)
4760 intel_post_enable_primary(&crtc->base);
4761
4762 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4763 intel_update_sprite_watermarks(plane, &crtc->base,
4764 0, 0, 0, false, false);
4765
4766 memset(atomic, 0, sizeof(*atomic));
4767 }
4768
4769 static void intel_pre_plane_update(struct intel_crtc *crtc)
4770 {
4771 struct drm_device *dev = crtc->base.dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4774 struct drm_plane *p;
4775
4776 /* Track fb's for any planes being disabled */
4777 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4778 struct intel_plane *plane = to_intel_plane(p);
4779
4780 mutex_lock(&dev->struct_mutex);
4781 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4782 plane->frontbuffer_bit);
4783 mutex_unlock(&dev->struct_mutex);
4784 }
4785
4786 if (atomic->wait_for_flips)
4787 intel_crtc_wait_for_pending_flips(&crtc->base);
4788
4789 if (atomic->disable_fbc)
4790 intel_fbc_disable_crtc(crtc);
4791
4792 if (crtc->atomic.disable_ips)
4793 hsw_disable_ips(crtc);
4794
4795 if (atomic->pre_disable_primary)
4796 intel_pre_disable_primary(&crtc->base);
4797
4798 if (atomic->disable_cxsr) {
4799 crtc->wm.cxsr_allowed = false;
4800 intel_set_memory_cxsr(dev_priv, false);
4801 }
4802 }
4803
4804 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4805 {
4806 struct drm_device *dev = crtc->dev;
4807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4808 struct drm_plane *p;
4809 int pipe = intel_crtc->pipe;
4810
4811 intel_crtc_dpms_overlay_disable(intel_crtc);
4812
4813 drm_for_each_plane_mask(p, dev, plane_mask)
4814 to_intel_plane(p)->disable_plane(p, crtc);
4815
4816 /*
4817 * FIXME: Once we grow proper nuclear flip support out of this we need
4818 * to compute the mask of flip planes precisely. For the time being
4819 * consider this a flip to a NULL plane.
4820 */
4821 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4822 }
4823
4824 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4825 {
4826 struct drm_device *dev = crtc->dev;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4829 struct intel_encoder *encoder;
4830 int pipe = intel_crtc->pipe;
4831
4832 if (WARN_ON(intel_crtc->active))
4833 return;
4834
4835 if (intel_crtc->config->has_pch_encoder)
4836 intel_prepare_shared_dpll(intel_crtc);
4837
4838 if (intel_crtc->config->has_dp_encoder)
4839 intel_dp_set_m_n(intel_crtc, M1_N1);
4840
4841 intel_set_pipe_timings(intel_crtc);
4842
4843 if (intel_crtc->config->has_pch_encoder) {
4844 intel_cpu_transcoder_set_m_n(intel_crtc,
4845 &intel_crtc->config->fdi_m_n, NULL);
4846 }
4847
4848 ironlake_set_pipeconf(crtc);
4849
4850 intel_crtc->active = true;
4851
4852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4853 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4854
4855 for_each_encoder_on_crtc(dev, crtc, encoder)
4856 if (encoder->pre_enable)
4857 encoder->pre_enable(encoder);
4858
4859 if (intel_crtc->config->has_pch_encoder) {
4860 /* Note: FDI PLL enabling _must_ be done before we enable the
4861 * cpu pipes, hence this is separate from all the other fdi/pch
4862 * enabling. */
4863 ironlake_fdi_pll_enable(intel_crtc);
4864 } else {
4865 assert_fdi_tx_disabled(dev_priv, pipe);
4866 assert_fdi_rx_disabled(dev_priv, pipe);
4867 }
4868
4869 ironlake_pfit_enable(intel_crtc);
4870
4871 /*
4872 * On ILK+ LUT must be loaded before the pipe is running but with
4873 * clocks enabled
4874 */
4875 intel_crtc_load_lut(crtc);
4876
4877 intel_update_watermarks(crtc);
4878 intel_enable_pipe(intel_crtc);
4879
4880 if (intel_crtc->config->has_pch_encoder)
4881 ironlake_pch_enable(crtc);
4882
4883 assert_vblank_disabled(crtc);
4884 drm_crtc_vblank_on(crtc);
4885
4886 for_each_encoder_on_crtc(dev, crtc, encoder)
4887 encoder->enable(encoder);
4888
4889 if (HAS_PCH_CPT(dev))
4890 cpt_verify_modeset(dev, intel_crtc->pipe);
4891 }
4892
4893 /* IPS only exists on ULT machines and is tied to pipe A. */
4894 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4895 {
4896 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4897 }
4898
4899 static void haswell_crtc_enable(struct drm_crtc *crtc)
4900 {
4901 struct drm_device *dev = crtc->dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4904 struct intel_encoder *encoder;
4905 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4906 struct intel_crtc_state *pipe_config =
4907 to_intel_crtc_state(crtc->state);
4908
4909 if (WARN_ON(intel_crtc->active))
4910 return;
4911
4912 if (intel_crtc_to_shared_dpll(intel_crtc))
4913 intel_enable_shared_dpll(intel_crtc);
4914
4915 if (intel_crtc->config->has_dp_encoder)
4916 intel_dp_set_m_n(intel_crtc, M1_N1);
4917
4918 intel_set_pipe_timings(intel_crtc);
4919
4920 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4921 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4922 intel_crtc->config->pixel_multiplier - 1);
4923 }
4924
4925 if (intel_crtc->config->has_pch_encoder) {
4926 intel_cpu_transcoder_set_m_n(intel_crtc,
4927 &intel_crtc->config->fdi_m_n, NULL);
4928 }
4929
4930 haswell_set_pipeconf(crtc);
4931
4932 intel_set_pipe_csc(crtc);
4933
4934 intel_crtc->active = true;
4935
4936 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4937 for_each_encoder_on_crtc(dev, crtc, encoder)
4938 if (encoder->pre_enable)
4939 encoder->pre_enable(encoder);
4940
4941 if (intel_crtc->config->has_pch_encoder) {
4942 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4943 true);
4944 dev_priv->display.fdi_link_train(crtc);
4945 }
4946
4947 intel_ddi_enable_pipe_clock(intel_crtc);
4948
4949 if (INTEL_INFO(dev)->gen == 9)
4950 skylake_pfit_enable(intel_crtc);
4951 else if (INTEL_INFO(dev)->gen < 9)
4952 ironlake_pfit_enable(intel_crtc);
4953 else
4954 MISSING_CASE(INTEL_INFO(dev)->gen);
4955
4956 /*
4957 * On ILK+ LUT must be loaded before the pipe is running but with
4958 * clocks enabled
4959 */
4960 intel_crtc_load_lut(crtc);
4961
4962 intel_ddi_set_pipe_settings(crtc);
4963 intel_ddi_enable_transcoder_func(crtc);
4964
4965 intel_update_watermarks(crtc);
4966 intel_enable_pipe(intel_crtc);
4967
4968 if (intel_crtc->config->has_pch_encoder)
4969 lpt_pch_enable(crtc);
4970
4971 if (intel_crtc->config->dp_encoder_is_mst)
4972 intel_ddi_set_vc_payload_alloc(crtc, true);
4973
4974 assert_vblank_disabled(crtc);
4975 drm_crtc_vblank_on(crtc);
4976
4977 for_each_encoder_on_crtc(dev, crtc, encoder) {
4978 encoder->enable(encoder);
4979 intel_opregion_notify_encoder(encoder, true);
4980 }
4981
4982 /* If we change the relative order between pipe/planes enabling, we need
4983 * to change the workaround. */
4984 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4985 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4986 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4987 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988 }
4989 }
4990
4991 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4992 {
4993 struct drm_device *dev = crtc->base.dev;
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995 int pipe = crtc->pipe;
4996
4997 /* To avoid upsetting the power well on haswell only disable the pfit if
4998 * it's in use. The hw state code will make sure we get this right. */
4999 if (crtc->config->pch_pfit.enabled) {
5000 I915_WRITE(PF_CTL(pipe), 0);
5001 I915_WRITE(PF_WIN_POS(pipe), 0);
5002 I915_WRITE(PF_WIN_SZ(pipe), 0);
5003 }
5004 }
5005
5006 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5007 {
5008 struct drm_device *dev = crtc->dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011 struct intel_encoder *encoder;
5012 int pipe = intel_crtc->pipe;
5013 u32 reg, temp;
5014
5015 for_each_encoder_on_crtc(dev, crtc, encoder)
5016 encoder->disable(encoder);
5017
5018 drm_crtc_vblank_off(crtc);
5019 assert_vblank_disabled(crtc);
5020
5021 if (intel_crtc->config->has_pch_encoder)
5022 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5023
5024 intel_disable_pipe(intel_crtc);
5025
5026 ironlake_pfit_disable(intel_crtc);
5027
5028 if (intel_crtc->config->has_pch_encoder)
5029 ironlake_fdi_disable(crtc);
5030
5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 if (encoder->post_disable)
5033 encoder->post_disable(encoder);
5034
5035 if (intel_crtc->config->has_pch_encoder) {
5036 ironlake_disable_pch_transcoder(dev_priv, pipe);
5037
5038 if (HAS_PCH_CPT(dev)) {
5039 /* disable TRANS_DP_CTL */
5040 reg = TRANS_DP_CTL(pipe);
5041 temp = I915_READ(reg);
5042 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5043 TRANS_DP_PORT_SEL_MASK);
5044 temp |= TRANS_DP_PORT_SEL_NONE;
5045 I915_WRITE(reg, temp);
5046
5047 /* disable DPLL_SEL */
5048 temp = I915_READ(PCH_DPLL_SEL);
5049 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5050 I915_WRITE(PCH_DPLL_SEL, temp);
5051 }
5052
5053 ironlake_fdi_pll_disable(intel_crtc);
5054 }
5055
5056 intel_crtc->active = false;
5057 intel_update_watermarks(crtc);
5058 }
5059
5060 static void haswell_crtc_disable(struct drm_crtc *crtc)
5061 {
5062 struct drm_device *dev = crtc->dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 struct intel_encoder *encoder;
5066 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5067
5068 for_each_encoder_on_crtc(dev, crtc, encoder) {
5069 intel_opregion_notify_encoder(encoder, false);
5070 encoder->disable(encoder);
5071 }
5072
5073 drm_crtc_vblank_off(crtc);
5074 assert_vblank_disabled(crtc);
5075
5076 if (intel_crtc->config->has_pch_encoder)
5077 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5078 false);
5079 intel_disable_pipe(intel_crtc);
5080
5081 if (intel_crtc->config->dp_encoder_is_mst)
5082 intel_ddi_set_vc_payload_alloc(crtc, false);
5083
5084 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5085
5086 if (INTEL_INFO(dev)->gen == 9)
5087 skylake_scaler_disable(intel_crtc);
5088 else if (INTEL_INFO(dev)->gen < 9)
5089 ironlake_pfit_disable(intel_crtc);
5090 else
5091 MISSING_CASE(INTEL_INFO(dev)->gen);
5092
5093 intel_ddi_disable_pipe_clock(intel_crtc);
5094
5095 if (intel_crtc->config->has_pch_encoder) {
5096 lpt_disable_pch_transcoder(dev_priv);
5097 intel_ddi_fdi_disable(crtc);
5098 }
5099
5100 for_each_encoder_on_crtc(dev, crtc, encoder)
5101 if (encoder->post_disable)
5102 encoder->post_disable(encoder);
5103
5104 intel_crtc->active = false;
5105 intel_update_watermarks(crtc);
5106 }
5107
5108 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5109 {
5110 struct drm_device *dev = crtc->base.dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 struct intel_crtc_state *pipe_config = crtc->config;
5113
5114 if (!pipe_config->gmch_pfit.control)
5115 return;
5116
5117 /*
5118 * The panel fitter should only be adjusted whilst the pipe is disabled,
5119 * according to register description and PRM.
5120 */
5121 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5122 assert_pipe_disabled(dev_priv, crtc->pipe);
5123
5124 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5125 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5126
5127 /* Border color in case we don't scale up to the full screen. Black by
5128 * default, change to something else for debugging. */
5129 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5130 }
5131
5132 static enum intel_display_power_domain port_to_power_domain(enum port port)
5133 {
5134 switch (port) {
5135 case PORT_A:
5136 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5137 case PORT_B:
5138 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5139 case PORT_C:
5140 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5141 case PORT_D:
5142 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5143 default:
5144 WARN_ON_ONCE(1);
5145 return POWER_DOMAIN_PORT_OTHER;
5146 }
5147 }
5148
5149 #define for_each_power_domain(domain, mask) \
5150 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5151 if ((1 << (domain)) & (mask))
5152
5153 enum intel_display_power_domain
5154 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5155 {
5156 struct drm_device *dev = intel_encoder->base.dev;
5157 struct intel_digital_port *intel_dig_port;
5158
5159 switch (intel_encoder->type) {
5160 case INTEL_OUTPUT_UNKNOWN:
5161 /* Only DDI platforms should ever use this output type */
5162 WARN_ON_ONCE(!HAS_DDI(dev));
5163 case INTEL_OUTPUT_DISPLAYPORT:
5164 case INTEL_OUTPUT_HDMI:
5165 case INTEL_OUTPUT_EDP:
5166 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5167 return port_to_power_domain(intel_dig_port->port);
5168 case INTEL_OUTPUT_DP_MST:
5169 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5170 return port_to_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_ANALOG:
5172 return POWER_DOMAIN_PORT_CRT;
5173 case INTEL_OUTPUT_DSI:
5174 return POWER_DOMAIN_PORT_DSI;
5175 default:
5176 return POWER_DOMAIN_PORT_OTHER;
5177 }
5178 }
5179
5180 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5181 {
5182 struct drm_device *dev = crtc->dev;
5183 struct intel_encoder *intel_encoder;
5184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185 enum pipe pipe = intel_crtc->pipe;
5186 unsigned long mask;
5187 enum transcoder transcoder;
5188
5189 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5190
5191 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5192 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5193 if (intel_crtc->config->pch_pfit.enabled ||
5194 intel_crtc->config->pch_pfit.force_thru)
5195 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5196
5197 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5198 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5199
5200 return mask;
5201 }
5202
5203 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5204 {
5205 struct drm_device *dev = state->dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5208 struct intel_crtc *crtc;
5209
5210 /*
5211 * First get all needed power domains, then put all unneeded, to avoid
5212 * any unnecessary toggling of the power wells.
5213 */
5214 for_each_intel_crtc(dev, crtc) {
5215 enum intel_display_power_domain domain;
5216
5217 if (!crtc->base.state->enable)
5218 continue;
5219
5220 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5221
5222 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5223 intel_display_power_get(dev_priv, domain);
5224 }
5225
5226 if (dev_priv->display.modeset_commit_cdclk) {
5227 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5228
5229 if (cdclk != dev_priv->cdclk_freq &&
5230 !WARN_ON(!state->allow_modeset))
5231 dev_priv->display.modeset_commit_cdclk(state);
5232 }
5233
5234 for_each_intel_crtc(dev, crtc) {
5235 enum intel_display_power_domain domain;
5236
5237 for_each_power_domain(domain, crtc->enabled_power_domains)
5238 intel_display_power_put(dev_priv, domain);
5239
5240 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5241 }
5242
5243 intel_display_set_init_power(dev_priv, false);
5244 }
5245
5246 static void intel_update_max_cdclk(struct drm_device *dev)
5247 {
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249
5250 if (IS_SKYLAKE(dev)) {
5251 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5252
5253 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5254 dev_priv->max_cdclk_freq = 675000;
5255 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5256 dev_priv->max_cdclk_freq = 540000;
5257 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5258 dev_priv->max_cdclk_freq = 450000;
5259 else
5260 dev_priv->max_cdclk_freq = 337500;
5261 } else if (IS_BROADWELL(dev)) {
5262 /*
5263 * FIXME with extra cooling we can allow
5264 * 540 MHz for ULX and 675 Mhz for ULT.
5265 * How can we know if extra cooling is
5266 * available? PCI ID, VTB, something else?
5267 */
5268 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5269 dev_priv->max_cdclk_freq = 450000;
5270 else if (IS_BDW_ULX(dev))
5271 dev_priv->max_cdclk_freq = 450000;
5272 else if (IS_BDW_ULT(dev))
5273 dev_priv->max_cdclk_freq = 540000;
5274 else
5275 dev_priv->max_cdclk_freq = 675000;
5276 } else if (IS_CHERRYVIEW(dev)) {
5277 dev_priv->max_cdclk_freq = 320000;
5278 } else if (IS_VALLEYVIEW(dev)) {
5279 dev_priv->max_cdclk_freq = 400000;
5280 } else {
5281 /* otherwise assume cdclk is fixed */
5282 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5283 }
5284
5285 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5286 dev_priv->max_cdclk_freq);
5287 }
5288
5289 static void intel_update_cdclk(struct drm_device *dev)
5290 {
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292
5293 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5294 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5295 dev_priv->cdclk_freq);
5296
5297 /*
5298 * Program the gmbus_freq based on the cdclk frequency.
5299 * BSpec erroneously claims we should aim for 4MHz, but
5300 * in fact 1MHz is the correct frequency.
5301 */
5302 if (IS_VALLEYVIEW(dev)) {
5303 /*
5304 * Program the gmbus_freq based on the cdclk frequency.
5305 * BSpec erroneously claims we should aim for 4MHz, but
5306 * in fact 1MHz is the correct frequency.
5307 */
5308 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5309 }
5310
5311 if (dev_priv->max_cdclk_freq == 0)
5312 intel_update_max_cdclk(dev);
5313 }
5314
5315 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5316 {
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318 uint32_t divider;
5319 uint32_t ratio;
5320 uint32_t current_freq;
5321 int ret;
5322
5323 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5324 switch (frequency) {
5325 case 144000:
5326 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5327 ratio = BXT_DE_PLL_RATIO(60);
5328 break;
5329 case 288000:
5330 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5331 ratio = BXT_DE_PLL_RATIO(60);
5332 break;
5333 case 384000:
5334 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5335 ratio = BXT_DE_PLL_RATIO(60);
5336 break;
5337 case 576000:
5338 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5339 ratio = BXT_DE_PLL_RATIO(60);
5340 break;
5341 case 624000:
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5343 ratio = BXT_DE_PLL_RATIO(65);
5344 break;
5345 case 19200:
5346 /*
5347 * Bypass frequency with DE PLL disabled. Init ratio, divider
5348 * to suppress GCC warning.
5349 */
5350 ratio = 0;
5351 divider = 0;
5352 break;
5353 default:
5354 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5355
5356 return;
5357 }
5358
5359 mutex_lock(&dev_priv->rps.hw_lock);
5360 /* Inform power controller of upcoming frequency change */
5361 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5362 0x80000000);
5363 mutex_unlock(&dev_priv->rps.hw_lock);
5364
5365 if (ret) {
5366 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5367 ret, frequency);
5368 return;
5369 }
5370
5371 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5372 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5373 current_freq = current_freq * 500 + 1000;
5374
5375 /*
5376 * DE PLL has to be disabled when
5377 * - setting to 19.2MHz (bypass, PLL isn't used)
5378 * - before setting to 624MHz (PLL needs toggling)
5379 * - before setting to any frequency from 624MHz (PLL needs toggling)
5380 */
5381 if (frequency == 19200 || frequency == 624000 ||
5382 current_freq == 624000) {
5383 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5384 /* Timeout 200us */
5385 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5386 1))
5387 DRM_ERROR("timout waiting for DE PLL unlock\n");
5388 }
5389
5390 if (frequency != 19200) {
5391 uint32_t val;
5392
5393 val = I915_READ(BXT_DE_PLL_CTL);
5394 val &= ~BXT_DE_PLL_RATIO_MASK;
5395 val |= ratio;
5396 I915_WRITE(BXT_DE_PLL_CTL, val);
5397
5398 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5399 /* Timeout 200us */
5400 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5401 DRM_ERROR("timeout waiting for DE PLL lock\n");
5402
5403 val = I915_READ(CDCLK_CTL);
5404 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5405 val |= divider;
5406 /*
5407 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5408 * enable otherwise.
5409 */
5410 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5411 if (frequency >= 500000)
5412 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5413
5414 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5415 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5416 val |= (frequency - 1000) / 500;
5417 I915_WRITE(CDCLK_CTL, val);
5418 }
5419
5420 mutex_lock(&dev_priv->rps.hw_lock);
5421 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5422 DIV_ROUND_UP(frequency, 25000));
5423 mutex_unlock(&dev_priv->rps.hw_lock);
5424
5425 if (ret) {
5426 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5427 ret, frequency);
5428 return;
5429 }
5430
5431 intel_update_cdclk(dev);
5432 }
5433
5434 void broxton_init_cdclk(struct drm_device *dev)
5435 {
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 uint32_t val;
5438
5439 /*
5440 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5441 * or else the reset will hang because there is no PCH to respond.
5442 * Move the handshake programming to initialization sequence.
5443 * Previously was left up to BIOS.
5444 */
5445 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5446 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5447 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5448
5449 /* Enable PG1 for cdclk */
5450 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5451
5452 /* check if cd clock is enabled */
5453 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5454 DRM_DEBUG_KMS("Display already initialized\n");
5455 return;
5456 }
5457
5458 /*
5459 * FIXME:
5460 * - The initial CDCLK needs to be read from VBT.
5461 * Need to make this change after VBT has changes for BXT.
5462 * - check if setting the max (or any) cdclk freq is really necessary
5463 * here, it belongs to modeset time
5464 */
5465 broxton_set_cdclk(dev, 624000);
5466
5467 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5468 POSTING_READ(DBUF_CTL);
5469
5470 udelay(10);
5471
5472 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5473 DRM_ERROR("DBuf power enable timeout!\n");
5474 }
5475
5476 void broxton_uninit_cdclk(struct drm_device *dev)
5477 {
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479
5480 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5481 POSTING_READ(DBUF_CTL);
5482
5483 udelay(10);
5484
5485 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5486 DRM_ERROR("DBuf power disable timeout!\n");
5487
5488 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5489 broxton_set_cdclk(dev, 19200);
5490
5491 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5492 }
5493
5494 static const struct skl_cdclk_entry {
5495 unsigned int freq;
5496 unsigned int vco;
5497 } skl_cdclk_frequencies[] = {
5498 { .freq = 308570, .vco = 8640 },
5499 { .freq = 337500, .vco = 8100 },
5500 { .freq = 432000, .vco = 8640 },
5501 { .freq = 450000, .vco = 8100 },
5502 { .freq = 540000, .vco = 8100 },
5503 { .freq = 617140, .vco = 8640 },
5504 { .freq = 675000, .vco = 8100 },
5505 };
5506
5507 static unsigned int skl_cdclk_decimal(unsigned int freq)
5508 {
5509 return (freq - 1000) / 500;
5510 }
5511
5512 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5513 {
5514 unsigned int i;
5515
5516 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5517 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5518
5519 if (e->freq == freq)
5520 return e->vco;
5521 }
5522
5523 return 8100;
5524 }
5525
5526 static void
5527 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5528 {
5529 unsigned int min_freq;
5530 u32 val;
5531
5532 /* select the minimum CDCLK before enabling DPLL 0 */
5533 val = I915_READ(CDCLK_CTL);
5534 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5535 val |= CDCLK_FREQ_337_308;
5536
5537 if (required_vco == 8640)
5538 min_freq = 308570;
5539 else
5540 min_freq = 337500;
5541
5542 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5543
5544 I915_WRITE(CDCLK_CTL, val);
5545 POSTING_READ(CDCLK_CTL);
5546
5547 /*
5548 * We always enable DPLL0 with the lowest link rate possible, but still
5549 * taking into account the VCO required to operate the eDP panel at the
5550 * desired frequency. The usual DP link rates operate with a VCO of
5551 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5552 * The modeset code is responsible for the selection of the exact link
5553 * rate later on, with the constraint of choosing a frequency that
5554 * works with required_vco.
5555 */
5556 val = I915_READ(DPLL_CTRL1);
5557
5558 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5559 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5560 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5561 if (required_vco == 8640)
5562 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5563 SKL_DPLL0);
5564 else
5565 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5566 SKL_DPLL0);
5567
5568 I915_WRITE(DPLL_CTRL1, val);
5569 POSTING_READ(DPLL_CTRL1);
5570
5571 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5572
5573 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5574 DRM_ERROR("DPLL0 not locked\n");
5575 }
5576
5577 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5578 {
5579 int ret;
5580 u32 val;
5581
5582 /* inform PCU we want to change CDCLK */
5583 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5584 mutex_lock(&dev_priv->rps.hw_lock);
5585 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5586 mutex_unlock(&dev_priv->rps.hw_lock);
5587
5588 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5589 }
5590
5591 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5592 {
5593 unsigned int i;
5594
5595 for (i = 0; i < 15; i++) {
5596 if (skl_cdclk_pcu_ready(dev_priv))
5597 return true;
5598 udelay(10);
5599 }
5600
5601 return false;
5602 }
5603
5604 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5605 {
5606 struct drm_device *dev = dev_priv->dev;
5607 u32 freq_select, pcu_ack;
5608
5609 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5610
5611 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5612 DRM_ERROR("failed to inform PCU about cdclk change\n");
5613 return;
5614 }
5615
5616 /* set CDCLK_CTL */
5617 switch(freq) {
5618 case 450000:
5619 case 432000:
5620 freq_select = CDCLK_FREQ_450_432;
5621 pcu_ack = 1;
5622 break;
5623 case 540000:
5624 freq_select = CDCLK_FREQ_540;
5625 pcu_ack = 2;
5626 break;
5627 case 308570:
5628 case 337500:
5629 default:
5630 freq_select = CDCLK_FREQ_337_308;
5631 pcu_ack = 0;
5632 break;
5633 case 617140:
5634 case 675000:
5635 freq_select = CDCLK_FREQ_675_617;
5636 pcu_ack = 3;
5637 break;
5638 }
5639
5640 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5641 POSTING_READ(CDCLK_CTL);
5642
5643 /* inform PCU of the change */
5644 mutex_lock(&dev_priv->rps.hw_lock);
5645 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5646 mutex_unlock(&dev_priv->rps.hw_lock);
5647
5648 intel_update_cdclk(dev);
5649 }
5650
5651 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5652 {
5653 /* disable DBUF power */
5654 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5655 POSTING_READ(DBUF_CTL);
5656
5657 udelay(10);
5658
5659 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5660 DRM_ERROR("DBuf power disable timeout\n");
5661
5662 /* disable DPLL0 */
5663 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5664 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5665 DRM_ERROR("Couldn't disable DPLL0\n");
5666
5667 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5668 }
5669
5670 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5671 {
5672 u32 val;
5673 unsigned int required_vco;
5674
5675 /* enable PCH reset handshake */
5676 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5677 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5678
5679 /* enable PG1 and Misc I/O */
5680 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5681
5682 /* DPLL0 already enabed !? */
5683 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5684 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5685 return;
5686 }
5687
5688 /* enable DPLL0 */
5689 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5690 skl_dpll0_enable(dev_priv, required_vco);
5691
5692 /* set CDCLK to the frequency the BIOS chose */
5693 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5694
5695 /* enable DBUF power */
5696 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5697 POSTING_READ(DBUF_CTL);
5698
5699 udelay(10);
5700
5701 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5702 DRM_ERROR("DBuf power enable timeout\n");
5703 }
5704
5705 /* returns HPLL frequency in kHz */
5706 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5707 {
5708 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5709
5710 /* Obtain SKU information */
5711 mutex_lock(&dev_priv->sb_lock);
5712 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5713 CCK_FUSE_HPLL_FREQ_MASK;
5714 mutex_unlock(&dev_priv->sb_lock);
5715
5716 return vco_freq[hpll_freq] * 1000;
5717 }
5718
5719 /* Adjust CDclk dividers to allow high res or save power if possible */
5720 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5721 {
5722 struct drm_i915_private *dev_priv = dev->dev_private;
5723 u32 val, cmd;
5724
5725 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5726 != dev_priv->cdclk_freq);
5727
5728 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5729 cmd = 2;
5730 else if (cdclk == 266667)
5731 cmd = 1;
5732 else
5733 cmd = 0;
5734
5735 mutex_lock(&dev_priv->rps.hw_lock);
5736 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5737 val &= ~DSPFREQGUAR_MASK;
5738 val |= (cmd << DSPFREQGUAR_SHIFT);
5739 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5740 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5741 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5742 50)) {
5743 DRM_ERROR("timed out waiting for CDclk change\n");
5744 }
5745 mutex_unlock(&dev_priv->rps.hw_lock);
5746
5747 mutex_lock(&dev_priv->sb_lock);
5748
5749 if (cdclk == 400000) {
5750 u32 divider;
5751
5752 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5753
5754 /* adjust cdclk divider */
5755 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5756 val &= ~DISPLAY_FREQUENCY_VALUES;
5757 val |= divider;
5758 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5759
5760 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5761 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5762 50))
5763 DRM_ERROR("timed out waiting for CDclk change\n");
5764 }
5765
5766 /* adjust self-refresh exit latency value */
5767 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5768 val &= ~0x7f;
5769
5770 /*
5771 * For high bandwidth configs, we set a higher latency in the bunit
5772 * so that the core display fetch happens in time to avoid underruns.
5773 */
5774 if (cdclk == 400000)
5775 val |= 4500 / 250; /* 4.5 usec */
5776 else
5777 val |= 3000 / 250; /* 3.0 usec */
5778 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5779
5780 mutex_unlock(&dev_priv->sb_lock);
5781
5782 intel_update_cdclk(dev);
5783 }
5784
5785 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5786 {
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 u32 val, cmd;
5789
5790 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5791 != dev_priv->cdclk_freq);
5792
5793 switch (cdclk) {
5794 case 333333:
5795 case 320000:
5796 case 266667:
5797 case 200000:
5798 break;
5799 default:
5800 MISSING_CASE(cdclk);
5801 return;
5802 }
5803
5804 /*
5805 * Specs are full of misinformation, but testing on actual
5806 * hardware has shown that we just need to write the desired
5807 * CCK divider into the Punit register.
5808 */
5809 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5810
5811 mutex_lock(&dev_priv->rps.hw_lock);
5812 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5813 val &= ~DSPFREQGUAR_MASK_CHV;
5814 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5815 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5816 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5817 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5818 50)) {
5819 DRM_ERROR("timed out waiting for CDclk change\n");
5820 }
5821 mutex_unlock(&dev_priv->rps.hw_lock);
5822
5823 intel_update_cdclk(dev);
5824 }
5825
5826 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5827 int max_pixclk)
5828 {
5829 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5830 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5831
5832 /*
5833 * Really only a few cases to deal with, as only 4 CDclks are supported:
5834 * 200MHz
5835 * 267MHz
5836 * 320/333MHz (depends on HPLL freq)
5837 * 400MHz (VLV only)
5838 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5839 * of the lower bin and adjust if needed.
5840 *
5841 * We seem to get an unstable or solid color picture at 200MHz.
5842 * Not sure what's wrong. For now use 200MHz only when all pipes
5843 * are off.
5844 */
5845 if (!IS_CHERRYVIEW(dev_priv) &&
5846 max_pixclk > freq_320*limit/100)
5847 return 400000;
5848 else if (max_pixclk > 266667*limit/100)
5849 return freq_320;
5850 else if (max_pixclk > 0)
5851 return 266667;
5852 else
5853 return 200000;
5854 }
5855
5856 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5857 int max_pixclk)
5858 {
5859 /*
5860 * FIXME:
5861 * - remove the guardband, it's not needed on BXT
5862 * - set 19.2MHz bypass frequency if there are no active pipes
5863 */
5864 if (max_pixclk > 576000*9/10)
5865 return 624000;
5866 else if (max_pixclk > 384000*9/10)
5867 return 576000;
5868 else if (max_pixclk > 288000*9/10)
5869 return 384000;
5870 else if (max_pixclk > 144000*9/10)
5871 return 288000;
5872 else
5873 return 144000;
5874 }
5875
5876 /* Compute the max pixel clock for new configuration. Uses atomic state if
5877 * that's non-NULL, look at current state otherwise. */
5878 static int intel_mode_max_pixclk(struct drm_device *dev,
5879 struct drm_atomic_state *state)
5880 {
5881 struct intel_crtc *intel_crtc;
5882 struct intel_crtc_state *crtc_state;
5883 int max_pixclk = 0;
5884
5885 for_each_intel_crtc(dev, intel_crtc) {
5886 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5887 if (IS_ERR(crtc_state))
5888 return PTR_ERR(crtc_state);
5889
5890 if (!crtc_state->base.enable)
5891 continue;
5892
5893 max_pixclk = max(max_pixclk,
5894 crtc_state->base.adjusted_mode.crtc_clock);
5895 }
5896
5897 return max_pixclk;
5898 }
5899
5900 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5901 {
5902 struct drm_device *dev = state->dev;
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904 int max_pixclk = intel_mode_max_pixclk(dev, state);
5905
5906 if (max_pixclk < 0)
5907 return max_pixclk;
5908
5909 to_intel_atomic_state(state)->cdclk =
5910 valleyview_calc_cdclk(dev_priv, max_pixclk);
5911
5912 return 0;
5913 }
5914
5915 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5916 {
5917 struct drm_device *dev = state->dev;
5918 struct drm_i915_private *dev_priv = dev->dev_private;
5919 int max_pixclk = intel_mode_max_pixclk(dev, state);
5920
5921 if (max_pixclk < 0)
5922 return max_pixclk;
5923
5924 to_intel_atomic_state(state)->cdclk =
5925 broxton_calc_cdclk(dev_priv, max_pixclk);
5926
5927 return 0;
5928 }
5929
5930 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5931 {
5932 unsigned int credits, default_credits;
5933
5934 if (IS_CHERRYVIEW(dev_priv))
5935 default_credits = PFI_CREDIT(12);
5936 else
5937 default_credits = PFI_CREDIT(8);
5938
5939 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5940 /* CHV suggested value is 31 or 63 */
5941 if (IS_CHERRYVIEW(dev_priv))
5942 credits = PFI_CREDIT_63;
5943 else
5944 credits = PFI_CREDIT(15);
5945 } else {
5946 credits = default_credits;
5947 }
5948
5949 /*
5950 * WA - write default credits before re-programming
5951 * FIXME: should we also set the resend bit here?
5952 */
5953 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5954 default_credits);
5955
5956 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5957 credits | PFI_CREDIT_RESEND);
5958
5959 /*
5960 * FIXME is this guaranteed to clear
5961 * immediately or should we poll for it?
5962 */
5963 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5964 }
5965
5966 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5967 {
5968 struct drm_device *dev = old_state->dev;
5969 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971
5972 /*
5973 * FIXME: We can end up here with all power domains off, yet
5974 * with a CDCLK frequency other than the minimum. To account
5975 * for this take the PIPE-A power domain, which covers the HW
5976 * blocks needed for the following programming. This can be
5977 * removed once it's guaranteed that we get here either with
5978 * the minimum CDCLK set, or the required power domains
5979 * enabled.
5980 */
5981 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5982
5983 if (IS_CHERRYVIEW(dev))
5984 cherryview_set_cdclk(dev, req_cdclk);
5985 else
5986 valleyview_set_cdclk(dev, req_cdclk);
5987
5988 vlv_program_pfi_credits(dev_priv);
5989
5990 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5991 }
5992
5993 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5994 {
5995 struct drm_device *dev = crtc->dev;
5996 struct drm_i915_private *dev_priv = to_i915(dev);
5997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998 struct intel_encoder *encoder;
5999 int pipe = intel_crtc->pipe;
6000 bool is_dsi;
6001
6002 if (WARN_ON(intel_crtc->active))
6003 return;
6004
6005 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6006
6007 if (!is_dsi) {
6008 if (IS_CHERRYVIEW(dev))
6009 chv_prepare_pll(intel_crtc, intel_crtc->config);
6010 else
6011 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6012 }
6013
6014 if (intel_crtc->config->has_dp_encoder)
6015 intel_dp_set_m_n(intel_crtc, M1_N1);
6016
6017 intel_set_pipe_timings(intel_crtc);
6018
6019 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021
6022 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6023 I915_WRITE(CHV_CANVAS(pipe), 0);
6024 }
6025
6026 i9xx_set_pipeconf(intel_crtc);
6027
6028 intel_crtc->active = true;
6029
6030 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6031
6032 for_each_encoder_on_crtc(dev, crtc, encoder)
6033 if (encoder->pre_pll_enable)
6034 encoder->pre_pll_enable(encoder);
6035
6036 if (!is_dsi) {
6037 if (IS_CHERRYVIEW(dev))
6038 chv_enable_pll(intel_crtc, intel_crtc->config);
6039 else
6040 vlv_enable_pll(intel_crtc, intel_crtc->config);
6041 }
6042
6043 for_each_encoder_on_crtc(dev, crtc, encoder)
6044 if (encoder->pre_enable)
6045 encoder->pre_enable(encoder);
6046
6047 i9xx_pfit_enable(intel_crtc);
6048
6049 intel_crtc_load_lut(crtc);
6050
6051 intel_enable_pipe(intel_crtc);
6052
6053 assert_vblank_disabled(crtc);
6054 drm_crtc_vblank_on(crtc);
6055
6056 for_each_encoder_on_crtc(dev, crtc, encoder)
6057 encoder->enable(encoder);
6058 }
6059
6060 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6061 {
6062 struct drm_device *dev = crtc->base.dev;
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064
6065 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6066 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6067 }
6068
6069 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6070 {
6071 struct drm_device *dev = crtc->dev;
6072 struct drm_i915_private *dev_priv = to_i915(dev);
6073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074 struct intel_encoder *encoder;
6075 int pipe = intel_crtc->pipe;
6076
6077 if (WARN_ON(intel_crtc->active))
6078 return;
6079
6080 i9xx_set_pll_dividers(intel_crtc);
6081
6082 if (intel_crtc->config->has_dp_encoder)
6083 intel_dp_set_m_n(intel_crtc, M1_N1);
6084
6085 intel_set_pipe_timings(intel_crtc);
6086
6087 i9xx_set_pipeconf(intel_crtc);
6088
6089 intel_crtc->active = true;
6090
6091 if (!IS_GEN2(dev))
6092 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6093
6094 for_each_encoder_on_crtc(dev, crtc, encoder)
6095 if (encoder->pre_enable)
6096 encoder->pre_enable(encoder);
6097
6098 i9xx_enable_pll(intel_crtc);
6099
6100 i9xx_pfit_enable(intel_crtc);
6101
6102 intel_crtc_load_lut(crtc);
6103
6104 intel_update_watermarks(crtc);
6105 intel_enable_pipe(intel_crtc);
6106
6107 assert_vblank_disabled(crtc);
6108 drm_crtc_vblank_on(crtc);
6109
6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 encoder->enable(encoder);
6112 }
6113
6114 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6115 {
6116 struct drm_device *dev = crtc->base.dev;
6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118
6119 if (!crtc->config->gmch_pfit.control)
6120 return;
6121
6122 assert_pipe_disabled(dev_priv, crtc->pipe);
6123
6124 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6125 I915_READ(PFIT_CONTROL));
6126 I915_WRITE(PFIT_CONTROL, 0);
6127 }
6128
6129 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6130 {
6131 struct drm_device *dev = crtc->dev;
6132 struct drm_i915_private *dev_priv = dev->dev_private;
6133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6134 struct intel_encoder *encoder;
6135 int pipe = intel_crtc->pipe;
6136
6137 /*
6138 * On gen2 planes are double buffered but the pipe isn't, so we must
6139 * wait for planes to fully turn off before disabling the pipe.
6140 * We also need to wait on all gmch platforms because of the
6141 * self-refresh mode constraint explained above.
6142 */
6143 intel_wait_for_vblank(dev, pipe);
6144
6145 for_each_encoder_on_crtc(dev, crtc, encoder)
6146 encoder->disable(encoder);
6147
6148 drm_crtc_vblank_off(crtc);
6149 assert_vblank_disabled(crtc);
6150
6151 intel_disable_pipe(intel_crtc);
6152
6153 i9xx_pfit_disable(intel_crtc);
6154
6155 for_each_encoder_on_crtc(dev, crtc, encoder)
6156 if (encoder->post_disable)
6157 encoder->post_disable(encoder);
6158
6159 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6160 if (IS_CHERRYVIEW(dev))
6161 chv_disable_pll(dev_priv, pipe);
6162 else if (IS_VALLEYVIEW(dev))
6163 vlv_disable_pll(dev_priv, pipe);
6164 else
6165 i9xx_disable_pll(intel_crtc);
6166 }
6167
6168 if (!IS_GEN2(dev))
6169 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6170
6171 intel_crtc->active = false;
6172 intel_update_watermarks(crtc);
6173 }
6174
6175 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6176 {
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6179 enum intel_display_power_domain domain;
6180 unsigned long domains;
6181
6182 if (!intel_crtc->active)
6183 return;
6184
6185 if (to_intel_plane_state(crtc->primary->state)->visible) {
6186 intel_crtc_wait_for_pending_flips(crtc);
6187 intel_pre_disable_primary(crtc);
6188 }
6189
6190 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6191 dev_priv->display.crtc_disable(crtc);
6192
6193 domains = intel_crtc->enabled_power_domains;
6194 for_each_power_domain(domain, domains)
6195 intel_display_power_put(dev_priv, domain);
6196 intel_crtc->enabled_power_domains = 0;
6197 }
6198
6199 /*
6200 * turn all crtc's off, but do not adjust state
6201 * This has to be paired with a call to intel_modeset_setup_hw_state.
6202 */
6203 void intel_display_suspend(struct drm_device *dev)
6204 {
6205 struct drm_crtc *crtc;
6206
6207 for_each_crtc(dev, crtc)
6208 intel_crtc_disable_noatomic(crtc);
6209 }
6210
6211 /* Master function to enable/disable CRTC and corresponding power wells */
6212 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6213 {
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_mode_config *config = &dev->mode_config;
6216 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218 struct intel_crtc_state *pipe_config;
6219 struct drm_atomic_state *state;
6220 int ret;
6221
6222 if (enable == intel_crtc->active)
6223 return 0;
6224
6225 if (enable && !crtc->state->enable)
6226 return 0;
6227
6228 /* this function should be called with drm_modeset_lock_all for now */
6229 if (WARN_ON(!ctx))
6230 return -EIO;
6231 lockdep_assert_held(&ctx->ww_ctx);
6232
6233 state = drm_atomic_state_alloc(dev);
6234 if (WARN_ON(!state))
6235 return -ENOMEM;
6236
6237 state->acquire_ctx = ctx;
6238 state->allow_modeset = true;
6239
6240 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6241 if (IS_ERR(pipe_config)) {
6242 ret = PTR_ERR(pipe_config);
6243 goto err;
6244 }
6245 pipe_config->base.active = enable;
6246
6247 ret = intel_set_mode(state);
6248 if (!ret)
6249 return ret;
6250
6251 err:
6252 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6253 drm_atomic_state_free(state);
6254 return ret;
6255 }
6256
6257 /**
6258 * Sets the power management mode of the pipe and plane.
6259 */
6260 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6261 {
6262 struct drm_device *dev = crtc->dev;
6263 struct intel_encoder *intel_encoder;
6264 bool enable = false;
6265
6266 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6267 enable |= intel_encoder->connectors_active;
6268
6269 intel_crtc_control(crtc, enable);
6270 }
6271
6272 void intel_encoder_destroy(struct drm_encoder *encoder)
6273 {
6274 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6275
6276 drm_encoder_cleanup(encoder);
6277 kfree(intel_encoder);
6278 }
6279
6280 /* Simple dpms helper for encoders with just one connector, no cloning and only
6281 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6282 * state of the entire output pipe. */
6283 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6284 {
6285 if (mode == DRM_MODE_DPMS_ON) {
6286 encoder->connectors_active = true;
6287
6288 intel_crtc_update_dpms(encoder->base.crtc);
6289 } else {
6290 encoder->connectors_active = false;
6291
6292 intel_crtc_update_dpms(encoder->base.crtc);
6293 }
6294 }
6295
6296 /* Cross check the actual hw state with our own modeset state tracking (and it's
6297 * internal consistency). */
6298 static void intel_connector_check_state(struct intel_connector *connector)
6299 {
6300 if (connector->get_hw_state(connector)) {
6301 struct intel_encoder *encoder = connector->encoder;
6302 struct drm_crtc *crtc;
6303 bool encoder_enabled;
6304 enum pipe pipe;
6305
6306 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6307 connector->base.base.id,
6308 connector->base.name);
6309
6310 /* there is no real hw state for MST connectors */
6311 if (connector->mst_port)
6312 return;
6313
6314 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6315 "wrong connector dpms state\n");
6316 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6317 "active connector not linked to encoder\n");
6318
6319 if (encoder) {
6320 I915_STATE_WARN(!encoder->connectors_active,
6321 "encoder->connectors_active not set\n");
6322
6323 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6324 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6325 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6326 return;
6327
6328 crtc = encoder->base.crtc;
6329
6330 I915_STATE_WARN(!crtc->state->enable,
6331 "crtc not enabled\n");
6332 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6333 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6334 "encoder active on the wrong pipe\n");
6335 }
6336 }
6337 }
6338
6339 int intel_connector_init(struct intel_connector *connector)
6340 {
6341 struct drm_connector_state *connector_state;
6342
6343 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6344 if (!connector_state)
6345 return -ENOMEM;
6346
6347 connector->base.state = connector_state;
6348 return 0;
6349 }
6350
6351 struct intel_connector *intel_connector_alloc(void)
6352 {
6353 struct intel_connector *connector;
6354
6355 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6356 if (!connector)
6357 return NULL;
6358
6359 if (intel_connector_init(connector) < 0) {
6360 kfree(connector);
6361 return NULL;
6362 }
6363
6364 return connector;
6365 }
6366
6367 /* Even simpler default implementation, if there's really no special case to
6368 * consider. */
6369 void intel_connector_dpms(struct drm_connector *connector, int mode)
6370 {
6371 /* All the simple cases only support two dpms states. */
6372 if (mode != DRM_MODE_DPMS_ON)
6373 mode = DRM_MODE_DPMS_OFF;
6374
6375 if (mode == connector->dpms)
6376 return;
6377
6378 connector->dpms = mode;
6379
6380 /* Only need to change hw state when actually enabled */
6381 if (connector->encoder)
6382 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6383
6384 intel_modeset_check_state(connector->dev);
6385 }
6386
6387 /* Simple connector->get_hw_state implementation for encoders that support only
6388 * one connector and no cloning and hence the encoder state determines the state
6389 * of the connector. */
6390 bool intel_connector_get_hw_state(struct intel_connector *connector)
6391 {
6392 enum pipe pipe = 0;
6393 struct intel_encoder *encoder = connector->encoder;
6394
6395 return encoder->get_hw_state(encoder, &pipe);
6396 }
6397
6398 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6399 {
6400 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6401 return crtc_state->fdi_lanes;
6402
6403 return 0;
6404 }
6405
6406 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6407 struct intel_crtc_state *pipe_config)
6408 {
6409 struct drm_atomic_state *state = pipe_config->base.state;
6410 struct intel_crtc *other_crtc;
6411 struct intel_crtc_state *other_crtc_state;
6412
6413 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6415 if (pipe_config->fdi_lanes > 4) {
6416 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6417 pipe_name(pipe), pipe_config->fdi_lanes);
6418 return -EINVAL;
6419 }
6420
6421 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6422 if (pipe_config->fdi_lanes > 2) {
6423 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6424 pipe_config->fdi_lanes);
6425 return -EINVAL;
6426 } else {
6427 return 0;
6428 }
6429 }
6430
6431 if (INTEL_INFO(dev)->num_pipes == 2)
6432 return 0;
6433
6434 /* Ivybridge 3 pipe is really complicated */
6435 switch (pipe) {
6436 case PIPE_A:
6437 return 0;
6438 case PIPE_B:
6439 if (pipe_config->fdi_lanes <= 2)
6440 return 0;
6441
6442 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6443 other_crtc_state =
6444 intel_atomic_get_crtc_state(state, other_crtc);
6445 if (IS_ERR(other_crtc_state))
6446 return PTR_ERR(other_crtc_state);
6447
6448 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6449 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 return -EINVAL;
6452 }
6453 return 0;
6454 case PIPE_C:
6455 if (pipe_config->fdi_lanes > 2) {
6456 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6457 pipe_name(pipe), pipe_config->fdi_lanes);
6458 return -EINVAL;
6459 }
6460
6461 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6462 other_crtc_state =
6463 intel_atomic_get_crtc_state(state, other_crtc);
6464 if (IS_ERR(other_crtc_state))
6465 return PTR_ERR(other_crtc_state);
6466
6467 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6468 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6469 return -EINVAL;
6470 }
6471 return 0;
6472 default:
6473 BUG();
6474 }
6475 }
6476
6477 #define RETRY 1
6478 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6479 struct intel_crtc_state *pipe_config)
6480 {
6481 struct drm_device *dev = intel_crtc->base.dev;
6482 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6483 int lane, link_bw, fdi_dotclock, ret;
6484 bool needs_recompute = false;
6485
6486 retry:
6487 /* FDI is a binary signal running at ~2.7GHz, encoding
6488 * each output octet as 10 bits. The actual frequency
6489 * is stored as a divider into a 100MHz clock, and the
6490 * mode pixel clock is stored in units of 1KHz.
6491 * Hence the bw of each lane in terms of the mode signal
6492 * is:
6493 */
6494 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6495
6496 fdi_dotclock = adjusted_mode->crtc_clock;
6497
6498 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6499 pipe_config->pipe_bpp);
6500
6501 pipe_config->fdi_lanes = lane;
6502
6503 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6504 link_bw, &pipe_config->fdi_m_n);
6505
6506 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6507 intel_crtc->pipe, pipe_config);
6508 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6509 pipe_config->pipe_bpp -= 2*3;
6510 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6511 pipe_config->pipe_bpp);
6512 needs_recompute = true;
6513 pipe_config->bw_constrained = true;
6514
6515 goto retry;
6516 }
6517
6518 if (needs_recompute)
6519 return RETRY;
6520
6521 return ret;
6522 }
6523
6524 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6525 struct intel_crtc_state *pipe_config)
6526 {
6527 if (pipe_config->pipe_bpp > 24)
6528 return false;
6529
6530 /* HSW can handle pixel rate up to cdclk? */
6531 if (IS_HASWELL(dev_priv->dev))
6532 return true;
6533
6534 /*
6535 * We compare against max which means we must take
6536 * the increased cdclk requirement into account when
6537 * calculating the new cdclk.
6538 *
6539 * Should measure whether using a lower cdclk w/o IPS
6540 */
6541 return ilk_pipe_pixel_rate(pipe_config) <=
6542 dev_priv->max_cdclk_freq * 95 / 100;
6543 }
6544
6545 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6546 struct intel_crtc_state *pipe_config)
6547 {
6548 struct drm_device *dev = crtc->base.dev;
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6550
6551 pipe_config->ips_enabled = i915.enable_ips &&
6552 hsw_crtc_supports_ips(crtc) &&
6553 pipe_config_supports_ips(dev_priv, pipe_config);
6554 }
6555
6556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6557 struct intel_crtc_state *pipe_config)
6558 {
6559 struct drm_device *dev = crtc->base.dev;
6560 struct drm_i915_private *dev_priv = dev->dev_private;
6561 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6562
6563 /* FIXME should check pixel clock limits on all platforms */
6564 if (INTEL_INFO(dev)->gen < 4) {
6565 int clock_limit = dev_priv->max_cdclk_freq;
6566
6567 /*
6568 * Enable pixel doubling when the dot clock
6569 * is > 90% of the (display) core speed.
6570 *
6571 * GDG double wide on either pipe,
6572 * otherwise pipe A only.
6573 */
6574 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6575 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6576 clock_limit *= 2;
6577 pipe_config->double_wide = true;
6578 }
6579
6580 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6581 return -EINVAL;
6582 }
6583
6584 /*
6585 * Pipe horizontal size must be even in:
6586 * - DVO ganged mode
6587 * - LVDS dual channel mode
6588 * - Double wide pipe
6589 */
6590 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6591 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6592 pipe_config->pipe_src_w &= ~1;
6593
6594 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6595 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6596 */
6597 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6598 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6599 return -EINVAL;
6600
6601 if (HAS_IPS(dev))
6602 hsw_compute_ips_config(crtc, pipe_config);
6603
6604 if (pipe_config->has_pch_encoder)
6605 return ironlake_fdi_compute_config(crtc, pipe_config);
6606
6607 return 0;
6608 }
6609
6610 static int skylake_get_display_clock_speed(struct drm_device *dev)
6611 {
6612 struct drm_i915_private *dev_priv = to_i915(dev);
6613 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6614 uint32_t cdctl = I915_READ(CDCLK_CTL);
6615 uint32_t linkrate;
6616
6617 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6618 return 24000; /* 24MHz is the cd freq with NSSC ref */
6619
6620 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6621 return 540000;
6622
6623 linkrate = (I915_READ(DPLL_CTRL1) &
6624 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6625
6626 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6627 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6628 /* vco 8640 */
6629 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6630 case CDCLK_FREQ_450_432:
6631 return 432000;
6632 case CDCLK_FREQ_337_308:
6633 return 308570;
6634 case CDCLK_FREQ_675_617:
6635 return 617140;
6636 default:
6637 WARN(1, "Unknown cd freq selection\n");
6638 }
6639 } else {
6640 /* vco 8100 */
6641 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6642 case CDCLK_FREQ_450_432:
6643 return 450000;
6644 case CDCLK_FREQ_337_308:
6645 return 337500;
6646 case CDCLK_FREQ_675_617:
6647 return 675000;
6648 default:
6649 WARN(1, "Unknown cd freq selection\n");
6650 }
6651 }
6652
6653 /* error case, do as if DPLL0 isn't enabled */
6654 return 24000;
6655 }
6656
6657 static int broxton_get_display_clock_speed(struct drm_device *dev)
6658 {
6659 struct drm_i915_private *dev_priv = to_i915(dev);
6660 uint32_t cdctl = I915_READ(CDCLK_CTL);
6661 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6662 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6663 int cdclk;
6664
6665 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6666 return 19200;
6667
6668 cdclk = 19200 * pll_ratio / 2;
6669
6670 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6671 case BXT_CDCLK_CD2X_DIV_SEL_1:
6672 return cdclk; /* 576MHz or 624MHz */
6673 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6674 return cdclk * 2 / 3; /* 384MHz */
6675 case BXT_CDCLK_CD2X_DIV_SEL_2:
6676 return cdclk / 2; /* 288MHz */
6677 case BXT_CDCLK_CD2X_DIV_SEL_4:
6678 return cdclk / 4; /* 144MHz */
6679 }
6680
6681 /* error case, do as if DE PLL isn't enabled */
6682 return 19200;
6683 }
6684
6685 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6686 {
6687 struct drm_i915_private *dev_priv = dev->dev_private;
6688 uint32_t lcpll = I915_READ(LCPLL_CTL);
6689 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6690
6691 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6692 return 800000;
6693 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6694 return 450000;
6695 else if (freq == LCPLL_CLK_FREQ_450)
6696 return 450000;
6697 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6698 return 540000;
6699 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6700 return 337500;
6701 else
6702 return 675000;
6703 }
6704
6705 static int haswell_get_display_clock_speed(struct drm_device *dev)
6706 {
6707 struct drm_i915_private *dev_priv = dev->dev_private;
6708 uint32_t lcpll = I915_READ(LCPLL_CTL);
6709 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6710
6711 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6712 return 800000;
6713 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6714 return 450000;
6715 else if (freq == LCPLL_CLK_FREQ_450)
6716 return 450000;
6717 else if (IS_HSW_ULT(dev))
6718 return 337500;
6719 else
6720 return 540000;
6721 }
6722
6723 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6724 {
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 u32 val;
6727 int divider;
6728
6729 if (dev_priv->hpll_freq == 0)
6730 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6731
6732 mutex_lock(&dev_priv->sb_lock);
6733 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6734 mutex_unlock(&dev_priv->sb_lock);
6735
6736 divider = val & DISPLAY_FREQUENCY_VALUES;
6737
6738 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6739 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6740 "cdclk change in progress\n");
6741
6742 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6743 }
6744
6745 static int ilk_get_display_clock_speed(struct drm_device *dev)
6746 {
6747 return 450000;
6748 }
6749
6750 static int i945_get_display_clock_speed(struct drm_device *dev)
6751 {
6752 return 400000;
6753 }
6754
6755 static int i915_get_display_clock_speed(struct drm_device *dev)
6756 {
6757 return 333333;
6758 }
6759
6760 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6761 {
6762 return 200000;
6763 }
6764
6765 static int pnv_get_display_clock_speed(struct drm_device *dev)
6766 {
6767 u16 gcfgc = 0;
6768
6769 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6770
6771 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6772 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6773 return 266667;
6774 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6775 return 333333;
6776 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6777 return 444444;
6778 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6779 return 200000;
6780 default:
6781 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6782 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6783 return 133333;
6784 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6785 return 166667;
6786 }
6787 }
6788
6789 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6790 {
6791 u16 gcfgc = 0;
6792
6793 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6794
6795 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6796 return 133333;
6797 else {
6798 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6799 case GC_DISPLAY_CLOCK_333_MHZ:
6800 return 333333;
6801 default:
6802 case GC_DISPLAY_CLOCK_190_200_MHZ:
6803 return 190000;
6804 }
6805 }
6806 }
6807
6808 static int i865_get_display_clock_speed(struct drm_device *dev)
6809 {
6810 return 266667;
6811 }
6812
6813 static int i85x_get_display_clock_speed(struct drm_device *dev)
6814 {
6815 u16 hpllcc = 0;
6816
6817 /*
6818 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6819 * encoding is different :(
6820 * FIXME is this the right way to detect 852GM/852GMV?
6821 */
6822 if (dev->pdev->revision == 0x1)
6823 return 133333;
6824
6825 pci_bus_read_config_word(dev->pdev->bus,
6826 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6827
6828 /* Assume that the hardware is in the high speed state. This
6829 * should be the default.
6830 */
6831 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6832 case GC_CLOCK_133_200:
6833 case GC_CLOCK_133_200_2:
6834 case GC_CLOCK_100_200:
6835 return 200000;
6836 case GC_CLOCK_166_250:
6837 return 250000;
6838 case GC_CLOCK_100_133:
6839 return 133333;
6840 case GC_CLOCK_133_266:
6841 case GC_CLOCK_133_266_2:
6842 case GC_CLOCK_166_266:
6843 return 266667;
6844 }
6845
6846 /* Shouldn't happen */
6847 return 0;
6848 }
6849
6850 static int i830_get_display_clock_speed(struct drm_device *dev)
6851 {
6852 return 133333;
6853 }
6854
6855 static unsigned int intel_hpll_vco(struct drm_device *dev)
6856 {
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 static const unsigned int blb_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 4800000,
6863 [4] = 6400000,
6864 };
6865 static const unsigned int pnv_vco[8] = {
6866 [0] = 3200000,
6867 [1] = 4000000,
6868 [2] = 5333333,
6869 [3] = 4800000,
6870 [4] = 2666667,
6871 };
6872 static const unsigned int cl_vco[8] = {
6873 [0] = 3200000,
6874 [1] = 4000000,
6875 [2] = 5333333,
6876 [3] = 6400000,
6877 [4] = 3333333,
6878 [5] = 3566667,
6879 [6] = 4266667,
6880 };
6881 static const unsigned int elk_vco[8] = {
6882 [0] = 3200000,
6883 [1] = 4000000,
6884 [2] = 5333333,
6885 [3] = 4800000,
6886 };
6887 static const unsigned int ctg_vco[8] = {
6888 [0] = 3200000,
6889 [1] = 4000000,
6890 [2] = 5333333,
6891 [3] = 6400000,
6892 [4] = 2666667,
6893 [5] = 4266667,
6894 };
6895 const unsigned int *vco_table;
6896 unsigned int vco;
6897 uint8_t tmp = 0;
6898
6899 /* FIXME other chipsets? */
6900 if (IS_GM45(dev))
6901 vco_table = ctg_vco;
6902 else if (IS_G4X(dev))
6903 vco_table = elk_vco;
6904 else if (IS_CRESTLINE(dev))
6905 vco_table = cl_vco;
6906 else if (IS_PINEVIEW(dev))
6907 vco_table = pnv_vco;
6908 else if (IS_G33(dev))
6909 vco_table = blb_vco;
6910 else
6911 return 0;
6912
6913 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6914
6915 vco = vco_table[tmp & 0x7];
6916 if (vco == 0)
6917 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6918 else
6919 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6920
6921 return vco;
6922 }
6923
6924 static int gm45_get_display_clock_speed(struct drm_device *dev)
6925 {
6926 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6927 uint16_t tmp = 0;
6928
6929 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6930
6931 cdclk_sel = (tmp >> 12) & 0x1;
6932
6933 switch (vco) {
6934 case 2666667:
6935 case 4000000:
6936 case 5333333:
6937 return cdclk_sel ? 333333 : 222222;
6938 case 3200000:
6939 return cdclk_sel ? 320000 : 228571;
6940 default:
6941 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6942 return 222222;
6943 }
6944 }
6945
6946 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6947 {
6948 static const uint8_t div_3200[] = { 16, 10, 8 };
6949 static const uint8_t div_4000[] = { 20, 12, 10 };
6950 static const uint8_t div_5333[] = { 24, 16, 14 };
6951 const uint8_t *div_table;
6952 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6953 uint16_t tmp = 0;
6954
6955 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6956
6957 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6958
6959 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6960 goto fail;
6961
6962 switch (vco) {
6963 case 3200000:
6964 div_table = div_3200;
6965 break;
6966 case 4000000:
6967 div_table = div_4000;
6968 break;
6969 case 5333333:
6970 div_table = div_5333;
6971 break;
6972 default:
6973 goto fail;
6974 }
6975
6976 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6977
6978 fail:
6979 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6980 return 200000;
6981 }
6982
6983 static int g33_get_display_clock_speed(struct drm_device *dev)
6984 {
6985 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6986 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6987 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6988 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6989 const uint8_t *div_table;
6990 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6991 uint16_t tmp = 0;
6992
6993 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6994
6995 cdclk_sel = (tmp >> 4) & 0x7;
6996
6997 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6998 goto fail;
6999
7000 switch (vco) {
7001 case 3200000:
7002 div_table = div_3200;
7003 break;
7004 case 4000000:
7005 div_table = div_4000;
7006 break;
7007 case 4800000:
7008 div_table = div_4800;
7009 break;
7010 case 5333333:
7011 div_table = div_5333;
7012 break;
7013 default:
7014 goto fail;
7015 }
7016
7017 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7018
7019 fail:
7020 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7021 return 190476;
7022 }
7023
7024 static void
7025 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7026 {
7027 while (*num > DATA_LINK_M_N_MASK ||
7028 *den > DATA_LINK_M_N_MASK) {
7029 *num >>= 1;
7030 *den >>= 1;
7031 }
7032 }
7033
7034 static void compute_m_n(unsigned int m, unsigned int n,
7035 uint32_t *ret_m, uint32_t *ret_n)
7036 {
7037 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7038 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7039 intel_reduce_m_n_ratio(ret_m, ret_n);
7040 }
7041
7042 void
7043 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7044 int pixel_clock, int link_clock,
7045 struct intel_link_m_n *m_n)
7046 {
7047 m_n->tu = 64;
7048
7049 compute_m_n(bits_per_pixel * pixel_clock,
7050 link_clock * nlanes * 8,
7051 &m_n->gmch_m, &m_n->gmch_n);
7052
7053 compute_m_n(pixel_clock, link_clock,
7054 &m_n->link_m, &m_n->link_n);
7055 }
7056
7057 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7058 {
7059 if (i915.panel_use_ssc >= 0)
7060 return i915.panel_use_ssc != 0;
7061 return dev_priv->vbt.lvds_use_ssc
7062 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7063 }
7064
7065 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7066 int num_connectors)
7067 {
7068 struct drm_device *dev = crtc_state->base.crtc->dev;
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7070 int refclk;
7071
7072 WARN_ON(!crtc_state->base.state);
7073
7074 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7075 refclk = 100000;
7076 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7077 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7078 refclk = dev_priv->vbt.lvds_ssc_freq;
7079 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7080 } else if (!IS_GEN2(dev)) {
7081 refclk = 96000;
7082 } else {
7083 refclk = 48000;
7084 }
7085
7086 return refclk;
7087 }
7088
7089 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7090 {
7091 return (1 << dpll->n) << 16 | dpll->m2;
7092 }
7093
7094 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7095 {
7096 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7097 }
7098
7099 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7100 struct intel_crtc_state *crtc_state,
7101 intel_clock_t *reduced_clock)
7102 {
7103 struct drm_device *dev = crtc->base.dev;
7104 u32 fp, fp2 = 0;
7105
7106 if (IS_PINEVIEW(dev)) {
7107 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7108 if (reduced_clock)
7109 fp2 = pnv_dpll_compute_fp(reduced_clock);
7110 } else {
7111 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7112 if (reduced_clock)
7113 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7114 }
7115
7116 crtc_state->dpll_hw_state.fp0 = fp;
7117
7118 crtc->lowfreq_avail = false;
7119 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7120 reduced_clock) {
7121 crtc_state->dpll_hw_state.fp1 = fp2;
7122 crtc->lowfreq_avail = true;
7123 } else {
7124 crtc_state->dpll_hw_state.fp1 = fp;
7125 }
7126 }
7127
7128 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7129 pipe)
7130 {
7131 u32 reg_val;
7132
7133 /*
7134 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7135 * and set it to a reasonable value instead.
7136 */
7137 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7138 reg_val &= 0xffffff00;
7139 reg_val |= 0x00000030;
7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7141
7142 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7143 reg_val &= 0x8cffffff;
7144 reg_val = 0x8c000000;
7145 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7146
7147 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7148 reg_val &= 0xffffff00;
7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7150
7151 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7152 reg_val &= 0x00ffffff;
7153 reg_val |= 0xb0000000;
7154 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7155 }
7156
7157 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7158 struct intel_link_m_n *m_n)
7159 {
7160 struct drm_device *dev = crtc->base.dev;
7161 struct drm_i915_private *dev_priv = dev->dev_private;
7162 int pipe = crtc->pipe;
7163
7164 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7165 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7166 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7167 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7168 }
7169
7170 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7171 struct intel_link_m_n *m_n,
7172 struct intel_link_m_n *m2_n2)
7173 {
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 int pipe = crtc->pipe;
7177 enum transcoder transcoder = crtc->config->cpu_transcoder;
7178
7179 if (INTEL_INFO(dev)->gen >= 5) {
7180 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7181 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7182 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7183 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7184 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7185 * for gen < 8) and if DRRS is supported (to make sure the
7186 * registers are not unnecessarily accessed).
7187 */
7188 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7189 crtc->config->has_drrs) {
7190 I915_WRITE(PIPE_DATA_M2(transcoder),
7191 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7192 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7193 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7194 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7195 }
7196 } else {
7197 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7199 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7200 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7201 }
7202 }
7203
7204 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7205 {
7206 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7207
7208 if (m_n == M1_N1) {
7209 dp_m_n = &crtc->config->dp_m_n;
7210 dp_m2_n2 = &crtc->config->dp_m2_n2;
7211 } else if (m_n == M2_N2) {
7212
7213 /*
7214 * M2_N2 registers are not supported. Hence m2_n2 divider value
7215 * needs to be programmed into M1_N1.
7216 */
7217 dp_m_n = &crtc->config->dp_m2_n2;
7218 } else {
7219 DRM_ERROR("Unsupported divider value\n");
7220 return;
7221 }
7222
7223 if (crtc->config->has_pch_encoder)
7224 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7225 else
7226 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7227 }
7228
7229 static void vlv_compute_dpll(struct intel_crtc *crtc,
7230 struct intel_crtc_state *pipe_config)
7231 {
7232 u32 dpll, dpll_md;
7233
7234 /*
7235 * Enable DPIO clock input. We should never disable the reference
7236 * clock for pipe B, since VGA hotplug / manual detection depends
7237 * on it.
7238 */
7239 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7240 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7241 /* We should never disable this, set it here for state tracking */
7242 if (crtc->pipe == PIPE_B)
7243 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7244 dpll |= DPLL_VCO_ENABLE;
7245 pipe_config->dpll_hw_state.dpll = dpll;
7246
7247 dpll_md = (pipe_config->pixel_multiplier - 1)
7248 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7249 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7250 }
7251
7252 static void vlv_prepare_pll(struct intel_crtc *crtc,
7253 const struct intel_crtc_state *pipe_config)
7254 {
7255 struct drm_device *dev = crtc->base.dev;
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 int pipe = crtc->pipe;
7258 u32 mdiv;
7259 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7260 u32 coreclk, reg_val;
7261
7262 mutex_lock(&dev_priv->sb_lock);
7263
7264 bestn = pipe_config->dpll.n;
7265 bestm1 = pipe_config->dpll.m1;
7266 bestm2 = pipe_config->dpll.m2;
7267 bestp1 = pipe_config->dpll.p1;
7268 bestp2 = pipe_config->dpll.p2;
7269
7270 /* See eDP HDMI DPIO driver vbios notes doc */
7271
7272 /* PLL B needs special handling */
7273 if (pipe == PIPE_B)
7274 vlv_pllb_recal_opamp(dev_priv, pipe);
7275
7276 /* Set up Tx target for periodic Rcomp update */
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7278
7279 /* Disable target IRef on PLL */
7280 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7281 reg_val &= 0x00ffffff;
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7283
7284 /* Disable fast lock */
7285 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7286
7287 /* Set idtafcrecal before PLL is enabled */
7288 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7289 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7290 mdiv |= ((bestn << DPIO_N_SHIFT));
7291 mdiv |= (1 << DPIO_K_SHIFT);
7292
7293 /*
7294 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7295 * but we don't support that).
7296 * Note: don't use the DAC post divider as it seems unstable.
7297 */
7298 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7300
7301 mdiv |= DPIO_ENABLE_CALIBRATION;
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7303
7304 /* Set HBR and RBR LPF coefficients */
7305 if (pipe_config->port_clock == 162000 ||
7306 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7307 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7309 0x009f0003);
7310 else
7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7312 0x00d0000f);
7313
7314 if (pipe_config->has_dp_encoder) {
7315 /* Use SSC source */
7316 if (pipe == PIPE_A)
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7318 0x0df40000);
7319 else
7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7321 0x0df70000);
7322 } else { /* HDMI or VGA */
7323 /* Use bend source */
7324 if (pipe == PIPE_A)
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326 0x0df70000);
7327 else
7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7329 0x0df40000);
7330 }
7331
7332 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7333 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7335 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7336 coreclk |= 0x01000000;
7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7338
7339 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7340 mutex_unlock(&dev_priv->sb_lock);
7341 }
7342
7343 static void chv_compute_dpll(struct intel_crtc *crtc,
7344 struct intel_crtc_state *pipe_config)
7345 {
7346 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7347 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7348 DPLL_VCO_ENABLE;
7349 if (crtc->pipe != PIPE_A)
7350 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7351
7352 pipe_config->dpll_hw_state.dpll_md =
7353 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7354 }
7355
7356 static void chv_prepare_pll(struct intel_crtc *crtc,
7357 const struct intel_crtc_state *pipe_config)
7358 {
7359 struct drm_device *dev = crtc->base.dev;
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 int pipe = crtc->pipe;
7362 int dpll_reg = DPLL(crtc->pipe);
7363 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7364 u32 loopfilter, tribuf_calcntr;
7365 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7366 u32 dpio_val;
7367 int vco;
7368
7369 bestn = pipe_config->dpll.n;
7370 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7371 bestm1 = pipe_config->dpll.m1;
7372 bestm2 = pipe_config->dpll.m2 >> 22;
7373 bestp1 = pipe_config->dpll.p1;
7374 bestp2 = pipe_config->dpll.p2;
7375 vco = pipe_config->dpll.vco;
7376 dpio_val = 0;
7377 loopfilter = 0;
7378
7379 /*
7380 * Enable Refclk and SSC
7381 */
7382 I915_WRITE(dpll_reg,
7383 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7384
7385 mutex_lock(&dev_priv->sb_lock);
7386
7387 /* p1 and p2 divider */
7388 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7389 5 << DPIO_CHV_S1_DIV_SHIFT |
7390 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7391 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7392 1 << DPIO_CHV_K_DIV_SHIFT);
7393
7394 /* Feedback post-divider - m2 */
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7396
7397 /* Feedback refclk divider - n and m1 */
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7399 DPIO_CHV_M1_DIV_BY_2 |
7400 1 << DPIO_CHV_N_DIV_SHIFT);
7401
7402 /* M2 fraction division */
7403 if (bestm2_frac)
7404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7405
7406 /* M2 fraction division enable */
7407 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7408 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7409 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7410 if (bestm2_frac)
7411 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7413
7414 /* Program digital lock detect threshold */
7415 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7416 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7417 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7418 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7419 if (!bestm2_frac)
7420 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7421 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7422
7423 /* Loop filter */
7424 if (vco == 5400000) {
7425 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7426 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7427 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7428 tribuf_calcntr = 0x9;
7429 } else if (vco <= 6200000) {
7430 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7431 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7432 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433 tribuf_calcntr = 0x9;
7434 } else if (vco <= 6480000) {
7435 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7436 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7437 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438 tribuf_calcntr = 0x8;
7439 } else {
7440 /* Not supported. Apply the same limits as in the max case */
7441 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7442 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7443 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7444 tribuf_calcntr = 0;
7445 }
7446 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7447
7448 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7449 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7450 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7452
7453 /* AFC Recal */
7454 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7455 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7456 DPIO_AFC_RECAL);
7457
7458 mutex_unlock(&dev_priv->sb_lock);
7459 }
7460
7461 /**
7462 * vlv_force_pll_on - forcibly enable just the PLL
7463 * @dev_priv: i915 private structure
7464 * @pipe: pipe PLL to enable
7465 * @dpll: PLL configuration
7466 *
7467 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7468 * in cases where we need the PLL enabled even when @pipe is not going to
7469 * be enabled.
7470 */
7471 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7472 const struct dpll *dpll)
7473 {
7474 struct intel_crtc *crtc =
7475 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7476 struct intel_crtc_state pipe_config = {
7477 .base.crtc = &crtc->base,
7478 .pixel_multiplier = 1,
7479 .dpll = *dpll,
7480 };
7481
7482 if (IS_CHERRYVIEW(dev)) {
7483 chv_compute_dpll(crtc, &pipe_config);
7484 chv_prepare_pll(crtc, &pipe_config);
7485 chv_enable_pll(crtc, &pipe_config);
7486 } else {
7487 vlv_compute_dpll(crtc, &pipe_config);
7488 vlv_prepare_pll(crtc, &pipe_config);
7489 vlv_enable_pll(crtc, &pipe_config);
7490 }
7491 }
7492
7493 /**
7494 * vlv_force_pll_off - forcibly disable just the PLL
7495 * @dev_priv: i915 private structure
7496 * @pipe: pipe PLL to disable
7497 *
7498 * Disable the PLL for @pipe. To be used in cases where we need
7499 * the PLL enabled even when @pipe is not going to be enabled.
7500 */
7501 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7502 {
7503 if (IS_CHERRYVIEW(dev))
7504 chv_disable_pll(to_i915(dev), pipe);
7505 else
7506 vlv_disable_pll(to_i915(dev), pipe);
7507 }
7508
7509 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7510 struct intel_crtc_state *crtc_state,
7511 intel_clock_t *reduced_clock,
7512 int num_connectors)
7513 {
7514 struct drm_device *dev = crtc->base.dev;
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 u32 dpll;
7517 bool is_sdvo;
7518 struct dpll *clock = &crtc_state->dpll;
7519
7520 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7521
7522 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7523 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7524
7525 dpll = DPLL_VGA_MODE_DIS;
7526
7527 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7528 dpll |= DPLLB_MODE_LVDS;
7529 else
7530 dpll |= DPLLB_MODE_DAC_SERIAL;
7531
7532 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7533 dpll |= (crtc_state->pixel_multiplier - 1)
7534 << SDVO_MULTIPLIER_SHIFT_HIRES;
7535 }
7536
7537 if (is_sdvo)
7538 dpll |= DPLL_SDVO_HIGH_SPEED;
7539
7540 if (crtc_state->has_dp_encoder)
7541 dpll |= DPLL_SDVO_HIGH_SPEED;
7542
7543 /* compute bitmask from p1 value */
7544 if (IS_PINEVIEW(dev))
7545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7546 else {
7547 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7548 if (IS_G4X(dev) && reduced_clock)
7549 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7550 }
7551 switch (clock->p2) {
7552 case 5:
7553 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7554 break;
7555 case 7:
7556 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7557 break;
7558 case 10:
7559 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7560 break;
7561 case 14:
7562 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7563 break;
7564 }
7565 if (INTEL_INFO(dev)->gen >= 4)
7566 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7567
7568 if (crtc_state->sdvo_tv_clock)
7569 dpll |= PLL_REF_INPUT_TVCLKINBC;
7570 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7571 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7572 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7573 else
7574 dpll |= PLL_REF_INPUT_DREFCLK;
7575
7576 dpll |= DPLL_VCO_ENABLE;
7577 crtc_state->dpll_hw_state.dpll = dpll;
7578
7579 if (INTEL_INFO(dev)->gen >= 4) {
7580 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7581 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7582 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7583 }
7584 }
7585
7586 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7587 struct intel_crtc_state *crtc_state,
7588 intel_clock_t *reduced_clock,
7589 int num_connectors)
7590 {
7591 struct drm_device *dev = crtc->base.dev;
7592 struct drm_i915_private *dev_priv = dev->dev_private;
7593 u32 dpll;
7594 struct dpll *clock = &crtc_state->dpll;
7595
7596 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7597
7598 dpll = DPLL_VGA_MODE_DIS;
7599
7600 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7601 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7602 } else {
7603 if (clock->p1 == 2)
7604 dpll |= PLL_P1_DIVIDE_BY_TWO;
7605 else
7606 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7607 if (clock->p2 == 4)
7608 dpll |= PLL_P2_DIVIDE_BY_4;
7609 }
7610
7611 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7612 dpll |= DPLL_DVO_2X_MODE;
7613
7614 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7615 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7616 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7617 else
7618 dpll |= PLL_REF_INPUT_DREFCLK;
7619
7620 dpll |= DPLL_VCO_ENABLE;
7621 crtc_state->dpll_hw_state.dpll = dpll;
7622 }
7623
7624 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7625 {
7626 struct drm_device *dev = intel_crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 enum pipe pipe = intel_crtc->pipe;
7629 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7630 struct drm_display_mode *adjusted_mode =
7631 &intel_crtc->config->base.adjusted_mode;
7632 uint32_t crtc_vtotal, crtc_vblank_end;
7633 int vsyncshift = 0;
7634
7635 /* We need to be careful not to changed the adjusted mode, for otherwise
7636 * the hw state checker will get angry at the mismatch. */
7637 crtc_vtotal = adjusted_mode->crtc_vtotal;
7638 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7639
7640 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7641 /* the chip adds 2 halflines automatically */
7642 crtc_vtotal -= 1;
7643 crtc_vblank_end -= 1;
7644
7645 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7646 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7647 else
7648 vsyncshift = adjusted_mode->crtc_hsync_start -
7649 adjusted_mode->crtc_htotal / 2;
7650 if (vsyncshift < 0)
7651 vsyncshift += adjusted_mode->crtc_htotal;
7652 }
7653
7654 if (INTEL_INFO(dev)->gen > 3)
7655 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7656
7657 I915_WRITE(HTOTAL(cpu_transcoder),
7658 (adjusted_mode->crtc_hdisplay - 1) |
7659 ((adjusted_mode->crtc_htotal - 1) << 16));
7660 I915_WRITE(HBLANK(cpu_transcoder),
7661 (adjusted_mode->crtc_hblank_start - 1) |
7662 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7663 I915_WRITE(HSYNC(cpu_transcoder),
7664 (adjusted_mode->crtc_hsync_start - 1) |
7665 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7666
7667 I915_WRITE(VTOTAL(cpu_transcoder),
7668 (adjusted_mode->crtc_vdisplay - 1) |
7669 ((crtc_vtotal - 1) << 16));
7670 I915_WRITE(VBLANK(cpu_transcoder),
7671 (adjusted_mode->crtc_vblank_start - 1) |
7672 ((crtc_vblank_end - 1) << 16));
7673 I915_WRITE(VSYNC(cpu_transcoder),
7674 (adjusted_mode->crtc_vsync_start - 1) |
7675 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7676
7677 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7678 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7679 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7680 * bits. */
7681 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7682 (pipe == PIPE_B || pipe == PIPE_C))
7683 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7684
7685 /* pipesrc controls the size that is scaled from, which should
7686 * always be the user's requested size.
7687 */
7688 I915_WRITE(PIPESRC(pipe),
7689 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7690 (intel_crtc->config->pipe_src_h - 1));
7691 }
7692
7693 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7694 struct intel_crtc_state *pipe_config)
7695 {
7696 struct drm_device *dev = crtc->base.dev;
7697 struct drm_i915_private *dev_priv = dev->dev_private;
7698 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7699 uint32_t tmp;
7700
7701 tmp = I915_READ(HTOTAL(cpu_transcoder));
7702 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7703 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7704 tmp = I915_READ(HBLANK(cpu_transcoder));
7705 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7706 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7707 tmp = I915_READ(HSYNC(cpu_transcoder));
7708 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7709 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7710
7711 tmp = I915_READ(VTOTAL(cpu_transcoder));
7712 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7713 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7714 tmp = I915_READ(VBLANK(cpu_transcoder));
7715 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7716 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7717 tmp = I915_READ(VSYNC(cpu_transcoder));
7718 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7719 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7720
7721 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7722 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7723 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7724 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7725 }
7726
7727 tmp = I915_READ(PIPESRC(crtc->pipe));
7728 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7729 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7730
7731 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7732 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7733 }
7734
7735 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7736 struct intel_crtc_state *pipe_config)
7737 {
7738 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7739 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7740 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7741 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7742
7743 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7744 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7745 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7746 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7747
7748 mode->flags = pipe_config->base.adjusted_mode.flags;
7749
7750 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7751 mode->flags |= pipe_config->base.adjusted_mode.flags;
7752 }
7753
7754 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7755 {
7756 struct drm_device *dev = intel_crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 uint32_t pipeconf;
7759
7760 pipeconf = 0;
7761
7762 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7763 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7764 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7765
7766 if (intel_crtc->config->double_wide)
7767 pipeconf |= PIPECONF_DOUBLE_WIDE;
7768
7769 /* only g4x and later have fancy bpc/dither controls */
7770 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7771 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7772 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7773 pipeconf |= PIPECONF_DITHER_EN |
7774 PIPECONF_DITHER_TYPE_SP;
7775
7776 switch (intel_crtc->config->pipe_bpp) {
7777 case 18:
7778 pipeconf |= PIPECONF_6BPC;
7779 break;
7780 case 24:
7781 pipeconf |= PIPECONF_8BPC;
7782 break;
7783 case 30:
7784 pipeconf |= PIPECONF_10BPC;
7785 break;
7786 default:
7787 /* Case prevented by intel_choose_pipe_bpp_dither. */
7788 BUG();
7789 }
7790 }
7791
7792 if (HAS_PIPE_CXSR(dev)) {
7793 if (intel_crtc->lowfreq_avail) {
7794 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7795 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7796 } else {
7797 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7798 }
7799 }
7800
7801 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7802 if (INTEL_INFO(dev)->gen < 4 ||
7803 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7804 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7805 else
7806 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7807 } else
7808 pipeconf |= PIPECONF_PROGRESSIVE;
7809
7810 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7811 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7812
7813 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7814 POSTING_READ(PIPECONF(intel_crtc->pipe));
7815 }
7816
7817 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7818 struct intel_crtc_state *crtc_state)
7819 {
7820 struct drm_device *dev = crtc->base.dev;
7821 struct drm_i915_private *dev_priv = dev->dev_private;
7822 int refclk, num_connectors = 0;
7823 intel_clock_t clock;
7824 bool ok;
7825 bool is_dsi = false;
7826 struct intel_encoder *encoder;
7827 const intel_limit_t *limit;
7828 struct drm_atomic_state *state = crtc_state->base.state;
7829 struct drm_connector *connector;
7830 struct drm_connector_state *connector_state;
7831 int i;
7832
7833 memset(&crtc_state->dpll_hw_state, 0,
7834 sizeof(crtc_state->dpll_hw_state));
7835
7836 for_each_connector_in_state(state, connector, connector_state, i) {
7837 if (connector_state->crtc != &crtc->base)
7838 continue;
7839
7840 encoder = to_intel_encoder(connector_state->best_encoder);
7841
7842 switch (encoder->type) {
7843 case INTEL_OUTPUT_DSI:
7844 is_dsi = true;
7845 break;
7846 default:
7847 break;
7848 }
7849
7850 num_connectors++;
7851 }
7852
7853 if (is_dsi)
7854 return 0;
7855
7856 if (!crtc_state->clock_set) {
7857 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7858
7859 /*
7860 * Returns a set of divisors for the desired target clock with
7861 * the given refclk, or FALSE. The returned values represent
7862 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7863 * 2) / p1 / p2.
7864 */
7865 limit = intel_limit(crtc_state, refclk);
7866 ok = dev_priv->display.find_dpll(limit, crtc_state,
7867 crtc_state->port_clock,
7868 refclk, NULL, &clock);
7869 if (!ok) {
7870 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7871 return -EINVAL;
7872 }
7873
7874 /* Compat-code for transition, will disappear. */
7875 crtc_state->dpll.n = clock.n;
7876 crtc_state->dpll.m1 = clock.m1;
7877 crtc_state->dpll.m2 = clock.m2;
7878 crtc_state->dpll.p1 = clock.p1;
7879 crtc_state->dpll.p2 = clock.p2;
7880 }
7881
7882 if (IS_GEN2(dev)) {
7883 i8xx_compute_dpll(crtc, crtc_state, NULL,
7884 num_connectors);
7885 } else if (IS_CHERRYVIEW(dev)) {
7886 chv_compute_dpll(crtc, crtc_state);
7887 } else if (IS_VALLEYVIEW(dev)) {
7888 vlv_compute_dpll(crtc, crtc_state);
7889 } else {
7890 i9xx_compute_dpll(crtc, crtc_state, NULL,
7891 num_connectors);
7892 }
7893
7894 return 0;
7895 }
7896
7897 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7898 struct intel_crtc_state *pipe_config)
7899 {
7900 struct drm_device *dev = crtc->base.dev;
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7902 uint32_t tmp;
7903
7904 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7905 return;
7906
7907 tmp = I915_READ(PFIT_CONTROL);
7908 if (!(tmp & PFIT_ENABLE))
7909 return;
7910
7911 /* Check whether the pfit is attached to our pipe. */
7912 if (INTEL_INFO(dev)->gen < 4) {
7913 if (crtc->pipe != PIPE_B)
7914 return;
7915 } else {
7916 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7917 return;
7918 }
7919
7920 pipe_config->gmch_pfit.control = tmp;
7921 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7922 if (INTEL_INFO(dev)->gen < 5)
7923 pipe_config->gmch_pfit.lvds_border_bits =
7924 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7925 }
7926
7927 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7928 struct intel_crtc_state *pipe_config)
7929 {
7930 struct drm_device *dev = crtc->base.dev;
7931 struct drm_i915_private *dev_priv = dev->dev_private;
7932 int pipe = pipe_config->cpu_transcoder;
7933 intel_clock_t clock;
7934 u32 mdiv;
7935 int refclk = 100000;
7936
7937 /* In case of MIPI DPLL will not even be used */
7938 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7939 return;
7940
7941 mutex_lock(&dev_priv->sb_lock);
7942 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7943 mutex_unlock(&dev_priv->sb_lock);
7944
7945 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7946 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7947 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7948 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7949 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7950
7951 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7952 }
7953
7954 static void
7955 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7956 struct intel_initial_plane_config *plane_config)
7957 {
7958 struct drm_device *dev = crtc->base.dev;
7959 struct drm_i915_private *dev_priv = dev->dev_private;
7960 u32 val, base, offset;
7961 int pipe = crtc->pipe, plane = crtc->plane;
7962 int fourcc, pixel_format;
7963 unsigned int aligned_height;
7964 struct drm_framebuffer *fb;
7965 struct intel_framebuffer *intel_fb;
7966
7967 val = I915_READ(DSPCNTR(plane));
7968 if (!(val & DISPLAY_PLANE_ENABLE))
7969 return;
7970
7971 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7972 if (!intel_fb) {
7973 DRM_DEBUG_KMS("failed to alloc fb\n");
7974 return;
7975 }
7976
7977 fb = &intel_fb->base;
7978
7979 if (INTEL_INFO(dev)->gen >= 4) {
7980 if (val & DISPPLANE_TILED) {
7981 plane_config->tiling = I915_TILING_X;
7982 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7983 }
7984 }
7985
7986 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7987 fourcc = i9xx_format_to_fourcc(pixel_format);
7988 fb->pixel_format = fourcc;
7989 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7990
7991 if (INTEL_INFO(dev)->gen >= 4) {
7992 if (plane_config->tiling)
7993 offset = I915_READ(DSPTILEOFF(plane));
7994 else
7995 offset = I915_READ(DSPLINOFF(plane));
7996 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7997 } else {
7998 base = I915_READ(DSPADDR(plane));
7999 }
8000 plane_config->base = base;
8001
8002 val = I915_READ(PIPESRC(pipe));
8003 fb->width = ((val >> 16) & 0xfff) + 1;
8004 fb->height = ((val >> 0) & 0xfff) + 1;
8005
8006 val = I915_READ(DSPSTRIDE(pipe));
8007 fb->pitches[0] = val & 0xffffffc0;
8008
8009 aligned_height = intel_fb_align_height(dev, fb->height,
8010 fb->pixel_format,
8011 fb->modifier[0]);
8012
8013 plane_config->size = fb->pitches[0] * aligned_height;
8014
8015 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8016 pipe_name(pipe), plane, fb->width, fb->height,
8017 fb->bits_per_pixel, base, fb->pitches[0],
8018 plane_config->size);
8019
8020 plane_config->fb = intel_fb;
8021 }
8022
8023 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8024 struct intel_crtc_state *pipe_config)
8025 {
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 int pipe = pipe_config->cpu_transcoder;
8029 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8030 intel_clock_t clock;
8031 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8032 int refclk = 100000;
8033
8034 mutex_lock(&dev_priv->sb_lock);
8035 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8036 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8037 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8038 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8039 mutex_unlock(&dev_priv->sb_lock);
8040
8041 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8042 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8043 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8044 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8045 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8046
8047 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8048 }
8049
8050 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8051 struct intel_crtc_state *pipe_config)
8052 {
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 uint32_t tmp;
8056
8057 if (!intel_display_power_is_enabled(dev_priv,
8058 POWER_DOMAIN_PIPE(crtc->pipe)))
8059 return false;
8060
8061 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8062 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8063
8064 tmp = I915_READ(PIPECONF(crtc->pipe));
8065 if (!(tmp & PIPECONF_ENABLE))
8066 return false;
8067
8068 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8069 switch (tmp & PIPECONF_BPC_MASK) {
8070 case PIPECONF_6BPC:
8071 pipe_config->pipe_bpp = 18;
8072 break;
8073 case PIPECONF_8BPC:
8074 pipe_config->pipe_bpp = 24;
8075 break;
8076 case PIPECONF_10BPC:
8077 pipe_config->pipe_bpp = 30;
8078 break;
8079 default:
8080 break;
8081 }
8082 }
8083
8084 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8085 pipe_config->limited_color_range = true;
8086
8087 if (INTEL_INFO(dev)->gen < 4)
8088 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8089
8090 intel_get_pipe_timings(crtc, pipe_config);
8091
8092 i9xx_get_pfit_config(crtc, pipe_config);
8093
8094 if (INTEL_INFO(dev)->gen >= 4) {
8095 tmp = I915_READ(DPLL_MD(crtc->pipe));
8096 pipe_config->pixel_multiplier =
8097 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8098 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8099 pipe_config->dpll_hw_state.dpll_md = tmp;
8100 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8101 tmp = I915_READ(DPLL(crtc->pipe));
8102 pipe_config->pixel_multiplier =
8103 ((tmp & SDVO_MULTIPLIER_MASK)
8104 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8105 } else {
8106 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8107 * port and will be fixed up in the encoder->get_config
8108 * function. */
8109 pipe_config->pixel_multiplier = 1;
8110 }
8111 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8112 if (!IS_VALLEYVIEW(dev)) {
8113 /*
8114 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8115 * on 830. Filter it out here so that we don't
8116 * report errors due to that.
8117 */
8118 if (IS_I830(dev))
8119 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8120
8121 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8122 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8123 } else {
8124 /* Mask out read-only status bits. */
8125 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8126 DPLL_PORTC_READY_MASK |
8127 DPLL_PORTB_READY_MASK);
8128 }
8129
8130 if (IS_CHERRYVIEW(dev))
8131 chv_crtc_clock_get(crtc, pipe_config);
8132 else if (IS_VALLEYVIEW(dev))
8133 vlv_crtc_clock_get(crtc, pipe_config);
8134 else
8135 i9xx_crtc_clock_get(crtc, pipe_config);
8136
8137 return true;
8138 }
8139
8140 static void ironlake_init_pch_refclk(struct drm_device *dev)
8141 {
8142 struct drm_i915_private *dev_priv = dev->dev_private;
8143 struct intel_encoder *encoder;
8144 u32 val, final;
8145 bool has_lvds = false;
8146 bool has_cpu_edp = false;
8147 bool has_panel = false;
8148 bool has_ck505 = false;
8149 bool can_ssc = false;
8150
8151 /* We need to take the global config into account */
8152 for_each_intel_encoder(dev, encoder) {
8153 switch (encoder->type) {
8154 case INTEL_OUTPUT_LVDS:
8155 has_panel = true;
8156 has_lvds = true;
8157 break;
8158 case INTEL_OUTPUT_EDP:
8159 has_panel = true;
8160 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8161 has_cpu_edp = true;
8162 break;
8163 default:
8164 break;
8165 }
8166 }
8167
8168 if (HAS_PCH_IBX(dev)) {
8169 has_ck505 = dev_priv->vbt.display_clock_mode;
8170 can_ssc = has_ck505;
8171 } else {
8172 has_ck505 = false;
8173 can_ssc = true;
8174 }
8175
8176 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8177 has_panel, has_lvds, has_ck505);
8178
8179 /* Ironlake: try to setup display ref clock before DPLL
8180 * enabling. This is only under driver's control after
8181 * PCH B stepping, previous chipset stepping should be
8182 * ignoring this setting.
8183 */
8184 val = I915_READ(PCH_DREF_CONTROL);
8185
8186 /* As we must carefully and slowly disable/enable each source in turn,
8187 * compute the final state we want first and check if we need to
8188 * make any changes at all.
8189 */
8190 final = val;
8191 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8192 if (has_ck505)
8193 final |= DREF_NONSPREAD_CK505_ENABLE;
8194 else
8195 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8196
8197 final &= ~DREF_SSC_SOURCE_MASK;
8198 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8199 final &= ~DREF_SSC1_ENABLE;
8200
8201 if (has_panel) {
8202 final |= DREF_SSC_SOURCE_ENABLE;
8203
8204 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8205 final |= DREF_SSC1_ENABLE;
8206
8207 if (has_cpu_edp) {
8208 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8209 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8210 else
8211 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8212 } else
8213 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8214 } else {
8215 final |= DREF_SSC_SOURCE_DISABLE;
8216 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8217 }
8218
8219 if (final == val)
8220 return;
8221
8222 /* Always enable nonspread source */
8223 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8224
8225 if (has_ck505)
8226 val |= DREF_NONSPREAD_CK505_ENABLE;
8227 else
8228 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8229
8230 if (has_panel) {
8231 val &= ~DREF_SSC_SOURCE_MASK;
8232 val |= DREF_SSC_SOURCE_ENABLE;
8233
8234 /* SSC must be turned on before enabling the CPU output */
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8236 DRM_DEBUG_KMS("Using SSC on panel\n");
8237 val |= DREF_SSC1_ENABLE;
8238 } else
8239 val &= ~DREF_SSC1_ENABLE;
8240
8241 /* Get SSC going before enabling the outputs */
8242 I915_WRITE(PCH_DREF_CONTROL, val);
8243 POSTING_READ(PCH_DREF_CONTROL);
8244 udelay(200);
8245
8246 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8247
8248 /* Enable CPU source on CPU attached eDP */
8249 if (has_cpu_edp) {
8250 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8251 DRM_DEBUG_KMS("Using SSC on eDP\n");
8252 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8253 } else
8254 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8255 } else
8256 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8257
8258 I915_WRITE(PCH_DREF_CONTROL, val);
8259 POSTING_READ(PCH_DREF_CONTROL);
8260 udelay(200);
8261 } else {
8262 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8263
8264 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8265
8266 /* Turn off CPU output */
8267 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8268
8269 I915_WRITE(PCH_DREF_CONTROL, val);
8270 POSTING_READ(PCH_DREF_CONTROL);
8271 udelay(200);
8272
8273 /* Turn off the SSC source */
8274 val &= ~DREF_SSC_SOURCE_MASK;
8275 val |= DREF_SSC_SOURCE_DISABLE;
8276
8277 /* Turn off SSC1 */
8278 val &= ~DREF_SSC1_ENABLE;
8279
8280 I915_WRITE(PCH_DREF_CONTROL, val);
8281 POSTING_READ(PCH_DREF_CONTROL);
8282 udelay(200);
8283 }
8284
8285 BUG_ON(val != final);
8286 }
8287
8288 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8289 {
8290 uint32_t tmp;
8291
8292 tmp = I915_READ(SOUTH_CHICKEN2);
8293 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8294 I915_WRITE(SOUTH_CHICKEN2, tmp);
8295
8296 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8297 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8298 DRM_ERROR("FDI mPHY reset assert timeout\n");
8299
8300 tmp = I915_READ(SOUTH_CHICKEN2);
8301 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8302 I915_WRITE(SOUTH_CHICKEN2, tmp);
8303
8304 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8305 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8306 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8307 }
8308
8309 /* WaMPhyProgramming:hsw */
8310 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8311 {
8312 uint32_t tmp;
8313
8314 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8315 tmp &= ~(0xFF << 24);
8316 tmp |= (0x12 << 24);
8317 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8318
8319 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8320 tmp |= (1 << 11);
8321 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8324 tmp |= (1 << 11);
8325 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8328 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8329 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8332 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8333 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8334
8335 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8336 tmp &= ~(7 << 13);
8337 tmp |= (5 << 13);
8338 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8339
8340 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8341 tmp &= ~(7 << 13);
8342 tmp |= (5 << 13);
8343 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8346 tmp &= ~0xFF;
8347 tmp |= 0x1C;
8348 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8351 tmp &= ~0xFF;
8352 tmp |= 0x1C;
8353 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8354
8355 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8356 tmp &= ~(0xFF << 16);
8357 tmp |= (0x1C << 16);
8358 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8361 tmp &= ~(0xFF << 16);
8362 tmp |= (0x1C << 16);
8363 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8366 tmp |= (1 << 27);
8367 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8370 tmp |= (1 << 27);
8371 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8372
8373 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8374 tmp &= ~(0xF << 28);
8375 tmp |= (4 << 28);
8376 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8377
8378 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8379 tmp &= ~(0xF << 28);
8380 tmp |= (4 << 28);
8381 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8382 }
8383
8384 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8385 * Programming" based on the parameters passed:
8386 * - Sequence to enable CLKOUT_DP
8387 * - Sequence to enable CLKOUT_DP without spread
8388 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8389 */
8390 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8391 bool with_fdi)
8392 {
8393 struct drm_i915_private *dev_priv = dev->dev_private;
8394 uint32_t reg, tmp;
8395
8396 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8397 with_spread = true;
8398 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8399 with_fdi, "LP PCH doesn't have FDI\n"))
8400 with_fdi = false;
8401
8402 mutex_lock(&dev_priv->sb_lock);
8403
8404 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8405 tmp &= ~SBI_SSCCTL_DISABLE;
8406 tmp |= SBI_SSCCTL_PATHALT;
8407 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8408
8409 udelay(24);
8410
8411 if (with_spread) {
8412 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8413 tmp &= ~SBI_SSCCTL_PATHALT;
8414 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8415
8416 if (with_fdi) {
8417 lpt_reset_fdi_mphy(dev_priv);
8418 lpt_program_fdi_mphy(dev_priv);
8419 }
8420 }
8421
8422 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8423 SBI_GEN0 : SBI_DBUFF0;
8424 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8425 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8426 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8427
8428 mutex_unlock(&dev_priv->sb_lock);
8429 }
8430
8431 /* Sequence to disable CLKOUT_DP */
8432 static void lpt_disable_clkout_dp(struct drm_device *dev)
8433 {
8434 struct drm_i915_private *dev_priv = dev->dev_private;
8435 uint32_t reg, tmp;
8436
8437 mutex_lock(&dev_priv->sb_lock);
8438
8439 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8440 SBI_GEN0 : SBI_DBUFF0;
8441 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8442 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8443 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8444
8445 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8446 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8447 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8448 tmp |= SBI_SSCCTL_PATHALT;
8449 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8450 udelay(32);
8451 }
8452 tmp |= SBI_SSCCTL_DISABLE;
8453 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8454 }
8455
8456 mutex_unlock(&dev_priv->sb_lock);
8457 }
8458
8459 static void lpt_init_pch_refclk(struct drm_device *dev)
8460 {
8461 struct intel_encoder *encoder;
8462 bool has_vga = false;
8463
8464 for_each_intel_encoder(dev, encoder) {
8465 switch (encoder->type) {
8466 case INTEL_OUTPUT_ANALOG:
8467 has_vga = true;
8468 break;
8469 default:
8470 break;
8471 }
8472 }
8473
8474 if (has_vga)
8475 lpt_enable_clkout_dp(dev, true, true);
8476 else
8477 lpt_disable_clkout_dp(dev);
8478 }
8479
8480 /*
8481 * Initialize reference clocks when the driver loads
8482 */
8483 void intel_init_pch_refclk(struct drm_device *dev)
8484 {
8485 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8486 ironlake_init_pch_refclk(dev);
8487 else if (HAS_PCH_LPT(dev))
8488 lpt_init_pch_refclk(dev);
8489 }
8490
8491 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8492 {
8493 struct drm_device *dev = crtc_state->base.crtc->dev;
8494 struct drm_i915_private *dev_priv = dev->dev_private;
8495 struct drm_atomic_state *state = crtc_state->base.state;
8496 struct drm_connector *connector;
8497 struct drm_connector_state *connector_state;
8498 struct intel_encoder *encoder;
8499 int num_connectors = 0, i;
8500 bool is_lvds = false;
8501
8502 for_each_connector_in_state(state, connector, connector_state, i) {
8503 if (connector_state->crtc != crtc_state->base.crtc)
8504 continue;
8505
8506 encoder = to_intel_encoder(connector_state->best_encoder);
8507
8508 switch (encoder->type) {
8509 case INTEL_OUTPUT_LVDS:
8510 is_lvds = true;
8511 break;
8512 default:
8513 break;
8514 }
8515 num_connectors++;
8516 }
8517
8518 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8519 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8520 dev_priv->vbt.lvds_ssc_freq);
8521 return dev_priv->vbt.lvds_ssc_freq;
8522 }
8523
8524 return 120000;
8525 }
8526
8527 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8528 {
8529 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8531 int pipe = intel_crtc->pipe;
8532 uint32_t val;
8533
8534 val = 0;
8535
8536 switch (intel_crtc->config->pipe_bpp) {
8537 case 18:
8538 val |= PIPECONF_6BPC;
8539 break;
8540 case 24:
8541 val |= PIPECONF_8BPC;
8542 break;
8543 case 30:
8544 val |= PIPECONF_10BPC;
8545 break;
8546 case 36:
8547 val |= PIPECONF_12BPC;
8548 break;
8549 default:
8550 /* Case prevented by intel_choose_pipe_bpp_dither. */
8551 BUG();
8552 }
8553
8554 if (intel_crtc->config->dither)
8555 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8556
8557 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8558 val |= PIPECONF_INTERLACED_ILK;
8559 else
8560 val |= PIPECONF_PROGRESSIVE;
8561
8562 if (intel_crtc->config->limited_color_range)
8563 val |= PIPECONF_COLOR_RANGE_SELECT;
8564
8565 I915_WRITE(PIPECONF(pipe), val);
8566 POSTING_READ(PIPECONF(pipe));
8567 }
8568
8569 /*
8570 * Set up the pipe CSC unit.
8571 *
8572 * Currently only full range RGB to limited range RGB conversion
8573 * is supported, but eventually this should handle various
8574 * RGB<->YCbCr scenarios as well.
8575 */
8576 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8577 {
8578 struct drm_device *dev = crtc->dev;
8579 struct drm_i915_private *dev_priv = dev->dev_private;
8580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8581 int pipe = intel_crtc->pipe;
8582 uint16_t coeff = 0x7800; /* 1.0 */
8583
8584 /*
8585 * TODO: Check what kind of values actually come out of the pipe
8586 * with these coeff/postoff values and adjust to get the best
8587 * accuracy. Perhaps we even need to take the bpc value into
8588 * consideration.
8589 */
8590
8591 if (intel_crtc->config->limited_color_range)
8592 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8593
8594 /*
8595 * GY/GU and RY/RU should be the other way around according
8596 * to BSpec, but reality doesn't agree. Just set them up in
8597 * a way that results in the correct picture.
8598 */
8599 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8600 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8601
8602 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8603 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8604
8605 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8606 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8607
8608 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8609 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8610 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8611
8612 if (INTEL_INFO(dev)->gen > 6) {
8613 uint16_t postoff = 0;
8614
8615 if (intel_crtc->config->limited_color_range)
8616 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8617
8618 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8619 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8620 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8621
8622 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8623 } else {
8624 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8625
8626 if (intel_crtc->config->limited_color_range)
8627 mode |= CSC_BLACK_SCREEN_OFFSET;
8628
8629 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8630 }
8631 }
8632
8633 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8634 {
8635 struct drm_device *dev = crtc->dev;
8636 struct drm_i915_private *dev_priv = dev->dev_private;
8637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8638 enum pipe pipe = intel_crtc->pipe;
8639 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8640 uint32_t val;
8641
8642 val = 0;
8643
8644 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8645 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8646
8647 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8648 val |= PIPECONF_INTERLACED_ILK;
8649 else
8650 val |= PIPECONF_PROGRESSIVE;
8651
8652 I915_WRITE(PIPECONF(cpu_transcoder), val);
8653 POSTING_READ(PIPECONF(cpu_transcoder));
8654
8655 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8656 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8657
8658 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8659 val = 0;
8660
8661 switch (intel_crtc->config->pipe_bpp) {
8662 case 18:
8663 val |= PIPEMISC_DITHER_6_BPC;
8664 break;
8665 case 24:
8666 val |= PIPEMISC_DITHER_8_BPC;
8667 break;
8668 case 30:
8669 val |= PIPEMISC_DITHER_10_BPC;
8670 break;
8671 case 36:
8672 val |= PIPEMISC_DITHER_12_BPC;
8673 break;
8674 default:
8675 /* Case prevented by pipe_config_set_bpp. */
8676 BUG();
8677 }
8678
8679 if (intel_crtc->config->dither)
8680 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8681
8682 I915_WRITE(PIPEMISC(pipe), val);
8683 }
8684 }
8685
8686 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8687 struct intel_crtc_state *crtc_state,
8688 intel_clock_t *clock,
8689 bool *has_reduced_clock,
8690 intel_clock_t *reduced_clock)
8691 {
8692 struct drm_device *dev = crtc->dev;
8693 struct drm_i915_private *dev_priv = dev->dev_private;
8694 int refclk;
8695 const intel_limit_t *limit;
8696 bool ret;
8697
8698 refclk = ironlake_get_refclk(crtc_state);
8699
8700 /*
8701 * Returns a set of divisors for the desired target clock with the given
8702 * refclk, or FALSE. The returned values represent the clock equation:
8703 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8704 */
8705 limit = intel_limit(crtc_state, refclk);
8706 ret = dev_priv->display.find_dpll(limit, crtc_state,
8707 crtc_state->port_clock,
8708 refclk, NULL, clock);
8709 if (!ret)
8710 return false;
8711
8712 return true;
8713 }
8714
8715 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8716 {
8717 /*
8718 * Account for spread spectrum to avoid
8719 * oversubscribing the link. Max center spread
8720 * is 2.5%; use 5% for safety's sake.
8721 */
8722 u32 bps = target_clock * bpp * 21 / 20;
8723 return DIV_ROUND_UP(bps, link_bw * 8);
8724 }
8725
8726 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8727 {
8728 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8729 }
8730
8731 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8732 struct intel_crtc_state *crtc_state,
8733 u32 *fp,
8734 intel_clock_t *reduced_clock, u32 *fp2)
8735 {
8736 struct drm_crtc *crtc = &intel_crtc->base;
8737 struct drm_device *dev = crtc->dev;
8738 struct drm_i915_private *dev_priv = dev->dev_private;
8739 struct drm_atomic_state *state = crtc_state->base.state;
8740 struct drm_connector *connector;
8741 struct drm_connector_state *connector_state;
8742 struct intel_encoder *encoder;
8743 uint32_t dpll;
8744 int factor, num_connectors = 0, i;
8745 bool is_lvds = false, is_sdvo = false;
8746
8747 for_each_connector_in_state(state, connector, connector_state, i) {
8748 if (connector_state->crtc != crtc_state->base.crtc)
8749 continue;
8750
8751 encoder = to_intel_encoder(connector_state->best_encoder);
8752
8753 switch (encoder->type) {
8754 case INTEL_OUTPUT_LVDS:
8755 is_lvds = true;
8756 break;
8757 case INTEL_OUTPUT_SDVO:
8758 case INTEL_OUTPUT_HDMI:
8759 is_sdvo = true;
8760 break;
8761 default:
8762 break;
8763 }
8764
8765 num_connectors++;
8766 }
8767
8768 /* Enable autotuning of the PLL clock (if permissible) */
8769 factor = 21;
8770 if (is_lvds) {
8771 if ((intel_panel_use_ssc(dev_priv) &&
8772 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8773 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8774 factor = 25;
8775 } else if (crtc_state->sdvo_tv_clock)
8776 factor = 20;
8777
8778 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8779 *fp |= FP_CB_TUNE;
8780
8781 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8782 *fp2 |= FP_CB_TUNE;
8783
8784 dpll = 0;
8785
8786 if (is_lvds)
8787 dpll |= DPLLB_MODE_LVDS;
8788 else
8789 dpll |= DPLLB_MODE_DAC_SERIAL;
8790
8791 dpll |= (crtc_state->pixel_multiplier - 1)
8792 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8793
8794 if (is_sdvo)
8795 dpll |= DPLL_SDVO_HIGH_SPEED;
8796 if (crtc_state->has_dp_encoder)
8797 dpll |= DPLL_SDVO_HIGH_SPEED;
8798
8799 /* compute bitmask from p1 value */
8800 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8801 /* also FPA1 */
8802 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8803
8804 switch (crtc_state->dpll.p2) {
8805 case 5:
8806 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8807 break;
8808 case 7:
8809 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8810 break;
8811 case 10:
8812 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8813 break;
8814 case 14:
8815 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8816 break;
8817 }
8818
8819 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8820 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8821 else
8822 dpll |= PLL_REF_INPUT_DREFCLK;
8823
8824 return dpll | DPLL_VCO_ENABLE;
8825 }
8826
8827 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8828 struct intel_crtc_state *crtc_state)
8829 {
8830 struct drm_device *dev = crtc->base.dev;
8831 intel_clock_t clock, reduced_clock;
8832 u32 dpll = 0, fp = 0, fp2 = 0;
8833 bool ok, has_reduced_clock = false;
8834 bool is_lvds = false;
8835 struct intel_shared_dpll *pll;
8836
8837 memset(&crtc_state->dpll_hw_state, 0,
8838 sizeof(crtc_state->dpll_hw_state));
8839
8840 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8841
8842 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8843 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8844
8845 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8846 &has_reduced_clock, &reduced_clock);
8847 if (!ok && !crtc_state->clock_set) {
8848 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8849 return -EINVAL;
8850 }
8851 /* Compat-code for transition, will disappear. */
8852 if (!crtc_state->clock_set) {
8853 crtc_state->dpll.n = clock.n;
8854 crtc_state->dpll.m1 = clock.m1;
8855 crtc_state->dpll.m2 = clock.m2;
8856 crtc_state->dpll.p1 = clock.p1;
8857 crtc_state->dpll.p2 = clock.p2;
8858 }
8859
8860 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8861 if (crtc_state->has_pch_encoder) {
8862 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8863 if (has_reduced_clock)
8864 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8865
8866 dpll = ironlake_compute_dpll(crtc, crtc_state,
8867 &fp, &reduced_clock,
8868 has_reduced_clock ? &fp2 : NULL);
8869
8870 crtc_state->dpll_hw_state.dpll = dpll;
8871 crtc_state->dpll_hw_state.fp0 = fp;
8872 if (has_reduced_clock)
8873 crtc_state->dpll_hw_state.fp1 = fp2;
8874 else
8875 crtc_state->dpll_hw_state.fp1 = fp;
8876
8877 pll = intel_get_shared_dpll(crtc, crtc_state);
8878 if (pll == NULL) {
8879 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8880 pipe_name(crtc->pipe));
8881 return -EINVAL;
8882 }
8883 }
8884
8885 if (is_lvds && has_reduced_clock)
8886 crtc->lowfreq_avail = true;
8887 else
8888 crtc->lowfreq_avail = false;
8889
8890 return 0;
8891 }
8892
8893 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8894 struct intel_link_m_n *m_n)
8895 {
8896 struct drm_device *dev = crtc->base.dev;
8897 struct drm_i915_private *dev_priv = dev->dev_private;
8898 enum pipe pipe = crtc->pipe;
8899
8900 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8901 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8902 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8903 & ~TU_SIZE_MASK;
8904 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8905 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8906 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8907 }
8908
8909 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8910 enum transcoder transcoder,
8911 struct intel_link_m_n *m_n,
8912 struct intel_link_m_n *m2_n2)
8913 {
8914 struct drm_device *dev = crtc->base.dev;
8915 struct drm_i915_private *dev_priv = dev->dev_private;
8916 enum pipe pipe = crtc->pipe;
8917
8918 if (INTEL_INFO(dev)->gen >= 5) {
8919 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8920 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8921 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8922 & ~TU_SIZE_MASK;
8923 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8924 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8925 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8926 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8927 * gen < 8) and if DRRS is supported (to make sure the
8928 * registers are not unnecessarily read).
8929 */
8930 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8931 crtc->config->has_drrs) {
8932 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8933 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8934 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8935 & ~TU_SIZE_MASK;
8936 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8937 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8938 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8939 }
8940 } else {
8941 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8942 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8943 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8944 & ~TU_SIZE_MASK;
8945 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8946 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8947 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8948 }
8949 }
8950
8951 void intel_dp_get_m_n(struct intel_crtc *crtc,
8952 struct intel_crtc_state *pipe_config)
8953 {
8954 if (pipe_config->has_pch_encoder)
8955 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8956 else
8957 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8958 &pipe_config->dp_m_n,
8959 &pipe_config->dp_m2_n2);
8960 }
8961
8962 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8963 struct intel_crtc_state *pipe_config)
8964 {
8965 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8966 &pipe_config->fdi_m_n, NULL);
8967 }
8968
8969 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8970 struct intel_crtc_state *pipe_config)
8971 {
8972 struct drm_device *dev = crtc->base.dev;
8973 struct drm_i915_private *dev_priv = dev->dev_private;
8974 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8975 uint32_t ps_ctrl = 0;
8976 int id = -1;
8977 int i;
8978
8979 /* find scaler attached to this pipe */
8980 for (i = 0; i < crtc->num_scalers; i++) {
8981 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8982 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8983 id = i;
8984 pipe_config->pch_pfit.enabled = true;
8985 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8986 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8987 break;
8988 }
8989 }
8990
8991 scaler_state->scaler_id = id;
8992 if (id >= 0) {
8993 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8994 } else {
8995 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8996 }
8997 }
8998
8999 static void
9000 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9001 struct intel_initial_plane_config *plane_config)
9002 {
9003 struct drm_device *dev = crtc->base.dev;
9004 struct drm_i915_private *dev_priv = dev->dev_private;
9005 u32 val, base, offset, stride_mult, tiling;
9006 int pipe = crtc->pipe;
9007 int fourcc, pixel_format;
9008 unsigned int aligned_height;
9009 struct drm_framebuffer *fb;
9010 struct intel_framebuffer *intel_fb;
9011
9012 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9013 if (!intel_fb) {
9014 DRM_DEBUG_KMS("failed to alloc fb\n");
9015 return;
9016 }
9017
9018 fb = &intel_fb->base;
9019
9020 val = I915_READ(PLANE_CTL(pipe, 0));
9021 if (!(val & PLANE_CTL_ENABLE))
9022 goto error;
9023
9024 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9025 fourcc = skl_format_to_fourcc(pixel_format,
9026 val & PLANE_CTL_ORDER_RGBX,
9027 val & PLANE_CTL_ALPHA_MASK);
9028 fb->pixel_format = fourcc;
9029 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9030
9031 tiling = val & PLANE_CTL_TILED_MASK;
9032 switch (tiling) {
9033 case PLANE_CTL_TILED_LINEAR:
9034 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9035 break;
9036 case PLANE_CTL_TILED_X:
9037 plane_config->tiling = I915_TILING_X;
9038 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9039 break;
9040 case PLANE_CTL_TILED_Y:
9041 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9042 break;
9043 case PLANE_CTL_TILED_YF:
9044 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9045 break;
9046 default:
9047 MISSING_CASE(tiling);
9048 goto error;
9049 }
9050
9051 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9052 plane_config->base = base;
9053
9054 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9055
9056 val = I915_READ(PLANE_SIZE(pipe, 0));
9057 fb->height = ((val >> 16) & 0xfff) + 1;
9058 fb->width = ((val >> 0) & 0x1fff) + 1;
9059
9060 val = I915_READ(PLANE_STRIDE(pipe, 0));
9061 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9062 fb->pixel_format);
9063 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9064
9065 aligned_height = intel_fb_align_height(dev, fb->height,
9066 fb->pixel_format,
9067 fb->modifier[0]);
9068
9069 plane_config->size = fb->pitches[0] * aligned_height;
9070
9071 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9072 pipe_name(pipe), fb->width, fb->height,
9073 fb->bits_per_pixel, base, fb->pitches[0],
9074 plane_config->size);
9075
9076 plane_config->fb = intel_fb;
9077 return;
9078
9079 error:
9080 kfree(fb);
9081 }
9082
9083 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9084 struct intel_crtc_state *pipe_config)
9085 {
9086 struct drm_device *dev = crtc->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 uint32_t tmp;
9089
9090 tmp = I915_READ(PF_CTL(crtc->pipe));
9091
9092 if (tmp & PF_ENABLE) {
9093 pipe_config->pch_pfit.enabled = true;
9094 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9095 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9096
9097 /* We currently do not free assignements of panel fitters on
9098 * ivb/hsw (since we don't use the higher upscaling modes which
9099 * differentiates them) so just WARN about this case for now. */
9100 if (IS_GEN7(dev)) {
9101 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9102 PF_PIPE_SEL_IVB(crtc->pipe));
9103 }
9104 }
9105 }
9106
9107 static void
9108 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9109 struct intel_initial_plane_config *plane_config)
9110 {
9111 struct drm_device *dev = crtc->base.dev;
9112 struct drm_i915_private *dev_priv = dev->dev_private;
9113 u32 val, base, offset;
9114 int pipe = crtc->pipe;
9115 int fourcc, pixel_format;
9116 unsigned int aligned_height;
9117 struct drm_framebuffer *fb;
9118 struct intel_framebuffer *intel_fb;
9119
9120 val = I915_READ(DSPCNTR(pipe));
9121 if (!(val & DISPLAY_PLANE_ENABLE))
9122 return;
9123
9124 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9125 if (!intel_fb) {
9126 DRM_DEBUG_KMS("failed to alloc fb\n");
9127 return;
9128 }
9129
9130 fb = &intel_fb->base;
9131
9132 if (INTEL_INFO(dev)->gen >= 4) {
9133 if (val & DISPPLANE_TILED) {
9134 plane_config->tiling = I915_TILING_X;
9135 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9136 }
9137 }
9138
9139 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9140 fourcc = i9xx_format_to_fourcc(pixel_format);
9141 fb->pixel_format = fourcc;
9142 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9143
9144 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9145 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9146 offset = I915_READ(DSPOFFSET(pipe));
9147 } else {
9148 if (plane_config->tiling)
9149 offset = I915_READ(DSPTILEOFF(pipe));
9150 else
9151 offset = I915_READ(DSPLINOFF(pipe));
9152 }
9153 plane_config->base = base;
9154
9155 val = I915_READ(PIPESRC(pipe));
9156 fb->width = ((val >> 16) & 0xfff) + 1;
9157 fb->height = ((val >> 0) & 0xfff) + 1;
9158
9159 val = I915_READ(DSPSTRIDE(pipe));
9160 fb->pitches[0] = val & 0xffffffc0;
9161
9162 aligned_height = intel_fb_align_height(dev, fb->height,
9163 fb->pixel_format,
9164 fb->modifier[0]);
9165
9166 plane_config->size = fb->pitches[0] * aligned_height;
9167
9168 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9169 pipe_name(pipe), fb->width, fb->height,
9170 fb->bits_per_pixel, base, fb->pitches[0],
9171 plane_config->size);
9172
9173 plane_config->fb = intel_fb;
9174 }
9175
9176 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9177 struct intel_crtc_state *pipe_config)
9178 {
9179 struct drm_device *dev = crtc->base.dev;
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 uint32_t tmp;
9182
9183 if (!intel_display_power_is_enabled(dev_priv,
9184 POWER_DOMAIN_PIPE(crtc->pipe)))
9185 return false;
9186
9187 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9188 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9189
9190 tmp = I915_READ(PIPECONF(crtc->pipe));
9191 if (!(tmp & PIPECONF_ENABLE))
9192 return false;
9193
9194 switch (tmp & PIPECONF_BPC_MASK) {
9195 case PIPECONF_6BPC:
9196 pipe_config->pipe_bpp = 18;
9197 break;
9198 case PIPECONF_8BPC:
9199 pipe_config->pipe_bpp = 24;
9200 break;
9201 case PIPECONF_10BPC:
9202 pipe_config->pipe_bpp = 30;
9203 break;
9204 case PIPECONF_12BPC:
9205 pipe_config->pipe_bpp = 36;
9206 break;
9207 default:
9208 break;
9209 }
9210
9211 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9212 pipe_config->limited_color_range = true;
9213
9214 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9215 struct intel_shared_dpll *pll;
9216
9217 pipe_config->has_pch_encoder = true;
9218
9219 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9220 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9221 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9222
9223 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9224
9225 if (HAS_PCH_IBX(dev_priv->dev)) {
9226 pipe_config->shared_dpll =
9227 (enum intel_dpll_id) crtc->pipe;
9228 } else {
9229 tmp = I915_READ(PCH_DPLL_SEL);
9230 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9231 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9232 else
9233 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9234 }
9235
9236 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9237
9238 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9239 &pipe_config->dpll_hw_state));
9240
9241 tmp = pipe_config->dpll_hw_state.dpll;
9242 pipe_config->pixel_multiplier =
9243 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9244 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9245
9246 ironlake_pch_clock_get(crtc, pipe_config);
9247 } else {
9248 pipe_config->pixel_multiplier = 1;
9249 }
9250
9251 intel_get_pipe_timings(crtc, pipe_config);
9252
9253 ironlake_get_pfit_config(crtc, pipe_config);
9254
9255 return true;
9256 }
9257
9258 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9259 {
9260 struct drm_device *dev = dev_priv->dev;
9261 struct intel_crtc *crtc;
9262
9263 for_each_intel_crtc(dev, crtc)
9264 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9265 pipe_name(crtc->pipe));
9266
9267 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9268 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9269 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9270 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9271 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9272 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9273 "CPU PWM1 enabled\n");
9274 if (IS_HASWELL(dev))
9275 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9276 "CPU PWM2 enabled\n");
9277 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9278 "PCH PWM1 enabled\n");
9279 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9280 "Utility pin enabled\n");
9281 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9282
9283 /*
9284 * In theory we can still leave IRQs enabled, as long as only the HPD
9285 * interrupts remain enabled. We used to check for that, but since it's
9286 * gen-specific and since we only disable LCPLL after we fully disable
9287 * the interrupts, the check below should be enough.
9288 */
9289 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9290 }
9291
9292 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9293 {
9294 struct drm_device *dev = dev_priv->dev;
9295
9296 if (IS_HASWELL(dev))
9297 return I915_READ(D_COMP_HSW);
9298 else
9299 return I915_READ(D_COMP_BDW);
9300 }
9301
9302 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9303 {
9304 struct drm_device *dev = dev_priv->dev;
9305
9306 if (IS_HASWELL(dev)) {
9307 mutex_lock(&dev_priv->rps.hw_lock);
9308 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9309 val))
9310 DRM_ERROR("Failed to write to D_COMP\n");
9311 mutex_unlock(&dev_priv->rps.hw_lock);
9312 } else {
9313 I915_WRITE(D_COMP_BDW, val);
9314 POSTING_READ(D_COMP_BDW);
9315 }
9316 }
9317
9318 /*
9319 * This function implements pieces of two sequences from BSpec:
9320 * - Sequence for display software to disable LCPLL
9321 * - Sequence for display software to allow package C8+
9322 * The steps implemented here are just the steps that actually touch the LCPLL
9323 * register. Callers should take care of disabling all the display engine
9324 * functions, doing the mode unset, fixing interrupts, etc.
9325 */
9326 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9327 bool switch_to_fclk, bool allow_power_down)
9328 {
9329 uint32_t val;
9330
9331 assert_can_disable_lcpll(dev_priv);
9332
9333 val = I915_READ(LCPLL_CTL);
9334
9335 if (switch_to_fclk) {
9336 val |= LCPLL_CD_SOURCE_FCLK;
9337 I915_WRITE(LCPLL_CTL, val);
9338
9339 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9340 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9341 DRM_ERROR("Switching to FCLK failed\n");
9342
9343 val = I915_READ(LCPLL_CTL);
9344 }
9345
9346 val |= LCPLL_PLL_DISABLE;
9347 I915_WRITE(LCPLL_CTL, val);
9348 POSTING_READ(LCPLL_CTL);
9349
9350 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9351 DRM_ERROR("LCPLL still locked\n");
9352
9353 val = hsw_read_dcomp(dev_priv);
9354 val |= D_COMP_COMP_DISABLE;
9355 hsw_write_dcomp(dev_priv, val);
9356 ndelay(100);
9357
9358 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9359 1))
9360 DRM_ERROR("D_COMP RCOMP still in progress\n");
9361
9362 if (allow_power_down) {
9363 val = I915_READ(LCPLL_CTL);
9364 val |= LCPLL_POWER_DOWN_ALLOW;
9365 I915_WRITE(LCPLL_CTL, val);
9366 POSTING_READ(LCPLL_CTL);
9367 }
9368 }
9369
9370 /*
9371 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9372 * source.
9373 */
9374 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9375 {
9376 uint32_t val;
9377
9378 val = I915_READ(LCPLL_CTL);
9379
9380 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9381 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9382 return;
9383
9384 /*
9385 * Make sure we're not on PC8 state before disabling PC8, otherwise
9386 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9387 */
9388 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9389
9390 if (val & LCPLL_POWER_DOWN_ALLOW) {
9391 val &= ~LCPLL_POWER_DOWN_ALLOW;
9392 I915_WRITE(LCPLL_CTL, val);
9393 POSTING_READ(LCPLL_CTL);
9394 }
9395
9396 val = hsw_read_dcomp(dev_priv);
9397 val |= D_COMP_COMP_FORCE;
9398 val &= ~D_COMP_COMP_DISABLE;
9399 hsw_write_dcomp(dev_priv, val);
9400
9401 val = I915_READ(LCPLL_CTL);
9402 val &= ~LCPLL_PLL_DISABLE;
9403 I915_WRITE(LCPLL_CTL, val);
9404
9405 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9406 DRM_ERROR("LCPLL not locked yet\n");
9407
9408 if (val & LCPLL_CD_SOURCE_FCLK) {
9409 val = I915_READ(LCPLL_CTL);
9410 val &= ~LCPLL_CD_SOURCE_FCLK;
9411 I915_WRITE(LCPLL_CTL, val);
9412
9413 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9414 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9415 DRM_ERROR("Switching back to LCPLL failed\n");
9416 }
9417
9418 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9419 intel_update_cdclk(dev_priv->dev);
9420 }
9421
9422 /*
9423 * Package states C8 and deeper are really deep PC states that can only be
9424 * reached when all the devices on the system allow it, so even if the graphics
9425 * device allows PC8+, it doesn't mean the system will actually get to these
9426 * states. Our driver only allows PC8+ when going into runtime PM.
9427 *
9428 * The requirements for PC8+ are that all the outputs are disabled, the power
9429 * well is disabled and most interrupts are disabled, and these are also
9430 * requirements for runtime PM. When these conditions are met, we manually do
9431 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9432 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9433 * hang the machine.
9434 *
9435 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9436 * the state of some registers, so when we come back from PC8+ we need to
9437 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9438 * need to take care of the registers kept by RC6. Notice that this happens even
9439 * if we don't put the device in PCI D3 state (which is what currently happens
9440 * because of the runtime PM support).
9441 *
9442 * For more, read "Display Sequences for Package C8" on the hardware
9443 * documentation.
9444 */
9445 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9446 {
9447 struct drm_device *dev = dev_priv->dev;
9448 uint32_t val;
9449
9450 DRM_DEBUG_KMS("Enabling package C8+\n");
9451
9452 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9453 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9454 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9455 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9456 }
9457
9458 lpt_disable_clkout_dp(dev);
9459 hsw_disable_lcpll(dev_priv, true, true);
9460 }
9461
9462 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9463 {
9464 struct drm_device *dev = dev_priv->dev;
9465 uint32_t val;
9466
9467 DRM_DEBUG_KMS("Disabling package C8+\n");
9468
9469 hsw_restore_lcpll(dev_priv);
9470 lpt_init_pch_refclk(dev);
9471
9472 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9473 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9474 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9475 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9476 }
9477
9478 intel_prepare_ddi(dev);
9479 }
9480
9481 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9482 {
9483 struct drm_device *dev = old_state->dev;
9484 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9485
9486 broxton_set_cdclk(dev, req_cdclk);
9487 }
9488
9489 /* compute the max rate for new configuration */
9490 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9491 {
9492 struct intel_crtc *intel_crtc;
9493 struct intel_crtc_state *crtc_state;
9494 int max_pixel_rate = 0;
9495
9496 for_each_intel_crtc(state->dev, intel_crtc) {
9497 int pixel_rate;
9498
9499 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9500 if (IS_ERR(crtc_state))
9501 return PTR_ERR(crtc_state);
9502
9503 if (!crtc_state->base.enable)
9504 continue;
9505
9506 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9507
9508 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9509 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9510 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9511
9512 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9513 }
9514
9515 return max_pixel_rate;
9516 }
9517
9518 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9519 {
9520 struct drm_i915_private *dev_priv = dev->dev_private;
9521 uint32_t val, data;
9522 int ret;
9523
9524 if (WARN((I915_READ(LCPLL_CTL) &
9525 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9526 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9527 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9528 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9529 "trying to change cdclk frequency with cdclk not enabled\n"))
9530 return;
9531
9532 mutex_lock(&dev_priv->rps.hw_lock);
9533 ret = sandybridge_pcode_write(dev_priv,
9534 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9535 mutex_unlock(&dev_priv->rps.hw_lock);
9536 if (ret) {
9537 DRM_ERROR("failed to inform pcode about cdclk change\n");
9538 return;
9539 }
9540
9541 val = I915_READ(LCPLL_CTL);
9542 val |= LCPLL_CD_SOURCE_FCLK;
9543 I915_WRITE(LCPLL_CTL, val);
9544
9545 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9546 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9547 DRM_ERROR("Switching to FCLK failed\n");
9548
9549 val = I915_READ(LCPLL_CTL);
9550 val &= ~LCPLL_CLK_FREQ_MASK;
9551
9552 switch (cdclk) {
9553 case 450000:
9554 val |= LCPLL_CLK_FREQ_450;
9555 data = 0;
9556 break;
9557 case 540000:
9558 val |= LCPLL_CLK_FREQ_54O_BDW;
9559 data = 1;
9560 break;
9561 case 337500:
9562 val |= LCPLL_CLK_FREQ_337_5_BDW;
9563 data = 2;
9564 break;
9565 case 675000:
9566 val |= LCPLL_CLK_FREQ_675_BDW;
9567 data = 3;
9568 break;
9569 default:
9570 WARN(1, "invalid cdclk frequency\n");
9571 return;
9572 }
9573
9574 I915_WRITE(LCPLL_CTL, val);
9575
9576 val = I915_READ(LCPLL_CTL);
9577 val &= ~LCPLL_CD_SOURCE_FCLK;
9578 I915_WRITE(LCPLL_CTL, val);
9579
9580 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9581 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9582 DRM_ERROR("Switching back to LCPLL failed\n");
9583
9584 mutex_lock(&dev_priv->rps.hw_lock);
9585 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9586 mutex_unlock(&dev_priv->rps.hw_lock);
9587
9588 intel_update_cdclk(dev);
9589
9590 WARN(cdclk != dev_priv->cdclk_freq,
9591 "cdclk requested %d kHz but got %d kHz\n",
9592 cdclk, dev_priv->cdclk_freq);
9593 }
9594
9595 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9596 {
9597 struct drm_i915_private *dev_priv = to_i915(state->dev);
9598 int max_pixclk = ilk_max_pixel_rate(state);
9599 int cdclk;
9600
9601 /*
9602 * FIXME should also account for plane ratio
9603 * once 64bpp pixel formats are supported.
9604 */
9605 if (max_pixclk > 540000)
9606 cdclk = 675000;
9607 else if (max_pixclk > 450000)
9608 cdclk = 540000;
9609 else if (max_pixclk > 337500)
9610 cdclk = 450000;
9611 else
9612 cdclk = 337500;
9613
9614 /*
9615 * FIXME move the cdclk caclulation to
9616 * compute_config() so we can fail gracegully.
9617 */
9618 if (cdclk > dev_priv->max_cdclk_freq) {
9619 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9620 cdclk, dev_priv->max_cdclk_freq);
9621 cdclk = dev_priv->max_cdclk_freq;
9622 }
9623
9624 to_intel_atomic_state(state)->cdclk = cdclk;
9625
9626 return 0;
9627 }
9628
9629 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9630 {
9631 struct drm_device *dev = old_state->dev;
9632 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9633
9634 broadwell_set_cdclk(dev, req_cdclk);
9635 }
9636
9637 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9638 struct intel_crtc_state *crtc_state)
9639 {
9640 if (!intel_ddi_pll_select(crtc, crtc_state))
9641 return -EINVAL;
9642
9643 crtc->lowfreq_avail = false;
9644
9645 return 0;
9646 }
9647
9648 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9649 enum port port,
9650 struct intel_crtc_state *pipe_config)
9651 {
9652 switch (port) {
9653 case PORT_A:
9654 pipe_config->ddi_pll_sel = SKL_DPLL0;
9655 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9656 break;
9657 case PORT_B:
9658 pipe_config->ddi_pll_sel = SKL_DPLL1;
9659 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9660 break;
9661 case PORT_C:
9662 pipe_config->ddi_pll_sel = SKL_DPLL2;
9663 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9664 break;
9665 default:
9666 DRM_ERROR("Incorrect port type\n");
9667 }
9668 }
9669
9670 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9671 enum port port,
9672 struct intel_crtc_state *pipe_config)
9673 {
9674 u32 temp, dpll_ctl1;
9675
9676 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9677 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9678
9679 switch (pipe_config->ddi_pll_sel) {
9680 case SKL_DPLL0:
9681 /*
9682 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9683 * of the shared DPLL framework and thus needs to be read out
9684 * separately
9685 */
9686 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9687 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9688 break;
9689 case SKL_DPLL1:
9690 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9691 break;
9692 case SKL_DPLL2:
9693 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9694 break;
9695 case SKL_DPLL3:
9696 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9697 break;
9698 }
9699 }
9700
9701 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9702 enum port port,
9703 struct intel_crtc_state *pipe_config)
9704 {
9705 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9706
9707 switch (pipe_config->ddi_pll_sel) {
9708 case PORT_CLK_SEL_WRPLL1:
9709 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9710 break;
9711 case PORT_CLK_SEL_WRPLL2:
9712 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9713 break;
9714 }
9715 }
9716
9717 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9718 struct intel_crtc_state *pipe_config)
9719 {
9720 struct drm_device *dev = crtc->base.dev;
9721 struct drm_i915_private *dev_priv = dev->dev_private;
9722 struct intel_shared_dpll *pll;
9723 enum port port;
9724 uint32_t tmp;
9725
9726 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9727
9728 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9729
9730 if (IS_SKYLAKE(dev))
9731 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9732 else if (IS_BROXTON(dev))
9733 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9734 else
9735 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9736
9737 if (pipe_config->shared_dpll >= 0) {
9738 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9739
9740 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9741 &pipe_config->dpll_hw_state));
9742 }
9743
9744 /*
9745 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9746 * DDI E. So just check whether this pipe is wired to DDI E and whether
9747 * the PCH transcoder is on.
9748 */
9749 if (INTEL_INFO(dev)->gen < 9 &&
9750 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9751 pipe_config->has_pch_encoder = true;
9752
9753 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9754 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9755 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9756
9757 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9758 }
9759 }
9760
9761 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9762 struct intel_crtc_state *pipe_config)
9763 {
9764 struct drm_device *dev = crtc->base.dev;
9765 struct drm_i915_private *dev_priv = dev->dev_private;
9766 enum intel_display_power_domain pfit_domain;
9767 uint32_t tmp;
9768
9769 if (!intel_display_power_is_enabled(dev_priv,
9770 POWER_DOMAIN_PIPE(crtc->pipe)))
9771 return false;
9772
9773 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9774 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9775
9776 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9777 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9778 enum pipe trans_edp_pipe;
9779 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9780 default:
9781 WARN(1, "unknown pipe linked to edp transcoder\n");
9782 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9783 case TRANS_DDI_EDP_INPUT_A_ON:
9784 trans_edp_pipe = PIPE_A;
9785 break;
9786 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9787 trans_edp_pipe = PIPE_B;
9788 break;
9789 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9790 trans_edp_pipe = PIPE_C;
9791 break;
9792 }
9793
9794 if (trans_edp_pipe == crtc->pipe)
9795 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9796 }
9797
9798 if (!intel_display_power_is_enabled(dev_priv,
9799 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9800 return false;
9801
9802 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9803 if (!(tmp & PIPECONF_ENABLE))
9804 return false;
9805
9806 haswell_get_ddi_port_state(crtc, pipe_config);
9807
9808 intel_get_pipe_timings(crtc, pipe_config);
9809
9810 if (INTEL_INFO(dev)->gen >= 9) {
9811 skl_init_scalers(dev, crtc, pipe_config);
9812 }
9813
9814 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9815
9816 if (INTEL_INFO(dev)->gen >= 9) {
9817 pipe_config->scaler_state.scaler_id = -1;
9818 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9819 }
9820
9821 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9822 if (INTEL_INFO(dev)->gen == 9)
9823 skylake_get_pfit_config(crtc, pipe_config);
9824 else if (INTEL_INFO(dev)->gen < 9)
9825 ironlake_get_pfit_config(crtc, pipe_config);
9826 else
9827 MISSING_CASE(INTEL_INFO(dev)->gen);
9828 }
9829
9830 if (IS_HASWELL(dev))
9831 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9832 (I915_READ(IPS_CTL) & IPS_ENABLE);
9833
9834 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9835 pipe_config->pixel_multiplier =
9836 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9837 } else {
9838 pipe_config->pixel_multiplier = 1;
9839 }
9840
9841 return true;
9842 }
9843
9844 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9845 {
9846 struct drm_device *dev = crtc->dev;
9847 struct drm_i915_private *dev_priv = dev->dev_private;
9848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9849 uint32_t cntl = 0, size = 0;
9850
9851 if (base) {
9852 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9853 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9854 unsigned int stride = roundup_pow_of_two(width) * 4;
9855
9856 switch (stride) {
9857 default:
9858 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9859 width, stride);
9860 stride = 256;
9861 /* fallthrough */
9862 case 256:
9863 case 512:
9864 case 1024:
9865 case 2048:
9866 break;
9867 }
9868
9869 cntl |= CURSOR_ENABLE |
9870 CURSOR_GAMMA_ENABLE |
9871 CURSOR_FORMAT_ARGB |
9872 CURSOR_STRIDE(stride);
9873
9874 size = (height << 12) | width;
9875 }
9876
9877 if (intel_crtc->cursor_cntl != 0 &&
9878 (intel_crtc->cursor_base != base ||
9879 intel_crtc->cursor_size != size ||
9880 intel_crtc->cursor_cntl != cntl)) {
9881 /* On these chipsets we can only modify the base/size/stride
9882 * whilst the cursor is disabled.
9883 */
9884 I915_WRITE(_CURACNTR, 0);
9885 POSTING_READ(_CURACNTR);
9886 intel_crtc->cursor_cntl = 0;
9887 }
9888
9889 if (intel_crtc->cursor_base != base) {
9890 I915_WRITE(_CURABASE, base);
9891 intel_crtc->cursor_base = base;
9892 }
9893
9894 if (intel_crtc->cursor_size != size) {
9895 I915_WRITE(CURSIZE, size);
9896 intel_crtc->cursor_size = size;
9897 }
9898
9899 if (intel_crtc->cursor_cntl != cntl) {
9900 I915_WRITE(_CURACNTR, cntl);
9901 POSTING_READ(_CURACNTR);
9902 intel_crtc->cursor_cntl = cntl;
9903 }
9904 }
9905
9906 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9907 {
9908 struct drm_device *dev = crtc->dev;
9909 struct drm_i915_private *dev_priv = dev->dev_private;
9910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9911 int pipe = intel_crtc->pipe;
9912 uint32_t cntl;
9913
9914 cntl = 0;
9915 if (base) {
9916 cntl = MCURSOR_GAMMA_ENABLE;
9917 switch (intel_crtc->base.cursor->state->crtc_w) {
9918 case 64:
9919 cntl |= CURSOR_MODE_64_ARGB_AX;
9920 break;
9921 case 128:
9922 cntl |= CURSOR_MODE_128_ARGB_AX;
9923 break;
9924 case 256:
9925 cntl |= CURSOR_MODE_256_ARGB_AX;
9926 break;
9927 default:
9928 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9929 return;
9930 }
9931 cntl |= pipe << 28; /* Connect to correct pipe */
9932
9933 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9934 cntl |= CURSOR_PIPE_CSC_ENABLE;
9935 }
9936
9937 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9938 cntl |= CURSOR_ROTATE_180;
9939
9940 if (intel_crtc->cursor_cntl != cntl) {
9941 I915_WRITE(CURCNTR(pipe), cntl);
9942 POSTING_READ(CURCNTR(pipe));
9943 intel_crtc->cursor_cntl = cntl;
9944 }
9945
9946 /* and commit changes on next vblank */
9947 I915_WRITE(CURBASE(pipe), base);
9948 POSTING_READ(CURBASE(pipe));
9949
9950 intel_crtc->cursor_base = base;
9951 }
9952
9953 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9954 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9955 bool on)
9956 {
9957 struct drm_device *dev = crtc->dev;
9958 struct drm_i915_private *dev_priv = dev->dev_private;
9959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9960 int pipe = intel_crtc->pipe;
9961 int x = crtc->cursor_x;
9962 int y = crtc->cursor_y;
9963 u32 base = 0, pos = 0;
9964
9965 if (on)
9966 base = intel_crtc->cursor_addr;
9967
9968 if (x >= intel_crtc->config->pipe_src_w)
9969 base = 0;
9970
9971 if (y >= intel_crtc->config->pipe_src_h)
9972 base = 0;
9973
9974 if (x < 0) {
9975 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9976 base = 0;
9977
9978 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9979 x = -x;
9980 }
9981 pos |= x << CURSOR_X_SHIFT;
9982
9983 if (y < 0) {
9984 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9985 base = 0;
9986
9987 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9988 y = -y;
9989 }
9990 pos |= y << CURSOR_Y_SHIFT;
9991
9992 if (base == 0 && intel_crtc->cursor_base == 0)
9993 return;
9994
9995 I915_WRITE(CURPOS(pipe), pos);
9996
9997 /* ILK+ do this automagically */
9998 if (HAS_GMCH_DISPLAY(dev) &&
9999 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10000 base += (intel_crtc->base.cursor->state->crtc_h *
10001 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10002 }
10003
10004 if (IS_845G(dev) || IS_I865G(dev))
10005 i845_update_cursor(crtc, base);
10006 else
10007 i9xx_update_cursor(crtc, base);
10008 }
10009
10010 static bool cursor_size_ok(struct drm_device *dev,
10011 uint32_t width, uint32_t height)
10012 {
10013 if (width == 0 || height == 0)
10014 return false;
10015
10016 /*
10017 * 845g/865g are special in that they are only limited by
10018 * the width of their cursors, the height is arbitrary up to
10019 * the precision of the register. Everything else requires
10020 * square cursors, limited to a few power-of-two sizes.
10021 */
10022 if (IS_845G(dev) || IS_I865G(dev)) {
10023 if ((width & 63) != 0)
10024 return false;
10025
10026 if (width > (IS_845G(dev) ? 64 : 512))
10027 return false;
10028
10029 if (height > 1023)
10030 return false;
10031 } else {
10032 switch (width | height) {
10033 case 256:
10034 case 128:
10035 if (IS_GEN2(dev))
10036 return false;
10037 case 64:
10038 break;
10039 default:
10040 return false;
10041 }
10042 }
10043
10044 return true;
10045 }
10046
10047 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10048 u16 *blue, uint32_t start, uint32_t size)
10049 {
10050 int end = (start + size > 256) ? 256 : start + size, i;
10051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10052
10053 for (i = start; i < end; i++) {
10054 intel_crtc->lut_r[i] = red[i] >> 8;
10055 intel_crtc->lut_g[i] = green[i] >> 8;
10056 intel_crtc->lut_b[i] = blue[i] >> 8;
10057 }
10058
10059 intel_crtc_load_lut(crtc);
10060 }
10061
10062 /* VESA 640x480x72Hz mode to set on the pipe */
10063 static struct drm_display_mode load_detect_mode = {
10064 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10065 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10066 };
10067
10068 struct drm_framebuffer *
10069 __intel_framebuffer_create(struct drm_device *dev,
10070 struct drm_mode_fb_cmd2 *mode_cmd,
10071 struct drm_i915_gem_object *obj)
10072 {
10073 struct intel_framebuffer *intel_fb;
10074 int ret;
10075
10076 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10077 if (!intel_fb) {
10078 drm_gem_object_unreference(&obj->base);
10079 return ERR_PTR(-ENOMEM);
10080 }
10081
10082 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10083 if (ret)
10084 goto err;
10085
10086 return &intel_fb->base;
10087 err:
10088 drm_gem_object_unreference(&obj->base);
10089 kfree(intel_fb);
10090
10091 return ERR_PTR(ret);
10092 }
10093
10094 static struct drm_framebuffer *
10095 intel_framebuffer_create(struct drm_device *dev,
10096 struct drm_mode_fb_cmd2 *mode_cmd,
10097 struct drm_i915_gem_object *obj)
10098 {
10099 struct drm_framebuffer *fb;
10100 int ret;
10101
10102 ret = i915_mutex_lock_interruptible(dev);
10103 if (ret)
10104 return ERR_PTR(ret);
10105 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10106 mutex_unlock(&dev->struct_mutex);
10107
10108 return fb;
10109 }
10110
10111 static u32
10112 intel_framebuffer_pitch_for_width(int width, int bpp)
10113 {
10114 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10115 return ALIGN(pitch, 64);
10116 }
10117
10118 static u32
10119 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10120 {
10121 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10122 return PAGE_ALIGN(pitch * mode->vdisplay);
10123 }
10124
10125 static struct drm_framebuffer *
10126 intel_framebuffer_create_for_mode(struct drm_device *dev,
10127 struct drm_display_mode *mode,
10128 int depth, int bpp)
10129 {
10130 struct drm_i915_gem_object *obj;
10131 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10132
10133 obj = i915_gem_alloc_object(dev,
10134 intel_framebuffer_size_for_mode(mode, bpp));
10135 if (obj == NULL)
10136 return ERR_PTR(-ENOMEM);
10137
10138 mode_cmd.width = mode->hdisplay;
10139 mode_cmd.height = mode->vdisplay;
10140 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10141 bpp);
10142 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10143
10144 return intel_framebuffer_create(dev, &mode_cmd, obj);
10145 }
10146
10147 static struct drm_framebuffer *
10148 mode_fits_in_fbdev(struct drm_device *dev,
10149 struct drm_display_mode *mode)
10150 {
10151 #ifdef CONFIG_DRM_I915_FBDEV
10152 struct drm_i915_private *dev_priv = dev->dev_private;
10153 struct drm_i915_gem_object *obj;
10154 struct drm_framebuffer *fb;
10155
10156 if (!dev_priv->fbdev)
10157 return NULL;
10158
10159 if (!dev_priv->fbdev->fb)
10160 return NULL;
10161
10162 obj = dev_priv->fbdev->fb->obj;
10163 BUG_ON(!obj);
10164
10165 fb = &dev_priv->fbdev->fb->base;
10166 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10167 fb->bits_per_pixel))
10168 return NULL;
10169
10170 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10171 return NULL;
10172
10173 return fb;
10174 #else
10175 return NULL;
10176 #endif
10177 }
10178
10179 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10180 struct drm_crtc *crtc,
10181 struct drm_display_mode *mode,
10182 struct drm_framebuffer *fb,
10183 int x, int y)
10184 {
10185 struct drm_plane_state *plane_state;
10186 int hdisplay, vdisplay;
10187 int ret;
10188
10189 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10190 if (IS_ERR(plane_state))
10191 return PTR_ERR(plane_state);
10192
10193 if (mode)
10194 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10195 else
10196 hdisplay = vdisplay = 0;
10197
10198 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10199 if (ret)
10200 return ret;
10201 drm_atomic_set_fb_for_plane(plane_state, fb);
10202 plane_state->crtc_x = 0;
10203 plane_state->crtc_y = 0;
10204 plane_state->crtc_w = hdisplay;
10205 plane_state->crtc_h = vdisplay;
10206 plane_state->src_x = x << 16;
10207 plane_state->src_y = y << 16;
10208 plane_state->src_w = hdisplay << 16;
10209 plane_state->src_h = vdisplay << 16;
10210
10211 return 0;
10212 }
10213
10214 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10215 struct drm_display_mode *mode,
10216 struct intel_load_detect_pipe *old,
10217 struct drm_modeset_acquire_ctx *ctx)
10218 {
10219 struct intel_crtc *intel_crtc;
10220 struct intel_encoder *intel_encoder =
10221 intel_attached_encoder(connector);
10222 struct drm_crtc *possible_crtc;
10223 struct drm_encoder *encoder = &intel_encoder->base;
10224 struct drm_crtc *crtc = NULL;
10225 struct drm_device *dev = encoder->dev;
10226 struct drm_framebuffer *fb;
10227 struct drm_mode_config *config = &dev->mode_config;
10228 struct drm_atomic_state *state = NULL;
10229 struct drm_connector_state *connector_state;
10230 struct intel_crtc_state *crtc_state;
10231 int ret, i = -1;
10232
10233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10234 connector->base.id, connector->name,
10235 encoder->base.id, encoder->name);
10236
10237 retry:
10238 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10239 if (ret)
10240 goto fail_unlock;
10241
10242 /*
10243 * Algorithm gets a little messy:
10244 *
10245 * - if the connector already has an assigned crtc, use it (but make
10246 * sure it's on first)
10247 *
10248 * - try to find the first unused crtc that can drive this connector,
10249 * and use that if we find one
10250 */
10251
10252 /* See if we already have a CRTC for this connector */
10253 if (encoder->crtc) {
10254 crtc = encoder->crtc;
10255
10256 ret = drm_modeset_lock(&crtc->mutex, ctx);
10257 if (ret)
10258 goto fail_unlock;
10259 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10260 if (ret)
10261 goto fail_unlock;
10262
10263 old->dpms_mode = connector->dpms;
10264 old->load_detect_temp = false;
10265
10266 /* Make sure the crtc and connector are running */
10267 if (connector->dpms != DRM_MODE_DPMS_ON)
10268 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10269
10270 return true;
10271 }
10272
10273 /* Find an unused one (if possible) */
10274 for_each_crtc(dev, possible_crtc) {
10275 i++;
10276 if (!(encoder->possible_crtcs & (1 << i)))
10277 continue;
10278 if (possible_crtc->state->enable)
10279 continue;
10280 /* This can occur when applying the pipe A quirk on resume. */
10281 if (to_intel_crtc(possible_crtc)->new_enabled)
10282 continue;
10283
10284 crtc = possible_crtc;
10285 break;
10286 }
10287
10288 /*
10289 * If we didn't find an unused CRTC, don't use any.
10290 */
10291 if (!crtc) {
10292 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10293 goto fail_unlock;
10294 }
10295
10296 ret = drm_modeset_lock(&crtc->mutex, ctx);
10297 if (ret)
10298 goto fail_unlock;
10299 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10300 if (ret)
10301 goto fail_unlock;
10302 intel_encoder->new_crtc = to_intel_crtc(crtc);
10303 to_intel_connector(connector)->new_encoder = intel_encoder;
10304
10305 intel_crtc = to_intel_crtc(crtc);
10306 intel_crtc->new_enabled = true;
10307 old->dpms_mode = connector->dpms;
10308 old->load_detect_temp = true;
10309 old->release_fb = NULL;
10310
10311 state = drm_atomic_state_alloc(dev);
10312 if (!state)
10313 return false;
10314
10315 state->acquire_ctx = ctx;
10316
10317 connector_state = drm_atomic_get_connector_state(state, connector);
10318 if (IS_ERR(connector_state)) {
10319 ret = PTR_ERR(connector_state);
10320 goto fail;
10321 }
10322
10323 connector_state->crtc = crtc;
10324 connector_state->best_encoder = &intel_encoder->base;
10325
10326 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10327 if (IS_ERR(crtc_state)) {
10328 ret = PTR_ERR(crtc_state);
10329 goto fail;
10330 }
10331
10332 crtc_state->base.active = crtc_state->base.enable = true;
10333
10334 if (!mode)
10335 mode = &load_detect_mode;
10336
10337 /* We need a framebuffer large enough to accommodate all accesses
10338 * that the plane may generate whilst we perform load detection.
10339 * We can not rely on the fbcon either being present (we get called
10340 * during its initialisation to detect all boot displays, or it may
10341 * not even exist) or that it is large enough to satisfy the
10342 * requested mode.
10343 */
10344 fb = mode_fits_in_fbdev(dev, mode);
10345 if (fb == NULL) {
10346 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10347 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10348 old->release_fb = fb;
10349 } else
10350 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10351 if (IS_ERR(fb)) {
10352 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10353 goto fail;
10354 }
10355
10356 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10357 if (ret)
10358 goto fail;
10359
10360 drm_mode_copy(&crtc_state->base.mode, mode);
10361
10362 if (intel_set_mode(state)) {
10363 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10364 if (old->release_fb)
10365 old->release_fb->funcs->destroy(old->release_fb);
10366 goto fail;
10367 }
10368 crtc->primary->crtc = crtc;
10369
10370 /* let the connector get through one full cycle before testing */
10371 intel_wait_for_vblank(dev, intel_crtc->pipe);
10372 return true;
10373
10374 fail:
10375 intel_crtc->new_enabled = crtc->state->enable;
10376 fail_unlock:
10377 drm_atomic_state_free(state);
10378 state = NULL;
10379
10380 if (ret == -EDEADLK) {
10381 drm_modeset_backoff(ctx);
10382 goto retry;
10383 }
10384
10385 return false;
10386 }
10387
10388 void intel_release_load_detect_pipe(struct drm_connector *connector,
10389 struct intel_load_detect_pipe *old,
10390 struct drm_modeset_acquire_ctx *ctx)
10391 {
10392 struct drm_device *dev = connector->dev;
10393 struct intel_encoder *intel_encoder =
10394 intel_attached_encoder(connector);
10395 struct drm_encoder *encoder = &intel_encoder->base;
10396 struct drm_crtc *crtc = encoder->crtc;
10397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10398 struct drm_atomic_state *state;
10399 struct drm_connector_state *connector_state;
10400 struct intel_crtc_state *crtc_state;
10401 int ret;
10402
10403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10404 connector->base.id, connector->name,
10405 encoder->base.id, encoder->name);
10406
10407 if (old->load_detect_temp) {
10408 state = drm_atomic_state_alloc(dev);
10409 if (!state)
10410 goto fail;
10411
10412 state->acquire_ctx = ctx;
10413
10414 connector_state = drm_atomic_get_connector_state(state, connector);
10415 if (IS_ERR(connector_state))
10416 goto fail;
10417
10418 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10419 if (IS_ERR(crtc_state))
10420 goto fail;
10421
10422 to_intel_connector(connector)->new_encoder = NULL;
10423 intel_encoder->new_crtc = NULL;
10424 intel_crtc->new_enabled = false;
10425
10426 connector_state->best_encoder = NULL;
10427 connector_state->crtc = NULL;
10428
10429 crtc_state->base.enable = crtc_state->base.active = false;
10430
10431 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10432 0, 0);
10433 if (ret)
10434 goto fail;
10435
10436 ret = intel_set_mode(state);
10437 if (ret)
10438 goto fail;
10439
10440 if (old->release_fb) {
10441 drm_framebuffer_unregister_private(old->release_fb);
10442 drm_framebuffer_unreference(old->release_fb);
10443 }
10444
10445 return;
10446 }
10447
10448 /* Switch crtc and encoder back off if necessary */
10449 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10450 connector->funcs->dpms(connector, old->dpms_mode);
10451
10452 return;
10453 fail:
10454 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10455 drm_atomic_state_free(state);
10456 }
10457
10458 static int i9xx_pll_refclk(struct drm_device *dev,
10459 const struct intel_crtc_state *pipe_config)
10460 {
10461 struct drm_i915_private *dev_priv = dev->dev_private;
10462 u32 dpll = pipe_config->dpll_hw_state.dpll;
10463
10464 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10465 return dev_priv->vbt.lvds_ssc_freq;
10466 else if (HAS_PCH_SPLIT(dev))
10467 return 120000;
10468 else if (!IS_GEN2(dev))
10469 return 96000;
10470 else
10471 return 48000;
10472 }
10473
10474 /* Returns the clock of the currently programmed mode of the given pipe. */
10475 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10476 struct intel_crtc_state *pipe_config)
10477 {
10478 struct drm_device *dev = crtc->base.dev;
10479 struct drm_i915_private *dev_priv = dev->dev_private;
10480 int pipe = pipe_config->cpu_transcoder;
10481 u32 dpll = pipe_config->dpll_hw_state.dpll;
10482 u32 fp;
10483 intel_clock_t clock;
10484 int port_clock;
10485 int refclk = i9xx_pll_refclk(dev, pipe_config);
10486
10487 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10488 fp = pipe_config->dpll_hw_state.fp0;
10489 else
10490 fp = pipe_config->dpll_hw_state.fp1;
10491
10492 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10493 if (IS_PINEVIEW(dev)) {
10494 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10495 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10496 } else {
10497 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10498 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10499 }
10500
10501 if (!IS_GEN2(dev)) {
10502 if (IS_PINEVIEW(dev))
10503 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10504 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10505 else
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT);
10508
10509 switch (dpll & DPLL_MODE_MASK) {
10510 case DPLLB_MODE_DAC_SERIAL:
10511 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10512 5 : 10;
10513 break;
10514 case DPLLB_MODE_LVDS:
10515 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10516 7 : 14;
10517 break;
10518 default:
10519 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10520 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10521 return;
10522 }
10523
10524 if (IS_PINEVIEW(dev))
10525 port_clock = pnv_calc_dpll_params(refclk, &clock);
10526 else
10527 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10528 } else {
10529 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10530 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10531
10532 if (is_lvds) {
10533 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10534 DPLL_FPA01_P1_POST_DIV_SHIFT);
10535
10536 if (lvds & LVDS_CLKB_POWER_UP)
10537 clock.p2 = 7;
10538 else
10539 clock.p2 = 14;
10540 } else {
10541 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10542 clock.p1 = 2;
10543 else {
10544 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10545 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10546 }
10547 if (dpll & PLL_P2_DIVIDE_BY_4)
10548 clock.p2 = 4;
10549 else
10550 clock.p2 = 2;
10551 }
10552
10553 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10554 }
10555
10556 /*
10557 * This value includes pixel_multiplier. We will use
10558 * port_clock to compute adjusted_mode.crtc_clock in the
10559 * encoder's get_config() function.
10560 */
10561 pipe_config->port_clock = port_clock;
10562 }
10563
10564 int intel_dotclock_calculate(int link_freq,
10565 const struct intel_link_m_n *m_n)
10566 {
10567 /*
10568 * The calculation for the data clock is:
10569 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10570 * But we want to avoid losing precison if possible, so:
10571 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10572 *
10573 * and the link clock is simpler:
10574 * link_clock = (m * link_clock) / n
10575 */
10576
10577 if (!m_n->link_n)
10578 return 0;
10579
10580 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10581 }
10582
10583 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10584 struct intel_crtc_state *pipe_config)
10585 {
10586 struct drm_device *dev = crtc->base.dev;
10587
10588 /* read out port_clock from the DPLL */
10589 i9xx_crtc_clock_get(crtc, pipe_config);
10590
10591 /*
10592 * This value does not include pixel_multiplier.
10593 * We will check that port_clock and adjusted_mode.crtc_clock
10594 * agree once we know their relationship in the encoder's
10595 * get_config() function.
10596 */
10597 pipe_config->base.adjusted_mode.crtc_clock =
10598 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10599 &pipe_config->fdi_m_n);
10600 }
10601
10602 /** Returns the currently programmed mode of the given pipe. */
10603 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10604 struct drm_crtc *crtc)
10605 {
10606 struct drm_i915_private *dev_priv = dev->dev_private;
10607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10608 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10609 struct drm_display_mode *mode;
10610 struct intel_crtc_state pipe_config;
10611 int htot = I915_READ(HTOTAL(cpu_transcoder));
10612 int hsync = I915_READ(HSYNC(cpu_transcoder));
10613 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10614 int vsync = I915_READ(VSYNC(cpu_transcoder));
10615 enum pipe pipe = intel_crtc->pipe;
10616
10617 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10618 if (!mode)
10619 return NULL;
10620
10621 /*
10622 * Construct a pipe_config sufficient for getting the clock info
10623 * back out of crtc_clock_get.
10624 *
10625 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10626 * to use a real value here instead.
10627 */
10628 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10629 pipe_config.pixel_multiplier = 1;
10630 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10631 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10632 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10633 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10634
10635 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10636 mode->hdisplay = (htot & 0xffff) + 1;
10637 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10638 mode->hsync_start = (hsync & 0xffff) + 1;
10639 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10640 mode->vdisplay = (vtot & 0xffff) + 1;
10641 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10642 mode->vsync_start = (vsync & 0xffff) + 1;
10643 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10644
10645 drm_mode_set_name(mode);
10646
10647 return mode;
10648 }
10649
10650 void intel_mark_busy(struct drm_device *dev)
10651 {
10652 struct drm_i915_private *dev_priv = dev->dev_private;
10653
10654 if (dev_priv->mm.busy)
10655 return;
10656
10657 intel_runtime_pm_get(dev_priv);
10658 i915_update_gfx_val(dev_priv);
10659 if (INTEL_INFO(dev)->gen >= 6)
10660 gen6_rps_busy(dev_priv);
10661 dev_priv->mm.busy = true;
10662 }
10663
10664 void intel_mark_idle(struct drm_device *dev)
10665 {
10666 struct drm_i915_private *dev_priv = dev->dev_private;
10667
10668 if (!dev_priv->mm.busy)
10669 return;
10670
10671 dev_priv->mm.busy = false;
10672
10673 if (INTEL_INFO(dev)->gen >= 6)
10674 gen6_rps_idle(dev->dev_private);
10675
10676 intel_runtime_pm_put(dev_priv);
10677 }
10678
10679 static void intel_crtc_destroy(struct drm_crtc *crtc)
10680 {
10681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10682 struct drm_device *dev = crtc->dev;
10683 struct intel_unpin_work *work;
10684
10685 spin_lock_irq(&dev->event_lock);
10686 work = intel_crtc->unpin_work;
10687 intel_crtc->unpin_work = NULL;
10688 spin_unlock_irq(&dev->event_lock);
10689
10690 if (work) {
10691 cancel_work_sync(&work->work);
10692 kfree(work);
10693 }
10694
10695 drm_crtc_cleanup(crtc);
10696
10697 kfree(intel_crtc);
10698 }
10699
10700 static void intel_unpin_work_fn(struct work_struct *__work)
10701 {
10702 struct intel_unpin_work *work =
10703 container_of(__work, struct intel_unpin_work, work);
10704 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10705 struct drm_device *dev = crtc->base.dev;
10706 struct drm_i915_private *dev_priv = dev->dev_private;
10707 struct drm_plane *primary = crtc->base.primary;
10708
10709 mutex_lock(&dev->struct_mutex);
10710 intel_unpin_fb_obj(work->old_fb, primary->state);
10711 drm_gem_object_unreference(&work->pending_flip_obj->base);
10712
10713 intel_fbc_update(dev_priv);
10714
10715 if (work->flip_queued_req)
10716 i915_gem_request_assign(&work->flip_queued_req, NULL);
10717 mutex_unlock(&dev->struct_mutex);
10718
10719 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10720 drm_framebuffer_unreference(work->old_fb);
10721
10722 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10723 atomic_dec(&crtc->unpin_work_count);
10724
10725 kfree(work);
10726 }
10727
10728 static void do_intel_finish_page_flip(struct drm_device *dev,
10729 struct drm_crtc *crtc)
10730 {
10731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10732 struct intel_unpin_work *work;
10733 unsigned long flags;
10734
10735 /* Ignore early vblank irqs */
10736 if (intel_crtc == NULL)
10737 return;
10738
10739 /*
10740 * This is called both by irq handlers and the reset code (to complete
10741 * lost pageflips) so needs the full irqsave spinlocks.
10742 */
10743 spin_lock_irqsave(&dev->event_lock, flags);
10744 work = intel_crtc->unpin_work;
10745
10746 /* Ensure we don't miss a work->pending update ... */
10747 smp_rmb();
10748
10749 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10750 spin_unlock_irqrestore(&dev->event_lock, flags);
10751 return;
10752 }
10753
10754 page_flip_completed(intel_crtc);
10755
10756 spin_unlock_irqrestore(&dev->event_lock, flags);
10757 }
10758
10759 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10760 {
10761 struct drm_i915_private *dev_priv = dev->dev_private;
10762 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10763
10764 do_intel_finish_page_flip(dev, crtc);
10765 }
10766
10767 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10768 {
10769 struct drm_i915_private *dev_priv = dev->dev_private;
10770 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10771
10772 do_intel_finish_page_flip(dev, crtc);
10773 }
10774
10775 /* Is 'a' after or equal to 'b'? */
10776 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10777 {
10778 return !((a - b) & 0x80000000);
10779 }
10780
10781 static bool page_flip_finished(struct intel_crtc *crtc)
10782 {
10783 struct drm_device *dev = crtc->base.dev;
10784 struct drm_i915_private *dev_priv = dev->dev_private;
10785
10786 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10787 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10788 return true;
10789
10790 /*
10791 * The relevant registers doen't exist on pre-ctg.
10792 * As the flip done interrupt doesn't trigger for mmio
10793 * flips on gmch platforms, a flip count check isn't
10794 * really needed there. But since ctg has the registers,
10795 * include it in the check anyway.
10796 */
10797 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10798 return true;
10799
10800 /*
10801 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10802 * used the same base address. In that case the mmio flip might
10803 * have completed, but the CS hasn't even executed the flip yet.
10804 *
10805 * A flip count check isn't enough as the CS might have updated
10806 * the base address just after start of vblank, but before we
10807 * managed to process the interrupt. This means we'd complete the
10808 * CS flip too soon.
10809 *
10810 * Combining both checks should get us a good enough result. It may
10811 * still happen that the CS flip has been executed, but has not
10812 * yet actually completed. But in case the base address is the same
10813 * anyway, we don't really care.
10814 */
10815 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10816 crtc->unpin_work->gtt_offset &&
10817 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10818 crtc->unpin_work->flip_count);
10819 }
10820
10821 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10822 {
10823 struct drm_i915_private *dev_priv = dev->dev_private;
10824 struct intel_crtc *intel_crtc =
10825 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10826 unsigned long flags;
10827
10828
10829 /*
10830 * This is called both by irq handlers and the reset code (to complete
10831 * lost pageflips) so needs the full irqsave spinlocks.
10832 *
10833 * NB: An MMIO update of the plane base pointer will also
10834 * generate a page-flip completion irq, i.e. every modeset
10835 * is also accompanied by a spurious intel_prepare_page_flip().
10836 */
10837 spin_lock_irqsave(&dev->event_lock, flags);
10838 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10839 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10840 spin_unlock_irqrestore(&dev->event_lock, flags);
10841 }
10842
10843 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10844 {
10845 /* Ensure that the work item is consistent when activating it ... */
10846 smp_wmb();
10847 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10848 /* and that it is marked active as soon as the irq could fire. */
10849 smp_wmb();
10850 }
10851
10852 static int intel_gen2_queue_flip(struct drm_device *dev,
10853 struct drm_crtc *crtc,
10854 struct drm_framebuffer *fb,
10855 struct drm_i915_gem_object *obj,
10856 struct drm_i915_gem_request *req,
10857 uint32_t flags)
10858 {
10859 struct intel_engine_cs *ring = req->ring;
10860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10861 u32 flip_mask;
10862 int ret;
10863
10864 ret = intel_ring_begin(req, 6);
10865 if (ret)
10866 return ret;
10867
10868 /* Can't queue multiple flips, so wait for the previous
10869 * one to finish before executing the next.
10870 */
10871 if (intel_crtc->plane)
10872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10873 else
10874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10876 intel_ring_emit(ring, MI_NOOP);
10877 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10879 intel_ring_emit(ring, fb->pitches[0]);
10880 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10881 intel_ring_emit(ring, 0); /* aux display base address, unused */
10882
10883 intel_mark_page_flip_active(intel_crtc);
10884 return 0;
10885 }
10886
10887 static int intel_gen3_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
10890 struct drm_i915_gem_object *obj,
10891 struct drm_i915_gem_request *req,
10892 uint32_t flags)
10893 {
10894 struct intel_engine_cs *ring = req->ring;
10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10896 u32 flip_mask;
10897 int ret;
10898
10899 ret = intel_ring_begin(req, 6);
10900 if (ret)
10901 return ret;
10902
10903 if (intel_crtc->plane)
10904 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10905 else
10906 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10907 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10908 intel_ring_emit(ring, MI_NOOP);
10909 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10910 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10911 intel_ring_emit(ring, fb->pitches[0]);
10912 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10913 intel_ring_emit(ring, MI_NOOP);
10914
10915 intel_mark_page_flip_active(intel_crtc);
10916 return 0;
10917 }
10918
10919 static int intel_gen4_queue_flip(struct drm_device *dev,
10920 struct drm_crtc *crtc,
10921 struct drm_framebuffer *fb,
10922 struct drm_i915_gem_object *obj,
10923 struct drm_i915_gem_request *req,
10924 uint32_t flags)
10925 {
10926 struct intel_engine_cs *ring = req->ring;
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 uint32_t pf, pipesrc;
10930 int ret;
10931
10932 ret = intel_ring_begin(req, 4);
10933 if (ret)
10934 return ret;
10935
10936 /* i965+ uses the linear or tiled offsets from the
10937 * Display Registers (which do not change across a page-flip)
10938 * so we need only reprogram the base address.
10939 */
10940 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10941 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10942 intel_ring_emit(ring, fb->pitches[0]);
10943 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10944 obj->tiling_mode);
10945
10946 /* XXX Enabling the panel-fitter across page-flip is so far
10947 * untested on non-native modes, so ignore it for now.
10948 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10949 */
10950 pf = 0;
10951 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10952 intel_ring_emit(ring, pf | pipesrc);
10953
10954 intel_mark_page_flip_active(intel_crtc);
10955 return 0;
10956 }
10957
10958 static int intel_gen6_queue_flip(struct drm_device *dev,
10959 struct drm_crtc *crtc,
10960 struct drm_framebuffer *fb,
10961 struct drm_i915_gem_object *obj,
10962 struct drm_i915_gem_request *req,
10963 uint32_t flags)
10964 {
10965 struct intel_engine_cs *ring = req->ring;
10966 struct drm_i915_private *dev_priv = dev->dev_private;
10967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10968 uint32_t pf, pipesrc;
10969 int ret;
10970
10971 ret = intel_ring_begin(req, 4);
10972 if (ret)
10973 return ret;
10974
10975 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10976 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10977 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10978 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10979
10980 /* Contrary to the suggestions in the documentation,
10981 * "Enable Panel Fitter" does not seem to be required when page
10982 * flipping with a non-native mode, and worse causes a normal
10983 * modeset to fail.
10984 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10985 */
10986 pf = 0;
10987 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10988 intel_ring_emit(ring, pf | pipesrc);
10989
10990 intel_mark_page_flip_active(intel_crtc);
10991 return 0;
10992 }
10993
10994 static int intel_gen7_queue_flip(struct drm_device *dev,
10995 struct drm_crtc *crtc,
10996 struct drm_framebuffer *fb,
10997 struct drm_i915_gem_object *obj,
10998 struct drm_i915_gem_request *req,
10999 uint32_t flags)
11000 {
11001 struct intel_engine_cs *ring = req->ring;
11002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11003 uint32_t plane_bit = 0;
11004 int len, ret;
11005
11006 switch (intel_crtc->plane) {
11007 case PLANE_A:
11008 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11009 break;
11010 case PLANE_B:
11011 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11012 break;
11013 case PLANE_C:
11014 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11015 break;
11016 default:
11017 WARN_ONCE(1, "unknown plane in flip command\n");
11018 return -ENODEV;
11019 }
11020
11021 len = 4;
11022 if (ring->id == RCS) {
11023 len += 6;
11024 /*
11025 * On Gen 8, SRM is now taking an extra dword to accommodate
11026 * 48bits addresses, and we need a NOOP for the batch size to
11027 * stay even.
11028 */
11029 if (IS_GEN8(dev))
11030 len += 2;
11031 }
11032
11033 /*
11034 * BSpec MI_DISPLAY_FLIP for IVB:
11035 * "The full packet must be contained within the same cache line."
11036 *
11037 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11038 * cacheline, if we ever start emitting more commands before
11039 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11040 * then do the cacheline alignment, and finally emit the
11041 * MI_DISPLAY_FLIP.
11042 */
11043 ret = intel_ring_cacheline_align(req);
11044 if (ret)
11045 return ret;
11046
11047 ret = intel_ring_begin(req, len);
11048 if (ret)
11049 return ret;
11050
11051 /* Unmask the flip-done completion message. Note that the bspec says that
11052 * we should do this for both the BCS and RCS, and that we must not unmask
11053 * more than one flip event at any time (or ensure that one flip message
11054 * can be sent by waiting for flip-done prior to queueing new flips).
11055 * Experimentation says that BCS works despite DERRMR masking all
11056 * flip-done completion events and that unmasking all planes at once
11057 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11058 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11059 */
11060 if (ring->id == RCS) {
11061 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11062 intel_ring_emit(ring, DERRMR);
11063 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11064 DERRMR_PIPEB_PRI_FLIP_DONE |
11065 DERRMR_PIPEC_PRI_FLIP_DONE));
11066 if (IS_GEN8(dev))
11067 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11068 MI_SRM_LRM_GLOBAL_GTT);
11069 else
11070 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11071 MI_SRM_LRM_GLOBAL_GTT);
11072 intel_ring_emit(ring, DERRMR);
11073 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11074 if (IS_GEN8(dev)) {
11075 intel_ring_emit(ring, 0);
11076 intel_ring_emit(ring, MI_NOOP);
11077 }
11078 }
11079
11080 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11081 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11082 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11083 intel_ring_emit(ring, (MI_NOOP));
11084
11085 intel_mark_page_flip_active(intel_crtc);
11086 return 0;
11087 }
11088
11089 static bool use_mmio_flip(struct intel_engine_cs *ring,
11090 struct drm_i915_gem_object *obj)
11091 {
11092 /*
11093 * This is not being used for older platforms, because
11094 * non-availability of flip done interrupt forces us to use
11095 * CS flips. Older platforms derive flip done using some clever
11096 * tricks involving the flip_pending status bits and vblank irqs.
11097 * So using MMIO flips there would disrupt this mechanism.
11098 */
11099
11100 if (ring == NULL)
11101 return true;
11102
11103 if (INTEL_INFO(ring->dev)->gen < 5)
11104 return false;
11105
11106 if (i915.use_mmio_flip < 0)
11107 return false;
11108 else if (i915.use_mmio_flip > 0)
11109 return true;
11110 else if (i915.enable_execlists)
11111 return true;
11112 else
11113 return ring != i915_gem_request_get_ring(obj->last_write_req);
11114 }
11115
11116 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11117 {
11118 struct drm_device *dev = intel_crtc->base.dev;
11119 struct drm_i915_private *dev_priv = dev->dev_private;
11120 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11121 const enum pipe pipe = intel_crtc->pipe;
11122 u32 ctl, stride;
11123
11124 ctl = I915_READ(PLANE_CTL(pipe, 0));
11125 ctl &= ~PLANE_CTL_TILED_MASK;
11126 switch (fb->modifier[0]) {
11127 case DRM_FORMAT_MOD_NONE:
11128 break;
11129 case I915_FORMAT_MOD_X_TILED:
11130 ctl |= PLANE_CTL_TILED_X;
11131 break;
11132 case I915_FORMAT_MOD_Y_TILED:
11133 ctl |= PLANE_CTL_TILED_Y;
11134 break;
11135 case I915_FORMAT_MOD_Yf_TILED:
11136 ctl |= PLANE_CTL_TILED_YF;
11137 break;
11138 default:
11139 MISSING_CASE(fb->modifier[0]);
11140 }
11141
11142 /*
11143 * The stride is either expressed as a multiple of 64 bytes chunks for
11144 * linear buffers or in number of tiles for tiled buffers.
11145 */
11146 stride = fb->pitches[0] /
11147 intel_fb_stride_alignment(dev, fb->modifier[0],
11148 fb->pixel_format);
11149
11150 /*
11151 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11152 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11153 */
11154 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11155 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11156
11157 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11158 POSTING_READ(PLANE_SURF(pipe, 0));
11159 }
11160
11161 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11162 {
11163 struct drm_device *dev = intel_crtc->base.dev;
11164 struct drm_i915_private *dev_priv = dev->dev_private;
11165 struct intel_framebuffer *intel_fb =
11166 to_intel_framebuffer(intel_crtc->base.primary->fb);
11167 struct drm_i915_gem_object *obj = intel_fb->obj;
11168 u32 dspcntr;
11169 u32 reg;
11170
11171 reg = DSPCNTR(intel_crtc->plane);
11172 dspcntr = I915_READ(reg);
11173
11174 if (obj->tiling_mode != I915_TILING_NONE)
11175 dspcntr |= DISPPLANE_TILED;
11176 else
11177 dspcntr &= ~DISPPLANE_TILED;
11178
11179 I915_WRITE(reg, dspcntr);
11180
11181 I915_WRITE(DSPSURF(intel_crtc->plane),
11182 intel_crtc->unpin_work->gtt_offset);
11183 POSTING_READ(DSPSURF(intel_crtc->plane));
11184
11185 }
11186
11187 /*
11188 * XXX: This is the temporary way to update the plane registers until we get
11189 * around to using the usual plane update functions for MMIO flips
11190 */
11191 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11192 {
11193 struct drm_device *dev = intel_crtc->base.dev;
11194 bool atomic_update;
11195 u32 start_vbl_count;
11196
11197 intel_mark_page_flip_active(intel_crtc);
11198
11199 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11200
11201 if (INTEL_INFO(dev)->gen >= 9)
11202 skl_do_mmio_flip(intel_crtc);
11203 else
11204 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11205 ilk_do_mmio_flip(intel_crtc);
11206
11207 if (atomic_update)
11208 intel_pipe_update_end(intel_crtc, start_vbl_count);
11209 }
11210
11211 static void intel_mmio_flip_work_func(struct work_struct *work)
11212 {
11213 struct intel_mmio_flip *mmio_flip =
11214 container_of(work, struct intel_mmio_flip, work);
11215
11216 if (mmio_flip->req)
11217 WARN_ON(__i915_wait_request(mmio_flip->req,
11218 mmio_flip->crtc->reset_counter,
11219 false, NULL,
11220 &mmio_flip->i915->rps.mmioflips));
11221
11222 intel_do_mmio_flip(mmio_flip->crtc);
11223
11224 i915_gem_request_unreference__unlocked(mmio_flip->req);
11225 kfree(mmio_flip);
11226 }
11227
11228 static int intel_queue_mmio_flip(struct drm_device *dev,
11229 struct drm_crtc *crtc,
11230 struct drm_framebuffer *fb,
11231 struct drm_i915_gem_object *obj,
11232 struct intel_engine_cs *ring,
11233 uint32_t flags)
11234 {
11235 struct intel_mmio_flip *mmio_flip;
11236
11237 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11238 if (mmio_flip == NULL)
11239 return -ENOMEM;
11240
11241 mmio_flip->i915 = to_i915(dev);
11242 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11243 mmio_flip->crtc = to_intel_crtc(crtc);
11244
11245 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11246 schedule_work(&mmio_flip->work);
11247
11248 return 0;
11249 }
11250
11251 static int intel_default_queue_flip(struct drm_device *dev,
11252 struct drm_crtc *crtc,
11253 struct drm_framebuffer *fb,
11254 struct drm_i915_gem_object *obj,
11255 struct drm_i915_gem_request *req,
11256 uint32_t flags)
11257 {
11258 return -ENODEV;
11259 }
11260
11261 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11262 struct drm_crtc *crtc)
11263 {
11264 struct drm_i915_private *dev_priv = dev->dev_private;
11265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11266 struct intel_unpin_work *work = intel_crtc->unpin_work;
11267 u32 addr;
11268
11269 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11270 return true;
11271
11272 if (!work->enable_stall_check)
11273 return false;
11274
11275 if (work->flip_ready_vblank == 0) {
11276 if (work->flip_queued_req &&
11277 !i915_gem_request_completed(work->flip_queued_req, true))
11278 return false;
11279
11280 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11281 }
11282
11283 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11284 return false;
11285
11286 /* Potential stall - if we see that the flip has happened,
11287 * assume a missed interrupt. */
11288 if (INTEL_INFO(dev)->gen >= 4)
11289 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11290 else
11291 addr = I915_READ(DSPADDR(intel_crtc->plane));
11292
11293 /* There is a potential issue here with a false positive after a flip
11294 * to the same address. We could address this by checking for a
11295 * non-incrementing frame counter.
11296 */
11297 return addr == work->gtt_offset;
11298 }
11299
11300 void intel_check_page_flip(struct drm_device *dev, int pipe)
11301 {
11302 struct drm_i915_private *dev_priv = dev->dev_private;
11303 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11305 struct intel_unpin_work *work;
11306
11307 WARN_ON(!in_interrupt());
11308
11309 if (crtc == NULL)
11310 return;
11311
11312 spin_lock(&dev->event_lock);
11313 work = intel_crtc->unpin_work;
11314 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11315 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11316 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11317 page_flip_completed(intel_crtc);
11318 work = NULL;
11319 }
11320 if (work != NULL &&
11321 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11322 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11323 spin_unlock(&dev->event_lock);
11324 }
11325
11326 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11327 struct drm_framebuffer *fb,
11328 struct drm_pending_vblank_event *event,
11329 uint32_t page_flip_flags)
11330 {
11331 struct drm_device *dev = crtc->dev;
11332 struct drm_i915_private *dev_priv = dev->dev_private;
11333 struct drm_framebuffer *old_fb = crtc->primary->fb;
11334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11336 struct drm_plane *primary = crtc->primary;
11337 enum pipe pipe = intel_crtc->pipe;
11338 struct intel_unpin_work *work;
11339 struct intel_engine_cs *ring;
11340 bool mmio_flip;
11341 struct drm_i915_gem_request *request = NULL;
11342 int ret;
11343
11344 /*
11345 * drm_mode_page_flip_ioctl() should already catch this, but double
11346 * check to be safe. In the future we may enable pageflipping from
11347 * a disabled primary plane.
11348 */
11349 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11350 return -EBUSY;
11351
11352 /* Can't change pixel format via MI display flips. */
11353 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11354 return -EINVAL;
11355
11356 /*
11357 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11358 * Note that pitch changes could also affect these register.
11359 */
11360 if (INTEL_INFO(dev)->gen > 3 &&
11361 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11362 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11363 return -EINVAL;
11364
11365 if (i915_terminally_wedged(&dev_priv->gpu_error))
11366 goto out_hang;
11367
11368 work = kzalloc(sizeof(*work), GFP_KERNEL);
11369 if (work == NULL)
11370 return -ENOMEM;
11371
11372 work->event = event;
11373 work->crtc = crtc;
11374 work->old_fb = old_fb;
11375 INIT_WORK(&work->work, intel_unpin_work_fn);
11376
11377 ret = drm_crtc_vblank_get(crtc);
11378 if (ret)
11379 goto free_work;
11380
11381 /* We borrow the event spin lock for protecting unpin_work */
11382 spin_lock_irq(&dev->event_lock);
11383 if (intel_crtc->unpin_work) {
11384 /* Before declaring the flip queue wedged, check if
11385 * the hardware completed the operation behind our backs.
11386 */
11387 if (__intel_pageflip_stall_check(dev, crtc)) {
11388 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11389 page_flip_completed(intel_crtc);
11390 } else {
11391 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11392 spin_unlock_irq(&dev->event_lock);
11393
11394 drm_crtc_vblank_put(crtc);
11395 kfree(work);
11396 return -EBUSY;
11397 }
11398 }
11399 intel_crtc->unpin_work = work;
11400 spin_unlock_irq(&dev->event_lock);
11401
11402 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11403 flush_workqueue(dev_priv->wq);
11404
11405 /* Reference the objects for the scheduled work. */
11406 drm_framebuffer_reference(work->old_fb);
11407 drm_gem_object_reference(&obj->base);
11408
11409 crtc->primary->fb = fb;
11410 update_state_fb(crtc->primary);
11411
11412 work->pending_flip_obj = obj;
11413
11414 ret = i915_mutex_lock_interruptible(dev);
11415 if (ret)
11416 goto cleanup;
11417
11418 atomic_inc(&intel_crtc->unpin_work_count);
11419 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11420
11421 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11422 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11423
11424 if (IS_VALLEYVIEW(dev)) {
11425 ring = &dev_priv->ring[BCS];
11426 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11427 /* vlv: DISPLAY_FLIP fails to change tiling */
11428 ring = NULL;
11429 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11430 ring = &dev_priv->ring[BCS];
11431 } else if (INTEL_INFO(dev)->gen >= 7) {
11432 ring = i915_gem_request_get_ring(obj->last_write_req);
11433 if (ring == NULL || ring->id != RCS)
11434 ring = &dev_priv->ring[BCS];
11435 } else {
11436 ring = &dev_priv->ring[RCS];
11437 }
11438
11439 mmio_flip = use_mmio_flip(ring, obj);
11440
11441 /* When using CS flips, we want to emit semaphores between rings.
11442 * However, when using mmio flips we will create a task to do the
11443 * synchronisation, so all we want here is to pin the framebuffer
11444 * into the display plane and skip any waits.
11445 */
11446 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11447 crtc->primary->state,
11448 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11449 if (ret)
11450 goto cleanup_pending;
11451
11452 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11453 + intel_crtc->dspaddr_offset;
11454
11455 if (mmio_flip) {
11456 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11457 page_flip_flags);
11458 if (ret)
11459 goto cleanup_unpin;
11460
11461 i915_gem_request_assign(&work->flip_queued_req,
11462 obj->last_write_req);
11463 } else {
11464 if (!request) {
11465 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11466 if (ret)
11467 goto cleanup_unpin;
11468 }
11469
11470 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11471 page_flip_flags);
11472 if (ret)
11473 goto cleanup_unpin;
11474
11475 i915_gem_request_assign(&work->flip_queued_req, request);
11476 }
11477
11478 if (request)
11479 i915_add_request_no_flush(request);
11480
11481 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11482 work->enable_stall_check = true;
11483
11484 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11485 to_intel_plane(primary)->frontbuffer_bit);
11486 mutex_unlock(&dev->struct_mutex);
11487
11488 intel_fbc_disable(dev_priv);
11489 intel_frontbuffer_flip_prepare(dev,
11490 to_intel_plane(primary)->frontbuffer_bit);
11491
11492 trace_i915_flip_request(intel_crtc->plane, obj);
11493
11494 return 0;
11495
11496 cleanup_unpin:
11497 intel_unpin_fb_obj(fb, crtc->primary->state);
11498 cleanup_pending:
11499 if (request)
11500 i915_gem_request_cancel(request);
11501 atomic_dec(&intel_crtc->unpin_work_count);
11502 mutex_unlock(&dev->struct_mutex);
11503 cleanup:
11504 crtc->primary->fb = old_fb;
11505 update_state_fb(crtc->primary);
11506
11507 drm_gem_object_unreference_unlocked(&obj->base);
11508 drm_framebuffer_unreference(work->old_fb);
11509
11510 spin_lock_irq(&dev->event_lock);
11511 intel_crtc->unpin_work = NULL;
11512 spin_unlock_irq(&dev->event_lock);
11513
11514 drm_crtc_vblank_put(crtc);
11515 free_work:
11516 kfree(work);
11517
11518 if (ret == -EIO) {
11519 struct drm_atomic_state *state;
11520 struct drm_plane_state *plane_state;
11521
11522 out_hang:
11523 state = drm_atomic_state_alloc(dev);
11524 if (!state)
11525 return -ENOMEM;
11526 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11527
11528 retry:
11529 plane_state = drm_atomic_get_plane_state(state, primary);
11530 ret = PTR_ERR_OR_ZERO(plane_state);
11531 if (!ret) {
11532 drm_atomic_set_fb_for_plane(plane_state, fb);
11533
11534 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11535 if (!ret)
11536 ret = drm_atomic_commit(state);
11537 }
11538
11539 if (ret == -EDEADLK) {
11540 drm_modeset_backoff(state->acquire_ctx);
11541 drm_atomic_state_clear(state);
11542 goto retry;
11543 }
11544
11545 if (ret)
11546 drm_atomic_state_free(state);
11547
11548 if (ret == 0 && event) {
11549 spin_lock_irq(&dev->event_lock);
11550 drm_send_vblank_event(dev, pipe, event);
11551 spin_unlock_irq(&dev->event_lock);
11552 }
11553 }
11554 return ret;
11555 }
11556
11557
11558 /**
11559 * intel_wm_need_update - Check whether watermarks need updating
11560 * @plane: drm plane
11561 * @state: new plane state
11562 *
11563 * Check current plane state versus the new one to determine whether
11564 * watermarks need to be recalculated.
11565 *
11566 * Returns true or false.
11567 */
11568 static bool intel_wm_need_update(struct drm_plane *plane,
11569 struct drm_plane_state *state)
11570 {
11571 /* Update watermarks on tiling changes. */
11572 if (!plane->state->fb || !state->fb ||
11573 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11574 plane->state->rotation != state->rotation)
11575 return true;
11576
11577 if (plane->state->crtc_w != state->crtc_w)
11578 return true;
11579
11580 return false;
11581 }
11582
11583 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11584 struct drm_plane_state *plane_state)
11585 {
11586 struct drm_crtc *crtc = crtc_state->crtc;
11587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11588 struct drm_plane *plane = plane_state->plane;
11589 struct drm_device *dev = crtc->dev;
11590 struct drm_i915_private *dev_priv = dev->dev_private;
11591 struct intel_plane_state *old_plane_state =
11592 to_intel_plane_state(plane->state);
11593 int idx = intel_crtc->base.base.id, ret;
11594 int i = drm_plane_index(plane);
11595 bool mode_changed = needs_modeset(crtc_state);
11596 bool was_crtc_enabled = crtc->state->active;
11597 bool is_crtc_enabled = crtc_state->active;
11598
11599 bool turn_off, turn_on, visible, was_visible;
11600 struct drm_framebuffer *fb = plane_state->fb;
11601
11602 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11603 plane->type != DRM_PLANE_TYPE_CURSOR) {
11604 ret = skl_update_scaler_plane(
11605 to_intel_crtc_state(crtc_state),
11606 to_intel_plane_state(plane_state));
11607 if (ret)
11608 return ret;
11609 }
11610
11611 /*
11612 * Disabling a plane is always okay; we just need to update
11613 * fb tracking in a special way since cleanup_fb() won't
11614 * get called by the plane helpers.
11615 */
11616 if (old_plane_state->base.fb && !fb)
11617 intel_crtc->atomic.disabled_planes |= 1 << i;
11618
11619 was_visible = old_plane_state->visible;
11620 visible = to_intel_plane_state(plane_state)->visible;
11621
11622 if (!was_crtc_enabled && WARN_ON(was_visible))
11623 was_visible = false;
11624
11625 if (!is_crtc_enabled && WARN_ON(visible))
11626 visible = false;
11627
11628 if (!was_visible && !visible)
11629 return 0;
11630
11631 turn_off = was_visible && (!visible || mode_changed);
11632 turn_on = visible && (!was_visible || mode_changed);
11633
11634 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11635 plane->base.id, fb ? fb->base.id : -1);
11636
11637 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11638 plane->base.id, was_visible, visible,
11639 turn_off, turn_on, mode_changed);
11640
11641 if (turn_on) {
11642 intel_crtc->atomic.update_wm_pre = true;
11643 /* must disable cxsr around plane enable/disable */
11644 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11645 intel_crtc->atomic.disable_cxsr = true;
11646 /* to potentially re-enable cxsr */
11647 intel_crtc->atomic.wait_vblank = true;
11648 intel_crtc->atomic.update_wm_post = true;
11649 }
11650 } else if (turn_off) {
11651 intel_crtc->atomic.update_wm_post = true;
11652 /* must disable cxsr around plane enable/disable */
11653 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11654 if (is_crtc_enabled)
11655 intel_crtc->atomic.wait_vblank = true;
11656 intel_crtc->atomic.disable_cxsr = true;
11657 }
11658 } else if (intel_wm_need_update(plane, plane_state)) {
11659 intel_crtc->atomic.update_wm_pre = true;
11660 }
11661
11662 if (visible)
11663 intel_crtc->atomic.fb_bits |=
11664 to_intel_plane(plane)->frontbuffer_bit;
11665
11666 switch (plane->type) {
11667 case DRM_PLANE_TYPE_PRIMARY:
11668 intel_crtc->atomic.wait_for_flips = true;
11669 intel_crtc->atomic.pre_disable_primary = turn_off;
11670 intel_crtc->atomic.post_enable_primary = turn_on;
11671
11672 if (turn_off) {
11673 /*
11674 * FIXME: Actually if we will still have any other
11675 * plane enabled on the pipe we could let IPS enabled
11676 * still, but for now lets consider that when we make
11677 * primary invisible by setting DSPCNTR to 0 on
11678 * update_primary_plane function IPS needs to be
11679 * disable.
11680 */
11681 intel_crtc->atomic.disable_ips = true;
11682
11683 intel_crtc->atomic.disable_fbc = true;
11684 }
11685
11686 /*
11687 * FBC does not work on some platforms for rotated
11688 * planes, so disable it when rotation is not 0 and
11689 * update it when rotation is set back to 0.
11690 *
11691 * FIXME: This is redundant with the fbc update done in
11692 * the primary plane enable function except that that
11693 * one is done too late. We eventually need to unify
11694 * this.
11695 */
11696
11697 if (visible &&
11698 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11699 dev_priv->fbc.crtc == intel_crtc &&
11700 plane_state->rotation != BIT(DRM_ROTATE_0))
11701 intel_crtc->atomic.disable_fbc = true;
11702
11703 /*
11704 * BDW signals flip done immediately if the plane
11705 * is disabled, even if the plane enable is already
11706 * armed to occur at the next vblank :(
11707 */
11708 if (turn_on && IS_BROADWELL(dev))
11709 intel_crtc->atomic.wait_vblank = true;
11710
11711 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11712 break;
11713 case DRM_PLANE_TYPE_CURSOR:
11714 break;
11715 case DRM_PLANE_TYPE_OVERLAY:
11716 if (turn_off && !mode_changed) {
11717 intel_crtc->atomic.wait_vblank = true;
11718 intel_crtc->atomic.update_sprite_watermarks |=
11719 1 << i;
11720 }
11721 }
11722 return 0;
11723 }
11724
11725 static bool encoders_cloneable(const struct intel_encoder *a,
11726 const struct intel_encoder *b)
11727 {
11728 /* masks could be asymmetric, so check both ways */
11729 return a == b || (a->cloneable & (1 << b->type) &&
11730 b->cloneable & (1 << a->type));
11731 }
11732
11733 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11734 struct intel_crtc *crtc,
11735 struct intel_encoder *encoder)
11736 {
11737 struct intel_encoder *source_encoder;
11738 struct drm_connector *connector;
11739 struct drm_connector_state *connector_state;
11740 int i;
11741
11742 for_each_connector_in_state(state, connector, connector_state, i) {
11743 if (connector_state->crtc != &crtc->base)
11744 continue;
11745
11746 source_encoder =
11747 to_intel_encoder(connector_state->best_encoder);
11748 if (!encoders_cloneable(encoder, source_encoder))
11749 return false;
11750 }
11751
11752 return true;
11753 }
11754
11755 static bool check_encoder_cloning(struct drm_atomic_state *state,
11756 struct intel_crtc *crtc)
11757 {
11758 struct intel_encoder *encoder;
11759 struct drm_connector *connector;
11760 struct drm_connector_state *connector_state;
11761 int i;
11762
11763 for_each_connector_in_state(state, connector, connector_state, i) {
11764 if (connector_state->crtc != &crtc->base)
11765 continue;
11766
11767 encoder = to_intel_encoder(connector_state->best_encoder);
11768 if (!check_single_encoder_cloning(state, crtc, encoder))
11769 return false;
11770 }
11771
11772 return true;
11773 }
11774
11775 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11776 struct drm_crtc_state *crtc_state)
11777 {
11778 struct intel_crtc_state *pipe_config =
11779 to_intel_crtc_state(crtc_state);
11780 struct drm_plane *p;
11781 unsigned visible_mask = 0;
11782
11783 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11784 struct drm_plane_state *plane_state =
11785 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11786
11787 if (WARN_ON(!plane_state))
11788 continue;
11789
11790 if (!plane_state->fb)
11791 crtc_state->plane_mask &=
11792 ~(1 << drm_plane_index(p));
11793 else if (to_intel_plane_state(plane_state)->visible)
11794 visible_mask |= 1 << drm_plane_index(p);
11795 }
11796
11797 if (!visible_mask)
11798 return;
11799
11800 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11801 }
11802
11803 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11804 struct drm_crtc_state *crtc_state)
11805 {
11806 struct drm_device *dev = crtc->dev;
11807 struct drm_i915_private *dev_priv = dev->dev_private;
11808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11809 struct intel_crtc_state *pipe_config =
11810 to_intel_crtc_state(crtc_state);
11811 struct drm_atomic_state *state = crtc_state->state;
11812 int ret, idx = crtc->base.id;
11813 bool mode_changed = needs_modeset(crtc_state);
11814
11815 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11816 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11817 return -EINVAL;
11818 }
11819
11820 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11821 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11822 idx, crtc->state->active, intel_crtc->active);
11823
11824 /* plane mask is fixed up after all initial planes are calculated */
11825 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11826 intel_crtc_check_initial_planes(crtc, crtc_state);
11827
11828 if (mode_changed && !crtc_state->active)
11829 intel_crtc->atomic.update_wm_post = true;
11830
11831 if (mode_changed && crtc_state->enable &&
11832 dev_priv->display.crtc_compute_clock &&
11833 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11834 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11835 pipe_config);
11836 if (ret)
11837 return ret;
11838 }
11839
11840 ret = 0;
11841 if (INTEL_INFO(dev)->gen >= 9) {
11842 if (mode_changed)
11843 ret = skl_update_scaler_crtc(pipe_config);
11844
11845 if (!ret)
11846 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11847 pipe_config);
11848 }
11849
11850 return ret;
11851 }
11852
11853 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11854 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11855 .load_lut = intel_crtc_load_lut,
11856 .atomic_begin = intel_begin_crtc_commit,
11857 .atomic_flush = intel_finish_crtc_commit,
11858 .atomic_check = intel_crtc_atomic_check,
11859 };
11860
11861 /**
11862 * intel_modeset_update_staged_output_state
11863 *
11864 * Updates the staged output configuration state, e.g. after we've read out the
11865 * current hw state.
11866 */
11867 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11868 {
11869 struct intel_crtc *crtc;
11870 struct intel_encoder *encoder;
11871 struct intel_connector *connector;
11872
11873 for_each_intel_connector(dev, connector) {
11874 connector->new_encoder =
11875 to_intel_encoder(connector->base.encoder);
11876 }
11877
11878 for_each_intel_encoder(dev, encoder) {
11879 encoder->new_crtc =
11880 to_intel_crtc(encoder->base.crtc);
11881 }
11882
11883 for_each_intel_crtc(dev, crtc) {
11884 crtc->new_enabled = crtc->base.state->enable;
11885 }
11886 }
11887
11888 /* Transitional helper to copy current connector/encoder state to
11889 * connector->state. This is needed so that code that is partially
11890 * converted to atomic does the right thing.
11891 */
11892 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11893 {
11894 struct intel_connector *connector;
11895
11896 for_each_intel_connector(dev, connector) {
11897 if (connector->base.encoder) {
11898 connector->base.state->best_encoder =
11899 connector->base.encoder;
11900 connector->base.state->crtc =
11901 connector->base.encoder->crtc;
11902 } else {
11903 connector->base.state->best_encoder = NULL;
11904 connector->base.state->crtc = NULL;
11905 }
11906 }
11907 }
11908
11909 static void
11910 connected_sink_compute_bpp(struct intel_connector *connector,
11911 struct intel_crtc_state *pipe_config)
11912 {
11913 int bpp = pipe_config->pipe_bpp;
11914
11915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11916 connector->base.base.id,
11917 connector->base.name);
11918
11919 /* Don't use an invalid EDID bpc value */
11920 if (connector->base.display_info.bpc &&
11921 connector->base.display_info.bpc * 3 < bpp) {
11922 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11923 bpp, connector->base.display_info.bpc*3);
11924 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11925 }
11926
11927 /* Clamp bpp to 8 on screens without EDID 1.4 */
11928 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11929 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11930 bpp);
11931 pipe_config->pipe_bpp = 24;
11932 }
11933 }
11934
11935 static int
11936 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11937 struct intel_crtc_state *pipe_config)
11938 {
11939 struct drm_device *dev = crtc->base.dev;
11940 struct drm_atomic_state *state;
11941 struct drm_connector *connector;
11942 struct drm_connector_state *connector_state;
11943 int bpp, i;
11944
11945 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11946 bpp = 10*3;
11947 else if (INTEL_INFO(dev)->gen >= 5)
11948 bpp = 12*3;
11949 else
11950 bpp = 8*3;
11951
11952
11953 pipe_config->pipe_bpp = bpp;
11954
11955 state = pipe_config->base.state;
11956
11957 /* Clamp display bpp to EDID value */
11958 for_each_connector_in_state(state, connector, connector_state, i) {
11959 if (connector_state->crtc != &crtc->base)
11960 continue;
11961
11962 connected_sink_compute_bpp(to_intel_connector(connector),
11963 pipe_config);
11964 }
11965
11966 return bpp;
11967 }
11968
11969 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11970 {
11971 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11972 "type: 0x%x flags: 0x%x\n",
11973 mode->crtc_clock,
11974 mode->crtc_hdisplay, mode->crtc_hsync_start,
11975 mode->crtc_hsync_end, mode->crtc_htotal,
11976 mode->crtc_vdisplay, mode->crtc_vsync_start,
11977 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11978 }
11979
11980 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11981 struct intel_crtc_state *pipe_config,
11982 const char *context)
11983 {
11984 struct drm_device *dev = crtc->base.dev;
11985 struct drm_plane *plane;
11986 struct intel_plane *intel_plane;
11987 struct intel_plane_state *state;
11988 struct drm_framebuffer *fb;
11989
11990 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11991 context, pipe_config, pipe_name(crtc->pipe));
11992
11993 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11994 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11995 pipe_config->pipe_bpp, pipe_config->dither);
11996 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11997 pipe_config->has_pch_encoder,
11998 pipe_config->fdi_lanes,
11999 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12000 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12001 pipe_config->fdi_m_n.tu);
12002 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12003 pipe_config->has_dp_encoder,
12004 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12005 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12006 pipe_config->dp_m_n.tu);
12007
12008 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12009 pipe_config->has_dp_encoder,
12010 pipe_config->dp_m2_n2.gmch_m,
12011 pipe_config->dp_m2_n2.gmch_n,
12012 pipe_config->dp_m2_n2.link_m,
12013 pipe_config->dp_m2_n2.link_n,
12014 pipe_config->dp_m2_n2.tu);
12015
12016 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12017 pipe_config->has_audio,
12018 pipe_config->has_infoframe);
12019
12020 DRM_DEBUG_KMS("requested mode:\n");
12021 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12022 DRM_DEBUG_KMS("adjusted mode:\n");
12023 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12024 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12025 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12026 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12027 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12028 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12029 crtc->num_scalers,
12030 pipe_config->scaler_state.scaler_users,
12031 pipe_config->scaler_state.scaler_id);
12032 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12033 pipe_config->gmch_pfit.control,
12034 pipe_config->gmch_pfit.pgm_ratios,
12035 pipe_config->gmch_pfit.lvds_border_bits);
12036 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12037 pipe_config->pch_pfit.pos,
12038 pipe_config->pch_pfit.size,
12039 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12040 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12041 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12042
12043 if (IS_BROXTON(dev)) {
12044 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12045 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12046 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12047 pipe_config->ddi_pll_sel,
12048 pipe_config->dpll_hw_state.ebb0,
12049 pipe_config->dpll_hw_state.ebb4,
12050 pipe_config->dpll_hw_state.pll0,
12051 pipe_config->dpll_hw_state.pll1,
12052 pipe_config->dpll_hw_state.pll2,
12053 pipe_config->dpll_hw_state.pll3,
12054 pipe_config->dpll_hw_state.pll6,
12055 pipe_config->dpll_hw_state.pll8,
12056 pipe_config->dpll_hw_state.pll9,
12057 pipe_config->dpll_hw_state.pll10,
12058 pipe_config->dpll_hw_state.pcsdw12);
12059 } else if (IS_SKYLAKE(dev)) {
12060 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12061 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12062 pipe_config->ddi_pll_sel,
12063 pipe_config->dpll_hw_state.ctrl1,
12064 pipe_config->dpll_hw_state.cfgcr1,
12065 pipe_config->dpll_hw_state.cfgcr2);
12066 } else if (HAS_DDI(dev)) {
12067 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12068 pipe_config->ddi_pll_sel,
12069 pipe_config->dpll_hw_state.wrpll);
12070 } else {
12071 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12072 "fp0: 0x%x, fp1: 0x%x\n",
12073 pipe_config->dpll_hw_state.dpll,
12074 pipe_config->dpll_hw_state.dpll_md,
12075 pipe_config->dpll_hw_state.fp0,
12076 pipe_config->dpll_hw_state.fp1);
12077 }
12078
12079 DRM_DEBUG_KMS("planes on this crtc\n");
12080 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12081 intel_plane = to_intel_plane(plane);
12082 if (intel_plane->pipe != crtc->pipe)
12083 continue;
12084
12085 state = to_intel_plane_state(plane->state);
12086 fb = state->base.fb;
12087 if (!fb) {
12088 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12089 "disabled, scaler_id = %d\n",
12090 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12091 plane->base.id, intel_plane->pipe,
12092 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12093 drm_plane_index(plane), state->scaler_id);
12094 continue;
12095 }
12096
12097 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12098 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12099 plane->base.id, intel_plane->pipe,
12100 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12101 drm_plane_index(plane));
12102 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12103 fb->base.id, fb->width, fb->height, fb->pixel_format);
12104 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12105 state->scaler_id,
12106 state->src.x1 >> 16, state->src.y1 >> 16,
12107 drm_rect_width(&state->src) >> 16,
12108 drm_rect_height(&state->src) >> 16,
12109 state->dst.x1, state->dst.y1,
12110 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12111 }
12112 }
12113
12114 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12115 {
12116 struct drm_device *dev = state->dev;
12117 struct intel_encoder *encoder;
12118 struct drm_connector *connector;
12119 struct drm_connector_state *connector_state;
12120 unsigned int used_ports = 0;
12121 int i;
12122
12123 /*
12124 * Walk the connector list instead of the encoder
12125 * list to detect the problem on ddi platforms
12126 * where there's just one encoder per digital port.
12127 */
12128 for_each_connector_in_state(state, connector, connector_state, i) {
12129 if (!connector_state->best_encoder)
12130 continue;
12131
12132 encoder = to_intel_encoder(connector_state->best_encoder);
12133
12134 WARN_ON(!connector_state->crtc);
12135
12136 switch (encoder->type) {
12137 unsigned int port_mask;
12138 case INTEL_OUTPUT_UNKNOWN:
12139 if (WARN_ON(!HAS_DDI(dev)))
12140 break;
12141 case INTEL_OUTPUT_DISPLAYPORT:
12142 case INTEL_OUTPUT_HDMI:
12143 case INTEL_OUTPUT_EDP:
12144 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12145
12146 /* the same port mustn't appear more than once */
12147 if (used_ports & port_mask)
12148 return false;
12149
12150 used_ports |= port_mask;
12151 default:
12152 break;
12153 }
12154 }
12155
12156 return true;
12157 }
12158
12159 static void
12160 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12161 {
12162 struct drm_crtc_state tmp_state;
12163 struct intel_crtc_scaler_state scaler_state;
12164 struct intel_dpll_hw_state dpll_hw_state;
12165 enum intel_dpll_id shared_dpll;
12166 uint32_t ddi_pll_sel;
12167
12168 /* FIXME: before the switch to atomic started, a new pipe_config was
12169 * kzalloc'd. Code that depends on any field being zero should be
12170 * fixed, so that the crtc_state can be safely duplicated. For now,
12171 * only fields that are know to not cause problems are preserved. */
12172
12173 tmp_state = crtc_state->base;
12174 scaler_state = crtc_state->scaler_state;
12175 shared_dpll = crtc_state->shared_dpll;
12176 dpll_hw_state = crtc_state->dpll_hw_state;
12177 ddi_pll_sel = crtc_state->ddi_pll_sel;
12178
12179 memset(crtc_state, 0, sizeof *crtc_state);
12180
12181 crtc_state->base = tmp_state;
12182 crtc_state->scaler_state = scaler_state;
12183 crtc_state->shared_dpll = shared_dpll;
12184 crtc_state->dpll_hw_state = dpll_hw_state;
12185 crtc_state->ddi_pll_sel = ddi_pll_sel;
12186 }
12187
12188 static int
12189 intel_modeset_pipe_config(struct drm_crtc *crtc,
12190 struct intel_crtc_state *pipe_config)
12191 {
12192 struct drm_atomic_state *state = pipe_config->base.state;
12193 struct intel_encoder *encoder;
12194 struct drm_connector *connector;
12195 struct drm_connector_state *connector_state;
12196 int base_bpp, ret = -EINVAL;
12197 int i;
12198 bool retry = true;
12199
12200 clear_intel_crtc_state(pipe_config);
12201
12202 pipe_config->cpu_transcoder =
12203 (enum transcoder) to_intel_crtc(crtc)->pipe;
12204
12205 /*
12206 * Sanitize sync polarity flags based on requested ones. If neither
12207 * positive or negative polarity is requested, treat this as meaning
12208 * negative polarity.
12209 */
12210 if (!(pipe_config->base.adjusted_mode.flags &
12211 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12212 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12213
12214 if (!(pipe_config->base.adjusted_mode.flags &
12215 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12216 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12217
12218 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12219 * plane pixel format and any sink constraints into account. Returns the
12220 * source plane bpp so that dithering can be selected on mismatches
12221 * after encoders and crtc also have had their say. */
12222 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12223 pipe_config);
12224 if (base_bpp < 0)
12225 goto fail;
12226
12227 /*
12228 * Determine the real pipe dimensions. Note that stereo modes can
12229 * increase the actual pipe size due to the frame doubling and
12230 * insertion of additional space for blanks between the frame. This
12231 * is stored in the crtc timings. We use the requested mode to do this
12232 * computation to clearly distinguish it from the adjusted mode, which
12233 * can be changed by the connectors in the below retry loop.
12234 */
12235 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12236 &pipe_config->pipe_src_w,
12237 &pipe_config->pipe_src_h);
12238
12239 encoder_retry:
12240 /* Ensure the port clock defaults are reset when retrying. */
12241 pipe_config->port_clock = 0;
12242 pipe_config->pixel_multiplier = 1;
12243
12244 /* Fill in default crtc timings, allow encoders to overwrite them. */
12245 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12246 CRTC_STEREO_DOUBLE);
12247
12248 /* Pass our mode to the connectors and the CRTC to give them a chance to
12249 * adjust it according to limitations or connector properties, and also
12250 * a chance to reject the mode entirely.
12251 */
12252 for_each_connector_in_state(state, connector, connector_state, i) {
12253 if (connector_state->crtc != crtc)
12254 continue;
12255
12256 encoder = to_intel_encoder(connector_state->best_encoder);
12257
12258 if (!(encoder->compute_config(encoder, pipe_config))) {
12259 DRM_DEBUG_KMS("Encoder config failure\n");
12260 goto fail;
12261 }
12262 }
12263
12264 /* Set default port clock if not overwritten by the encoder. Needs to be
12265 * done afterwards in case the encoder adjusts the mode. */
12266 if (!pipe_config->port_clock)
12267 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12268 * pipe_config->pixel_multiplier;
12269
12270 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12271 if (ret < 0) {
12272 DRM_DEBUG_KMS("CRTC fixup failed\n");
12273 goto fail;
12274 }
12275
12276 if (ret == RETRY) {
12277 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12278 ret = -EINVAL;
12279 goto fail;
12280 }
12281
12282 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12283 retry = false;
12284 goto encoder_retry;
12285 }
12286
12287 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12288 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12289 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12290
12291 fail:
12292 return ret;
12293 }
12294
12295 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12296 {
12297 struct drm_encoder *encoder;
12298 struct drm_device *dev = crtc->dev;
12299
12300 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12301 if (encoder->crtc == crtc)
12302 return true;
12303
12304 return false;
12305 }
12306
12307 static void
12308 intel_modeset_update_state(struct drm_atomic_state *state)
12309 {
12310 struct drm_device *dev = state->dev;
12311 struct intel_encoder *intel_encoder;
12312 struct drm_crtc *crtc;
12313 struct drm_crtc_state *crtc_state;
12314 struct drm_connector *connector;
12315 int i;
12316
12317 intel_shared_dpll_commit(state);
12318
12319 for_each_intel_encoder(dev, intel_encoder) {
12320 if (!intel_encoder->base.crtc)
12321 continue;
12322
12323 crtc = intel_encoder->base.crtc;
12324 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12325 if (!crtc_state || !needs_modeset(crtc->state))
12326 continue;
12327
12328 intel_encoder->connectors_active = false;
12329 }
12330
12331 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12332 intel_modeset_update_staged_output_state(state->dev);
12333
12334 /* Double check state. */
12335 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12336 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12337
12338 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12339
12340 /* Update hwmode for vblank functions */
12341 if (crtc->state->active)
12342 crtc->hwmode = crtc->state->adjusted_mode;
12343 else
12344 crtc->hwmode.crtc_clock = 0;
12345 }
12346
12347 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12348 if (!connector->encoder || !connector->encoder->crtc)
12349 continue;
12350
12351 crtc = connector->encoder->crtc;
12352 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12353 if (!crtc_state || !needs_modeset(crtc->state))
12354 continue;
12355
12356 if (crtc->state->active) {
12357 struct drm_property *dpms_property =
12358 dev->mode_config.dpms_property;
12359
12360 connector->dpms = DRM_MODE_DPMS_ON;
12361 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12362
12363 intel_encoder = to_intel_encoder(connector->encoder);
12364 intel_encoder->connectors_active = true;
12365 } else
12366 connector->dpms = DRM_MODE_DPMS_OFF;
12367 }
12368 }
12369
12370 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12371 {
12372 int diff;
12373
12374 if (clock1 == clock2)
12375 return true;
12376
12377 if (!clock1 || !clock2)
12378 return false;
12379
12380 diff = abs(clock1 - clock2);
12381
12382 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12383 return true;
12384
12385 return false;
12386 }
12387
12388 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12389 list_for_each_entry((intel_crtc), \
12390 &(dev)->mode_config.crtc_list, \
12391 base.head) \
12392 if (mask & (1 <<(intel_crtc)->pipe))
12393
12394
12395 static bool
12396 intel_compare_m_n(unsigned int m, unsigned int n,
12397 unsigned int m2, unsigned int n2,
12398 bool exact)
12399 {
12400 if (m == m2 && n == n2)
12401 return true;
12402
12403 if (exact || !m || !n || !m2 || !n2)
12404 return false;
12405
12406 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12407
12408 if (m > m2) {
12409 while (m > m2) {
12410 m2 <<= 1;
12411 n2 <<= 1;
12412 }
12413 } else if (m < m2) {
12414 while (m < m2) {
12415 m <<= 1;
12416 n <<= 1;
12417 }
12418 }
12419
12420 return m == m2 && n == n2;
12421 }
12422
12423 static bool
12424 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12425 struct intel_link_m_n *m2_n2,
12426 bool adjust)
12427 {
12428 if (m_n->tu == m2_n2->tu &&
12429 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12430 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12431 intel_compare_m_n(m_n->link_m, m_n->link_n,
12432 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12433 if (adjust)
12434 *m2_n2 = *m_n;
12435
12436 return true;
12437 }
12438
12439 return false;
12440 }
12441
12442 static bool
12443 intel_pipe_config_compare(struct drm_device *dev,
12444 struct intel_crtc_state *current_config,
12445 struct intel_crtc_state *pipe_config,
12446 bool adjust)
12447 {
12448 bool ret = true;
12449
12450 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12451 do { \
12452 if (!adjust) \
12453 DRM_ERROR(fmt, ##__VA_ARGS__); \
12454 else \
12455 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12456 } while (0)
12457
12458 #define PIPE_CONF_CHECK_X(name) \
12459 if (current_config->name != pipe_config->name) { \
12460 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12461 "(expected 0x%08x, found 0x%08x)\n", \
12462 current_config->name, \
12463 pipe_config->name); \
12464 ret = false; \
12465 }
12466
12467 #define PIPE_CONF_CHECK_I(name) \
12468 if (current_config->name != pipe_config->name) { \
12469 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12470 "(expected %i, found %i)\n", \
12471 current_config->name, \
12472 pipe_config->name); \
12473 ret = false; \
12474 }
12475
12476 #define PIPE_CONF_CHECK_M_N(name) \
12477 if (!intel_compare_link_m_n(&current_config->name, \
12478 &pipe_config->name,\
12479 adjust)) { \
12480 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12481 "(expected tu %i gmch %i/%i link %i/%i, " \
12482 "found tu %i, gmch %i/%i link %i/%i)\n", \
12483 current_config->name.tu, \
12484 current_config->name.gmch_m, \
12485 current_config->name.gmch_n, \
12486 current_config->name.link_m, \
12487 current_config->name.link_n, \
12488 pipe_config->name.tu, \
12489 pipe_config->name.gmch_m, \
12490 pipe_config->name.gmch_n, \
12491 pipe_config->name.link_m, \
12492 pipe_config->name.link_n); \
12493 ret = false; \
12494 }
12495
12496 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12497 if (!intel_compare_link_m_n(&current_config->name, \
12498 &pipe_config->name, adjust) && \
12499 !intel_compare_link_m_n(&current_config->alt_name, \
12500 &pipe_config->name, adjust)) { \
12501 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12502 "(expected tu %i gmch %i/%i link %i/%i, " \
12503 "or tu %i gmch %i/%i link %i/%i, " \
12504 "found tu %i, gmch %i/%i link %i/%i)\n", \
12505 current_config->name.tu, \
12506 current_config->name.gmch_m, \
12507 current_config->name.gmch_n, \
12508 current_config->name.link_m, \
12509 current_config->name.link_n, \
12510 current_config->alt_name.tu, \
12511 current_config->alt_name.gmch_m, \
12512 current_config->alt_name.gmch_n, \
12513 current_config->alt_name.link_m, \
12514 current_config->alt_name.link_n, \
12515 pipe_config->name.tu, \
12516 pipe_config->name.gmch_m, \
12517 pipe_config->name.gmch_n, \
12518 pipe_config->name.link_m, \
12519 pipe_config->name.link_n); \
12520 ret = false; \
12521 }
12522
12523 /* This is required for BDW+ where there is only one set of registers for
12524 * switching between high and low RR.
12525 * This macro can be used whenever a comparison has to be made between one
12526 * hw state and multiple sw state variables.
12527 */
12528 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12529 if ((current_config->name != pipe_config->name) && \
12530 (current_config->alt_name != pipe_config->name)) { \
12531 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12532 "(expected %i or %i, found %i)\n", \
12533 current_config->name, \
12534 current_config->alt_name, \
12535 pipe_config->name); \
12536 ret = false; \
12537 }
12538
12539 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12540 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12541 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12542 "(expected %i, found %i)\n", \
12543 current_config->name & (mask), \
12544 pipe_config->name & (mask)); \
12545 ret = false; \
12546 }
12547
12548 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12549 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12550 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12551 "(expected %i, found %i)\n", \
12552 current_config->name, \
12553 pipe_config->name); \
12554 ret = false; \
12555 }
12556
12557 #define PIPE_CONF_QUIRK(quirk) \
12558 ((current_config->quirks | pipe_config->quirks) & (quirk))
12559
12560 PIPE_CONF_CHECK_I(cpu_transcoder);
12561
12562 PIPE_CONF_CHECK_I(has_pch_encoder);
12563 PIPE_CONF_CHECK_I(fdi_lanes);
12564 PIPE_CONF_CHECK_M_N(fdi_m_n);
12565
12566 PIPE_CONF_CHECK_I(has_dp_encoder);
12567
12568 if (INTEL_INFO(dev)->gen < 8) {
12569 PIPE_CONF_CHECK_M_N(dp_m_n);
12570
12571 PIPE_CONF_CHECK_I(has_drrs);
12572 if (current_config->has_drrs)
12573 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12574 } else
12575 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12576
12577 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12578 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12579 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12580 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12581 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12582 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12583
12584 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12585 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12586 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12587 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12588 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12589 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12590
12591 PIPE_CONF_CHECK_I(pixel_multiplier);
12592 PIPE_CONF_CHECK_I(has_hdmi_sink);
12593 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12594 IS_VALLEYVIEW(dev))
12595 PIPE_CONF_CHECK_I(limited_color_range);
12596 PIPE_CONF_CHECK_I(has_infoframe);
12597
12598 PIPE_CONF_CHECK_I(has_audio);
12599
12600 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12601 DRM_MODE_FLAG_INTERLACE);
12602
12603 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12604 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12605 DRM_MODE_FLAG_PHSYNC);
12606 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12607 DRM_MODE_FLAG_NHSYNC);
12608 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12609 DRM_MODE_FLAG_PVSYNC);
12610 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12611 DRM_MODE_FLAG_NVSYNC);
12612 }
12613
12614 PIPE_CONF_CHECK_I(pipe_src_w);
12615 PIPE_CONF_CHECK_I(pipe_src_h);
12616
12617 /*
12618 * FIXME: BIOS likes to set up a cloned config with lvds+external
12619 * screen. Since we don't yet re-compute the pipe config when moving
12620 * just the lvds port away to another pipe the sw tracking won't match.
12621 *
12622 * Proper atomic modesets with recomputed global state will fix this.
12623 * Until then just don't check gmch state for inherited modes.
12624 */
12625 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12626 PIPE_CONF_CHECK_I(gmch_pfit.control);
12627 /* pfit ratios are autocomputed by the hw on gen4+ */
12628 if (INTEL_INFO(dev)->gen < 4)
12629 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12630 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12631 }
12632
12633 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12634 if (current_config->pch_pfit.enabled) {
12635 PIPE_CONF_CHECK_I(pch_pfit.pos);
12636 PIPE_CONF_CHECK_I(pch_pfit.size);
12637 }
12638
12639 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12640
12641 /* BDW+ don't expose a synchronous way to read the state */
12642 if (IS_HASWELL(dev))
12643 PIPE_CONF_CHECK_I(ips_enabled);
12644
12645 PIPE_CONF_CHECK_I(double_wide);
12646
12647 PIPE_CONF_CHECK_X(ddi_pll_sel);
12648
12649 PIPE_CONF_CHECK_I(shared_dpll);
12650 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12651 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12652 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12653 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12654 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12655 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12656 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12657 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12658
12659 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12660 PIPE_CONF_CHECK_I(pipe_bpp);
12661
12662 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12663 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12664
12665 #undef PIPE_CONF_CHECK_X
12666 #undef PIPE_CONF_CHECK_I
12667 #undef PIPE_CONF_CHECK_I_ALT
12668 #undef PIPE_CONF_CHECK_FLAGS
12669 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12670 #undef PIPE_CONF_QUIRK
12671 #undef INTEL_ERR_OR_DBG_KMS
12672
12673 return ret;
12674 }
12675
12676 static void check_wm_state(struct drm_device *dev)
12677 {
12678 struct drm_i915_private *dev_priv = dev->dev_private;
12679 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12680 struct intel_crtc *intel_crtc;
12681 int plane;
12682
12683 if (INTEL_INFO(dev)->gen < 9)
12684 return;
12685
12686 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12687 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12688
12689 for_each_intel_crtc(dev, intel_crtc) {
12690 struct skl_ddb_entry *hw_entry, *sw_entry;
12691 const enum pipe pipe = intel_crtc->pipe;
12692
12693 if (!intel_crtc->active)
12694 continue;
12695
12696 /* planes */
12697 for_each_plane(dev_priv, pipe, plane) {
12698 hw_entry = &hw_ddb.plane[pipe][plane];
12699 sw_entry = &sw_ddb->plane[pipe][plane];
12700
12701 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12702 continue;
12703
12704 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12705 "(expected (%u,%u), found (%u,%u))\n",
12706 pipe_name(pipe), plane + 1,
12707 sw_entry->start, sw_entry->end,
12708 hw_entry->start, hw_entry->end);
12709 }
12710
12711 /* cursor */
12712 hw_entry = &hw_ddb.cursor[pipe];
12713 sw_entry = &sw_ddb->cursor[pipe];
12714
12715 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12716 continue;
12717
12718 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12719 "(expected (%u,%u), found (%u,%u))\n",
12720 pipe_name(pipe),
12721 sw_entry->start, sw_entry->end,
12722 hw_entry->start, hw_entry->end);
12723 }
12724 }
12725
12726 static void
12727 check_connector_state(struct drm_device *dev)
12728 {
12729 struct intel_connector *connector;
12730
12731 for_each_intel_connector(dev, connector) {
12732 /* This also checks the encoder/connector hw state with the
12733 * ->get_hw_state callbacks. */
12734 intel_connector_check_state(connector);
12735
12736 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12737 "connector's staged encoder doesn't match current encoder\n");
12738 }
12739 }
12740
12741 static void
12742 check_encoder_state(struct drm_device *dev)
12743 {
12744 struct intel_encoder *encoder;
12745 struct intel_connector *connector;
12746
12747 for_each_intel_encoder(dev, encoder) {
12748 bool enabled = false;
12749 bool active = false;
12750 enum pipe pipe, tracked_pipe;
12751
12752 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12753 encoder->base.base.id,
12754 encoder->base.name);
12755
12756 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12757 "encoder's stage crtc doesn't match current crtc\n");
12758 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12759 "encoder's active_connectors set, but no crtc\n");
12760
12761 for_each_intel_connector(dev, connector) {
12762 if (connector->base.encoder != &encoder->base)
12763 continue;
12764 enabled = true;
12765 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12766 active = true;
12767 }
12768 /*
12769 * for MST connectors if we unplug the connector is gone
12770 * away but the encoder is still connected to a crtc
12771 * until a modeset happens in response to the hotplug.
12772 */
12773 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12774 continue;
12775
12776 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12777 "encoder's enabled state mismatch "
12778 "(expected %i, found %i)\n",
12779 !!encoder->base.crtc, enabled);
12780 I915_STATE_WARN(active && !encoder->base.crtc,
12781 "active encoder with no crtc\n");
12782
12783 I915_STATE_WARN(encoder->connectors_active != active,
12784 "encoder's computed active state doesn't match tracked active state "
12785 "(expected %i, found %i)\n", active, encoder->connectors_active);
12786
12787 active = encoder->get_hw_state(encoder, &pipe);
12788 I915_STATE_WARN(active != encoder->connectors_active,
12789 "encoder's hw state doesn't match sw tracking "
12790 "(expected %i, found %i)\n",
12791 encoder->connectors_active, active);
12792
12793 if (!encoder->base.crtc)
12794 continue;
12795
12796 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12797 I915_STATE_WARN(active && pipe != tracked_pipe,
12798 "active encoder's pipe doesn't match"
12799 "(expected %i, found %i)\n",
12800 tracked_pipe, pipe);
12801
12802 }
12803 }
12804
12805 static void
12806 check_crtc_state(struct drm_device *dev)
12807 {
12808 struct drm_i915_private *dev_priv = dev->dev_private;
12809 struct intel_crtc *crtc;
12810 struct intel_encoder *encoder;
12811 struct intel_crtc_state pipe_config;
12812
12813 for_each_intel_crtc(dev, crtc) {
12814 bool enabled = false;
12815 bool active = false;
12816
12817 memset(&pipe_config, 0, sizeof(pipe_config));
12818
12819 DRM_DEBUG_KMS("[CRTC:%d]\n",
12820 crtc->base.base.id);
12821
12822 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12823 "active crtc, but not enabled in sw tracking\n");
12824
12825 for_each_intel_encoder(dev, encoder) {
12826 if (encoder->base.crtc != &crtc->base)
12827 continue;
12828 enabled = true;
12829 if (encoder->connectors_active)
12830 active = true;
12831 }
12832
12833 I915_STATE_WARN(active != crtc->active,
12834 "crtc's computed active state doesn't match tracked active state "
12835 "(expected %i, found %i)\n", active, crtc->active);
12836 I915_STATE_WARN(enabled != crtc->base.state->enable,
12837 "crtc's computed enabled state doesn't match tracked enabled state "
12838 "(expected %i, found %i)\n", enabled,
12839 crtc->base.state->enable);
12840
12841 active = dev_priv->display.get_pipe_config(crtc,
12842 &pipe_config);
12843
12844 /* hw state is inconsistent with the pipe quirk */
12845 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12846 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12847 active = crtc->active;
12848
12849 for_each_intel_encoder(dev, encoder) {
12850 enum pipe pipe;
12851 if (encoder->base.crtc != &crtc->base)
12852 continue;
12853 if (encoder->get_hw_state(encoder, &pipe))
12854 encoder->get_config(encoder, &pipe_config);
12855 }
12856
12857 I915_STATE_WARN(crtc->active != active,
12858 "crtc active state doesn't match with hw state "
12859 "(expected %i, found %i)\n", crtc->active, active);
12860
12861 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12862 "transitional active state does not match atomic hw state "
12863 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12864
12865 if (!active)
12866 continue;
12867
12868 if (!intel_pipe_config_compare(dev, crtc->config,
12869 &pipe_config, false)) {
12870 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12871 intel_dump_pipe_config(crtc, &pipe_config,
12872 "[hw state]");
12873 intel_dump_pipe_config(crtc, crtc->config,
12874 "[sw state]");
12875 }
12876 }
12877 }
12878
12879 static void
12880 check_shared_dpll_state(struct drm_device *dev)
12881 {
12882 struct drm_i915_private *dev_priv = dev->dev_private;
12883 struct intel_crtc *crtc;
12884 struct intel_dpll_hw_state dpll_hw_state;
12885 int i;
12886
12887 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12888 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12889 int enabled_crtcs = 0, active_crtcs = 0;
12890 bool active;
12891
12892 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12893
12894 DRM_DEBUG_KMS("%s\n", pll->name);
12895
12896 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12897
12898 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12899 "more active pll users than references: %i vs %i\n",
12900 pll->active, hweight32(pll->config.crtc_mask));
12901 I915_STATE_WARN(pll->active && !pll->on,
12902 "pll in active use but not on in sw tracking\n");
12903 I915_STATE_WARN(pll->on && !pll->active,
12904 "pll in on but not on in use in sw tracking\n");
12905 I915_STATE_WARN(pll->on != active,
12906 "pll on state mismatch (expected %i, found %i)\n",
12907 pll->on, active);
12908
12909 for_each_intel_crtc(dev, crtc) {
12910 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12911 enabled_crtcs++;
12912 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12913 active_crtcs++;
12914 }
12915 I915_STATE_WARN(pll->active != active_crtcs,
12916 "pll active crtcs mismatch (expected %i, found %i)\n",
12917 pll->active, active_crtcs);
12918 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12919 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12920 hweight32(pll->config.crtc_mask), enabled_crtcs);
12921
12922 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12923 sizeof(dpll_hw_state)),
12924 "pll hw state mismatch\n");
12925 }
12926 }
12927
12928 void
12929 intel_modeset_check_state(struct drm_device *dev)
12930 {
12931 check_wm_state(dev);
12932 check_connector_state(dev);
12933 check_encoder_state(dev);
12934 check_crtc_state(dev);
12935 check_shared_dpll_state(dev);
12936 }
12937
12938 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12939 int dotclock)
12940 {
12941 /*
12942 * FDI already provided one idea for the dotclock.
12943 * Yell if the encoder disagrees.
12944 */
12945 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12946 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12947 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12948 }
12949
12950 static void update_scanline_offset(struct intel_crtc *crtc)
12951 {
12952 struct drm_device *dev = crtc->base.dev;
12953
12954 /*
12955 * The scanline counter increments at the leading edge of hsync.
12956 *
12957 * On most platforms it starts counting from vtotal-1 on the
12958 * first active line. That means the scanline counter value is
12959 * always one less than what we would expect. Ie. just after
12960 * start of vblank, which also occurs at start of hsync (on the
12961 * last active line), the scanline counter will read vblank_start-1.
12962 *
12963 * On gen2 the scanline counter starts counting from 1 instead
12964 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12965 * to keep the value positive), instead of adding one.
12966 *
12967 * On HSW+ the behaviour of the scanline counter depends on the output
12968 * type. For DP ports it behaves like most other platforms, but on HDMI
12969 * there's an extra 1 line difference. So we need to add two instead of
12970 * one to the value.
12971 */
12972 if (IS_GEN2(dev)) {
12973 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12974 int vtotal;
12975
12976 vtotal = mode->crtc_vtotal;
12977 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12978 vtotal /= 2;
12979
12980 crtc->scanline_offset = vtotal - 1;
12981 } else if (HAS_DDI(dev) &&
12982 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12983 crtc->scanline_offset = 2;
12984 } else
12985 crtc->scanline_offset = 1;
12986 }
12987
12988 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12989 {
12990 struct drm_device *dev = state->dev;
12991 struct drm_i915_private *dev_priv = to_i915(dev);
12992 struct intel_shared_dpll_config *shared_dpll = NULL;
12993 struct intel_crtc *intel_crtc;
12994 struct intel_crtc_state *intel_crtc_state;
12995 struct drm_crtc *crtc;
12996 struct drm_crtc_state *crtc_state;
12997 int i;
12998
12999 if (!dev_priv->display.crtc_compute_clock)
13000 return;
13001
13002 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13003 int dpll;
13004
13005 intel_crtc = to_intel_crtc(crtc);
13006 intel_crtc_state = to_intel_crtc_state(crtc_state);
13007 dpll = intel_crtc_state->shared_dpll;
13008
13009 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13010 continue;
13011
13012 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13013
13014 if (!shared_dpll)
13015 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13016
13017 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13018 }
13019 }
13020
13021 /*
13022 * This implements the workaround described in the "notes" section of the mode
13023 * set sequence documentation. When going from no pipes or single pipe to
13024 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13025 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13026 */
13027 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13028 {
13029 struct drm_crtc_state *crtc_state;
13030 struct intel_crtc *intel_crtc;
13031 struct drm_crtc *crtc;
13032 struct intel_crtc_state *first_crtc_state = NULL;
13033 struct intel_crtc_state *other_crtc_state = NULL;
13034 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13035 int i;
13036
13037 /* look at all crtc's that are going to be enabled in during modeset */
13038 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13039 intel_crtc = to_intel_crtc(crtc);
13040
13041 if (!crtc_state->active || !needs_modeset(crtc_state))
13042 continue;
13043
13044 if (first_crtc_state) {
13045 other_crtc_state = to_intel_crtc_state(crtc_state);
13046 break;
13047 } else {
13048 first_crtc_state = to_intel_crtc_state(crtc_state);
13049 first_pipe = intel_crtc->pipe;
13050 }
13051 }
13052
13053 /* No workaround needed? */
13054 if (!first_crtc_state)
13055 return 0;
13056
13057 /* w/a possibly needed, check how many crtc's are already enabled. */
13058 for_each_intel_crtc(state->dev, intel_crtc) {
13059 struct intel_crtc_state *pipe_config;
13060
13061 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13062 if (IS_ERR(pipe_config))
13063 return PTR_ERR(pipe_config);
13064
13065 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13066
13067 if (!pipe_config->base.active ||
13068 needs_modeset(&pipe_config->base))
13069 continue;
13070
13071 /* 2 or more enabled crtcs means no need for w/a */
13072 if (enabled_pipe != INVALID_PIPE)
13073 return 0;
13074
13075 enabled_pipe = intel_crtc->pipe;
13076 }
13077
13078 if (enabled_pipe != INVALID_PIPE)
13079 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13080 else if (other_crtc_state)
13081 other_crtc_state->hsw_workaround_pipe = first_pipe;
13082
13083 return 0;
13084 }
13085
13086 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13087 {
13088 struct drm_crtc *crtc;
13089 struct drm_crtc_state *crtc_state;
13090 int ret = 0;
13091
13092 /* add all active pipes to the state */
13093 for_each_crtc(state->dev, crtc) {
13094 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13095 if (IS_ERR(crtc_state))
13096 return PTR_ERR(crtc_state);
13097
13098 if (!crtc_state->active || needs_modeset(crtc_state))
13099 continue;
13100
13101 crtc_state->mode_changed = true;
13102
13103 ret = drm_atomic_add_affected_connectors(state, crtc);
13104 if (ret)
13105 break;
13106
13107 ret = drm_atomic_add_affected_planes(state, crtc);
13108 if (ret)
13109 break;
13110 }
13111
13112 return ret;
13113 }
13114
13115
13116 /* Code that should eventually be part of atomic_check() */
13117 static int intel_modeset_checks(struct drm_atomic_state *state)
13118 {
13119 struct drm_device *dev = state->dev;
13120 struct drm_i915_private *dev_priv = dev->dev_private;
13121 int ret;
13122
13123 if (!check_digital_port_conflicts(state)) {
13124 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13125 return -EINVAL;
13126 }
13127
13128 /*
13129 * See if the config requires any additional preparation, e.g.
13130 * to adjust global state with pipes off. We need to do this
13131 * here so we can get the modeset_pipe updated config for the new
13132 * mode set on this crtc. For other crtcs we need to use the
13133 * adjusted_mode bits in the crtc directly.
13134 */
13135 if (dev_priv->display.modeset_calc_cdclk) {
13136 unsigned int cdclk;
13137
13138 ret = dev_priv->display.modeset_calc_cdclk(state);
13139
13140 cdclk = to_intel_atomic_state(state)->cdclk;
13141 if (!ret && cdclk != dev_priv->cdclk_freq)
13142 ret = intel_modeset_all_pipes(state);
13143
13144 if (ret < 0)
13145 return ret;
13146 } else
13147 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13148
13149 intel_modeset_clear_plls(state);
13150
13151 if (IS_HASWELL(dev))
13152 return haswell_mode_set_planes_workaround(state);
13153
13154 return 0;
13155 }
13156
13157 static int
13158 intel_modeset_compute_config(struct drm_atomic_state *state)
13159 {
13160 struct drm_crtc *crtc;
13161 struct drm_crtc_state *crtc_state;
13162 int ret, i;
13163 bool any_ms = false;
13164
13165 ret = drm_atomic_helper_check_modeset(state->dev, state);
13166 if (ret)
13167 return ret;
13168
13169 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13170 struct intel_crtc_state *pipe_config =
13171 to_intel_crtc_state(crtc_state);
13172 bool modeset, recalc;
13173
13174 if (!crtc_state->enable) {
13175 if (needs_modeset(crtc_state))
13176 any_ms = true;
13177 continue;
13178 }
13179
13180 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13181 ret = drm_atomic_add_affected_planes(state, crtc);
13182 if (ret)
13183 return ret;
13184
13185 /*
13186 * We ought to handle i915.fastboot here.
13187 * If no modeset is required and the primary plane has
13188 * a fb, update the members of crtc_state as needed,
13189 * and run the necessary updates during vblank evasion.
13190 */
13191 }
13192
13193 modeset = needs_modeset(crtc_state);
13194 recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
13195
13196 if (!modeset && !recalc)
13197 continue;
13198
13199 if (recalc) {
13200 ret = drm_atomic_add_affected_connectors(state, crtc);
13201 if (ret)
13202 return ret;
13203 }
13204
13205 ret = intel_modeset_pipe_config(crtc, pipe_config);
13206 if (ret)
13207 return ret;
13208
13209 if (recalc && !intel_pipe_config_compare(state->dev,
13210 to_intel_crtc_state(crtc->state),
13211 pipe_config, true)) {
13212 modeset = crtc_state->mode_changed = true;
13213
13214 ret = drm_atomic_add_affected_planes(state, crtc);
13215 if (ret)
13216 return ret;
13217 }
13218
13219 any_ms = modeset;
13220 intel_dump_pipe_config(to_intel_crtc(crtc),
13221 pipe_config,
13222 modeset ? "[modeset]" : "[fastboot]");
13223 }
13224
13225 if (any_ms) {
13226 ret = intel_modeset_checks(state);
13227
13228 if (ret)
13229 return ret;
13230 } else
13231 to_intel_atomic_state(state)->cdclk =
13232 to_i915(state->dev)->cdclk_freq;
13233
13234 return drm_atomic_helper_check_planes(state->dev, state);
13235 }
13236
13237 static int __intel_set_mode(struct drm_atomic_state *state)
13238 {
13239 struct drm_device *dev = state->dev;
13240 struct drm_i915_private *dev_priv = dev->dev_private;
13241 struct drm_crtc *crtc;
13242 struct drm_crtc_state *crtc_state;
13243 int ret = 0;
13244 int i;
13245 bool any_ms = false;
13246
13247 ret = drm_atomic_helper_prepare_planes(dev, state);
13248 if (ret)
13249 return ret;
13250
13251 drm_atomic_helper_swap_state(dev, state);
13252
13253 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13255
13256 if (!needs_modeset(crtc->state))
13257 continue;
13258
13259 any_ms = true;
13260 intel_pre_plane_update(intel_crtc);
13261
13262 if (crtc_state->active) {
13263 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13264 dev_priv->display.crtc_disable(crtc);
13265 intel_crtc->active = false;
13266 intel_disable_shared_dpll(intel_crtc);
13267 }
13268 }
13269
13270 /* Only after disabling all output pipelines that will be changed can we
13271 * update the the output configuration. */
13272 intel_modeset_update_state(state);
13273
13274 /* The state has been swaped above, so state actually contains the
13275 * old state now. */
13276 if (any_ms)
13277 modeset_update_crtc_power_domains(state);
13278
13279 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13280 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13281 if (needs_modeset(crtc->state) && crtc->state->active) {
13282 update_scanline_offset(to_intel_crtc(crtc));
13283 dev_priv->display.crtc_enable(crtc);
13284 }
13285
13286 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13287 }
13288
13289 /* FIXME: add subpixel order */
13290
13291 drm_atomic_helper_cleanup_planes(dev, state);
13292
13293 drm_atomic_state_free(state);
13294
13295 return 0;
13296 }
13297
13298 static int intel_set_mode_checked(struct drm_atomic_state *state)
13299 {
13300 struct drm_device *dev = state->dev;
13301 int ret;
13302
13303 ret = __intel_set_mode(state);
13304 if (ret == 0)
13305 intel_modeset_check_state(dev);
13306
13307 return ret;
13308 }
13309
13310 static int intel_set_mode(struct drm_atomic_state *state)
13311 {
13312 int ret;
13313
13314 ret = intel_modeset_compute_config(state);
13315 if (ret)
13316 return ret;
13317
13318 return intel_set_mode_checked(state);
13319 }
13320
13321 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13322 {
13323 struct drm_device *dev = crtc->dev;
13324 struct drm_atomic_state *state;
13325 struct intel_encoder *encoder;
13326 struct intel_connector *connector;
13327 struct drm_connector_state *connector_state;
13328 struct intel_crtc_state *crtc_state;
13329 int ret;
13330
13331 state = drm_atomic_state_alloc(dev);
13332 if (!state) {
13333 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13334 crtc->base.id);
13335 return;
13336 }
13337
13338 state->acquire_ctx = dev->mode_config.acquire_ctx;
13339
13340 /* The force restore path in the HW readout code relies on the staged
13341 * config still keeping the user requested config while the actual
13342 * state has been overwritten by the configuration read from HW. We
13343 * need to copy the staged config to the atomic state, otherwise the
13344 * mode set will just reapply the state the HW is already in. */
13345 for_each_intel_encoder(dev, encoder) {
13346 if (&encoder->new_crtc->base != crtc)
13347 continue;
13348
13349 for_each_intel_connector(dev, connector) {
13350 if (connector->new_encoder != encoder)
13351 continue;
13352
13353 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13354 if (IS_ERR(connector_state)) {
13355 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13356 connector->base.base.id,
13357 connector->base.name,
13358 PTR_ERR(connector_state));
13359 continue;
13360 }
13361
13362 connector_state->crtc = crtc;
13363 connector_state->best_encoder = &encoder->base;
13364 }
13365 }
13366
13367 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13368 if (IS_ERR(crtc_state)) {
13369 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13370 crtc->base.id, PTR_ERR(crtc_state));
13371 drm_atomic_state_free(state);
13372 return;
13373 }
13374
13375 crtc_state->base.active = crtc_state->base.enable =
13376 to_intel_crtc(crtc)->new_enabled;
13377
13378 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13379
13380 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13381 crtc->primary->fb, crtc->x, crtc->y);
13382
13383 ret = intel_set_mode(state);
13384 if (ret)
13385 drm_atomic_state_free(state);
13386 }
13387
13388 #undef for_each_intel_crtc_masked
13389
13390 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13391 struct drm_mode_set *set)
13392 {
13393 int ro;
13394
13395 for (ro = 0; ro < set->num_connectors; ro++)
13396 if (set->connectors[ro] == &connector->base)
13397 return true;
13398
13399 return false;
13400 }
13401
13402 static int
13403 intel_modeset_stage_output_state(struct drm_device *dev,
13404 struct drm_mode_set *set,
13405 struct drm_atomic_state *state)
13406 {
13407 struct intel_connector *connector;
13408 struct drm_connector *drm_connector;
13409 struct drm_connector_state *connector_state;
13410 struct drm_crtc *crtc;
13411 struct drm_crtc_state *crtc_state;
13412 int i, ret;
13413
13414 /* The upper layers ensure that we either disable a crtc or have a list
13415 * of connectors. For paranoia, double-check this. */
13416 WARN_ON(!set->fb && (set->num_connectors != 0));
13417 WARN_ON(set->fb && (set->num_connectors == 0));
13418
13419 for_each_intel_connector(dev, connector) {
13420 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13421
13422 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13423 continue;
13424
13425 connector_state =
13426 drm_atomic_get_connector_state(state, &connector->base);
13427 if (IS_ERR(connector_state))
13428 return PTR_ERR(connector_state);
13429
13430 if (in_mode_set) {
13431 int pipe = to_intel_crtc(set->crtc)->pipe;
13432 connector_state->best_encoder =
13433 &intel_find_encoder(connector, pipe)->base;
13434 }
13435
13436 if (connector->base.state->crtc != set->crtc)
13437 continue;
13438
13439 /* If we disable the crtc, disable all its connectors. Also, if
13440 * the connector is on the changing crtc but not on the new
13441 * connector list, disable it. */
13442 if (!set->fb || !in_mode_set) {
13443 connector_state->best_encoder = NULL;
13444
13445 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13446 connector->base.base.id,
13447 connector->base.name);
13448 }
13449 }
13450 /* connector->new_encoder is now updated for all connectors. */
13451
13452 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13453 connector = to_intel_connector(drm_connector);
13454
13455 if (!connector_state->best_encoder) {
13456 ret = drm_atomic_set_crtc_for_connector(connector_state,
13457 NULL);
13458 if (ret)
13459 return ret;
13460
13461 continue;
13462 }
13463
13464 if (intel_connector_in_mode_set(connector, set)) {
13465 struct drm_crtc *crtc = connector->base.state->crtc;
13466
13467 /* If this connector was in a previous crtc, add it
13468 * to the state. We might need to disable it. */
13469 if (crtc) {
13470 crtc_state =
13471 drm_atomic_get_crtc_state(state, crtc);
13472 if (IS_ERR(crtc_state))
13473 return PTR_ERR(crtc_state);
13474 }
13475
13476 ret = drm_atomic_set_crtc_for_connector(connector_state,
13477 set->crtc);
13478 if (ret)
13479 return ret;
13480 }
13481
13482 /* Make sure the new CRTC will work with the encoder */
13483 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13484 connector_state->crtc)) {
13485 return -EINVAL;
13486 }
13487
13488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13489 connector->base.base.id,
13490 connector->base.name,
13491 connector_state->crtc->base.id);
13492
13493 if (connector_state->best_encoder != &connector->encoder->base)
13494 connector->encoder =
13495 to_intel_encoder(connector_state->best_encoder);
13496 }
13497
13498 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13499 bool has_connectors;
13500
13501 ret = drm_atomic_add_affected_connectors(state, crtc);
13502 if (ret)
13503 return ret;
13504
13505 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13506 if (has_connectors != crtc_state->enable)
13507 crtc_state->enable =
13508 crtc_state->active = has_connectors;
13509 }
13510
13511 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13512 set->fb, set->x, set->y);
13513 if (ret)
13514 return ret;
13515
13516 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13517 if (IS_ERR(crtc_state))
13518 return PTR_ERR(crtc_state);
13519
13520 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13521 if (ret)
13522 return ret;
13523
13524 if (set->num_connectors)
13525 crtc_state->active = true;
13526
13527 return 0;
13528 }
13529
13530 static int intel_crtc_set_config(struct drm_mode_set *set)
13531 {
13532 struct drm_device *dev;
13533 struct drm_atomic_state *state = NULL;
13534 int ret;
13535
13536 BUG_ON(!set);
13537 BUG_ON(!set->crtc);
13538 BUG_ON(!set->crtc->helper_private);
13539
13540 /* Enforce sane interface api - has been abused by the fb helper. */
13541 BUG_ON(!set->mode && set->fb);
13542 BUG_ON(set->fb && set->num_connectors == 0);
13543
13544 if (set->fb) {
13545 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13546 set->crtc->base.id, set->fb->base.id,
13547 (int)set->num_connectors, set->x, set->y);
13548 } else {
13549 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13550 }
13551
13552 dev = set->crtc->dev;
13553
13554 state = drm_atomic_state_alloc(dev);
13555 if (!state)
13556 return -ENOMEM;
13557
13558 state->acquire_ctx = dev->mode_config.acquire_ctx;
13559
13560 ret = intel_modeset_stage_output_state(dev, set, state);
13561 if (ret)
13562 goto out;
13563
13564 ret = intel_modeset_compute_config(state);
13565 if (ret)
13566 goto out;
13567
13568 intel_update_pipe_size(to_intel_crtc(set->crtc));
13569
13570 ret = intel_set_mode_checked(state);
13571 if (ret) {
13572 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13573 set->crtc->base.id, ret);
13574 }
13575
13576 out:
13577 if (ret)
13578 drm_atomic_state_free(state);
13579 return ret;
13580 }
13581
13582 static const struct drm_crtc_funcs intel_crtc_funcs = {
13583 .gamma_set = intel_crtc_gamma_set,
13584 .set_config = intel_crtc_set_config,
13585 .destroy = intel_crtc_destroy,
13586 .page_flip = intel_crtc_page_flip,
13587 .atomic_duplicate_state = intel_crtc_duplicate_state,
13588 .atomic_destroy_state = intel_crtc_destroy_state,
13589 };
13590
13591 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13592 struct intel_shared_dpll *pll,
13593 struct intel_dpll_hw_state *hw_state)
13594 {
13595 uint32_t val;
13596
13597 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13598 return false;
13599
13600 val = I915_READ(PCH_DPLL(pll->id));
13601 hw_state->dpll = val;
13602 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13603 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13604
13605 return val & DPLL_VCO_ENABLE;
13606 }
13607
13608 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13609 struct intel_shared_dpll *pll)
13610 {
13611 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13612 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13613 }
13614
13615 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13616 struct intel_shared_dpll *pll)
13617 {
13618 /* PCH refclock must be enabled first */
13619 ibx_assert_pch_refclk_enabled(dev_priv);
13620
13621 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13622
13623 /* Wait for the clocks to stabilize. */
13624 POSTING_READ(PCH_DPLL(pll->id));
13625 udelay(150);
13626
13627 /* The pixel multiplier can only be updated once the
13628 * DPLL is enabled and the clocks are stable.
13629 *
13630 * So write it again.
13631 */
13632 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13633 POSTING_READ(PCH_DPLL(pll->id));
13634 udelay(200);
13635 }
13636
13637 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13638 struct intel_shared_dpll *pll)
13639 {
13640 struct drm_device *dev = dev_priv->dev;
13641 struct intel_crtc *crtc;
13642
13643 /* Make sure no transcoder isn't still depending on us. */
13644 for_each_intel_crtc(dev, crtc) {
13645 if (intel_crtc_to_shared_dpll(crtc) == pll)
13646 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13647 }
13648
13649 I915_WRITE(PCH_DPLL(pll->id), 0);
13650 POSTING_READ(PCH_DPLL(pll->id));
13651 udelay(200);
13652 }
13653
13654 static char *ibx_pch_dpll_names[] = {
13655 "PCH DPLL A",
13656 "PCH DPLL B",
13657 };
13658
13659 static void ibx_pch_dpll_init(struct drm_device *dev)
13660 {
13661 struct drm_i915_private *dev_priv = dev->dev_private;
13662 int i;
13663
13664 dev_priv->num_shared_dpll = 2;
13665
13666 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13667 dev_priv->shared_dplls[i].id = i;
13668 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13669 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13670 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13671 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13672 dev_priv->shared_dplls[i].get_hw_state =
13673 ibx_pch_dpll_get_hw_state;
13674 }
13675 }
13676
13677 static void intel_shared_dpll_init(struct drm_device *dev)
13678 {
13679 struct drm_i915_private *dev_priv = dev->dev_private;
13680
13681 intel_update_cdclk(dev);
13682
13683 if (HAS_DDI(dev))
13684 intel_ddi_pll_init(dev);
13685 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13686 ibx_pch_dpll_init(dev);
13687 else
13688 dev_priv->num_shared_dpll = 0;
13689
13690 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13691 }
13692
13693 /**
13694 * intel_prepare_plane_fb - Prepare fb for usage on plane
13695 * @plane: drm plane to prepare for
13696 * @fb: framebuffer to prepare for presentation
13697 *
13698 * Prepares a framebuffer for usage on a display plane. Generally this
13699 * involves pinning the underlying object and updating the frontbuffer tracking
13700 * bits. Some older platforms need special physical address handling for
13701 * cursor planes.
13702 *
13703 * Returns 0 on success, negative error code on failure.
13704 */
13705 int
13706 intel_prepare_plane_fb(struct drm_plane *plane,
13707 struct drm_framebuffer *fb,
13708 const struct drm_plane_state *new_state)
13709 {
13710 struct drm_device *dev = plane->dev;
13711 struct intel_plane *intel_plane = to_intel_plane(plane);
13712 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13713 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13714 int ret = 0;
13715
13716 if (!obj)
13717 return 0;
13718
13719 mutex_lock(&dev->struct_mutex);
13720
13721 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13722 INTEL_INFO(dev)->cursor_needs_physical) {
13723 int align = IS_I830(dev) ? 16 * 1024 : 256;
13724 ret = i915_gem_object_attach_phys(obj, align);
13725 if (ret)
13726 DRM_DEBUG_KMS("failed to attach phys object\n");
13727 } else {
13728 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13729 }
13730
13731 if (ret == 0)
13732 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13733
13734 mutex_unlock(&dev->struct_mutex);
13735
13736 return ret;
13737 }
13738
13739 /**
13740 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13741 * @plane: drm plane to clean up for
13742 * @fb: old framebuffer that was on plane
13743 *
13744 * Cleans up a framebuffer that has just been removed from a plane.
13745 */
13746 void
13747 intel_cleanup_plane_fb(struct drm_plane *plane,
13748 struct drm_framebuffer *fb,
13749 const struct drm_plane_state *old_state)
13750 {
13751 struct drm_device *dev = plane->dev;
13752 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13753
13754 if (WARN_ON(!obj))
13755 return;
13756
13757 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13758 !INTEL_INFO(dev)->cursor_needs_physical) {
13759 mutex_lock(&dev->struct_mutex);
13760 intel_unpin_fb_obj(fb, old_state);
13761 mutex_unlock(&dev->struct_mutex);
13762 }
13763 }
13764
13765 int
13766 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13767 {
13768 int max_scale;
13769 struct drm_device *dev;
13770 struct drm_i915_private *dev_priv;
13771 int crtc_clock, cdclk;
13772
13773 if (!intel_crtc || !crtc_state)
13774 return DRM_PLANE_HELPER_NO_SCALING;
13775
13776 dev = intel_crtc->base.dev;
13777 dev_priv = dev->dev_private;
13778 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13779 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13780
13781 if (!crtc_clock || !cdclk)
13782 return DRM_PLANE_HELPER_NO_SCALING;
13783
13784 /*
13785 * skl max scale is lower of:
13786 * close to 3 but not 3, -1 is for that purpose
13787 * or
13788 * cdclk/crtc_clock
13789 */
13790 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13791
13792 return max_scale;
13793 }
13794
13795 static int
13796 intel_check_primary_plane(struct drm_plane *plane,
13797 struct intel_crtc_state *crtc_state,
13798 struct intel_plane_state *state)
13799 {
13800 struct drm_crtc *crtc = state->base.crtc;
13801 struct drm_framebuffer *fb = state->base.fb;
13802 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13803 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13804 bool can_position = false;
13805
13806 /* use scaler when colorkey is not required */
13807 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13808 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13809 min_scale = 1;
13810 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13811 can_position = true;
13812 }
13813
13814 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13815 &state->dst, &state->clip,
13816 min_scale, max_scale,
13817 can_position, true,
13818 &state->visible);
13819 }
13820
13821 static void
13822 intel_commit_primary_plane(struct drm_plane *plane,
13823 struct intel_plane_state *state)
13824 {
13825 struct drm_crtc *crtc = state->base.crtc;
13826 struct drm_framebuffer *fb = state->base.fb;
13827 struct drm_device *dev = plane->dev;
13828 struct drm_i915_private *dev_priv = dev->dev_private;
13829 struct intel_crtc *intel_crtc;
13830 struct drm_rect *src = &state->src;
13831
13832 crtc = crtc ? crtc : plane->crtc;
13833 intel_crtc = to_intel_crtc(crtc);
13834
13835 plane->fb = fb;
13836 crtc->x = src->x1 >> 16;
13837 crtc->y = src->y1 >> 16;
13838
13839 if (!crtc->state->active)
13840 return;
13841
13842 if (state->visible)
13843 /* FIXME: kill this fastboot hack */
13844 intel_update_pipe_size(intel_crtc);
13845
13846 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13847 }
13848
13849 static void
13850 intel_disable_primary_plane(struct drm_plane *plane,
13851 struct drm_crtc *crtc)
13852 {
13853 struct drm_device *dev = plane->dev;
13854 struct drm_i915_private *dev_priv = dev->dev_private;
13855
13856 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13857 }
13858
13859 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13860 {
13861 struct drm_device *dev = crtc->dev;
13862 struct drm_i915_private *dev_priv = dev->dev_private;
13863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13864
13865 if (!needs_modeset(crtc->state))
13866 intel_pre_plane_update(intel_crtc);
13867
13868 if (intel_crtc->atomic.update_wm_pre)
13869 intel_update_watermarks(crtc);
13870
13871 intel_runtime_pm_get(dev_priv);
13872
13873 /* Perform vblank evasion around commit operation */
13874 if (crtc->state->active)
13875 intel_crtc->atomic.evade =
13876 intel_pipe_update_start(intel_crtc,
13877 &intel_crtc->atomic.start_vbl_count);
13878
13879 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13880 skl_detach_scalers(intel_crtc);
13881 }
13882
13883 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13884 {
13885 struct drm_device *dev = crtc->dev;
13886 struct drm_i915_private *dev_priv = dev->dev_private;
13887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13888
13889 if (intel_crtc->atomic.evade)
13890 intel_pipe_update_end(intel_crtc,
13891 intel_crtc->atomic.start_vbl_count);
13892
13893 intel_runtime_pm_put(dev_priv);
13894
13895 intel_post_plane_update(intel_crtc);
13896 }
13897
13898 /**
13899 * intel_plane_destroy - destroy a plane
13900 * @plane: plane to destroy
13901 *
13902 * Common destruction function for all types of planes (primary, cursor,
13903 * sprite).
13904 */
13905 void intel_plane_destroy(struct drm_plane *plane)
13906 {
13907 struct intel_plane *intel_plane = to_intel_plane(plane);
13908 drm_plane_cleanup(plane);
13909 kfree(intel_plane);
13910 }
13911
13912 const struct drm_plane_funcs intel_plane_funcs = {
13913 .update_plane = drm_atomic_helper_update_plane,
13914 .disable_plane = drm_atomic_helper_disable_plane,
13915 .destroy = intel_plane_destroy,
13916 .set_property = drm_atomic_helper_plane_set_property,
13917 .atomic_get_property = intel_plane_atomic_get_property,
13918 .atomic_set_property = intel_plane_atomic_set_property,
13919 .atomic_duplicate_state = intel_plane_duplicate_state,
13920 .atomic_destroy_state = intel_plane_destroy_state,
13921
13922 };
13923
13924 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13925 int pipe)
13926 {
13927 struct intel_plane *primary;
13928 struct intel_plane_state *state;
13929 const uint32_t *intel_primary_formats;
13930 int num_formats;
13931
13932 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13933 if (primary == NULL)
13934 return NULL;
13935
13936 state = intel_create_plane_state(&primary->base);
13937 if (!state) {
13938 kfree(primary);
13939 return NULL;
13940 }
13941 primary->base.state = &state->base;
13942
13943 primary->can_scale = false;
13944 primary->max_downscale = 1;
13945 if (INTEL_INFO(dev)->gen >= 9) {
13946 primary->can_scale = true;
13947 state->scaler_id = -1;
13948 }
13949 primary->pipe = pipe;
13950 primary->plane = pipe;
13951 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13952 primary->check_plane = intel_check_primary_plane;
13953 primary->commit_plane = intel_commit_primary_plane;
13954 primary->disable_plane = intel_disable_primary_plane;
13955 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13956 primary->plane = !pipe;
13957
13958 if (INTEL_INFO(dev)->gen >= 9) {
13959 intel_primary_formats = skl_primary_formats;
13960 num_formats = ARRAY_SIZE(skl_primary_formats);
13961 } else if (INTEL_INFO(dev)->gen >= 4) {
13962 intel_primary_formats = i965_primary_formats;
13963 num_formats = ARRAY_SIZE(i965_primary_formats);
13964 } else {
13965 intel_primary_formats = i8xx_primary_formats;
13966 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13967 }
13968
13969 drm_universal_plane_init(dev, &primary->base, 0,
13970 &intel_plane_funcs,
13971 intel_primary_formats, num_formats,
13972 DRM_PLANE_TYPE_PRIMARY);
13973
13974 if (INTEL_INFO(dev)->gen >= 4)
13975 intel_create_rotation_property(dev, primary);
13976
13977 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13978
13979 return &primary->base;
13980 }
13981
13982 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13983 {
13984 if (!dev->mode_config.rotation_property) {
13985 unsigned long flags = BIT(DRM_ROTATE_0) |
13986 BIT(DRM_ROTATE_180);
13987
13988 if (INTEL_INFO(dev)->gen >= 9)
13989 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13990
13991 dev->mode_config.rotation_property =
13992 drm_mode_create_rotation_property(dev, flags);
13993 }
13994 if (dev->mode_config.rotation_property)
13995 drm_object_attach_property(&plane->base.base,
13996 dev->mode_config.rotation_property,
13997 plane->base.state->rotation);
13998 }
13999
14000 static int
14001 intel_check_cursor_plane(struct drm_plane *plane,
14002 struct intel_crtc_state *crtc_state,
14003 struct intel_plane_state *state)
14004 {
14005 struct drm_crtc *crtc = crtc_state->base.crtc;
14006 struct drm_framebuffer *fb = state->base.fb;
14007 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14008 unsigned stride;
14009 int ret;
14010
14011 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14012 &state->dst, &state->clip,
14013 DRM_PLANE_HELPER_NO_SCALING,
14014 DRM_PLANE_HELPER_NO_SCALING,
14015 true, true, &state->visible);
14016 if (ret)
14017 return ret;
14018
14019 /* if we want to turn off the cursor ignore width and height */
14020 if (!obj)
14021 return 0;
14022
14023 /* Check for which cursor types we support */
14024 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14025 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14026 state->base.crtc_w, state->base.crtc_h);
14027 return -EINVAL;
14028 }
14029
14030 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14031 if (obj->base.size < stride * state->base.crtc_h) {
14032 DRM_DEBUG_KMS("buffer is too small\n");
14033 return -ENOMEM;
14034 }
14035
14036 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14037 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14038 return -EINVAL;
14039 }
14040
14041 return 0;
14042 }
14043
14044 static void
14045 intel_disable_cursor_plane(struct drm_plane *plane,
14046 struct drm_crtc *crtc)
14047 {
14048 intel_crtc_update_cursor(crtc, false);
14049 }
14050
14051 static void
14052 intel_commit_cursor_plane(struct drm_plane *plane,
14053 struct intel_plane_state *state)
14054 {
14055 struct drm_crtc *crtc = state->base.crtc;
14056 struct drm_device *dev = plane->dev;
14057 struct intel_crtc *intel_crtc;
14058 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14059 uint32_t addr;
14060
14061 crtc = crtc ? crtc : plane->crtc;
14062 intel_crtc = to_intel_crtc(crtc);
14063
14064 plane->fb = state->base.fb;
14065 crtc->cursor_x = state->base.crtc_x;
14066 crtc->cursor_y = state->base.crtc_y;
14067
14068 if (intel_crtc->cursor_bo == obj)
14069 goto update;
14070
14071 if (!obj)
14072 addr = 0;
14073 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14074 addr = i915_gem_obj_ggtt_offset(obj);
14075 else
14076 addr = obj->phys_handle->busaddr;
14077
14078 intel_crtc->cursor_addr = addr;
14079 intel_crtc->cursor_bo = obj;
14080
14081 update:
14082 if (crtc->state->active)
14083 intel_crtc_update_cursor(crtc, state->visible);
14084 }
14085
14086 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14087 int pipe)
14088 {
14089 struct intel_plane *cursor;
14090 struct intel_plane_state *state;
14091
14092 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14093 if (cursor == NULL)
14094 return NULL;
14095
14096 state = intel_create_plane_state(&cursor->base);
14097 if (!state) {
14098 kfree(cursor);
14099 return NULL;
14100 }
14101 cursor->base.state = &state->base;
14102
14103 cursor->can_scale = false;
14104 cursor->max_downscale = 1;
14105 cursor->pipe = pipe;
14106 cursor->plane = pipe;
14107 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14108 cursor->check_plane = intel_check_cursor_plane;
14109 cursor->commit_plane = intel_commit_cursor_plane;
14110 cursor->disable_plane = intel_disable_cursor_plane;
14111
14112 drm_universal_plane_init(dev, &cursor->base, 0,
14113 &intel_plane_funcs,
14114 intel_cursor_formats,
14115 ARRAY_SIZE(intel_cursor_formats),
14116 DRM_PLANE_TYPE_CURSOR);
14117
14118 if (INTEL_INFO(dev)->gen >= 4) {
14119 if (!dev->mode_config.rotation_property)
14120 dev->mode_config.rotation_property =
14121 drm_mode_create_rotation_property(dev,
14122 BIT(DRM_ROTATE_0) |
14123 BIT(DRM_ROTATE_180));
14124 if (dev->mode_config.rotation_property)
14125 drm_object_attach_property(&cursor->base.base,
14126 dev->mode_config.rotation_property,
14127 state->base.rotation);
14128 }
14129
14130 if (INTEL_INFO(dev)->gen >=9)
14131 state->scaler_id = -1;
14132
14133 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14134
14135 return &cursor->base;
14136 }
14137
14138 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14139 struct intel_crtc_state *crtc_state)
14140 {
14141 int i;
14142 struct intel_scaler *intel_scaler;
14143 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14144
14145 for (i = 0; i < intel_crtc->num_scalers; i++) {
14146 intel_scaler = &scaler_state->scalers[i];
14147 intel_scaler->in_use = 0;
14148 intel_scaler->mode = PS_SCALER_MODE_DYN;
14149 }
14150
14151 scaler_state->scaler_id = -1;
14152 }
14153
14154 static void intel_crtc_init(struct drm_device *dev, int pipe)
14155 {
14156 struct drm_i915_private *dev_priv = dev->dev_private;
14157 struct intel_crtc *intel_crtc;
14158 struct intel_crtc_state *crtc_state = NULL;
14159 struct drm_plane *primary = NULL;
14160 struct drm_plane *cursor = NULL;
14161 int i, ret;
14162
14163 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14164 if (intel_crtc == NULL)
14165 return;
14166
14167 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14168 if (!crtc_state)
14169 goto fail;
14170 intel_crtc->config = crtc_state;
14171 intel_crtc->base.state = &crtc_state->base;
14172 crtc_state->base.crtc = &intel_crtc->base;
14173
14174 /* initialize shared scalers */
14175 if (INTEL_INFO(dev)->gen >= 9) {
14176 if (pipe == PIPE_C)
14177 intel_crtc->num_scalers = 1;
14178 else
14179 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14180
14181 skl_init_scalers(dev, intel_crtc, crtc_state);
14182 }
14183
14184 primary = intel_primary_plane_create(dev, pipe);
14185 if (!primary)
14186 goto fail;
14187
14188 cursor = intel_cursor_plane_create(dev, pipe);
14189 if (!cursor)
14190 goto fail;
14191
14192 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14193 cursor, &intel_crtc_funcs);
14194 if (ret)
14195 goto fail;
14196
14197 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14198 for (i = 0; i < 256; i++) {
14199 intel_crtc->lut_r[i] = i;
14200 intel_crtc->lut_g[i] = i;
14201 intel_crtc->lut_b[i] = i;
14202 }
14203
14204 /*
14205 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14206 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14207 */
14208 intel_crtc->pipe = pipe;
14209 intel_crtc->plane = pipe;
14210 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14211 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14212 intel_crtc->plane = !pipe;
14213 }
14214
14215 intel_crtc->cursor_base = ~0;
14216 intel_crtc->cursor_cntl = ~0;
14217 intel_crtc->cursor_size = ~0;
14218
14219 intel_crtc->wm.cxsr_allowed = true;
14220
14221 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14222 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14223 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14224 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14225
14226 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14227
14228 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14229 return;
14230
14231 fail:
14232 if (primary)
14233 drm_plane_cleanup(primary);
14234 if (cursor)
14235 drm_plane_cleanup(cursor);
14236 kfree(crtc_state);
14237 kfree(intel_crtc);
14238 }
14239
14240 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14241 {
14242 struct drm_encoder *encoder = connector->base.encoder;
14243 struct drm_device *dev = connector->base.dev;
14244
14245 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14246
14247 if (!encoder || WARN_ON(!encoder->crtc))
14248 return INVALID_PIPE;
14249
14250 return to_intel_crtc(encoder->crtc)->pipe;
14251 }
14252
14253 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14254 struct drm_file *file)
14255 {
14256 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14257 struct drm_crtc *drmmode_crtc;
14258 struct intel_crtc *crtc;
14259
14260 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14261
14262 if (!drmmode_crtc) {
14263 DRM_ERROR("no such CRTC id\n");
14264 return -ENOENT;
14265 }
14266
14267 crtc = to_intel_crtc(drmmode_crtc);
14268 pipe_from_crtc_id->pipe = crtc->pipe;
14269
14270 return 0;
14271 }
14272
14273 static int intel_encoder_clones(struct intel_encoder *encoder)
14274 {
14275 struct drm_device *dev = encoder->base.dev;
14276 struct intel_encoder *source_encoder;
14277 int index_mask = 0;
14278 int entry = 0;
14279
14280 for_each_intel_encoder(dev, source_encoder) {
14281 if (encoders_cloneable(encoder, source_encoder))
14282 index_mask |= (1 << entry);
14283
14284 entry++;
14285 }
14286
14287 return index_mask;
14288 }
14289
14290 static bool has_edp_a(struct drm_device *dev)
14291 {
14292 struct drm_i915_private *dev_priv = dev->dev_private;
14293
14294 if (!IS_MOBILE(dev))
14295 return false;
14296
14297 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14298 return false;
14299
14300 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14301 return false;
14302
14303 return true;
14304 }
14305
14306 static bool intel_crt_present(struct drm_device *dev)
14307 {
14308 struct drm_i915_private *dev_priv = dev->dev_private;
14309
14310 if (INTEL_INFO(dev)->gen >= 9)
14311 return false;
14312
14313 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14314 return false;
14315
14316 if (IS_CHERRYVIEW(dev))
14317 return false;
14318
14319 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14320 return false;
14321
14322 return true;
14323 }
14324
14325 static void intel_setup_outputs(struct drm_device *dev)
14326 {
14327 struct drm_i915_private *dev_priv = dev->dev_private;
14328 struct intel_encoder *encoder;
14329 bool dpd_is_edp = false;
14330
14331 intel_lvds_init(dev);
14332
14333 if (intel_crt_present(dev))
14334 intel_crt_init(dev);
14335
14336 if (IS_BROXTON(dev)) {
14337 /*
14338 * FIXME: Broxton doesn't support port detection via the
14339 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14340 * detect the ports.
14341 */
14342 intel_ddi_init(dev, PORT_A);
14343 intel_ddi_init(dev, PORT_B);
14344 intel_ddi_init(dev, PORT_C);
14345 } else if (HAS_DDI(dev)) {
14346 int found;
14347
14348 /*
14349 * Haswell uses DDI functions to detect digital outputs.
14350 * On SKL pre-D0 the strap isn't connected, so we assume
14351 * it's there.
14352 */
14353 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14354 /* WaIgnoreDDIAStrap: skl */
14355 if (found ||
14356 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14357 intel_ddi_init(dev, PORT_A);
14358
14359 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14360 * register */
14361 found = I915_READ(SFUSE_STRAP);
14362
14363 if (found & SFUSE_STRAP_DDIB_DETECTED)
14364 intel_ddi_init(dev, PORT_B);
14365 if (found & SFUSE_STRAP_DDIC_DETECTED)
14366 intel_ddi_init(dev, PORT_C);
14367 if (found & SFUSE_STRAP_DDID_DETECTED)
14368 intel_ddi_init(dev, PORT_D);
14369 } else if (HAS_PCH_SPLIT(dev)) {
14370 int found;
14371 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14372
14373 if (has_edp_a(dev))
14374 intel_dp_init(dev, DP_A, PORT_A);
14375
14376 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14377 /* PCH SDVOB multiplex with HDMIB */
14378 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14379 if (!found)
14380 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14381 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14382 intel_dp_init(dev, PCH_DP_B, PORT_B);
14383 }
14384
14385 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14386 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14387
14388 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14389 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14390
14391 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14392 intel_dp_init(dev, PCH_DP_C, PORT_C);
14393
14394 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14395 intel_dp_init(dev, PCH_DP_D, PORT_D);
14396 } else if (IS_VALLEYVIEW(dev)) {
14397 /*
14398 * The DP_DETECTED bit is the latched state of the DDC
14399 * SDA pin at boot. However since eDP doesn't require DDC
14400 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14401 * eDP ports may have been muxed to an alternate function.
14402 * Thus we can't rely on the DP_DETECTED bit alone to detect
14403 * eDP ports. Consult the VBT as well as DP_DETECTED to
14404 * detect eDP ports.
14405 */
14406 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14407 !intel_dp_is_edp(dev, PORT_B))
14408 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14409 PORT_B);
14410 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14411 intel_dp_is_edp(dev, PORT_B))
14412 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14413
14414 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14415 !intel_dp_is_edp(dev, PORT_C))
14416 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14417 PORT_C);
14418 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14419 intel_dp_is_edp(dev, PORT_C))
14420 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14421
14422 if (IS_CHERRYVIEW(dev)) {
14423 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14424 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14425 PORT_D);
14426 /* eDP not supported on port D, so don't check VBT */
14427 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14428 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14429 }
14430
14431 intel_dsi_init(dev);
14432 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14433 bool found = false;
14434
14435 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14436 DRM_DEBUG_KMS("probing SDVOB\n");
14437 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14438 if (!found && IS_G4X(dev)) {
14439 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14440 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14441 }
14442
14443 if (!found && IS_G4X(dev))
14444 intel_dp_init(dev, DP_B, PORT_B);
14445 }
14446
14447 /* Before G4X SDVOC doesn't have its own detect register */
14448
14449 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14450 DRM_DEBUG_KMS("probing SDVOC\n");
14451 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14452 }
14453
14454 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14455
14456 if (IS_G4X(dev)) {
14457 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14458 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14459 }
14460 if (IS_G4X(dev))
14461 intel_dp_init(dev, DP_C, PORT_C);
14462 }
14463
14464 if (IS_G4X(dev) &&
14465 (I915_READ(DP_D) & DP_DETECTED))
14466 intel_dp_init(dev, DP_D, PORT_D);
14467 } else if (IS_GEN2(dev))
14468 intel_dvo_init(dev);
14469
14470 if (SUPPORTS_TV(dev))
14471 intel_tv_init(dev);
14472
14473 intel_psr_init(dev);
14474
14475 for_each_intel_encoder(dev, encoder) {
14476 encoder->base.possible_crtcs = encoder->crtc_mask;
14477 encoder->base.possible_clones =
14478 intel_encoder_clones(encoder);
14479 }
14480
14481 intel_init_pch_refclk(dev);
14482
14483 drm_helper_move_panel_connectors_to_head(dev);
14484 }
14485
14486 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14487 {
14488 struct drm_device *dev = fb->dev;
14489 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14490
14491 drm_framebuffer_cleanup(fb);
14492 mutex_lock(&dev->struct_mutex);
14493 WARN_ON(!intel_fb->obj->framebuffer_references--);
14494 drm_gem_object_unreference(&intel_fb->obj->base);
14495 mutex_unlock(&dev->struct_mutex);
14496 kfree(intel_fb);
14497 }
14498
14499 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14500 struct drm_file *file,
14501 unsigned int *handle)
14502 {
14503 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14504 struct drm_i915_gem_object *obj = intel_fb->obj;
14505
14506 return drm_gem_handle_create(file, &obj->base, handle);
14507 }
14508
14509 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14510 struct drm_file *file,
14511 unsigned flags, unsigned color,
14512 struct drm_clip_rect *clips,
14513 unsigned num_clips)
14514 {
14515 struct drm_device *dev = fb->dev;
14516 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14517 struct drm_i915_gem_object *obj = intel_fb->obj;
14518
14519 mutex_lock(&dev->struct_mutex);
14520 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14521 mutex_unlock(&dev->struct_mutex);
14522
14523 return 0;
14524 }
14525
14526 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14527 .destroy = intel_user_framebuffer_destroy,
14528 .create_handle = intel_user_framebuffer_create_handle,
14529 .dirty = intel_user_framebuffer_dirty,
14530 };
14531
14532 static
14533 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14534 uint32_t pixel_format)
14535 {
14536 u32 gen = INTEL_INFO(dev)->gen;
14537
14538 if (gen >= 9) {
14539 /* "The stride in bytes must not exceed the of the size of 8K
14540 * pixels and 32K bytes."
14541 */
14542 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14543 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14544 return 32*1024;
14545 } else if (gen >= 4) {
14546 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14547 return 16*1024;
14548 else
14549 return 32*1024;
14550 } else if (gen >= 3) {
14551 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14552 return 8*1024;
14553 else
14554 return 16*1024;
14555 } else {
14556 /* XXX DSPC is limited to 4k tiled */
14557 return 8*1024;
14558 }
14559 }
14560
14561 static int intel_framebuffer_init(struct drm_device *dev,
14562 struct intel_framebuffer *intel_fb,
14563 struct drm_mode_fb_cmd2 *mode_cmd,
14564 struct drm_i915_gem_object *obj)
14565 {
14566 unsigned int aligned_height;
14567 int ret;
14568 u32 pitch_limit, stride_alignment;
14569
14570 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14571
14572 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14573 /* Enforce that fb modifier and tiling mode match, but only for
14574 * X-tiled. This is needed for FBC. */
14575 if (!!(obj->tiling_mode == I915_TILING_X) !=
14576 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14577 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14578 return -EINVAL;
14579 }
14580 } else {
14581 if (obj->tiling_mode == I915_TILING_X)
14582 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14583 else if (obj->tiling_mode == I915_TILING_Y) {
14584 DRM_DEBUG("No Y tiling for legacy addfb\n");
14585 return -EINVAL;
14586 }
14587 }
14588
14589 /* Passed in modifier sanity checking. */
14590 switch (mode_cmd->modifier[0]) {
14591 case I915_FORMAT_MOD_Y_TILED:
14592 case I915_FORMAT_MOD_Yf_TILED:
14593 if (INTEL_INFO(dev)->gen < 9) {
14594 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14595 mode_cmd->modifier[0]);
14596 return -EINVAL;
14597 }
14598 case DRM_FORMAT_MOD_NONE:
14599 case I915_FORMAT_MOD_X_TILED:
14600 break;
14601 default:
14602 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14603 mode_cmd->modifier[0]);
14604 return -EINVAL;
14605 }
14606
14607 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14608 mode_cmd->pixel_format);
14609 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14610 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14611 mode_cmd->pitches[0], stride_alignment);
14612 return -EINVAL;
14613 }
14614
14615 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14616 mode_cmd->pixel_format);
14617 if (mode_cmd->pitches[0] > pitch_limit) {
14618 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14619 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14620 "tiled" : "linear",
14621 mode_cmd->pitches[0], pitch_limit);
14622 return -EINVAL;
14623 }
14624
14625 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14626 mode_cmd->pitches[0] != obj->stride) {
14627 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14628 mode_cmd->pitches[0], obj->stride);
14629 return -EINVAL;
14630 }
14631
14632 /* Reject formats not supported by any plane early. */
14633 switch (mode_cmd->pixel_format) {
14634 case DRM_FORMAT_C8:
14635 case DRM_FORMAT_RGB565:
14636 case DRM_FORMAT_XRGB8888:
14637 case DRM_FORMAT_ARGB8888:
14638 break;
14639 case DRM_FORMAT_XRGB1555:
14640 if (INTEL_INFO(dev)->gen > 3) {
14641 DRM_DEBUG("unsupported pixel format: %s\n",
14642 drm_get_format_name(mode_cmd->pixel_format));
14643 return -EINVAL;
14644 }
14645 break;
14646 case DRM_FORMAT_ABGR8888:
14647 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14648 DRM_DEBUG("unsupported pixel format: %s\n",
14649 drm_get_format_name(mode_cmd->pixel_format));
14650 return -EINVAL;
14651 }
14652 break;
14653 case DRM_FORMAT_XBGR8888:
14654 case DRM_FORMAT_XRGB2101010:
14655 case DRM_FORMAT_XBGR2101010:
14656 if (INTEL_INFO(dev)->gen < 4) {
14657 DRM_DEBUG("unsupported pixel format: %s\n",
14658 drm_get_format_name(mode_cmd->pixel_format));
14659 return -EINVAL;
14660 }
14661 break;
14662 case DRM_FORMAT_ABGR2101010:
14663 if (!IS_VALLEYVIEW(dev)) {
14664 DRM_DEBUG("unsupported pixel format: %s\n",
14665 drm_get_format_name(mode_cmd->pixel_format));
14666 return -EINVAL;
14667 }
14668 break;
14669 case DRM_FORMAT_YUYV:
14670 case DRM_FORMAT_UYVY:
14671 case DRM_FORMAT_YVYU:
14672 case DRM_FORMAT_VYUY:
14673 if (INTEL_INFO(dev)->gen < 5) {
14674 DRM_DEBUG("unsupported pixel format: %s\n",
14675 drm_get_format_name(mode_cmd->pixel_format));
14676 return -EINVAL;
14677 }
14678 break;
14679 default:
14680 DRM_DEBUG("unsupported pixel format: %s\n",
14681 drm_get_format_name(mode_cmd->pixel_format));
14682 return -EINVAL;
14683 }
14684
14685 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14686 if (mode_cmd->offsets[0] != 0)
14687 return -EINVAL;
14688
14689 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14690 mode_cmd->pixel_format,
14691 mode_cmd->modifier[0]);
14692 /* FIXME drm helper for size checks (especially planar formats)? */
14693 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14694 return -EINVAL;
14695
14696 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14697 intel_fb->obj = obj;
14698 intel_fb->obj->framebuffer_references++;
14699
14700 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14701 if (ret) {
14702 DRM_ERROR("framebuffer init failed %d\n", ret);
14703 return ret;
14704 }
14705
14706 return 0;
14707 }
14708
14709 static struct drm_framebuffer *
14710 intel_user_framebuffer_create(struct drm_device *dev,
14711 struct drm_file *filp,
14712 struct drm_mode_fb_cmd2 *mode_cmd)
14713 {
14714 struct drm_i915_gem_object *obj;
14715
14716 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14717 mode_cmd->handles[0]));
14718 if (&obj->base == NULL)
14719 return ERR_PTR(-ENOENT);
14720
14721 return intel_framebuffer_create(dev, mode_cmd, obj);
14722 }
14723
14724 #ifndef CONFIG_DRM_I915_FBDEV
14725 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14726 {
14727 }
14728 #endif
14729
14730 static const struct drm_mode_config_funcs intel_mode_funcs = {
14731 .fb_create = intel_user_framebuffer_create,
14732 .output_poll_changed = intel_fbdev_output_poll_changed,
14733 .atomic_check = intel_atomic_check,
14734 .atomic_commit = intel_atomic_commit,
14735 .atomic_state_alloc = intel_atomic_state_alloc,
14736 .atomic_state_clear = intel_atomic_state_clear,
14737 };
14738
14739 /* Set up chip specific display functions */
14740 static void intel_init_display(struct drm_device *dev)
14741 {
14742 struct drm_i915_private *dev_priv = dev->dev_private;
14743
14744 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14745 dev_priv->display.find_dpll = g4x_find_best_dpll;
14746 else if (IS_CHERRYVIEW(dev))
14747 dev_priv->display.find_dpll = chv_find_best_dpll;
14748 else if (IS_VALLEYVIEW(dev))
14749 dev_priv->display.find_dpll = vlv_find_best_dpll;
14750 else if (IS_PINEVIEW(dev))
14751 dev_priv->display.find_dpll = pnv_find_best_dpll;
14752 else
14753 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14754
14755 if (INTEL_INFO(dev)->gen >= 9) {
14756 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14757 dev_priv->display.get_initial_plane_config =
14758 skylake_get_initial_plane_config;
14759 dev_priv->display.crtc_compute_clock =
14760 haswell_crtc_compute_clock;
14761 dev_priv->display.crtc_enable = haswell_crtc_enable;
14762 dev_priv->display.crtc_disable = haswell_crtc_disable;
14763 dev_priv->display.update_primary_plane =
14764 skylake_update_primary_plane;
14765 } else if (HAS_DDI(dev)) {
14766 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14767 dev_priv->display.get_initial_plane_config =
14768 ironlake_get_initial_plane_config;
14769 dev_priv->display.crtc_compute_clock =
14770 haswell_crtc_compute_clock;
14771 dev_priv->display.crtc_enable = haswell_crtc_enable;
14772 dev_priv->display.crtc_disable = haswell_crtc_disable;
14773 dev_priv->display.update_primary_plane =
14774 ironlake_update_primary_plane;
14775 } else if (HAS_PCH_SPLIT(dev)) {
14776 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14777 dev_priv->display.get_initial_plane_config =
14778 ironlake_get_initial_plane_config;
14779 dev_priv->display.crtc_compute_clock =
14780 ironlake_crtc_compute_clock;
14781 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14782 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14783 dev_priv->display.update_primary_plane =
14784 ironlake_update_primary_plane;
14785 } else if (IS_VALLEYVIEW(dev)) {
14786 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14787 dev_priv->display.get_initial_plane_config =
14788 i9xx_get_initial_plane_config;
14789 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14790 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14791 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14792 dev_priv->display.update_primary_plane =
14793 i9xx_update_primary_plane;
14794 } else {
14795 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14796 dev_priv->display.get_initial_plane_config =
14797 i9xx_get_initial_plane_config;
14798 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14799 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14800 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14801 dev_priv->display.update_primary_plane =
14802 i9xx_update_primary_plane;
14803 }
14804
14805 /* Returns the core display clock speed */
14806 if (IS_SKYLAKE(dev))
14807 dev_priv->display.get_display_clock_speed =
14808 skylake_get_display_clock_speed;
14809 else if (IS_BROXTON(dev))
14810 dev_priv->display.get_display_clock_speed =
14811 broxton_get_display_clock_speed;
14812 else if (IS_BROADWELL(dev))
14813 dev_priv->display.get_display_clock_speed =
14814 broadwell_get_display_clock_speed;
14815 else if (IS_HASWELL(dev))
14816 dev_priv->display.get_display_clock_speed =
14817 haswell_get_display_clock_speed;
14818 else if (IS_VALLEYVIEW(dev))
14819 dev_priv->display.get_display_clock_speed =
14820 valleyview_get_display_clock_speed;
14821 else if (IS_GEN5(dev))
14822 dev_priv->display.get_display_clock_speed =
14823 ilk_get_display_clock_speed;
14824 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14825 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14826 dev_priv->display.get_display_clock_speed =
14827 i945_get_display_clock_speed;
14828 else if (IS_GM45(dev))
14829 dev_priv->display.get_display_clock_speed =
14830 gm45_get_display_clock_speed;
14831 else if (IS_CRESTLINE(dev))
14832 dev_priv->display.get_display_clock_speed =
14833 i965gm_get_display_clock_speed;
14834 else if (IS_PINEVIEW(dev))
14835 dev_priv->display.get_display_clock_speed =
14836 pnv_get_display_clock_speed;
14837 else if (IS_G33(dev) || IS_G4X(dev))
14838 dev_priv->display.get_display_clock_speed =
14839 g33_get_display_clock_speed;
14840 else if (IS_I915G(dev))
14841 dev_priv->display.get_display_clock_speed =
14842 i915_get_display_clock_speed;
14843 else if (IS_I945GM(dev) || IS_845G(dev))
14844 dev_priv->display.get_display_clock_speed =
14845 i9xx_misc_get_display_clock_speed;
14846 else if (IS_PINEVIEW(dev))
14847 dev_priv->display.get_display_clock_speed =
14848 pnv_get_display_clock_speed;
14849 else if (IS_I915GM(dev))
14850 dev_priv->display.get_display_clock_speed =
14851 i915gm_get_display_clock_speed;
14852 else if (IS_I865G(dev))
14853 dev_priv->display.get_display_clock_speed =
14854 i865_get_display_clock_speed;
14855 else if (IS_I85X(dev))
14856 dev_priv->display.get_display_clock_speed =
14857 i85x_get_display_clock_speed;
14858 else { /* 830 */
14859 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14860 dev_priv->display.get_display_clock_speed =
14861 i830_get_display_clock_speed;
14862 }
14863
14864 if (IS_GEN5(dev)) {
14865 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14866 } else if (IS_GEN6(dev)) {
14867 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14868 } else if (IS_IVYBRIDGE(dev)) {
14869 /* FIXME: detect B0+ stepping and use auto training */
14870 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14871 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14872 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14873 if (IS_BROADWELL(dev)) {
14874 dev_priv->display.modeset_commit_cdclk =
14875 broadwell_modeset_commit_cdclk;
14876 dev_priv->display.modeset_calc_cdclk =
14877 broadwell_modeset_calc_cdclk;
14878 }
14879 } else if (IS_VALLEYVIEW(dev)) {
14880 dev_priv->display.modeset_commit_cdclk =
14881 valleyview_modeset_commit_cdclk;
14882 dev_priv->display.modeset_calc_cdclk =
14883 valleyview_modeset_calc_cdclk;
14884 } else if (IS_BROXTON(dev)) {
14885 dev_priv->display.modeset_commit_cdclk =
14886 broxton_modeset_commit_cdclk;
14887 dev_priv->display.modeset_calc_cdclk =
14888 broxton_modeset_calc_cdclk;
14889 }
14890
14891 switch (INTEL_INFO(dev)->gen) {
14892 case 2:
14893 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14894 break;
14895
14896 case 3:
14897 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14898 break;
14899
14900 case 4:
14901 case 5:
14902 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14903 break;
14904
14905 case 6:
14906 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14907 break;
14908 case 7:
14909 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14910 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14911 break;
14912 case 9:
14913 /* Drop through - unsupported since execlist only. */
14914 default:
14915 /* Default just returns -ENODEV to indicate unsupported */
14916 dev_priv->display.queue_flip = intel_default_queue_flip;
14917 }
14918
14919 intel_panel_init_backlight_funcs(dev);
14920
14921 mutex_init(&dev_priv->pps_mutex);
14922 }
14923
14924 /*
14925 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14926 * resume, or other times. This quirk makes sure that's the case for
14927 * affected systems.
14928 */
14929 static void quirk_pipea_force(struct drm_device *dev)
14930 {
14931 struct drm_i915_private *dev_priv = dev->dev_private;
14932
14933 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14934 DRM_INFO("applying pipe a force quirk\n");
14935 }
14936
14937 static void quirk_pipeb_force(struct drm_device *dev)
14938 {
14939 struct drm_i915_private *dev_priv = dev->dev_private;
14940
14941 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14942 DRM_INFO("applying pipe b force quirk\n");
14943 }
14944
14945 /*
14946 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14947 */
14948 static void quirk_ssc_force_disable(struct drm_device *dev)
14949 {
14950 struct drm_i915_private *dev_priv = dev->dev_private;
14951 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14952 DRM_INFO("applying lvds SSC disable quirk\n");
14953 }
14954
14955 /*
14956 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14957 * brightness value
14958 */
14959 static void quirk_invert_brightness(struct drm_device *dev)
14960 {
14961 struct drm_i915_private *dev_priv = dev->dev_private;
14962 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14963 DRM_INFO("applying inverted panel brightness quirk\n");
14964 }
14965
14966 /* Some VBT's incorrectly indicate no backlight is present */
14967 static void quirk_backlight_present(struct drm_device *dev)
14968 {
14969 struct drm_i915_private *dev_priv = dev->dev_private;
14970 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14971 DRM_INFO("applying backlight present quirk\n");
14972 }
14973
14974 struct intel_quirk {
14975 int device;
14976 int subsystem_vendor;
14977 int subsystem_device;
14978 void (*hook)(struct drm_device *dev);
14979 };
14980
14981 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14982 struct intel_dmi_quirk {
14983 void (*hook)(struct drm_device *dev);
14984 const struct dmi_system_id (*dmi_id_list)[];
14985 };
14986
14987 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14988 {
14989 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14990 return 1;
14991 }
14992
14993 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14994 {
14995 .dmi_id_list = &(const struct dmi_system_id[]) {
14996 {
14997 .callback = intel_dmi_reverse_brightness,
14998 .ident = "NCR Corporation",
14999 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15000 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15001 },
15002 },
15003 { } /* terminating entry */
15004 },
15005 .hook = quirk_invert_brightness,
15006 },
15007 };
15008
15009 static struct intel_quirk intel_quirks[] = {
15010 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15011 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15012
15013 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15014 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15015
15016 /* 830 needs to leave pipe A & dpll A up */
15017 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15018
15019 /* 830 needs to leave pipe B & dpll B up */
15020 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15021
15022 /* Lenovo U160 cannot use SSC on LVDS */
15023 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15024
15025 /* Sony Vaio Y cannot use SSC on LVDS */
15026 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15027
15028 /* Acer Aspire 5734Z must invert backlight brightness */
15029 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15030
15031 /* Acer/eMachines G725 */
15032 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15033
15034 /* Acer/eMachines e725 */
15035 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15036
15037 /* Acer/Packard Bell NCL20 */
15038 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15039
15040 /* Acer Aspire 4736Z */
15041 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15042
15043 /* Acer Aspire 5336 */
15044 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15045
15046 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15047 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15048
15049 /* Acer C720 Chromebook (Core i3 4005U) */
15050 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15051
15052 /* Apple Macbook 2,1 (Core 2 T7400) */
15053 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15054
15055 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15056 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15057
15058 /* HP Chromebook 14 (Celeron 2955U) */
15059 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15060
15061 /* Dell Chromebook 11 */
15062 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15063 };
15064
15065 static void intel_init_quirks(struct drm_device *dev)
15066 {
15067 struct pci_dev *d = dev->pdev;
15068 int i;
15069
15070 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15071 struct intel_quirk *q = &intel_quirks[i];
15072
15073 if (d->device == q->device &&
15074 (d->subsystem_vendor == q->subsystem_vendor ||
15075 q->subsystem_vendor == PCI_ANY_ID) &&
15076 (d->subsystem_device == q->subsystem_device ||
15077 q->subsystem_device == PCI_ANY_ID))
15078 q->hook(dev);
15079 }
15080 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15081 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15082 intel_dmi_quirks[i].hook(dev);
15083 }
15084 }
15085
15086 /* Disable the VGA plane that we never use */
15087 static void i915_disable_vga(struct drm_device *dev)
15088 {
15089 struct drm_i915_private *dev_priv = dev->dev_private;
15090 u8 sr1;
15091 u32 vga_reg = i915_vgacntrl_reg(dev);
15092
15093 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15094 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15095 outb(SR01, VGA_SR_INDEX);
15096 sr1 = inb(VGA_SR_DATA);
15097 outb(sr1 | 1<<5, VGA_SR_DATA);
15098 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15099 udelay(300);
15100
15101 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15102 POSTING_READ(vga_reg);
15103 }
15104
15105 void intel_modeset_init_hw(struct drm_device *dev)
15106 {
15107 intel_update_cdclk(dev);
15108 intel_prepare_ddi(dev);
15109 intel_init_clock_gating(dev);
15110 intel_enable_gt_powersave(dev);
15111 }
15112
15113 void intel_modeset_init(struct drm_device *dev)
15114 {
15115 struct drm_i915_private *dev_priv = dev->dev_private;
15116 int sprite, ret;
15117 enum pipe pipe;
15118 struct intel_crtc *crtc;
15119
15120 drm_mode_config_init(dev);
15121
15122 dev->mode_config.min_width = 0;
15123 dev->mode_config.min_height = 0;
15124
15125 dev->mode_config.preferred_depth = 24;
15126 dev->mode_config.prefer_shadow = 1;
15127
15128 dev->mode_config.allow_fb_modifiers = true;
15129
15130 dev->mode_config.funcs = &intel_mode_funcs;
15131
15132 intel_init_quirks(dev);
15133
15134 intel_init_pm(dev);
15135
15136 if (INTEL_INFO(dev)->num_pipes == 0)
15137 return;
15138
15139 intel_init_display(dev);
15140 intel_init_audio(dev);
15141
15142 if (IS_GEN2(dev)) {
15143 dev->mode_config.max_width = 2048;
15144 dev->mode_config.max_height = 2048;
15145 } else if (IS_GEN3(dev)) {
15146 dev->mode_config.max_width = 4096;
15147 dev->mode_config.max_height = 4096;
15148 } else {
15149 dev->mode_config.max_width = 8192;
15150 dev->mode_config.max_height = 8192;
15151 }
15152
15153 if (IS_845G(dev) || IS_I865G(dev)) {
15154 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15155 dev->mode_config.cursor_height = 1023;
15156 } else if (IS_GEN2(dev)) {
15157 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15158 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15159 } else {
15160 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15161 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15162 }
15163
15164 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15165
15166 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15167 INTEL_INFO(dev)->num_pipes,
15168 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15169
15170 for_each_pipe(dev_priv, pipe) {
15171 intel_crtc_init(dev, pipe);
15172 for_each_sprite(dev_priv, pipe, sprite) {
15173 ret = intel_plane_init(dev, pipe, sprite);
15174 if (ret)
15175 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15176 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15177 }
15178 }
15179
15180 intel_init_dpio(dev);
15181
15182 intel_shared_dpll_init(dev);
15183
15184 /* Just disable it once at startup */
15185 i915_disable_vga(dev);
15186 intel_setup_outputs(dev);
15187
15188 /* Just in case the BIOS is doing something questionable. */
15189 intel_fbc_disable(dev_priv);
15190
15191 drm_modeset_lock_all(dev);
15192 intel_modeset_setup_hw_state(dev, false);
15193 drm_modeset_unlock_all(dev);
15194
15195 for_each_intel_crtc(dev, crtc) {
15196 if (!crtc->active)
15197 continue;
15198
15199 /*
15200 * Note that reserving the BIOS fb up front prevents us
15201 * from stuffing other stolen allocations like the ring
15202 * on top. This prevents some ugliness at boot time, and
15203 * can even allow for smooth boot transitions if the BIOS
15204 * fb is large enough for the active pipe configuration.
15205 */
15206 if (dev_priv->display.get_initial_plane_config) {
15207 dev_priv->display.get_initial_plane_config(crtc,
15208 &crtc->plane_config);
15209 /*
15210 * If the fb is shared between multiple heads, we'll
15211 * just get the first one.
15212 */
15213 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15214 }
15215 }
15216 }
15217
15218 static void intel_enable_pipe_a(struct drm_device *dev)
15219 {
15220 struct intel_connector *connector;
15221 struct drm_connector *crt = NULL;
15222 struct intel_load_detect_pipe load_detect_temp;
15223 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15224
15225 /* We can't just switch on the pipe A, we need to set things up with a
15226 * proper mode and output configuration. As a gross hack, enable pipe A
15227 * by enabling the load detect pipe once. */
15228 for_each_intel_connector(dev, connector) {
15229 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15230 crt = &connector->base;
15231 break;
15232 }
15233 }
15234
15235 if (!crt)
15236 return;
15237
15238 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15239 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15240 }
15241
15242 static bool
15243 intel_check_plane_mapping(struct intel_crtc *crtc)
15244 {
15245 struct drm_device *dev = crtc->base.dev;
15246 struct drm_i915_private *dev_priv = dev->dev_private;
15247 u32 reg, val;
15248
15249 if (INTEL_INFO(dev)->num_pipes == 1)
15250 return true;
15251
15252 reg = DSPCNTR(!crtc->plane);
15253 val = I915_READ(reg);
15254
15255 if ((val & DISPLAY_PLANE_ENABLE) &&
15256 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15257 return false;
15258
15259 return true;
15260 }
15261
15262 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15263 {
15264 struct drm_device *dev = crtc->base.dev;
15265 struct drm_i915_private *dev_priv = dev->dev_private;
15266 struct intel_encoder *encoder;
15267 u32 reg;
15268 bool enable;
15269
15270 /* Clear any frame start delays used for debugging left by the BIOS */
15271 reg = PIPECONF(crtc->config->cpu_transcoder);
15272 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15273
15274 /* restore vblank interrupts to correct state */
15275 drm_crtc_vblank_reset(&crtc->base);
15276 if (crtc->active) {
15277 update_scanline_offset(crtc);
15278 drm_crtc_vblank_on(&crtc->base);
15279 }
15280
15281 /* We need to sanitize the plane -> pipe mapping first because this will
15282 * disable the crtc (and hence change the state) if it is wrong. Note
15283 * that gen4+ has a fixed plane -> pipe mapping. */
15284 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15285 bool plane;
15286
15287 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15288 crtc->base.base.id);
15289
15290 /* Pipe has the wrong plane attached and the plane is active.
15291 * Temporarily change the plane mapping and disable everything
15292 * ... */
15293 plane = crtc->plane;
15294 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15295 crtc->plane = !plane;
15296 intel_crtc_disable_noatomic(&crtc->base);
15297 crtc->plane = plane;
15298 }
15299
15300 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15301 crtc->pipe == PIPE_A && !crtc->active) {
15302 /* BIOS forgot to enable pipe A, this mostly happens after
15303 * resume. Force-enable the pipe to fix this, the update_dpms
15304 * call below we restore the pipe to the right state, but leave
15305 * the required bits on. */
15306 intel_enable_pipe_a(dev);
15307 }
15308
15309 /* Adjust the state of the output pipe according to whether we
15310 * have active connectors/encoders. */
15311 enable = false;
15312 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15313 enable |= encoder->connectors_active;
15314
15315 if (!enable)
15316 intel_crtc_disable_noatomic(&crtc->base);
15317
15318 if (crtc->active != crtc->base.state->active) {
15319
15320 /* This can happen either due to bugs in the get_hw_state
15321 * functions or because of calls to intel_crtc_disable_noatomic,
15322 * or because the pipe is force-enabled due to the
15323 * pipe A quirk. */
15324 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15325 crtc->base.base.id,
15326 crtc->base.state->enable ? "enabled" : "disabled",
15327 crtc->active ? "enabled" : "disabled");
15328
15329 crtc->base.state->enable = crtc->active;
15330 crtc->base.state->active = crtc->active;
15331 crtc->base.enabled = crtc->active;
15332
15333 /* Because we only establish the connector -> encoder ->
15334 * crtc links if something is active, this means the
15335 * crtc is now deactivated. Break the links. connector
15336 * -> encoder links are only establish when things are
15337 * actually up, hence no need to break them. */
15338 WARN_ON(crtc->active);
15339
15340 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15341 WARN_ON(encoder->connectors_active);
15342 encoder->base.crtc = NULL;
15343 }
15344 }
15345
15346 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15347 /*
15348 * We start out with underrun reporting disabled to avoid races.
15349 * For correct bookkeeping mark this on active crtcs.
15350 *
15351 * Also on gmch platforms we dont have any hardware bits to
15352 * disable the underrun reporting. Which means we need to start
15353 * out with underrun reporting disabled also on inactive pipes,
15354 * since otherwise we'll complain about the garbage we read when
15355 * e.g. coming up after runtime pm.
15356 *
15357 * No protection against concurrent access is required - at
15358 * worst a fifo underrun happens which also sets this to false.
15359 */
15360 crtc->cpu_fifo_underrun_disabled = true;
15361 crtc->pch_fifo_underrun_disabled = true;
15362 }
15363 }
15364
15365 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15366 {
15367 struct intel_connector *connector;
15368 struct drm_device *dev = encoder->base.dev;
15369
15370 /* We need to check both for a crtc link (meaning that the
15371 * encoder is active and trying to read from a pipe) and the
15372 * pipe itself being active. */
15373 bool has_active_crtc = encoder->base.crtc &&
15374 to_intel_crtc(encoder->base.crtc)->active;
15375
15376 if (encoder->connectors_active && !has_active_crtc) {
15377 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15378 encoder->base.base.id,
15379 encoder->base.name);
15380
15381 /* Connector is active, but has no active pipe. This is
15382 * fallout from our resume register restoring. Disable
15383 * the encoder manually again. */
15384 if (encoder->base.crtc) {
15385 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15386 encoder->base.base.id,
15387 encoder->base.name);
15388 encoder->disable(encoder);
15389 if (encoder->post_disable)
15390 encoder->post_disable(encoder);
15391 }
15392 encoder->base.crtc = NULL;
15393 encoder->connectors_active = false;
15394
15395 /* Inconsistent output/port/pipe state happens presumably due to
15396 * a bug in one of the get_hw_state functions. Or someplace else
15397 * in our code, like the register restore mess on resume. Clamp
15398 * things to off as a safer default. */
15399 for_each_intel_connector(dev, connector) {
15400 if (connector->encoder != encoder)
15401 continue;
15402 connector->base.dpms = DRM_MODE_DPMS_OFF;
15403 connector->base.encoder = NULL;
15404 }
15405 }
15406 /* Enabled encoders without active connectors will be fixed in
15407 * the crtc fixup. */
15408 }
15409
15410 void i915_redisable_vga_power_on(struct drm_device *dev)
15411 {
15412 struct drm_i915_private *dev_priv = dev->dev_private;
15413 u32 vga_reg = i915_vgacntrl_reg(dev);
15414
15415 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15416 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15417 i915_disable_vga(dev);
15418 }
15419 }
15420
15421 void i915_redisable_vga(struct drm_device *dev)
15422 {
15423 struct drm_i915_private *dev_priv = dev->dev_private;
15424
15425 /* This function can be called both from intel_modeset_setup_hw_state or
15426 * at a very early point in our resume sequence, where the power well
15427 * structures are not yet restored. Since this function is at a very
15428 * paranoid "someone might have enabled VGA while we were not looking"
15429 * level, just check if the power well is enabled instead of trying to
15430 * follow the "don't touch the power well if we don't need it" policy
15431 * the rest of the driver uses. */
15432 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15433 return;
15434
15435 i915_redisable_vga_power_on(dev);
15436 }
15437
15438 static bool primary_get_hw_state(struct intel_crtc *crtc)
15439 {
15440 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15441
15442 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15443 }
15444
15445 static void readout_plane_state(struct intel_crtc *crtc,
15446 struct intel_crtc_state *crtc_state)
15447 {
15448 struct intel_plane *p;
15449 struct drm_plane_state *drm_plane_state;
15450 bool active = crtc_state->base.active;
15451
15452 if (active) {
15453 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15454
15455 /* apply to previous sw state too */
15456 to_intel_crtc_state(crtc->base.state)->quirks |=
15457 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15458 }
15459
15460 for_each_intel_plane(crtc->base.dev, p) {
15461 bool visible = active;
15462
15463 if (crtc->pipe != p->pipe)
15464 continue;
15465
15466 drm_plane_state = p->base.state;
15467
15468 /* Plane scaler state is not touched here. The first atomic
15469 * commit will restore all plane scalers to its old state.
15470 */
15471
15472 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15473 visible = primary_get_hw_state(crtc);
15474 to_intel_plane_state(drm_plane_state)->visible = visible;
15475 } else {
15476 /*
15477 * unknown state, assume it's off to force a transition
15478 * to on when calculating state changes.
15479 */
15480 to_intel_plane_state(drm_plane_state)->visible = false;
15481 }
15482
15483 if (visible) {
15484 crtc_state->base.plane_mask |=
15485 1 << drm_plane_index(&p->base);
15486 } else if (crtc_state->base.state) {
15487 /* Make this unconditional for atomic hw readout. */
15488 crtc_state->base.plane_mask &=
15489 ~(1 << drm_plane_index(&p->base));
15490 }
15491 }
15492 }
15493
15494 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15495 {
15496 struct drm_i915_private *dev_priv = dev->dev_private;
15497 enum pipe pipe;
15498 struct intel_crtc *crtc;
15499 struct intel_encoder *encoder;
15500 struct intel_connector *connector;
15501 int i;
15502
15503 for_each_intel_crtc(dev, crtc) {
15504 memset(crtc->config, 0, sizeof(*crtc->config));
15505 crtc->config->base.crtc = &crtc->base;
15506
15507 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15508
15509 crtc->active = dev_priv->display.get_pipe_config(crtc,
15510 crtc->config);
15511
15512 crtc->base.state->enable = crtc->active;
15513 crtc->base.state->active = crtc->active;
15514 crtc->base.enabled = crtc->active;
15515 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15516
15517 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15518
15519 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15520 crtc->base.base.id,
15521 crtc->active ? "enabled" : "disabled");
15522 }
15523
15524 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15525 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15526
15527 pll->on = pll->get_hw_state(dev_priv, pll,
15528 &pll->config.hw_state);
15529 pll->active = 0;
15530 pll->config.crtc_mask = 0;
15531 for_each_intel_crtc(dev, crtc) {
15532 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15533 pll->active++;
15534 pll->config.crtc_mask |= 1 << crtc->pipe;
15535 }
15536 }
15537
15538 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15539 pll->name, pll->config.crtc_mask, pll->on);
15540
15541 if (pll->config.crtc_mask)
15542 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15543 }
15544
15545 for_each_intel_encoder(dev, encoder) {
15546 pipe = 0;
15547
15548 if (encoder->get_hw_state(encoder, &pipe)) {
15549 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15550 encoder->base.crtc = &crtc->base;
15551 encoder->get_config(encoder, crtc->config);
15552 } else {
15553 encoder->base.crtc = NULL;
15554 }
15555
15556 encoder->connectors_active = false;
15557 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15558 encoder->base.base.id,
15559 encoder->base.name,
15560 encoder->base.crtc ? "enabled" : "disabled",
15561 pipe_name(pipe));
15562 }
15563
15564 for_each_intel_connector(dev, connector) {
15565 if (connector->get_hw_state(connector)) {
15566 connector->base.dpms = DRM_MODE_DPMS_ON;
15567 connector->encoder->connectors_active = true;
15568 connector->base.encoder = &connector->encoder->base;
15569 } else {
15570 connector->base.dpms = DRM_MODE_DPMS_OFF;
15571 connector->base.encoder = NULL;
15572 }
15573 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15574 connector->base.base.id,
15575 connector->base.name,
15576 connector->base.encoder ? "enabled" : "disabled");
15577 }
15578 }
15579
15580 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15581 * and i915 state tracking structures. */
15582 void intel_modeset_setup_hw_state(struct drm_device *dev,
15583 bool force_restore)
15584 {
15585 struct drm_i915_private *dev_priv = dev->dev_private;
15586 enum pipe pipe;
15587 struct intel_crtc *crtc;
15588 struct intel_encoder *encoder;
15589 int i;
15590
15591 intel_modeset_readout_hw_state(dev);
15592
15593 /*
15594 * Now that we have the config, copy it to each CRTC struct
15595 * Note that this could go away if we move to using crtc_config
15596 * checking everywhere.
15597 */
15598 for_each_intel_crtc(dev, crtc) {
15599 if (crtc->active && i915.fastboot) {
15600 intel_mode_from_pipe_config(&crtc->base.mode,
15601 crtc->config);
15602 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15603 crtc->base.base.id);
15604 drm_mode_debug_printmodeline(&crtc->base.mode);
15605 }
15606 }
15607
15608 /* HW state is read out, now we need to sanitize this mess. */
15609 for_each_intel_encoder(dev, encoder) {
15610 intel_sanitize_encoder(encoder);
15611 }
15612
15613 for_each_pipe(dev_priv, pipe) {
15614 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15615 intel_sanitize_crtc(crtc);
15616 intel_dump_pipe_config(crtc, crtc->config,
15617 "[setup_hw_state]");
15618 }
15619
15620 intel_modeset_update_connector_atomic_state(dev);
15621
15622 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15623 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15624
15625 if (!pll->on || pll->active)
15626 continue;
15627
15628 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15629
15630 pll->disable(dev_priv, pll);
15631 pll->on = false;
15632 }
15633
15634 if (IS_VALLEYVIEW(dev))
15635 vlv_wm_get_hw_state(dev);
15636 else if (IS_GEN9(dev))
15637 skl_wm_get_hw_state(dev);
15638 else if (HAS_PCH_SPLIT(dev))
15639 ilk_wm_get_hw_state(dev);
15640
15641 if (force_restore) {
15642 i915_redisable_vga(dev);
15643
15644 /*
15645 * We need to use raw interfaces for restoring state to avoid
15646 * checking (bogus) intermediate states.
15647 */
15648 for_each_pipe(dev_priv, pipe) {
15649 struct drm_crtc *crtc =
15650 dev_priv->pipe_to_crtc_mapping[pipe];
15651
15652 intel_crtc_restore_mode(crtc);
15653 }
15654 } else {
15655 intel_modeset_update_staged_output_state(dev);
15656 }
15657
15658 intel_modeset_check_state(dev);
15659 }
15660
15661 void intel_modeset_gem_init(struct drm_device *dev)
15662 {
15663 struct drm_i915_private *dev_priv = dev->dev_private;
15664 struct drm_crtc *c;
15665 struct drm_i915_gem_object *obj;
15666 int ret;
15667
15668 mutex_lock(&dev->struct_mutex);
15669 intel_init_gt_powersave(dev);
15670 mutex_unlock(&dev->struct_mutex);
15671
15672 /*
15673 * There may be no VBT; and if the BIOS enabled SSC we can
15674 * just keep using it to avoid unnecessary flicker. Whereas if the
15675 * BIOS isn't using it, don't assume it will work even if the VBT
15676 * indicates as much.
15677 */
15678 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15679 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15680 DREF_SSC1_ENABLE);
15681
15682 intel_modeset_init_hw(dev);
15683
15684 intel_setup_overlay(dev);
15685
15686 /*
15687 * Make sure any fbs we allocated at startup are properly
15688 * pinned & fenced. When we do the allocation it's too early
15689 * for this.
15690 */
15691 for_each_crtc(dev, c) {
15692 obj = intel_fb_obj(c->primary->fb);
15693 if (obj == NULL)
15694 continue;
15695
15696 mutex_lock(&dev->struct_mutex);
15697 ret = intel_pin_and_fence_fb_obj(c->primary,
15698 c->primary->fb,
15699 c->primary->state,
15700 NULL, NULL);
15701 mutex_unlock(&dev->struct_mutex);
15702 if (ret) {
15703 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15704 to_intel_crtc(c)->pipe);
15705 drm_framebuffer_unreference(c->primary->fb);
15706 c->primary->fb = NULL;
15707 c->primary->crtc = c->primary->state->crtc = NULL;
15708 update_state_fb(c->primary);
15709 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15710 }
15711 }
15712
15713 intel_backlight_register(dev);
15714 }
15715
15716 void intel_connector_unregister(struct intel_connector *intel_connector)
15717 {
15718 struct drm_connector *connector = &intel_connector->base;
15719
15720 intel_panel_destroy_backlight(connector);
15721 drm_connector_unregister(connector);
15722 }
15723
15724 void intel_modeset_cleanup(struct drm_device *dev)
15725 {
15726 struct drm_i915_private *dev_priv = dev->dev_private;
15727 struct drm_connector *connector;
15728
15729 intel_disable_gt_powersave(dev);
15730
15731 intel_backlight_unregister(dev);
15732
15733 /*
15734 * Interrupts and polling as the first thing to avoid creating havoc.
15735 * Too much stuff here (turning of connectors, ...) would
15736 * experience fancy races otherwise.
15737 */
15738 intel_irq_uninstall(dev_priv);
15739
15740 /*
15741 * Due to the hpd irq storm handling the hotplug work can re-arm the
15742 * poll handlers. Hence disable polling after hpd handling is shut down.
15743 */
15744 drm_kms_helper_poll_fini(dev);
15745
15746 intel_unregister_dsm_handler();
15747
15748 intel_fbc_disable(dev_priv);
15749
15750 /* flush any delayed tasks or pending work */
15751 flush_scheduled_work();
15752
15753 /* destroy the backlight and sysfs files before encoders/connectors */
15754 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15755 struct intel_connector *intel_connector;
15756
15757 intel_connector = to_intel_connector(connector);
15758 intel_connector->unregister(intel_connector);
15759 }
15760
15761 drm_mode_config_cleanup(dev);
15762
15763 intel_cleanup_overlay(dev);
15764
15765 mutex_lock(&dev->struct_mutex);
15766 intel_cleanup_gt_powersave(dev);
15767 mutex_unlock(&dev->struct_mutex);
15768 }
15769
15770 /*
15771 * Return which encoder is currently attached for connector.
15772 */
15773 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15774 {
15775 return &intel_attached_encoder(connector)->base;
15776 }
15777
15778 void intel_connector_attach_encoder(struct intel_connector *connector,
15779 struct intel_encoder *encoder)
15780 {
15781 connector->encoder = encoder;
15782 drm_mode_connector_attach_encoder(&connector->base,
15783 &encoder->base);
15784 }
15785
15786 /*
15787 * set vga decode state - true == enable VGA decode
15788 */
15789 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15790 {
15791 struct drm_i915_private *dev_priv = dev->dev_private;
15792 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15793 u16 gmch_ctrl;
15794
15795 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15796 DRM_ERROR("failed to read control word\n");
15797 return -EIO;
15798 }
15799
15800 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15801 return 0;
15802
15803 if (state)
15804 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15805 else
15806 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15807
15808 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15809 DRM_ERROR("failed to write control word\n");
15810 return -EIO;
15811 }
15812
15813 return 0;
15814 }
15815
15816 struct intel_display_error_state {
15817
15818 u32 power_well_driver;
15819
15820 int num_transcoders;
15821
15822 struct intel_cursor_error_state {
15823 u32 control;
15824 u32 position;
15825 u32 base;
15826 u32 size;
15827 } cursor[I915_MAX_PIPES];
15828
15829 struct intel_pipe_error_state {
15830 bool power_domain_on;
15831 u32 source;
15832 u32 stat;
15833 } pipe[I915_MAX_PIPES];
15834
15835 struct intel_plane_error_state {
15836 u32 control;
15837 u32 stride;
15838 u32 size;
15839 u32 pos;
15840 u32 addr;
15841 u32 surface;
15842 u32 tile_offset;
15843 } plane[I915_MAX_PIPES];
15844
15845 struct intel_transcoder_error_state {
15846 bool power_domain_on;
15847 enum transcoder cpu_transcoder;
15848
15849 u32 conf;
15850
15851 u32 htotal;
15852 u32 hblank;
15853 u32 hsync;
15854 u32 vtotal;
15855 u32 vblank;
15856 u32 vsync;
15857 } transcoder[4];
15858 };
15859
15860 struct intel_display_error_state *
15861 intel_display_capture_error_state(struct drm_device *dev)
15862 {
15863 struct drm_i915_private *dev_priv = dev->dev_private;
15864 struct intel_display_error_state *error;
15865 int transcoders[] = {
15866 TRANSCODER_A,
15867 TRANSCODER_B,
15868 TRANSCODER_C,
15869 TRANSCODER_EDP,
15870 };
15871 int i;
15872
15873 if (INTEL_INFO(dev)->num_pipes == 0)
15874 return NULL;
15875
15876 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15877 if (error == NULL)
15878 return NULL;
15879
15880 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15881 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15882
15883 for_each_pipe(dev_priv, i) {
15884 error->pipe[i].power_domain_on =
15885 __intel_display_power_is_enabled(dev_priv,
15886 POWER_DOMAIN_PIPE(i));
15887 if (!error->pipe[i].power_domain_on)
15888 continue;
15889
15890 error->cursor[i].control = I915_READ(CURCNTR(i));
15891 error->cursor[i].position = I915_READ(CURPOS(i));
15892 error->cursor[i].base = I915_READ(CURBASE(i));
15893
15894 error->plane[i].control = I915_READ(DSPCNTR(i));
15895 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15896 if (INTEL_INFO(dev)->gen <= 3) {
15897 error->plane[i].size = I915_READ(DSPSIZE(i));
15898 error->plane[i].pos = I915_READ(DSPPOS(i));
15899 }
15900 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15901 error->plane[i].addr = I915_READ(DSPADDR(i));
15902 if (INTEL_INFO(dev)->gen >= 4) {
15903 error->plane[i].surface = I915_READ(DSPSURF(i));
15904 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15905 }
15906
15907 error->pipe[i].source = I915_READ(PIPESRC(i));
15908
15909 if (HAS_GMCH_DISPLAY(dev))
15910 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15911 }
15912
15913 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15914 if (HAS_DDI(dev_priv->dev))
15915 error->num_transcoders++; /* Account for eDP. */
15916
15917 for (i = 0; i < error->num_transcoders; i++) {
15918 enum transcoder cpu_transcoder = transcoders[i];
15919
15920 error->transcoder[i].power_domain_on =
15921 __intel_display_power_is_enabled(dev_priv,
15922 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15923 if (!error->transcoder[i].power_domain_on)
15924 continue;
15925
15926 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15927
15928 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15929 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15930 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15931 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15932 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15933 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15934 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15935 }
15936
15937 return error;
15938 }
15939
15940 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15941
15942 void
15943 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15944 struct drm_device *dev,
15945 struct intel_display_error_state *error)
15946 {
15947 struct drm_i915_private *dev_priv = dev->dev_private;
15948 int i;
15949
15950 if (!error)
15951 return;
15952
15953 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15954 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15955 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15956 error->power_well_driver);
15957 for_each_pipe(dev_priv, i) {
15958 err_printf(m, "Pipe [%d]:\n", i);
15959 err_printf(m, " Power: %s\n",
15960 error->pipe[i].power_domain_on ? "on" : "off");
15961 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15962 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15963
15964 err_printf(m, "Plane [%d]:\n", i);
15965 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15966 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15967 if (INTEL_INFO(dev)->gen <= 3) {
15968 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15969 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15970 }
15971 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15972 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15973 if (INTEL_INFO(dev)->gen >= 4) {
15974 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15975 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15976 }
15977
15978 err_printf(m, "Cursor [%d]:\n", i);
15979 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15980 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15981 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15982 }
15983
15984 for (i = 0; i < error->num_transcoders; i++) {
15985 err_printf(m, "CPU transcoder: %c\n",
15986 transcoder_name(error->transcoder[i].cpu_transcoder));
15987 err_printf(m, " Power: %s\n",
15988 error->transcoder[i].power_domain_on ? "on" : "off");
15989 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15990 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15991 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15992 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15993 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15994 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15995 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15996 }
15997 }
15998
15999 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16000 {
16001 struct intel_crtc *crtc;
16002
16003 for_each_intel_crtc(dev, crtc) {
16004 struct intel_unpin_work *work;
16005
16006 spin_lock_irq(&dev->event_lock);
16007
16008 work = crtc->unpin_work;
16009
16010 if (work && work->event &&
16011 work->event->base.file_priv == file) {
16012 kfree(work->event);
16013 work->event = NULL;
16014 }
16015
16016 spin_unlock_irq(&dev->event_lock);
16017 }
16018 }
Linux kernel - Deliverables
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