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drm/i915: Update less state during modeset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
112
113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114 {
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119 }
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 int
137 intel_pch_rawclk(struct drm_device *dev)
138 {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144 }
145
146 static inline u32 /* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device *dev)
148 {
149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
154 }
155
156 static const intel_limit_t intel_limits_i8xx_dac = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
167 };
168
169 static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180 };
181
182 static const intel_limit_t intel_limits_i8xx_lvds = {
183 .dot = { .min = 25000, .max = 350000 },
184 .vco = { .min = 908000, .max = 1512000 },
185 .n = { .min = 2, .max = 16 },
186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
193 };
194
195 static const intel_limit_t intel_limits_i9xx_sdvo = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
206 };
207
208 static const intel_limit_t intel_limits_i9xx_lvds = {
209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
219 };
220
221
222 static const intel_limit_t intel_limits_g4x_sdvo = {
223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
234 },
235 };
236
237 static const intel_limit_t intel_limits_g4x_hdmi = {
238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
248 };
249
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
261 },
262 };
263
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
275 },
276 };
277
278 static const intel_limit_t intel_limits_pineview_sdvo = {
279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
291 };
292
293 static const intel_limit_t intel_limits_pineview_lvds = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
304 };
305
306 /* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
311 static const intel_limit_t intel_limits_ironlake_dac = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
322 };
323
324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
335 };
336
337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
348 };
349
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
359 .p1 = { .min = 2, .max = 8 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
362 };
363
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
372 .p1 = { .min = 2, .max = 6 },
373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
375 };
376
377 static const intel_limit_t intel_limits_vlv = {
378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
385 .vco = { .min = 4000000, .max = 6000000 },
386 .n = { .min = 1, .max = 7 },
387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
391 };
392
393 static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
401 .vco = { .min = 4800000, .max = 6480000 },
402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407 };
408
409 static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419 };
420
421 static void vlv_clock(int refclk, intel_clock_t *clock)
422 {
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
429 }
430
431 static bool
432 needs_modeset(struct drm_crtc_state *state)
433 {
434 return state->mode_changed || state->active_changed;
435 }
436
437 /**
438 * Returns whether any output on the specified pipe is of the specified type
439 */
440 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
441 {
442 struct drm_device *dev = crtc->base.dev;
443 struct intel_encoder *encoder;
444
445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
446 if (encoder->type == type)
447 return true;
448
449 return false;
450 }
451
452 /**
453 * Returns whether any output on the specified pipe will have the specified
454 * type after a staged modeset is complete, i.e., the same as
455 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 * encoder->crtc.
457 */
458 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 int type)
460 {
461 struct drm_atomic_state *state = crtc_state->base.state;
462 struct drm_connector *connector;
463 struct drm_connector_state *connector_state;
464 struct intel_encoder *encoder;
465 int i, num_connectors = 0;
466
467 for_each_connector_in_state(state, connector, connector_state, i) {
468 if (connector_state->crtc != crtc_state->base.crtc)
469 continue;
470
471 num_connectors++;
472
473 encoder = to_intel_encoder(connector_state->best_encoder);
474 if (encoder->type == type)
475 return true;
476 }
477
478 WARN_ON(num_connectors == 0);
479
480 return false;
481 }
482
483 static const intel_limit_t *
484 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
485 {
486 struct drm_device *dev = crtc_state->base.crtc->dev;
487 const intel_limit_t *limit;
488
489 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
490 if (intel_is_dual_link_lvds(dev)) {
491 if (refclk == 100000)
492 limit = &intel_limits_ironlake_dual_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_dual_lvds;
495 } else {
496 if (refclk == 100000)
497 limit = &intel_limits_ironlake_single_lvds_100m;
498 else
499 limit = &intel_limits_ironlake_single_lvds;
500 }
501 } else
502 limit = &intel_limits_ironlake_dac;
503
504 return limit;
505 }
506
507 static const intel_limit_t *
508 intel_g4x_limit(struct intel_crtc_state *crtc_state)
509 {
510 struct drm_device *dev = crtc_state->base.crtc->dev;
511 const intel_limit_t *limit;
512
513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
514 if (intel_is_dual_link_lvds(dev))
515 limit = &intel_limits_g4x_dual_channel_lvds;
516 else
517 limit = &intel_limits_g4x_single_channel_lvds;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
519 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
520 limit = &intel_limits_g4x_hdmi;
521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
522 limit = &intel_limits_g4x_sdvo;
523 } else /* The option is for other outputs */
524 limit = &intel_limits_i9xx_sdvo;
525
526 return limit;
527 }
528
529 static const intel_limit_t *
530 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
531 {
532 struct drm_device *dev = crtc_state->base.crtc->dev;
533 const intel_limit_t *limit;
534
535 if (IS_BROXTON(dev))
536 limit = &intel_limits_bxt;
537 else if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc_state, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc_state);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_CHERRYVIEW(dev)) {
547 limit = &intel_limits_chv;
548 } else if (IS_VALLEYVIEW(dev)) {
549 limit = &intel_limits_vlv;
550 } else if (!IS_GEN2(dev)) {
551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
552 limit = &intel_limits_i9xx_lvds;
553 else
554 limit = &intel_limits_i9xx_sdvo;
555 } else {
556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
557 limit = &intel_limits_i8xx_lvds;
558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
559 limit = &intel_limits_i8xx_dvo;
560 else
561 limit = &intel_limits_i8xx_dac;
562 }
563 return limit;
564 }
565
566 /* m1 is reserved as 0 in Pineview, n is a ring counter */
567 static void pineview_clock(int refclk, intel_clock_t *clock)
568 {
569 clock->m = clock->m2 + 2;
570 clock->p = clock->p1 * clock->p2;
571 if (WARN_ON(clock->n == 0 || clock->p == 0))
572 return;
573 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
574 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
575 }
576
577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578 {
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580 }
581
582 static void i9xx_clock(int refclk, intel_clock_t *clock)
583 {
584 clock->m = i9xx_dpll_compute_m(clock);
585 clock->p = clock->p1 * clock->p2;
586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return;
588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 }
591
592 static void chv_clock(int refclk, intel_clock_t *clock)
593 {
594 clock->m = clock->m1 * clock->m2;
595 clock->p = clock->p1 * clock->p2;
596 if (WARN_ON(clock->n == 0 || clock->p == 0))
597 return;
598 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
599 clock->n << 22);
600 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
616 INTELPllInvalid("p1 out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621
622 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
623 if (clock->m1 <= clock->m2)
624 INTELPllInvalid("m1 <= m2\n");
625
626 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
627 if (clock->p < limit->p.min || limit->p.max < clock->p)
628 INTELPllInvalid("p out of range\n");
629 if (clock->m < limit->m.min || limit->m.max < clock->m)
630 INTELPllInvalid("m out of range\n");
631 }
632
633 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
634 INTELPllInvalid("vco out of range\n");
635 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
636 * connector, etc., rather than just a single range.
637 */
638 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
639 INTELPllInvalid("dot out of range\n");
640
641 return true;
642 }
643
644 static bool
645 i9xx_find_best_dpll(const intel_limit_t *limit,
646 struct intel_crtc_state *crtc_state,
647 int target, int refclk, intel_clock_t *match_clock,
648 intel_clock_t *best_clock)
649 {
650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
651 struct drm_device *dev = crtc->base.dev;
652 intel_clock_t clock;
653 int err = target;
654
655 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
656 /*
657 * For LVDS just rely on its current settings for dual-channel.
658 * We haven't figured out how to reliably set up different
659 * single/dual channel state, if we even can.
660 */
661 if (intel_is_dual_link_lvds(dev))
662 clock.p2 = limit->p2.p2_fast;
663 else
664 clock.p2 = limit->p2.p2_slow;
665 } else {
666 if (target < limit->p2.dot_limit)
667 clock.p2 = limit->p2.p2_slow;
668 else
669 clock.p2 = limit->p2.p2_fast;
670 }
671
672 memset(best_clock, 0, sizeof(*best_clock));
673
674 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
675 clock.m1++) {
676 for (clock.m2 = limit->m2.min;
677 clock.m2 <= limit->m2.max; clock.m2++) {
678 if (clock.m2 >= clock.m1)
679 break;
680 for (clock.n = limit->n.min;
681 clock.n <= limit->n.max; clock.n++) {
682 for (clock.p1 = limit->p1.min;
683 clock.p1 <= limit->p1.max; clock.p1++) {
684 int this_err;
685
686 i9xx_clock(refclk, &clock);
687 if (!intel_PLL_is_valid(dev, limit,
688 &clock))
689 continue;
690 if (match_clock &&
691 clock.p != match_clock->p)
692 continue;
693
694 this_err = abs(clock.dot - target);
695 if (this_err < err) {
696 *best_clock = clock;
697 err = this_err;
698 }
699 }
700 }
701 }
702 }
703
704 return (err != target);
705 }
706
707 static bool
708 pnv_find_best_dpll(const intel_limit_t *limit,
709 struct intel_crtc_state *crtc_state,
710 int target, int refclk, intel_clock_t *match_clock,
711 intel_clock_t *best_clock)
712 {
713 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
714 struct drm_device *dev = crtc->base.dev;
715 intel_clock_t clock;
716 int err = target;
717
718 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
719 /*
720 * For LVDS just rely on its current settings for dual-channel.
721 * We haven't figured out how to reliably set up different
722 * single/dual channel state, if we even can.
723 */
724 if (intel_is_dual_link_lvds(dev))
725 clock.p2 = limit->p2.p2_fast;
726 else
727 clock.p2 = limit->p2.p2_slow;
728 } else {
729 if (target < limit->p2.dot_limit)
730 clock.p2 = limit->p2.p2_slow;
731 else
732 clock.p2 = limit->p2.p2_fast;
733 }
734
735 memset(best_clock, 0, sizeof(*best_clock));
736
737 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
738 clock.m1++) {
739 for (clock.m2 = limit->m2.min;
740 clock.m2 <= limit->m2.max; clock.m2++) {
741 for (clock.n = limit->n.min;
742 clock.n <= limit->n.max; clock.n++) {
743 for (clock.p1 = limit->p1.min;
744 clock.p1 <= limit->p1.max; clock.p1++) {
745 int this_err;
746
747 pineview_clock(refclk, &clock);
748 if (!intel_PLL_is_valid(dev, limit,
749 &clock))
750 continue;
751 if (match_clock &&
752 clock.p != match_clock->p)
753 continue;
754
755 this_err = abs(clock.dot - target);
756 if (this_err < err) {
757 *best_clock = clock;
758 err = this_err;
759 }
760 }
761 }
762 }
763 }
764
765 return (err != target);
766 }
767
768 static bool
769 g4x_find_best_dpll(const intel_limit_t *limit,
770 struct intel_crtc_state *crtc_state,
771 int target, int refclk, intel_clock_t *match_clock,
772 intel_clock_t *best_clock)
773 {
774 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
775 struct drm_device *dev = crtc->base.dev;
776 intel_clock_t clock;
777 int max_n;
778 bool found;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
781 found = false;
782
783 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
784 if (intel_is_dual_link_lvds(dev))
785 clock.p2 = limit->p2.p2_fast;
786 else
787 clock.p2 = limit->p2.p2_slow;
788 } else {
789 if (target < limit->p2.dot_limit)
790 clock.p2 = limit->p2.p2_slow;
791 else
792 clock.p2 = limit->p2.p2_fast;
793 }
794
795 memset(best_clock, 0, sizeof(*best_clock));
796 max_n = limit->n.max;
797 /* based on hardware requirement, prefer smaller n to precision */
798 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
799 /* based on hardware requirement, prefere larger m1,m2 */
800 for (clock.m1 = limit->m1.max;
801 clock.m1 >= limit->m1.min; clock.m1--) {
802 for (clock.m2 = limit->m2.max;
803 clock.m2 >= limit->m2.min; clock.m2--) {
804 for (clock.p1 = limit->p1.max;
805 clock.p1 >= limit->p1.min; clock.p1--) {
806 int this_err;
807
808 i9xx_clock(refclk, &clock);
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 this_err = abs(clock.dot - target);
814 if (this_err < err_most) {
815 *best_clock = clock;
816 err_most = this_err;
817 max_n = clock.n;
818 found = true;
819 }
820 }
821 }
822 }
823 }
824 return found;
825 }
826
827 /*
828 * Check if the calculated PLL configuration is more optimal compared to the
829 * best configuration and error found so far. Return the calculated error.
830 */
831 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
832 const intel_clock_t *calculated_clock,
833 const intel_clock_t *best_clock,
834 unsigned int best_error_ppm,
835 unsigned int *error_ppm)
836 {
837 /*
838 * For CHV ignore the error and consider only the P value.
839 * Prefer a bigger P value based on HW requirements.
840 */
841 if (IS_CHERRYVIEW(dev)) {
842 *error_ppm = 0;
843
844 return calculated_clock->p > best_clock->p;
845 }
846
847 if (WARN_ON_ONCE(!target_freq))
848 return false;
849
850 *error_ppm = div_u64(1000000ULL *
851 abs(target_freq - calculated_clock->dot),
852 target_freq);
853 /*
854 * Prefer a better P value over a better (smaller) error if the error
855 * is small. Ensure this preference for future configurations too by
856 * setting the error to 0.
857 */
858 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
859 *error_ppm = 0;
860
861 return true;
862 }
863
864 return *error_ppm + 10 < best_error_ppm;
865 }
866
867 static bool
868 vlv_find_best_dpll(const intel_limit_t *limit,
869 struct intel_crtc_state *crtc_state,
870 int target, int refclk, intel_clock_t *match_clock,
871 intel_clock_t *best_clock)
872 {
873 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
874 struct drm_device *dev = crtc->base.dev;
875 intel_clock_t clock;
876 unsigned int bestppm = 1000000;
877 /* min update 19.2 MHz */
878 int max_n = min(limit->n.max, refclk / 19200);
879 bool found = false;
880
881 target *= 5; /* fast clock */
882
883 memset(best_clock, 0, sizeof(*best_clock));
884
885 /* based on hardware requirement, prefer smaller n to precision */
886 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
887 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
888 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
889 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
890 clock.p = clock.p1 * clock.p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
893 unsigned int ppm;
894
895 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
896 refclk * clock.m1);
897
898 vlv_clock(refclk, &clock);
899
900 if (!intel_PLL_is_valid(dev, limit,
901 &clock))
902 continue;
903
904 if (!vlv_PLL_is_optimal(dev, target,
905 &clock,
906 best_clock,
907 bestppm, &ppm))
908 continue;
909
910 *best_clock = clock;
911 bestppm = ppm;
912 found = true;
913 }
914 }
915 }
916 }
917
918 return found;
919 }
920
921 static bool
922 chv_find_best_dpll(const intel_limit_t *limit,
923 struct intel_crtc_state *crtc_state,
924 int target, int refclk, intel_clock_t *match_clock,
925 intel_clock_t *best_clock)
926 {
927 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
928 struct drm_device *dev = crtc->base.dev;
929 unsigned int best_error_ppm;
930 intel_clock_t clock;
931 uint64_t m2;
932 int found = false;
933
934 memset(best_clock, 0, sizeof(*best_clock));
935 best_error_ppm = 1000000;
936
937 /*
938 * Based on hardware doc, the n always set to 1, and m1 always
939 * set to 2. If requires to support 200Mhz refclk, we need to
940 * revisit this because n may not 1 anymore.
941 */
942 clock.n = 1, clock.m1 = 2;
943 target *= 5; /* fast clock */
944
945 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
946 for (clock.p2 = limit->p2.p2_fast;
947 clock.p2 >= limit->p2.p2_slow;
948 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
949 unsigned int error_ppm;
950
951 clock.p = clock.p1 * clock.p2;
952
953 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
954 clock.n) << 22, refclk * clock.m1);
955
956 if (m2 > INT_MAX/clock.m1)
957 continue;
958
959 clock.m2 = m2;
960
961 chv_clock(refclk, &clock);
962
963 if (!intel_PLL_is_valid(dev, limit, &clock))
964 continue;
965
966 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
967 best_error_ppm, &error_ppm))
968 continue;
969
970 *best_clock = clock;
971 best_error_ppm = error_ppm;
972 found = true;
973 }
974 }
975
976 return found;
977 }
978
979 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
980 intel_clock_t *best_clock)
981 {
982 int refclk = i9xx_get_refclk(crtc_state, 0);
983
984 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
985 target_clock, refclk, NULL, best_clock);
986 }
987
988 bool intel_crtc_active(struct drm_crtc *crtc)
989 {
990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
991
992 /* Be paranoid as we can arrive here with only partial
993 * state retrieved from the hardware during setup.
994 *
995 * We can ditch the adjusted_mode.crtc_clock check as soon
996 * as Haswell has gained clock readout/fastboot support.
997 *
998 * We can ditch the crtc->primary->fb check as soon as we can
999 * properly reconstruct framebuffers.
1000 *
1001 * FIXME: The intel_crtc->active here should be switched to
1002 * crtc->state->active once we have proper CRTC states wired up
1003 * for atomic.
1004 */
1005 return intel_crtc->active && crtc->primary->state->fb &&
1006 intel_crtc->config->base.adjusted_mode.crtc_clock;
1007 }
1008
1009 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011 {
1012 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1014
1015 return intel_crtc->config->cpu_transcoder;
1016 }
1017
1018 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1019 {
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 u32 reg = PIPEDSL(pipe);
1022 u32 line1, line2;
1023 u32 line_mask;
1024
1025 if (IS_GEN2(dev))
1026 line_mask = DSL_LINEMASK_GEN2;
1027 else
1028 line_mask = DSL_LINEMASK_GEN3;
1029
1030 line1 = I915_READ(reg) & line_mask;
1031 mdelay(5);
1032 line2 = I915_READ(reg) & line_mask;
1033
1034 return line1 == line2;
1035 }
1036
1037 /*
1038 * intel_wait_for_pipe_off - wait for pipe to turn off
1039 * @crtc: crtc whose pipe to wait for
1040 *
1041 * After disabling a pipe, we can't wait for vblank in the usual way,
1042 * spinning on the vblank interrupt status bit, since we won't actually
1043 * see an interrupt when the pipe is disabled.
1044 *
1045 * On Gen4 and above:
1046 * wait for the pipe register state bit to turn off
1047 *
1048 * Otherwise:
1049 * wait for the display line value to settle (it usually
1050 * ends up stopping at the start of the next frame).
1051 *
1052 */
1053 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1054 {
1055 struct drm_device *dev = crtc->base.dev;
1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1058 enum pipe pipe = crtc->pipe;
1059
1060 if (INTEL_INFO(dev)->gen >= 4) {
1061 int reg = PIPECONF(cpu_transcoder);
1062
1063 /* Wait for the Pipe State to go off */
1064 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1065 100))
1066 WARN(1, "pipe_off wait timed out\n");
1067 } else {
1068 /* Wait for the display line to settle */
1069 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1070 WARN(1, "pipe_off wait timed out\n");
1071 }
1072 }
1073
1074 /*
1075 * ibx_digital_port_connected - is the specified port connected?
1076 * @dev_priv: i915 private structure
1077 * @port: the port to test
1078 *
1079 * Returns true if @port is connected, false otherwise.
1080 */
1081 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1082 struct intel_digital_port *port)
1083 {
1084 u32 bit;
1085
1086 if (HAS_PCH_IBX(dev_priv->dev)) {
1087 switch (port->port) {
1088 case PORT_B:
1089 bit = SDE_PORTB_HOTPLUG;
1090 break;
1091 case PORT_C:
1092 bit = SDE_PORTC_HOTPLUG;
1093 break;
1094 case PORT_D:
1095 bit = SDE_PORTD_HOTPLUG;
1096 break;
1097 default:
1098 return true;
1099 }
1100 } else {
1101 switch (port->port) {
1102 case PORT_B:
1103 bit = SDE_PORTB_HOTPLUG_CPT;
1104 break;
1105 case PORT_C:
1106 bit = SDE_PORTC_HOTPLUG_CPT;
1107 break;
1108 case PORT_D:
1109 bit = SDE_PORTD_HOTPLUG_CPT;
1110 break;
1111 default:
1112 return true;
1113 }
1114 }
1115
1116 return I915_READ(SDEISR) & bit;
1117 }
1118
1119 static const char *state_string(bool enabled)
1120 {
1121 return enabled ? "on" : "off";
1122 }
1123
1124 /* Only for pre-ILK configs */
1125 void assert_pll(struct drm_i915_private *dev_priv,
1126 enum pipe pipe, bool state)
1127 {
1128 int reg;
1129 u32 val;
1130 bool cur_state;
1131
1132 reg = DPLL(pipe);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & DPLL_VCO_ENABLE);
1135 I915_STATE_WARN(cur_state != state,
1136 "PLL state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138 }
1139
1140 /* XXX: the dsi pll is shared between MIPI DSI ports */
1141 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1142 {
1143 u32 val;
1144 bool cur_state;
1145
1146 mutex_lock(&dev_priv->sb_lock);
1147 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1148 mutex_unlock(&dev_priv->sb_lock);
1149
1150 cur_state = val & DSI_PLL_VCO_EN;
1151 I915_STATE_WARN(cur_state != state,
1152 "DSI PLL state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1156 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1157
1158 struct intel_shared_dpll *
1159 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1160 {
1161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1162
1163 if (crtc->config->shared_dpll < 0)
1164 return NULL;
1165
1166 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1167 }
1168
1169 /* For ILK+ */
1170 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1171 struct intel_shared_dpll *pll,
1172 bool state)
1173 {
1174 bool cur_state;
1175 struct intel_dpll_hw_state hw_state;
1176
1177 if (WARN (!pll,
1178 "asserting DPLL %s with no DPLL\n", state_string(state)))
1179 return;
1180
1181 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1182 I915_STATE_WARN(cur_state != state,
1183 "%s assertion failure (expected %s, current %s)\n",
1184 pll->name, state_string(state), state_string(cur_state));
1185 }
1186
1187 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
1189 {
1190 int reg;
1191 u32 val;
1192 bool cur_state;
1193 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1194 pipe);
1195
1196 if (HAS_DDI(dev_priv->dev)) {
1197 /* DDI does not have a specific FDI_TX register */
1198 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1201 } else {
1202 reg = FDI_TX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_TX_ENABLE);
1205 }
1206 I915_STATE_WARN(cur_state != state,
1207 "FDI TX state assertion failure (expected %s, current %s)\n",
1208 state_string(state), state_string(cur_state));
1209 }
1210 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1211 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1212
1213 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 int reg;
1217 u32 val;
1218 bool cur_state;
1219
1220 reg = FDI_RX_CTL(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & FDI_RX_ENABLE);
1223 I915_STATE_WARN(cur_state != state,
1224 "FDI RX state assertion failure (expected %s, current %s)\n",
1225 state_string(state), state_string(cur_state));
1226 }
1227 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1228 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1229
1230 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235
1236 /* ILK FDI PLL is always enabled */
1237 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1238 return;
1239
1240 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1241 if (HAS_DDI(dev_priv->dev))
1242 return;
1243
1244 reg = FDI_TX_CTL(pipe);
1245 val = I915_READ(reg);
1246 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1247 }
1248
1249 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1250 enum pipe pipe, bool state)
1251 {
1252 int reg;
1253 u32 val;
1254 bool cur_state;
1255
1256 reg = FDI_RX_CTL(pipe);
1257 val = I915_READ(reg);
1258 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1259 I915_STATE_WARN(cur_state != state,
1260 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1261 state_string(state), state_string(cur_state));
1262 }
1263
1264 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1265 enum pipe pipe)
1266 {
1267 struct drm_device *dev = dev_priv->dev;
1268 int pp_reg;
1269 u32 val;
1270 enum pipe panel_pipe = PIPE_A;
1271 bool locked = true;
1272
1273 if (WARN_ON(HAS_DDI(dev)))
1274 return;
1275
1276 if (HAS_PCH_SPLIT(dev)) {
1277 u32 port_sel;
1278
1279 pp_reg = PCH_PP_CONTROL;
1280 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1281
1282 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1283 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1284 panel_pipe = PIPE_B;
1285 /* XXX: else fix for eDP */
1286 } else if (IS_VALLEYVIEW(dev)) {
1287 /* presumably write lock depends on pipe, not port select */
1288 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1289 panel_pipe = pipe;
1290 } else {
1291 pp_reg = PP_CONTROL;
1292 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1293 panel_pipe = PIPE_B;
1294 }
1295
1296 val = I915_READ(pp_reg);
1297 if (!(val & PANEL_POWER_ON) ||
1298 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1299 locked = false;
1300
1301 I915_STATE_WARN(panel_pipe == pipe && locked,
1302 "panel assertion failure, pipe %c regs locked\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static void assert_cursor(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
1308 {
1309 struct drm_device *dev = dev_priv->dev;
1310 bool cur_state;
1311
1312 if (IS_845G(dev) || IS_I865G(dev))
1313 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1314 else
1315 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1316
1317 I915_STATE_WARN(cur_state != state,
1318 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe), state_string(state), state_string(cur_state));
1320 }
1321 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1322 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1323
1324 void assert_pipe(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, bool state)
1326 {
1327 int reg;
1328 u32 val;
1329 bool cur_state;
1330 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1331 pipe);
1332
1333 /* if we need the pipe quirk it must be always on */
1334 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1335 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1336 state = true;
1337
1338 if (!intel_display_power_is_enabled(dev_priv,
1339 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1340 cur_state = false;
1341 } else {
1342 reg = PIPECONF(cpu_transcoder);
1343 val = I915_READ(reg);
1344 cur_state = !!(val & PIPECONF_ENABLE);
1345 }
1346
1347 I915_STATE_WARN(cur_state != state,
1348 "pipe %c assertion failure (expected %s, current %s)\n",
1349 pipe_name(pipe), state_string(state), state_string(cur_state));
1350 }
1351
1352 static void assert_plane(struct drm_i915_private *dev_priv,
1353 enum plane plane, bool state)
1354 {
1355 int reg;
1356 u32 val;
1357 bool cur_state;
1358
1359 reg = DSPCNTR(plane);
1360 val = I915_READ(reg);
1361 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1362 I915_STATE_WARN(cur_state != state,
1363 "plane %c assertion failure (expected %s, current %s)\n",
1364 plane_name(plane), state_string(state), state_string(cur_state));
1365 }
1366
1367 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1368 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1369
1370 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe)
1372 {
1373 struct drm_device *dev = dev_priv->dev;
1374 int reg, i;
1375 u32 val;
1376 int cur_pipe;
1377
1378 /* Primary planes are fixed to pipes on gen4+ */
1379 if (INTEL_INFO(dev)->gen >= 4) {
1380 reg = DSPCNTR(pipe);
1381 val = I915_READ(reg);
1382 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1383 "plane %c assertion failure, should be disabled but not\n",
1384 plane_name(pipe));
1385 return;
1386 }
1387
1388 /* Need to check both planes against the pipe */
1389 for_each_pipe(dev_priv, i) {
1390 reg = DSPCNTR(i);
1391 val = I915_READ(reg);
1392 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1393 DISPPLANE_SEL_PIPE_SHIFT;
1394 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1395 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1396 plane_name(i), pipe_name(pipe));
1397 }
1398 }
1399
1400 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402 {
1403 struct drm_device *dev = dev_priv->dev;
1404 int reg, sprite;
1405 u32 val;
1406
1407 if (INTEL_INFO(dev)->gen >= 9) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 val = I915_READ(PLANE_CTL(pipe, sprite));
1410 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1411 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1412 sprite, pipe_name(pipe));
1413 }
1414 } else if (IS_VALLEYVIEW(dev)) {
1415 for_each_sprite(dev_priv, pipe, sprite) {
1416 reg = SPCNTR(pipe, sprite);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SP_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 sprite_name(pipe, sprite), pipe_name(pipe));
1421 }
1422 } else if (INTEL_INFO(dev)->gen >= 7) {
1423 reg = SPRCTL(pipe);
1424 val = I915_READ(reg);
1425 I915_STATE_WARN(val & SPRITE_ENABLE,
1426 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1427 plane_name(pipe), pipe_name(pipe));
1428 } else if (INTEL_INFO(dev)->gen >= 5) {
1429 reg = DVSCNTR(pipe);
1430 val = I915_READ(reg);
1431 I915_STATE_WARN(val & DVS_ENABLE,
1432 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1433 plane_name(pipe), pipe_name(pipe));
1434 }
1435 }
1436
1437 static void assert_vblank_disabled(struct drm_crtc *crtc)
1438 {
1439 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1440 drm_crtc_vblank_put(crtc);
1441 }
1442
1443 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1444 {
1445 u32 val;
1446 bool enabled;
1447
1448 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1449
1450 val = I915_READ(PCH_DREF_CONTROL);
1451 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1452 DREF_SUPERSPREAD_SOURCE_MASK));
1453 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1454 }
1455
1456 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe)
1458 {
1459 int reg;
1460 u32 val;
1461 bool enabled;
1462
1463 reg = PCH_TRANSCONF(pipe);
1464 val = I915_READ(reg);
1465 enabled = !!(val & TRANS_ENABLE);
1466 I915_STATE_WARN(enabled,
1467 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1468 pipe_name(pipe));
1469 }
1470
1471 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe, u32 port_sel, u32 val)
1473 {
1474 if ((val & DP_PORT_EN) == 0)
1475 return false;
1476
1477 if (HAS_PCH_CPT(dev_priv->dev)) {
1478 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1479 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1480 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1481 return false;
1482 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1483 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 return false;
1485 } else {
1486 if ((val & DP_PIPE_MASK) != (pipe << 30))
1487 return false;
1488 }
1489 return true;
1490 }
1491
1492 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe, u32 val)
1494 {
1495 if ((val & SDVO_ENABLE) == 0)
1496 return false;
1497
1498 if (HAS_PCH_CPT(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1500 return false;
1501 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1502 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 return false;
1504 } else {
1505 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1506 return false;
1507 }
1508 return true;
1509 }
1510
1511 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1512 enum pipe pipe, u32 val)
1513 {
1514 if ((val & LVDS_PORT_EN) == 0)
1515 return false;
1516
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1522 return false;
1523 }
1524 return true;
1525 }
1526
1527 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, u32 val)
1529 {
1530 if ((val & ADPA_DAC_ENABLE) == 0)
1531 return false;
1532 if (HAS_PCH_CPT(dev_priv->dev)) {
1533 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 return false;
1535 } else {
1536 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1537 return false;
1538 }
1539 return true;
1540 }
1541
1542 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1543 enum pipe pipe, int reg, u32 port_sel)
1544 {
1545 u32 val = I915_READ(reg);
1546 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1547 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1548 reg, pipe_name(pipe));
1549
1550 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1551 && (val & DP_PIPEB_SELECT),
1552 "IBX PCH dp port still using transcoder B\n");
1553 }
1554
1555 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1556 enum pipe pipe, int reg)
1557 {
1558 u32 val = I915_READ(reg);
1559 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1560 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1561 reg, pipe_name(pipe));
1562
1563 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1564 && (val & SDVO_PIPE_B_SELECT),
1565 "IBX PCH hdmi port still using transcoder B\n");
1566 }
1567
1568 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1569 enum pipe pipe)
1570 {
1571 int reg;
1572 u32 val;
1573
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577
1578 reg = PCH_ADPA;
1579 val = I915_READ(reg);
1580 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1581 "PCH VGA enabled on transcoder %c, should be disabled\n",
1582 pipe_name(pipe));
1583
1584 reg = PCH_LVDS;
1585 val = I915_READ(reg);
1586 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1587 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1588 pipe_name(pipe));
1589
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1591 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1593 }
1594
1595 static void intel_init_dpio(struct drm_device *dev)
1596 {
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598
1599 if (!IS_VALLEYVIEW(dev))
1600 return;
1601
1602 /*
1603 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1604 * CHV x1 PHY (DP/HDMI D)
1605 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1606 */
1607 if (IS_CHERRYVIEW(dev)) {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1610 } else {
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1612 }
1613 }
1614
1615 static void vlv_enable_pll(struct intel_crtc *crtc,
1616 const struct intel_crtc_state *pipe_config)
1617 {
1618 struct drm_device *dev = crtc->base.dev;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 int reg = DPLL(crtc->pipe);
1621 u32 dpll = pipe_config->dpll_hw_state.dpll;
1622
1623 assert_pipe_disabled(dev_priv, crtc->pipe);
1624
1625 /* No really, not for ILK+ */
1626 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1627
1628 /* PLL is protected by panel, make sure we can write it */
1629 if (IS_MOBILE(dev_priv->dev))
1630 assert_panel_unlocked(dev_priv, crtc->pipe);
1631
1632 I915_WRITE(reg, dpll);
1633 POSTING_READ(reg);
1634 udelay(150);
1635
1636 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1637 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1638
1639 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1640 POSTING_READ(DPLL_MD(crtc->pipe));
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 static void chv_enable_pll(struct intel_crtc *crtc,
1655 const struct intel_crtc_state *pipe_config)
1656 {
1657 struct drm_device *dev = crtc->base.dev;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 int pipe = crtc->pipe;
1660 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1661 u32 tmp;
1662
1663 assert_pipe_disabled(dev_priv, crtc->pipe);
1664
1665 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1666
1667 mutex_lock(&dev_priv->sb_lock);
1668
1669 /* Enable back the 10bit clock to display controller */
1670 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1671 tmp |= DPIO_DCLKP_EN;
1672 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1673
1674 mutex_unlock(&dev_priv->sb_lock);
1675
1676 /*
1677 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1678 */
1679 udelay(1);
1680
1681 /* Enable PLL */
1682 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1683
1684 /* Check PLL is locked */
1685 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1686 DRM_ERROR("PLL %d failed to lock\n", pipe);
1687
1688 /* not sure when this should be written */
1689 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1690 POSTING_READ(DPLL_MD(pipe));
1691 }
1692
1693 static int intel_num_dvo_pipes(struct drm_device *dev)
1694 {
1695 struct intel_crtc *crtc;
1696 int count = 0;
1697
1698 for_each_intel_crtc(dev, crtc)
1699 count += crtc->base.state->active &&
1700 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1701
1702 return count;
1703 }
1704
1705 static void i9xx_enable_pll(struct intel_crtc *crtc)
1706 {
1707 struct drm_device *dev = crtc->base.dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 int reg = DPLL(crtc->pipe);
1710 u32 dpll = crtc->config->dpll_hw_state.dpll;
1711
1712 assert_pipe_disabled(dev_priv, crtc->pipe);
1713
1714 /* No really, not for ILK+ */
1715 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1716
1717 /* PLL is protected by panel, make sure we can write it */
1718 if (IS_MOBILE(dev) && !IS_I830(dev))
1719 assert_panel_unlocked(dev_priv, crtc->pipe);
1720
1721 /* Enable DVO 2x clock on both PLLs if necessary */
1722 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1723 /*
1724 * It appears to be important that we don't enable this
1725 * for the current pipe before otherwise configuring the
1726 * PLL. No idea how this should be handled if multiple
1727 * DVO outputs are enabled simultaneosly.
1728 */
1729 dpll |= DPLL_DVO_2X_MODE;
1730 I915_WRITE(DPLL(!crtc->pipe),
1731 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1732 }
1733
1734 /* Wait for the clocks to stabilize. */
1735 POSTING_READ(reg);
1736 udelay(150);
1737
1738 if (INTEL_INFO(dev)->gen >= 4) {
1739 I915_WRITE(DPLL_MD(crtc->pipe),
1740 crtc->config->dpll_hw_state.dpll_md);
1741 } else {
1742 /* The pixel multiplier can only be updated once the
1743 * DPLL is enabled and the clocks are stable.
1744 *
1745 * So write it again.
1746 */
1747 I915_WRITE(reg, dpll);
1748 }
1749
1750 /* We do this three times for luck */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg, dpll);
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757 I915_WRITE(reg, dpll);
1758 POSTING_READ(reg);
1759 udelay(150); /* wait for warmup */
1760 }
1761
1762 /**
1763 * i9xx_disable_pll - disable a PLL
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to disable
1766 *
1767 * Disable the PLL for @pipe, making sure the pipe is off first.
1768 *
1769 * Note! This is for pre-ILK only.
1770 */
1771 static void i9xx_disable_pll(struct intel_crtc *crtc)
1772 {
1773 struct drm_device *dev = crtc->base.dev;
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 enum pipe pipe = crtc->pipe;
1776
1777 /* Disable DVO 2x clock on both PLLs if necessary */
1778 if (IS_I830(dev) &&
1779 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1780 !intel_num_dvo_pipes(dev)) {
1781 I915_WRITE(DPLL(PIPE_B),
1782 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1783 I915_WRITE(DPLL(PIPE_A),
1784 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1785 }
1786
1787 /* Don't disable pipe or pipe PLLs if needed */
1788 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1789 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1790 return;
1791
1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
1794
1795 I915_WRITE(DPLL(pipe), 0);
1796 POSTING_READ(DPLL(pipe));
1797 }
1798
1799 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800 {
1801 u32 val = 0;
1802
1803 /* Make sure the pipe isn't still relying on us */
1804 assert_pipe_disabled(dev_priv, pipe);
1805
1806 /*
1807 * Leave integrated clock source and reference clock enabled for pipe B.
1808 * The latter is needed for VGA hotplug / manual detection.
1809 */
1810 if (pipe == PIPE_B)
1811 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1812 I915_WRITE(DPLL(pipe), val);
1813 POSTING_READ(DPLL(pipe));
1814
1815 }
1816
1817 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1818 {
1819 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1820 u32 val;
1821
1822 /* Make sure the pipe isn't still relying on us */
1823 assert_pipe_disabled(dev_priv, pipe);
1824
1825 /* Set PLL en = 0 */
1826 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1827 if (pipe != PIPE_A)
1828 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1829 I915_WRITE(DPLL(pipe), val);
1830 POSTING_READ(DPLL(pipe));
1831
1832 mutex_lock(&dev_priv->sb_lock);
1833
1834 /* Disable 10bit clock to display controller */
1835 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1836 val &= ~DPIO_DCLKP_EN;
1837 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1838
1839 /* disable left/right clock distribution */
1840 if (pipe != PIPE_B) {
1841 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1842 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1843 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1844 } else {
1845 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1846 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1847 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 }
1849
1850 mutex_unlock(&dev_priv->sb_lock);
1851 }
1852
1853 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1854 struct intel_digital_port *dport,
1855 unsigned int expected_mask)
1856 {
1857 u32 port_mask;
1858 int dpll_reg;
1859
1860 switch (dport->port) {
1861 case PORT_B:
1862 port_mask = DPLL_PORTB_READY_MASK;
1863 dpll_reg = DPLL(0);
1864 break;
1865 case PORT_C:
1866 port_mask = DPLL_PORTC_READY_MASK;
1867 dpll_reg = DPLL(0);
1868 expected_mask <<= 4;
1869 break;
1870 case PORT_D:
1871 port_mask = DPLL_PORTD_READY_MASK;
1872 dpll_reg = DPIO_PHY_STATUS;
1873 break;
1874 default:
1875 BUG();
1876 }
1877
1878 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1879 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1880 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1881 }
1882
1883 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 WARN_ON(!pll->config.crtc_mask);
1893 if (pll->active == 0) {
1894 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1895 WARN_ON(pll->on);
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897
1898 pll->mode_set(dev_priv, pll);
1899 }
1900 }
1901
1902 /**
1903 * intel_enable_shared_dpll - enable PCH PLL
1904 * @dev_priv: i915 private structure
1905 * @pipe: pipe PLL to enable
1906 *
1907 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1908 * drives the transcoder clock.
1909 */
1910 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1911 {
1912 struct drm_device *dev = crtc->base.dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1915
1916 if (WARN_ON(pll == NULL))
1917 return;
1918
1919 if (WARN_ON(pll->config.crtc_mask == 0))
1920 return;
1921
1922 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1923 pll->name, pll->active, pll->on,
1924 crtc->base.base.id);
1925
1926 if (pll->active++) {
1927 WARN_ON(!pll->on);
1928 assert_shared_dpll_enabled(dev_priv, pll);
1929 return;
1930 }
1931 WARN_ON(pll->on);
1932
1933 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1934
1935 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1936 pll->enable(dev_priv, pll);
1937 pll->on = true;
1938 }
1939
1940 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1941 {
1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1945
1946 /* PCH only available on ILK+ */
1947 BUG_ON(INTEL_INFO(dev)->gen < 5);
1948 if (pll == NULL)
1949 return;
1950
1951 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1952 return;
1953
1954 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1955 pll->name, pll->active, pll->on,
1956 crtc->base.base.id);
1957
1958 if (WARN_ON(pll->active == 0)) {
1959 assert_shared_dpll_disabled(dev_priv, pll);
1960 return;
1961 }
1962
1963 assert_shared_dpll_enabled(dev_priv, pll);
1964 WARN_ON(!pll->on);
1965 if (--pll->active)
1966 return;
1967
1968 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1969 pll->disable(dev_priv, pll);
1970 pll->on = false;
1971
1972 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1973 }
1974
1975 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 enum pipe pipe)
1977 {
1978 struct drm_device *dev = dev_priv->dev;
1979 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981 uint32_t reg, val, pipeconf_val;
1982
1983 /* PCH only available on ILK+ */
1984 BUG_ON(!HAS_PCH_SPLIT(dev));
1985
1986 /* Make sure PCH DPLL is enabled */
1987 assert_shared_dpll_enabled(dev_priv,
1988 intel_crtc_to_shared_dpll(intel_crtc));
1989
1990 /* FDI must be feeding us bits for PCH ports */
1991 assert_fdi_tx_enabled(dev_priv, pipe);
1992 assert_fdi_rx_enabled(dev_priv, pipe);
1993
1994 if (HAS_PCH_CPT(dev)) {
1995 /* Workaround: Set the timing override bit before enabling the
1996 * pch transcoder. */
1997 reg = TRANS_CHICKEN2(pipe);
1998 val = I915_READ(reg);
1999 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2000 I915_WRITE(reg, val);
2001 }
2002
2003 reg = PCH_TRANSCONF(pipe);
2004 val = I915_READ(reg);
2005 pipeconf_val = I915_READ(PIPECONF(pipe));
2006
2007 if (HAS_PCH_IBX(dev_priv->dev)) {
2008 /*
2009 * Make the BPC in transcoder be consistent with
2010 * that in pipeconf reg. For HDMI we must use 8bpc
2011 * here for both 8bpc and 12bpc.
2012 */
2013 val &= ~PIPECONF_BPC_MASK;
2014 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2015 val |= PIPECONF_8BPC;
2016 else
2017 val |= pipeconf_val & PIPECONF_BPC_MASK;
2018 }
2019
2020 val &= ~TRANS_INTERLACE_MASK;
2021 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2022 if (HAS_PCH_IBX(dev_priv->dev) &&
2023 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2024 val |= TRANS_LEGACY_INTERLACED_ILK;
2025 else
2026 val |= TRANS_INTERLACED;
2027 else
2028 val |= TRANS_PROGRESSIVE;
2029
2030 I915_WRITE(reg, val | TRANS_ENABLE);
2031 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2032 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2033 }
2034
2035 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2036 enum transcoder cpu_transcoder)
2037 {
2038 u32 val, pipeconf_val;
2039
2040 /* PCH only available on ILK+ */
2041 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2042
2043 /* FDI must be feeding us bits for PCH ports */
2044 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2045 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2046
2047 /* Workaround: set timing override bit. */
2048 val = I915_READ(_TRANSA_CHICKEN2);
2049 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2050 I915_WRITE(_TRANSA_CHICKEN2, val);
2051
2052 val = TRANS_ENABLE;
2053 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2054
2055 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2056 PIPECONF_INTERLACED_ILK)
2057 val |= TRANS_INTERLACED;
2058 else
2059 val |= TRANS_PROGRESSIVE;
2060
2061 I915_WRITE(LPT_TRANSCONF, val);
2062 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2063 DRM_ERROR("Failed to enable PCH transcoder\n");
2064 }
2065
2066 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067 enum pipe pipe)
2068 {
2069 struct drm_device *dev = dev_priv->dev;
2070 uint32_t reg, val;
2071
2072 /* FDI relies on the transcoder */
2073 assert_fdi_tx_disabled(dev_priv, pipe);
2074 assert_fdi_rx_disabled(dev_priv, pipe);
2075
2076 /* Ports must be off as well */
2077 assert_pch_ports_disabled(dev_priv, pipe);
2078
2079 reg = PCH_TRANSCONF(pipe);
2080 val = I915_READ(reg);
2081 val &= ~TRANS_ENABLE;
2082 I915_WRITE(reg, val);
2083 /* wait for PCH transcoder off, transcoder state */
2084 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2085 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2086
2087 if (!HAS_PCH_IBX(dev)) {
2088 /* Workaround: Clear the timing override chicken bit again. */
2089 reg = TRANS_CHICKEN2(pipe);
2090 val = I915_READ(reg);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(reg, val);
2093 }
2094 }
2095
2096 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2097 {
2098 u32 val;
2099
2100 val = I915_READ(LPT_TRANSCONF);
2101 val &= ~TRANS_ENABLE;
2102 I915_WRITE(LPT_TRANSCONF, val);
2103 /* wait for PCH transcoder off, transcoder state */
2104 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2105 DRM_ERROR("Failed to disable PCH transcoder\n");
2106
2107 /* Workaround: clear timing override bit. */
2108 val = I915_READ(_TRANSA_CHICKEN2);
2109 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2110 I915_WRITE(_TRANSA_CHICKEN2, val);
2111 }
2112
2113 /**
2114 * intel_enable_pipe - enable a pipe, asserting requirements
2115 * @crtc: crtc responsible for the pipe
2116 *
2117 * Enable @crtc's pipe, making sure that various hardware specific requirements
2118 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2119 */
2120 static void intel_enable_pipe(struct intel_crtc *crtc)
2121 {
2122 struct drm_device *dev = crtc->base.dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 enum pipe pipe = crtc->pipe;
2125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2126 pipe);
2127 enum pipe pch_transcoder;
2128 int reg;
2129 u32 val;
2130
2131 assert_planes_disabled(dev_priv, pipe);
2132 assert_cursor_disabled(dev_priv, pipe);
2133 assert_sprites_disabled(dev_priv, pipe);
2134
2135 if (HAS_PCH_LPT(dev_priv->dev))
2136 pch_transcoder = TRANSCODER_A;
2137 else
2138 pch_transcoder = pipe;
2139
2140 /*
2141 * A pipe without a PLL won't actually be able to drive bits from
2142 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2143 * need the check.
2144 */
2145 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2147 assert_dsi_pll_enabled(dev_priv);
2148 else
2149 assert_pll_enabled(dev_priv, pipe);
2150 else {
2151 if (crtc->config->has_pch_encoder) {
2152 /* if driving the PCH, we need FDI enabled */
2153 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2154 assert_fdi_tx_pll_enabled(dev_priv,
2155 (enum pipe) cpu_transcoder);
2156 }
2157 /* FIXME: assert CPU port conditions for SNB+ */
2158 }
2159
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if (val & PIPECONF_ENABLE) {
2163 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2164 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2165 return;
2166 }
2167
2168 I915_WRITE(reg, val | PIPECONF_ENABLE);
2169 POSTING_READ(reg);
2170 }
2171
2172 /**
2173 * intel_disable_pipe - disable a pipe, asserting requirements
2174 * @crtc: crtc whose pipes is to be disabled
2175 *
2176 * Disable the pipe of @crtc, making sure that various hardware
2177 * specific requirements are met, if applicable, e.g. plane
2178 * disabled, panel fitter off, etc.
2179 *
2180 * Will wait until the pipe has shut down before returning.
2181 */
2182 static void intel_disable_pipe(struct intel_crtc *crtc)
2183 {
2184 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2185 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2186 enum pipe pipe = crtc->pipe;
2187 int reg;
2188 u32 val;
2189
2190 /*
2191 * Make sure planes won't keep trying to pump pixels to us,
2192 * or we might hang the display.
2193 */
2194 assert_planes_disabled(dev_priv, pipe);
2195 assert_cursor_disabled(dev_priv, pipe);
2196 assert_sprites_disabled(dev_priv, pipe);
2197
2198 reg = PIPECONF(cpu_transcoder);
2199 val = I915_READ(reg);
2200 if ((val & PIPECONF_ENABLE) == 0)
2201 return;
2202
2203 /*
2204 * Double wide has implications for planes
2205 * so best keep it disabled when not needed.
2206 */
2207 if (crtc->config->double_wide)
2208 val &= ~PIPECONF_DOUBLE_WIDE;
2209
2210 /* Don't disable pipe or pipe PLLs if needed */
2211 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2212 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2213 val &= ~PIPECONF_ENABLE;
2214
2215 I915_WRITE(reg, val);
2216 if ((val & PIPECONF_ENABLE) == 0)
2217 intel_wait_for_pipe_off(crtc);
2218 }
2219
2220 static bool need_vtd_wa(struct drm_device *dev)
2221 {
2222 #ifdef CONFIG_INTEL_IOMMU
2223 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2224 return true;
2225 #endif
2226 return false;
2227 }
2228
2229 unsigned int
2230 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2231 uint64_t fb_format_modifier)
2232 {
2233 unsigned int tile_height;
2234 uint32_t pixel_bytes;
2235
2236 switch (fb_format_modifier) {
2237 case DRM_FORMAT_MOD_NONE:
2238 tile_height = 1;
2239 break;
2240 case I915_FORMAT_MOD_X_TILED:
2241 tile_height = IS_GEN2(dev) ? 16 : 8;
2242 break;
2243 case I915_FORMAT_MOD_Y_TILED:
2244 tile_height = 32;
2245 break;
2246 case I915_FORMAT_MOD_Yf_TILED:
2247 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2248 switch (pixel_bytes) {
2249 default:
2250 case 1:
2251 tile_height = 64;
2252 break;
2253 case 2:
2254 case 4:
2255 tile_height = 32;
2256 break;
2257 case 8:
2258 tile_height = 16;
2259 break;
2260 case 16:
2261 WARN_ONCE(1,
2262 "128-bit pixels are not supported for display!");
2263 tile_height = 16;
2264 break;
2265 }
2266 break;
2267 default:
2268 MISSING_CASE(fb_format_modifier);
2269 tile_height = 1;
2270 break;
2271 }
2272
2273 return tile_height;
2274 }
2275
2276 unsigned int
2277 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2278 uint32_t pixel_format, uint64_t fb_format_modifier)
2279 {
2280 return ALIGN(height, intel_tile_height(dev, pixel_format,
2281 fb_format_modifier));
2282 }
2283
2284 static int
2285 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2286 const struct drm_plane_state *plane_state)
2287 {
2288 struct intel_rotation_info *info = &view->rotation_info;
2289
2290 *view = i915_ggtt_view_normal;
2291
2292 if (!plane_state)
2293 return 0;
2294
2295 if (!intel_rotation_90_or_270(plane_state->rotation))
2296 return 0;
2297
2298 *view = i915_ggtt_view_rotated;
2299
2300 info->height = fb->height;
2301 info->pixel_format = fb->pixel_format;
2302 info->pitch = fb->pitches[0];
2303 info->fb_modifier = fb->modifier[0];
2304
2305 return 0;
2306 }
2307
2308 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2309 {
2310 if (INTEL_INFO(dev_priv)->gen >= 9)
2311 return 256 * 1024;
2312 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2313 IS_VALLEYVIEW(dev_priv))
2314 return 128 * 1024;
2315 else if (INTEL_INFO(dev_priv)->gen >= 4)
2316 return 4 * 1024;
2317 else
2318 return 0;
2319 }
2320
2321 int
2322 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2323 struct drm_framebuffer *fb,
2324 const struct drm_plane_state *plane_state,
2325 struct intel_engine_cs *pipelined)
2326 {
2327 struct drm_device *dev = fb->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2330 struct i915_ggtt_view view;
2331 u32 alignment;
2332 int ret;
2333
2334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2335
2336 switch (fb->modifier[0]) {
2337 case DRM_FORMAT_MOD_NONE:
2338 alignment = intel_linear_alignment(dev_priv);
2339 break;
2340 case I915_FORMAT_MOD_X_TILED:
2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else {
2344 /* pin() will align the object as required by fence */
2345 alignment = 0;
2346 }
2347 break;
2348 case I915_FORMAT_MOD_Y_TILED:
2349 case I915_FORMAT_MOD_Yf_TILED:
2350 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351 "Y tiling bo slipped through, driver bug!\n"))
2352 return -EINVAL;
2353 alignment = 1 * 1024 * 1024;
2354 break;
2355 default:
2356 MISSING_CASE(fb->modifier[0]);
2357 return -EINVAL;
2358 }
2359
2360 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2361 if (ret)
2362 return ret;
2363
2364 /* Note that the w/a also requires 64 PTE of padding following the
2365 * bo. We currently fill all unused PTE with the shadow page and so
2366 * we should always have valid PTE following the scanout preventing
2367 * the VT-d warning.
2368 */
2369 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370 alignment = 256 * 1024;
2371
2372 /*
2373 * Global gtt pte registers are special registers which actually forward
2374 * writes to a chunk of system memory. Which means that there is no risk
2375 * that the register values disappear as soon as we call
2376 * intel_runtime_pm_put(), so it is correct to wrap only the
2377 * pin/unpin/fence and not more.
2378 */
2379 intel_runtime_pm_get(dev_priv);
2380
2381 dev_priv->mm.interruptible = false;
2382 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2383 &view);
2384 if (ret)
2385 goto err_interruptible;
2386
2387 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2388 * fence, whereas 965+ only requires a fence if using
2389 * framebuffer compression. For simplicity, we always install
2390 * a fence as the cost is not that onerous.
2391 */
2392 ret = i915_gem_object_get_fence(obj);
2393 if (ret)
2394 goto err_unpin;
2395
2396 i915_gem_object_pin_fence(obj);
2397
2398 dev_priv->mm.interruptible = true;
2399 intel_runtime_pm_put(dev_priv);
2400 return 0;
2401
2402 err_unpin:
2403 i915_gem_object_unpin_from_display_plane(obj, &view);
2404 err_interruptible:
2405 dev_priv->mm.interruptible = true;
2406 intel_runtime_pm_put(dev_priv);
2407 return ret;
2408 }
2409
2410 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2411 const struct drm_plane_state *plane_state)
2412 {
2413 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2414 struct i915_ggtt_view view;
2415 int ret;
2416
2417 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2418
2419 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2420 WARN_ONCE(ret, "Couldn't get view from plane state!");
2421
2422 i915_gem_object_unpin_fence(obj);
2423 i915_gem_object_unpin_from_display_plane(obj, &view);
2424 }
2425
2426 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2427 * is assumed to be a power-of-two. */
2428 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2429 int *x, int *y,
2430 unsigned int tiling_mode,
2431 unsigned int cpp,
2432 unsigned int pitch)
2433 {
2434 if (tiling_mode != I915_TILING_NONE) {
2435 unsigned int tile_rows, tiles;
2436
2437 tile_rows = *y / 8;
2438 *y %= 8;
2439
2440 tiles = *x / (512/cpp);
2441 *x %= 512/cpp;
2442
2443 return tile_rows * pitch * 8 + tiles * 4096;
2444 } else {
2445 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2446 unsigned int offset;
2447
2448 offset = *y * pitch + *x * cpp;
2449 *y = (offset & alignment) / pitch;
2450 *x = ((offset & alignment) - *y * pitch) / cpp;
2451 return offset & ~alignment;
2452 }
2453 }
2454
2455 static int i9xx_format_to_fourcc(int format)
2456 {
2457 switch (format) {
2458 case DISPPLANE_8BPP:
2459 return DRM_FORMAT_C8;
2460 case DISPPLANE_BGRX555:
2461 return DRM_FORMAT_XRGB1555;
2462 case DISPPLANE_BGRX565:
2463 return DRM_FORMAT_RGB565;
2464 default:
2465 case DISPPLANE_BGRX888:
2466 return DRM_FORMAT_XRGB8888;
2467 case DISPPLANE_RGBX888:
2468 return DRM_FORMAT_XBGR8888;
2469 case DISPPLANE_BGRX101010:
2470 return DRM_FORMAT_XRGB2101010;
2471 case DISPPLANE_RGBX101010:
2472 return DRM_FORMAT_XBGR2101010;
2473 }
2474 }
2475
2476 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2477 {
2478 switch (format) {
2479 case PLANE_CTL_FORMAT_RGB_565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case PLANE_CTL_FORMAT_XRGB_8888:
2483 if (rgb_order) {
2484 if (alpha)
2485 return DRM_FORMAT_ABGR8888;
2486 else
2487 return DRM_FORMAT_XBGR8888;
2488 } else {
2489 if (alpha)
2490 return DRM_FORMAT_ARGB8888;
2491 else
2492 return DRM_FORMAT_XRGB8888;
2493 }
2494 case PLANE_CTL_FORMAT_XRGB_2101010:
2495 if (rgb_order)
2496 return DRM_FORMAT_XBGR2101010;
2497 else
2498 return DRM_FORMAT_XRGB2101010;
2499 }
2500 }
2501
2502 static bool
2503 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2504 struct intel_initial_plane_config *plane_config)
2505 {
2506 struct drm_device *dev = crtc->base.dev;
2507 struct drm_i915_gem_object *obj = NULL;
2508 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2509 struct drm_framebuffer *fb = &plane_config->fb->base;
2510 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2511 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2512 PAGE_SIZE);
2513
2514 size_aligned -= base_aligned;
2515
2516 if (plane_config->size == 0)
2517 return false;
2518
2519 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2520 base_aligned,
2521 base_aligned,
2522 size_aligned);
2523 if (!obj)
2524 return false;
2525
2526 obj->tiling_mode = plane_config->tiling;
2527 if (obj->tiling_mode == I915_TILING_X)
2528 obj->stride = fb->pitches[0];
2529
2530 mode_cmd.pixel_format = fb->pixel_format;
2531 mode_cmd.width = fb->width;
2532 mode_cmd.height = fb->height;
2533 mode_cmd.pitches[0] = fb->pitches[0];
2534 mode_cmd.modifier[0] = fb->modifier[0];
2535 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2536
2537 mutex_lock(&dev->struct_mutex);
2538 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2539 &mode_cmd, obj)) {
2540 DRM_DEBUG_KMS("intel fb init failed\n");
2541 goto out_unref_obj;
2542 }
2543 mutex_unlock(&dev->struct_mutex);
2544
2545 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2546 return true;
2547
2548 out_unref_obj:
2549 drm_gem_object_unreference(&obj->base);
2550 mutex_unlock(&dev->struct_mutex);
2551 return false;
2552 }
2553
2554 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2555 static void
2556 update_state_fb(struct drm_plane *plane)
2557 {
2558 if (plane->fb == plane->state->fb)
2559 return;
2560
2561 if (plane->state->fb)
2562 drm_framebuffer_unreference(plane->state->fb);
2563 plane->state->fb = plane->fb;
2564 if (plane->state->fb)
2565 drm_framebuffer_reference(plane->state->fb);
2566 }
2567
2568 static void
2569 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2570 struct intel_initial_plane_config *plane_config)
2571 {
2572 struct drm_device *dev = intel_crtc->base.dev;
2573 struct drm_i915_private *dev_priv = dev->dev_private;
2574 struct drm_crtc *c;
2575 struct intel_crtc *i;
2576 struct drm_i915_gem_object *obj;
2577 struct drm_plane *primary = intel_crtc->base.primary;
2578 struct drm_framebuffer *fb;
2579
2580 if (!plane_config->fb)
2581 return;
2582
2583 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2584 fb = &plane_config->fb->base;
2585 goto valid_fb;
2586 }
2587
2588 kfree(plane_config->fb);
2589
2590 /*
2591 * Failed to alloc the obj, check to see if we should share
2592 * an fb with another CRTC instead
2593 */
2594 for_each_crtc(dev, c) {
2595 i = to_intel_crtc(c);
2596
2597 if (c == &intel_crtc->base)
2598 continue;
2599
2600 if (!i->active)
2601 continue;
2602
2603 fb = c->primary->fb;
2604 if (!fb)
2605 continue;
2606
2607 obj = intel_fb_obj(fb);
2608 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2609 drm_framebuffer_reference(fb);
2610 goto valid_fb;
2611 }
2612 }
2613
2614 return;
2615
2616 valid_fb:
2617 obj = intel_fb_obj(fb);
2618 if (obj->tiling_mode != I915_TILING_NONE)
2619 dev_priv->preserve_bios_swizzle = true;
2620
2621 primary->fb = fb;
2622 primary->crtc = primary->state->crtc = &intel_crtc->base;
2623 update_state_fb(primary);
2624 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2625 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2626 }
2627
2628 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2629 struct drm_framebuffer *fb,
2630 int x, int y)
2631 {
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 struct drm_plane *primary = crtc->primary;
2636 bool visible = to_intel_plane_state(primary->state)->visible;
2637 struct drm_i915_gem_object *obj;
2638 int plane = intel_crtc->plane;
2639 unsigned long linear_offset;
2640 u32 dspcntr;
2641 u32 reg = DSPCNTR(plane);
2642 int pixel_size;
2643
2644 if (!visible || !fb) {
2645 I915_WRITE(reg, 0);
2646 if (INTEL_INFO(dev)->gen >= 4)
2647 I915_WRITE(DSPSURF(plane), 0);
2648 else
2649 I915_WRITE(DSPADDR(plane), 0);
2650 POSTING_READ(reg);
2651 return;
2652 }
2653
2654 obj = intel_fb_obj(fb);
2655 if (WARN_ON(obj == NULL))
2656 return;
2657
2658 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2659
2660 dspcntr = DISPPLANE_GAMMA_ENABLE;
2661
2662 dspcntr |= DISPLAY_PLANE_ENABLE;
2663
2664 if (INTEL_INFO(dev)->gen < 4) {
2665 if (intel_crtc->pipe == PIPE_B)
2666 dspcntr |= DISPPLANE_SEL_PIPE_B;
2667
2668 /* pipesrc and dspsize control the size that is scaled from,
2669 * which should always be the user's requested size.
2670 */
2671 I915_WRITE(DSPSIZE(plane),
2672 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2673 (intel_crtc->config->pipe_src_w - 1));
2674 I915_WRITE(DSPPOS(plane), 0);
2675 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2676 I915_WRITE(PRIMSIZE(plane),
2677 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2678 (intel_crtc->config->pipe_src_w - 1));
2679 I915_WRITE(PRIMPOS(plane), 0);
2680 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2681 }
2682
2683 switch (fb->pixel_format) {
2684 case DRM_FORMAT_C8:
2685 dspcntr |= DISPPLANE_8BPP;
2686 break;
2687 case DRM_FORMAT_XRGB1555:
2688 dspcntr |= DISPPLANE_BGRX555;
2689 break;
2690 case DRM_FORMAT_RGB565:
2691 dspcntr |= DISPPLANE_BGRX565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 dspcntr |= DISPPLANE_BGRX888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 dspcntr |= DISPPLANE_RGBX888;
2698 break;
2699 case DRM_FORMAT_XRGB2101010:
2700 dspcntr |= DISPPLANE_BGRX101010;
2701 break;
2702 case DRM_FORMAT_XBGR2101010:
2703 dspcntr |= DISPPLANE_RGBX101010;
2704 break;
2705 default:
2706 BUG();
2707 }
2708
2709 if (INTEL_INFO(dev)->gen >= 4 &&
2710 obj->tiling_mode != I915_TILING_NONE)
2711 dspcntr |= DISPPLANE_TILED;
2712
2713 if (IS_G4X(dev))
2714 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2715
2716 linear_offset = y * fb->pitches[0] + x * pixel_size;
2717
2718 if (INTEL_INFO(dev)->gen >= 4) {
2719 intel_crtc->dspaddr_offset =
2720 intel_gen4_compute_page_offset(dev_priv,
2721 &x, &y, obj->tiling_mode,
2722 pixel_size,
2723 fb->pitches[0]);
2724 linear_offset -= intel_crtc->dspaddr_offset;
2725 } else {
2726 intel_crtc->dspaddr_offset = linear_offset;
2727 }
2728
2729 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2730 dspcntr |= DISPPLANE_ROTATE_180;
2731
2732 x += (intel_crtc->config->pipe_src_w - 1);
2733 y += (intel_crtc->config->pipe_src_h - 1);
2734
2735 /* Finding the last pixel of the last line of the display
2736 data and adding to linear_offset*/
2737 linear_offset +=
2738 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2739 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2740 }
2741
2742 I915_WRITE(reg, dspcntr);
2743
2744 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 I915_WRITE(DSPSURF(plane),
2747 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2748 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2749 I915_WRITE(DSPLINOFF(plane), linear_offset);
2750 } else
2751 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 POSTING_READ(reg);
2753 }
2754
2755 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2756 struct drm_framebuffer *fb,
2757 int x, int y)
2758 {
2759 struct drm_device *dev = crtc->dev;
2760 struct drm_i915_private *dev_priv = dev->dev_private;
2761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2762 struct drm_plane *primary = crtc->primary;
2763 bool visible = to_intel_plane_state(primary->state)->visible;
2764 struct drm_i915_gem_object *obj;
2765 int plane = intel_crtc->plane;
2766 unsigned long linear_offset;
2767 u32 dspcntr;
2768 u32 reg = DSPCNTR(plane);
2769 int pixel_size;
2770
2771 if (!visible || !fb) {
2772 I915_WRITE(reg, 0);
2773 I915_WRITE(DSPSURF(plane), 0);
2774 POSTING_READ(reg);
2775 return;
2776 }
2777
2778 obj = intel_fb_obj(fb);
2779 if (WARN_ON(obj == NULL))
2780 return;
2781
2782 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2783
2784 dspcntr = DISPPLANE_GAMMA_ENABLE;
2785
2786 dspcntr |= DISPLAY_PLANE_ENABLE;
2787
2788 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2789 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2790
2791 switch (fb->pixel_format) {
2792 case DRM_FORMAT_C8:
2793 dspcntr |= DISPPLANE_8BPP;
2794 break;
2795 case DRM_FORMAT_RGB565:
2796 dspcntr |= DISPPLANE_BGRX565;
2797 break;
2798 case DRM_FORMAT_XRGB8888:
2799 dspcntr |= DISPPLANE_BGRX888;
2800 break;
2801 case DRM_FORMAT_XBGR8888:
2802 dspcntr |= DISPPLANE_RGBX888;
2803 break;
2804 case DRM_FORMAT_XRGB2101010:
2805 dspcntr |= DISPPLANE_BGRX101010;
2806 break;
2807 case DRM_FORMAT_XBGR2101010:
2808 dspcntr |= DISPPLANE_RGBX101010;
2809 break;
2810 default:
2811 BUG();
2812 }
2813
2814 if (obj->tiling_mode != I915_TILING_NONE)
2815 dspcntr |= DISPPLANE_TILED;
2816
2817 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2818 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2819
2820 linear_offset = y * fb->pitches[0] + x * pixel_size;
2821 intel_crtc->dspaddr_offset =
2822 intel_gen4_compute_page_offset(dev_priv,
2823 &x, &y, obj->tiling_mode,
2824 pixel_size,
2825 fb->pitches[0]);
2826 linear_offset -= intel_crtc->dspaddr_offset;
2827 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2828 dspcntr |= DISPPLANE_ROTATE_180;
2829
2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2831 x += (intel_crtc->config->pipe_src_w - 1);
2832 y += (intel_crtc->config->pipe_src_h - 1);
2833
2834 /* Finding the last pixel of the last line of the display
2835 data and adding to linear_offset*/
2836 linear_offset +=
2837 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2838 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2839 }
2840 }
2841
2842 I915_WRITE(reg, dspcntr);
2843
2844 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2845 I915_WRITE(DSPSURF(plane),
2846 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2847 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2848 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2849 } else {
2850 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2851 I915_WRITE(DSPLINOFF(plane), linear_offset);
2852 }
2853 POSTING_READ(reg);
2854 }
2855
2856 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2857 uint32_t pixel_format)
2858 {
2859 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2860
2861 /*
2862 * The stride is either expressed as a multiple of 64 bytes
2863 * chunks for linear buffers or in number of tiles for tiled
2864 * buffers.
2865 */
2866 switch (fb_modifier) {
2867 case DRM_FORMAT_MOD_NONE:
2868 return 64;
2869 case I915_FORMAT_MOD_X_TILED:
2870 if (INTEL_INFO(dev)->gen == 2)
2871 return 128;
2872 return 512;
2873 case I915_FORMAT_MOD_Y_TILED:
2874 /* No need to check for old gens and Y tiling since this is
2875 * about the display engine and those will be blocked before
2876 * we get here.
2877 */
2878 return 128;
2879 case I915_FORMAT_MOD_Yf_TILED:
2880 if (bits_per_pixel == 8)
2881 return 64;
2882 else
2883 return 128;
2884 default:
2885 MISSING_CASE(fb_modifier);
2886 return 64;
2887 }
2888 }
2889
2890 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2891 struct drm_i915_gem_object *obj)
2892 {
2893 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2894
2895 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2896 view = &i915_ggtt_view_rotated;
2897
2898 return i915_gem_obj_ggtt_offset_view(obj, view);
2899 }
2900
2901 /*
2902 * This function detaches (aka. unbinds) unused scalers in hardware
2903 */
2904 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2905 {
2906 struct drm_device *dev;
2907 struct drm_i915_private *dev_priv;
2908 struct intel_crtc_scaler_state *scaler_state;
2909 int i;
2910
2911 dev = intel_crtc->base.dev;
2912 dev_priv = dev->dev_private;
2913 scaler_state = &intel_crtc->config->scaler_state;
2914
2915 /* loop through and disable scalers that aren't in use */
2916 for (i = 0; i < intel_crtc->num_scalers; i++) {
2917 if (!scaler_state->scalers[i].in_use) {
2918 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2919 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2920 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2921 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2922 intel_crtc->base.base.id, intel_crtc->pipe, i);
2923 }
2924 }
2925 }
2926
2927 u32 skl_plane_ctl_format(uint32_t pixel_format)
2928 {
2929 switch (pixel_format) {
2930 case DRM_FORMAT_C8:
2931 return PLANE_CTL_FORMAT_INDEXED;
2932 case DRM_FORMAT_RGB565:
2933 return PLANE_CTL_FORMAT_RGB_565;
2934 case DRM_FORMAT_XBGR8888:
2935 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2936 case DRM_FORMAT_XRGB8888:
2937 return PLANE_CTL_FORMAT_XRGB_8888;
2938 /*
2939 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2940 * to be already pre-multiplied. We need to add a knob (or a different
2941 * DRM_FORMAT) for user-space to configure that.
2942 */
2943 case DRM_FORMAT_ABGR8888:
2944 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2945 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946 case DRM_FORMAT_ARGB8888:
2947 return PLANE_CTL_FORMAT_XRGB_8888 |
2948 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2949 case DRM_FORMAT_XRGB2101010:
2950 return PLANE_CTL_FORMAT_XRGB_2101010;
2951 case DRM_FORMAT_XBGR2101010:
2952 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2953 case DRM_FORMAT_YUYV:
2954 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2955 case DRM_FORMAT_YVYU:
2956 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2957 case DRM_FORMAT_UYVY:
2958 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2959 case DRM_FORMAT_VYUY:
2960 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2961 default:
2962 MISSING_CASE(pixel_format);
2963 }
2964
2965 return 0;
2966 }
2967
2968 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2969 {
2970 switch (fb_modifier) {
2971 case DRM_FORMAT_MOD_NONE:
2972 break;
2973 case I915_FORMAT_MOD_X_TILED:
2974 return PLANE_CTL_TILED_X;
2975 case I915_FORMAT_MOD_Y_TILED:
2976 return PLANE_CTL_TILED_Y;
2977 case I915_FORMAT_MOD_Yf_TILED:
2978 return PLANE_CTL_TILED_YF;
2979 default:
2980 MISSING_CASE(fb_modifier);
2981 }
2982
2983 return 0;
2984 }
2985
2986 u32 skl_plane_ctl_rotation(unsigned int rotation)
2987 {
2988 switch (rotation) {
2989 case BIT(DRM_ROTATE_0):
2990 break;
2991 /*
2992 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2993 * while i915 HW rotation is clockwise, thats why this swapping.
2994 */
2995 case BIT(DRM_ROTATE_90):
2996 return PLANE_CTL_ROTATE_270;
2997 case BIT(DRM_ROTATE_180):
2998 return PLANE_CTL_ROTATE_180;
2999 case BIT(DRM_ROTATE_270):
3000 return PLANE_CTL_ROTATE_90;
3001 default:
3002 MISSING_CASE(rotation);
3003 }
3004
3005 return 0;
3006 }
3007
3008 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3009 struct drm_framebuffer *fb,
3010 int x, int y)
3011 {
3012 struct drm_device *dev = crtc->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 struct drm_plane *plane = crtc->primary;
3016 bool visible = to_intel_plane_state(plane->state)->visible;
3017 struct drm_i915_gem_object *obj;
3018 int pipe = intel_crtc->pipe;
3019 u32 plane_ctl, stride_div, stride;
3020 u32 tile_height, plane_offset, plane_size;
3021 unsigned int rotation;
3022 int x_offset, y_offset;
3023 unsigned long surf_addr;
3024 struct intel_crtc_state *crtc_state = intel_crtc->config;
3025 struct intel_plane_state *plane_state;
3026 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3027 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3028 int scaler_id = -1;
3029
3030 plane_state = to_intel_plane_state(plane->state);
3031
3032 if (!visible || !fb) {
3033 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3034 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3035 POSTING_READ(PLANE_CTL(pipe, 0));
3036 return;
3037 }
3038
3039 plane_ctl = PLANE_CTL_ENABLE |
3040 PLANE_CTL_PIPE_GAMMA_ENABLE |
3041 PLANE_CTL_PIPE_CSC_ENABLE;
3042
3043 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3044 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3045 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3046
3047 rotation = plane->state->rotation;
3048 plane_ctl |= skl_plane_ctl_rotation(rotation);
3049
3050 obj = intel_fb_obj(fb);
3051 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3052 fb->pixel_format);
3053 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3054
3055 /*
3056 * FIXME: intel_plane_state->src, dst aren't set when transitional
3057 * update_plane helpers are called from legacy paths.
3058 * Once full atomic crtc is available, below check can be avoided.
3059 */
3060 if (drm_rect_width(&plane_state->src)) {
3061 scaler_id = plane_state->scaler_id;
3062 src_x = plane_state->src.x1 >> 16;
3063 src_y = plane_state->src.y1 >> 16;
3064 src_w = drm_rect_width(&plane_state->src) >> 16;
3065 src_h = drm_rect_height(&plane_state->src) >> 16;
3066 dst_x = plane_state->dst.x1;
3067 dst_y = plane_state->dst.y1;
3068 dst_w = drm_rect_width(&plane_state->dst);
3069 dst_h = drm_rect_height(&plane_state->dst);
3070
3071 WARN_ON(x != src_x || y != src_y);
3072 } else {
3073 src_w = intel_crtc->config->pipe_src_w;
3074 src_h = intel_crtc->config->pipe_src_h;
3075 }
3076
3077 if (intel_rotation_90_or_270(rotation)) {
3078 /* stride = Surface height in tiles */
3079 tile_height = intel_tile_height(dev, fb->pixel_format,
3080 fb->modifier[0]);
3081 stride = DIV_ROUND_UP(fb->height, tile_height);
3082 x_offset = stride * tile_height - y - src_h;
3083 y_offset = x;
3084 plane_size = (src_w - 1) << 16 | (src_h - 1);
3085 } else {
3086 stride = fb->pitches[0] / stride_div;
3087 x_offset = x;
3088 y_offset = y;
3089 plane_size = (src_h - 1) << 16 | (src_w - 1);
3090 }
3091 plane_offset = y_offset << 16 | x_offset;
3092
3093 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3094 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3095 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3096 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3097
3098 if (scaler_id >= 0) {
3099 uint32_t ps_ctrl = 0;
3100
3101 WARN_ON(!dst_w || !dst_h);
3102 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3103 crtc_state->scaler_state.scalers[scaler_id].mode;
3104 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3105 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3106 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3107 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3108 I915_WRITE(PLANE_POS(pipe, 0), 0);
3109 } else {
3110 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3111 }
3112
3113 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3114
3115 POSTING_READ(PLANE_SURF(pipe, 0));
3116 }
3117
3118 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3119 static int
3120 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3121 int x, int y, enum mode_set_atomic state)
3122 {
3123 struct drm_device *dev = crtc->dev;
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125
3126 if (dev_priv->display.disable_fbc)
3127 dev_priv->display.disable_fbc(dev);
3128
3129 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3130
3131 return 0;
3132 }
3133
3134 static void intel_complete_page_flips(struct drm_device *dev)
3135 {
3136 struct drm_crtc *crtc;
3137
3138 for_each_crtc(dev, crtc) {
3139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3140 enum plane plane = intel_crtc->plane;
3141
3142 intel_prepare_page_flip(dev, plane);
3143 intel_finish_page_flip_plane(dev, plane);
3144 }
3145 }
3146
3147 static void intel_update_primary_planes(struct drm_device *dev)
3148 {
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 struct drm_crtc *crtc;
3151
3152 for_each_crtc(dev, crtc) {
3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154
3155 drm_modeset_lock(&crtc->mutex, NULL);
3156 /*
3157 * FIXME: Once we have proper support for primary planes (and
3158 * disabling them without disabling the entire crtc) allow again
3159 * a NULL crtc->primary->fb.
3160 */
3161 if (intel_crtc->active && crtc->primary->fb)
3162 dev_priv->display.update_primary_plane(crtc,
3163 crtc->primary->fb,
3164 crtc->x,
3165 crtc->y);
3166 drm_modeset_unlock(&crtc->mutex);
3167 }
3168 }
3169
3170 void intel_prepare_reset(struct drm_device *dev)
3171 {
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev))
3174 return;
3175
3176 /* reset doesn't touch the display */
3177 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3178 return;
3179
3180 drm_modeset_lock_all(dev);
3181 /*
3182 * Disabling the crtcs gracefully seems nicer. Also the
3183 * g33 docs say we should at least disable all the planes.
3184 */
3185 intel_display_suspend(dev);
3186 }
3187
3188 void intel_finish_reset(struct drm_device *dev)
3189 {
3190 struct drm_i915_private *dev_priv = to_i915(dev);
3191
3192 /*
3193 * Flips in the rings will be nuked by the reset,
3194 * so complete all pending flips so that user space
3195 * will get its events and not get stuck.
3196 */
3197 intel_complete_page_flips(dev);
3198
3199 /* no reset support for gen2 */
3200 if (IS_GEN2(dev))
3201 return;
3202
3203 /* reset doesn't touch the display */
3204 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3205 /*
3206 * Flips in the rings have been nuked by the reset,
3207 * so update the base address of all primary
3208 * planes to the the last fb to make sure we're
3209 * showing the correct fb after a reset.
3210 */
3211 intel_update_primary_planes(dev);
3212 return;
3213 }
3214
3215 /*
3216 * The display has been reset as well,
3217 * so need a full re-initialization.
3218 */
3219 intel_runtime_pm_disable_interrupts(dev_priv);
3220 intel_runtime_pm_enable_interrupts(dev_priv);
3221
3222 intel_modeset_init_hw(dev);
3223
3224 spin_lock_irq(&dev_priv->irq_lock);
3225 if (dev_priv->display.hpd_irq_setup)
3226 dev_priv->display.hpd_irq_setup(dev);
3227 spin_unlock_irq(&dev_priv->irq_lock);
3228
3229 intel_modeset_setup_hw_state(dev, true);
3230
3231 intel_hpd_init(dev_priv);
3232
3233 drm_modeset_unlock_all(dev);
3234 }
3235
3236 static void
3237 intel_finish_fb(struct drm_framebuffer *old_fb)
3238 {
3239 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3240 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3241 bool was_interruptible = dev_priv->mm.interruptible;
3242 int ret;
3243
3244 /* Big Hammer, we also need to ensure that any pending
3245 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3246 * current scanout is retired before unpinning the old
3247 * framebuffer. Note that we rely on userspace rendering
3248 * into the buffer attached to the pipe they are waiting
3249 * on. If not, userspace generates a GPU hang with IPEHR
3250 * point to the MI_WAIT_FOR_EVENT.
3251 *
3252 * This should only fail upon a hung GPU, in which case we
3253 * can safely continue.
3254 */
3255 dev_priv->mm.interruptible = false;
3256 ret = i915_gem_object_wait_rendering(obj, true);
3257 dev_priv->mm.interruptible = was_interruptible;
3258
3259 WARN_ON(ret);
3260 }
3261
3262 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3263 {
3264 struct drm_device *dev = crtc->dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267 bool pending;
3268
3269 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3270 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3271 return false;
3272
3273 spin_lock_irq(&dev->event_lock);
3274 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3275 spin_unlock_irq(&dev->event_lock);
3276
3277 return pending;
3278 }
3279
3280 static void intel_update_pipe_size(struct intel_crtc *crtc)
3281 {
3282 struct drm_device *dev = crtc->base.dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 const struct drm_display_mode *adjusted_mode;
3285
3286 if (!i915.fastboot)
3287 return;
3288
3289 /*
3290 * Update pipe size and adjust fitter if needed: the reason for this is
3291 * that in compute_mode_changes we check the native mode (not the pfit
3292 * mode) to see if we can flip rather than do a full mode set. In the
3293 * fastboot case, we'll flip, but if we don't update the pipesrc and
3294 * pfit state, we'll end up with a big fb scanned out into the wrong
3295 * sized surface.
3296 *
3297 * To fix this properly, we need to hoist the checks up into
3298 * compute_mode_changes (or above), check the actual pfit state and
3299 * whether the platform allows pfit disable with pipe active, and only
3300 * then update the pipesrc and pfit state, even on the flip path.
3301 */
3302
3303 adjusted_mode = &crtc->config->base.adjusted_mode;
3304
3305 I915_WRITE(PIPESRC(crtc->pipe),
3306 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3307 (adjusted_mode->crtc_vdisplay - 1));
3308 if (!crtc->config->pch_pfit.enabled &&
3309 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3311 I915_WRITE(PF_CTL(crtc->pipe), 0);
3312 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3313 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3314 }
3315 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3316 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3317 }
3318
3319 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3320 {
3321 struct drm_device *dev = crtc->dev;
3322 struct drm_i915_private *dev_priv = dev->dev_private;
3323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324 int pipe = intel_crtc->pipe;
3325 u32 reg, temp;
3326
3327 /* enable normal train */
3328 reg = FDI_TX_CTL(pipe);
3329 temp = I915_READ(reg);
3330 if (IS_IVYBRIDGE(dev)) {
3331 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3332 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3333 } else {
3334 temp &= ~FDI_LINK_TRAIN_NONE;
3335 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3336 }
3337 I915_WRITE(reg, temp);
3338
3339 reg = FDI_RX_CTL(pipe);
3340 temp = I915_READ(reg);
3341 if (HAS_PCH_CPT(dev)) {
3342 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3343 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3344 } else {
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_NONE;
3347 }
3348 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3349
3350 /* wait one idle pattern time */
3351 POSTING_READ(reg);
3352 udelay(1000);
3353
3354 /* IVB wants error correction enabled */
3355 if (IS_IVYBRIDGE(dev))
3356 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3357 FDI_FE_ERRC_ENABLE);
3358 }
3359
3360 /* The FDI link training functions for ILK/Ibexpeak. */
3361 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3362 {
3363 struct drm_device *dev = crtc->dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 int pipe = intel_crtc->pipe;
3367 u32 reg, temp, tries;
3368
3369 /* FDI needs bits from pipe first */
3370 assert_pipe_enabled(dev_priv, pipe);
3371
3372 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3373 for train result */
3374 reg = FDI_RX_IMR(pipe);
3375 temp = I915_READ(reg);
3376 temp &= ~FDI_RX_SYMBOL_LOCK;
3377 temp &= ~FDI_RX_BIT_LOCK;
3378 I915_WRITE(reg, temp);
3379 I915_READ(reg);
3380 udelay(150);
3381
3382 /* enable CPU FDI TX and PCH FDI RX */
3383 reg = FDI_TX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3386 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3387 temp &= ~FDI_LINK_TRAIN_NONE;
3388 temp |= FDI_LINK_TRAIN_PATTERN_1;
3389 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3390
3391 reg = FDI_RX_CTL(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~FDI_LINK_TRAIN_NONE;
3394 temp |= FDI_LINK_TRAIN_PATTERN_1;
3395 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3396
3397 POSTING_READ(reg);
3398 udelay(150);
3399
3400 /* Ironlake workaround, enable clock pointer after FDI enable*/
3401 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3402 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3403 FDI_RX_PHASE_SYNC_POINTER_EN);
3404
3405 reg = FDI_RX_IIR(pipe);
3406 for (tries = 0; tries < 5; tries++) {
3407 temp = I915_READ(reg);
3408 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3409
3410 if ((temp & FDI_RX_BIT_LOCK)) {
3411 DRM_DEBUG_KMS("FDI train 1 done.\n");
3412 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3413 break;
3414 }
3415 }
3416 if (tries == 5)
3417 DRM_ERROR("FDI train 1 fail!\n");
3418
3419 /* Train 2 */
3420 reg = FDI_TX_CTL(pipe);
3421 temp = I915_READ(reg);
3422 temp &= ~FDI_LINK_TRAIN_NONE;
3423 temp |= FDI_LINK_TRAIN_PATTERN_2;
3424 I915_WRITE(reg, temp);
3425
3426 reg = FDI_RX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_LINK_TRAIN_NONE;
3429 temp |= FDI_LINK_TRAIN_PATTERN_2;
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
3435 reg = FDI_RX_IIR(pipe);
3436 for (tries = 0; tries < 5; tries++) {
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440 if (temp & FDI_RX_SYMBOL_LOCK) {
3441 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3442 DRM_DEBUG_KMS("FDI train 2 done.\n");
3443 break;
3444 }
3445 }
3446 if (tries == 5)
3447 DRM_ERROR("FDI train 2 fail!\n");
3448
3449 DRM_DEBUG_KMS("FDI train done\n");
3450
3451 }
3452
3453 static const int snb_b_fdi_train_param[] = {
3454 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3455 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3456 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3457 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3458 };
3459
3460 /* The FDI link training functions for SNB/Cougarpoint. */
3461 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3462 {
3463 struct drm_device *dev = crtc->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3466 int pipe = intel_crtc->pipe;
3467 u32 reg, temp, i, retry;
3468
3469 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3470 for train result */
3471 reg = FDI_RX_IMR(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~FDI_RX_SYMBOL_LOCK;
3474 temp &= ~FDI_RX_BIT_LOCK;
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(150);
3479
3480 /* enable CPU FDI TX and PCH FDI RX */
3481 reg = FDI_TX_CTL(pipe);
3482 temp = I915_READ(reg);
3483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3485 temp &= ~FDI_LINK_TRAIN_NONE;
3486 temp |= FDI_LINK_TRAIN_PATTERN_1;
3487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3488 /* SNB-B */
3489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3490 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3491
3492 I915_WRITE(FDI_RX_MISC(pipe),
3493 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3494
3495 reg = FDI_RX_CTL(pipe);
3496 temp = I915_READ(reg);
3497 if (HAS_PCH_CPT(dev)) {
3498 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3500 } else {
3501 temp &= ~FDI_LINK_TRAIN_NONE;
3502 temp |= FDI_LINK_TRAIN_PATTERN_1;
3503 }
3504 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3505
3506 POSTING_READ(reg);
3507 udelay(150);
3508
3509 for (i = 0; i < 4; i++) {
3510 reg = FDI_TX_CTL(pipe);
3511 temp = I915_READ(reg);
3512 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3513 temp |= snb_b_fdi_train_param[i];
3514 I915_WRITE(reg, temp);
3515
3516 POSTING_READ(reg);
3517 udelay(500);
3518
3519 for (retry = 0; retry < 5; retry++) {
3520 reg = FDI_RX_IIR(pipe);
3521 temp = I915_READ(reg);
3522 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3523 if (temp & FDI_RX_BIT_LOCK) {
3524 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3525 DRM_DEBUG_KMS("FDI train 1 done.\n");
3526 break;
3527 }
3528 udelay(50);
3529 }
3530 if (retry < 5)
3531 break;
3532 }
3533 if (i == 4)
3534 DRM_ERROR("FDI train 1 fail!\n");
3535
3536 /* Train 2 */
3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
3539 temp &= ~FDI_LINK_TRAIN_NONE;
3540 temp |= FDI_LINK_TRAIN_PATTERN_2;
3541 if (IS_GEN6(dev)) {
3542 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3543 /* SNB-B */
3544 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3545 }
3546 I915_WRITE(reg, temp);
3547
3548 reg = FDI_RX_CTL(pipe);
3549 temp = I915_READ(reg);
3550 if (HAS_PCH_CPT(dev)) {
3551 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3552 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3553 } else {
3554 temp &= ~FDI_LINK_TRAIN_NONE;
3555 temp |= FDI_LINK_TRAIN_PATTERN_2;
3556 }
3557 I915_WRITE(reg, temp);
3558
3559 POSTING_READ(reg);
3560 udelay(150);
3561
3562 for (i = 0; i < 4; i++) {
3563 reg = FDI_TX_CTL(pipe);
3564 temp = I915_READ(reg);
3565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3566 temp |= snb_b_fdi_train_param[i];
3567 I915_WRITE(reg, temp);
3568
3569 POSTING_READ(reg);
3570 udelay(500);
3571
3572 for (retry = 0; retry < 5; retry++) {
3573 reg = FDI_RX_IIR(pipe);
3574 temp = I915_READ(reg);
3575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3576 if (temp & FDI_RX_SYMBOL_LOCK) {
3577 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3578 DRM_DEBUG_KMS("FDI train 2 done.\n");
3579 break;
3580 }
3581 udelay(50);
3582 }
3583 if (retry < 5)
3584 break;
3585 }
3586 if (i == 4)
3587 DRM_ERROR("FDI train 2 fail!\n");
3588
3589 DRM_DEBUG_KMS("FDI train done.\n");
3590 }
3591
3592 /* Manual link training for Ivy Bridge A0 parts */
3593 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3594 {
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 int pipe = intel_crtc->pipe;
3599 u32 reg, temp, i, j;
3600
3601 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3602 for train result */
3603 reg = FDI_RX_IMR(pipe);
3604 temp = I915_READ(reg);
3605 temp &= ~FDI_RX_SYMBOL_LOCK;
3606 temp &= ~FDI_RX_BIT_LOCK;
3607 I915_WRITE(reg, temp);
3608
3609 POSTING_READ(reg);
3610 udelay(150);
3611
3612 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3613 I915_READ(FDI_RX_IIR(pipe)));
3614
3615 /* Try each vswing and preemphasis setting twice before moving on */
3616 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3617 /* disable first in case we need to retry */
3618 reg = FDI_TX_CTL(pipe);
3619 temp = I915_READ(reg);
3620 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3621 temp &= ~FDI_TX_ENABLE;
3622 I915_WRITE(reg, temp);
3623
3624 reg = FDI_RX_CTL(pipe);
3625 temp = I915_READ(reg);
3626 temp &= ~FDI_LINK_TRAIN_AUTO;
3627 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3628 temp &= ~FDI_RX_ENABLE;
3629 I915_WRITE(reg, temp);
3630
3631 /* enable CPU FDI TX and PCH FDI RX */
3632 reg = FDI_TX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3635 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3636 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3638 temp |= snb_b_fdi_train_param[j/2];
3639 temp |= FDI_COMPOSITE_SYNC;
3640 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3641
3642 I915_WRITE(FDI_RX_MISC(pipe),
3643 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3644
3645 reg = FDI_RX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3648 temp |= FDI_COMPOSITE_SYNC;
3649 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3650
3651 POSTING_READ(reg);
3652 udelay(1); /* should be 0.5us */
3653
3654 for (i = 0; i < 4; i++) {
3655 reg = FDI_RX_IIR(pipe);
3656 temp = I915_READ(reg);
3657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3658
3659 if (temp & FDI_RX_BIT_LOCK ||
3660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3662 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3663 i);
3664 break;
3665 }
3666 udelay(1); /* should be 0.5us */
3667 }
3668 if (i == 4) {
3669 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3670 continue;
3671 }
3672
3673 /* Train 2 */
3674 reg = FDI_TX_CTL(pipe);
3675 temp = I915_READ(reg);
3676 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3677 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3678 I915_WRITE(reg, temp);
3679
3680 reg = FDI_RX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3683 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3684 I915_WRITE(reg, temp);
3685
3686 POSTING_READ(reg);
3687 udelay(2); /* should be 1.5us */
3688
3689 for (i = 0; i < 4; i++) {
3690 reg = FDI_RX_IIR(pipe);
3691 temp = I915_READ(reg);
3692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3693
3694 if (temp & FDI_RX_SYMBOL_LOCK ||
3695 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3696 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3697 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3698 i);
3699 goto train_done;
3700 }
3701 udelay(2); /* should be 1.5us */
3702 }
3703 if (i == 4)
3704 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3705 }
3706
3707 train_done:
3708 DRM_DEBUG_KMS("FDI train done.\n");
3709 }
3710
3711 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3712 {
3713 struct drm_device *dev = intel_crtc->base.dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 int pipe = intel_crtc->pipe;
3716 u32 reg, temp;
3717
3718
3719 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3720 reg = FDI_RX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3723 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3724 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3725 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3726
3727 POSTING_READ(reg);
3728 udelay(200);
3729
3730 /* Switch from Rawclk to PCDclk */
3731 temp = I915_READ(reg);
3732 I915_WRITE(reg, temp | FDI_PCDCLK);
3733
3734 POSTING_READ(reg);
3735 udelay(200);
3736
3737 /* Enable CPU FDI TX PLL, always on for Ironlake */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3741 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3742
3743 POSTING_READ(reg);
3744 udelay(100);
3745 }
3746 }
3747
3748 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3749 {
3750 struct drm_device *dev = intel_crtc->base.dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 int pipe = intel_crtc->pipe;
3753 u32 reg, temp;
3754
3755 /* Switch from PCDclk to Rawclk */
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3759
3760 /* Disable CPU FDI TX PLL */
3761 reg = FDI_TX_CTL(pipe);
3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3764
3765 POSTING_READ(reg);
3766 udelay(100);
3767
3768 reg = FDI_RX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3771
3772 /* Wait for the clocks to turn off. */
3773 POSTING_READ(reg);
3774 udelay(100);
3775 }
3776
3777 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3778 {
3779 struct drm_device *dev = crtc->dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782 int pipe = intel_crtc->pipe;
3783 u32 reg, temp;
3784
3785 /* disable CPU FDI tx and PCH FDI rx */
3786 reg = FDI_TX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3789 POSTING_READ(reg);
3790
3791 reg = FDI_RX_CTL(pipe);
3792 temp = I915_READ(reg);
3793 temp &= ~(0x7 << 16);
3794 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3795 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3796
3797 POSTING_READ(reg);
3798 udelay(100);
3799
3800 /* Ironlake workaround, disable clock pointer after downing FDI */
3801 if (HAS_PCH_IBX(dev))
3802 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3803
3804 /* still set train pattern 1 */
3805 reg = FDI_TX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 temp &= ~FDI_LINK_TRAIN_NONE;
3808 temp |= FDI_LINK_TRAIN_PATTERN_1;
3809 I915_WRITE(reg, temp);
3810
3811 reg = FDI_RX_CTL(pipe);
3812 temp = I915_READ(reg);
3813 if (HAS_PCH_CPT(dev)) {
3814 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3815 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3816 } else {
3817 temp &= ~FDI_LINK_TRAIN_NONE;
3818 temp |= FDI_LINK_TRAIN_PATTERN_1;
3819 }
3820 /* BPC in FDI rx is consistent with that in PIPECONF */
3821 temp &= ~(0x07 << 16);
3822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3823 I915_WRITE(reg, temp);
3824
3825 POSTING_READ(reg);
3826 udelay(100);
3827 }
3828
3829 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3830 {
3831 struct intel_crtc *crtc;
3832
3833 /* Note that we don't need to be called with mode_config.lock here
3834 * as our list of CRTC objects is static for the lifetime of the
3835 * device and so cannot disappear as we iterate. Similarly, we can
3836 * happily treat the predicates as racy, atomic checks as userspace
3837 * cannot claim and pin a new fb without at least acquring the
3838 * struct_mutex and so serialising with us.
3839 */
3840 for_each_intel_crtc(dev, crtc) {
3841 if (atomic_read(&crtc->unpin_work_count) == 0)
3842 continue;
3843
3844 if (crtc->unpin_work)
3845 intel_wait_for_vblank(dev, crtc->pipe);
3846
3847 return true;
3848 }
3849
3850 return false;
3851 }
3852
3853 static void page_flip_completed(struct intel_crtc *intel_crtc)
3854 {
3855 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3856 struct intel_unpin_work *work = intel_crtc->unpin_work;
3857
3858 /* ensure that the unpin work is consistent wrt ->pending. */
3859 smp_rmb();
3860 intel_crtc->unpin_work = NULL;
3861
3862 if (work->event)
3863 drm_send_vblank_event(intel_crtc->base.dev,
3864 intel_crtc->pipe,
3865 work->event);
3866
3867 drm_crtc_vblank_put(&intel_crtc->base);
3868
3869 wake_up_all(&dev_priv->pending_flip_queue);
3870 queue_work(dev_priv->wq, &work->work);
3871
3872 trace_i915_flip_complete(intel_crtc->plane,
3873 work->pending_flip_obj);
3874 }
3875
3876 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3877 {
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3882 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3883 !intel_crtc_has_pending_flip(crtc),
3884 60*HZ) == 0)) {
3885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886
3887 spin_lock_irq(&dev->event_lock);
3888 if (intel_crtc->unpin_work) {
3889 WARN_ONCE(1, "Removing stuck page flip\n");
3890 page_flip_completed(intel_crtc);
3891 }
3892 spin_unlock_irq(&dev->event_lock);
3893 }
3894
3895 if (crtc->primary->fb) {
3896 mutex_lock(&dev->struct_mutex);
3897 intel_finish_fb(crtc->primary->fb);
3898 mutex_unlock(&dev->struct_mutex);
3899 }
3900 }
3901
3902 /* Program iCLKIP clock to the desired frequency */
3903 static void lpt_program_iclkip(struct drm_crtc *crtc)
3904 {
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3908 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3909 u32 temp;
3910
3911 mutex_lock(&dev_priv->sb_lock);
3912
3913 /* It is necessary to ungate the pixclk gate prior to programming
3914 * the divisors, and gate it back when it is done.
3915 */
3916 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3917
3918 /* Disable SSCCTL */
3919 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3920 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3921 SBI_SSCCTL_DISABLE,
3922 SBI_ICLK);
3923
3924 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3925 if (clock == 20000) {
3926 auxdiv = 1;
3927 divsel = 0x41;
3928 phaseinc = 0x20;
3929 } else {
3930 /* The iCLK virtual clock root frequency is in MHz,
3931 * but the adjusted_mode->crtc_clock in in KHz. To get the
3932 * divisors, it is necessary to divide one by another, so we
3933 * convert the virtual clock precision to KHz here for higher
3934 * precision.
3935 */
3936 u32 iclk_virtual_root_freq = 172800 * 1000;
3937 u32 iclk_pi_range = 64;
3938 u32 desired_divisor, msb_divisor_value, pi_value;
3939
3940 desired_divisor = (iclk_virtual_root_freq / clock);
3941 msb_divisor_value = desired_divisor / iclk_pi_range;
3942 pi_value = desired_divisor % iclk_pi_range;
3943
3944 auxdiv = 0;
3945 divsel = msb_divisor_value - 2;
3946 phaseinc = pi_value;
3947 }
3948
3949 /* This should not happen with any sane values */
3950 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3951 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3952 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3953 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3954
3955 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3956 clock,
3957 auxdiv,
3958 divsel,
3959 phasedir,
3960 phaseinc);
3961
3962 /* Program SSCDIVINTPHASE6 */
3963 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3964 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3965 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3966 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3967 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3968 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3969 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3970 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3971
3972 /* Program SSCAUXDIV */
3973 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3974 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3975 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3976 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3977
3978 /* Enable modulator and associated divider */
3979 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3980 temp &= ~SBI_SSCCTL_DISABLE;
3981 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3982
3983 /* Wait for initialization time */
3984 udelay(24);
3985
3986 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3987
3988 mutex_unlock(&dev_priv->sb_lock);
3989 }
3990
3991 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3992 enum pipe pch_transcoder)
3993 {
3994 struct drm_device *dev = crtc->base.dev;
3995 struct drm_i915_private *dev_priv = dev->dev_private;
3996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3997
3998 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3999 I915_READ(HTOTAL(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4001 I915_READ(HBLANK(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4003 I915_READ(HSYNC(cpu_transcoder)));
4004
4005 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4006 I915_READ(VTOTAL(cpu_transcoder)));
4007 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4008 I915_READ(VBLANK(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4010 I915_READ(VSYNC(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4012 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4013 }
4014
4015 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4016 {
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4018 uint32_t temp;
4019
4020 temp = I915_READ(SOUTH_CHICKEN1);
4021 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4022 return;
4023
4024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4025 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4026
4027 temp &= ~FDI_BC_BIFURCATION_SELECT;
4028 if (enable)
4029 temp |= FDI_BC_BIFURCATION_SELECT;
4030
4031 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4032 I915_WRITE(SOUTH_CHICKEN1, temp);
4033 POSTING_READ(SOUTH_CHICKEN1);
4034 }
4035
4036 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4037 {
4038 struct drm_device *dev = intel_crtc->base.dev;
4039
4040 switch (intel_crtc->pipe) {
4041 case PIPE_A:
4042 break;
4043 case PIPE_B:
4044 if (intel_crtc->config->fdi_lanes > 2)
4045 cpt_set_fdi_bc_bifurcation(dev, false);
4046 else
4047 cpt_set_fdi_bc_bifurcation(dev, true);
4048
4049 break;
4050 case PIPE_C:
4051 cpt_set_fdi_bc_bifurcation(dev, true);
4052
4053 break;
4054 default:
4055 BUG();
4056 }
4057 }
4058
4059 /*
4060 * Enable PCH resources required for PCH ports:
4061 * - PCH PLLs
4062 * - FDI training & RX/TX
4063 * - update transcoder timings
4064 * - DP transcoding bits
4065 * - transcoder
4066 */
4067 static void ironlake_pch_enable(struct drm_crtc *crtc)
4068 {
4069 struct drm_device *dev = crtc->dev;
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4072 int pipe = intel_crtc->pipe;
4073 u32 reg, temp;
4074
4075 assert_pch_transcoder_disabled(dev_priv, pipe);
4076
4077 if (IS_IVYBRIDGE(dev))
4078 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4079
4080 /* Write the TU size bits before fdi link training, so that error
4081 * detection works. */
4082 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4083 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4084
4085 /* For PCH output, training FDI link */
4086 dev_priv->display.fdi_link_train(crtc);
4087
4088 /* We need to program the right clock selection before writing the pixel
4089 * mutliplier into the DPLL. */
4090 if (HAS_PCH_CPT(dev)) {
4091 u32 sel;
4092
4093 temp = I915_READ(PCH_DPLL_SEL);
4094 temp |= TRANS_DPLL_ENABLE(pipe);
4095 sel = TRANS_DPLLB_SEL(pipe);
4096 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4097 temp |= sel;
4098 else
4099 temp &= ~sel;
4100 I915_WRITE(PCH_DPLL_SEL, temp);
4101 }
4102
4103 /* XXX: pch pll's can be enabled any time before we enable the PCH
4104 * transcoder, and we actually should do this to not upset any PCH
4105 * transcoder that already use the clock when we share it.
4106 *
4107 * Note that enable_shared_dpll tries to do the right thing, but
4108 * get_shared_dpll unconditionally resets the pll - we need that to have
4109 * the right LVDS enable sequence. */
4110 intel_enable_shared_dpll(intel_crtc);
4111
4112 /* set transcoder timing, panel must allow it */
4113 assert_panel_unlocked(dev_priv, pipe);
4114 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4115
4116 intel_fdi_normal_train(crtc);
4117
4118 /* For PCH DP, enable TRANS_DP_CTL */
4119 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4120 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4121 reg = TRANS_DP_CTL(pipe);
4122 temp = I915_READ(reg);
4123 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4124 TRANS_DP_SYNC_MASK |
4125 TRANS_DP_BPC_MASK);
4126 temp |= TRANS_DP_OUTPUT_ENABLE;
4127 temp |= bpc << 9; /* same format but at 11:9 */
4128
4129 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4130 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4131 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4132 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4133
4134 switch (intel_trans_dp_port_sel(crtc)) {
4135 case PCH_DP_B:
4136 temp |= TRANS_DP_PORT_SEL_B;
4137 break;
4138 case PCH_DP_C:
4139 temp |= TRANS_DP_PORT_SEL_C;
4140 break;
4141 case PCH_DP_D:
4142 temp |= TRANS_DP_PORT_SEL_D;
4143 break;
4144 default:
4145 BUG();
4146 }
4147
4148 I915_WRITE(reg, temp);
4149 }
4150
4151 ironlake_enable_pch_transcoder(dev_priv, pipe);
4152 }
4153
4154 static void lpt_pch_enable(struct drm_crtc *crtc)
4155 {
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4160
4161 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4162
4163 lpt_program_iclkip(crtc);
4164
4165 /* Set transcoder timing. */
4166 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4167
4168 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4169 }
4170
4171 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4172 struct intel_crtc_state *crtc_state)
4173 {
4174 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4175 struct intel_shared_dpll *pll;
4176 struct intel_shared_dpll_config *shared_dpll;
4177 enum intel_dpll_id i;
4178
4179 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4180
4181 if (HAS_PCH_IBX(dev_priv->dev)) {
4182 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4183 i = (enum intel_dpll_id) crtc->pipe;
4184 pll = &dev_priv->shared_dplls[i];
4185
4186 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4187 crtc->base.base.id, pll->name);
4188
4189 WARN_ON(shared_dpll[i].crtc_mask);
4190
4191 goto found;
4192 }
4193
4194 if (IS_BROXTON(dev_priv->dev)) {
4195 /* PLL is attached to port in bxt */
4196 struct intel_encoder *encoder;
4197 struct intel_digital_port *intel_dig_port;
4198
4199 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4200 if (WARN_ON(!encoder))
4201 return NULL;
4202
4203 intel_dig_port = enc_to_dig_port(&encoder->base);
4204 /* 1:1 mapping between ports and PLLs */
4205 i = (enum intel_dpll_id)intel_dig_port->port;
4206 pll = &dev_priv->shared_dplls[i];
4207 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4208 crtc->base.base.id, pll->name);
4209 WARN_ON(shared_dpll[i].crtc_mask);
4210
4211 goto found;
4212 }
4213
4214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215 pll = &dev_priv->shared_dplls[i];
4216
4217 /* Only want to check enabled timings first */
4218 if (shared_dpll[i].crtc_mask == 0)
4219 continue;
4220
4221 if (memcmp(&crtc_state->dpll_hw_state,
4222 &shared_dpll[i].hw_state,
4223 sizeof(crtc_state->dpll_hw_state)) == 0) {
4224 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4225 crtc->base.base.id, pll->name,
4226 shared_dpll[i].crtc_mask,
4227 pll->active);
4228 goto found;
4229 }
4230 }
4231
4232 /* Ok no matching timings, maybe there's a free one? */
4233 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4234 pll = &dev_priv->shared_dplls[i];
4235 if (shared_dpll[i].crtc_mask == 0) {
4236 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4237 crtc->base.base.id, pll->name);
4238 goto found;
4239 }
4240 }
4241
4242 return NULL;
4243
4244 found:
4245 if (shared_dpll[i].crtc_mask == 0)
4246 shared_dpll[i].hw_state =
4247 crtc_state->dpll_hw_state;
4248
4249 crtc_state->shared_dpll = i;
4250 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4251 pipe_name(crtc->pipe));
4252
4253 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4254
4255 return pll;
4256 }
4257
4258 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4259 {
4260 struct drm_i915_private *dev_priv = to_i915(state->dev);
4261 struct intel_shared_dpll_config *shared_dpll;
4262 struct intel_shared_dpll *pll;
4263 enum intel_dpll_id i;
4264
4265 if (!to_intel_atomic_state(state)->dpll_set)
4266 return;
4267
4268 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4269 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4270 pll = &dev_priv->shared_dplls[i];
4271 pll->config = shared_dpll[i];
4272 }
4273 }
4274
4275 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4276 {
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278 int dslreg = PIPEDSL(pipe);
4279 u32 temp;
4280
4281 temp = I915_READ(dslreg);
4282 udelay(500);
4283 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4284 if (wait_for(I915_READ(dslreg) != temp, 5))
4285 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4286 }
4287 }
4288
4289 static int
4290 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4291 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4292 int src_w, int src_h, int dst_w, int dst_h)
4293 {
4294 struct intel_crtc_scaler_state *scaler_state =
4295 &crtc_state->scaler_state;
4296 struct intel_crtc *intel_crtc =
4297 to_intel_crtc(crtc_state->base.crtc);
4298 int need_scaling;
4299
4300 need_scaling = intel_rotation_90_or_270(rotation) ?
4301 (src_h != dst_w || src_w != dst_h):
4302 (src_w != dst_w || src_h != dst_h);
4303
4304 /*
4305 * if plane is being disabled or scaler is no more required or force detach
4306 * - free scaler binded to this plane/crtc
4307 * - in order to do this, update crtc->scaler_usage
4308 *
4309 * Here scaler state in crtc_state is set free so that
4310 * scaler can be assigned to other user. Actual register
4311 * update to free the scaler is done in plane/panel-fit programming.
4312 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4313 */
4314 if (force_detach || !need_scaling) {
4315 if (*scaler_id >= 0) {
4316 scaler_state->scaler_users &= ~(1 << scaler_user);
4317 scaler_state->scalers[*scaler_id].in_use = 0;
4318
4319 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4320 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4321 intel_crtc->pipe, scaler_user, *scaler_id,
4322 scaler_state->scaler_users);
4323 *scaler_id = -1;
4324 }
4325 return 0;
4326 }
4327
4328 /* range checks */
4329 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4330 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4331
4332 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4333 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4334 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4335 "size is out of scaler range\n",
4336 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4337 return -EINVAL;
4338 }
4339
4340 /* mark this plane as a scaler user in crtc_state */
4341 scaler_state->scaler_users |= (1 << scaler_user);
4342 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4343 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4344 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4345 scaler_state->scaler_users);
4346
4347 return 0;
4348 }
4349
4350 /**
4351 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4352 *
4353 * @state: crtc's scaler state
4354 * @force_detach: whether to forcibly disable scaler
4355 *
4356 * Return
4357 * 0 - scaler_usage updated successfully
4358 * error - requested scaling cannot be supported or other error condition
4359 */
4360 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4361 {
4362 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4363 struct drm_display_mode *adjusted_mode =
4364 &state->base.adjusted_mode;
4365
4366 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4367 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4368
4369 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4370 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4371 state->pipe_src_w, state->pipe_src_h,
4372 adjusted_mode->hdisplay, adjusted_mode->hdisplay);
4373 }
4374
4375 /**
4376 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4377 *
4378 * @state: crtc's scaler state
4379 * @plane_state: atomic plane state to update
4380 *
4381 * Return
4382 * 0 - scaler_usage updated successfully
4383 * error - requested scaling cannot be supported or other error condition
4384 */
4385 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4386 struct intel_plane_state *plane_state)
4387 {
4388
4389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4390 struct intel_plane *intel_plane =
4391 to_intel_plane(plane_state->base.plane);
4392 struct drm_framebuffer *fb = plane_state->base.fb;
4393 int ret;
4394
4395 bool force_detach = !fb || !plane_state->visible;
4396
4397 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4398 intel_plane->base.base.id, intel_crtc->pipe,
4399 drm_plane_index(&intel_plane->base));
4400
4401 ret = skl_update_scaler(crtc_state, force_detach,
4402 drm_plane_index(&intel_plane->base),
4403 &plane_state->scaler_id,
4404 plane_state->base.rotation,
4405 drm_rect_width(&plane_state->src) >> 16,
4406 drm_rect_height(&plane_state->src) >> 16,
4407 drm_rect_width(&plane_state->dst),
4408 drm_rect_height(&plane_state->dst));
4409
4410 if (ret || plane_state->scaler_id < 0)
4411 return ret;
4412
4413 /* check colorkey */
4414 if (WARN_ON(intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4415 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4416 intel_plane->base.base.id);
4417 return -EINVAL;
4418 }
4419
4420 /* Check src format */
4421 switch (fb->pixel_format) {
4422 case DRM_FORMAT_RGB565:
4423 case DRM_FORMAT_XBGR8888:
4424 case DRM_FORMAT_XRGB8888:
4425 case DRM_FORMAT_ABGR8888:
4426 case DRM_FORMAT_ARGB8888:
4427 case DRM_FORMAT_XRGB2101010:
4428 case DRM_FORMAT_XBGR2101010:
4429 case DRM_FORMAT_YUYV:
4430 case DRM_FORMAT_YVYU:
4431 case DRM_FORMAT_UYVY:
4432 case DRM_FORMAT_VYUY:
4433 break;
4434 default:
4435 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4436 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4437 return -EINVAL;
4438 }
4439
4440 return 0;
4441 }
4442
4443 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4444 {
4445 struct drm_device *dev = crtc->base.dev;
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447 int pipe = crtc->pipe;
4448 struct intel_crtc_scaler_state *scaler_state =
4449 &crtc->config->scaler_state;
4450
4451 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4452
4453 /* To update pfit, first update scaler state */
4454 skl_update_scaler_crtc(crtc->config, !enable);
4455 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4456 skl_detach_scalers(crtc);
4457 if (!enable)
4458 return;
4459
4460 if (crtc->config->pch_pfit.enabled) {
4461 int id;
4462
4463 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4464 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4465 return;
4466 }
4467
4468 id = scaler_state->scaler_id;
4469 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4470 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4471 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4472 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4473
4474 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4475 }
4476 }
4477
4478 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4479 {
4480 struct drm_device *dev = crtc->base.dev;
4481 struct drm_i915_private *dev_priv = dev->dev_private;
4482 int pipe = crtc->pipe;
4483
4484 if (crtc->config->pch_pfit.enabled) {
4485 /* Force use of hard-coded filter coefficients
4486 * as some pre-programmed values are broken,
4487 * e.g. x201.
4488 */
4489 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4490 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4491 PF_PIPE_SEL_IVB(pipe));
4492 else
4493 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4494 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4495 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4496 }
4497 }
4498
4499 void hsw_enable_ips(struct intel_crtc *crtc)
4500 {
4501 struct drm_device *dev = crtc->base.dev;
4502 struct drm_i915_private *dev_priv = dev->dev_private;
4503
4504 if (!crtc->config->ips_enabled)
4505 return;
4506
4507 /* We can only enable IPS after we enable a plane and wait for a vblank */
4508 intel_wait_for_vblank(dev, crtc->pipe);
4509
4510 assert_plane_enabled(dev_priv, crtc->plane);
4511 if (IS_BROADWELL(dev)) {
4512 mutex_lock(&dev_priv->rps.hw_lock);
4513 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4514 mutex_unlock(&dev_priv->rps.hw_lock);
4515 /* Quoting Art Runyan: "its not safe to expect any particular
4516 * value in IPS_CTL bit 31 after enabling IPS through the
4517 * mailbox." Moreover, the mailbox may return a bogus state,
4518 * so we need to just enable it and continue on.
4519 */
4520 } else {
4521 I915_WRITE(IPS_CTL, IPS_ENABLE);
4522 /* The bit only becomes 1 in the next vblank, so this wait here
4523 * is essentially intel_wait_for_vblank. If we don't have this
4524 * and don't wait for vblanks until the end of crtc_enable, then
4525 * the HW state readout code will complain that the expected
4526 * IPS_CTL value is not the one we read. */
4527 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4528 DRM_ERROR("Timed out waiting for IPS enable\n");
4529 }
4530 }
4531
4532 void hsw_disable_ips(struct intel_crtc *crtc)
4533 {
4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536
4537 if (!crtc->config->ips_enabled)
4538 return;
4539
4540 assert_plane_enabled(dev_priv, crtc->plane);
4541 if (IS_BROADWELL(dev)) {
4542 mutex_lock(&dev_priv->rps.hw_lock);
4543 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4544 mutex_unlock(&dev_priv->rps.hw_lock);
4545 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4546 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4547 DRM_ERROR("Timed out waiting for IPS disable\n");
4548 } else {
4549 I915_WRITE(IPS_CTL, 0);
4550 POSTING_READ(IPS_CTL);
4551 }
4552
4553 /* We need to wait for a vblank before we can disable the plane. */
4554 intel_wait_for_vblank(dev, crtc->pipe);
4555 }
4556
4557 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4558 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4559 {
4560 struct drm_device *dev = crtc->dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4563 enum pipe pipe = intel_crtc->pipe;
4564 int palreg = PALETTE(pipe);
4565 int i;
4566 bool reenable_ips = false;
4567
4568 /* The clocks have to be on to load the palette. */
4569 if (!crtc->state->active)
4570 return;
4571
4572 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4573 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4574 assert_dsi_pll_enabled(dev_priv);
4575 else
4576 assert_pll_enabled(dev_priv, pipe);
4577 }
4578
4579 /* use legacy palette for Ironlake */
4580 if (!HAS_GMCH_DISPLAY(dev))
4581 palreg = LGC_PALETTE(pipe);
4582
4583 /* Workaround : Do not read or write the pipe palette/gamma data while
4584 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4585 */
4586 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4587 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4588 GAMMA_MODE_MODE_SPLIT)) {
4589 hsw_disable_ips(intel_crtc);
4590 reenable_ips = true;
4591 }
4592
4593 for (i = 0; i < 256; i++) {
4594 I915_WRITE(palreg + 4 * i,
4595 (intel_crtc->lut_r[i] << 16) |
4596 (intel_crtc->lut_g[i] << 8) |
4597 intel_crtc->lut_b[i]);
4598 }
4599
4600 if (reenable_ips)
4601 hsw_enable_ips(intel_crtc);
4602 }
4603
4604 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4605 {
4606 if (intel_crtc->overlay) {
4607 struct drm_device *dev = intel_crtc->base.dev;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609
4610 mutex_lock(&dev->struct_mutex);
4611 dev_priv->mm.interruptible = false;
4612 (void) intel_overlay_switch_off(intel_crtc->overlay);
4613 dev_priv->mm.interruptible = true;
4614 mutex_unlock(&dev->struct_mutex);
4615 }
4616
4617 /* Let userspace switch the overlay on again. In most cases userspace
4618 * has to recompute where to put it anyway.
4619 */
4620 }
4621
4622 /**
4623 * intel_post_enable_primary - Perform operations after enabling primary plane
4624 * @crtc: the CRTC whose primary plane was just enabled
4625 *
4626 * Performs potentially sleeping operations that must be done after the primary
4627 * plane is enabled, such as updating FBC and IPS. Note that this may be
4628 * called due to an explicit primary plane update, or due to an implicit
4629 * re-enable that is caused when a sprite plane is updated to no longer
4630 * completely hide the primary plane.
4631 */
4632 static void
4633 intel_post_enable_primary(struct drm_crtc *crtc)
4634 {
4635 struct drm_device *dev = crtc->dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4638 int pipe = intel_crtc->pipe;
4639
4640 /*
4641 * BDW signals flip done immediately if the plane
4642 * is disabled, even if the plane enable is already
4643 * armed to occur at the next vblank :(
4644 */
4645 if (IS_BROADWELL(dev))
4646 intel_wait_for_vblank(dev, pipe);
4647
4648 /*
4649 * FIXME IPS should be fine as long as one plane is
4650 * enabled, but in practice it seems to have problems
4651 * when going from primary only to sprite only and vice
4652 * versa.
4653 */
4654 hsw_enable_ips(intel_crtc);
4655
4656 /*
4657 * Gen2 reports pipe underruns whenever all planes are disabled.
4658 * So don't enable underrun reporting before at least some planes
4659 * are enabled.
4660 * FIXME: Need to fix the logic to work when we turn off all planes
4661 * but leave the pipe running.
4662 */
4663 if (IS_GEN2(dev))
4664 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4665
4666 /* Underruns don't raise interrupts, so check manually. */
4667 if (HAS_GMCH_DISPLAY(dev))
4668 i9xx_check_fifo_underruns(dev_priv);
4669 }
4670
4671 /**
4672 * intel_pre_disable_primary - Perform operations before disabling primary plane
4673 * @crtc: the CRTC whose primary plane is to be disabled
4674 *
4675 * Performs potentially sleeping operations that must be done before the
4676 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4677 * be called due to an explicit primary plane update, or due to an implicit
4678 * disable that is caused when a sprite plane completely hides the primary
4679 * plane.
4680 */
4681 static void
4682 intel_pre_disable_primary(struct drm_crtc *crtc)
4683 {
4684 struct drm_device *dev = crtc->dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4687 int pipe = intel_crtc->pipe;
4688
4689 /*
4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So diasble underrun reporting before all the planes get disabled.
4692 * FIXME: Need to fix the logic to work when we turn off all planes
4693 * but leave the pipe running.
4694 */
4695 if (IS_GEN2(dev))
4696 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4697
4698 /*
4699 * Vblank time updates from the shadow to live plane control register
4700 * are blocked if the memory self-refresh mode is active at that
4701 * moment. So to make sure the plane gets truly disabled, disable
4702 * first the self-refresh mode. The self-refresh enable bit in turn
4703 * will be checked/applied by the HW only at the next frame start
4704 * event which is after the vblank start event, so we need to have a
4705 * wait-for-vblank between disabling the plane and the pipe.
4706 */
4707 if (HAS_GMCH_DISPLAY(dev))
4708 intel_set_memory_cxsr(dev_priv, false);
4709
4710 /*
4711 * FIXME IPS should be fine as long as one plane is
4712 * enabled, but in practice it seems to have problems
4713 * when going from primary only to sprite only and vice
4714 * versa.
4715 */
4716 hsw_disable_ips(intel_crtc);
4717 }
4718
4719 static void intel_post_plane_update(struct intel_crtc *crtc)
4720 {
4721 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4722 struct drm_device *dev = crtc->base.dev;
4723 struct drm_plane *plane;
4724
4725 if (atomic->wait_vblank)
4726 intel_wait_for_vblank(dev, crtc->pipe);
4727
4728 intel_frontbuffer_flip(dev, atomic->fb_bits);
4729
4730 if (atomic->update_fbc) {
4731 mutex_lock(&dev->struct_mutex);
4732 intel_fbc_update(dev);
4733 mutex_unlock(&dev->struct_mutex);
4734 }
4735
4736 if (atomic->post_enable_primary)
4737 intel_post_enable_primary(&crtc->base);
4738
4739 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4740 intel_update_sprite_watermarks(plane, &crtc->base,
4741 0, 0, 0, false, false);
4742
4743 memset(atomic, 0, sizeof(*atomic));
4744 }
4745
4746 static void intel_pre_plane_update(struct intel_crtc *crtc)
4747 {
4748 struct drm_device *dev = crtc->base.dev;
4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4751 struct drm_plane *p;
4752
4753 /* Track fb's for any planes being disabled */
4754
4755 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4756 struct intel_plane *plane = to_intel_plane(p);
4757 unsigned fb_bits = 0;
4758
4759 switch (p->type) {
4760 case DRM_PLANE_TYPE_PRIMARY:
4761 fb_bits = INTEL_FRONTBUFFER_PRIMARY(plane->pipe);
4762 break;
4763 case DRM_PLANE_TYPE_CURSOR:
4764 fb_bits = INTEL_FRONTBUFFER_CURSOR(plane->pipe);
4765 break;
4766 case DRM_PLANE_TYPE_OVERLAY:
4767 fb_bits = INTEL_FRONTBUFFER_SPRITE(plane->pipe);
4768 break;
4769 }
4770
4771 mutex_lock(&dev->struct_mutex);
4772 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, fb_bits);
4773 mutex_unlock(&dev->struct_mutex);
4774 }
4775
4776 if (atomic->wait_for_flips)
4777 intel_crtc_wait_for_pending_flips(&crtc->base);
4778
4779 if (atomic->disable_fbc &&
4780 dev_priv->fbc.crtc == crtc) {
4781 mutex_lock(&dev->struct_mutex);
4782 if (dev_priv->fbc.crtc == crtc)
4783 intel_fbc_disable(dev);
4784 mutex_unlock(&dev->struct_mutex);
4785 }
4786
4787 if (atomic->pre_disable_primary)
4788 intel_pre_disable_primary(&crtc->base);
4789 }
4790
4791 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4792 {
4793 struct drm_device *dev = crtc->dev;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795 struct drm_plane *p;
4796 int pipe = intel_crtc->pipe;
4797
4798 intel_crtc_dpms_overlay_disable(intel_crtc);
4799
4800 drm_for_each_plane_mask(p, dev, plane_mask)
4801 to_intel_plane(p)->disable_plane(p, crtc);
4802
4803 /*
4804 * FIXME: Once we grow proper nuclear flip support out of this we need
4805 * to compute the mask of flip planes precisely. For the time being
4806 * consider this a flip to a NULL plane.
4807 */
4808 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4809 }
4810
4811 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4812 {
4813 struct drm_device *dev = crtc->dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4816 struct intel_encoder *encoder;
4817 int pipe = intel_crtc->pipe;
4818
4819 if (WARN_ON(intel_crtc->active))
4820 return;
4821
4822 if (intel_crtc->config->has_pch_encoder)
4823 intel_prepare_shared_dpll(intel_crtc);
4824
4825 if (intel_crtc->config->has_dp_encoder)
4826 intel_dp_set_m_n(intel_crtc, M1_N1);
4827
4828 intel_set_pipe_timings(intel_crtc);
4829
4830 if (intel_crtc->config->has_pch_encoder) {
4831 intel_cpu_transcoder_set_m_n(intel_crtc,
4832 &intel_crtc->config->fdi_m_n, NULL);
4833 }
4834
4835 ironlake_set_pipeconf(crtc);
4836
4837 intel_crtc->active = true;
4838
4839 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4840 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4841
4842 for_each_encoder_on_crtc(dev, crtc, encoder)
4843 if (encoder->pre_enable)
4844 encoder->pre_enable(encoder);
4845
4846 if (intel_crtc->config->has_pch_encoder) {
4847 /* Note: FDI PLL enabling _must_ be done before we enable the
4848 * cpu pipes, hence this is separate from all the other fdi/pch
4849 * enabling. */
4850 ironlake_fdi_pll_enable(intel_crtc);
4851 } else {
4852 assert_fdi_tx_disabled(dev_priv, pipe);
4853 assert_fdi_rx_disabled(dev_priv, pipe);
4854 }
4855
4856 ironlake_pfit_enable(intel_crtc);
4857
4858 /*
4859 * On ILK+ LUT must be loaded before the pipe is running but with
4860 * clocks enabled
4861 */
4862 intel_crtc_load_lut(crtc);
4863
4864 intel_update_watermarks(crtc);
4865 intel_enable_pipe(intel_crtc);
4866
4867 if (intel_crtc->config->has_pch_encoder)
4868 ironlake_pch_enable(crtc);
4869
4870 assert_vblank_disabled(crtc);
4871 drm_crtc_vblank_on(crtc);
4872
4873 for_each_encoder_on_crtc(dev, crtc, encoder)
4874 encoder->enable(encoder);
4875
4876 if (HAS_PCH_CPT(dev))
4877 cpt_verify_modeset(dev, intel_crtc->pipe);
4878 }
4879
4880 /* IPS only exists on ULT machines and is tied to pipe A. */
4881 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4882 {
4883 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4884 }
4885
4886 static void haswell_crtc_enable(struct drm_crtc *crtc)
4887 {
4888 struct drm_device *dev = crtc->dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 struct intel_encoder *encoder;
4892 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4893 struct intel_crtc_state *pipe_config =
4894 to_intel_crtc_state(crtc->state);
4895
4896 if (WARN_ON(intel_crtc->active))
4897 return;
4898
4899 if (intel_crtc_to_shared_dpll(intel_crtc))
4900 intel_enable_shared_dpll(intel_crtc);
4901
4902 if (intel_crtc->config->has_dp_encoder)
4903 intel_dp_set_m_n(intel_crtc, M1_N1);
4904
4905 intel_set_pipe_timings(intel_crtc);
4906
4907 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4908 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4909 intel_crtc->config->pixel_multiplier - 1);
4910 }
4911
4912 if (intel_crtc->config->has_pch_encoder) {
4913 intel_cpu_transcoder_set_m_n(intel_crtc,
4914 &intel_crtc->config->fdi_m_n, NULL);
4915 }
4916
4917 haswell_set_pipeconf(crtc);
4918
4919 intel_set_pipe_csc(crtc);
4920
4921 intel_crtc->active = true;
4922
4923 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4924 for_each_encoder_on_crtc(dev, crtc, encoder)
4925 if (encoder->pre_enable)
4926 encoder->pre_enable(encoder);
4927
4928 if (intel_crtc->config->has_pch_encoder) {
4929 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4930 true);
4931 dev_priv->display.fdi_link_train(crtc);
4932 }
4933
4934 intel_ddi_enable_pipe_clock(intel_crtc);
4935
4936 if (INTEL_INFO(dev)->gen == 9)
4937 skylake_pfit_update(intel_crtc, 1);
4938 else if (INTEL_INFO(dev)->gen < 9)
4939 ironlake_pfit_enable(intel_crtc);
4940 else
4941 MISSING_CASE(INTEL_INFO(dev)->gen);
4942
4943 /*
4944 * On ILK+ LUT must be loaded before the pipe is running but with
4945 * clocks enabled
4946 */
4947 intel_crtc_load_lut(crtc);
4948
4949 intel_ddi_set_pipe_settings(crtc);
4950 intel_ddi_enable_transcoder_func(crtc);
4951
4952 intel_update_watermarks(crtc);
4953 intel_enable_pipe(intel_crtc);
4954
4955 if (intel_crtc->config->has_pch_encoder)
4956 lpt_pch_enable(crtc);
4957
4958 if (intel_crtc->config->dp_encoder_is_mst)
4959 intel_ddi_set_vc_payload_alloc(crtc, true);
4960
4961 assert_vblank_disabled(crtc);
4962 drm_crtc_vblank_on(crtc);
4963
4964 for_each_encoder_on_crtc(dev, crtc, encoder) {
4965 encoder->enable(encoder);
4966 intel_opregion_notify_encoder(encoder, true);
4967 }
4968
4969 /* If we change the relative order between pipe/planes enabling, we need
4970 * to change the workaround. */
4971 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4972 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4973 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4974 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4975 }
4976 }
4977
4978 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4979 {
4980 struct drm_device *dev = crtc->base.dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 int pipe = crtc->pipe;
4983
4984 /* To avoid upsetting the power well on haswell only disable the pfit if
4985 * it's in use. The hw state code will make sure we get this right. */
4986 if (crtc->config->pch_pfit.enabled) {
4987 I915_WRITE(PF_CTL(pipe), 0);
4988 I915_WRITE(PF_WIN_POS(pipe), 0);
4989 I915_WRITE(PF_WIN_SZ(pipe), 0);
4990 }
4991 }
4992
4993 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4994 {
4995 struct drm_device *dev = crtc->dev;
4996 struct drm_i915_private *dev_priv = dev->dev_private;
4997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4998 struct intel_encoder *encoder;
4999 int pipe = intel_crtc->pipe;
5000 u32 reg, temp;
5001
5002 for_each_encoder_on_crtc(dev, crtc, encoder)
5003 encoder->disable(encoder);
5004
5005 drm_crtc_vblank_off(crtc);
5006 assert_vblank_disabled(crtc);
5007
5008 if (intel_crtc->config->has_pch_encoder)
5009 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5010
5011 intel_disable_pipe(intel_crtc);
5012
5013 ironlake_pfit_disable(intel_crtc);
5014
5015 if (intel_crtc->config->has_pch_encoder)
5016 ironlake_fdi_disable(crtc);
5017
5018 for_each_encoder_on_crtc(dev, crtc, encoder)
5019 if (encoder->post_disable)
5020 encoder->post_disable(encoder);
5021
5022 if (intel_crtc->config->has_pch_encoder) {
5023 ironlake_disable_pch_transcoder(dev_priv, pipe);
5024
5025 if (HAS_PCH_CPT(dev)) {
5026 /* disable TRANS_DP_CTL */
5027 reg = TRANS_DP_CTL(pipe);
5028 temp = I915_READ(reg);
5029 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5030 TRANS_DP_PORT_SEL_MASK);
5031 temp |= TRANS_DP_PORT_SEL_NONE;
5032 I915_WRITE(reg, temp);
5033
5034 /* disable DPLL_SEL */
5035 temp = I915_READ(PCH_DPLL_SEL);
5036 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5037 I915_WRITE(PCH_DPLL_SEL, temp);
5038 }
5039
5040 ironlake_fdi_pll_disable(intel_crtc);
5041 }
5042 }
5043
5044 static void haswell_crtc_disable(struct drm_crtc *crtc)
5045 {
5046 struct drm_device *dev = crtc->dev;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049 struct intel_encoder *encoder;
5050 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5051
5052 for_each_encoder_on_crtc(dev, crtc, encoder) {
5053 intel_opregion_notify_encoder(encoder, false);
5054 encoder->disable(encoder);
5055 }
5056
5057 drm_crtc_vblank_off(crtc);
5058 assert_vblank_disabled(crtc);
5059
5060 if (intel_crtc->config->has_pch_encoder)
5061 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5062 false);
5063 intel_disable_pipe(intel_crtc);
5064
5065 if (intel_crtc->config->dp_encoder_is_mst)
5066 intel_ddi_set_vc_payload_alloc(crtc, false);
5067
5068 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5069
5070 if (INTEL_INFO(dev)->gen == 9)
5071 skylake_pfit_update(intel_crtc, 0);
5072 else if (INTEL_INFO(dev)->gen < 9)
5073 ironlake_pfit_disable(intel_crtc);
5074 else
5075 MISSING_CASE(INTEL_INFO(dev)->gen);
5076
5077 intel_ddi_disable_pipe_clock(intel_crtc);
5078
5079 if (intel_crtc->config->has_pch_encoder) {
5080 lpt_disable_pch_transcoder(dev_priv);
5081 intel_ddi_fdi_disable(crtc);
5082 }
5083
5084 for_each_encoder_on_crtc(dev, crtc, encoder)
5085 if (encoder->post_disable)
5086 encoder->post_disable(encoder);
5087 }
5088
5089 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5090 {
5091 struct drm_device *dev = crtc->base.dev;
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 struct intel_crtc_state *pipe_config = crtc->config;
5094
5095 if (!pipe_config->gmch_pfit.control)
5096 return;
5097
5098 /*
5099 * The panel fitter should only be adjusted whilst the pipe is disabled,
5100 * according to register description and PRM.
5101 */
5102 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5103 assert_pipe_disabled(dev_priv, crtc->pipe);
5104
5105 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5106 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5107
5108 /* Border color in case we don't scale up to the full screen. Black by
5109 * default, change to something else for debugging. */
5110 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5111 }
5112
5113 static enum intel_display_power_domain port_to_power_domain(enum port port)
5114 {
5115 switch (port) {
5116 case PORT_A:
5117 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5118 case PORT_B:
5119 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5120 case PORT_C:
5121 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5122 case PORT_D:
5123 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5124 default:
5125 WARN_ON_ONCE(1);
5126 return POWER_DOMAIN_PORT_OTHER;
5127 }
5128 }
5129
5130 #define for_each_power_domain(domain, mask) \
5131 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5132 if ((1 << (domain)) & (mask))
5133
5134 enum intel_display_power_domain
5135 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5136 {
5137 struct drm_device *dev = intel_encoder->base.dev;
5138 struct intel_digital_port *intel_dig_port;
5139
5140 switch (intel_encoder->type) {
5141 case INTEL_OUTPUT_UNKNOWN:
5142 /* Only DDI platforms should ever use this output type */
5143 WARN_ON_ONCE(!HAS_DDI(dev));
5144 case INTEL_OUTPUT_DISPLAYPORT:
5145 case INTEL_OUTPUT_HDMI:
5146 case INTEL_OUTPUT_EDP:
5147 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5148 return port_to_power_domain(intel_dig_port->port);
5149 case INTEL_OUTPUT_DP_MST:
5150 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5151 return port_to_power_domain(intel_dig_port->port);
5152 case INTEL_OUTPUT_ANALOG:
5153 return POWER_DOMAIN_PORT_CRT;
5154 case INTEL_OUTPUT_DSI:
5155 return POWER_DOMAIN_PORT_DSI;
5156 default:
5157 return POWER_DOMAIN_PORT_OTHER;
5158 }
5159 }
5160
5161 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5162 {
5163 struct drm_device *dev = crtc->dev;
5164 struct intel_encoder *intel_encoder;
5165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5166 enum pipe pipe = intel_crtc->pipe;
5167 unsigned long mask;
5168 enum transcoder transcoder;
5169
5170 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5171
5172 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5173 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5174 if (intel_crtc->config->pch_pfit.enabled ||
5175 intel_crtc->config->pch_pfit.force_thru)
5176 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5177
5178 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5179 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5180
5181 return mask;
5182 }
5183
5184 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5185 {
5186 struct drm_device *dev = state->dev;
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5189 struct intel_crtc *crtc;
5190
5191 /*
5192 * First get all needed power domains, then put all unneeded, to avoid
5193 * any unnecessary toggling of the power wells.
5194 */
5195 for_each_intel_crtc(dev, crtc) {
5196 enum intel_display_power_domain domain;
5197
5198 if (!crtc->base.state->enable)
5199 continue;
5200
5201 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5202
5203 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5204 intel_display_power_get(dev_priv, domain);
5205 }
5206
5207 if (dev_priv->display.modeset_global_resources)
5208 dev_priv->display.modeset_global_resources(state);
5209
5210 for_each_intel_crtc(dev, crtc) {
5211 enum intel_display_power_domain domain;
5212
5213 for_each_power_domain(domain, crtc->enabled_power_domains)
5214 intel_display_power_put(dev_priv, domain);
5215
5216 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5217 }
5218
5219 intel_display_set_init_power(dev_priv, false);
5220 }
5221
5222 static void intel_update_max_cdclk(struct drm_device *dev)
5223 {
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225
5226 if (IS_SKYLAKE(dev)) {
5227 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5228
5229 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5230 dev_priv->max_cdclk_freq = 675000;
5231 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5232 dev_priv->max_cdclk_freq = 540000;
5233 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5234 dev_priv->max_cdclk_freq = 450000;
5235 else
5236 dev_priv->max_cdclk_freq = 337500;
5237 } else if (IS_BROADWELL(dev)) {
5238 /*
5239 * FIXME with extra cooling we can allow
5240 * 540 MHz for ULX and 675 Mhz for ULT.
5241 * How can we know if extra cooling is
5242 * available? PCI ID, VTB, something else?
5243 */
5244 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5245 dev_priv->max_cdclk_freq = 450000;
5246 else if (IS_BDW_ULX(dev))
5247 dev_priv->max_cdclk_freq = 450000;
5248 else if (IS_BDW_ULT(dev))
5249 dev_priv->max_cdclk_freq = 540000;
5250 else
5251 dev_priv->max_cdclk_freq = 675000;
5252 } else if (IS_CHERRYVIEW(dev)) {
5253 dev_priv->max_cdclk_freq = 320000;
5254 } else if (IS_VALLEYVIEW(dev)) {
5255 dev_priv->max_cdclk_freq = 400000;
5256 } else {
5257 /* otherwise assume cdclk is fixed */
5258 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5259 }
5260
5261 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5262 dev_priv->max_cdclk_freq);
5263 }
5264
5265 static void intel_update_cdclk(struct drm_device *dev)
5266 {
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268
5269 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5270 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5271 dev_priv->cdclk_freq);
5272
5273 /*
5274 * Program the gmbus_freq based on the cdclk frequency.
5275 * BSpec erroneously claims we should aim for 4MHz, but
5276 * in fact 1MHz is the correct frequency.
5277 */
5278 if (IS_VALLEYVIEW(dev)) {
5279 /*
5280 * Program the gmbus_freq based on the cdclk frequency.
5281 * BSpec erroneously claims we should aim for 4MHz, but
5282 * in fact 1MHz is the correct frequency.
5283 */
5284 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5285 }
5286
5287 if (dev_priv->max_cdclk_freq == 0)
5288 intel_update_max_cdclk(dev);
5289 }
5290
5291 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5292 {
5293 struct drm_i915_private *dev_priv = dev->dev_private;
5294 uint32_t divider;
5295 uint32_t ratio;
5296 uint32_t current_freq;
5297 int ret;
5298
5299 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5300 switch (frequency) {
5301 case 144000:
5302 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5303 ratio = BXT_DE_PLL_RATIO(60);
5304 break;
5305 case 288000:
5306 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5307 ratio = BXT_DE_PLL_RATIO(60);
5308 break;
5309 case 384000:
5310 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5311 ratio = BXT_DE_PLL_RATIO(60);
5312 break;
5313 case 576000:
5314 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5315 ratio = BXT_DE_PLL_RATIO(60);
5316 break;
5317 case 624000:
5318 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5319 ratio = BXT_DE_PLL_RATIO(65);
5320 break;
5321 case 19200:
5322 /*
5323 * Bypass frequency with DE PLL disabled. Init ratio, divider
5324 * to suppress GCC warning.
5325 */
5326 ratio = 0;
5327 divider = 0;
5328 break;
5329 default:
5330 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5331
5332 return;
5333 }
5334
5335 mutex_lock(&dev_priv->rps.hw_lock);
5336 /* Inform power controller of upcoming frequency change */
5337 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5338 0x80000000);
5339 mutex_unlock(&dev_priv->rps.hw_lock);
5340
5341 if (ret) {
5342 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5343 ret, frequency);
5344 return;
5345 }
5346
5347 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5348 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5349 current_freq = current_freq * 500 + 1000;
5350
5351 /*
5352 * DE PLL has to be disabled when
5353 * - setting to 19.2MHz (bypass, PLL isn't used)
5354 * - before setting to 624MHz (PLL needs toggling)
5355 * - before setting to any frequency from 624MHz (PLL needs toggling)
5356 */
5357 if (frequency == 19200 || frequency == 624000 ||
5358 current_freq == 624000) {
5359 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5360 /* Timeout 200us */
5361 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5362 1))
5363 DRM_ERROR("timout waiting for DE PLL unlock\n");
5364 }
5365
5366 if (frequency != 19200) {
5367 uint32_t val;
5368
5369 val = I915_READ(BXT_DE_PLL_CTL);
5370 val &= ~BXT_DE_PLL_RATIO_MASK;
5371 val |= ratio;
5372 I915_WRITE(BXT_DE_PLL_CTL, val);
5373
5374 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5375 /* Timeout 200us */
5376 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5377 DRM_ERROR("timeout waiting for DE PLL lock\n");
5378
5379 val = I915_READ(CDCLK_CTL);
5380 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5381 val |= divider;
5382 /*
5383 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5384 * enable otherwise.
5385 */
5386 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5387 if (frequency >= 500000)
5388 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5389
5390 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5391 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5392 val |= (frequency - 1000) / 500;
5393 I915_WRITE(CDCLK_CTL, val);
5394 }
5395
5396 mutex_lock(&dev_priv->rps.hw_lock);
5397 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 DIV_ROUND_UP(frequency, 25000));
5399 mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401 if (ret) {
5402 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5403 ret, frequency);
5404 return;
5405 }
5406
5407 intel_update_cdclk(dev);
5408 }
5409
5410 void broxton_init_cdclk(struct drm_device *dev)
5411 {
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413 uint32_t val;
5414
5415 /*
5416 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5417 * or else the reset will hang because there is no PCH to respond.
5418 * Move the handshake programming to initialization sequence.
5419 * Previously was left up to BIOS.
5420 */
5421 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5422 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5423 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5424
5425 /* Enable PG1 for cdclk */
5426 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5427
5428 /* check if cd clock is enabled */
5429 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5430 DRM_DEBUG_KMS("Display already initialized\n");
5431 return;
5432 }
5433
5434 /*
5435 * FIXME:
5436 * - The initial CDCLK needs to be read from VBT.
5437 * Need to make this change after VBT has changes for BXT.
5438 * - check if setting the max (or any) cdclk freq is really necessary
5439 * here, it belongs to modeset time
5440 */
5441 broxton_set_cdclk(dev, 624000);
5442
5443 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5444 POSTING_READ(DBUF_CTL);
5445
5446 udelay(10);
5447
5448 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5449 DRM_ERROR("DBuf power enable timeout!\n");
5450 }
5451
5452 void broxton_uninit_cdclk(struct drm_device *dev)
5453 {
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455
5456 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5457 POSTING_READ(DBUF_CTL);
5458
5459 udelay(10);
5460
5461 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5462 DRM_ERROR("DBuf power disable timeout!\n");
5463
5464 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5465 broxton_set_cdclk(dev, 19200);
5466
5467 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5468 }
5469
5470 static const struct skl_cdclk_entry {
5471 unsigned int freq;
5472 unsigned int vco;
5473 } skl_cdclk_frequencies[] = {
5474 { .freq = 308570, .vco = 8640 },
5475 { .freq = 337500, .vco = 8100 },
5476 { .freq = 432000, .vco = 8640 },
5477 { .freq = 450000, .vco = 8100 },
5478 { .freq = 540000, .vco = 8100 },
5479 { .freq = 617140, .vco = 8640 },
5480 { .freq = 675000, .vco = 8100 },
5481 };
5482
5483 static unsigned int skl_cdclk_decimal(unsigned int freq)
5484 {
5485 return (freq - 1000) / 500;
5486 }
5487
5488 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5489 {
5490 unsigned int i;
5491
5492 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5493 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5494
5495 if (e->freq == freq)
5496 return e->vco;
5497 }
5498
5499 return 8100;
5500 }
5501
5502 static void
5503 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5504 {
5505 unsigned int min_freq;
5506 u32 val;
5507
5508 /* select the minimum CDCLK before enabling DPLL 0 */
5509 val = I915_READ(CDCLK_CTL);
5510 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5511 val |= CDCLK_FREQ_337_308;
5512
5513 if (required_vco == 8640)
5514 min_freq = 308570;
5515 else
5516 min_freq = 337500;
5517
5518 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5519
5520 I915_WRITE(CDCLK_CTL, val);
5521 POSTING_READ(CDCLK_CTL);
5522
5523 /*
5524 * We always enable DPLL0 with the lowest link rate possible, but still
5525 * taking into account the VCO required to operate the eDP panel at the
5526 * desired frequency. The usual DP link rates operate with a VCO of
5527 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5528 * The modeset code is responsible for the selection of the exact link
5529 * rate later on, with the constraint of choosing a frequency that
5530 * works with required_vco.
5531 */
5532 val = I915_READ(DPLL_CTRL1);
5533
5534 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5535 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5536 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5537 if (required_vco == 8640)
5538 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5539 SKL_DPLL0);
5540 else
5541 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5542 SKL_DPLL0);
5543
5544 I915_WRITE(DPLL_CTRL1, val);
5545 POSTING_READ(DPLL_CTRL1);
5546
5547 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5548
5549 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5550 DRM_ERROR("DPLL0 not locked\n");
5551 }
5552
5553 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5554 {
5555 int ret;
5556 u32 val;
5557
5558 /* inform PCU we want to change CDCLK */
5559 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5560 mutex_lock(&dev_priv->rps.hw_lock);
5561 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5562 mutex_unlock(&dev_priv->rps.hw_lock);
5563
5564 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5565 }
5566
5567 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5568 {
5569 unsigned int i;
5570
5571 for (i = 0; i < 15; i++) {
5572 if (skl_cdclk_pcu_ready(dev_priv))
5573 return true;
5574 udelay(10);
5575 }
5576
5577 return false;
5578 }
5579
5580 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5581 {
5582 struct drm_device *dev = dev_priv->dev;
5583 u32 freq_select, pcu_ack;
5584
5585 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5586
5587 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5588 DRM_ERROR("failed to inform PCU about cdclk change\n");
5589 return;
5590 }
5591
5592 /* set CDCLK_CTL */
5593 switch(freq) {
5594 case 450000:
5595 case 432000:
5596 freq_select = CDCLK_FREQ_450_432;
5597 pcu_ack = 1;
5598 break;
5599 case 540000:
5600 freq_select = CDCLK_FREQ_540;
5601 pcu_ack = 2;
5602 break;
5603 case 308570:
5604 case 337500:
5605 default:
5606 freq_select = CDCLK_FREQ_337_308;
5607 pcu_ack = 0;
5608 break;
5609 case 617140:
5610 case 675000:
5611 freq_select = CDCLK_FREQ_675_617;
5612 pcu_ack = 3;
5613 break;
5614 }
5615
5616 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5617 POSTING_READ(CDCLK_CTL);
5618
5619 /* inform PCU of the change */
5620 mutex_lock(&dev_priv->rps.hw_lock);
5621 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5622 mutex_unlock(&dev_priv->rps.hw_lock);
5623
5624 intel_update_cdclk(dev);
5625 }
5626
5627 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5628 {
5629 /* disable DBUF power */
5630 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5631 POSTING_READ(DBUF_CTL);
5632
5633 udelay(10);
5634
5635 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5636 DRM_ERROR("DBuf power disable timeout\n");
5637
5638 /* disable DPLL0 */
5639 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5640 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5641 DRM_ERROR("Couldn't disable DPLL0\n");
5642
5643 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5644 }
5645
5646 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5647 {
5648 u32 val;
5649 unsigned int required_vco;
5650
5651 /* enable PCH reset handshake */
5652 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5653 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5654
5655 /* enable PG1 and Misc I/O */
5656 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5657
5658 /* DPLL0 already enabed !? */
5659 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5660 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5661 return;
5662 }
5663
5664 /* enable DPLL0 */
5665 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5666 skl_dpll0_enable(dev_priv, required_vco);
5667
5668 /* set CDCLK to the frequency the BIOS chose */
5669 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5670
5671 /* enable DBUF power */
5672 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5673 POSTING_READ(DBUF_CTL);
5674
5675 udelay(10);
5676
5677 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5678 DRM_ERROR("DBuf power enable timeout\n");
5679 }
5680
5681 /* returns HPLL frequency in kHz */
5682 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5683 {
5684 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5685
5686 /* Obtain SKU information */
5687 mutex_lock(&dev_priv->sb_lock);
5688 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5689 CCK_FUSE_HPLL_FREQ_MASK;
5690 mutex_unlock(&dev_priv->sb_lock);
5691
5692 return vco_freq[hpll_freq] * 1000;
5693 }
5694
5695 /* Adjust CDclk dividers to allow high res or save power if possible */
5696 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5697 {
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 u32 val, cmd;
5700
5701 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5702 != dev_priv->cdclk_freq);
5703
5704 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5705 cmd = 2;
5706 else if (cdclk == 266667)
5707 cmd = 1;
5708 else
5709 cmd = 0;
5710
5711 mutex_lock(&dev_priv->rps.hw_lock);
5712 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5713 val &= ~DSPFREQGUAR_MASK;
5714 val |= (cmd << DSPFREQGUAR_SHIFT);
5715 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5716 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5717 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5718 50)) {
5719 DRM_ERROR("timed out waiting for CDclk change\n");
5720 }
5721 mutex_unlock(&dev_priv->rps.hw_lock);
5722
5723 mutex_lock(&dev_priv->sb_lock);
5724
5725 if (cdclk == 400000) {
5726 u32 divider;
5727
5728 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5729
5730 /* adjust cdclk divider */
5731 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5732 val &= ~DISPLAY_FREQUENCY_VALUES;
5733 val |= divider;
5734 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5735
5736 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5737 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5738 50))
5739 DRM_ERROR("timed out waiting for CDclk change\n");
5740 }
5741
5742 /* adjust self-refresh exit latency value */
5743 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5744 val &= ~0x7f;
5745
5746 /*
5747 * For high bandwidth configs, we set a higher latency in the bunit
5748 * so that the core display fetch happens in time to avoid underruns.
5749 */
5750 if (cdclk == 400000)
5751 val |= 4500 / 250; /* 4.5 usec */
5752 else
5753 val |= 3000 / 250; /* 3.0 usec */
5754 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5755
5756 mutex_unlock(&dev_priv->sb_lock);
5757
5758 intel_update_cdclk(dev);
5759 }
5760
5761 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5762 {
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764 u32 val, cmd;
5765
5766 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5767 != dev_priv->cdclk_freq);
5768
5769 switch (cdclk) {
5770 case 333333:
5771 case 320000:
5772 case 266667:
5773 case 200000:
5774 break;
5775 default:
5776 MISSING_CASE(cdclk);
5777 return;
5778 }
5779
5780 /*
5781 * Specs are full of misinformation, but testing on actual
5782 * hardware has shown that we just need to write the desired
5783 * CCK divider into the Punit register.
5784 */
5785 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5786
5787 mutex_lock(&dev_priv->rps.hw_lock);
5788 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5789 val &= ~DSPFREQGUAR_MASK_CHV;
5790 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5791 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5792 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5793 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5794 50)) {
5795 DRM_ERROR("timed out waiting for CDclk change\n");
5796 }
5797 mutex_unlock(&dev_priv->rps.hw_lock);
5798
5799 intel_update_cdclk(dev);
5800 }
5801
5802 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5803 int max_pixclk)
5804 {
5805 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5806 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5807
5808 /*
5809 * Really only a few cases to deal with, as only 4 CDclks are supported:
5810 * 200MHz
5811 * 267MHz
5812 * 320/333MHz (depends on HPLL freq)
5813 * 400MHz (VLV only)
5814 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5815 * of the lower bin and adjust if needed.
5816 *
5817 * We seem to get an unstable or solid color picture at 200MHz.
5818 * Not sure what's wrong. For now use 200MHz only when all pipes
5819 * are off.
5820 */
5821 if (!IS_CHERRYVIEW(dev_priv) &&
5822 max_pixclk > freq_320*limit/100)
5823 return 400000;
5824 else if (max_pixclk > 266667*limit/100)
5825 return freq_320;
5826 else if (max_pixclk > 0)
5827 return 266667;
5828 else
5829 return 200000;
5830 }
5831
5832 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5833 int max_pixclk)
5834 {
5835 /*
5836 * FIXME:
5837 * - remove the guardband, it's not needed on BXT
5838 * - set 19.2MHz bypass frequency if there are no active pipes
5839 */
5840 if (max_pixclk > 576000*9/10)
5841 return 624000;
5842 else if (max_pixclk > 384000*9/10)
5843 return 576000;
5844 else if (max_pixclk > 288000*9/10)
5845 return 384000;
5846 else if (max_pixclk > 144000*9/10)
5847 return 288000;
5848 else
5849 return 144000;
5850 }
5851
5852 /* Compute the max pixel clock for new configuration. Uses atomic state if
5853 * that's non-NULL, look at current state otherwise. */
5854 static int intel_mode_max_pixclk(struct drm_device *dev,
5855 struct drm_atomic_state *state)
5856 {
5857 struct intel_crtc *intel_crtc;
5858 struct intel_crtc_state *crtc_state;
5859 int max_pixclk = 0;
5860
5861 for_each_intel_crtc(dev, intel_crtc) {
5862 if (state)
5863 crtc_state =
5864 intel_atomic_get_crtc_state(state, intel_crtc);
5865 else
5866 crtc_state = intel_crtc->config;
5867 if (IS_ERR(crtc_state))
5868 return PTR_ERR(crtc_state);
5869
5870 if (!crtc_state->base.enable)
5871 continue;
5872
5873 max_pixclk = max(max_pixclk,
5874 crtc_state->base.adjusted_mode.crtc_clock);
5875 }
5876
5877 return max_pixclk;
5878 }
5879
5880 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5881 {
5882 struct drm_i915_private *dev_priv = to_i915(state->dev);
5883 struct drm_crtc *crtc;
5884 struct drm_crtc_state *crtc_state;
5885 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5886 int cdclk, ret = 0;
5887
5888 if (max_pixclk < 0)
5889 return max_pixclk;
5890
5891 if (IS_VALLEYVIEW(dev_priv))
5892 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5893 else
5894 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5895
5896 if (cdclk == dev_priv->cdclk_freq)
5897 return 0;
5898
5899 /* add all active pipes to the state */
5900 for_each_crtc(state->dev, crtc) {
5901 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5902 if (IS_ERR(crtc_state))
5903 return PTR_ERR(crtc_state);
5904
5905 if (!crtc_state->active || needs_modeset(crtc_state))
5906 continue;
5907
5908 crtc_state->mode_changed = true;
5909
5910 ret = drm_atomic_add_affected_connectors(state, crtc);
5911 if (ret)
5912 break;
5913
5914 ret = drm_atomic_add_affected_planes(state, crtc);
5915 if (ret)
5916 break;
5917 }
5918
5919 return ret;
5920 }
5921
5922 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5923 {
5924 unsigned int credits, default_credits;
5925
5926 if (IS_CHERRYVIEW(dev_priv))
5927 default_credits = PFI_CREDIT(12);
5928 else
5929 default_credits = PFI_CREDIT(8);
5930
5931 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5932 /* CHV suggested value is 31 or 63 */
5933 if (IS_CHERRYVIEW(dev_priv))
5934 credits = PFI_CREDIT_63;
5935 else
5936 credits = PFI_CREDIT(15);
5937 } else {
5938 credits = default_credits;
5939 }
5940
5941 /*
5942 * WA - write default credits before re-programming
5943 * FIXME: should we also set the resend bit here?
5944 */
5945 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5946 default_credits);
5947
5948 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5949 credits | PFI_CREDIT_RESEND);
5950
5951 /*
5952 * FIXME is this guaranteed to clear
5953 * immediately or should we poll for it?
5954 */
5955 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5956 }
5957
5958 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5959 {
5960 struct drm_device *dev = old_state->dev;
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5963 int req_cdclk;
5964
5965 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5966 * never fail. */
5967 if (WARN_ON(max_pixclk < 0))
5968 return;
5969
5970 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5971
5972 if (req_cdclk != dev_priv->cdclk_freq) {
5973 /*
5974 * FIXME: We can end up here with all power domains off, yet
5975 * with a CDCLK frequency other than the minimum. To account
5976 * for this take the PIPE-A power domain, which covers the HW
5977 * blocks needed for the following programming. This can be
5978 * removed once it's guaranteed that we get here either with
5979 * the minimum CDCLK set, or the required power domains
5980 * enabled.
5981 */
5982 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5983
5984 if (IS_CHERRYVIEW(dev))
5985 cherryview_set_cdclk(dev, req_cdclk);
5986 else
5987 valleyview_set_cdclk(dev, req_cdclk);
5988
5989 vlv_program_pfi_credits(dev_priv);
5990
5991 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5992 }
5993 }
5994
5995 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5996 {
5997 struct drm_device *dev = crtc->dev;
5998 struct drm_i915_private *dev_priv = to_i915(dev);
5999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000 struct intel_encoder *encoder;
6001 int pipe = intel_crtc->pipe;
6002 bool is_dsi;
6003
6004 if (WARN_ON(intel_crtc->active))
6005 return;
6006
6007 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6008
6009 if (!is_dsi) {
6010 if (IS_CHERRYVIEW(dev))
6011 chv_prepare_pll(intel_crtc, intel_crtc->config);
6012 else
6013 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6014 }
6015
6016 if (intel_crtc->config->has_dp_encoder)
6017 intel_dp_set_m_n(intel_crtc, M1_N1);
6018
6019 intel_set_pipe_timings(intel_crtc);
6020
6021 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023
6024 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6025 I915_WRITE(CHV_CANVAS(pipe), 0);
6026 }
6027
6028 i9xx_set_pipeconf(intel_crtc);
6029
6030 intel_crtc->active = true;
6031
6032 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6033
6034 for_each_encoder_on_crtc(dev, crtc, encoder)
6035 if (encoder->pre_pll_enable)
6036 encoder->pre_pll_enable(encoder);
6037
6038 if (!is_dsi) {
6039 if (IS_CHERRYVIEW(dev))
6040 chv_enable_pll(intel_crtc, intel_crtc->config);
6041 else
6042 vlv_enable_pll(intel_crtc, intel_crtc->config);
6043 }
6044
6045 for_each_encoder_on_crtc(dev, crtc, encoder)
6046 if (encoder->pre_enable)
6047 encoder->pre_enable(encoder);
6048
6049 i9xx_pfit_enable(intel_crtc);
6050
6051 intel_crtc_load_lut(crtc);
6052
6053 intel_update_watermarks(crtc);
6054 intel_enable_pipe(intel_crtc);
6055
6056 assert_vblank_disabled(crtc);
6057 drm_crtc_vblank_on(crtc);
6058
6059 for_each_encoder_on_crtc(dev, crtc, encoder)
6060 encoder->enable(encoder);
6061 }
6062
6063 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6064 {
6065 struct drm_device *dev = crtc->base.dev;
6066 struct drm_i915_private *dev_priv = dev->dev_private;
6067
6068 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6069 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6070 }
6071
6072 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6073 {
6074 struct drm_device *dev = crtc->dev;
6075 struct drm_i915_private *dev_priv = to_i915(dev);
6076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6077 struct intel_encoder *encoder;
6078 int pipe = intel_crtc->pipe;
6079
6080 if (WARN_ON(intel_crtc->active))
6081 return;
6082
6083 i9xx_set_pll_dividers(intel_crtc);
6084
6085 if (intel_crtc->config->has_dp_encoder)
6086 intel_dp_set_m_n(intel_crtc, M1_N1);
6087
6088 intel_set_pipe_timings(intel_crtc);
6089
6090 i9xx_set_pipeconf(intel_crtc);
6091
6092 intel_crtc->active = true;
6093
6094 if (!IS_GEN2(dev))
6095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6096
6097 for_each_encoder_on_crtc(dev, crtc, encoder)
6098 if (encoder->pre_enable)
6099 encoder->pre_enable(encoder);
6100
6101 i9xx_enable_pll(intel_crtc);
6102
6103 i9xx_pfit_enable(intel_crtc);
6104
6105 intel_crtc_load_lut(crtc);
6106
6107 intel_update_watermarks(crtc);
6108 intel_enable_pipe(intel_crtc);
6109
6110 assert_vblank_disabled(crtc);
6111 drm_crtc_vblank_on(crtc);
6112
6113 for_each_encoder_on_crtc(dev, crtc, encoder)
6114 encoder->enable(encoder);
6115 }
6116
6117 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6118 {
6119 struct drm_device *dev = crtc->base.dev;
6120 struct drm_i915_private *dev_priv = dev->dev_private;
6121
6122 if (!crtc->config->gmch_pfit.control)
6123 return;
6124
6125 assert_pipe_disabled(dev_priv, crtc->pipe);
6126
6127 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6128 I915_READ(PFIT_CONTROL));
6129 I915_WRITE(PFIT_CONTROL, 0);
6130 }
6131
6132 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6133 {
6134 struct drm_device *dev = crtc->dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137 struct intel_encoder *encoder;
6138 int pipe = intel_crtc->pipe;
6139
6140 /*
6141 * On gen2 planes are double buffered but the pipe isn't, so we must
6142 * wait for planes to fully turn off before disabling the pipe.
6143 * We also need to wait on all gmch platforms because of the
6144 * self-refresh mode constraint explained above.
6145 */
6146 intel_wait_for_vblank(dev, pipe);
6147
6148 for_each_encoder_on_crtc(dev, crtc, encoder)
6149 encoder->disable(encoder);
6150
6151 drm_crtc_vblank_off(crtc);
6152 assert_vblank_disabled(crtc);
6153
6154 intel_disable_pipe(intel_crtc);
6155
6156 i9xx_pfit_disable(intel_crtc);
6157
6158 for_each_encoder_on_crtc(dev, crtc, encoder)
6159 if (encoder->post_disable)
6160 encoder->post_disable(encoder);
6161
6162 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6163 if (IS_CHERRYVIEW(dev))
6164 chv_disable_pll(dev_priv, pipe);
6165 else if (IS_VALLEYVIEW(dev))
6166 vlv_disable_pll(dev_priv, pipe);
6167 else
6168 i9xx_disable_pll(intel_crtc);
6169 }
6170
6171 if (!IS_GEN2(dev))
6172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6173 }
6174
6175 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6176 {
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6179 enum intel_display_power_domain domain;
6180 unsigned long domains;
6181
6182 if (!intel_crtc->active)
6183 return;
6184
6185 if (to_intel_plane_state(crtc->primary->state)->visible) {
6186 intel_crtc_wait_for_pending_flips(crtc);
6187 intel_pre_disable_primary(crtc);
6188 }
6189
6190 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6191 dev_priv->display.crtc_disable(crtc);
6192
6193 domains = intel_crtc->enabled_power_domains;
6194 for_each_power_domain(domain, domains)
6195 intel_display_power_put(dev_priv, domain);
6196 intel_crtc->enabled_power_domains = 0;
6197 }
6198
6199 /*
6200 * turn all crtc's off, but do not adjust state
6201 * This has to be paired with a call to intel_modeset_setup_hw_state.
6202 */
6203 void intel_display_suspend(struct drm_device *dev)
6204 {
6205 struct drm_crtc *crtc;
6206
6207 for_each_crtc(dev, crtc)
6208 intel_crtc_disable_noatomic(crtc);
6209 }
6210
6211 /* Master function to enable/disable CRTC and corresponding power wells */
6212 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6213 {
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_mode_config *config = &dev->mode_config;
6216 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218 struct intel_crtc_state *pipe_config;
6219 struct drm_atomic_state *state;
6220 int ret;
6221
6222 if (enable == intel_crtc->active)
6223 return 0;
6224
6225 if (enable && !crtc->state->enable)
6226 return 0;
6227
6228 /* this function should be called with drm_modeset_lock_all for now */
6229 if (WARN_ON(!ctx))
6230 return -EIO;
6231 lockdep_assert_held(&ctx->ww_ctx);
6232
6233 state = drm_atomic_state_alloc(dev);
6234 if (WARN_ON(!state))
6235 return -ENOMEM;
6236
6237 state->acquire_ctx = ctx;
6238 state->allow_modeset = true;
6239
6240 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6241 if (IS_ERR(pipe_config)) {
6242 ret = PTR_ERR(pipe_config);
6243 goto err;
6244 }
6245 pipe_config->base.active = enable;
6246
6247 ret = intel_set_mode(state);
6248 if (!ret)
6249 return ret;
6250
6251 err:
6252 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6253 drm_atomic_state_free(state);
6254 return ret;
6255 }
6256
6257 /**
6258 * Sets the power management mode of the pipe and plane.
6259 */
6260 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6261 {
6262 struct drm_device *dev = crtc->dev;
6263 struct intel_encoder *intel_encoder;
6264 bool enable = false;
6265
6266 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6267 enable |= intel_encoder->connectors_active;
6268
6269 intel_crtc_control(crtc, enable);
6270 }
6271
6272 void intel_encoder_destroy(struct drm_encoder *encoder)
6273 {
6274 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6275
6276 drm_encoder_cleanup(encoder);
6277 kfree(intel_encoder);
6278 }
6279
6280 /* Simple dpms helper for encoders with just one connector, no cloning and only
6281 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6282 * state of the entire output pipe. */
6283 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6284 {
6285 if (mode == DRM_MODE_DPMS_ON) {
6286 encoder->connectors_active = true;
6287
6288 intel_crtc_update_dpms(encoder->base.crtc);
6289 } else {
6290 encoder->connectors_active = false;
6291
6292 intel_crtc_update_dpms(encoder->base.crtc);
6293 }
6294 }
6295
6296 /* Cross check the actual hw state with our own modeset state tracking (and it's
6297 * internal consistency). */
6298 static void intel_connector_check_state(struct intel_connector *connector)
6299 {
6300 if (connector->get_hw_state(connector)) {
6301 struct intel_encoder *encoder = connector->encoder;
6302 struct drm_crtc *crtc;
6303 bool encoder_enabled;
6304 enum pipe pipe;
6305
6306 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6307 connector->base.base.id,
6308 connector->base.name);
6309
6310 /* there is no real hw state for MST connectors */
6311 if (connector->mst_port)
6312 return;
6313
6314 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6315 "wrong connector dpms state\n");
6316 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6317 "active connector not linked to encoder\n");
6318
6319 if (encoder) {
6320 I915_STATE_WARN(!encoder->connectors_active,
6321 "encoder->connectors_active not set\n");
6322
6323 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6324 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6325 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6326 return;
6327
6328 crtc = encoder->base.crtc;
6329
6330 I915_STATE_WARN(!crtc->state->enable,
6331 "crtc not enabled\n");
6332 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6333 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6334 "encoder active on the wrong pipe\n");
6335 }
6336 }
6337 }
6338
6339 int intel_connector_init(struct intel_connector *connector)
6340 {
6341 struct drm_connector_state *connector_state;
6342
6343 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6344 if (!connector_state)
6345 return -ENOMEM;
6346
6347 connector->base.state = connector_state;
6348 return 0;
6349 }
6350
6351 struct intel_connector *intel_connector_alloc(void)
6352 {
6353 struct intel_connector *connector;
6354
6355 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6356 if (!connector)
6357 return NULL;
6358
6359 if (intel_connector_init(connector) < 0) {
6360 kfree(connector);
6361 return NULL;
6362 }
6363
6364 return connector;
6365 }
6366
6367 /* Even simpler default implementation, if there's really no special case to
6368 * consider. */
6369 void intel_connector_dpms(struct drm_connector *connector, int mode)
6370 {
6371 /* All the simple cases only support two dpms states. */
6372 if (mode != DRM_MODE_DPMS_ON)
6373 mode = DRM_MODE_DPMS_OFF;
6374
6375 if (mode == connector->dpms)
6376 return;
6377
6378 connector->dpms = mode;
6379
6380 /* Only need to change hw state when actually enabled */
6381 if (connector->encoder)
6382 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6383
6384 intel_modeset_check_state(connector->dev);
6385 }
6386
6387 /* Simple connector->get_hw_state implementation for encoders that support only
6388 * one connector and no cloning and hence the encoder state determines the state
6389 * of the connector. */
6390 bool intel_connector_get_hw_state(struct intel_connector *connector)
6391 {
6392 enum pipe pipe = 0;
6393 struct intel_encoder *encoder = connector->encoder;
6394
6395 return encoder->get_hw_state(encoder, &pipe);
6396 }
6397
6398 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6399 {
6400 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6401 return crtc_state->fdi_lanes;
6402
6403 return 0;
6404 }
6405
6406 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6407 struct intel_crtc_state *pipe_config)
6408 {
6409 struct drm_atomic_state *state = pipe_config->base.state;
6410 struct intel_crtc *other_crtc;
6411 struct intel_crtc_state *other_crtc_state;
6412
6413 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6415 if (pipe_config->fdi_lanes > 4) {
6416 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6417 pipe_name(pipe), pipe_config->fdi_lanes);
6418 return -EINVAL;
6419 }
6420
6421 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6422 if (pipe_config->fdi_lanes > 2) {
6423 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6424 pipe_config->fdi_lanes);
6425 return -EINVAL;
6426 } else {
6427 return 0;
6428 }
6429 }
6430
6431 if (INTEL_INFO(dev)->num_pipes == 2)
6432 return 0;
6433
6434 /* Ivybridge 3 pipe is really complicated */
6435 switch (pipe) {
6436 case PIPE_A:
6437 return 0;
6438 case PIPE_B:
6439 if (pipe_config->fdi_lanes <= 2)
6440 return 0;
6441
6442 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6443 other_crtc_state =
6444 intel_atomic_get_crtc_state(state, other_crtc);
6445 if (IS_ERR(other_crtc_state))
6446 return PTR_ERR(other_crtc_state);
6447
6448 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6449 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6451 return -EINVAL;
6452 }
6453 return 0;
6454 case PIPE_C:
6455 if (pipe_config->fdi_lanes > 2) {
6456 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6457 pipe_name(pipe), pipe_config->fdi_lanes);
6458 return -EINVAL;
6459 }
6460
6461 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6462 other_crtc_state =
6463 intel_atomic_get_crtc_state(state, other_crtc);
6464 if (IS_ERR(other_crtc_state))
6465 return PTR_ERR(other_crtc_state);
6466
6467 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6468 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6469 return -EINVAL;
6470 }
6471 return 0;
6472 default:
6473 BUG();
6474 }
6475 }
6476
6477 #define RETRY 1
6478 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6479 struct intel_crtc_state *pipe_config)
6480 {
6481 struct drm_device *dev = intel_crtc->base.dev;
6482 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6483 int lane, link_bw, fdi_dotclock, ret;
6484 bool needs_recompute = false;
6485
6486 retry:
6487 /* FDI is a binary signal running at ~2.7GHz, encoding
6488 * each output octet as 10 bits. The actual frequency
6489 * is stored as a divider into a 100MHz clock, and the
6490 * mode pixel clock is stored in units of 1KHz.
6491 * Hence the bw of each lane in terms of the mode signal
6492 * is:
6493 */
6494 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6495
6496 fdi_dotclock = adjusted_mode->crtc_clock;
6497
6498 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6499 pipe_config->pipe_bpp);
6500
6501 pipe_config->fdi_lanes = lane;
6502
6503 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6504 link_bw, &pipe_config->fdi_m_n);
6505
6506 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6507 intel_crtc->pipe, pipe_config);
6508 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6509 pipe_config->pipe_bpp -= 2*3;
6510 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6511 pipe_config->pipe_bpp);
6512 needs_recompute = true;
6513 pipe_config->bw_constrained = true;
6514
6515 goto retry;
6516 }
6517
6518 if (needs_recompute)
6519 return RETRY;
6520
6521 return ret;
6522 }
6523
6524 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6525 struct intel_crtc_state *pipe_config)
6526 {
6527 if (pipe_config->pipe_bpp > 24)
6528 return false;
6529
6530 /* HSW can handle pixel rate up to cdclk? */
6531 if (IS_HASWELL(dev_priv->dev))
6532 return true;
6533
6534 /*
6535 * We compare against max which means we must take
6536 * the increased cdclk requirement into account when
6537 * calculating the new cdclk.
6538 *
6539 * Should measure whether using a lower cdclk w/o IPS
6540 */
6541 return ilk_pipe_pixel_rate(pipe_config) <=
6542 dev_priv->max_cdclk_freq * 95 / 100;
6543 }
6544
6545 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6546 struct intel_crtc_state *pipe_config)
6547 {
6548 struct drm_device *dev = crtc->base.dev;
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6550
6551 pipe_config->ips_enabled = i915.enable_ips &&
6552 hsw_crtc_supports_ips(crtc) &&
6553 pipe_config_supports_ips(dev_priv, pipe_config);
6554 }
6555
6556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6557 struct intel_crtc_state *pipe_config)
6558 {
6559 struct drm_device *dev = crtc->base.dev;
6560 struct drm_i915_private *dev_priv = dev->dev_private;
6561 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6562
6563 /* FIXME should check pixel clock limits on all platforms */
6564 if (INTEL_INFO(dev)->gen < 4) {
6565 int clock_limit = dev_priv->max_cdclk_freq;
6566
6567 /*
6568 * Enable pixel doubling when the dot clock
6569 * is > 90% of the (display) core speed.
6570 *
6571 * GDG double wide on either pipe,
6572 * otherwise pipe A only.
6573 */
6574 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6575 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6576 clock_limit *= 2;
6577 pipe_config->double_wide = true;
6578 }
6579
6580 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6581 return -EINVAL;
6582 }
6583
6584 /*
6585 * Pipe horizontal size must be even in:
6586 * - DVO ganged mode
6587 * - LVDS dual channel mode
6588 * - Double wide pipe
6589 */
6590 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6591 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6592 pipe_config->pipe_src_w &= ~1;
6593
6594 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6595 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6596 */
6597 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6598 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6599 return -EINVAL;
6600
6601 if (HAS_IPS(dev))
6602 hsw_compute_ips_config(crtc, pipe_config);
6603
6604 if (pipe_config->has_pch_encoder)
6605 return ironlake_fdi_compute_config(crtc, pipe_config);
6606
6607 return 0;
6608 }
6609
6610 static int skylake_get_display_clock_speed(struct drm_device *dev)
6611 {
6612 struct drm_i915_private *dev_priv = to_i915(dev);
6613 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6614 uint32_t cdctl = I915_READ(CDCLK_CTL);
6615 uint32_t linkrate;
6616
6617 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6618 return 24000; /* 24MHz is the cd freq with NSSC ref */
6619
6620 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6621 return 540000;
6622
6623 linkrate = (I915_READ(DPLL_CTRL1) &
6624 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6625
6626 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6627 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6628 /* vco 8640 */
6629 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6630 case CDCLK_FREQ_450_432:
6631 return 432000;
6632 case CDCLK_FREQ_337_308:
6633 return 308570;
6634 case CDCLK_FREQ_675_617:
6635 return 617140;
6636 default:
6637 WARN(1, "Unknown cd freq selection\n");
6638 }
6639 } else {
6640 /* vco 8100 */
6641 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6642 case CDCLK_FREQ_450_432:
6643 return 450000;
6644 case CDCLK_FREQ_337_308:
6645 return 337500;
6646 case CDCLK_FREQ_675_617:
6647 return 675000;
6648 default:
6649 WARN(1, "Unknown cd freq selection\n");
6650 }
6651 }
6652
6653 /* error case, do as if DPLL0 isn't enabled */
6654 return 24000;
6655 }
6656
6657 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6658 {
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6660 uint32_t lcpll = I915_READ(LCPLL_CTL);
6661 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6662
6663 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6664 return 800000;
6665 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6666 return 450000;
6667 else if (freq == LCPLL_CLK_FREQ_450)
6668 return 450000;
6669 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6670 return 540000;
6671 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6672 return 337500;
6673 else
6674 return 675000;
6675 }
6676
6677 static int haswell_get_display_clock_speed(struct drm_device *dev)
6678 {
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6680 uint32_t lcpll = I915_READ(LCPLL_CTL);
6681 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6682
6683 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6684 return 800000;
6685 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6686 return 450000;
6687 else if (freq == LCPLL_CLK_FREQ_450)
6688 return 450000;
6689 else if (IS_HSW_ULT(dev))
6690 return 337500;
6691 else
6692 return 540000;
6693 }
6694
6695 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6696 {
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 u32 val;
6699 int divider;
6700
6701 if (dev_priv->hpll_freq == 0)
6702 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6703
6704 mutex_lock(&dev_priv->sb_lock);
6705 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6706 mutex_unlock(&dev_priv->sb_lock);
6707
6708 divider = val & DISPLAY_FREQUENCY_VALUES;
6709
6710 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6711 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6712 "cdclk change in progress\n");
6713
6714 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6715 }
6716
6717 static int ilk_get_display_clock_speed(struct drm_device *dev)
6718 {
6719 return 450000;
6720 }
6721
6722 static int i945_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 return 400000;
6725 }
6726
6727 static int i915_get_display_clock_speed(struct drm_device *dev)
6728 {
6729 return 333333;
6730 }
6731
6732 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6733 {
6734 return 200000;
6735 }
6736
6737 static int pnv_get_display_clock_speed(struct drm_device *dev)
6738 {
6739 u16 gcfgc = 0;
6740
6741 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6742
6743 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6744 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6745 return 266667;
6746 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6747 return 333333;
6748 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6749 return 444444;
6750 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6751 return 200000;
6752 default:
6753 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6754 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6755 return 133333;
6756 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6757 return 166667;
6758 }
6759 }
6760
6761 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6762 {
6763 u16 gcfgc = 0;
6764
6765 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6766
6767 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6768 return 133333;
6769 else {
6770 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6771 case GC_DISPLAY_CLOCK_333_MHZ:
6772 return 333333;
6773 default:
6774 case GC_DISPLAY_CLOCK_190_200_MHZ:
6775 return 190000;
6776 }
6777 }
6778 }
6779
6780 static int i865_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 return 266667;
6783 }
6784
6785 static int i85x_get_display_clock_speed(struct drm_device *dev)
6786 {
6787 u16 hpllcc = 0;
6788
6789 /*
6790 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6791 * encoding is different :(
6792 * FIXME is this the right way to detect 852GM/852GMV?
6793 */
6794 if (dev->pdev->revision == 0x1)
6795 return 133333;
6796
6797 pci_bus_read_config_word(dev->pdev->bus,
6798 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6799
6800 /* Assume that the hardware is in the high speed state. This
6801 * should be the default.
6802 */
6803 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6804 case GC_CLOCK_133_200:
6805 case GC_CLOCK_133_200_2:
6806 case GC_CLOCK_100_200:
6807 return 200000;
6808 case GC_CLOCK_166_250:
6809 return 250000;
6810 case GC_CLOCK_100_133:
6811 return 133333;
6812 case GC_CLOCK_133_266:
6813 case GC_CLOCK_133_266_2:
6814 case GC_CLOCK_166_266:
6815 return 266667;
6816 }
6817
6818 /* Shouldn't happen */
6819 return 0;
6820 }
6821
6822 static int i830_get_display_clock_speed(struct drm_device *dev)
6823 {
6824 return 133333;
6825 }
6826
6827 static unsigned int intel_hpll_vco(struct drm_device *dev)
6828 {
6829 struct drm_i915_private *dev_priv = dev->dev_private;
6830 static const unsigned int blb_vco[8] = {
6831 [0] = 3200000,
6832 [1] = 4000000,
6833 [2] = 5333333,
6834 [3] = 4800000,
6835 [4] = 6400000,
6836 };
6837 static const unsigned int pnv_vco[8] = {
6838 [0] = 3200000,
6839 [1] = 4000000,
6840 [2] = 5333333,
6841 [3] = 4800000,
6842 [4] = 2666667,
6843 };
6844 static const unsigned int cl_vco[8] = {
6845 [0] = 3200000,
6846 [1] = 4000000,
6847 [2] = 5333333,
6848 [3] = 6400000,
6849 [4] = 3333333,
6850 [5] = 3566667,
6851 [6] = 4266667,
6852 };
6853 static const unsigned int elk_vco[8] = {
6854 [0] = 3200000,
6855 [1] = 4000000,
6856 [2] = 5333333,
6857 [3] = 4800000,
6858 };
6859 static const unsigned int ctg_vco[8] = {
6860 [0] = 3200000,
6861 [1] = 4000000,
6862 [2] = 5333333,
6863 [3] = 6400000,
6864 [4] = 2666667,
6865 [5] = 4266667,
6866 };
6867 const unsigned int *vco_table;
6868 unsigned int vco;
6869 uint8_t tmp = 0;
6870
6871 /* FIXME other chipsets? */
6872 if (IS_GM45(dev))
6873 vco_table = ctg_vco;
6874 else if (IS_G4X(dev))
6875 vco_table = elk_vco;
6876 else if (IS_CRESTLINE(dev))
6877 vco_table = cl_vco;
6878 else if (IS_PINEVIEW(dev))
6879 vco_table = pnv_vco;
6880 else if (IS_G33(dev))
6881 vco_table = blb_vco;
6882 else
6883 return 0;
6884
6885 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6886
6887 vco = vco_table[tmp & 0x7];
6888 if (vco == 0)
6889 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6890 else
6891 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6892
6893 return vco;
6894 }
6895
6896 static int gm45_get_display_clock_speed(struct drm_device *dev)
6897 {
6898 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6899 uint16_t tmp = 0;
6900
6901 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6902
6903 cdclk_sel = (tmp >> 12) & 0x1;
6904
6905 switch (vco) {
6906 case 2666667:
6907 case 4000000:
6908 case 5333333:
6909 return cdclk_sel ? 333333 : 222222;
6910 case 3200000:
6911 return cdclk_sel ? 320000 : 228571;
6912 default:
6913 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6914 return 222222;
6915 }
6916 }
6917
6918 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6919 {
6920 static const uint8_t div_3200[] = { 16, 10, 8 };
6921 static const uint8_t div_4000[] = { 20, 12, 10 };
6922 static const uint8_t div_5333[] = { 24, 16, 14 };
6923 const uint8_t *div_table;
6924 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6925 uint16_t tmp = 0;
6926
6927 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6928
6929 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6930
6931 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6932 goto fail;
6933
6934 switch (vco) {
6935 case 3200000:
6936 div_table = div_3200;
6937 break;
6938 case 4000000:
6939 div_table = div_4000;
6940 break;
6941 case 5333333:
6942 div_table = div_5333;
6943 break;
6944 default:
6945 goto fail;
6946 }
6947
6948 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6949
6950 fail:
6951 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6952 return 200000;
6953 }
6954
6955 static int g33_get_display_clock_speed(struct drm_device *dev)
6956 {
6957 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6958 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6959 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6960 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6961 const uint8_t *div_table;
6962 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6963 uint16_t tmp = 0;
6964
6965 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6966
6967 cdclk_sel = (tmp >> 4) & 0x7;
6968
6969 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6970 goto fail;
6971
6972 switch (vco) {
6973 case 3200000:
6974 div_table = div_3200;
6975 break;
6976 case 4000000:
6977 div_table = div_4000;
6978 break;
6979 case 4800000:
6980 div_table = div_4800;
6981 break;
6982 case 5333333:
6983 div_table = div_5333;
6984 break;
6985 default:
6986 goto fail;
6987 }
6988
6989 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6990
6991 fail:
6992 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6993 return 190476;
6994 }
6995
6996 static void
6997 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6998 {
6999 while (*num > DATA_LINK_M_N_MASK ||
7000 *den > DATA_LINK_M_N_MASK) {
7001 *num >>= 1;
7002 *den >>= 1;
7003 }
7004 }
7005
7006 static void compute_m_n(unsigned int m, unsigned int n,
7007 uint32_t *ret_m, uint32_t *ret_n)
7008 {
7009 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7010 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7011 intel_reduce_m_n_ratio(ret_m, ret_n);
7012 }
7013
7014 void
7015 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7016 int pixel_clock, int link_clock,
7017 struct intel_link_m_n *m_n)
7018 {
7019 m_n->tu = 64;
7020
7021 compute_m_n(bits_per_pixel * pixel_clock,
7022 link_clock * nlanes * 8,
7023 &m_n->gmch_m, &m_n->gmch_n);
7024
7025 compute_m_n(pixel_clock, link_clock,
7026 &m_n->link_m, &m_n->link_n);
7027 }
7028
7029 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7030 {
7031 if (i915.panel_use_ssc >= 0)
7032 return i915.panel_use_ssc != 0;
7033 return dev_priv->vbt.lvds_use_ssc
7034 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7035 }
7036
7037 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7038 int num_connectors)
7039 {
7040 struct drm_device *dev = crtc_state->base.crtc->dev;
7041 struct drm_i915_private *dev_priv = dev->dev_private;
7042 int refclk;
7043
7044 WARN_ON(!crtc_state->base.state);
7045
7046 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7047 refclk = 100000;
7048 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7049 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7050 refclk = dev_priv->vbt.lvds_ssc_freq;
7051 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7052 } else if (!IS_GEN2(dev)) {
7053 refclk = 96000;
7054 } else {
7055 refclk = 48000;
7056 }
7057
7058 return refclk;
7059 }
7060
7061 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7062 {
7063 return (1 << dpll->n) << 16 | dpll->m2;
7064 }
7065
7066 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7067 {
7068 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7069 }
7070
7071 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7072 struct intel_crtc_state *crtc_state,
7073 intel_clock_t *reduced_clock)
7074 {
7075 struct drm_device *dev = crtc->base.dev;
7076 u32 fp, fp2 = 0;
7077
7078 if (IS_PINEVIEW(dev)) {
7079 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7080 if (reduced_clock)
7081 fp2 = pnv_dpll_compute_fp(reduced_clock);
7082 } else {
7083 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7084 if (reduced_clock)
7085 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7086 }
7087
7088 crtc_state->dpll_hw_state.fp0 = fp;
7089
7090 crtc->lowfreq_avail = false;
7091 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7092 reduced_clock) {
7093 crtc_state->dpll_hw_state.fp1 = fp2;
7094 crtc->lowfreq_avail = true;
7095 } else {
7096 crtc_state->dpll_hw_state.fp1 = fp;
7097 }
7098 }
7099
7100 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7101 pipe)
7102 {
7103 u32 reg_val;
7104
7105 /*
7106 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7107 * and set it to a reasonable value instead.
7108 */
7109 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7110 reg_val &= 0xffffff00;
7111 reg_val |= 0x00000030;
7112 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7113
7114 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7115 reg_val &= 0x8cffffff;
7116 reg_val = 0x8c000000;
7117 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7118
7119 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7120 reg_val &= 0xffffff00;
7121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7122
7123 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7124 reg_val &= 0x00ffffff;
7125 reg_val |= 0xb0000000;
7126 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7127 }
7128
7129 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7130 struct intel_link_m_n *m_n)
7131 {
7132 struct drm_device *dev = crtc->base.dev;
7133 struct drm_i915_private *dev_priv = dev->dev_private;
7134 int pipe = crtc->pipe;
7135
7136 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7137 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7138 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7139 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7140 }
7141
7142 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7143 struct intel_link_m_n *m_n,
7144 struct intel_link_m_n *m2_n2)
7145 {
7146 struct drm_device *dev = crtc->base.dev;
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 int pipe = crtc->pipe;
7149 enum transcoder transcoder = crtc->config->cpu_transcoder;
7150
7151 if (INTEL_INFO(dev)->gen >= 5) {
7152 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7153 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7154 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7155 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7156 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7157 * for gen < 8) and if DRRS is supported (to make sure the
7158 * registers are not unnecessarily accessed).
7159 */
7160 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7161 crtc->config->has_drrs) {
7162 I915_WRITE(PIPE_DATA_M2(transcoder),
7163 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7164 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7165 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7166 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7167 }
7168 } else {
7169 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7170 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7171 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7172 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7173 }
7174 }
7175
7176 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7177 {
7178 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7179
7180 if (m_n == M1_N1) {
7181 dp_m_n = &crtc->config->dp_m_n;
7182 dp_m2_n2 = &crtc->config->dp_m2_n2;
7183 } else if (m_n == M2_N2) {
7184
7185 /*
7186 * M2_N2 registers are not supported. Hence m2_n2 divider value
7187 * needs to be programmed into M1_N1.
7188 */
7189 dp_m_n = &crtc->config->dp_m2_n2;
7190 } else {
7191 DRM_ERROR("Unsupported divider value\n");
7192 return;
7193 }
7194
7195 if (crtc->config->has_pch_encoder)
7196 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7197 else
7198 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7199 }
7200
7201 static void vlv_update_pll(struct intel_crtc *crtc,
7202 struct intel_crtc_state *pipe_config)
7203 {
7204 u32 dpll, dpll_md;
7205
7206 /*
7207 * Enable DPIO clock input. We should never disable the reference
7208 * clock for pipe B, since VGA hotplug / manual detection depends
7209 * on it.
7210 */
7211 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7212 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7213 /* We should never disable this, set it here for state tracking */
7214 if (crtc->pipe == PIPE_B)
7215 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7216 dpll |= DPLL_VCO_ENABLE;
7217 pipe_config->dpll_hw_state.dpll = dpll;
7218
7219 dpll_md = (pipe_config->pixel_multiplier - 1)
7220 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7221 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7222 }
7223
7224 static void vlv_prepare_pll(struct intel_crtc *crtc,
7225 const struct intel_crtc_state *pipe_config)
7226 {
7227 struct drm_device *dev = crtc->base.dev;
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 int pipe = crtc->pipe;
7230 u32 mdiv;
7231 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7232 u32 coreclk, reg_val;
7233
7234 mutex_lock(&dev_priv->sb_lock);
7235
7236 bestn = pipe_config->dpll.n;
7237 bestm1 = pipe_config->dpll.m1;
7238 bestm2 = pipe_config->dpll.m2;
7239 bestp1 = pipe_config->dpll.p1;
7240 bestp2 = pipe_config->dpll.p2;
7241
7242 /* See eDP HDMI DPIO driver vbios notes doc */
7243
7244 /* PLL B needs special handling */
7245 if (pipe == PIPE_B)
7246 vlv_pllb_recal_opamp(dev_priv, pipe);
7247
7248 /* Set up Tx target for periodic Rcomp update */
7249 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7250
7251 /* Disable target IRef on PLL */
7252 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7253 reg_val &= 0x00ffffff;
7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7255
7256 /* Disable fast lock */
7257 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7258
7259 /* Set idtafcrecal before PLL is enabled */
7260 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7261 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7262 mdiv |= ((bestn << DPIO_N_SHIFT));
7263 mdiv |= (1 << DPIO_K_SHIFT);
7264
7265 /*
7266 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7267 * but we don't support that).
7268 * Note: don't use the DAC post divider as it seems unstable.
7269 */
7270 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7271 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7272
7273 mdiv |= DPIO_ENABLE_CALIBRATION;
7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7275
7276 /* Set HBR and RBR LPF coefficients */
7277 if (pipe_config->port_clock == 162000 ||
7278 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7279 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7281 0x009f0003);
7282 else
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7284 0x00d0000f);
7285
7286 if (pipe_config->has_dp_encoder) {
7287 /* Use SSC source */
7288 if (pipe == PIPE_A)
7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7290 0x0df40000);
7291 else
7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7293 0x0df70000);
7294 } else { /* HDMI or VGA */
7295 /* Use bend source */
7296 if (pipe == PIPE_A)
7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298 0x0df70000);
7299 else
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7301 0x0df40000);
7302 }
7303
7304 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7305 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7306 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7307 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7308 coreclk |= 0x01000000;
7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7310
7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7312 mutex_unlock(&dev_priv->sb_lock);
7313 }
7314
7315 static void chv_update_pll(struct intel_crtc *crtc,
7316 struct intel_crtc_state *pipe_config)
7317 {
7318 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7319 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7320 DPLL_VCO_ENABLE;
7321 if (crtc->pipe != PIPE_A)
7322 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7323
7324 pipe_config->dpll_hw_state.dpll_md =
7325 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7326 }
7327
7328 static void chv_prepare_pll(struct intel_crtc *crtc,
7329 const struct intel_crtc_state *pipe_config)
7330 {
7331 struct drm_device *dev = crtc->base.dev;
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 int pipe = crtc->pipe;
7334 int dpll_reg = DPLL(crtc->pipe);
7335 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7336 u32 loopfilter, tribuf_calcntr;
7337 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7338 u32 dpio_val;
7339 int vco;
7340
7341 bestn = pipe_config->dpll.n;
7342 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7343 bestm1 = pipe_config->dpll.m1;
7344 bestm2 = pipe_config->dpll.m2 >> 22;
7345 bestp1 = pipe_config->dpll.p1;
7346 bestp2 = pipe_config->dpll.p2;
7347 vco = pipe_config->dpll.vco;
7348 dpio_val = 0;
7349 loopfilter = 0;
7350
7351 /*
7352 * Enable Refclk and SSC
7353 */
7354 I915_WRITE(dpll_reg,
7355 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7356
7357 mutex_lock(&dev_priv->sb_lock);
7358
7359 /* p1 and p2 divider */
7360 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7361 5 << DPIO_CHV_S1_DIV_SHIFT |
7362 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7363 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7364 1 << DPIO_CHV_K_DIV_SHIFT);
7365
7366 /* Feedback post-divider - m2 */
7367 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7368
7369 /* Feedback refclk divider - n and m1 */
7370 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7371 DPIO_CHV_M1_DIV_BY_2 |
7372 1 << DPIO_CHV_N_DIV_SHIFT);
7373
7374 /* M2 fraction division */
7375 if (bestm2_frac)
7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7377
7378 /* M2 fraction division enable */
7379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7380 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7381 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7382 if (bestm2_frac)
7383 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7385
7386 /* Program digital lock detect threshold */
7387 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7388 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7389 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7390 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7391 if (!bestm2_frac)
7392 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7393 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7394
7395 /* Loop filter */
7396 if (vco == 5400000) {
7397 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x9;
7401 } else if (vco <= 6200000) {
7402 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x9;
7406 } else if (vco <= 6480000) {
7407 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7408 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7409 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410 tribuf_calcntr = 0x8;
7411 } else {
7412 /* Not supported. Apply the same limits as in the max case */
7413 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7414 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7415 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7416 tribuf_calcntr = 0;
7417 }
7418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7419
7420 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7421 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7422 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7424
7425 /* AFC Recal */
7426 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7427 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7428 DPIO_AFC_RECAL);
7429
7430 mutex_unlock(&dev_priv->sb_lock);
7431 }
7432
7433 /**
7434 * vlv_force_pll_on - forcibly enable just the PLL
7435 * @dev_priv: i915 private structure
7436 * @pipe: pipe PLL to enable
7437 * @dpll: PLL configuration
7438 *
7439 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7440 * in cases where we need the PLL enabled even when @pipe is not going to
7441 * be enabled.
7442 */
7443 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7444 const struct dpll *dpll)
7445 {
7446 struct intel_crtc *crtc =
7447 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7448 struct intel_crtc_state pipe_config = {
7449 .base.crtc = &crtc->base,
7450 .pixel_multiplier = 1,
7451 .dpll = *dpll,
7452 };
7453
7454 if (IS_CHERRYVIEW(dev)) {
7455 chv_update_pll(crtc, &pipe_config);
7456 chv_prepare_pll(crtc, &pipe_config);
7457 chv_enable_pll(crtc, &pipe_config);
7458 } else {
7459 vlv_update_pll(crtc, &pipe_config);
7460 vlv_prepare_pll(crtc, &pipe_config);
7461 vlv_enable_pll(crtc, &pipe_config);
7462 }
7463 }
7464
7465 /**
7466 * vlv_force_pll_off - forcibly disable just the PLL
7467 * @dev_priv: i915 private structure
7468 * @pipe: pipe PLL to disable
7469 *
7470 * Disable the PLL for @pipe. To be used in cases where we need
7471 * the PLL enabled even when @pipe is not going to be enabled.
7472 */
7473 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7474 {
7475 if (IS_CHERRYVIEW(dev))
7476 chv_disable_pll(to_i915(dev), pipe);
7477 else
7478 vlv_disable_pll(to_i915(dev), pipe);
7479 }
7480
7481 static void i9xx_update_pll(struct intel_crtc *crtc,
7482 struct intel_crtc_state *crtc_state,
7483 intel_clock_t *reduced_clock,
7484 int num_connectors)
7485 {
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 u32 dpll;
7489 bool is_sdvo;
7490 struct dpll *clock = &crtc_state->dpll;
7491
7492 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7493
7494 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7495 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7496
7497 dpll = DPLL_VGA_MODE_DIS;
7498
7499 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7500 dpll |= DPLLB_MODE_LVDS;
7501 else
7502 dpll |= DPLLB_MODE_DAC_SERIAL;
7503
7504 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7505 dpll |= (crtc_state->pixel_multiplier - 1)
7506 << SDVO_MULTIPLIER_SHIFT_HIRES;
7507 }
7508
7509 if (is_sdvo)
7510 dpll |= DPLL_SDVO_HIGH_SPEED;
7511
7512 if (crtc_state->has_dp_encoder)
7513 dpll |= DPLL_SDVO_HIGH_SPEED;
7514
7515 /* compute bitmask from p1 value */
7516 if (IS_PINEVIEW(dev))
7517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7518 else {
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7520 if (IS_G4X(dev) && reduced_clock)
7521 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7522 }
7523 switch (clock->p2) {
7524 case 5:
7525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7526 break;
7527 case 7:
7528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7529 break;
7530 case 10:
7531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7532 break;
7533 case 14:
7534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7535 break;
7536 }
7537 if (INTEL_INFO(dev)->gen >= 4)
7538 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7539
7540 if (crtc_state->sdvo_tv_clock)
7541 dpll |= PLL_REF_INPUT_TVCLKINBC;
7542 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7543 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7545 else
7546 dpll |= PLL_REF_INPUT_DREFCLK;
7547
7548 dpll |= DPLL_VCO_ENABLE;
7549 crtc_state->dpll_hw_state.dpll = dpll;
7550
7551 if (INTEL_INFO(dev)->gen >= 4) {
7552 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7553 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7554 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7555 }
7556 }
7557
7558 static void i8xx_update_pll(struct intel_crtc *crtc,
7559 struct intel_crtc_state *crtc_state,
7560 intel_clock_t *reduced_clock,
7561 int num_connectors)
7562 {
7563 struct drm_device *dev = crtc->base.dev;
7564 struct drm_i915_private *dev_priv = dev->dev_private;
7565 u32 dpll;
7566 struct dpll *clock = &crtc_state->dpll;
7567
7568 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7569
7570 dpll = DPLL_VGA_MODE_DIS;
7571
7572 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7573 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7574 } else {
7575 if (clock->p1 == 2)
7576 dpll |= PLL_P1_DIVIDE_BY_TWO;
7577 else
7578 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579 if (clock->p2 == 4)
7580 dpll |= PLL_P2_DIVIDE_BY_4;
7581 }
7582
7583 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7584 dpll |= DPLL_DVO_2X_MODE;
7585
7586 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7589 else
7590 dpll |= PLL_REF_INPUT_DREFCLK;
7591
7592 dpll |= DPLL_VCO_ENABLE;
7593 crtc_state->dpll_hw_state.dpll = dpll;
7594 }
7595
7596 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7597 {
7598 struct drm_device *dev = intel_crtc->base.dev;
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 enum pipe pipe = intel_crtc->pipe;
7601 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7602 struct drm_display_mode *adjusted_mode =
7603 &intel_crtc->config->base.adjusted_mode;
7604 uint32_t crtc_vtotal, crtc_vblank_end;
7605 int vsyncshift = 0;
7606
7607 /* We need to be careful not to changed the adjusted mode, for otherwise
7608 * the hw state checker will get angry at the mismatch. */
7609 crtc_vtotal = adjusted_mode->crtc_vtotal;
7610 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7611
7612 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7613 /* the chip adds 2 halflines automatically */
7614 crtc_vtotal -= 1;
7615 crtc_vblank_end -= 1;
7616
7617 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7618 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7619 else
7620 vsyncshift = adjusted_mode->crtc_hsync_start -
7621 adjusted_mode->crtc_htotal / 2;
7622 if (vsyncshift < 0)
7623 vsyncshift += adjusted_mode->crtc_htotal;
7624 }
7625
7626 if (INTEL_INFO(dev)->gen > 3)
7627 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7628
7629 I915_WRITE(HTOTAL(cpu_transcoder),
7630 (adjusted_mode->crtc_hdisplay - 1) |
7631 ((adjusted_mode->crtc_htotal - 1) << 16));
7632 I915_WRITE(HBLANK(cpu_transcoder),
7633 (adjusted_mode->crtc_hblank_start - 1) |
7634 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7635 I915_WRITE(HSYNC(cpu_transcoder),
7636 (adjusted_mode->crtc_hsync_start - 1) |
7637 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7638
7639 I915_WRITE(VTOTAL(cpu_transcoder),
7640 (adjusted_mode->crtc_vdisplay - 1) |
7641 ((crtc_vtotal - 1) << 16));
7642 I915_WRITE(VBLANK(cpu_transcoder),
7643 (adjusted_mode->crtc_vblank_start - 1) |
7644 ((crtc_vblank_end - 1) << 16));
7645 I915_WRITE(VSYNC(cpu_transcoder),
7646 (adjusted_mode->crtc_vsync_start - 1) |
7647 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7648
7649 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7650 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7651 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7652 * bits. */
7653 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7654 (pipe == PIPE_B || pipe == PIPE_C))
7655 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7656
7657 /* pipesrc controls the size that is scaled from, which should
7658 * always be the user's requested size.
7659 */
7660 I915_WRITE(PIPESRC(pipe),
7661 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7662 (intel_crtc->config->pipe_src_h - 1));
7663 }
7664
7665 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7666 struct intel_crtc_state *pipe_config)
7667 {
7668 struct drm_device *dev = crtc->base.dev;
7669 struct drm_i915_private *dev_priv = dev->dev_private;
7670 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7671 uint32_t tmp;
7672
7673 tmp = I915_READ(HTOTAL(cpu_transcoder));
7674 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7675 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7676 tmp = I915_READ(HBLANK(cpu_transcoder));
7677 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7678 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7679 tmp = I915_READ(HSYNC(cpu_transcoder));
7680 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7681 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7682
7683 tmp = I915_READ(VTOTAL(cpu_transcoder));
7684 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7686 tmp = I915_READ(VBLANK(cpu_transcoder));
7687 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7689 tmp = I915_READ(VSYNC(cpu_transcoder));
7690 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7692
7693 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7694 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7695 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7696 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7697 }
7698
7699 tmp = I915_READ(PIPESRC(crtc->pipe));
7700 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7701 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7702
7703 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7704 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7705 }
7706
7707 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7708 struct intel_crtc_state *pipe_config)
7709 {
7710 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7711 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7712 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7713 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7714
7715 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7716 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7717 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7718 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7719
7720 mode->flags = pipe_config->base.adjusted_mode.flags;
7721
7722 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7723 mode->flags |= pipe_config->base.adjusted_mode.flags;
7724 }
7725
7726 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7727 {
7728 struct drm_device *dev = intel_crtc->base.dev;
7729 struct drm_i915_private *dev_priv = dev->dev_private;
7730 uint32_t pipeconf;
7731
7732 pipeconf = 0;
7733
7734 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7735 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7736 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7737
7738 if (intel_crtc->config->double_wide)
7739 pipeconf |= PIPECONF_DOUBLE_WIDE;
7740
7741 /* only g4x and later have fancy bpc/dither controls */
7742 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7743 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7744 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7745 pipeconf |= PIPECONF_DITHER_EN |
7746 PIPECONF_DITHER_TYPE_SP;
7747
7748 switch (intel_crtc->config->pipe_bpp) {
7749 case 18:
7750 pipeconf |= PIPECONF_6BPC;
7751 break;
7752 case 24:
7753 pipeconf |= PIPECONF_8BPC;
7754 break;
7755 case 30:
7756 pipeconf |= PIPECONF_10BPC;
7757 break;
7758 default:
7759 /* Case prevented by intel_choose_pipe_bpp_dither. */
7760 BUG();
7761 }
7762 }
7763
7764 if (HAS_PIPE_CXSR(dev)) {
7765 if (intel_crtc->lowfreq_avail) {
7766 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7767 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7768 } else {
7769 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7770 }
7771 }
7772
7773 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7774 if (INTEL_INFO(dev)->gen < 4 ||
7775 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7776 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7777 else
7778 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7779 } else
7780 pipeconf |= PIPECONF_PROGRESSIVE;
7781
7782 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7783 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7784
7785 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7786 POSTING_READ(PIPECONF(intel_crtc->pipe));
7787 }
7788
7789 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7790 struct intel_crtc_state *crtc_state)
7791 {
7792 struct drm_device *dev = crtc->base.dev;
7793 struct drm_i915_private *dev_priv = dev->dev_private;
7794 int refclk, num_connectors = 0;
7795 intel_clock_t clock, reduced_clock;
7796 bool ok, has_reduced_clock = false;
7797 bool is_lvds = false, is_dsi = false;
7798 struct intel_encoder *encoder;
7799 const intel_limit_t *limit;
7800 struct drm_atomic_state *state = crtc_state->base.state;
7801 struct drm_connector *connector;
7802 struct drm_connector_state *connector_state;
7803 int i;
7804
7805 memset(&crtc_state->dpll_hw_state, 0,
7806 sizeof(crtc_state->dpll_hw_state));
7807
7808 for_each_connector_in_state(state, connector, connector_state, i) {
7809 if (connector_state->crtc != &crtc->base)
7810 continue;
7811
7812 encoder = to_intel_encoder(connector_state->best_encoder);
7813
7814 switch (encoder->type) {
7815 case INTEL_OUTPUT_LVDS:
7816 is_lvds = true;
7817 break;
7818 case INTEL_OUTPUT_DSI:
7819 is_dsi = true;
7820 break;
7821 default:
7822 break;
7823 }
7824
7825 num_connectors++;
7826 }
7827
7828 if (is_dsi)
7829 return 0;
7830
7831 if (!crtc_state->clock_set) {
7832 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7833
7834 /*
7835 * Returns a set of divisors for the desired target clock with
7836 * the given refclk, or FALSE. The returned values represent
7837 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7838 * 2) / p1 / p2.
7839 */
7840 limit = intel_limit(crtc_state, refclk);
7841 ok = dev_priv->display.find_dpll(limit, crtc_state,
7842 crtc_state->port_clock,
7843 refclk, NULL, &clock);
7844 if (!ok) {
7845 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7846 return -EINVAL;
7847 }
7848
7849 if (is_lvds && dev_priv->lvds_downclock_avail) {
7850 /*
7851 * Ensure we match the reduced clock's P to the target
7852 * clock. If the clocks don't match, we can't switch
7853 * the display clock by using the FP0/FP1. In such case
7854 * we will disable the LVDS downclock feature.
7855 */
7856 has_reduced_clock =
7857 dev_priv->display.find_dpll(limit, crtc_state,
7858 dev_priv->lvds_downclock,
7859 refclk, &clock,
7860 &reduced_clock);
7861 }
7862 /* Compat-code for transition, will disappear. */
7863 crtc_state->dpll.n = clock.n;
7864 crtc_state->dpll.m1 = clock.m1;
7865 crtc_state->dpll.m2 = clock.m2;
7866 crtc_state->dpll.p1 = clock.p1;
7867 crtc_state->dpll.p2 = clock.p2;
7868 }
7869
7870 if (IS_GEN2(dev)) {
7871 i8xx_update_pll(crtc, crtc_state,
7872 has_reduced_clock ? &reduced_clock : NULL,
7873 num_connectors);
7874 } else if (IS_CHERRYVIEW(dev)) {
7875 chv_update_pll(crtc, crtc_state);
7876 } else if (IS_VALLEYVIEW(dev)) {
7877 vlv_update_pll(crtc, crtc_state);
7878 } else {
7879 i9xx_update_pll(crtc, crtc_state,
7880 has_reduced_clock ? &reduced_clock : NULL,
7881 num_connectors);
7882 }
7883
7884 return 0;
7885 }
7886
7887 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7888 struct intel_crtc_state *pipe_config)
7889 {
7890 struct drm_device *dev = crtc->base.dev;
7891 struct drm_i915_private *dev_priv = dev->dev_private;
7892 uint32_t tmp;
7893
7894 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7895 return;
7896
7897 tmp = I915_READ(PFIT_CONTROL);
7898 if (!(tmp & PFIT_ENABLE))
7899 return;
7900
7901 /* Check whether the pfit is attached to our pipe. */
7902 if (INTEL_INFO(dev)->gen < 4) {
7903 if (crtc->pipe != PIPE_B)
7904 return;
7905 } else {
7906 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7907 return;
7908 }
7909
7910 pipe_config->gmch_pfit.control = tmp;
7911 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7912 if (INTEL_INFO(dev)->gen < 5)
7913 pipe_config->gmch_pfit.lvds_border_bits =
7914 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7915 }
7916
7917 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7918 struct intel_crtc_state *pipe_config)
7919 {
7920 struct drm_device *dev = crtc->base.dev;
7921 struct drm_i915_private *dev_priv = dev->dev_private;
7922 int pipe = pipe_config->cpu_transcoder;
7923 intel_clock_t clock;
7924 u32 mdiv;
7925 int refclk = 100000;
7926
7927 /* In case of MIPI DPLL will not even be used */
7928 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7929 return;
7930
7931 mutex_lock(&dev_priv->sb_lock);
7932 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7933 mutex_unlock(&dev_priv->sb_lock);
7934
7935 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7936 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7937 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7938 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7939 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7940
7941 vlv_clock(refclk, &clock);
7942
7943 /* clock.dot is the fast clock */
7944 pipe_config->port_clock = clock.dot / 5;
7945 }
7946
7947 static void
7948 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7949 struct intel_initial_plane_config *plane_config)
7950 {
7951 struct drm_device *dev = crtc->base.dev;
7952 struct drm_i915_private *dev_priv = dev->dev_private;
7953 u32 val, base, offset;
7954 int pipe = crtc->pipe, plane = crtc->plane;
7955 int fourcc, pixel_format;
7956 unsigned int aligned_height;
7957 struct drm_framebuffer *fb;
7958 struct intel_framebuffer *intel_fb;
7959
7960 val = I915_READ(DSPCNTR(plane));
7961 if (!(val & DISPLAY_PLANE_ENABLE))
7962 return;
7963
7964 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7965 if (!intel_fb) {
7966 DRM_DEBUG_KMS("failed to alloc fb\n");
7967 return;
7968 }
7969
7970 fb = &intel_fb->base;
7971
7972 if (INTEL_INFO(dev)->gen >= 4) {
7973 if (val & DISPPLANE_TILED) {
7974 plane_config->tiling = I915_TILING_X;
7975 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7976 }
7977 }
7978
7979 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7980 fourcc = i9xx_format_to_fourcc(pixel_format);
7981 fb->pixel_format = fourcc;
7982 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7983
7984 if (INTEL_INFO(dev)->gen >= 4) {
7985 if (plane_config->tiling)
7986 offset = I915_READ(DSPTILEOFF(plane));
7987 else
7988 offset = I915_READ(DSPLINOFF(plane));
7989 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7990 } else {
7991 base = I915_READ(DSPADDR(plane));
7992 }
7993 plane_config->base = base;
7994
7995 val = I915_READ(PIPESRC(pipe));
7996 fb->width = ((val >> 16) & 0xfff) + 1;
7997 fb->height = ((val >> 0) & 0xfff) + 1;
7998
7999 val = I915_READ(DSPSTRIDE(pipe));
8000 fb->pitches[0] = val & 0xffffffc0;
8001
8002 aligned_height = intel_fb_align_height(dev, fb->height,
8003 fb->pixel_format,
8004 fb->modifier[0]);
8005
8006 plane_config->size = fb->pitches[0] * aligned_height;
8007
8008 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8009 pipe_name(pipe), plane, fb->width, fb->height,
8010 fb->bits_per_pixel, base, fb->pitches[0],
8011 plane_config->size);
8012
8013 plane_config->fb = intel_fb;
8014 }
8015
8016 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8017 struct intel_crtc_state *pipe_config)
8018 {
8019 struct drm_device *dev = crtc->base.dev;
8020 struct drm_i915_private *dev_priv = dev->dev_private;
8021 int pipe = pipe_config->cpu_transcoder;
8022 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8023 intel_clock_t clock;
8024 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8025 int refclk = 100000;
8026
8027 mutex_lock(&dev_priv->sb_lock);
8028 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8029 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8030 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8031 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8032 mutex_unlock(&dev_priv->sb_lock);
8033
8034 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8035 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8036 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8037 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8038 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8039
8040 chv_clock(refclk, &clock);
8041
8042 /* clock.dot is the fast clock */
8043 pipe_config->port_clock = clock.dot / 5;
8044 }
8045
8046 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8047 struct intel_crtc_state *pipe_config)
8048 {
8049 struct drm_device *dev = crtc->base.dev;
8050 struct drm_i915_private *dev_priv = dev->dev_private;
8051 uint32_t tmp;
8052
8053 if (!intel_display_power_is_enabled(dev_priv,
8054 POWER_DOMAIN_PIPE(crtc->pipe)))
8055 return false;
8056
8057 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8058 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8059
8060 tmp = I915_READ(PIPECONF(crtc->pipe));
8061 if (!(tmp & PIPECONF_ENABLE))
8062 return false;
8063
8064 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8065 switch (tmp & PIPECONF_BPC_MASK) {
8066 case PIPECONF_6BPC:
8067 pipe_config->pipe_bpp = 18;
8068 break;
8069 case PIPECONF_8BPC:
8070 pipe_config->pipe_bpp = 24;
8071 break;
8072 case PIPECONF_10BPC:
8073 pipe_config->pipe_bpp = 30;
8074 break;
8075 default:
8076 break;
8077 }
8078 }
8079
8080 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8081 pipe_config->limited_color_range = true;
8082
8083 if (INTEL_INFO(dev)->gen < 4)
8084 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8085
8086 intel_get_pipe_timings(crtc, pipe_config);
8087
8088 i9xx_get_pfit_config(crtc, pipe_config);
8089
8090 if (INTEL_INFO(dev)->gen >= 4) {
8091 tmp = I915_READ(DPLL_MD(crtc->pipe));
8092 pipe_config->pixel_multiplier =
8093 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8094 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8095 pipe_config->dpll_hw_state.dpll_md = tmp;
8096 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8097 tmp = I915_READ(DPLL(crtc->pipe));
8098 pipe_config->pixel_multiplier =
8099 ((tmp & SDVO_MULTIPLIER_MASK)
8100 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8101 } else {
8102 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8103 * port and will be fixed up in the encoder->get_config
8104 * function. */
8105 pipe_config->pixel_multiplier = 1;
8106 }
8107 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8108 if (!IS_VALLEYVIEW(dev)) {
8109 /*
8110 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8111 * on 830. Filter it out here so that we don't
8112 * report errors due to that.
8113 */
8114 if (IS_I830(dev))
8115 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8116
8117 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8118 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8119 } else {
8120 /* Mask out read-only status bits. */
8121 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8122 DPLL_PORTC_READY_MASK |
8123 DPLL_PORTB_READY_MASK);
8124 }
8125
8126 if (IS_CHERRYVIEW(dev))
8127 chv_crtc_clock_get(crtc, pipe_config);
8128 else if (IS_VALLEYVIEW(dev))
8129 vlv_crtc_clock_get(crtc, pipe_config);
8130 else
8131 i9xx_crtc_clock_get(crtc, pipe_config);
8132
8133 return true;
8134 }
8135
8136 static void ironlake_init_pch_refclk(struct drm_device *dev)
8137 {
8138 struct drm_i915_private *dev_priv = dev->dev_private;
8139 struct intel_encoder *encoder;
8140 u32 val, final;
8141 bool has_lvds = false;
8142 bool has_cpu_edp = false;
8143 bool has_panel = false;
8144 bool has_ck505 = false;
8145 bool can_ssc = false;
8146
8147 /* We need to take the global config into account */
8148 for_each_intel_encoder(dev, encoder) {
8149 switch (encoder->type) {
8150 case INTEL_OUTPUT_LVDS:
8151 has_panel = true;
8152 has_lvds = true;
8153 break;
8154 case INTEL_OUTPUT_EDP:
8155 has_panel = true;
8156 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8157 has_cpu_edp = true;
8158 break;
8159 default:
8160 break;
8161 }
8162 }
8163
8164 if (HAS_PCH_IBX(dev)) {
8165 has_ck505 = dev_priv->vbt.display_clock_mode;
8166 can_ssc = has_ck505;
8167 } else {
8168 has_ck505 = false;
8169 can_ssc = true;
8170 }
8171
8172 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8173 has_panel, has_lvds, has_ck505);
8174
8175 /* Ironlake: try to setup display ref clock before DPLL
8176 * enabling. This is only under driver's control after
8177 * PCH B stepping, previous chipset stepping should be
8178 * ignoring this setting.
8179 */
8180 val = I915_READ(PCH_DREF_CONTROL);
8181
8182 /* As we must carefully and slowly disable/enable each source in turn,
8183 * compute the final state we want first and check if we need to
8184 * make any changes at all.
8185 */
8186 final = val;
8187 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8188 if (has_ck505)
8189 final |= DREF_NONSPREAD_CK505_ENABLE;
8190 else
8191 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8192
8193 final &= ~DREF_SSC_SOURCE_MASK;
8194 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8195 final &= ~DREF_SSC1_ENABLE;
8196
8197 if (has_panel) {
8198 final |= DREF_SSC_SOURCE_ENABLE;
8199
8200 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8201 final |= DREF_SSC1_ENABLE;
8202
8203 if (has_cpu_edp) {
8204 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8205 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8206 else
8207 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8208 } else
8209 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8210 } else {
8211 final |= DREF_SSC_SOURCE_DISABLE;
8212 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8213 }
8214
8215 if (final == val)
8216 return;
8217
8218 /* Always enable nonspread source */
8219 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8220
8221 if (has_ck505)
8222 val |= DREF_NONSPREAD_CK505_ENABLE;
8223 else
8224 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8225
8226 if (has_panel) {
8227 val &= ~DREF_SSC_SOURCE_MASK;
8228 val |= DREF_SSC_SOURCE_ENABLE;
8229
8230 /* SSC must be turned on before enabling the CPU output */
8231 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8232 DRM_DEBUG_KMS("Using SSC on panel\n");
8233 val |= DREF_SSC1_ENABLE;
8234 } else
8235 val &= ~DREF_SSC1_ENABLE;
8236
8237 /* Get SSC going before enabling the outputs */
8238 I915_WRITE(PCH_DREF_CONTROL, val);
8239 POSTING_READ(PCH_DREF_CONTROL);
8240 udelay(200);
8241
8242 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8243
8244 /* Enable CPU source on CPU attached eDP */
8245 if (has_cpu_edp) {
8246 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8247 DRM_DEBUG_KMS("Using SSC on eDP\n");
8248 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8249 } else
8250 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8251 } else
8252 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253
8254 I915_WRITE(PCH_DREF_CONTROL, val);
8255 POSTING_READ(PCH_DREF_CONTROL);
8256 udelay(200);
8257 } else {
8258 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8259
8260 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8261
8262 /* Turn off CPU output */
8263 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8264
8265 I915_WRITE(PCH_DREF_CONTROL, val);
8266 POSTING_READ(PCH_DREF_CONTROL);
8267 udelay(200);
8268
8269 /* Turn off the SSC source */
8270 val &= ~DREF_SSC_SOURCE_MASK;
8271 val |= DREF_SSC_SOURCE_DISABLE;
8272
8273 /* Turn off SSC1 */
8274 val &= ~DREF_SSC1_ENABLE;
8275
8276 I915_WRITE(PCH_DREF_CONTROL, val);
8277 POSTING_READ(PCH_DREF_CONTROL);
8278 udelay(200);
8279 }
8280
8281 BUG_ON(val != final);
8282 }
8283
8284 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8285 {
8286 uint32_t tmp;
8287
8288 tmp = I915_READ(SOUTH_CHICKEN2);
8289 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8290 I915_WRITE(SOUTH_CHICKEN2, tmp);
8291
8292 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8293 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8294 DRM_ERROR("FDI mPHY reset assert timeout\n");
8295
8296 tmp = I915_READ(SOUTH_CHICKEN2);
8297 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8298 I915_WRITE(SOUTH_CHICKEN2, tmp);
8299
8300 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8301 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8302 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8303 }
8304
8305 /* WaMPhyProgramming:hsw */
8306 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8307 {
8308 uint32_t tmp;
8309
8310 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8311 tmp &= ~(0xFF << 24);
8312 tmp |= (0x12 << 24);
8313 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8314
8315 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8316 tmp |= (1 << 11);
8317 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8318
8319 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8320 tmp |= (1 << 11);
8321 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8324 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8325 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8326
8327 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8328 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8329 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8332 tmp &= ~(7 << 13);
8333 tmp |= (5 << 13);
8334 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8335
8336 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8337 tmp &= ~(7 << 13);
8338 tmp |= (5 << 13);
8339 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8342 tmp &= ~0xFF;
8343 tmp |= 0x1C;
8344 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8345
8346 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8347 tmp &= ~0xFF;
8348 tmp |= 0x1C;
8349 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8350
8351 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8352 tmp &= ~(0xFF << 16);
8353 tmp |= (0x1C << 16);
8354 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8357 tmp &= ~(0xFF << 16);
8358 tmp |= (0x1C << 16);
8359 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8360
8361 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8362 tmp |= (1 << 27);
8363 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8366 tmp |= (1 << 27);
8367 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8370 tmp &= ~(0xF << 28);
8371 tmp |= (4 << 28);
8372 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8373
8374 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8375 tmp &= ~(0xF << 28);
8376 tmp |= (4 << 28);
8377 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8378 }
8379
8380 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8381 * Programming" based on the parameters passed:
8382 * - Sequence to enable CLKOUT_DP
8383 * - Sequence to enable CLKOUT_DP without spread
8384 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8385 */
8386 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8387 bool with_fdi)
8388 {
8389 struct drm_i915_private *dev_priv = dev->dev_private;
8390 uint32_t reg, tmp;
8391
8392 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8393 with_spread = true;
8394 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8395 with_fdi, "LP PCH doesn't have FDI\n"))
8396 with_fdi = false;
8397
8398 mutex_lock(&dev_priv->sb_lock);
8399
8400 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8401 tmp &= ~SBI_SSCCTL_DISABLE;
8402 tmp |= SBI_SSCCTL_PATHALT;
8403 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8404
8405 udelay(24);
8406
8407 if (with_spread) {
8408 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8409 tmp &= ~SBI_SSCCTL_PATHALT;
8410 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8411
8412 if (with_fdi) {
8413 lpt_reset_fdi_mphy(dev_priv);
8414 lpt_program_fdi_mphy(dev_priv);
8415 }
8416 }
8417
8418 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8419 SBI_GEN0 : SBI_DBUFF0;
8420 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8421 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8422 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8423
8424 mutex_unlock(&dev_priv->sb_lock);
8425 }
8426
8427 /* Sequence to disable CLKOUT_DP */
8428 static void lpt_disable_clkout_dp(struct drm_device *dev)
8429 {
8430 struct drm_i915_private *dev_priv = dev->dev_private;
8431 uint32_t reg, tmp;
8432
8433 mutex_lock(&dev_priv->sb_lock);
8434
8435 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8436 SBI_GEN0 : SBI_DBUFF0;
8437 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8438 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8439 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8440
8441 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8442 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8443 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8444 tmp |= SBI_SSCCTL_PATHALT;
8445 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8446 udelay(32);
8447 }
8448 tmp |= SBI_SSCCTL_DISABLE;
8449 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8450 }
8451
8452 mutex_unlock(&dev_priv->sb_lock);
8453 }
8454
8455 static void lpt_init_pch_refclk(struct drm_device *dev)
8456 {
8457 struct intel_encoder *encoder;
8458 bool has_vga = false;
8459
8460 for_each_intel_encoder(dev, encoder) {
8461 switch (encoder->type) {
8462 case INTEL_OUTPUT_ANALOG:
8463 has_vga = true;
8464 break;
8465 default:
8466 break;
8467 }
8468 }
8469
8470 if (has_vga)
8471 lpt_enable_clkout_dp(dev, true, true);
8472 else
8473 lpt_disable_clkout_dp(dev);
8474 }
8475
8476 /*
8477 * Initialize reference clocks when the driver loads
8478 */
8479 void intel_init_pch_refclk(struct drm_device *dev)
8480 {
8481 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8482 ironlake_init_pch_refclk(dev);
8483 else if (HAS_PCH_LPT(dev))
8484 lpt_init_pch_refclk(dev);
8485 }
8486
8487 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8488 {
8489 struct drm_device *dev = crtc_state->base.crtc->dev;
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 struct drm_atomic_state *state = crtc_state->base.state;
8492 struct drm_connector *connector;
8493 struct drm_connector_state *connector_state;
8494 struct intel_encoder *encoder;
8495 int num_connectors = 0, i;
8496 bool is_lvds = false;
8497
8498 for_each_connector_in_state(state, connector, connector_state, i) {
8499 if (connector_state->crtc != crtc_state->base.crtc)
8500 continue;
8501
8502 encoder = to_intel_encoder(connector_state->best_encoder);
8503
8504 switch (encoder->type) {
8505 case INTEL_OUTPUT_LVDS:
8506 is_lvds = true;
8507 break;
8508 default:
8509 break;
8510 }
8511 num_connectors++;
8512 }
8513
8514 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8515 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8516 dev_priv->vbt.lvds_ssc_freq);
8517 return dev_priv->vbt.lvds_ssc_freq;
8518 }
8519
8520 return 120000;
8521 }
8522
8523 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8524 {
8525 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8527 int pipe = intel_crtc->pipe;
8528 uint32_t val;
8529
8530 val = 0;
8531
8532 switch (intel_crtc->config->pipe_bpp) {
8533 case 18:
8534 val |= PIPECONF_6BPC;
8535 break;
8536 case 24:
8537 val |= PIPECONF_8BPC;
8538 break;
8539 case 30:
8540 val |= PIPECONF_10BPC;
8541 break;
8542 case 36:
8543 val |= PIPECONF_12BPC;
8544 break;
8545 default:
8546 /* Case prevented by intel_choose_pipe_bpp_dither. */
8547 BUG();
8548 }
8549
8550 if (intel_crtc->config->dither)
8551 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8552
8553 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8554 val |= PIPECONF_INTERLACED_ILK;
8555 else
8556 val |= PIPECONF_PROGRESSIVE;
8557
8558 if (intel_crtc->config->limited_color_range)
8559 val |= PIPECONF_COLOR_RANGE_SELECT;
8560
8561 I915_WRITE(PIPECONF(pipe), val);
8562 POSTING_READ(PIPECONF(pipe));
8563 }
8564
8565 /*
8566 * Set up the pipe CSC unit.
8567 *
8568 * Currently only full range RGB to limited range RGB conversion
8569 * is supported, but eventually this should handle various
8570 * RGB<->YCbCr scenarios as well.
8571 */
8572 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8573 {
8574 struct drm_device *dev = crtc->dev;
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8577 int pipe = intel_crtc->pipe;
8578 uint16_t coeff = 0x7800; /* 1.0 */
8579
8580 /*
8581 * TODO: Check what kind of values actually come out of the pipe
8582 * with these coeff/postoff values and adjust to get the best
8583 * accuracy. Perhaps we even need to take the bpc value into
8584 * consideration.
8585 */
8586
8587 if (intel_crtc->config->limited_color_range)
8588 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8589
8590 /*
8591 * GY/GU and RY/RU should be the other way around according
8592 * to BSpec, but reality doesn't agree. Just set them up in
8593 * a way that results in the correct picture.
8594 */
8595 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8596 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8597
8598 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8599 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8600
8601 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8602 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8603
8604 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8605 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8606 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8607
8608 if (INTEL_INFO(dev)->gen > 6) {
8609 uint16_t postoff = 0;
8610
8611 if (intel_crtc->config->limited_color_range)
8612 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8613
8614 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8615 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8616 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8617
8618 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8619 } else {
8620 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8621
8622 if (intel_crtc->config->limited_color_range)
8623 mode |= CSC_BLACK_SCREEN_OFFSET;
8624
8625 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8626 }
8627 }
8628
8629 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8630 {
8631 struct drm_device *dev = crtc->dev;
8632 struct drm_i915_private *dev_priv = dev->dev_private;
8633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8634 enum pipe pipe = intel_crtc->pipe;
8635 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8636 uint32_t val;
8637
8638 val = 0;
8639
8640 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8641 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8642
8643 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8644 val |= PIPECONF_INTERLACED_ILK;
8645 else
8646 val |= PIPECONF_PROGRESSIVE;
8647
8648 I915_WRITE(PIPECONF(cpu_transcoder), val);
8649 POSTING_READ(PIPECONF(cpu_transcoder));
8650
8651 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8652 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8653
8654 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8655 val = 0;
8656
8657 switch (intel_crtc->config->pipe_bpp) {
8658 case 18:
8659 val |= PIPEMISC_DITHER_6_BPC;
8660 break;
8661 case 24:
8662 val |= PIPEMISC_DITHER_8_BPC;
8663 break;
8664 case 30:
8665 val |= PIPEMISC_DITHER_10_BPC;
8666 break;
8667 case 36:
8668 val |= PIPEMISC_DITHER_12_BPC;
8669 break;
8670 default:
8671 /* Case prevented by pipe_config_set_bpp. */
8672 BUG();
8673 }
8674
8675 if (intel_crtc->config->dither)
8676 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8677
8678 I915_WRITE(PIPEMISC(pipe), val);
8679 }
8680 }
8681
8682 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8683 struct intel_crtc_state *crtc_state,
8684 intel_clock_t *clock,
8685 bool *has_reduced_clock,
8686 intel_clock_t *reduced_clock)
8687 {
8688 struct drm_device *dev = crtc->dev;
8689 struct drm_i915_private *dev_priv = dev->dev_private;
8690 int refclk;
8691 const intel_limit_t *limit;
8692 bool ret, is_lvds = false;
8693
8694 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8695
8696 refclk = ironlake_get_refclk(crtc_state);
8697
8698 /*
8699 * Returns a set of divisors for the desired target clock with the given
8700 * refclk, or FALSE. The returned values represent the clock equation:
8701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8702 */
8703 limit = intel_limit(crtc_state, refclk);
8704 ret = dev_priv->display.find_dpll(limit, crtc_state,
8705 crtc_state->port_clock,
8706 refclk, NULL, clock);
8707 if (!ret)
8708 return false;
8709
8710 if (is_lvds && dev_priv->lvds_downclock_avail) {
8711 /*
8712 * Ensure we match the reduced clock's P to the target clock.
8713 * If the clocks don't match, we can't switch the display clock
8714 * by using the FP0/FP1. In such case we will disable the LVDS
8715 * downclock feature.
8716 */
8717 *has_reduced_clock =
8718 dev_priv->display.find_dpll(limit, crtc_state,
8719 dev_priv->lvds_downclock,
8720 refclk, clock,
8721 reduced_clock);
8722 }
8723
8724 return true;
8725 }
8726
8727 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8728 {
8729 /*
8730 * Account for spread spectrum to avoid
8731 * oversubscribing the link. Max center spread
8732 * is 2.5%; use 5% for safety's sake.
8733 */
8734 u32 bps = target_clock * bpp * 21 / 20;
8735 return DIV_ROUND_UP(bps, link_bw * 8);
8736 }
8737
8738 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8739 {
8740 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8741 }
8742
8743 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8744 struct intel_crtc_state *crtc_state,
8745 u32 *fp,
8746 intel_clock_t *reduced_clock, u32 *fp2)
8747 {
8748 struct drm_crtc *crtc = &intel_crtc->base;
8749 struct drm_device *dev = crtc->dev;
8750 struct drm_i915_private *dev_priv = dev->dev_private;
8751 struct drm_atomic_state *state = crtc_state->base.state;
8752 struct drm_connector *connector;
8753 struct drm_connector_state *connector_state;
8754 struct intel_encoder *encoder;
8755 uint32_t dpll;
8756 int factor, num_connectors = 0, i;
8757 bool is_lvds = false, is_sdvo = false;
8758
8759 for_each_connector_in_state(state, connector, connector_state, i) {
8760 if (connector_state->crtc != crtc_state->base.crtc)
8761 continue;
8762
8763 encoder = to_intel_encoder(connector_state->best_encoder);
8764
8765 switch (encoder->type) {
8766 case INTEL_OUTPUT_LVDS:
8767 is_lvds = true;
8768 break;
8769 case INTEL_OUTPUT_SDVO:
8770 case INTEL_OUTPUT_HDMI:
8771 is_sdvo = true;
8772 break;
8773 default:
8774 break;
8775 }
8776
8777 num_connectors++;
8778 }
8779
8780 /* Enable autotuning of the PLL clock (if permissible) */
8781 factor = 21;
8782 if (is_lvds) {
8783 if ((intel_panel_use_ssc(dev_priv) &&
8784 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8785 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8786 factor = 25;
8787 } else if (crtc_state->sdvo_tv_clock)
8788 factor = 20;
8789
8790 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8791 *fp |= FP_CB_TUNE;
8792
8793 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8794 *fp2 |= FP_CB_TUNE;
8795
8796 dpll = 0;
8797
8798 if (is_lvds)
8799 dpll |= DPLLB_MODE_LVDS;
8800 else
8801 dpll |= DPLLB_MODE_DAC_SERIAL;
8802
8803 dpll |= (crtc_state->pixel_multiplier - 1)
8804 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8805
8806 if (is_sdvo)
8807 dpll |= DPLL_SDVO_HIGH_SPEED;
8808 if (crtc_state->has_dp_encoder)
8809 dpll |= DPLL_SDVO_HIGH_SPEED;
8810
8811 /* compute bitmask from p1 value */
8812 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8813 /* also FPA1 */
8814 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8815
8816 switch (crtc_state->dpll.p2) {
8817 case 5:
8818 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8819 break;
8820 case 7:
8821 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8822 break;
8823 case 10:
8824 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8825 break;
8826 case 14:
8827 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8828 break;
8829 }
8830
8831 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8832 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8833 else
8834 dpll |= PLL_REF_INPUT_DREFCLK;
8835
8836 return dpll | DPLL_VCO_ENABLE;
8837 }
8838
8839 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8840 struct intel_crtc_state *crtc_state)
8841 {
8842 struct drm_device *dev = crtc->base.dev;
8843 intel_clock_t clock, reduced_clock;
8844 u32 dpll = 0, fp = 0, fp2 = 0;
8845 bool ok, has_reduced_clock = false;
8846 bool is_lvds = false;
8847 struct intel_shared_dpll *pll;
8848
8849 memset(&crtc_state->dpll_hw_state, 0,
8850 sizeof(crtc_state->dpll_hw_state));
8851
8852 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8853
8854 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8855 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8856
8857 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8858 &has_reduced_clock, &reduced_clock);
8859 if (!ok && !crtc_state->clock_set) {
8860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8861 return -EINVAL;
8862 }
8863 /* Compat-code for transition, will disappear. */
8864 if (!crtc_state->clock_set) {
8865 crtc_state->dpll.n = clock.n;
8866 crtc_state->dpll.m1 = clock.m1;
8867 crtc_state->dpll.m2 = clock.m2;
8868 crtc_state->dpll.p1 = clock.p1;
8869 crtc_state->dpll.p2 = clock.p2;
8870 }
8871
8872 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8873 if (crtc_state->has_pch_encoder) {
8874 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8875 if (has_reduced_clock)
8876 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8877
8878 dpll = ironlake_compute_dpll(crtc, crtc_state,
8879 &fp, &reduced_clock,
8880 has_reduced_clock ? &fp2 : NULL);
8881
8882 crtc_state->dpll_hw_state.dpll = dpll;
8883 crtc_state->dpll_hw_state.fp0 = fp;
8884 if (has_reduced_clock)
8885 crtc_state->dpll_hw_state.fp1 = fp2;
8886 else
8887 crtc_state->dpll_hw_state.fp1 = fp;
8888
8889 pll = intel_get_shared_dpll(crtc, crtc_state);
8890 if (pll == NULL) {
8891 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8892 pipe_name(crtc->pipe));
8893 return -EINVAL;
8894 }
8895 }
8896
8897 if (is_lvds && has_reduced_clock)
8898 crtc->lowfreq_avail = true;
8899 else
8900 crtc->lowfreq_avail = false;
8901
8902 return 0;
8903 }
8904
8905 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8906 struct intel_link_m_n *m_n)
8907 {
8908 struct drm_device *dev = crtc->base.dev;
8909 struct drm_i915_private *dev_priv = dev->dev_private;
8910 enum pipe pipe = crtc->pipe;
8911
8912 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8913 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8914 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8915 & ~TU_SIZE_MASK;
8916 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8917 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8918 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8919 }
8920
8921 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8922 enum transcoder transcoder,
8923 struct intel_link_m_n *m_n,
8924 struct intel_link_m_n *m2_n2)
8925 {
8926 struct drm_device *dev = crtc->base.dev;
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928 enum pipe pipe = crtc->pipe;
8929
8930 if (INTEL_INFO(dev)->gen >= 5) {
8931 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8932 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8933 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8934 & ~TU_SIZE_MASK;
8935 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8936 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8937 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8938 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8939 * gen < 8) and if DRRS is supported (to make sure the
8940 * registers are not unnecessarily read).
8941 */
8942 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8943 crtc->config->has_drrs) {
8944 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8945 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8946 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8947 & ~TU_SIZE_MASK;
8948 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8949 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8950 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8951 }
8952 } else {
8953 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8954 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8955 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8956 & ~TU_SIZE_MASK;
8957 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8958 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8959 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8960 }
8961 }
8962
8963 void intel_dp_get_m_n(struct intel_crtc *crtc,
8964 struct intel_crtc_state *pipe_config)
8965 {
8966 if (pipe_config->has_pch_encoder)
8967 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8968 else
8969 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8970 &pipe_config->dp_m_n,
8971 &pipe_config->dp_m2_n2);
8972 }
8973
8974 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8975 struct intel_crtc_state *pipe_config)
8976 {
8977 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8978 &pipe_config->fdi_m_n, NULL);
8979 }
8980
8981 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8982 struct intel_crtc_state *pipe_config)
8983 {
8984 struct drm_device *dev = crtc->base.dev;
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8987 uint32_t ps_ctrl = 0;
8988 int id = -1;
8989 int i;
8990
8991 /* find scaler attached to this pipe */
8992 for (i = 0; i < crtc->num_scalers; i++) {
8993 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8994 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8995 id = i;
8996 pipe_config->pch_pfit.enabled = true;
8997 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8998 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8999 break;
9000 }
9001 }
9002
9003 scaler_state->scaler_id = id;
9004 if (id >= 0) {
9005 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9006 } else {
9007 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9008 }
9009 }
9010
9011 static void
9012 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9013 struct intel_initial_plane_config *plane_config)
9014 {
9015 struct drm_device *dev = crtc->base.dev;
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017 u32 val, base, offset, stride_mult, tiling;
9018 int pipe = crtc->pipe;
9019 int fourcc, pixel_format;
9020 unsigned int aligned_height;
9021 struct drm_framebuffer *fb;
9022 struct intel_framebuffer *intel_fb;
9023
9024 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9025 if (!intel_fb) {
9026 DRM_DEBUG_KMS("failed to alloc fb\n");
9027 return;
9028 }
9029
9030 fb = &intel_fb->base;
9031
9032 val = I915_READ(PLANE_CTL(pipe, 0));
9033 if (!(val & PLANE_CTL_ENABLE))
9034 goto error;
9035
9036 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9037 fourcc = skl_format_to_fourcc(pixel_format,
9038 val & PLANE_CTL_ORDER_RGBX,
9039 val & PLANE_CTL_ALPHA_MASK);
9040 fb->pixel_format = fourcc;
9041 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9042
9043 tiling = val & PLANE_CTL_TILED_MASK;
9044 switch (tiling) {
9045 case PLANE_CTL_TILED_LINEAR:
9046 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9047 break;
9048 case PLANE_CTL_TILED_X:
9049 plane_config->tiling = I915_TILING_X;
9050 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9051 break;
9052 case PLANE_CTL_TILED_Y:
9053 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9054 break;
9055 case PLANE_CTL_TILED_YF:
9056 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9057 break;
9058 default:
9059 MISSING_CASE(tiling);
9060 goto error;
9061 }
9062
9063 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9064 plane_config->base = base;
9065
9066 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9067
9068 val = I915_READ(PLANE_SIZE(pipe, 0));
9069 fb->height = ((val >> 16) & 0xfff) + 1;
9070 fb->width = ((val >> 0) & 0x1fff) + 1;
9071
9072 val = I915_READ(PLANE_STRIDE(pipe, 0));
9073 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9074 fb->pixel_format);
9075 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9076
9077 aligned_height = intel_fb_align_height(dev, fb->height,
9078 fb->pixel_format,
9079 fb->modifier[0]);
9080
9081 plane_config->size = fb->pitches[0] * aligned_height;
9082
9083 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9084 pipe_name(pipe), fb->width, fb->height,
9085 fb->bits_per_pixel, base, fb->pitches[0],
9086 plane_config->size);
9087
9088 plane_config->fb = intel_fb;
9089 return;
9090
9091 error:
9092 kfree(fb);
9093 }
9094
9095 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9096 struct intel_crtc_state *pipe_config)
9097 {
9098 struct drm_device *dev = crtc->base.dev;
9099 struct drm_i915_private *dev_priv = dev->dev_private;
9100 uint32_t tmp;
9101
9102 tmp = I915_READ(PF_CTL(crtc->pipe));
9103
9104 if (tmp & PF_ENABLE) {
9105 pipe_config->pch_pfit.enabled = true;
9106 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9107 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9108
9109 /* We currently do not free assignements of panel fitters on
9110 * ivb/hsw (since we don't use the higher upscaling modes which
9111 * differentiates them) so just WARN about this case for now. */
9112 if (IS_GEN7(dev)) {
9113 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9114 PF_PIPE_SEL_IVB(crtc->pipe));
9115 }
9116 }
9117 }
9118
9119 static void
9120 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9121 struct intel_initial_plane_config *plane_config)
9122 {
9123 struct drm_device *dev = crtc->base.dev;
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 u32 val, base, offset;
9126 int pipe = crtc->pipe;
9127 int fourcc, pixel_format;
9128 unsigned int aligned_height;
9129 struct drm_framebuffer *fb;
9130 struct intel_framebuffer *intel_fb;
9131
9132 val = I915_READ(DSPCNTR(pipe));
9133 if (!(val & DISPLAY_PLANE_ENABLE))
9134 return;
9135
9136 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9137 if (!intel_fb) {
9138 DRM_DEBUG_KMS("failed to alloc fb\n");
9139 return;
9140 }
9141
9142 fb = &intel_fb->base;
9143
9144 if (INTEL_INFO(dev)->gen >= 4) {
9145 if (val & DISPPLANE_TILED) {
9146 plane_config->tiling = I915_TILING_X;
9147 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9148 }
9149 }
9150
9151 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9152 fourcc = i9xx_format_to_fourcc(pixel_format);
9153 fb->pixel_format = fourcc;
9154 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9155
9156 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9157 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9158 offset = I915_READ(DSPOFFSET(pipe));
9159 } else {
9160 if (plane_config->tiling)
9161 offset = I915_READ(DSPTILEOFF(pipe));
9162 else
9163 offset = I915_READ(DSPLINOFF(pipe));
9164 }
9165 plane_config->base = base;
9166
9167 val = I915_READ(PIPESRC(pipe));
9168 fb->width = ((val >> 16) & 0xfff) + 1;
9169 fb->height = ((val >> 0) & 0xfff) + 1;
9170
9171 val = I915_READ(DSPSTRIDE(pipe));
9172 fb->pitches[0] = val & 0xffffffc0;
9173
9174 aligned_height = intel_fb_align_height(dev, fb->height,
9175 fb->pixel_format,
9176 fb->modifier[0]);
9177
9178 plane_config->size = fb->pitches[0] * aligned_height;
9179
9180 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9181 pipe_name(pipe), fb->width, fb->height,
9182 fb->bits_per_pixel, base, fb->pitches[0],
9183 plane_config->size);
9184
9185 plane_config->fb = intel_fb;
9186 }
9187
9188 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9189 struct intel_crtc_state *pipe_config)
9190 {
9191 struct drm_device *dev = crtc->base.dev;
9192 struct drm_i915_private *dev_priv = dev->dev_private;
9193 uint32_t tmp;
9194
9195 if (!intel_display_power_is_enabled(dev_priv,
9196 POWER_DOMAIN_PIPE(crtc->pipe)))
9197 return false;
9198
9199 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9200 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9201
9202 tmp = I915_READ(PIPECONF(crtc->pipe));
9203 if (!(tmp & PIPECONF_ENABLE))
9204 return false;
9205
9206 switch (tmp & PIPECONF_BPC_MASK) {
9207 case PIPECONF_6BPC:
9208 pipe_config->pipe_bpp = 18;
9209 break;
9210 case PIPECONF_8BPC:
9211 pipe_config->pipe_bpp = 24;
9212 break;
9213 case PIPECONF_10BPC:
9214 pipe_config->pipe_bpp = 30;
9215 break;
9216 case PIPECONF_12BPC:
9217 pipe_config->pipe_bpp = 36;
9218 break;
9219 default:
9220 break;
9221 }
9222
9223 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9224 pipe_config->limited_color_range = true;
9225
9226 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9227 struct intel_shared_dpll *pll;
9228
9229 pipe_config->has_pch_encoder = true;
9230
9231 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9232 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9233 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9234
9235 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9236
9237 if (HAS_PCH_IBX(dev_priv->dev)) {
9238 pipe_config->shared_dpll =
9239 (enum intel_dpll_id) crtc->pipe;
9240 } else {
9241 tmp = I915_READ(PCH_DPLL_SEL);
9242 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9243 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9244 else
9245 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9246 }
9247
9248 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9249
9250 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9251 &pipe_config->dpll_hw_state));
9252
9253 tmp = pipe_config->dpll_hw_state.dpll;
9254 pipe_config->pixel_multiplier =
9255 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9256 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9257
9258 ironlake_pch_clock_get(crtc, pipe_config);
9259 } else {
9260 pipe_config->pixel_multiplier = 1;
9261 }
9262
9263 intel_get_pipe_timings(crtc, pipe_config);
9264
9265 ironlake_get_pfit_config(crtc, pipe_config);
9266
9267 return true;
9268 }
9269
9270 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9271 {
9272 struct drm_device *dev = dev_priv->dev;
9273 struct intel_crtc *crtc;
9274
9275 for_each_intel_crtc(dev, crtc)
9276 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9277 pipe_name(crtc->pipe));
9278
9279 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9280 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9281 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9282 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9283 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9284 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9285 "CPU PWM1 enabled\n");
9286 if (IS_HASWELL(dev))
9287 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9288 "CPU PWM2 enabled\n");
9289 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9290 "PCH PWM1 enabled\n");
9291 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9292 "Utility pin enabled\n");
9293 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9294
9295 /*
9296 * In theory we can still leave IRQs enabled, as long as only the HPD
9297 * interrupts remain enabled. We used to check for that, but since it's
9298 * gen-specific and since we only disable LCPLL after we fully disable
9299 * the interrupts, the check below should be enough.
9300 */
9301 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9302 }
9303
9304 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9305 {
9306 struct drm_device *dev = dev_priv->dev;
9307
9308 if (IS_HASWELL(dev))
9309 return I915_READ(D_COMP_HSW);
9310 else
9311 return I915_READ(D_COMP_BDW);
9312 }
9313
9314 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9315 {
9316 struct drm_device *dev = dev_priv->dev;
9317
9318 if (IS_HASWELL(dev)) {
9319 mutex_lock(&dev_priv->rps.hw_lock);
9320 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9321 val))
9322 DRM_ERROR("Failed to write to D_COMP\n");
9323 mutex_unlock(&dev_priv->rps.hw_lock);
9324 } else {
9325 I915_WRITE(D_COMP_BDW, val);
9326 POSTING_READ(D_COMP_BDW);
9327 }
9328 }
9329
9330 /*
9331 * This function implements pieces of two sequences from BSpec:
9332 * - Sequence for display software to disable LCPLL
9333 * - Sequence for display software to allow package C8+
9334 * The steps implemented here are just the steps that actually touch the LCPLL
9335 * register. Callers should take care of disabling all the display engine
9336 * functions, doing the mode unset, fixing interrupts, etc.
9337 */
9338 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9339 bool switch_to_fclk, bool allow_power_down)
9340 {
9341 uint32_t val;
9342
9343 assert_can_disable_lcpll(dev_priv);
9344
9345 val = I915_READ(LCPLL_CTL);
9346
9347 if (switch_to_fclk) {
9348 val |= LCPLL_CD_SOURCE_FCLK;
9349 I915_WRITE(LCPLL_CTL, val);
9350
9351 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9352 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9353 DRM_ERROR("Switching to FCLK failed\n");
9354
9355 val = I915_READ(LCPLL_CTL);
9356 }
9357
9358 val |= LCPLL_PLL_DISABLE;
9359 I915_WRITE(LCPLL_CTL, val);
9360 POSTING_READ(LCPLL_CTL);
9361
9362 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9363 DRM_ERROR("LCPLL still locked\n");
9364
9365 val = hsw_read_dcomp(dev_priv);
9366 val |= D_COMP_COMP_DISABLE;
9367 hsw_write_dcomp(dev_priv, val);
9368 ndelay(100);
9369
9370 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9371 1))
9372 DRM_ERROR("D_COMP RCOMP still in progress\n");
9373
9374 if (allow_power_down) {
9375 val = I915_READ(LCPLL_CTL);
9376 val |= LCPLL_POWER_DOWN_ALLOW;
9377 I915_WRITE(LCPLL_CTL, val);
9378 POSTING_READ(LCPLL_CTL);
9379 }
9380 }
9381
9382 /*
9383 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9384 * source.
9385 */
9386 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9387 {
9388 uint32_t val;
9389
9390 val = I915_READ(LCPLL_CTL);
9391
9392 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9393 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9394 return;
9395
9396 /*
9397 * Make sure we're not on PC8 state before disabling PC8, otherwise
9398 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9399 */
9400 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9401
9402 if (val & LCPLL_POWER_DOWN_ALLOW) {
9403 val &= ~LCPLL_POWER_DOWN_ALLOW;
9404 I915_WRITE(LCPLL_CTL, val);
9405 POSTING_READ(LCPLL_CTL);
9406 }
9407
9408 val = hsw_read_dcomp(dev_priv);
9409 val |= D_COMP_COMP_FORCE;
9410 val &= ~D_COMP_COMP_DISABLE;
9411 hsw_write_dcomp(dev_priv, val);
9412
9413 val = I915_READ(LCPLL_CTL);
9414 val &= ~LCPLL_PLL_DISABLE;
9415 I915_WRITE(LCPLL_CTL, val);
9416
9417 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9418 DRM_ERROR("LCPLL not locked yet\n");
9419
9420 if (val & LCPLL_CD_SOURCE_FCLK) {
9421 val = I915_READ(LCPLL_CTL);
9422 val &= ~LCPLL_CD_SOURCE_FCLK;
9423 I915_WRITE(LCPLL_CTL, val);
9424
9425 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9426 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9427 DRM_ERROR("Switching back to LCPLL failed\n");
9428 }
9429
9430 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9431 intel_update_cdclk(dev_priv->dev);
9432 }
9433
9434 /*
9435 * Package states C8 and deeper are really deep PC states that can only be
9436 * reached when all the devices on the system allow it, so even if the graphics
9437 * device allows PC8+, it doesn't mean the system will actually get to these
9438 * states. Our driver only allows PC8+ when going into runtime PM.
9439 *
9440 * The requirements for PC8+ are that all the outputs are disabled, the power
9441 * well is disabled and most interrupts are disabled, and these are also
9442 * requirements for runtime PM. When these conditions are met, we manually do
9443 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9444 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9445 * hang the machine.
9446 *
9447 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9448 * the state of some registers, so when we come back from PC8+ we need to
9449 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9450 * need to take care of the registers kept by RC6. Notice that this happens even
9451 * if we don't put the device in PCI D3 state (which is what currently happens
9452 * because of the runtime PM support).
9453 *
9454 * For more, read "Display Sequences for Package C8" on the hardware
9455 * documentation.
9456 */
9457 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9458 {
9459 struct drm_device *dev = dev_priv->dev;
9460 uint32_t val;
9461
9462 DRM_DEBUG_KMS("Enabling package C8+\n");
9463
9464 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9465 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9466 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9467 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9468 }
9469
9470 lpt_disable_clkout_dp(dev);
9471 hsw_disable_lcpll(dev_priv, true, true);
9472 }
9473
9474 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9475 {
9476 struct drm_device *dev = dev_priv->dev;
9477 uint32_t val;
9478
9479 DRM_DEBUG_KMS("Disabling package C8+\n");
9480
9481 hsw_restore_lcpll(dev_priv);
9482 lpt_init_pch_refclk(dev);
9483
9484 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9485 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9486 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9487 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9488 }
9489
9490 intel_prepare_ddi(dev);
9491 }
9492
9493 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9494 {
9495 struct drm_device *dev = old_state->dev;
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9497 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9498 int req_cdclk;
9499
9500 /* see the comment in valleyview_modeset_global_resources */
9501 if (WARN_ON(max_pixclk < 0))
9502 return;
9503
9504 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9505
9506 if (req_cdclk != dev_priv->cdclk_freq)
9507 broxton_set_cdclk(dev, req_cdclk);
9508 }
9509
9510 /* compute the max rate for new configuration */
9511 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9512 {
9513 struct drm_device *dev = dev_priv->dev;
9514 struct intel_crtc *intel_crtc;
9515 struct drm_crtc *crtc;
9516 int max_pixel_rate = 0;
9517 int pixel_rate;
9518
9519 for_each_crtc(dev, crtc) {
9520 if (!crtc->state->enable)
9521 continue;
9522
9523 intel_crtc = to_intel_crtc(crtc);
9524 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9525
9526 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9527 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9528 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9529
9530 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9531 }
9532
9533 return max_pixel_rate;
9534 }
9535
9536 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9537 {
9538 struct drm_i915_private *dev_priv = dev->dev_private;
9539 uint32_t val, data;
9540 int ret;
9541
9542 if (WARN((I915_READ(LCPLL_CTL) &
9543 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9544 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9545 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9546 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9547 "trying to change cdclk frequency with cdclk not enabled\n"))
9548 return;
9549
9550 mutex_lock(&dev_priv->rps.hw_lock);
9551 ret = sandybridge_pcode_write(dev_priv,
9552 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9553 mutex_unlock(&dev_priv->rps.hw_lock);
9554 if (ret) {
9555 DRM_ERROR("failed to inform pcode about cdclk change\n");
9556 return;
9557 }
9558
9559 val = I915_READ(LCPLL_CTL);
9560 val |= LCPLL_CD_SOURCE_FCLK;
9561 I915_WRITE(LCPLL_CTL, val);
9562
9563 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9564 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9565 DRM_ERROR("Switching to FCLK failed\n");
9566
9567 val = I915_READ(LCPLL_CTL);
9568 val &= ~LCPLL_CLK_FREQ_MASK;
9569
9570 switch (cdclk) {
9571 case 450000:
9572 val |= LCPLL_CLK_FREQ_450;
9573 data = 0;
9574 break;
9575 case 540000:
9576 val |= LCPLL_CLK_FREQ_54O_BDW;
9577 data = 1;
9578 break;
9579 case 337500:
9580 val |= LCPLL_CLK_FREQ_337_5_BDW;
9581 data = 2;
9582 break;
9583 case 675000:
9584 val |= LCPLL_CLK_FREQ_675_BDW;
9585 data = 3;
9586 break;
9587 default:
9588 WARN(1, "invalid cdclk frequency\n");
9589 return;
9590 }
9591
9592 I915_WRITE(LCPLL_CTL, val);
9593
9594 val = I915_READ(LCPLL_CTL);
9595 val &= ~LCPLL_CD_SOURCE_FCLK;
9596 I915_WRITE(LCPLL_CTL, val);
9597
9598 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9599 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9600 DRM_ERROR("Switching back to LCPLL failed\n");
9601
9602 mutex_lock(&dev_priv->rps.hw_lock);
9603 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9604 mutex_unlock(&dev_priv->rps.hw_lock);
9605
9606 intel_update_cdclk(dev);
9607
9608 WARN(cdclk != dev_priv->cdclk_freq,
9609 "cdclk requested %d kHz but got %d kHz\n",
9610 cdclk, dev_priv->cdclk_freq);
9611 }
9612
9613 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9614 int max_pixel_rate)
9615 {
9616 int cdclk;
9617
9618 /*
9619 * FIXME should also account for plane ratio
9620 * once 64bpp pixel formats are supported.
9621 */
9622 if (max_pixel_rate > 540000)
9623 cdclk = 675000;
9624 else if (max_pixel_rate > 450000)
9625 cdclk = 540000;
9626 else if (max_pixel_rate > 337500)
9627 cdclk = 450000;
9628 else
9629 cdclk = 337500;
9630
9631 /*
9632 * FIXME move the cdclk caclulation to
9633 * compute_config() so we can fail gracegully.
9634 */
9635 if (cdclk > dev_priv->max_cdclk_freq) {
9636 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9637 cdclk, dev_priv->max_cdclk_freq);
9638 cdclk = dev_priv->max_cdclk_freq;
9639 }
9640
9641 return cdclk;
9642 }
9643
9644 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9645 {
9646 struct drm_i915_private *dev_priv = to_i915(state->dev);
9647 struct drm_crtc *crtc;
9648 struct drm_crtc_state *crtc_state;
9649 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9650 int cdclk, i;
9651
9652 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9653
9654 if (cdclk == dev_priv->cdclk_freq)
9655 return 0;
9656
9657 /* add all active pipes to the state */
9658 for_each_crtc(state->dev, crtc) {
9659 if (!crtc->state->enable)
9660 continue;
9661
9662 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9663 if (IS_ERR(crtc_state))
9664 return PTR_ERR(crtc_state);
9665 }
9666
9667 /* disable/enable all currently active pipes while we change cdclk */
9668 for_each_crtc_in_state(state, crtc, crtc_state, i)
9669 if (crtc_state->enable)
9670 crtc_state->mode_changed = true;
9671
9672 return 0;
9673 }
9674
9675 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9676 {
9677 struct drm_device *dev = state->dev;
9678 struct drm_i915_private *dev_priv = dev->dev_private;
9679 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9680 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9681
9682 if (req_cdclk != dev_priv->cdclk_freq)
9683 broadwell_set_cdclk(dev, req_cdclk);
9684 }
9685
9686 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9687 struct intel_crtc_state *crtc_state)
9688 {
9689 if (!intel_ddi_pll_select(crtc, crtc_state))
9690 return -EINVAL;
9691
9692 crtc->lowfreq_avail = false;
9693
9694 return 0;
9695 }
9696
9697 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9698 enum port port,
9699 struct intel_crtc_state *pipe_config)
9700 {
9701 switch (port) {
9702 case PORT_A:
9703 pipe_config->ddi_pll_sel = SKL_DPLL0;
9704 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9705 break;
9706 case PORT_B:
9707 pipe_config->ddi_pll_sel = SKL_DPLL1;
9708 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9709 break;
9710 case PORT_C:
9711 pipe_config->ddi_pll_sel = SKL_DPLL2;
9712 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9713 break;
9714 default:
9715 DRM_ERROR("Incorrect port type\n");
9716 }
9717 }
9718
9719 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9720 enum port port,
9721 struct intel_crtc_state *pipe_config)
9722 {
9723 u32 temp, dpll_ctl1;
9724
9725 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9726 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9727
9728 switch (pipe_config->ddi_pll_sel) {
9729 case SKL_DPLL0:
9730 /*
9731 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9732 * of the shared DPLL framework and thus needs to be read out
9733 * separately
9734 */
9735 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9736 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9737 break;
9738 case SKL_DPLL1:
9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9740 break;
9741 case SKL_DPLL2:
9742 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9743 break;
9744 case SKL_DPLL3:
9745 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9746 break;
9747 }
9748 }
9749
9750 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9751 enum port port,
9752 struct intel_crtc_state *pipe_config)
9753 {
9754 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9755
9756 switch (pipe_config->ddi_pll_sel) {
9757 case PORT_CLK_SEL_WRPLL1:
9758 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9759 break;
9760 case PORT_CLK_SEL_WRPLL2:
9761 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9762 break;
9763 }
9764 }
9765
9766 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9767 struct intel_crtc_state *pipe_config)
9768 {
9769 struct drm_device *dev = crtc->base.dev;
9770 struct drm_i915_private *dev_priv = dev->dev_private;
9771 struct intel_shared_dpll *pll;
9772 enum port port;
9773 uint32_t tmp;
9774
9775 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9776
9777 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9778
9779 if (IS_SKYLAKE(dev))
9780 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9781 else if (IS_BROXTON(dev))
9782 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9783 else
9784 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9785
9786 if (pipe_config->shared_dpll >= 0) {
9787 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9788
9789 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9790 &pipe_config->dpll_hw_state));
9791 }
9792
9793 /*
9794 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9795 * DDI E. So just check whether this pipe is wired to DDI E and whether
9796 * the PCH transcoder is on.
9797 */
9798 if (INTEL_INFO(dev)->gen < 9 &&
9799 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9800 pipe_config->has_pch_encoder = true;
9801
9802 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9803 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9804 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9805
9806 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9807 }
9808 }
9809
9810 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9811 struct intel_crtc_state *pipe_config)
9812 {
9813 struct drm_device *dev = crtc->base.dev;
9814 struct drm_i915_private *dev_priv = dev->dev_private;
9815 enum intel_display_power_domain pfit_domain;
9816 uint32_t tmp;
9817
9818 if (!intel_display_power_is_enabled(dev_priv,
9819 POWER_DOMAIN_PIPE(crtc->pipe)))
9820 return false;
9821
9822 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9823 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9824
9825 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9826 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9827 enum pipe trans_edp_pipe;
9828 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9829 default:
9830 WARN(1, "unknown pipe linked to edp transcoder\n");
9831 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9832 case TRANS_DDI_EDP_INPUT_A_ON:
9833 trans_edp_pipe = PIPE_A;
9834 break;
9835 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9836 trans_edp_pipe = PIPE_B;
9837 break;
9838 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9839 trans_edp_pipe = PIPE_C;
9840 break;
9841 }
9842
9843 if (trans_edp_pipe == crtc->pipe)
9844 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9845 }
9846
9847 if (!intel_display_power_is_enabled(dev_priv,
9848 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9849 return false;
9850
9851 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9852 if (!(tmp & PIPECONF_ENABLE))
9853 return false;
9854
9855 haswell_get_ddi_port_state(crtc, pipe_config);
9856
9857 intel_get_pipe_timings(crtc, pipe_config);
9858
9859 if (INTEL_INFO(dev)->gen >= 9) {
9860 skl_init_scalers(dev, crtc, pipe_config);
9861 }
9862
9863 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9864
9865 if (INTEL_INFO(dev)->gen >= 9) {
9866 pipe_config->scaler_state.scaler_id = -1;
9867 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9868 }
9869
9870 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9871 if (INTEL_INFO(dev)->gen == 9)
9872 skylake_get_pfit_config(crtc, pipe_config);
9873 else if (INTEL_INFO(dev)->gen < 9)
9874 ironlake_get_pfit_config(crtc, pipe_config);
9875 else
9876 MISSING_CASE(INTEL_INFO(dev)->gen);
9877 }
9878
9879 if (IS_HASWELL(dev))
9880 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9881 (I915_READ(IPS_CTL) & IPS_ENABLE);
9882
9883 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9884 pipe_config->pixel_multiplier =
9885 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9886 } else {
9887 pipe_config->pixel_multiplier = 1;
9888 }
9889
9890 return true;
9891 }
9892
9893 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9894 {
9895 struct drm_device *dev = crtc->dev;
9896 struct drm_i915_private *dev_priv = dev->dev_private;
9897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9898 uint32_t cntl = 0, size = 0;
9899
9900 if (base) {
9901 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9902 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9903 unsigned int stride = roundup_pow_of_two(width) * 4;
9904
9905 switch (stride) {
9906 default:
9907 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9908 width, stride);
9909 stride = 256;
9910 /* fallthrough */
9911 case 256:
9912 case 512:
9913 case 1024:
9914 case 2048:
9915 break;
9916 }
9917
9918 cntl |= CURSOR_ENABLE |
9919 CURSOR_GAMMA_ENABLE |
9920 CURSOR_FORMAT_ARGB |
9921 CURSOR_STRIDE(stride);
9922
9923 size = (height << 12) | width;
9924 }
9925
9926 if (intel_crtc->cursor_cntl != 0 &&
9927 (intel_crtc->cursor_base != base ||
9928 intel_crtc->cursor_size != size ||
9929 intel_crtc->cursor_cntl != cntl)) {
9930 /* On these chipsets we can only modify the base/size/stride
9931 * whilst the cursor is disabled.
9932 */
9933 I915_WRITE(_CURACNTR, 0);
9934 POSTING_READ(_CURACNTR);
9935 intel_crtc->cursor_cntl = 0;
9936 }
9937
9938 if (intel_crtc->cursor_base != base) {
9939 I915_WRITE(_CURABASE, base);
9940 intel_crtc->cursor_base = base;
9941 }
9942
9943 if (intel_crtc->cursor_size != size) {
9944 I915_WRITE(CURSIZE, size);
9945 intel_crtc->cursor_size = size;
9946 }
9947
9948 if (intel_crtc->cursor_cntl != cntl) {
9949 I915_WRITE(_CURACNTR, cntl);
9950 POSTING_READ(_CURACNTR);
9951 intel_crtc->cursor_cntl = cntl;
9952 }
9953 }
9954
9955 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9956 {
9957 struct drm_device *dev = crtc->dev;
9958 struct drm_i915_private *dev_priv = dev->dev_private;
9959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9960 int pipe = intel_crtc->pipe;
9961 uint32_t cntl;
9962
9963 cntl = 0;
9964 if (base) {
9965 cntl = MCURSOR_GAMMA_ENABLE;
9966 switch (intel_crtc->base.cursor->state->crtc_w) {
9967 case 64:
9968 cntl |= CURSOR_MODE_64_ARGB_AX;
9969 break;
9970 case 128:
9971 cntl |= CURSOR_MODE_128_ARGB_AX;
9972 break;
9973 case 256:
9974 cntl |= CURSOR_MODE_256_ARGB_AX;
9975 break;
9976 default:
9977 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9978 return;
9979 }
9980 cntl |= pipe << 28; /* Connect to correct pipe */
9981
9982 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9983 cntl |= CURSOR_PIPE_CSC_ENABLE;
9984 }
9985
9986 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9987 cntl |= CURSOR_ROTATE_180;
9988
9989 if (intel_crtc->cursor_cntl != cntl) {
9990 I915_WRITE(CURCNTR(pipe), cntl);
9991 POSTING_READ(CURCNTR(pipe));
9992 intel_crtc->cursor_cntl = cntl;
9993 }
9994
9995 /* and commit changes on next vblank */
9996 I915_WRITE(CURBASE(pipe), base);
9997 POSTING_READ(CURBASE(pipe));
9998
9999 intel_crtc->cursor_base = base;
10000 }
10001
10002 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10003 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10004 bool on)
10005 {
10006 struct drm_device *dev = crtc->dev;
10007 struct drm_i915_private *dev_priv = dev->dev_private;
10008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10009 int pipe = intel_crtc->pipe;
10010 int x = crtc->cursor_x;
10011 int y = crtc->cursor_y;
10012 u32 base = 0, pos = 0;
10013
10014 if (on)
10015 base = intel_crtc->cursor_addr;
10016
10017 if (x >= intel_crtc->config->pipe_src_w)
10018 base = 0;
10019
10020 if (y >= intel_crtc->config->pipe_src_h)
10021 base = 0;
10022
10023 if (x < 0) {
10024 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10025 base = 0;
10026
10027 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10028 x = -x;
10029 }
10030 pos |= x << CURSOR_X_SHIFT;
10031
10032 if (y < 0) {
10033 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10034 base = 0;
10035
10036 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10037 y = -y;
10038 }
10039 pos |= y << CURSOR_Y_SHIFT;
10040
10041 if (base == 0 && intel_crtc->cursor_base == 0)
10042 return;
10043
10044 I915_WRITE(CURPOS(pipe), pos);
10045
10046 /* ILK+ do this automagically */
10047 if (HAS_GMCH_DISPLAY(dev) &&
10048 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10049 base += (intel_crtc->base.cursor->state->crtc_h *
10050 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10051 }
10052
10053 if (IS_845G(dev) || IS_I865G(dev))
10054 i845_update_cursor(crtc, base);
10055 else
10056 i9xx_update_cursor(crtc, base);
10057 }
10058
10059 static bool cursor_size_ok(struct drm_device *dev,
10060 uint32_t width, uint32_t height)
10061 {
10062 if (width == 0 || height == 0)
10063 return false;
10064
10065 /*
10066 * 845g/865g are special in that they are only limited by
10067 * the width of their cursors, the height is arbitrary up to
10068 * the precision of the register. Everything else requires
10069 * square cursors, limited to a few power-of-two sizes.
10070 */
10071 if (IS_845G(dev) || IS_I865G(dev)) {
10072 if ((width & 63) != 0)
10073 return false;
10074
10075 if (width > (IS_845G(dev) ? 64 : 512))
10076 return false;
10077
10078 if (height > 1023)
10079 return false;
10080 } else {
10081 switch (width | height) {
10082 case 256:
10083 case 128:
10084 if (IS_GEN2(dev))
10085 return false;
10086 case 64:
10087 break;
10088 default:
10089 return false;
10090 }
10091 }
10092
10093 return true;
10094 }
10095
10096 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10097 u16 *blue, uint32_t start, uint32_t size)
10098 {
10099 int end = (start + size > 256) ? 256 : start + size, i;
10100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10101
10102 for (i = start; i < end; i++) {
10103 intel_crtc->lut_r[i] = red[i] >> 8;
10104 intel_crtc->lut_g[i] = green[i] >> 8;
10105 intel_crtc->lut_b[i] = blue[i] >> 8;
10106 }
10107
10108 intel_crtc_load_lut(crtc);
10109 }
10110
10111 /* VESA 640x480x72Hz mode to set on the pipe */
10112 static struct drm_display_mode load_detect_mode = {
10113 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10114 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10115 };
10116
10117 struct drm_framebuffer *
10118 __intel_framebuffer_create(struct drm_device *dev,
10119 struct drm_mode_fb_cmd2 *mode_cmd,
10120 struct drm_i915_gem_object *obj)
10121 {
10122 struct intel_framebuffer *intel_fb;
10123 int ret;
10124
10125 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10126 if (!intel_fb) {
10127 drm_gem_object_unreference(&obj->base);
10128 return ERR_PTR(-ENOMEM);
10129 }
10130
10131 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10132 if (ret)
10133 goto err;
10134
10135 return &intel_fb->base;
10136 err:
10137 drm_gem_object_unreference(&obj->base);
10138 kfree(intel_fb);
10139
10140 return ERR_PTR(ret);
10141 }
10142
10143 static struct drm_framebuffer *
10144 intel_framebuffer_create(struct drm_device *dev,
10145 struct drm_mode_fb_cmd2 *mode_cmd,
10146 struct drm_i915_gem_object *obj)
10147 {
10148 struct drm_framebuffer *fb;
10149 int ret;
10150
10151 ret = i915_mutex_lock_interruptible(dev);
10152 if (ret)
10153 return ERR_PTR(ret);
10154 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10155 mutex_unlock(&dev->struct_mutex);
10156
10157 return fb;
10158 }
10159
10160 static u32
10161 intel_framebuffer_pitch_for_width(int width, int bpp)
10162 {
10163 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10164 return ALIGN(pitch, 64);
10165 }
10166
10167 static u32
10168 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10169 {
10170 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10171 return PAGE_ALIGN(pitch * mode->vdisplay);
10172 }
10173
10174 static struct drm_framebuffer *
10175 intel_framebuffer_create_for_mode(struct drm_device *dev,
10176 struct drm_display_mode *mode,
10177 int depth, int bpp)
10178 {
10179 struct drm_i915_gem_object *obj;
10180 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10181
10182 obj = i915_gem_alloc_object(dev,
10183 intel_framebuffer_size_for_mode(mode, bpp));
10184 if (obj == NULL)
10185 return ERR_PTR(-ENOMEM);
10186
10187 mode_cmd.width = mode->hdisplay;
10188 mode_cmd.height = mode->vdisplay;
10189 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10190 bpp);
10191 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10192
10193 return intel_framebuffer_create(dev, &mode_cmd, obj);
10194 }
10195
10196 static struct drm_framebuffer *
10197 mode_fits_in_fbdev(struct drm_device *dev,
10198 struct drm_display_mode *mode)
10199 {
10200 #ifdef CONFIG_DRM_I915_FBDEV
10201 struct drm_i915_private *dev_priv = dev->dev_private;
10202 struct drm_i915_gem_object *obj;
10203 struct drm_framebuffer *fb;
10204
10205 if (!dev_priv->fbdev)
10206 return NULL;
10207
10208 if (!dev_priv->fbdev->fb)
10209 return NULL;
10210
10211 obj = dev_priv->fbdev->fb->obj;
10212 BUG_ON(!obj);
10213
10214 fb = &dev_priv->fbdev->fb->base;
10215 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10216 fb->bits_per_pixel))
10217 return NULL;
10218
10219 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10220 return NULL;
10221
10222 return fb;
10223 #else
10224 return NULL;
10225 #endif
10226 }
10227
10228 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10229 struct drm_crtc *crtc,
10230 struct drm_display_mode *mode,
10231 struct drm_framebuffer *fb,
10232 int x, int y)
10233 {
10234 struct drm_plane_state *plane_state;
10235 int hdisplay, vdisplay;
10236 int ret;
10237
10238 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10239 if (IS_ERR(plane_state))
10240 return PTR_ERR(plane_state);
10241
10242 if (mode)
10243 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10244 else
10245 hdisplay = vdisplay = 0;
10246
10247 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10248 if (ret)
10249 return ret;
10250 drm_atomic_set_fb_for_plane(plane_state, fb);
10251 plane_state->crtc_x = 0;
10252 plane_state->crtc_y = 0;
10253 plane_state->crtc_w = hdisplay;
10254 plane_state->crtc_h = vdisplay;
10255 plane_state->src_x = x << 16;
10256 plane_state->src_y = y << 16;
10257 plane_state->src_w = hdisplay << 16;
10258 plane_state->src_h = vdisplay << 16;
10259
10260 return 0;
10261 }
10262
10263 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10264 struct drm_display_mode *mode,
10265 struct intel_load_detect_pipe *old,
10266 struct drm_modeset_acquire_ctx *ctx)
10267 {
10268 struct intel_crtc *intel_crtc;
10269 struct intel_encoder *intel_encoder =
10270 intel_attached_encoder(connector);
10271 struct drm_crtc *possible_crtc;
10272 struct drm_encoder *encoder = &intel_encoder->base;
10273 struct drm_crtc *crtc = NULL;
10274 struct drm_device *dev = encoder->dev;
10275 struct drm_framebuffer *fb;
10276 struct drm_mode_config *config = &dev->mode_config;
10277 struct drm_atomic_state *state = NULL;
10278 struct drm_connector_state *connector_state;
10279 struct intel_crtc_state *crtc_state;
10280 int ret, i = -1;
10281
10282 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10283 connector->base.id, connector->name,
10284 encoder->base.id, encoder->name);
10285
10286 retry:
10287 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10288 if (ret)
10289 goto fail_unlock;
10290
10291 /*
10292 * Algorithm gets a little messy:
10293 *
10294 * - if the connector already has an assigned crtc, use it (but make
10295 * sure it's on first)
10296 *
10297 * - try to find the first unused crtc that can drive this connector,
10298 * and use that if we find one
10299 */
10300
10301 /* See if we already have a CRTC for this connector */
10302 if (encoder->crtc) {
10303 crtc = encoder->crtc;
10304
10305 ret = drm_modeset_lock(&crtc->mutex, ctx);
10306 if (ret)
10307 goto fail_unlock;
10308 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10309 if (ret)
10310 goto fail_unlock;
10311
10312 old->dpms_mode = connector->dpms;
10313 old->load_detect_temp = false;
10314
10315 /* Make sure the crtc and connector are running */
10316 if (connector->dpms != DRM_MODE_DPMS_ON)
10317 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10318
10319 return true;
10320 }
10321
10322 /* Find an unused one (if possible) */
10323 for_each_crtc(dev, possible_crtc) {
10324 i++;
10325 if (!(encoder->possible_crtcs & (1 << i)))
10326 continue;
10327 if (possible_crtc->state->enable)
10328 continue;
10329 /* This can occur when applying the pipe A quirk on resume. */
10330 if (to_intel_crtc(possible_crtc)->new_enabled)
10331 continue;
10332
10333 crtc = possible_crtc;
10334 break;
10335 }
10336
10337 /*
10338 * If we didn't find an unused CRTC, don't use any.
10339 */
10340 if (!crtc) {
10341 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10342 goto fail_unlock;
10343 }
10344
10345 ret = drm_modeset_lock(&crtc->mutex, ctx);
10346 if (ret)
10347 goto fail_unlock;
10348 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10349 if (ret)
10350 goto fail_unlock;
10351 intel_encoder->new_crtc = to_intel_crtc(crtc);
10352 to_intel_connector(connector)->new_encoder = intel_encoder;
10353
10354 intel_crtc = to_intel_crtc(crtc);
10355 intel_crtc->new_enabled = true;
10356 old->dpms_mode = connector->dpms;
10357 old->load_detect_temp = true;
10358 old->release_fb = NULL;
10359
10360 state = drm_atomic_state_alloc(dev);
10361 if (!state)
10362 return false;
10363
10364 state->acquire_ctx = ctx;
10365
10366 connector_state = drm_atomic_get_connector_state(state, connector);
10367 if (IS_ERR(connector_state)) {
10368 ret = PTR_ERR(connector_state);
10369 goto fail;
10370 }
10371
10372 connector_state->crtc = crtc;
10373 connector_state->best_encoder = &intel_encoder->base;
10374
10375 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10376 if (IS_ERR(crtc_state)) {
10377 ret = PTR_ERR(crtc_state);
10378 goto fail;
10379 }
10380
10381 crtc_state->base.active = crtc_state->base.enable = true;
10382
10383 if (!mode)
10384 mode = &load_detect_mode;
10385
10386 /* We need a framebuffer large enough to accommodate all accesses
10387 * that the plane may generate whilst we perform load detection.
10388 * We can not rely on the fbcon either being present (we get called
10389 * during its initialisation to detect all boot displays, or it may
10390 * not even exist) or that it is large enough to satisfy the
10391 * requested mode.
10392 */
10393 fb = mode_fits_in_fbdev(dev, mode);
10394 if (fb == NULL) {
10395 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10396 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10397 old->release_fb = fb;
10398 } else
10399 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10400 if (IS_ERR(fb)) {
10401 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10402 goto fail;
10403 }
10404
10405 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10406 if (ret)
10407 goto fail;
10408
10409 drm_mode_copy(&crtc_state->base.mode, mode);
10410
10411 if (intel_set_mode(state)) {
10412 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10413 if (old->release_fb)
10414 old->release_fb->funcs->destroy(old->release_fb);
10415 goto fail;
10416 }
10417 crtc->primary->crtc = crtc;
10418
10419 /* let the connector get through one full cycle before testing */
10420 intel_wait_for_vblank(dev, intel_crtc->pipe);
10421 return true;
10422
10423 fail:
10424 intel_crtc->new_enabled = crtc->state->enable;
10425 fail_unlock:
10426 drm_atomic_state_free(state);
10427 state = NULL;
10428
10429 if (ret == -EDEADLK) {
10430 drm_modeset_backoff(ctx);
10431 goto retry;
10432 }
10433
10434 return false;
10435 }
10436
10437 void intel_release_load_detect_pipe(struct drm_connector *connector,
10438 struct intel_load_detect_pipe *old,
10439 struct drm_modeset_acquire_ctx *ctx)
10440 {
10441 struct drm_device *dev = connector->dev;
10442 struct intel_encoder *intel_encoder =
10443 intel_attached_encoder(connector);
10444 struct drm_encoder *encoder = &intel_encoder->base;
10445 struct drm_crtc *crtc = encoder->crtc;
10446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10447 struct drm_atomic_state *state;
10448 struct drm_connector_state *connector_state;
10449 struct intel_crtc_state *crtc_state;
10450 int ret;
10451
10452 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10453 connector->base.id, connector->name,
10454 encoder->base.id, encoder->name);
10455
10456 if (old->load_detect_temp) {
10457 state = drm_atomic_state_alloc(dev);
10458 if (!state)
10459 goto fail;
10460
10461 state->acquire_ctx = ctx;
10462
10463 connector_state = drm_atomic_get_connector_state(state, connector);
10464 if (IS_ERR(connector_state))
10465 goto fail;
10466
10467 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10468 if (IS_ERR(crtc_state))
10469 goto fail;
10470
10471 to_intel_connector(connector)->new_encoder = NULL;
10472 intel_encoder->new_crtc = NULL;
10473 intel_crtc->new_enabled = false;
10474
10475 connector_state->best_encoder = NULL;
10476 connector_state->crtc = NULL;
10477
10478 crtc_state->base.enable = crtc_state->base.active = false;
10479
10480 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10481 0, 0);
10482 if (ret)
10483 goto fail;
10484
10485 ret = intel_set_mode(state);
10486 if (ret)
10487 goto fail;
10488
10489 if (old->release_fb) {
10490 drm_framebuffer_unregister_private(old->release_fb);
10491 drm_framebuffer_unreference(old->release_fb);
10492 }
10493
10494 return;
10495 }
10496
10497 /* Switch crtc and encoder back off if necessary */
10498 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10499 connector->funcs->dpms(connector, old->dpms_mode);
10500
10501 return;
10502 fail:
10503 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10504 drm_atomic_state_free(state);
10505 }
10506
10507 static int i9xx_pll_refclk(struct drm_device *dev,
10508 const struct intel_crtc_state *pipe_config)
10509 {
10510 struct drm_i915_private *dev_priv = dev->dev_private;
10511 u32 dpll = pipe_config->dpll_hw_state.dpll;
10512
10513 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10514 return dev_priv->vbt.lvds_ssc_freq;
10515 else if (HAS_PCH_SPLIT(dev))
10516 return 120000;
10517 else if (!IS_GEN2(dev))
10518 return 96000;
10519 else
10520 return 48000;
10521 }
10522
10523 /* Returns the clock of the currently programmed mode of the given pipe. */
10524 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10525 struct intel_crtc_state *pipe_config)
10526 {
10527 struct drm_device *dev = crtc->base.dev;
10528 struct drm_i915_private *dev_priv = dev->dev_private;
10529 int pipe = pipe_config->cpu_transcoder;
10530 u32 dpll = pipe_config->dpll_hw_state.dpll;
10531 u32 fp;
10532 intel_clock_t clock;
10533 int refclk = i9xx_pll_refclk(dev, pipe_config);
10534
10535 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10536 fp = pipe_config->dpll_hw_state.fp0;
10537 else
10538 fp = pipe_config->dpll_hw_state.fp1;
10539
10540 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10541 if (IS_PINEVIEW(dev)) {
10542 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10543 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10544 } else {
10545 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10546 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10547 }
10548
10549 if (!IS_GEN2(dev)) {
10550 if (IS_PINEVIEW(dev))
10551 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10552 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10553 else
10554 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10555 DPLL_FPA01_P1_POST_DIV_SHIFT);
10556
10557 switch (dpll & DPLL_MODE_MASK) {
10558 case DPLLB_MODE_DAC_SERIAL:
10559 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10560 5 : 10;
10561 break;
10562 case DPLLB_MODE_LVDS:
10563 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10564 7 : 14;
10565 break;
10566 default:
10567 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10568 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10569 return;
10570 }
10571
10572 if (IS_PINEVIEW(dev))
10573 pineview_clock(refclk, &clock);
10574 else
10575 i9xx_clock(refclk, &clock);
10576 } else {
10577 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10578 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10579
10580 if (is_lvds) {
10581 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10582 DPLL_FPA01_P1_POST_DIV_SHIFT);
10583
10584 if (lvds & LVDS_CLKB_POWER_UP)
10585 clock.p2 = 7;
10586 else
10587 clock.p2 = 14;
10588 } else {
10589 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10590 clock.p1 = 2;
10591 else {
10592 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10593 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10594 }
10595 if (dpll & PLL_P2_DIVIDE_BY_4)
10596 clock.p2 = 4;
10597 else
10598 clock.p2 = 2;
10599 }
10600
10601 i9xx_clock(refclk, &clock);
10602 }
10603
10604 /*
10605 * This value includes pixel_multiplier. We will use
10606 * port_clock to compute adjusted_mode.crtc_clock in the
10607 * encoder's get_config() function.
10608 */
10609 pipe_config->port_clock = clock.dot;
10610 }
10611
10612 int intel_dotclock_calculate(int link_freq,
10613 const struct intel_link_m_n *m_n)
10614 {
10615 /*
10616 * The calculation for the data clock is:
10617 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10618 * But we want to avoid losing precison if possible, so:
10619 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10620 *
10621 * and the link clock is simpler:
10622 * link_clock = (m * link_clock) / n
10623 */
10624
10625 if (!m_n->link_n)
10626 return 0;
10627
10628 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10629 }
10630
10631 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10632 struct intel_crtc_state *pipe_config)
10633 {
10634 struct drm_device *dev = crtc->base.dev;
10635
10636 /* read out port_clock from the DPLL */
10637 i9xx_crtc_clock_get(crtc, pipe_config);
10638
10639 /*
10640 * This value does not include pixel_multiplier.
10641 * We will check that port_clock and adjusted_mode.crtc_clock
10642 * agree once we know their relationship in the encoder's
10643 * get_config() function.
10644 */
10645 pipe_config->base.adjusted_mode.crtc_clock =
10646 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10647 &pipe_config->fdi_m_n);
10648 }
10649
10650 /** Returns the currently programmed mode of the given pipe. */
10651 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10652 struct drm_crtc *crtc)
10653 {
10654 struct drm_i915_private *dev_priv = dev->dev_private;
10655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10656 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10657 struct drm_display_mode *mode;
10658 struct intel_crtc_state pipe_config;
10659 int htot = I915_READ(HTOTAL(cpu_transcoder));
10660 int hsync = I915_READ(HSYNC(cpu_transcoder));
10661 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10662 int vsync = I915_READ(VSYNC(cpu_transcoder));
10663 enum pipe pipe = intel_crtc->pipe;
10664
10665 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10666 if (!mode)
10667 return NULL;
10668
10669 /*
10670 * Construct a pipe_config sufficient for getting the clock info
10671 * back out of crtc_clock_get.
10672 *
10673 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10674 * to use a real value here instead.
10675 */
10676 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10677 pipe_config.pixel_multiplier = 1;
10678 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10679 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10680 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10681 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10682
10683 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10684 mode->hdisplay = (htot & 0xffff) + 1;
10685 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10686 mode->hsync_start = (hsync & 0xffff) + 1;
10687 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10688 mode->vdisplay = (vtot & 0xffff) + 1;
10689 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10690 mode->vsync_start = (vsync & 0xffff) + 1;
10691 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10692
10693 drm_mode_set_name(mode);
10694
10695 return mode;
10696 }
10697
10698 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10699 {
10700 struct drm_device *dev = crtc->dev;
10701 struct drm_i915_private *dev_priv = dev->dev_private;
10702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10703
10704 if (!HAS_GMCH_DISPLAY(dev))
10705 return;
10706
10707 if (!dev_priv->lvds_downclock_avail)
10708 return;
10709
10710 /*
10711 * Since this is called by a timer, we should never get here in
10712 * the manual case.
10713 */
10714 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10715 int pipe = intel_crtc->pipe;
10716 int dpll_reg = DPLL(pipe);
10717 int dpll;
10718
10719 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10720
10721 assert_panel_unlocked(dev_priv, pipe);
10722
10723 dpll = I915_READ(dpll_reg);
10724 dpll |= DISPLAY_RATE_SELECT_FPA1;
10725 I915_WRITE(dpll_reg, dpll);
10726 intel_wait_for_vblank(dev, pipe);
10727 dpll = I915_READ(dpll_reg);
10728 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10729 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10730 }
10731
10732 }
10733
10734 void intel_mark_busy(struct drm_device *dev)
10735 {
10736 struct drm_i915_private *dev_priv = dev->dev_private;
10737
10738 if (dev_priv->mm.busy)
10739 return;
10740
10741 intel_runtime_pm_get(dev_priv);
10742 i915_update_gfx_val(dev_priv);
10743 if (INTEL_INFO(dev)->gen >= 6)
10744 gen6_rps_busy(dev_priv);
10745 dev_priv->mm.busy = true;
10746 }
10747
10748 void intel_mark_idle(struct drm_device *dev)
10749 {
10750 struct drm_i915_private *dev_priv = dev->dev_private;
10751 struct drm_crtc *crtc;
10752
10753 if (!dev_priv->mm.busy)
10754 return;
10755
10756 dev_priv->mm.busy = false;
10757
10758 for_each_crtc(dev, crtc) {
10759 if (!crtc->primary->fb)
10760 continue;
10761
10762 intel_decrease_pllclock(crtc);
10763 }
10764
10765 if (INTEL_INFO(dev)->gen >= 6)
10766 gen6_rps_idle(dev->dev_private);
10767
10768 intel_runtime_pm_put(dev_priv);
10769 }
10770
10771 static void intel_crtc_destroy(struct drm_crtc *crtc)
10772 {
10773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10774 struct drm_device *dev = crtc->dev;
10775 struct intel_unpin_work *work;
10776
10777 spin_lock_irq(&dev->event_lock);
10778 work = intel_crtc->unpin_work;
10779 intel_crtc->unpin_work = NULL;
10780 spin_unlock_irq(&dev->event_lock);
10781
10782 if (work) {
10783 cancel_work_sync(&work->work);
10784 kfree(work);
10785 }
10786
10787 drm_crtc_cleanup(crtc);
10788
10789 kfree(intel_crtc);
10790 }
10791
10792 static void intel_unpin_work_fn(struct work_struct *__work)
10793 {
10794 struct intel_unpin_work *work =
10795 container_of(__work, struct intel_unpin_work, work);
10796 struct drm_device *dev = work->crtc->dev;
10797 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10798
10799 mutex_lock(&dev->struct_mutex);
10800 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10801 drm_gem_object_unreference(&work->pending_flip_obj->base);
10802
10803 intel_fbc_update(dev);
10804
10805 if (work->flip_queued_req)
10806 i915_gem_request_assign(&work->flip_queued_req, NULL);
10807 mutex_unlock(&dev->struct_mutex);
10808
10809 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10810 drm_framebuffer_unreference(work->old_fb);
10811
10812 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10813 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10814
10815 kfree(work);
10816 }
10817
10818 static void do_intel_finish_page_flip(struct drm_device *dev,
10819 struct drm_crtc *crtc)
10820 {
10821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10822 struct intel_unpin_work *work;
10823 unsigned long flags;
10824
10825 /* Ignore early vblank irqs */
10826 if (intel_crtc == NULL)
10827 return;
10828
10829 /*
10830 * This is called both by irq handlers and the reset code (to complete
10831 * lost pageflips) so needs the full irqsave spinlocks.
10832 */
10833 spin_lock_irqsave(&dev->event_lock, flags);
10834 work = intel_crtc->unpin_work;
10835
10836 /* Ensure we don't miss a work->pending update ... */
10837 smp_rmb();
10838
10839 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10840 spin_unlock_irqrestore(&dev->event_lock, flags);
10841 return;
10842 }
10843
10844 page_flip_completed(intel_crtc);
10845
10846 spin_unlock_irqrestore(&dev->event_lock, flags);
10847 }
10848
10849 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10850 {
10851 struct drm_i915_private *dev_priv = dev->dev_private;
10852 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10853
10854 do_intel_finish_page_flip(dev, crtc);
10855 }
10856
10857 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10858 {
10859 struct drm_i915_private *dev_priv = dev->dev_private;
10860 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10861
10862 do_intel_finish_page_flip(dev, crtc);
10863 }
10864
10865 /* Is 'a' after or equal to 'b'? */
10866 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10867 {
10868 return !((a - b) & 0x80000000);
10869 }
10870
10871 static bool page_flip_finished(struct intel_crtc *crtc)
10872 {
10873 struct drm_device *dev = crtc->base.dev;
10874 struct drm_i915_private *dev_priv = dev->dev_private;
10875
10876 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10877 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10878 return true;
10879
10880 /*
10881 * The relevant registers doen't exist on pre-ctg.
10882 * As the flip done interrupt doesn't trigger for mmio
10883 * flips on gmch platforms, a flip count check isn't
10884 * really needed there. But since ctg has the registers,
10885 * include it in the check anyway.
10886 */
10887 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10888 return true;
10889
10890 /*
10891 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10892 * used the same base address. In that case the mmio flip might
10893 * have completed, but the CS hasn't even executed the flip yet.
10894 *
10895 * A flip count check isn't enough as the CS might have updated
10896 * the base address just after start of vblank, but before we
10897 * managed to process the interrupt. This means we'd complete the
10898 * CS flip too soon.
10899 *
10900 * Combining both checks should get us a good enough result. It may
10901 * still happen that the CS flip has been executed, but has not
10902 * yet actually completed. But in case the base address is the same
10903 * anyway, we don't really care.
10904 */
10905 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10906 crtc->unpin_work->gtt_offset &&
10907 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10908 crtc->unpin_work->flip_count);
10909 }
10910
10911 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10912 {
10913 struct drm_i915_private *dev_priv = dev->dev_private;
10914 struct intel_crtc *intel_crtc =
10915 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10916 unsigned long flags;
10917
10918
10919 /*
10920 * This is called both by irq handlers and the reset code (to complete
10921 * lost pageflips) so needs the full irqsave spinlocks.
10922 *
10923 * NB: An MMIO update of the plane base pointer will also
10924 * generate a page-flip completion irq, i.e. every modeset
10925 * is also accompanied by a spurious intel_prepare_page_flip().
10926 */
10927 spin_lock_irqsave(&dev->event_lock, flags);
10928 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10929 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10930 spin_unlock_irqrestore(&dev->event_lock, flags);
10931 }
10932
10933 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10934 {
10935 /* Ensure that the work item is consistent when activating it ... */
10936 smp_wmb();
10937 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10938 /* and that it is marked active as soon as the irq could fire. */
10939 smp_wmb();
10940 }
10941
10942 static int intel_gen2_queue_flip(struct drm_device *dev,
10943 struct drm_crtc *crtc,
10944 struct drm_framebuffer *fb,
10945 struct drm_i915_gem_object *obj,
10946 struct intel_engine_cs *ring,
10947 uint32_t flags)
10948 {
10949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10950 u32 flip_mask;
10951 int ret;
10952
10953 ret = intel_ring_begin(ring, 6);
10954 if (ret)
10955 return ret;
10956
10957 /* Can't queue multiple flips, so wait for the previous
10958 * one to finish before executing the next.
10959 */
10960 if (intel_crtc->plane)
10961 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10962 else
10963 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10964 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10965 intel_ring_emit(ring, MI_NOOP);
10966 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10967 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10968 intel_ring_emit(ring, fb->pitches[0]);
10969 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10970 intel_ring_emit(ring, 0); /* aux display base address, unused */
10971
10972 intel_mark_page_flip_active(intel_crtc);
10973 __intel_ring_advance(ring);
10974 return 0;
10975 }
10976
10977 static int intel_gen3_queue_flip(struct drm_device *dev,
10978 struct drm_crtc *crtc,
10979 struct drm_framebuffer *fb,
10980 struct drm_i915_gem_object *obj,
10981 struct intel_engine_cs *ring,
10982 uint32_t flags)
10983 {
10984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10985 u32 flip_mask;
10986 int ret;
10987
10988 ret = intel_ring_begin(ring, 6);
10989 if (ret)
10990 return ret;
10991
10992 if (intel_crtc->plane)
10993 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10994 else
10995 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10996 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10997 intel_ring_emit(ring, MI_NOOP);
10998 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10999 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11000 intel_ring_emit(ring, fb->pitches[0]);
11001 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11002 intel_ring_emit(ring, MI_NOOP);
11003
11004 intel_mark_page_flip_active(intel_crtc);
11005 __intel_ring_advance(ring);
11006 return 0;
11007 }
11008
11009 static int intel_gen4_queue_flip(struct drm_device *dev,
11010 struct drm_crtc *crtc,
11011 struct drm_framebuffer *fb,
11012 struct drm_i915_gem_object *obj,
11013 struct intel_engine_cs *ring,
11014 uint32_t flags)
11015 {
11016 struct drm_i915_private *dev_priv = dev->dev_private;
11017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11018 uint32_t pf, pipesrc;
11019 int ret;
11020
11021 ret = intel_ring_begin(ring, 4);
11022 if (ret)
11023 return ret;
11024
11025 /* i965+ uses the linear or tiled offsets from the
11026 * Display Registers (which do not change across a page-flip)
11027 * so we need only reprogram the base address.
11028 */
11029 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11030 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11031 intel_ring_emit(ring, fb->pitches[0]);
11032 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11033 obj->tiling_mode);
11034
11035 /* XXX Enabling the panel-fitter across page-flip is so far
11036 * untested on non-native modes, so ignore it for now.
11037 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11038 */
11039 pf = 0;
11040 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11041 intel_ring_emit(ring, pf | pipesrc);
11042
11043 intel_mark_page_flip_active(intel_crtc);
11044 __intel_ring_advance(ring);
11045 return 0;
11046 }
11047
11048 static int intel_gen6_queue_flip(struct drm_device *dev,
11049 struct drm_crtc *crtc,
11050 struct drm_framebuffer *fb,
11051 struct drm_i915_gem_object *obj,
11052 struct intel_engine_cs *ring,
11053 uint32_t flags)
11054 {
11055 struct drm_i915_private *dev_priv = dev->dev_private;
11056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11057 uint32_t pf, pipesrc;
11058 int ret;
11059
11060 ret = intel_ring_begin(ring, 4);
11061 if (ret)
11062 return ret;
11063
11064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11067 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11068
11069 /* Contrary to the suggestions in the documentation,
11070 * "Enable Panel Fitter" does not seem to be required when page
11071 * flipping with a non-native mode, and worse causes a normal
11072 * modeset to fail.
11073 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11074 */
11075 pf = 0;
11076 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11077 intel_ring_emit(ring, pf | pipesrc);
11078
11079 intel_mark_page_flip_active(intel_crtc);
11080 __intel_ring_advance(ring);
11081 return 0;
11082 }
11083
11084 static int intel_gen7_queue_flip(struct drm_device *dev,
11085 struct drm_crtc *crtc,
11086 struct drm_framebuffer *fb,
11087 struct drm_i915_gem_object *obj,
11088 struct intel_engine_cs *ring,
11089 uint32_t flags)
11090 {
11091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092 uint32_t plane_bit = 0;
11093 int len, ret;
11094
11095 switch (intel_crtc->plane) {
11096 case PLANE_A:
11097 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11098 break;
11099 case PLANE_B:
11100 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11101 break;
11102 case PLANE_C:
11103 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11104 break;
11105 default:
11106 WARN_ONCE(1, "unknown plane in flip command\n");
11107 return -ENODEV;
11108 }
11109
11110 len = 4;
11111 if (ring->id == RCS) {
11112 len += 6;
11113 /*
11114 * On Gen 8, SRM is now taking an extra dword to accommodate
11115 * 48bits addresses, and we need a NOOP for the batch size to
11116 * stay even.
11117 */
11118 if (IS_GEN8(dev))
11119 len += 2;
11120 }
11121
11122 /*
11123 * BSpec MI_DISPLAY_FLIP for IVB:
11124 * "The full packet must be contained within the same cache line."
11125 *
11126 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11127 * cacheline, if we ever start emitting more commands before
11128 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11129 * then do the cacheline alignment, and finally emit the
11130 * MI_DISPLAY_FLIP.
11131 */
11132 ret = intel_ring_cacheline_align(ring);
11133 if (ret)
11134 return ret;
11135
11136 ret = intel_ring_begin(ring, len);
11137 if (ret)
11138 return ret;
11139
11140 /* Unmask the flip-done completion message. Note that the bspec says that
11141 * we should do this for both the BCS and RCS, and that we must not unmask
11142 * more than one flip event at any time (or ensure that one flip message
11143 * can be sent by waiting for flip-done prior to queueing new flips).
11144 * Experimentation says that BCS works despite DERRMR masking all
11145 * flip-done completion events and that unmasking all planes at once
11146 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11147 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11148 */
11149 if (ring->id == RCS) {
11150 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11151 intel_ring_emit(ring, DERRMR);
11152 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11153 DERRMR_PIPEB_PRI_FLIP_DONE |
11154 DERRMR_PIPEC_PRI_FLIP_DONE));
11155 if (IS_GEN8(dev))
11156 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11157 MI_SRM_LRM_GLOBAL_GTT);
11158 else
11159 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11160 MI_SRM_LRM_GLOBAL_GTT);
11161 intel_ring_emit(ring, DERRMR);
11162 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11163 if (IS_GEN8(dev)) {
11164 intel_ring_emit(ring, 0);
11165 intel_ring_emit(ring, MI_NOOP);
11166 }
11167 }
11168
11169 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11170 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11171 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11172 intel_ring_emit(ring, (MI_NOOP));
11173
11174 intel_mark_page_flip_active(intel_crtc);
11175 __intel_ring_advance(ring);
11176 return 0;
11177 }
11178
11179 static bool use_mmio_flip(struct intel_engine_cs *ring,
11180 struct drm_i915_gem_object *obj)
11181 {
11182 /*
11183 * This is not being used for older platforms, because
11184 * non-availability of flip done interrupt forces us to use
11185 * CS flips. Older platforms derive flip done using some clever
11186 * tricks involving the flip_pending status bits and vblank irqs.
11187 * So using MMIO flips there would disrupt this mechanism.
11188 */
11189
11190 if (ring == NULL)
11191 return true;
11192
11193 if (INTEL_INFO(ring->dev)->gen < 5)
11194 return false;
11195
11196 if (i915.use_mmio_flip < 0)
11197 return false;
11198 else if (i915.use_mmio_flip > 0)
11199 return true;
11200 else if (i915.enable_execlists)
11201 return true;
11202 else
11203 return ring != i915_gem_request_get_ring(obj->last_write_req);
11204 }
11205
11206 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11207 {
11208 struct drm_device *dev = intel_crtc->base.dev;
11209 struct drm_i915_private *dev_priv = dev->dev_private;
11210 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11211 const enum pipe pipe = intel_crtc->pipe;
11212 u32 ctl, stride;
11213
11214 ctl = I915_READ(PLANE_CTL(pipe, 0));
11215 ctl &= ~PLANE_CTL_TILED_MASK;
11216 switch (fb->modifier[0]) {
11217 case DRM_FORMAT_MOD_NONE:
11218 break;
11219 case I915_FORMAT_MOD_X_TILED:
11220 ctl |= PLANE_CTL_TILED_X;
11221 break;
11222 case I915_FORMAT_MOD_Y_TILED:
11223 ctl |= PLANE_CTL_TILED_Y;
11224 break;
11225 case I915_FORMAT_MOD_Yf_TILED:
11226 ctl |= PLANE_CTL_TILED_YF;
11227 break;
11228 default:
11229 MISSING_CASE(fb->modifier[0]);
11230 }
11231
11232 /*
11233 * The stride is either expressed as a multiple of 64 bytes chunks for
11234 * linear buffers or in number of tiles for tiled buffers.
11235 */
11236 stride = fb->pitches[0] /
11237 intel_fb_stride_alignment(dev, fb->modifier[0],
11238 fb->pixel_format);
11239
11240 /*
11241 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11242 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11243 */
11244 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11245 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11246
11247 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11248 POSTING_READ(PLANE_SURF(pipe, 0));
11249 }
11250
11251 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11252 {
11253 struct drm_device *dev = intel_crtc->base.dev;
11254 struct drm_i915_private *dev_priv = dev->dev_private;
11255 struct intel_framebuffer *intel_fb =
11256 to_intel_framebuffer(intel_crtc->base.primary->fb);
11257 struct drm_i915_gem_object *obj = intel_fb->obj;
11258 u32 dspcntr;
11259 u32 reg;
11260
11261 reg = DSPCNTR(intel_crtc->plane);
11262 dspcntr = I915_READ(reg);
11263
11264 if (obj->tiling_mode != I915_TILING_NONE)
11265 dspcntr |= DISPPLANE_TILED;
11266 else
11267 dspcntr &= ~DISPPLANE_TILED;
11268
11269 I915_WRITE(reg, dspcntr);
11270
11271 I915_WRITE(DSPSURF(intel_crtc->plane),
11272 intel_crtc->unpin_work->gtt_offset);
11273 POSTING_READ(DSPSURF(intel_crtc->plane));
11274
11275 }
11276
11277 /*
11278 * XXX: This is the temporary way to update the plane registers until we get
11279 * around to using the usual plane update functions for MMIO flips
11280 */
11281 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11282 {
11283 struct drm_device *dev = intel_crtc->base.dev;
11284 bool atomic_update;
11285 u32 start_vbl_count;
11286
11287 intel_mark_page_flip_active(intel_crtc);
11288
11289 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11290
11291 if (INTEL_INFO(dev)->gen >= 9)
11292 skl_do_mmio_flip(intel_crtc);
11293 else
11294 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11295 ilk_do_mmio_flip(intel_crtc);
11296
11297 if (atomic_update)
11298 intel_pipe_update_end(intel_crtc, start_vbl_count);
11299 }
11300
11301 static void intel_mmio_flip_work_func(struct work_struct *work)
11302 {
11303 struct intel_mmio_flip *mmio_flip =
11304 container_of(work, struct intel_mmio_flip, work);
11305
11306 if (mmio_flip->req)
11307 WARN_ON(__i915_wait_request(mmio_flip->req,
11308 mmio_flip->crtc->reset_counter,
11309 false, NULL,
11310 &mmio_flip->i915->rps.mmioflips));
11311
11312 intel_do_mmio_flip(mmio_flip->crtc);
11313
11314 i915_gem_request_unreference__unlocked(mmio_flip->req);
11315 kfree(mmio_flip);
11316 }
11317
11318 static int intel_queue_mmio_flip(struct drm_device *dev,
11319 struct drm_crtc *crtc,
11320 struct drm_framebuffer *fb,
11321 struct drm_i915_gem_object *obj,
11322 struct intel_engine_cs *ring,
11323 uint32_t flags)
11324 {
11325 struct intel_mmio_flip *mmio_flip;
11326
11327 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11328 if (mmio_flip == NULL)
11329 return -ENOMEM;
11330
11331 mmio_flip->i915 = to_i915(dev);
11332 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11333 mmio_flip->crtc = to_intel_crtc(crtc);
11334
11335 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11336 schedule_work(&mmio_flip->work);
11337
11338 return 0;
11339 }
11340
11341 static int intel_default_queue_flip(struct drm_device *dev,
11342 struct drm_crtc *crtc,
11343 struct drm_framebuffer *fb,
11344 struct drm_i915_gem_object *obj,
11345 struct intel_engine_cs *ring,
11346 uint32_t flags)
11347 {
11348 return -ENODEV;
11349 }
11350
11351 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11352 struct drm_crtc *crtc)
11353 {
11354 struct drm_i915_private *dev_priv = dev->dev_private;
11355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11356 struct intel_unpin_work *work = intel_crtc->unpin_work;
11357 u32 addr;
11358
11359 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11360 return true;
11361
11362 if (!work->enable_stall_check)
11363 return false;
11364
11365 if (work->flip_ready_vblank == 0) {
11366 if (work->flip_queued_req &&
11367 !i915_gem_request_completed(work->flip_queued_req, true))
11368 return false;
11369
11370 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11371 }
11372
11373 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11374 return false;
11375
11376 /* Potential stall - if we see that the flip has happened,
11377 * assume a missed interrupt. */
11378 if (INTEL_INFO(dev)->gen >= 4)
11379 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11380 else
11381 addr = I915_READ(DSPADDR(intel_crtc->plane));
11382
11383 /* There is a potential issue here with a false positive after a flip
11384 * to the same address. We could address this by checking for a
11385 * non-incrementing frame counter.
11386 */
11387 return addr == work->gtt_offset;
11388 }
11389
11390 void intel_check_page_flip(struct drm_device *dev, int pipe)
11391 {
11392 struct drm_i915_private *dev_priv = dev->dev_private;
11393 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11395 struct intel_unpin_work *work;
11396
11397 WARN_ON(!in_interrupt());
11398
11399 if (crtc == NULL)
11400 return;
11401
11402 spin_lock(&dev->event_lock);
11403 work = intel_crtc->unpin_work;
11404 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11405 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11406 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11407 page_flip_completed(intel_crtc);
11408 work = NULL;
11409 }
11410 if (work != NULL &&
11411 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11412 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11413 spin_unlock(&dev->event_lock);
11414 }
11415
11416 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11417 struct drm_framebuffer *fb,
11418 struct drm_pending_vblank_event *event,
11419 uint32_t page_flip_flags)
11420 {
11421 struct drm_device *dev = crtc->dev;
11422 struct drm_i915_private *dev_priv = dev->dev_private;
11423 struct drm_framebuffer *old_fb = crtc->primary->fb;
11424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11426 struct drm_plane *primary = crtc->primary;
11427 enum pipe pipe = intel_crtc->pipe;
11428 struct intel_unpin_work *work;
11429 struct intel_engine_cs *ring;
11430 bool mmio_flip;
11431 int ret;
11432
11433 /*
11434 * drm_mode_page_flip_ioctl() should already catch this, but double
11435 * check to be safe. In the future we may enable pageflipping from
11436 * a disabled primary plane.
11437 */
11438 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11439 return -EBUSY;
11440
11441 /* Can't change pixel format via MI display flips. */
11442 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11443 return -EINVAL;
11444
11445 /*
11446 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11447 * Note that pitch changes could also affect these register.
11448 */
11449 if (INTEL_INFO(dev)->gen > 3 &&
11450 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11451 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11452 return -EINVAL;
11453
11454 if (i915_terminally_wedged(&dev_priv->gpu_error))
11455 goto out_hang;
11456
11457 work = kzalloc(sizeof(*work), GFP_KERNEL);
11458 if (work == NULL)
11459 return -ENOMEM;
11460
11461 work->event = event;
11462 work->crtc = crtc;
11463 work->old_fb = old_fb;
11464 INIT_WORK(&work->work, intel_unpin_work_fn);
11465
11466 ret = drm_crtc_vblank_get(crtc);
11467 if (ret)
11468 goto free_work;
11469
11470 /* We borrow the event spin lock for protecting unpin_work */
11471 spin_lock_irq(&dev->event_lock);
11472 if (intel_crtc->unpin_work) {
11473 /* Before declaring the flip queue wedged, check if
11474 * the hardware completed the operation behind our backs.
11475 */
11476 if (__intel_pageflip_stall_check(dev, crtc)) {
11477 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11478 page_flip_completed(intel_crtc);
11479 } else {
11480 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11481 spin_unlock_irq(&dev->event_lock);
11482
11483 drm_crtc_vblank_put(crtc);
11484 kfree(work);
11485 return -EBUSY;
11486 }
11487 }
11488 intel_crtc->unpin_work = work;
11489 spin_unlock_irq(&dev->event_lock);
11490
11491 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11492 flush_workqueue(dev_priv->wq);
11493
11494 /* Reference the objects for the scheduled work. */
11495 drm_framebuffer_reference(work->old_fb);
11496 drm_gem_object_reference(&obj->base);
11497
11498 crtc->primary->fb = fb;
11499 update_state_fb(crtc->primary);
11500
11501 work->pending_flip_obj = obj;
11502
11503 ret = i915_mutex_lock_interruptible(dev);
11504 if (ret)
11505 goto cleanup;
11506
11507 atomic_inc(&intel_crtc->unpin_work_count);
11508 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11509
11510 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11511 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11512
11513 if (IS_VALLEYVIEW(dev)) {
11514 ring = &dev_priv->ring[BCS];
11515 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11516 /* vlv: DISPLAY_FLIP fails to change tiling */
11517 ring = NULL;
11518 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11519 ring = &dev_priv->ring[BCS];
11520 } else if (INTEL_INFO(dev)->gen >= 7) {
11521 ring = i915_gem_request_get_ring(obj->last_write_req);
11522 if (ring == NULL || ring->id != RCS)
11523 ring = &dev_priv->ring[BCS];
11524 } else {
11525 ring = &dev_priv->ring[RCS];
11526 }
11527
11528 mmio_flip = use_mmio_flip(ring, obj);
11529
11530 /* When using CS flips, we want to emit semaphores between rings.
11531 * However, when using mmio flips we will create a task to do the
11532 * synchronisation, so all we want here is to pin the framebuffer
11533 * into the display plane and skip any waits.
11534 */
11535 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11536 crtc->primary->state,
11537 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11538 if (ret)
11539 goto cleanup_pending;
11540
11541 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11542 + intel_crtc->dspaddr_offset;
11543
11544 if (mmio_flip) {
11545 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11546 page_flip_flags);
11547 if (ret)
11548 goto cleanup_unpin;
11549
11550 i915_gem_request_assign(&work->flip_queued_req,
11551 obj->last_write_req);
11552 } else {
11553 if (obj->last_write_req) {
11554 ret = i915_gem_check_olr(obj->last_write_req);
11555 if (ret)
11556 goto cleanup_unpin;
11557 }
11558
11559 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11560 page_flip_flags);
11561 if (ret)
11562 goto cleanup_unpin;
11563
11564 i915_gem_request_assign(&work->flip_queued_req,
11565 intel_ring_get_request(ring));
11566 }
11567
11568 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11569 work->enable_stall_check = true;
11570
11571 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11572 INTEL_FRONTBUFFER_PRIMARY(pipe));
11573
11574 intel_fbc_disable(dev);
11575 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11576 mutex_unlock(&dev->struct_mutex);
11577
11578 trace_i915_flip_request(intel_crtc->plane, obj);
11579
11580 return 0;
11581
11582 cleanup_unpin:
11583 intel_unpin_fb_obj(fb, crtc->primary->state);
11584 cleanup_pending:
11585 atomic_dec(&intel_crtc->unpin_work_count);
11586 mutex_unlock(&dev->struct_mutex);
11587 cleanup:
11588 crtc->primary->fb = old_fb;
11589 update_state_fb(crtc->primary);
11590
11591 drm_gem_object_unreference_unlocked(&obj->base);
11592 drm_framebuffer_unreference(work->old_fb);
11593
11594 spin_lock_irq(&dev->event_lock);
11595 intel_crtc->unpin_work = NULL;
11596 spin_unlock_irq(&dev->event_lock);
11597
11598 drm_crtc_vblank_put(crtc);
11599 free_work:
11600 kfree(work);
11601
11602 if (ret == -EIO) {
11603 struct drm_atomic_state *state;
11604 struct drm_plane_state *plane_state;
11605
11606 out_hang:
11607 state = drm_atomic_state_alloc(dev);
11608 if (!state)
11609 return -ENOMEM;
11610 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11611
11612 retry:
11613 plane_state = drm_atomic_get_plane_state(state, primary);
11614 ret = PTR_ERR_OR_ZERO(plane_state);
11615 if (!ret) {
11616 drm_atomic_set_fb_for_plane(plane_state, fb);
11617
11618 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11619 if (!ret)
11620 ret = drm_atomic_commit(state);
11621 }
11622
11623 if (ret == -EDEADLK) {
11624 drm_modeset_backoff(state->acquire_ctx);
11625 drm_atomic_state_clear(state);
11626 goto retry;
11627 }
11628
11629 if (ret)
11630 drm_atomic_state_free(state);
11631
11632 if (ret == 0 && event) {
11633 spin_lock_irq(&dev->event_lock);
11634 drm_send_vblank_event(dev, pipe, event);
11635 spin_unlock_irq(&dev->event_lock);
11636 }
11637 }
11638 return ret;
11639 }
11640
11641
11642 /**
11643 * intel_wm_need_update - Check whether watermarks need updating
11644 * @plane: drm plane
11645 * @state: new plane state
11646 *
11647 * Check current plane state versus the new one to determine whether
11648 * watermarks need to be recalculated.
11649 *
11650 * Returns true or false.
11651 */
11652 static bool intel_wm_need_update(struct drm_plane *plane,
11653 struct drm_plane_state *state)
11654 {
11655 /* Update watermarks on tiling changes. */
11656 if (!plane->state->fb || !state->fb ||
11657 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11658 plane->state->rotation != state->rotation)
11659 return true;
11660
11661 if (plane->state->crtc_w != state->crtc_w)
11662 return true;
11663
11664 return false;
11665 }
11666
11667 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11668 struct drm_plane_state *plane_state)
11669 {
11670 struct drm_crtc *crtc = crtc_state->crtc;
11671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11672 struct drm_plane *plane = plane_state->plane;
11673 struct drm_device *dev = crtc->dev;
11674 struct drm_i915_private *dev_priv = dev->dev_private;
11675 struct intel_plane_state *old_plane_state =
11676 to_intel_plane_state(plane->state);
11677 int idx = intel_crtc->base.base.id, ret;
11678 int i = drm_plane_index(plane);
11679 bool mode_changed = needs_modeset(crtc_state);
11680 bool was_crtc_enabled = crtc->state->active;
11681 bool is_crtc_enabled = crtc_state->active;
11682
11683 bool turn_off, turn_on, visible, was_visible;
11684 struct drm_framebuffer *fb = plane_state->fb;
11685
11686 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11687 plane->type != DRM_PLANE_TYPE_CURSOR) {
11688 ret = skl_update_scaler_plane(
11689 to_intel_crtc_state(crtc_state),
11690 to_intel_plane_state(plane_state));
11691 if (ret)
11692 return ret;
11693 }
11694
11695 /*
11696 * Disabling a plane is always okay; we just need to update
11697 * fb tracking in a special way since cleanup_fb() won't
11698 * get called by the plane helpers.
11699 */
11700 if (old_plane_state->base.fb && !fb)
11701 intel_crtc->atomic.disabled_planes |= 1 << i;
11702
11703 was_visible = old_plane_state->visible;
11704 visible = to_intel_plane_state(plane_state)->visible;
11705
11706 if (!was_crtc_enabled && WARN_ON(was_visible))
11707 was_visible = false;
11708
11709 if (!is_crtc_enabled && WARN_ON(visible))
11710 visible = false;
11711
11712 if (!was_visible && !visible)
11713 return 0;
11714
11715 turn_off = was_visible && (!visible || mode_changed);
11716 turn_on = visible && (!was_visible || mode_changed);
11717
11718 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11719 plane->base.id, fb ? fb->base.id : -1);
11720
11721 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11722 plane->base.id, was_visible, visible,
11723 turn_off, turn_on, mode_changed);
11724
11725 if (intel_wm_need_update(plane, plane_state))
11726 intel_crtc->atomic.update_wm = true;
11727
11728 switch (plane->type) {
11729 case DRM_PLANE_TYPE_PRIMARY:
11730 if (visible)
11731 intel_crtc->atomic.fb_bits |=
11732 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11733
11734 intel_crtc->atomic.wait_for_flips = true;
11735 intel_crtc->atomic.pre_disable_primary = turn_off;
11736 intel_crtc->atomic.post_enable_primary = turn_on;
11737
11738 if (turn_off)
11739 intel_crtc->atomic.disable_fbc = true;
11740
11741 /*
11742 * FBC does not work on some platforms for rotated
11743 * planes, so disable it when rotation is not 0 and
11744 * update it when rotation is set back to 0.
11745 *
11746 * FIXME: This is redundant with the fbc update done in
11747 * the primary plane enable function except that that
11748 * one is done too late. We eventually need to unify
11749 * this.
11750 */
11751
11752 if (visible &&
11753 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11754 dev_priv->fbc.crtc == intel_crtc &&
11755 plane_state->rotation != BIT(DRM_ROTATE_0))
11756 intel_crtc->atomic.disable_fbc = true;
11757
11758 /*
11759 * BDW signals flip done immediately if the plane
11760 * is disabled, even if the plane enable is already
11761 * armed to occur at the next vblank :(
11762 */
11763 if (turn_on && IS_BROADWELL(dev))
11764 intel_crtc->atomic.wait_vblank = true;
11765
11766 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11767 break;
11768 case DRM_PLANE_TYPE_CURSOR:
11769 if (visible)
11770 intel_crtc->atomic.fb_bits |=
11771 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11772 break;
11773 case DRM_PLANE_TYPE_OVERLAY:
11774 /*
11775 * 'prepare' is never called when plane is being disabled, so
11776 * we need to handle frontbuffer tracking as a special case
11777 */
11778 if (visible)
11779 intel_crtc->atomic.fb_bits |=
11780 INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11781
11782 if (turn_off && !mode_changed) {
11783 intel_crtc->atomic.wait_vblank = true;
11784 intel_crtc->atomic.update_sprite_watermarks |=
11785 1 << i;
11786 }
11787 break;
11788 }
11789 return 0;
11790 }
11791
11792 static bool encoders_cloneable(const struct intel_encoder *a,
11793 const struct intel_encoder *b)
11794 {
11795 /* masks could be asymmetric, so check both ways */
11796 return a == b || (a->cloneable & (1 << b->type) &&
11797 b->cloneable & (1 << a->type));
11798 }
11799
11800 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11801 struct intel_crtc *crtc,
11802 struct intel_encoder *encoder)
11803 {
11804 struct intel_encoder *source_encoder;
11805 struct drm_connector *connector;
11806 struct drm_connector_state *connector_state;
11807 int i;
11808
11809 for_each_connector_in_state(state, connector, connector_state, i) {
11810 if (connector_state->crtc != &crtc->base)
11811 continue;
11812
11813 source_encoder =
11814 to_intel_encoder(connector_state->best_encoder);
11815 if (!encoders_cloneable(encoder, source_encoder))
11816 return false;
11817 }
11818
11819 return true;
11820 }
11821
11822 static bool check_encoder_cloning(struct drm_atomic_state *state,
11823 struct intel_crtc *crtc)
11824 {
11825 struct intel_encoder *encoder;
11826 struct drm_connector *connector;
11827 struct drm_connector_state *connector_state;
11828 int i;
11829
11830 for_each_connector_in_state(state, connector, connector_state, i) {
11831 if (connector_state->crtc != &crtc->base)
11832 continue;
11833
11834 encoder = to_intel_encoder(connector_state->best_encoder);
11835 if (!check_single_encoder_cloning(state, crtc, encoder))
11836 return false;
11837 }
11838
11839 return true;
11840 }
11841
11842 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11843 struct drm_crtc_state *crtc_state)
11844 {
11845 struct intel_crtc_state *pipe_config =
11846 to_intel_crtc_state(crtc_state);
11847 struct drm_plane *p;
11848 unsigned visible_mask = 0;
11849
11850 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11851 struct drm_plane_state *plane_state =
11852 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11853
11854 if (WARN_ON(!plane_state))
11855 continue;
11856
11857 if (!plane_state->fb)
11858 crtc_state->plane_mask &=
11859 ~(1 << drm_plane_index(p));
11860 else if (to_intel_plane_state(plane_state)->visible)
11861 visible_mask |= 1 << drm_plane_index(p);
11862 }
11863
11864 if (!visible_mask)
11865 return;
11866
11867 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11868 }
11869
11870 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11871 struct drm_crtc_state *crtc_state)
11872 {
11873 struct drm_device *dev = crtc->dev;
11874 struct drm_i915_private *dev_priv = dev->dev_private;
11875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11876 struct intel_crtc_state *pipe_config =
11877 to_intel_crtc_state(crtc_state);
11878 struct drm_atomic_state *state = crtc_state->state;
11879 int ret, idx = crtc->base.id;
11880 bool mode_changed = needs_modeset(crtc_state);
11881
11882 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11883 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11884 return -EINVAL;
11885 }
11886
11887 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11888 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11889 idx, crtc->state->active, intel_crtc->active);
11890
11891 /* plane mask is fixed up after all initial planes are calculated */
11892 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11893 intel_crtc_check_initial_planes(crtc, crtc_state);
11894
11895 if (mode_changed)
11896 intel_crtc->atomic.update_wm = !crtc_state->active;
11897
11898 if (mode_changed && crtc_state->enable &&
11899 dev_priv->display.crtc_compute_clock &&
11900 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11901 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11902 pipe_config);
11903 if (ret)
11904 return ret;
11905 }
11906
11907 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11908 }
11909
11910 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11911 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11912 .load_lut = intel_crtc_load_lut,
11913 .atomic_begin = intel_begin_crtc_commit,
11914 .atomic_flush = intel_finish_crtc_commit,
11915 .atomic_check = intel_crtc_atomic_check,
11916 };
11917
11918 /**
11919 * intel_modeset_update_staged_output_state
11920 *
11921 * Updates the staged output configuration state, e.g. after we've read out the
11922 * current hw state.
11923 */
11924 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11925 {
11926 struct intel_crtc *crtc;
11927 struct intel_encoder *encoder;
11928 struct intel_connector *connector;
11929
11930 for_each_intel_connector(dev, connector) {
11931 connector->new_encoder =
11932 to_intel_encoder(connector->base.encoder);
11933 }
11934
11935 for_each_intel_encoder(dev, encoder) {
11936 encoder->new_crtc =
11937 to_intel_crtc(encoder->base.crtc);
11938 }
11939
11940 for_each_intel_crtc(dev, crtc) {
11941 crtc->new_enabled = crtc->base.state->enable;
11942 }
11943 }
11944
11945 /* Transitional helper to copy current connector/encoder state to
11946 * connector->state. This is needed so that code that is partially
11947 * converted to atomic does the right thing.
11948 */
11949 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11950 {
11951 struct intel_connector *connector;
11952
11953 for_each_intel_connector(dev, connector) {
11954 if (connector->base.encoder) {
11955 connector->base.state->best_encoder =
11956 connector->base.encoder;
11957 connector->base.state->crtc =
11958 connector->base.encoder->crtc;
11959 } else {
11960 connector->base.state->best_encoder = NULL;
11961 connector->base.state->crtc = NULL;
11962 }
11963 }
11964 }
11965
11966 static void
11967 connected_sink_compute_bpp(struct intel_connector *connector,
11968 struct intel_crtc_state *pipe_config)
11969 {
11970 int bpp = pipe_config->pipe_bpp;
11971
11972 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11973 connector->base.base.id,
11974 connector->base.name);
11975
11976 /* Don't use an invalid EDID bpc value */
11977 if (connector->base.display_info.bpc &&
11978 connector->base.display_info.bpc * 3 < bpp) {
11979 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11980 bpp, connector->base.display_info.bpc*3);
11981 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11982 }
11983
11984 /* Clamp bpp to 8 on screens without EDID 1.4 */
11985 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11986 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11987 bpp);
11988 pipe_config->pipe_bpp = 24;
11989 }
11990 }
11991
11992 static int
11993 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11994 struct intel_crtc_state *pipe_config)
11995 {
11996 struct drm_device *dev = crtc->base.dev;
11997 struct drm_atomic_state *state;
11998 struct drm_connector *connector;
11999 struct drm_connector_state *connector_state;
12000 int bpp, i;
12001
12002 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12003 bpp = 10*3;
12004 else if (INTEL_INFO(dev)->gen >= 5)
12005 bpp = 12*3;
12006 else
12007 bpp = 8*3;
12008
12009
12010 pipe_config->pipe_bpp = bpp;
12011
12012 state = pipe_config->base.state;
12013
12014 /* Clamp display bpp to EDID value */
12015 for_each_connector_in_state(state, connector, connector_state, i) {
12016 if (connector_state->crtc != &crtc->base)
12017 continue;
12018
12019 connected_sink_compute_bpp(to_intel_connector(connector),
12020 pipe_config);
12021 }
12022
12023 return bpp;
12024 }
12025
12026 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12027 {
12028 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12029 "type: 0x%x flags: 0x%x\n",
12030 mode->crtc_clock,
12031 mode->crtc_hdisplay, mode->crtc_hsync_start,
12032 mode->crtc_hsync_end, mode->crtc_htotal,
12033 mode->crtc_vdisplay, mode->crtc_vsync_start,
12034 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12035 }
12036
12037 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12038 struct intel_crtc_state *pipe_config,
12039 const char *context)
12040 {
12041 struct drm_device *dev = crtc->base.dev;
12042 struct drm_plane *plane;
12043 struct intel_plane *intel_plane;
12044 struct intel_plane_state *state;
12045 struct drm_framebuffer *fb;
12046
12047 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12048 context, pipe_config, pipe_name(crtc->pipe));
12049
12050 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12051 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12052 pipe_config->pipe_bpp, pipe_config->dither);
12053 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12054 pipe_config->has_pch_encoder,
12055 pipe_config->fdi_lanes,
12056 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12057 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12058 pipe_config->fdi_m_n.tu);
12059 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12060 pipe_config->has_dp_encoder,
12061 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12062 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12063 pipe_config->dp_m_n.tu);
12064
12065 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12066 pipe_config->has_dp_encoder,
12067 pipe_config->dp_m2_n2.gmch_m,
12068 pipe_config->dp_m2_n2.gmch_n,
12069 pipe_config->dp_m2_n2.link_m,
12070 pipe_config->dp_m2_n2.link_n,
12071 pipe_config->dp_m2_n2.tu);
12072
12073 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12074 pipe_config->has_audio,
12075 pipe_config->has_infoframe);
12076
12077 DRM_DEBUG_KMS("requested mode:\n");
12078 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12079 DRM_DEBUG_KMS("adjusted mode:\n");
12080 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12081 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12082 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12083 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12084 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12085 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12086 crtc->num_scalers,
12087 pipe_config->scaler_state.scaler_users,
12088 pipe_config->scaler_state.scaler_id);
12089 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12090 pipe_config->gmch_pfit.control,
12091 pipe_config->gmch_pfit.pgm_ratios,
12092 pipe_config->gmch_pfit.lvds_border_bits);
12093 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12094 pipe_config->pch_pfit.pos,
12095 pipe_config->pch_pfit.size,
12096 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12097 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12098 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12099
12100 if (IS_BROXTON(dev)) {
12101 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
12102 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12103 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
12104 pipe_config->ddi_pll_sel,
12105 pipe_config->dpll_hw_state.ebb0,
12106 pipe_config->dpll_hw_state.pll0,
12107 pipe_config->dpll_hw_state.pll1,
12108 pipe_config->dpll_hw_state.pll2,
12109 pipe_config->dpll_hw_state.pll3,
12110 pipe_config->dpll_hw_state.pll6,
12111 pipe_config->dpll_hw_state.pll8,
12112 pipe_config->dpll_hw_state.pcsdw12);
12113 } else if (IS_SKYLAKE(dev)) {
12114 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12115 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12116 pipe_config->ddi_pll_sel,
12117 pipe_config->dpll_hw_state.ctrl1,
12118 pipe_config->dpll_hw_state.cfgcr1,
12119 pipe_config->dpll_hw_state.cfgcr2);
12120 } else if (HAS_DDI(dev)) {
12121 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12122 pipe_config->ddi_pll_sel,
12123 pipe_config->dpll_hw_state.wrpll);
12124 } else {
12125 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12126 "fp0: 0x%x, fp1: 0x%x\n",
12127 pipe_config->dpll_hw_state.dpll,
12128 pipe_config->dpll_hw_state.dpll_md,
12129 pipe_config->dpll_hw_state.fp0,
12130 pipe_config->dpll_hw_state.fp1);
12131 }
12132
12133 DRM_DEBUG_KMS("planes on this crtc\n");
12134 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12135 intel_plane = to_intel_plane(plane);
12136 if (intel_plane->pipe != crtc->pipe)
12137 continue;
12138
12139 state = to_intel_plane_state(plane->state);
12140 fb = state->base.fb;
12141 if (!fb) {
12142 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12143 "disabled, scaler_id = %d\n",
12144 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12145 plane->base.id, intel_plane->pipe,
12146 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12147 drm_plane_index(plane), state->scaler_id);
12148 continue;
12149 }
12150
12151 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12152 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12153 plane->base.id, intel_plane->pipe,
12154 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12155 drm_plane_index(plane));
12156 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12157 fb->base.id, fb->width, fb->height, fb->pixel_format);
12158 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12159 state->scaler_id,
12160 state->src.x1 >> 16, state->src.y1 >> 16,
12161 drm_rect_width(&state->src) >> 16,
12162 drm_rect_height(&state->src) >> 16,
12163 state->dst.x1, state->dst.y1,
12164 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12165 }
12166 }
12167
12168 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12169 {
12170 struct drm_device *dev = state->dev;
12171 struct intel_encoder *encoder;
12172 struct drm_connector *connector;
12173 struct drm_connector_state *connector_state;
12174 unsigned int used_ports = 0;
12175 int i;
12176
12177 /*
12178 * Walk the connector list instead of the encoder
12179 * list to detect the problem on ddi platforms
12180 * where there's just one encoder per digital port.
12181 */
12182 for_each_connector_in_state(state, connector, connector_state, i) {
12183 if (!connector_state->best_encoder)
12184 continue;
12185
12186 encoder = to_intel_encoder(connector_state->best_encoder);
12187
12188 WARN_ON(!connector_state->crtc);
12189
12190 switch (encoder->type) {
12191 unsigned int port_mask;
12192 case INTEL_OUTPUT_UNKNOWN:
12193 if (WARN_ON(!HAS_DDI(dev)))
12194 break;
12195 case INTEL_OUTPUT_DISPLAYPORT:
12196 case INTEL_OUTPUT_HDMI:
12197 case INTEL_OUTPUT_EDP:
12198 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12199
12200 /* the same port mustn't appear more than once */
12201 if (used_ports & port_mask)
12202 return false;
12203
12204 used_ports |= port_mask;
12205 default:
12206 break;
12207 }
12208 }
12209
12210 return true;
12211 }
12212
12213 static void
12214 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12215 {
12216 struct drm_crtc_state tmp_state;
12217 struct intel_crtc_scaler_state scaler_state;
12218 struct intel_dpll_hw_state dpll_hw_state;
12219 enum intel_dpll_id shared_dpll;
12220 uint32_t ddi_pll_sel;
12221
12222 /* FIXME: before the switch to atomic started, a new pipe_config was
12223 * kzalloc'd. Code that depends on any field being zero should be
12224 * fixed, so that the crtc_state can be safely duplicated. For now,
12225 * only fields that are know to not cause problems are preserved. */
12226
12227 tmp_state = crtc_state->base;
12228 scaler_state = crtc_state->scaler_state;
12229 shared_dpll = crtc_state->shared_dpll;
12230 dpll_hw_state = crtc_state->dpll_hw_state;
12231 ddi_pll_sel = crtc_state->ddi_pll_sel;
12232
12233 memset(crtc_state, 0, sizeof *crtc_state);
12234
12235 crtc_state->base = tmp_state;
12236 crtc_state->scaler_state = scaler_state;
12237 crtc_state->shared_dpll = shared_dpll;
12238 crtc_state->dpll_hw_state = dpll_hw_state;
12239 crtc_state->ddi_pll_sel = ddi_pll_sel;
12240 }
12241
12242 static int
12243 intel_modeset_pipe_config(struct drm_crtc *crtc,
12244 struct intel_crtc_state *pipe_config)
12245 {
12246 struct drm_atomic_state *state = pipe_config->base.state;
12247 struct intel_encoder *encoder;
12248 struct drm_connector *connector;
12249 struct drm_connector_state *connector_state;
12250 int base_bpp, ret = -EINVAL;
12251 int i;
12252 bool retry = true;
12253
12254 clear_intel_crtc_state(pipe_config);
12255
12256 pipe_config->cpu_transcoder =
12257 (enum transcoder) to_intel_crtc(crtc)->pipe;
12258
12259 /*
12260 * Sanitize sync polarity flags based on requested ones. If neither
12261 * positive or negative polarity is requested, treat this as meaning
12262 * negative polarity.
12263 */
12264 if (!(pipe_config->base.adjusted_mode.flags &
12265 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12266 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12267
12268 if (!(pipe_config->base.adjusted_mode.flags &
12269 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12270 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12271
12272 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12273 * plane pixel format and any sink constraints into account. Returns the
12274 * source plane bpp so that dithering can be selected on mismatches
12275 * after encoders and crtc also have had their say. */
12276 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12277 pipe_config);
12278 if (base_bpp < 0)
12279 goto fail;
12280
12281 /*
12282 * Determine the real pipe dimensions. Note that stereo modes can
12283 * increase the actual pipe size due to the frame doubling and
12284 * insertion of additional space for blanks between the frame. This
12285 * is stored in the crtc timings. We use the requested mode to do this
12286 * computation to clearly distinguish it from the adjusted mode, which
12287 * can be changed by the connectors in the below retry loop.
12288 */
12289 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12290 &pipe_config->pipe_src_w,
12291 &pipe_config->pipe_src_h);
12292
12293 encoder_retry:
12294 /* Ensure the port clock defaults are reset when retrying. */
12295 pipe_config->port_clock = 0;
12296 pipe_config->pixel_multiplier = 1;
12297
12298 /* Fill in default crtc timings, allow encoders to overwrite them. */
12299 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12300 CRTC_STEREO_DOUBLE);
12301
12302 /* Pass our mode to the connectors and the CRTC to give them a chance to
12303 * adjust it according to limitations or connector properties, and also
12304 * a chance to reject the mode entirely.
12305 */
12306 for_each_connector_in_state(state, connector, connector_state, i) {
12307 if (connector_state->crtc != crtc)
12308 continue;
12309
12310 encoder = to_intel_encoder(connector_state->best_encoder);
12311
12312 if (!(encoder->compute_config(encoder, pipe_config))) {
12313 DRM_DEBUG_KMS("Encoder config failure\n");
12314 goto fail;
12315 }
12316 }
12317
12318 /* Set default port clock if not overwritten by the encoder. Needs to be
12319 * done afterwards in case the encoder adjusts the mode. */
12320 if (!pipe_config->port_clock)
12321 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12322 * pipe_config->pixel_multiplier;
12323
12324 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12325 if (ret < 0) {
12326 DRM_DEBUG_KMS("CRTC fixup failed\n");
12327 goto fail;
12328 }
12329
12330 if (ret == RETRY) {
12331 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12332 ret = -EINVAL;
12333 goto fail;
12334 }
12335
12336 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12337 retry = false;
12338 goto encoder_retry;
12339 }
12340
12341 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12342 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12343 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12344
12345 /* Check if we need to force a modeset */
12346 if (pipe_config->has_audio !=
12347 to_intel_crtc_state(crtc->state)->has_audio) {
12348 pipe_config->base.mode_changed = true;
12349 ret = drm_atomic_add_affected_planes(state, crtc);
12350 }
12351
12352 /*
12353 * Note we have an issue here with infoframes: current code
12354 * only updates them on the full mode set path per hw
12355 * requirements. So here we should be checking for any
12356 * required changes and forcing a mode set.
12357 */
12358 fail:
12359 return ret;
12360 }
12361
12362 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12363 {
12364 struct drm_encoder *encoder;
12365 struct drm_device *dev = crtc->dev;
12366
12367 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12368 if (encoder->crtc == crtc)
12369 return true;
12370
12371 return false;
12372 }
12373
12374 static void
12375 intel_modeset_update_state(struct drm_atomic_state *state)
12376 {
12377 struct drm_device *dev = state->dev;
12378 struct intel_encoder *intel_encoder;
12379 struct drm_crtc *crtc;
12380 struct drm_crtc_state *crtc_state;
12381 struct drm_connector *connector;
12382
12383 intel_shared_dpll_commit(state);
12384
12385 for_each_intel_encoder(dev, intel_encoder) {
12386 if (!intel_encoder->base.crtc)
12387 continue;
12388
12389 crtc = intel_encoder->base.crtc;
12390 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12391 if (!crtc_state || !needs_modeset(crtc->state))
12392 continue;
12393
12394 intel_encoder->connectors_active = false;
12395 }
12396
12397 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12398 intel_modeset_update_staged_output_state(state->dev);
12399
12400 /* Double check state. */
12401 for_each_crtc(dev, crtc) {
12402 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12403
12404 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12405
12406 /* Update hwmode for vblank functions */
12407 if (crtc->state->active)
12408 crtc->hwmode = crtc->state->adjusted_mode;
12409 else
12410 crtc->hwmode.crtc_clock = 0;
12411 }
12412
12413 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12414 if (!connector->encoder || !connector->encoder->crtc)
12415 continue;
12416
12417 crtc = connector->encoder->crtc;
12418 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12419 if (!crtc_state || !needs_modeset(crtc->state))
12420 continue;
12421
12422 if (crtc->state->active) {
12423 struct drm_property *dpms_property =
12424 dev->mode_config.dpms_property;
12425
12426 connector->dpms = DRM_MODE_DPMS_ON;
12427 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12428
12429 intel_encoder = to_intel_encoder(connector->encoder);
12430 intel_encoder->connectors_active = true;
12431 } else
12432 connector->dpms = DRM_MODE_DPMS_OFF;
12433 }
12434 }
12435
12436 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12437 {
12438 int diff;
12439
12440 if (clock1 == clock2)
12441 return true;
12442
12443 if (!clock1 || !clock2)
12444 return false;
12445
12446 diff = abs(clock1 - clock2);
12447
12448 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12449 return true;
12450
12451 return false;
12452 }
12453
12454 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12455 list_for_each_entry((intel_crtc), \
12456 &(dev)->mode_config.crtc_list, \
12457 base.head) \
12458 if (mask & (1 <<(intel_crtc)->pipe))
12459
12460 static bool
12461 intel_pipe_config_compare(struct drm_device *dev,
12462 struct intel_crtc_state *current_config,
12463 struct intel_crtc_state *pipe_config)
12464 {
12465 #define PIPE_CONF_CHECK_X(name) \
12466 if (current_config->name != pipe_config->name) { \
12467 DRM_ERROR("mismatch in " #name " " \
12468 "(expected 0x%08x, found 0x%08x)\n", \
12469 current_config->name, \
12470 pipe_config->name); \
12471 return false; \
12472 }
12473
12474 #define PIPE_CONF_CHECK_I(name) \
12475 if (current_config->name != pipe_config->name) { \
12476 DRM_ERROR("mismatch in " #name " " \
12477 "(expected %i, found %i)\n", \
12478 current_config->name, \
12479 pipe_config->name); \
12480 return false; \
12481 }
12482
12483 /* This is required for BDW+ where there is only one set of registers for
12484 * switching between high and low RR.
12485 * This macro can be used whenever a comparison has to be made between one
12486 * hw state and multiple sw state variables.
12487 */
12488 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12489 if ((current_config->name != pipe_config->name) && \
12490 (current_config->alt_name != pipe_config->name)) { \
12491 DRM_ERROR("mismatch in " #name " " \
12492 "(expected %i or %i, found %i)\n", \
12493 current_config->name, \
12494 current_config->alt_name, \
12495 pipe_config->name); \
12496 return false; \
12497 }
12498
12499 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12500 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12501 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12502 "(expected %i, found %i)\n", \
12503 current_config->name & (mask), \
12504 pipe_config->name & (mask)); \
12505 return false; \
12506 }
12507
12508 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12509 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12510 DRM_ERROR("mismatch in " #name " " \
12511 "(expected %i, found %i)\n", \
12512 current_config->name, \
12513 pipe_config->name); \
12514 return false; \
12515 }
12516
12517 #define PIPE_CONF_QUIRK(quirk) \
12518 ((current_config->quirks | pipe_config->quirks) & (quirk))
12519
12520 PIPE_CONF_CHECK_I(cpu_transcoder);
12521
12522 PIPE_CONF_CHECK_I(has_pch_encoder);
12523 PIPE_CONF_CHECK_I(fdi_lanes);
12524 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12525 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12526 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12527 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12528 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12529
12530 PIPE_CONF_CHECK_I(has_dp_encoder);
12531
12532 if (INTEL_INFO(dev)->gen < 8) {
12533 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12534 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12535 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12536 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12537 PIPE_CONF_CHECK_I(dp_m_n.tu);
12538
12539 if (current_config->has_drrs) {
12540 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12541 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12542 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12543 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12544 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12545 }
12546 } else {
12547 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12548 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12549 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12550 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12551 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12552 }
12553
12554 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12555 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12556 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12557 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12558 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12559 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12560
12561 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12562 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12563 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12564 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12565 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12566 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12567
12568 PIPE_CONF_CHECK_I(pixel_multiplier);
12569 PIPE_CONF_CHECK_I(has_hdmi_sink);
12570 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12571 IS_VALLEYVIEW(dev))
12572 PIPE_CONF_CHECK_I(limited_color_range);
12573 PIPE_CONF_CHECK_I(has_infoframe);
12574
12575 PIPE_CONF_CHECK_I(has_audio);
12576
12577 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12578 DRM_MODE_FLAG_INTERLACE);
12579
12580 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12581 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12582 DRM_MODE_FLAG_PHSYNC);
12583 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12584 DRM_MODE_FLAG_NHSYNC);
12585 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12586 DRM_MODE_FLAG_PVSYNC);
12587 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12588 DRM_MODE_FLAG_NVSYNC);
12589 }
12590
12591 PIPE_CONF_CHECK_I(pipe_src_w);
12592 PIPE_CONF_CHECK_I(pipe_src_h);
12593
12594 /*
12595 * FIXME: BIOS likes to set up a cloned config with lvds+external
12596 * screen. Since we don't yet re-compute the pipe config when moving
12597 * just the lvds port away to another pipe the sw tracking won't match.
12598 *
12599 * Proper atomic modesets with recomputed global state will fix this.
12600 * Until then just don't check gmch state for inherited modes.
12601 */
12602 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12603 PIPE_CONF_CHECK_I(gmch_pfit.control);
12604 /* pfit ratios are autocomputed by the hw on gen4+ */
12605 if (INTEL_INFO(dev)->gen < 4)
12606 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12607 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12608 }
12609
12610 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12611 if (current_config->pch_pfit.enabled) {
12612 PIPE_CONF_CHECK_I(pch_pfit.pos);
12613 PIPE_CONF_CHECK_I(pch_pfit.size);
12614 }
12615
12616 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12617
12618 /* BDW+ don't expose a synchronous way to read the state */
12619 if (IS_HASWELL(dev))
12620 PIPE_CONF_CHECK_I(ips_enabled);
12621
12622 PIPE_CONF_CHECK_I(double_wide);
12623
12624 PIPE_CONF_CHECK_X(ddi_pll_sel);
12625
12626 PIPE_CONF_CHECK_I(shared_dpll);
12627 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12628 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12629 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12630 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12631 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12632 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12633 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12634 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12635
12636 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12637 PIPE_CONF_CHECK_I(pipe_bpp);
12638
12639 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12640 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12641
12642 #undef PIPE_CONF_CHECK_X
12643 #undef PIPE_CONF_CHECK_I
12644 #undef PIPE_CONF_CHECK_I_ALT
12645 #undef PIPE_CONF_CHECK_FLAGS
12646 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12647 #undef PIPE_CONF_QUIRK
12648
12649 return true;
12650 }
12651
12652 static void check_wm_state(struct drm_device *dev)
12653 {
12654 struct drm_i915_private *dev_priv = dev->dev_private;
12655 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12656 struct intel_crtc *intel_crtc;
12657 int plane;
12658
12659 if (INTEL_INFO(dev)->gen < 9)
12660 return;
12661
12662 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12663 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12664
12665 for_each_intel_crtc(dev, intel_crtc) {
12666 struct skl_ddb_entry *hw_entry, *sw_entry;
12667 const enum pipe pipe = intel_crtc->pipe;
12668
12669 if (!intel_crtc->active)
12670 continue;
12671
12672 /* planes */
12673 for_each_plane(dev_priv, pipe, plane) {
12674 hw_entry = &hw_ddb.plane[pipe][plane];
12675 sw_entry = &sw_ddb->plane[pipe][plane];
12676
12677 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12678 continue;
12679
12680 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12681 "(expected (%u,%u), found (%u,%u))\n",
12682 pipe_name(pipe), plane + 1,
12683 sw_entry->start, sw_entry->end,
12684 hw_entry->start, hw_entry->end);
12685 }
12686
12687 /* cursor */
12688 hw_entry = &hw_ddb.cursor[pipe];
12689 sw_entry = &sw_ddb->cursor[pipe];
12690
12691 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12692 continue;
12693
12694 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12695 "(expected (%u,%u), found (%u,%u))\n",
12696 pipe_name(pipe),
12697 sw_entry->start, sw_entry->end,
12698 hw_entry->start, hw_entry->end);
12699 }
12700 }
12701
12702 static void
12703 check_connector_state(struct drm_device *dev)
12704 {
12705 struct intel_connector *connector;
12706
12707 for_each_intel_connector(dev, connector) {
12708 /* This also checks the encoder/connector hw state with the
12709 * ->get_hw_state callbacks. */
12710 intel_connector_check_state(connector);
12711
12712 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12713 "connector's staged encoder doesn't match current encoder\n");
12714 }
12715 }
12716
12717 static void
12718 check_encoder_state(struct drm_device *dev)
12719 {
12720 struct intel_encoder *encoder;
12721 struct intel_connector *connector;
12722
12723 for_each_intel_encoder(dev, encoder) {
12724 bool enabled = false;
12725 bool active = false;
12726 enum pipe pipe, tracked_pipe;
12727
12728 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12729 encoder->base.base.id,
12730 encoder->base.name);
12731
12732 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12733 "encoder's stage crtc doesn't match current crtc\n");
12734 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12735 "encoder's active_connectors set, but no crtc\n");
12736
12737 for_each_intel_connector(dev, connector) {
12738 if (connector->base.encoder != &encoder->base)
12739 continue;
12740 enabled = true;
12741 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12742 active = true;
12743 }
12744 /*
12745 * for MST connectors if we unplug the connector is gone
12746 * away but the encoder is still connected to a crtc
12747 * until a modeset happens in response to the hotplug.
12748 */
12749 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12750 continue;
12751
12752 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12753 "encoder's enabled state mismatch "
12754 "(expected %i, found %i)\n",
12755 !!encoder->base.crtc, enabled);
12756 I915_STATE_WARN(active && !encoder->base.crtc,
12757 "active encoder with no crtc\n");
12758
12759 I915_STATE_WARN(encoder->connectors_active != active,
12760 "encoder's computed active state doesn't match tracked active state "
12761 "(expected %i, found %i)\n", active, encoder->connectors_active);
12762
12763 active = encoder->get_hw_state(encoder, &pipe);
12764 I915_STATE_WARN(active != encoder->connectors_active,
12765 "encoder's hw state doesn't match sw tracking "
12766 "(expected %i, found %i)\n",
12767 encoder->connectors_active, active);
12768
12769 if (!encoder->base.crtc)
12770 continue;
12771
12772 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12773 I915_STATE_WARN(active && pipe != tracked_pipe,
12774 "active encoder's pipe doesn't match"
12775 "(expected %i, found %i)\n",
12776 tracked_pipe, pipe);
12777
12778 }
12779 }
12780
12781 static void
12782 check_crtc_state(struct drm_device *dev)
12783 {
12784 struct drm_i915_private *dev_priv = dev->dev_private;
12785 struct intel_crtc *crtc;
12786 struct intel_encoder *encoder;
12787 struct intel_crtc_state pipe_config;
12788
12789 for_each_intel_crtc(dev, crtc) {
12790 bool enabled = false;
12791 bool active = false;
12792
12793 memset(&pipe_config, 0, sizeof(pipe_config));
12794
12795 DRM_DEBUG_KMS("[CRTC:%d]\n",
12796 crtc->base.base.id);
12797
12798 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12799 "active crtc, but not enabled in sw tracking\n");
12800
12801 for_each_intel_encoder(dev, encoder) {
12802 if (encoder->base.crtc != &crtc->base)
12803 continue;
12804 enabled = true;
12805 if (encoder->connectors_active)
12806 active = true;
12807 }
12808
12809 I915_STATE_WARN(active != crtc->active,
12810 "crtc's computed active state doesn't match tracked active state "
12811 "(expected %i, found %i)\n", active, crtc->active);
12812 I915_STATE_WARN(enabled != crtc->base.state->enable,
12813 "crtc's computed enabled state doesn't match tracked enabled state "
12814 "(expected %i, found %i)\n", enabled,
12815 crtc->base.state->enable);
12816
12817 active = dev_priv->display.get_pipe_config(crtc,
12818 &pipe_config);
12819
12820 /* hw state is inconsistent with the pipe quirk */
12821 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12822 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12823 active = crtc->active;
12824
12825 for_each_intel_encoder(dev, encoder) {
12826 enum pipe pipe;
12827 if (encoder->base.crtc != &crtc->base)
12828 continue;
12829 if (encoder->get_hw_state(encoder, &pipe))
12830 encoder->get_config(encoder, &pipe_config);
12831 }
12832
12833 I915_STATE_WARN(crtc->active != active,
12834 "crtc active state doesn't match with hw state "
12835 "(expected %i, found %i)\n", crtc->active, active);
12836
12837 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12838 "transitional active state does not match atomic hw state "
12839 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12840
12841 if (active &&
12842 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12843 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12844 intel_dump_pipe_config(crtc, &pipe_config,
12845 "[hw state]");
12846 intel_dump_pipe_config(crtc, crtc->config,
12847 "[sw state]");
12848 }
12849 }
12850 }
12851
12852 static void
12853 check_shared_dpll_state(struct drm_device *dev)
12854 {
12855 struct drm_i915_private *dev_priv = dev->dev_private;
12856 struct intel_crtc *crtc;
12857 struct intel_dpll_hw_state dpll_hw_state;
12858 int i;
12859
12860 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12861 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12862 int enabled_crtcs = 0, active_crtcs = 0;
12863 bool active;
12864
12865 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12866
12867 DRM_DEBUG_KMS("%s\n", pll->name);
12868
12869 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12870
12871 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12872 "more active pll users than references: %i vs %i\n",
12873 pll->active, hweight32(pll->config.crtc_mask));
12874 I915_STATE_WARN(pll->active && !pll->on,
12875 "pll in active use but not on in sw tracking\n");
12876 I915_STATE_WARN(pll->on && !pll->active,
12877 "pll in on but not on in use in sw tracking\n");
12878 I915_STATE_WARN(pll->on != active,
12879 "pll on state mismatch (expected %i, found %i)\n",
12880 pll->on, active);
12881
12882 for_each_intel_crtc(dev, crtc) {
12883 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12884 enabled_crtcs++;
12885 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12886 active_crtcs++;
12887 }
12888 I915_STATE_WARN(pll->active != active_crtcs,
12889 "pll active crtcs mismatch (expected %i, found %i)\n",
12890 pll->active, active_crtcs);
12891 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12892 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12893 hweight32(pll->config.crtc_mask), enabled_crtcs);
12894
12895 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12896 sizeof(dpll_hw_state)),
12897 "pll hw state mismatch\n");
12898 }
12899 }
12900
12901 void
12902 intel_modeset_check_state(struct drm_device *dev)
12903 {
12904 check_wm_state(dev);
12905 check_connector_state(dev);
12906 check_encoder_state(dev);
12907 check_crtc_state(dev);
12908 check_shared_dpll_state(dev);
12909 }
12910
12911 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12912 int dotclock)
12913 {
12914 /*
12915 * FDI already provided one idea for the dotclock.
12916 * Yell if the encoder disagrees.
12917 */
12918 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12919 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12920 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12921 }
12922
12923 static void update_scanline_offset(struct intel_crtc *crtc)
12924 {
12925 struct drm_device *dev = crtc->base.dev;
12926
12927 /*
12928 * The scanline counter increments at the leading edge of hsync.
12929 *
12930 * On most platforms it starts counting from vtotal-1 on the
12931 * first active line. That means the scanline counter value is
12932 * always one less than what we would expect. Ie. just after
12933 * start of vblank, which also occurs at start of hsync (on the
12934 * last active line), the scanline counter will read vblank_start-1.
12935 *
12936 * On gen2 the scanline counter starts counting from 1 instead
12937 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12938 * to keep the value positive), instead of adding one.
12939 *
12940 * On HSW+ the behaviour of the scanline counter depends on the output
12941 * type. For DP ports it behaves like most other platforms, but on HDMI
12942 * there's an extra 1 line difference. So we need to add two instead of
12943 * one to the value.
12944 */
12945 if (IS_GEN2(dev)) {
12946 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12947 int vtotal;
12948
12949 vtotal = mode->crtc_vtotal;
12950 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12951 vtotal /= 2;
12952
12953 crtc->scanline_offset = vtotal - 1;
12954 } else if (HAS_DDI(dev) &&
12955 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12956 crtc->scanline_offset = 2;
12957 } else
12958 crtc->scanline_offset = 1;
12959 }
12960
12961 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12962 {
12963 struct drm_device *dev = state->dev;
12964 struct drm_i915_private *dev_priv = to_i915(dev);
12965 struct intel_shared_dpll_config *shared_dpll = NULL;
12966 struct intel_crtc *intel_crtc;
12967 struct intel_crtc_state *intel_crtc_state;
12968 struct drm_crtc *crtc;
12969 struct drm_crtc_state *crtc_state;
12970 int i;
12971
12972 if (!dev_priv->display.crtc_compute_clock)
12973 return;
12974
12975 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12976 int dpll;
12977
12978 intel_crtc = to_intel_crtc(crtc);
12979 intel_crtc_state = to_intel_crtc_state(crtc_state);
12980 dpll = intel_crtc_state->shared_dpll;
12981
12982 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12983 continue;
12984
12985 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12986
12987 if (!shared_dpll)
12988 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12989
12990 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12991 }
12992 }
12993
12994 /*
12995 * This implements the workaround described in the "notes" section of the mode
12996 * set sequence documentation. When going from no pipes or single pipe to
12997 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12998 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12999 */
13000 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13001 {
13002 struct drm_crtc_state *crtc_state;
13003 struct intel_crtc *intel_crtc;
13004 struct drm_crtc *crtc;
13005 struct intel_crtc_state *first_crtc_state = NULL;
13006 struct intel_crtc_state *other_crtc_state = NULL;
13007 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13008 int i;
13009
13010 /* look at all crtc's that are going to be enabled in during modeset */
13011 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13012 intel_crtc = to_intel_crtc(crtc);
13013
13014 if (!crtc_state->active || !needs_modeset(crtc_state))
13015 continue;
13016
13017 if (first_crtc_state) {
13018 other_crtc_state = to_intel_crtc_state(crtc_state);
13019 break;
13020 } else {
13021 first_crtc_state = to_intel_crtc_state(crtc_state);
13022 first_pipe = intel_crtc->pipe;
13023 }
13024 }
13025
13026 /* No workaround needed? */
13027 if (!first_crtc_state)
13028 return 0;
13029
13030 /* w/a possibly needed, check how many crtc's are already enabled. */
13031 for_each_intel_crtc(state->dev, intel_crtc) {
13032 struct intel_crtc_state *pipe_config;
13033
13034 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13035 if (IS_ERR(pipe_config))
13036 return PTR_ERR(pipe_config);
13037
13038 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13039
13040 if (!pipe_config->base.active ||
13041 needs_modeset(&pipe_config->base))
13042 continue;
13043
13044 /* 2 or more enabled crtcs means no need for w/a */
13045 if (enabled_pipe != INVALID_PIPE)
13046 return 0;
13047
13048 enabled_pipe = intel_crtc->pipe;
13049 }
13050
13051 if (enabled_pipe != INVALID_PIPE)
13052 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13053 else if (other_crtc_state)
13054 other_crtc_state->hsw_workaround_pipe = first_pipe;
13055
13056 return 0;
13057 }
13058
13059 /* Code that should eventually be part of atomic_check() */
13060 static int intel_modeset_checks(struct drm_atomic_state *state)
13061 {
13062 struct drm_device *dev = state->dev;
13063 int ret;
13064
13065 if (!check_digital_port_conflicts(state)) {
13066 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13067 return -EINVAL;
13068 }
13069
13070 /*
13071 * See if the config requires any additional preparation, e.g.
13072 * to adjust global state with pipes off. We need to do this
13073 * here so we can get the modeset_pipe updated config for the new
13074 * mode set on this crtc. For other crtcs we need to use the
13075 * adjusted_mode bits in the crtc directly.
13076 */
13077 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
13078 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
13079 ret = valleyview_modeset_global_pipes(state);
13080 else
13081 ret = broadwell_modeset_global_pipes(state);
13082
13083 if (ret)
13084 return ret;
13085 }
13086
13087 intel_modeset_clear_plls(state);
13088
13089 if (IS_HASWELL(dev))
13090 return haswell_mode_set_planes_workaround(state);
13091
13092 return 0;
13093 }
13094
13095 static int
13096 intel_modeset_compute_config(struct drm_atomic_state *state)
13097 {
13098 struct drm_crtc *crtc;
13099 struct drm_crtc_state *crtc_state;
13100 int ret, i;
13101 bool any_ms = false;
13102
13103 ret = drm_atomic_helper_check_modeset(state->dev, state);
13104 if (ret)
13105 return ret;
13106
13107 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13108 if (!crtc_state->enable) {
13109 if (needs_modeset(crtc_state))
13110 any_ms = true;
13111 continue;
13112 }
13113
13114 if (to_intel_crtc_state(crtc_state)->quirks &
13115 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13116 ret = drm_atomic_add_affected_planes(state, crtc);
13117 if (ret)
13118 return ret;
13119
13120 /*
13121 * We ought to handle i915.fastboot here.
13122 * If no modeset is required and the primary plane has
13123 * a fb, update the members of crtc_state as needed,
13124 * and run the necessary updates during vblank evasion.
13125 */
13126 }
13127
13128 if (!needs_modeset(crtc_state)) {
13129 ret = drm_atomic_add_affected_connectors(state, crtc);
13130 if (ret)
13131 return ret;
13132 }
13133
13134 ret = intel_modeset_pipe_config(crtc,
13135 to_intel_crtc_state(crtc_state));
13136 if (ret)
13137 return ret;
13138
13139 if (needs_modeset(crtc_state))
13140 any_ms = true;
13141
13142 intel_dump_pipe_config(to_intel_crtc(crtc),
13143 to_intel_crtc_state(crtc_state),
13144 "[modeset]");
13145 }
13146
13147 if (any_ms) {
13148 ret = intel_modeset_checks(state);
13149
13150 if (ret)
13151 return ret;
13152 }
13153
13154 return drm_atomic_helper_check_planes(state->dev, state);
13155 }
13156
13157 static int __intel_set_mode(struct drm_atomic_state *state)
13158 {
13159 struct drm_device *dev = state->dev;
13160 struct drm_i915_private *dev_priv = dev->dev_private;
13161 struct drm_crtc *crtc;
13162 struct drm_crtc_state *crtc_state;
13163 int ret = 0;
13164 int i;
13165 bool any_ms = false;
13166
13167 ret = drm_atomic_helper_prepare_planes(dev, state);
13168 if (ret)
13169 return ret;
13170
13171 drm_atomic_helper_swap_state(dev, state);
13172
13173 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13175
13176 if (!needs_modeset(crtc->state))
13177 continue;
13178
13179 any_ms = true;
13180 intel_pre_plane_update(intel_crtc);
13181
13182 if (crtc_state->active) {
13183 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13184 dev_priv->display.crtc_disable(crtc);
13185 intel_crtc->active = false;
13186 intel_disable_shared_dpll(intel_crtc);
13187 }
13188 }
13189
13190 /* Only after disabling all output pipelines that will be changed can we
13191 * update the the output configuration. */
13192 intel_modeset_update_state(state);
13193
13194 /* The state has been swaped above, so state actually contains the
13195 * old state now. */
13196 if (any_ms)
13197 modeset_update_crtc_power_domains(state);
13198
13199 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13200 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13201 if (needs_modeset(crtc->state) && crtc->state->active) {
13202 update_scanline_offset(to_intel_crtc(crtc));
13203 dev_priv->display.crtc_enable(crtc);
13204 }
13205
13206 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13207 }
13208
13209 /* FIXME: add subpixel order */
13210
13211 drm_atomic_helper_cleanup_planes(dev, state);
13212
13213 drm_atomic_state_free(state);
13214
13215 return 0;
13216 }
13217
13218 static int intel_set_mode_checked(struct drm_atomic_state *state)
13219 {
13220 struct drm_device *dev = state->dev;
13221 int ret;
13222
13223 ret = __intel_set_mode(state);
13224 if (ret == 0)
13225 intel_modeset_check_state(dev);
13226
13227 return ret;
13228 }
13229
13230 static int intel_set_mode(struct drm_atomic_state *state)
13231 {
13232 int ret;
13233
13234 ret = intel_modeset_compute_config(state);
13235 if (ret)
13236 return ret;
13237
13238 return intel_set_mode_checked(state);
13239 }
13240
13241 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13242 {
13243 struct drm_device *dev = crtc->dev;
13244 struct drm_atomic_state *state;
13245 struct intel_crtc *intel_crtc;
13246 struct intel_encoder *encoder;
13247 struct intel_connector *connector;
13248 struct drm_connector_state *connector_state;
13249 struct intel_crtc_state *crtc_state;
13250 int ret;
13251
13252 state = drm_atomic_state_alloc(dev);
13253 if (!state) {
13254 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13255 crtc->base.id);
13256 return;
13257 }
13258
13259 state->acquire_ctx = dev->mode_config.acquire_ctx;
13260
13261 /* The force restore path in the HW readout code relies on the staged
13262 * config still keeping the user requested config while the actual
13263 * state has been overwritten by the configuration read from HW. We
13264 * need to copy the staged config to the atomic state, otherwise the
13265 * mode set will just reapply the state the HW is already in. */
13266 for_each_intel_encoder(dev, encoder) {
13267 if (&encoder->new_crtc->base != crtc)
13268 continue;
13269
13270 for_each_intel_connector(dev, connector) {
13271 if (connector->new_encoder != encoder)
13272 continue;
13273
13274 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13275 if (IS_ERR(connector_state)) {
13276 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13277 connector->base.base.id,
13278 connector->base.name,
13279 PTR_ERR(connector_state));
13280 continue;
13281 }
13282
13283 connector_state->crtc = crtc;
13284 connector_state->best_encoder = &encoder->base;
13285 }
13286 }
13287
13288 for_each_intel_crtc(dev, intel_crtc) {
13289 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13290 continue;
13291
13292 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13293 if (IS_ERR(crtc_state)) {
13294 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13295 intel_crtc->base.base.id,
13296 PTR_ERR(crtc_state));
13297 continue;
13298 }
13299
13300 crtc_state->base.active = crtc_state->base.enable =
13301 intel_crtc->new_enabled;
13302
13303 if (&intel_crtc->base == crtc)
13304 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13305 }
13306
13307 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13308 crtc->primary->fb, crtc->x, crtc->y);
13309
13310 ret = intel_set_mode(state);
13311 if (ret)
13312 drm_atomic_state_free(state);
13313 }
13314
13315 #undef for_each_intel_crtc_masked
13316
13317 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13318 struct drm_mode_set *set)
13319 {
13320 int ro;
13321
13322 for (ro = 0; ro < set->num_connectors; ro++)
13323 if (set->connectors[ro] == &connector->base)
13324 return true;
13325
13326 return false;
13327 }
13328
13329 static int
13330 intel_modeset_stage_output_state(struct drm_device *dev,
13331 struct drm_mode_set *set,
13332 struct drm_atomic_state *state)
13333 {
13334 struct intel_connector *connector;
13335 struct drm_connector *drm_connector;
13336 struct drm_connector_state *connector_state;
13337 struct drm_crtc *crtc;
13338 struct drm_crtc_state *crtc_state;
13339 int i, ret;
13340
13341 /* The upper layers ensure that we either disable a crtc or have a list
13342 * of connectors. For paranoia, double-check this. */
13343 WARN_ON(!set->fb && (set->num_connectors != 0));
13344 WARN_ON(set->fb && (set->num_connectors == 0));
13345
13346 for_each_intel_connector(dev, connector) {
13347 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13348
13349 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13350 continue;
13351
13352 connector_state =
13353 drm_atomic_get_connector_state(state, &connector->base);
13354 if (IS_ERR(connector_state))
13355 return PTR_ERR(connector_state);
13356
13357 if (in_mode_set) {
13358 int pipe = to_intel_crtc(set->crtc)->pipe;
13359 connector_state->best_encoder =
13360 &intel_find_encoder(connector, pipe)->base;
13361 }
13362
13363 if (connector->base.state->crtc != set->crtc)
13364 continue;
13365
13366 /* If we disable the crtc, disable all its connectors. Also, if
13367 * the connector is on the changing crtc but not on the new
13368 * connector list, disable it. */
13369 if (!set->fb || !in_mode_set) {
13370 connector_state->best_encoder = NULL;
13371
13372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13373 connector->base.base.id,
13374 connector->base.name);
13375 }
13376 }
13377 /* connector->new_encoder is now updated for all connectors. */
13378
13379 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13380 connector = to_intel_connector(drm_connector);
13381
13382 if (!connector_state->best_encoder) {
13383 ret = drm_atomic_set_crtc_for_connector(connector_state,
13384 NULL);
13385 if (ret)
13386 return ret;
13387
13388 continue;
13389 }
13390
13391 if (intel_connector_in_mode_set(connector, set)) {
13392 struct drm_crtc *crtc = connector->base.state->crtc;
13393
13394 /* If this connector was in a previous crtc, add it
13395 * to the state. We might need to disable it. */
13396 if (crtc) {
13397 crtc_state =
13398 drm_atomic_get_crtc_state(state, crtc);
13399 if (IS_ERR(crtc_state))
13400 return PTR_ERR(crtc_state);
13401 }
13402
13403 ret = drm_atomic_set_crtc_for_connector(connector_state,
13404 set->crtc);
13405 if (ret)
13406 return ret;
13407 }
13408
13409 /* Make sure the new CRTC will work with the encoder */
13410 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13411 connector_state->crtc)) {
13412 return -EINVAL;
13413 }
13414
13415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13416 connector->base.base.id,
13417 connector->base.name,
13418 connector_state->crtc->base.id);
13419
13420 if (connector_state->best_encoder != &connector->encoder->base)
13421 connector->encoder =
13422 to_intel_encoder(connector_state->best_encoder);
13423 }
13424
13425 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13426 bool has_connectors;
13427
13428 ret = drm_atomic_add_affected_connectors(state, crtc);
13429 if (ret)
13430 return ret;
13431
13432 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13433 if (has_connectors != crtc_state->enable)
13434 crtc_state->enable =
13435 crtc_state->active = has_connectors;
13436 }
13437
13438 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13439 set->fb, set->x, set->y);
13440 if (ret)
13441 return ret;
13442
13443 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13444 if (IS_ERR(crtc_state))
13445 return PTR_ERR(crtc_state);
13446
13447 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13448 if (ret)
13449 return ret;
13450
13451 if (set->num_connectors)
13452 crtc_state->active = true;
13453
13454 return 0;
13455 }
13456
13457 static int intel_crtc_set_config(struct drm_mode_set *set)
13458 {
13459 struct drm_device *dev;
13460 struct drm_atomic_state *state = NULL;
13461 int ret;
13462
13463 BUG_ON(!set);
13464 BUG_ON(!set->crtc);
13465 BUG_ON(!set->crtc->helper_private);
13466
13467 /* Enforce sane interface api - has been abused by the fb helper. */
13468 BUG_ON(!set->mode && set->fb);
13469 BUG_ON(set->fb && set->num_connectors == 0);
13470
13471 if (set->fb) {
13472 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13473 set->crtc->base.id, set->fb->base.id,
13474 (int)set->num_connectors, set->x, set->y);
13475 } else {
13476 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13477 }
13478
13479 dev = set->crtc->dev;
13480
13481 state = drm_atomic_state_alloc(dev);
13482 if (!state)
13483 return -ENOMEM;
13484
13485 state->acquire_ctx = dev->mode_config.acquire_ctx;
13486
13487 ret = intel_modeset_stage_output_state(dev, set, state);
13488 if (ret)
13489 goto out;
13490
13491 ret = intel_modeset_compute_config(state);
13492 if (ret)
13493 goto out;
13494
13495 intel_update_pipe_size(to_intel_crtc(set->crtc));
13496
13497 ret = intel_set_mode_checked(state);
13498 if (ret) {
13499 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13500 set->crtc->base.id, ret);
13501 }
13502
13503 out:
13504 if (ret)
13505 drm_atomic_state_free(state);
13506 return ret;
13507 }
13508
13509 static const struct drm_crtc_funcs intel_crtc_funcs = {
13510 .gamma_set = intel_crtc_gamma_set,
13511 .set_config = intel_crtc_set_config,
13512 .destroy = intel_crtc_destroy,
13513 .page_flip = intel_crtc_page_flip,
13514 .atomic_duplicate_state = intel_crtc_duplicate_state,
13515 .atomic_destroy_state = intel_crtc_destroy_state,
13516 };
13517
13518 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13519 struct intel_shared_dpll *pll,
13520 struct intel_dpll_hw_state *hw_state)
13521 {
13522 uint32_t val;
13523
13524 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13525 return false;
13526
13527 val = I915_READ(PCH_DPLL(pll->id));
13528 hw_state->dpll = val;
13529 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13530 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13531
13532 return val & DPLL_VCO_ENABLE;
13533 }
13534
13535 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13536 struct intel_shared_dpll *pll)
13537 {
13538 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13539 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13540 }
13541
13542 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13543 struct intel_shared_dpll *pll)
13544 {
13545 /* PCH refclock must be enabled first */
13546 ibx_assert_pch_refclk_enabled(dev_priv);
13547
13548 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13549
13550 /* Wait for the clocks to stabilize. */
13551 POSTING_READ(PCH_DPLL(pll->id));
13552 udelay(150);
13553
13554 /* The pixel multiplier can only be updated once the
13555 * DPLL is enabled and the clocks are stable.
13556 *
13557 * So write it again.
13558 */
13559 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13560 POSTING_READ(PCH_DPLL(pll->id));
13561 udelay(200);
13562 }
13563
13564 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13565 struct intel_shared_dpll *pll)
13566 {
13567 struct drm_device *dev = dev_priv->dev;
13568 struct intel_crtc *crtc;
13569
13570 /* Make sure no transcoder isn't still depending on us. */
13571 for_each_intel_crtc(dev, crtc) {
13572 if (intel_crtc_to_shared_dpll(crtc) == pll)
13573 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13574 }
13575
13576 I915_WRITE(PCH_DPLL(pll->id), 0);
13577 POSTING_READ(PCH_DPLL(pll->id));
13578 udelay(200);
13579 }
13580
13581 static char *ibx_pch_dpll_names[] = {
13582 "PCH DPLL A",
13583 "PCH DPLL B",
13584 };
13585
13586 static void ibx_pch_dpll_init(struct drm_device *dev)
13587 {
13588 struct drm_i915_private *dev_priv = dev->dev_private;
13589 int i;
13590
13591 dev_priv->num_shared_dpll = 2;
13592
13593 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13594 dev_priv->shared_dplls[i].id = i;
13595 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13596 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13597 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13598 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13599 dev_priv->shared_dplls[i].get_hw_state =
13600 ibx_pch_dpll_get_hw_state;
13601 }
13602 }
13603
13604 static void intel_shared_dpll_init(struct drm_device *dev)
13605 {
13606 struct drm_i915_private *dev_priv = dev->dev_private;
13607
13608 intel_update_cdclk(dev);
13609
13610 if (HAS_DDI(dev))
13611 intel_ddi_pll_init(dev);
13612 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13613 ibx_pch_dpll_init(dev);
13614 else
13615 dev_priv->num_shared_dpll = 0;
13616
13617 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13618 }
13619
13620 /**
13621 * intel_prepare_plane_fb - Prepare fb for usage on plane
13622 * @plane: drm plane to prepare for
13623 * @fb: framebuffer to prepare for presentation
13624 *
13625 * Prepares a framebuffer for usage on a display plane. Generally this
13626 * involves pinning the underlying object and updating the frontbuffer tracking
13627 * bits. Some older platforms need special physical address handling for
13628 * cursor planes.
13629 *
13630 * Returns 0 on success, negative error code on failure.
13631 */
13632 int
13633 intel_prepare_plane_fb(struct drm_plane *plane,
13634 struct drm_framebuffer *fb,
13635 const struct drm_plane_state *new_state)
13636 {
13637 struct drm_device *dev = plane->dev;
13638 struct intel_plane *intel_plane = to_intel_plane(plane);
13639 enum pipe pipe = intel_plane->pipe;
13640 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13641 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13642 unsigned frontbuffer_bits = 0;
13643 int ret = 0;
13644
13645 if (!obj)
13646 return 0;
13647
13648 switch (plane->type) {
13649 case DRM_PLANE_TYPE_PRIMARY:
13650 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13651 break;
13652 case DRM_PLANE_TYPE_CURSOR:
13653 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13654 break;
13655 case DRM_PLANE_TYPE_OVERLAY:
13656 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13657 break;
13658 }
13659
13660 mutex_lock(&dev->struct_mutex);
13661
13662 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13663 INTEL_INFO(dev)->cursor_needs_physical) {
13664 int align = IS_I830(dev) ? 16 * 1024 : 256;
13665 ret = i915_gem_object_attach_phys(obj, align);
13666 if (ret)
13667 DRM_DEBUG_KMS("failed to attach phys object\n");
13668 } else {
13669 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13670 }
13671
13672 if (ret == 0)
13673 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13674
13675 mutex_unlock(&dev->struct_mutex);
13676
13677 return ret;
13678 }
13679
13680 /**
13681 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13682 * @plane: drm plane to clean up for
13683 * @fb: old framebuffer that was on plane
13684 *
13685 * Cleans up a framebuffer that has just been removed from a plane.
13686 */
13687 void
13688 intel_cleanup_plane_fb(struct drm_plane *plane,
13689 struct drm_framebuffer *fb,
13690 const struct drm_plane_state *old_state)
13691 {
13692 struct drm_device *dev = plane->dev;
13693 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13694
13695 if (WARN_ON(!obj))
13696 return;
13697
13698 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13699 !INTEL_INFO(dev)->cursor_needs_physical) {
13700 mutex_lock(&dev->struct_mutex);
13701 intel_unpin_fb_obj(fb, old_state);
13702 mutex_unlock(&dev->struct_mutex);
13703 }
13704 }
13705
13706 int
13707 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13708 {
13709 int max_scale;
13710 struct drm_device *dev;
13711 struct drm_i915_private *dev_priv;
13712 int crtc_clock, cdclk;
13713
13714 if (!intel_crtc || !crtc_state)
13715 return DRM_PLANE_HELPER_NO_SCALING;
13716
13717 dev = intel_crtc->base.dev;
13718 dev_priv = dev->dev_private;
13719 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13720 cdclk = dev_priv->display.get_display_clock_speed(dev);
13721
13722 if (!crtc_clock || !cdclk)
13723 return DRM_PLANE_HELPER_NO_SCALING;
13724
13725 /*
13726 * skl max scale is lower of:
13727 * close to 3 but not 3, -1 is for that purpose
13728 * or
13729 * cdclk/crtc_clock
13730 */
13731 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13732
13733 return max_scale;
13734 }
13735
13736 static int
13737 intel_check_primary_plane(struct drm_plane *plane,
13738 struct intel_crtc_state *crtc_state,
13739 struct intel_plane_state *state)
13740 {
13741 struct drm_crtc *crtc = state->base.crtc;
13742 struct drm_framebuffer *fb = state->base.fb;
13743 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13744 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13745 bool can_position = false;
13746
13747 /* use scaler when colorkey is not required */
13748 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13749 to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13750 min_scale = 1;
13751 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13752 can_position = true;
13753 }
13754
13755 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13756 &state->dst, &state->clip,
13757 min_scale, max_scale,
13758 can_position, true,
13759 &state->visible);
13760 }
13761
13762 static void
13763 intel_commit_primary_plane(struct drm_plane *plane,
13764 struct intel_plane_state *state)
13765 {
13766 struct drm_crtc *crtc = state->base.crtc;
13767 struct drm_framebuffer *fb = state->base.fb;
13768 struct drm_device *dev = plane->dev;
13769 struct drm_i915_private *dev_priv = dev->dev_private;
13770 struct intel_crtc *intel_crtc;
13771 struct drm_rect *src = &state->src;
13772
13773 crtc = crtc ? crtc : plane->crtc;
13774 intel_crtc = to_intel_crtc(crtc);
13775
13776 plane->fb = fb;
13777 crtc->x = src->x1 >> 16;
13778 crtc->y = src->y1 >> 16;
13779
13780 if (!crtc->state->active)
13781 return;
13782
13783 if (state->visible)
13784 /* FIXME: kill this fastboot hack */
13785 intel_update_pipe_size(intel_crtc);
13786
13787 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13788 }
13789
13790 static void
13791 intel_disable_primary_plane(struct drm_plane *plane,
13792 struct drm_crtc *crtc)
13793 {
13794 struct drm_device *dev = plane->dev;
13795 struct drm_i915_private *dev_priv = dev->dev_private;
13796
13797 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13798 }
13799
13800 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13801 {
13802 struct drm_device *dev = crtc->dev;
13803 struct drm_i915_private *dev_priv = dev->dev_private;
13804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13805
13806 if (!needs_modeset(crtc->state))
13807 intel_pre_plane_update(intel_crtc);
13808
13809 if (intel_crtc->atomic.update_wm)
13810 intel_update_watermarks(crtc);
13811
13812 intel_runtime_pm_get(dev_priv);
13813
13814 /* Perform vblank evasion around commit operation */
13815 if (crtc->state->active)
13816 intel_crtc->atomic.evade =
13817 intel_pipe_update_start(intel_crtc,
13818 &intel_crtc->atomic.start_vbl_count);
13819
13820 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13821 skl_detach_scalers(intel_crtc);
13822 }
13823
13824 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13825 {
13826 struct drm_device *dev = crtc->dev;
13827 struct drm_i915_private *dev_priv = dev->dev_private;
13828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13829
13830 if (intel_crtc->atomic.evade)
13831 intel_pipe_update_end(intel_crtc,
13832 intel_crtc->atomic.start_vbl_count);
13833
13834 intel_runtime_pm_put(dev_priv);
13835
13836 intel_post_plane_update(intel_crtc);
13837 }
13838
13839 /**
13840 * intel_plane_destroy - destroy a plane
13841 * @plane: plane to destroy
13842 *
13843 * Common destruction function for all types of planes (primary, cursor,
13844 * sprite).
13845 */
13846 void intel_plane_destroy(struct drm_plane *plane)
13847 {
13848 struct intel_plane *intel_plane = to_intel_plane(plane);
13849 drm_plane_cleanup(plane);
13850 kfree(intel_plane);
13851 }
13852
13853 const struct drm_plane_funcs intel_plane_funcs = {
13854 .update_plane = drm_atomic_helper_update_plane,
13855 .disable_plane = drm_atomic_helper_disable_plane,
13856 .destroy = intel_plane_destroy,
13857 .set_property = drm_atomic_helper_plane_set_property,
13858 .atomic_get_property = intel_plane_atomic_get_property,
13859 .atomic_set_property = intel_plane_atomic_set_property,
13860 .atomic_duplicate_state = intel_plane_duplicate_state,
13861 .atomic_destroy_state = intel_plane_destroy_state,
13862
13863 };
13864
13865 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13866 int pipe)
13867 {
13868 struct intel_plane *primary;
13869 struct intel_plane_state *state;
13870 const uint32_t *intel_primary_formats;
13871 int num_formats;
13872
13873 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13874 if (primary == NULL)
13875 return NULL;
13876
13877 state = intel_create_plane_state(&primary->base);
13878 if (!state) {
13879 kfree(primary);
13880 return NULL;
13881 }
13882 primary->base.state = &state->base;
13883
13884 primary->can_scale = false;
13885 primary->max_downscale = 1;
13886 if (INTEL_INFO(dev)->gen >= 9) {
13887 primary->can_scale = true;
13888 state->scaler_id = -1;
13889 }
13890 primary->pipe = pipe;
13891 primary->plane = pipe;
13892 primary->check_plane = intel_check_primary_plane;
13893 primary->commit_plane = intel_commit_primary_plane;
13894 primary->disable_plane = intel_disable_primary_plane;
13895 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13896 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13897 primary->plane = !pipe;
13898
13899 if (INTEL_INFO(dev)->gen >= 9) {
13900 intel_primary_formats = skl_primary_formats;
13901 num_formats = ARRAY_SIZE(skl_primary_formats);
13902 } else if (INTEL_INFO(dev)->gen >= 4) {
13903 intel_primary_formats = i965_primary_formats;
13904 num_formats = ARRAY_SIZE(i965_primary_formats);
13905 } else {
13906 intel_primary_formats = i8xx_primary_formats;
13907 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13908 }
13909
13910 drm_universal_plane_init(dev, &primary->base, 0,
13911 &intel_plane_funcs,
13912 intel_primary_formats, num_formats,
13913 DRM_PLANE_TYPE_PRIMARY);
13914
13915 if (INTEL_INFO(dev)->gen >= 4)
13916 intel_create_rotation_property(dev, primary);
13917
13918 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13919
13920 return &primary->base;
13921 }
13922
13923 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13924 {
13925 if (!dev->mode_config.rotation_property) {
13926 unsigned long flags = BIT(DRM_ROTATE_0) |
13927 BIT(DRM_ROTATE_180);
13928
13929 if (INTEL_INFO(dev)->gen >= 9)
13930 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13931
13932 dev->mode_config.rotation_property =
13933 drm_mode_create_rotation_property(dev, flags);
13934 }
13935 if (dev->mode_config.rotation_property)
13936 drm_object_attach_property(&plane->base.base,
13937 dev->mode_config.rotation_property,
13938 plane->base.state->rotation);
13939 }
13940
13941 static int
13942 intel_check_cursor_plane(struct drm_plane *plane,
13943 struct intel_crtc_state *crtc_state,
13944 struct intel_plane_state *state)
13945 {
13946 struct drm_crtc *crtc = crtc_state->base.crtc;
13947 struct drm_framebuffer *fb = state->base.fb;
13948 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13949 unsigned stride;
13950 int ret;
13951
13952 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13953 &state->dst, &state->clip,
13954 DRM_PLANE_HELPER_NO_SCALING,
13955 DRM_PLANE_HELPER_NO_SCALING,
13956 true, true, &state->visible);
13957 if (ret)
13958 return ret;
13959
13960 /* if we want to turn off the cursor ignore width and height */
13961 if (!obj)
13962 return 0;
13963
13964 /* Check for which cursor types we support */
13965 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13966 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13967 state->base.crtc_w, state->base.crtc_h);
13968 return -EINVAL;
13969 }
13970
13971 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13972 if (obj->base.size < stride * state->base.crtc_h) {
13973 DRM_DEBUG_KMS("buffer is too small\n");
13974 return -ENOMEM;
13975 }
13976
13977 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13978 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13979 return -EINVAL;
13980 }
13981
13982 return 0;
13983 }
13984
13985 static void
13986 intel_disable_cursor_plane(struct drm_plane *plane,
13987 struct drm_crtc *crtc)
13988 {
13989 intel_crtc_update_cursor(crtc, false);
13990 }
13991
13992 static void
13993 intel_commit_cursor_plane(struct drm_plane *plane,
13994 struct intel_plane_state *state)
13995 {
13996 struct drm_crtc *crtc = state->base.crtc;
13997 struct drm_device *dev = plane->dev;
13998 struct intel_crtc *intel_crtc;
13999 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14000 uint32_t addr;
14001
14002 crtc = crtc ? crtc : plane->crtc;
14003 intel_crtc = to_intel_crtc(crtc);
14004
14005 plane->fb = state->base.fb;
14006 crtc->cursor_x = state->base.crtc_x;
14007 crtc->cursor_y = state->base.crtc_y;
14008
14009 if (intel_crtc->cursor_bo == obj)
14010 goto update;
14011
14012 if (!obj)
14013 addr = 0;
14014 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14015 addr = i915_gem_obj_ggtt_offset(obj);
14016 else
14017 addr = obj->phys_handle->busaddr;
14018
14019 intel_crtc->cursor_addr = addr;
14020 intel_crtc->cursor_bo = obj;
14021
14022 update:
14023 if (crtc->state->active)
14024 intel_crtc_update_cursor(crtc, state->visible);
14025 }
14026
14027 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14028 int pipe)
14029 {
14030 struct intel_plane *cursor;
14031 struct intel_plane_state *state;
14032
14033 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14034 if (cursor == NULL)
14035 return NULL;
14036
14037 state = intel_create_plane_state(&cursor->base);
14038 if (!state) {
14039 kfree(cursor);
14040 return NULL;
14041 }
14042 cursor->base.state = &state->base;
14043
14044 cursor->can_scale = false;
14045 cursor->max_downscale = 1;
14046 cursor->pipe = pipe;
14047 cursor->plane = pipe;
14048 cursor->check_plane = intel_check_cursor_plane;
14049 cursor->commit_plane = intel_commit_cursor_plane;
14050 cursor->disable_plane = intel_disable_cursor_plane;
14051
14052 drm_universal_plane_init(dev, &cursor->base, 0,
14053 &intel_plane_funcs,
14054 intel_cursor_formats,
14055 ARRAY_SIZE(intel_cursor_formats),
14056 DRM_PLANE_TYPE_CURSOR);
14057
14058 if (INTEL_INFO(dev)->gen >= 4) {
14059 if (!dev->mode_config.rotation_property)
14060 dev->mode_config.rotation_property =
14061 drm_mode_create_rotation_property(dev,
14062 BIT(DRM_ROTATE_0) |
14063 BIT(DRM_ROTATE_180));
14064 if (dev->mode_config.rotation_property)
14065 drm_object_attach_property(&cursor->base.base,
14066 dev->mode_config.rotation_property,
14067 state->base.rotation);
14068 }
14069
14070 if (INTEL_INFO(dev)->gen >=9)
14071 state->scaler_id = -1;
14072
14073 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14074
14075 return &cursor->base;
14076 }
14077
14078 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14079 struct intel_crtc_state *crtc_state)
14080 {
14081 int i;
14082 struct intel_scaler *intel_scaler;
14083 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14084
14085 for (i = 0; i < intel_crtc->num_scalers; i++) {
14086 intel_scaler = &scaler_state->scalers[i];
14087 intel_scaler->in_use = 0;
14088 intel_scaler->mode = PS_SCALER_MODE_DYN;
14089 }
14090
14091 scaler_state->scaler_id = -1;
14092 }
14093
14094 static void intel_crtc_init(struct drm_device *dev, int pipe)
14095 {
14096 struct drm_i915_private *dev_priv = dev->dev_private;
14097 struct intel_crtc *intel_crtc;
14098 struct intel_crtc_state *crtc_state = NULL;
14099 struct drm_plane *primary = NULL;
14100 struct drm_plane *cursor = NULL;
14101 int i, ret;
14102
14103 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14104 if (intel_crtc == NULL)
14105 return;
14106
14107 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14108 if (!crtc_state)
14109 goto fail;
14110 intel_crtc->config = crtc_state;
14111 intel_crtc->base.state = &crtc_state->base;
14112 crtc_state->base.crtc = &intel_crtc->base;
14113
14114 /* initialize shared scalers */
14115 if (INTEL_INFO(dev)->gen >= 9) {
14116 if (pipe == PIPE_C)
14117 intel_crtc->num_scalers = 1;
14118 else
14119 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14120
14121 skl_init_scalers(dev, intel_crtc, crtc_state);
14122 }
14123
14124 primary = intel_primary_plane_create(dev, pipe);
14125 if (!primary)
14126 goto fail;
14127
14128 cursor = intel_cursor_plane_create(dev, pipe);
14129 if (!cursor)
14130 goto fail;
14131
14132 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14133 cursor, &intel_crtc_funcs);
14134 if (ret)
14135 goto fail;
14136
14137 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14138 for (i = 0; i < 256; i++) {
14139 intel_crtc->lut_r[i] = i;
14140 intel_crtc->lut_g[i] = i;
14141 intel_crtc->lut_b[i] = i;
14142 }
14143
14144 /*
14145 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14146 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14147 */
14148 intel_crtc->pipe = pipe;
14149 intel_crtc->plane = pipe;
14150 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14151 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14152 intel_crtc->plane = !pipe;
14153 }
14154
14155 intel_crtc->cursor_base = ~0;
14156 intel_crtc->cursor_cntl = ~0;
14157 intel_crtc->cursor_size = ~0;
14158
14159 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14160 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14161 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14162 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14163
14164 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14165
14166 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14167 return;
14168
14169 fail:
14170 if (primary)
14171 drm_plane_cleanup(primary);
14172 if (cursor)
14173 drm_plane_cleanup(cursor);
14174 kfree(crtc_state);
14175 kfree(intel_crtc);
14176 }
14177
14178 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14179 {
14180 struct drm_encoder *encoder = connector->base.encoder;
14181 struct drm_device *dev = connector->base.dev;
14182
14183 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14184
14185 if (!encoder || WARN_ON(!encoder->crtc))
14186 return INVALID_PIPE;
14187
14188 return to_intel_crtc(encoder->crtc)->pipe;
14189 }
14190
14191 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14192 struct drm_file *file)
14193 {
14194 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14195 struct drm_crtc *drmmode_crtc;
14196 struct intel_crtc *crtc;
14197
14198 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14199
14200 if (!drmmode_crtc) {
14201 DRM_ERROR("no such CRTC id\n");
14202 return -ENOENT;
14203 }
14204
14205 crtc = to_intel_crtc(drmmode_crtc);
14206 pipe_from_crtc_id->pipe = crtc->pipe;
14207
14208 return 0;
14209 }
14210
14211 static int intel_encoder_clones(struct intel_encoder *encoder)
14212 {
14213 struct drm_device *dev = encoder->base.dev;
14214 struct intel_encoder *source_encoder;
14215 int index_mask = 0;
14216 int entry = 0;
14217
14218 for_each_intel_encoder(dev, source_encoder) {
14219 if (encoders_cloneable(encoder, source_encoder))
14220 index_mask |= (1 << entry);
14221
14222 entry++;
14223 }
14224
14225 return index_mask;
14226 }
14227
14228 static bool has_edp_a(struct drm_device *dev)
14229 {
14230 struct drm_i915_private *dev_priv = dev->dev_private;
14231
14232 if (!IS_MOBILE(dev))
14233 return false;
14234
14235 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14236 return false;
14237
14238 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14239 return false;
14240
14241 return true;
14242 }
14243
14244 static bool intel_crt_present(struct drm_device *dev)
14245 {
14246 struct drm_i915_private *dev_priv = dev->dev_private;
14247
14248 if (INTEL_INFO(dev)->gen >= 9)
14249 return false;
14250
14251 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14252 return false;
14253
14254 if (IS_CHERRYVIEW(dev))
14255 return false;
14256
14257 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14258 return false;
14259
14260 return true;
14261 }
14262
14263 static void intel_setup_outputs(struct drm_device *dev)
14264 {
14265 struct drm_i915_private *dev_priv = dev->dev_private;
14266 struct intel_encoder *encoder;
14267 bool dpd_is_edp = false;
14268
14269 intel_lvds_init(dev);
14270
14271 if (intel_crt_present(dev))
14272 intel_crt_init(dev);
14273
14274 if (IS_BROXTON(dev)) {
14275 /*
14276 * FIXME: Broxton doesn't support port detection via the
14277 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14278 * detect the ports.
14279 */
14280 intel_ddi_init(dev, PORT_A);
14281 intel_ddi_init(dev, PORT_B);
14282 intel_ddi_init(dev, PORT_C);
14283 } else if (HAS_DDI(dev)) {
14284 int found;
14285
14286 /*
14287 * Haswell uses DDI functions to detect digital outputs.
14288 * On SKL pre-D0 the strap isn't connected, so we assume
14289 * it's there.
14290 */
14291 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14292 /* WaIgnoreDDIAStrap: skl */
14293 if (found ||
14294 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14295 intel_ddi_init(dev, PORT_A);
14296
14297 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14298 * register */
14299 found = I915_READ(SFUSE_STRAP);
14300
14301 if (found & SFUSE_STRAP_DDIB_DETECTED)
14302 intel_ddi_init(dev, PORT_B);
14303 if (found & SFUSE_STRAP_DDIC_DETECTED)
14304 intel_ddi_init(dev, PORT_C);
14305 if (found & SFUSE_STRAP_DDID_DETECTED)
14306 intel_ddi_init(dev, PORT_D);
14307 } else if (HAS_PCH_SPLIT(dev)) {
14308 int found;
14309 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14310
14311 if (has_edp_a(dev))
14312 intel_dp_init(dev, DP_A, PORT_A);
14313
14314 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14315 /* PCH SDVOB multiplex with HDMIB */
14316 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14317 if (!found)
14318 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14319 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14320 intel_dp_init(dev, PCH_DP_B, PORT_B);
14321 }
14322
14323 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14324 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14325
14326 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14327 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14328
14329 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14330 intel_dp_init(dev, PCH_DP_C, PORT_C);
14331
14332 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14333 intel_dp_init(dev, PCH_DP_D, PORT_D);
14334 } else if (IS_VALLEYVIEW(dev)) {
14335 /*
14336 * The DP_DETECTED bit is the latched state of the DDC
14337 * SDA pin at boot. However since eDP doesn't require DDC
14338 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14339 * eDP ports may have been muxed to an alternate function.
14340 * Thus we can't rely on the DP_DETECTED bit alone to detect
14341 * eDP ports. Consult the VBT as well as DP_DETECTED to
14342 * detect eDP ports.
14343 */
14344 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14345 !intel_dp_is_edp(dev, PORT_B))
14346 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14347 PORT_B);
14348 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14349 intel_dp_is_edp(dev, PORT_B))
14350 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14351
14352 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14353 !intel_dp_is_edp(dev, PORT_C))
14354 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14355 PORT_C);
14356 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14357 intel_dp_is_edp(dev, PORT_C))
14358 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14359
14360 if (IS_CHERRYVIEW(dev)) {
14361 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14362 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14363 PORT_D);
14364 /* eDP not supported on port D, so don't check VBT */
14365 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14366 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14367 }
14368
14369 intel_dsi_init(dev);
14370 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14371 bool found = false;
14372
14373 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14374 DRM_DEBUG_KMS("probing SDVOB\n");
14375 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14376 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14377 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14378 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14379 }
14380
14381 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14382 intel_dp_init(dev, DP_B, PORT_B);
14383 }
14384
14385 /* Before G4X SDVOC doesn't have its own detect register */
14386
14387 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14388 DRM_DEBUG_KMS("probing SDVOC\n");
14389 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14390 }
14391
14392 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14393
14394 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14395 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14396 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14397 }
14398 if (SUPPORTS_INTEGRATED_DP(dev))
14399 intel_dp_init(dev, DP_C, PORT_C);
14400 }
14401
14402 if (SUPPORTS_INTEGRATED_DP(dev) &&
14403 (I915_READ(DP_D) & DP_DETECTED))
14404 intel_dp_init(dev, DP_D, PORT_D);
14405 } else if (IS_GEN2(dev))
14406 intel_dvo_init(dev);
14407
14408 if (SUPPORTS_TV(dev))
14409 intel_tv_init(dev);
14410
14411 intel_psr_init(dev);
14412
14413 for_each_intel_encoder(dev, encoder) {
14414 encoder->base.possible_crtcs = encoder->crtc_mask;
14415 encoder->base.possible_clones =
14416 intel_encoder_clones(encoder);
14417 }
14418
14419 intel_init_pch_refclk(dev);
14420
14421 drm_helper_move_panel_connectors_to_head(dev);
14422 }
14423
14424 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14425 {
14426 struct drm_device *dev = fb->dev;
14427 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14428
14429 drm_framebuffer_cleanup(fb);
14430 mutex_lock(&dev->struct_mutex);
14431 WARN_ON(!intel_fb->obj->framebuffer_references--);
14432 drm_gem_object_unreference(&intel_fb->obj->base);
14433 mutex_unlock(&dev->struct_mutex);
14434 kfree(intel_fb);
14435 }
14436
14437 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14438 struct drm_file *file,
14439 unsigned int *handle)
14440 {
14441 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14442 struct drm_i915_gem_object *obj = intel_fb->obj;
14443
14444 return drm_gem_handle_create(file, &obj->base, handle);
14445 }
14446
14447 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14448 .destroy = intel_user_framebuffer_destroy,
14449 .create_handle = intel_user_framebuffer_create_handle,
14450 };
14451
14452 static
14453 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14454 uint32_t pixel_format)
14455 {
14456 u32 gen = INTEL_INFO(dev)->gen;
14457
14458 if (gen >= 9) {
14459 /* "The stride in bytes must not exceed the of the size of 8K
14460 * pixels and 32K bytes."
14461 */
14462 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14463 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14464 return 32*1024;
14465 } else if (gen >= 4) {
14466 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14467 return 16*1024;
14468 else
14469 return 32*1024;
14470 } else if (gen >= 3) {
14471 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14472 return 8*1024;
14473 else
14474 return 16*1024;
14475 } else {
14476 /* XXX DSPC is limited to 4k tiled */
14477 return 8*1024;
14478 }
14479 }
14480
14481 static int intel_framebuffer_init(struct drm_device *dev,
14482 struct intel_framebuffer *intel_fb,
14483 struct drm_mode_fb_cmd2 *mode_cmd,
14484 struct drm_i915_gem_object *obj)
14485 {
14486 unsigned int aligned_height;
14487 int ret;
14488 u32 pitch_limit, stride_alignment;
14489
14490 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14491
14492 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14493 /* Enforce that fb modifier and tiling mode match, but only for
14494 * X-tiled. This is needed for FBC. */
14495 if (!!(obj->tiling_mode == I915_TILING_X) !=
14496 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14497 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14498 return -EINVAL;
14499 }
14500 } else {
14501 if (obj->tiling_mode == I915_TILING_X)
14502 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14503 else if (obj->tiling_mode == I915_TILING_Y) {
14504 DRM_DEBUG("No Y tiling for legacy addfb\n");
14505 return -EINVAL;
14506 }
14507 }
14508
14509 /* Passed in modifier sanity checking. */
14510 switch (mode_cmd->modifier[0]) {
14511 case I915_FORMAT_MOD_Y_TILED:
14512 case I915_FORMAT_MOD_Yf_TILED:
14513 if (INTEL_INFO(dev)->gen < 9) {
14514 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14515 mode_cmd->modifier[0]);
14516 return -EINVAL;
14517 }
14518 case DRM_FORMAT_MOD_NONE:
14519 case I915_FORMAT_MOD_X_TILED:
14520 break;
14521 default:
14522 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14523 mode_cmd->modifier[0]);
14524 return -EINVAL;
14525 }
14526
14527 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14528 mode_cmd->pixel_format);
14529 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14530 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14531 mode_cmd->pitches[0], stride_alignment);
14532 return -EINVAL;
14533 }
14534
14535 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14536 mode_cmd->pixel_format);
14537 if (mode_cmd->pitches[0] > pitch_limit) {
14538 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14539 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14540 "tiled" : "linear",
14541 mode_cmd->pitches[0], pitch_limit);
14542 return -EINVAL;
14543 }
14544
14545 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14546 mode_cmd->pitches[0] != obj->stride) {
14547 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14548 mode_cmd->pitches[0], obj->stride);
14549 return -EINVAL;
14550 }
14551
14552 /* Reject formats not supported by any plane early. */
14553 switch (mode_cmd->pixel_format) {
14554 case DRM_FORMAT_C8:
14555 case DRM_FORMAT_RGB565:
14556 case DRM_FORMAT_XRGB8888:
14557 case DRM_FORMAT_ARGB8888:
14558 break;
14559 case DRM_FORMAT_XRGB1555:
14560 if (INTEL_INFO(dev)->gen > 3) {
14561 DRM_DEBUG("unsupported pixel format: %s\n",
14562 drm_get_format_name(mode_cmd->pixel_format));
14563 return -EINVAL;
14564 }
14565 break;
14566 case DRM_FORMAT_ABGR8888:
14567 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14568 DRM_DEBUG("unsupported pixel format: %s\n",
14569 drm_get_format_name(mode_cmd->pixel_format));
14570 return -EINVAL;
14571 }
14572 break;
14573 case DRM_FORMAT_XBGR8888:
14574 case DRM_FORMAT_XRGB2101010:
14575 case DRM_FORMAT_XBGR2101010:
14576 if (INTEL_INFO(dev)->gen < 4) {
14577 DRM_DEBUG("unsupported pixel format: %s\n",
14578 drm_get_format_name(mode_cmd->pixel_format));
14579 return -EINVAL;
14580 }
14581 break;
14582 case DRM_FORMAT_ABGR2101010:
14583 if (!IS_VALLEYVIEW(dev)) {
14584 DRM_DEBUG("unsupported pixel format: %s\n",
14585 drm_get_format_name(mode_cmd->pixel_format));
14586 return -EINVAL;
14587 }
14588 break;
14589 case DRM_FORMAT_YUYV:
14590 case DRM_FORMAT_UYVY:
14591 case DRM_FORMAT_YVYU:
14592 case DRM_FORMAT_VYUY:
14593 if (INTEL_INFO(dev)->gen < 5) {
14594 DRM_DEBUG("unsupported pixel format: %s\n",
14595 drm_get_format_name(mode_cmd->pixel_format));
14596 return -EINVAL;
14597 }
14598 break;
14599 default:
14600 DRM_DEBUG("unsupported pixel format: %s\n",
14601 drm_get_format_name(mode_cmd->pixel_format));
14602 return -EINVAL;
14603 }
14604
14605 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14606 if (mode_cmd->offsets[0] != 0)
14607 return -EINVAL;
14608
14609 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14610 mode_cmd->pixel_format,
14611 mode_cmd->modifier[0]);
14612 /* FIXME drm helper for size checks (especially planar formats)? */
14613 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14614 return -EINVAL;
14615
14616 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14617 intel_fb->obj = obj;
14618 intel_fb->obj->framebuffer_references++;
14619
14620 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14621 if (ret) {
14622 DRM_ERROR("framebuffer init failed %d\n", ret);
14623 return ret;
14624 }
14625
14626 return 0;
14627 }
14628
14629 static struct drm_framebuffer *
14630 intel_user_framebuffer_create(struct drm_device *dev,
14631 struct drm_file *filp,
14632 struct drm_mode_fb_cmd2 *mode_cmd)
14633 {
14634 struct drm_i915_gem_object *obj;
14635
14636 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14637 mode_cmd->handles[0]));
14638 if (&obj->base == NULL)
14639 return ERR_PTR(-ENOENT);
14640
14641 return intel_framebuffer_create(dev, mode_cmd, obj);
14642 }
14643
14644 #ifndef CONFIG_DRM_I915_FBDEV
14645 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14646 {
14647 }
14648 #endif
14649
14650 static const struct drm_mode_config_funcs intel_mode_funcs = {
14651 .fb_create = intel_user_framebuffer_create,
14652 .output_poll_changed = intel_fbdev_output_poll_changed,
14653 .atomic_check = intel_atomic_check,
14654 .atomic_commit = intel_atomic_commit,
14655 .atomic_state_alloc = intel_atomic_state_alloc,
14656 .atomic_state_clear = intel_atomic_state_clear,
14657 };
14658
14659 /* Set up chip specific display functions */
14660 static void intel_init_display(struct drm_device *dev)
14661 {
14662 struct drm_i915_private *dev_priv = dev->dev_private;
14663
14664 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14665 dev_priv->display.find_dpll = g4x_find_best_dpll;
14666 else if (IS_CHERRYVIEW(dev))
14667 dev_priv->display.find_dpll = chv_find_best_dpll;
14668 else if (IS_VALLEYVIEW(dev))
14669 dev_priv->display.find_dpll = vlv_find_best_dpll;
14670 else if (IS_PINEVIEW(dev))
14671 dev_priv->display.find_dpll = pnv_find_best_dpll;
14672 else
14673 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14674
14675 if (INTEL_INFO(dev)->gen >= 9) {
14676 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14677 dev_priv->display.get_initial_plane_config =
14678 skylake_get_initial_plane_config;
14679 dev_priv->display.crtc_compute_clock =
14680 haswell_crtc_compute_clock;
14681 dev_priv->display.crtc_enable = haswell_crtc_enable;
14682 dev_priv->display.crtc_disable = haswell_crtc_disable;
14683 dev_priv->display.update_primary_plane =
14684 skylake_update_primary_plane;
14685 } else if (HAS_DDI(dev)) {
14686 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14687 dev_priv->display.get_initial_plane_config =
14688 ironlake_get_initial_plane_config;
14689 dev_priv->display.crtc_compute_clock =
14690 haswell_crtc_compute_clock;
14691 dev_priv->display.crtc_enable = haswell_crtc_enable;
14692 dev_priv->display.crtc_disable = haswell_crtc_disable;
14693 dev_priv->display.update_primary_plane =
14694 ironlake_update_primary_plane;
14695 } else if (HAS_PCH_SPLIT(dev)) {
14696 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14697 dev_priv->display.get_initial_plane_config =
14698 ironlake_get_initial_plane_config;
14699 dev_priv->display.crtc_compute_clock =
14700 ironlake_crtc_compute_clock;
14701 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14702 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14703 dev_priv->display.update_primary_plane =
14704 ironlake_update_primary_plane;
14705 } else if (IS_VALLEYVIEW(dev)) {
14706 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14707 dev_priv->display.get_initial_plane_config =
14708 i9xx_get_initial_plane_config;
14709 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14710 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14711 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14712 dev_priv->display.update_primary_plane =
14713 i9xx_update_primary_plane;
14714 } else {
14715 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14716 dev_priv->display.get_initial_plane_config =
14717 i9xx_get_initial_plane_config;
14718 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14719 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14720 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14721 dev_priv->display.update_primary_plane =
14722 i9xx_update_primary_plane;
14723 }
14724
14725 /* Returns the core display clock speed */
14726 if (IS_SKYLAKE(dev))
14727 dev_priv->display.get_display_clock_speed =
14728 skylake_get_display_clock_speed;
14729 else if (IS_BROADWELL(dev))
14730 dev_priv->display.get_display_clock_speed =
14731 broadwell_get_display_clock_speed;
14732 else if (IS_HASWELL(dev))
14733 dev_priv->display.get_display_clock_speed =
14734 haswell_get_display_clock_speed;
14735 else if (IS_VALLEYVIEW(dev))
14736 dev_priv->display.get_display_clock_speed =
14737 valleyview_get_display_clock_speed;
14738 else if (IS_GEN5(dev))
14739 dev_priv->display.get_display_clock_speed =
14740 ilk_get_display_clock_speed;
14741 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14742 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14743 dev_priv->display.get_display_clock_speed =
14744 i945_get_display_clock_speed;
14745 else if (IS_GM45(dev))
14746 dev_priv->display.get_display_clock_speed =
14747 gm45_get_display_clock_speed;
14748 else if (IS_CRESTLINE(dev))
14749 dev_priv->display.get_display_clock_speed =
14750 i965gm_get_display_clock_speed;
14751 else if (IS_PINEVIEW(dev))
14752 dev_priv->display.get_display_clock_speed =
14753 pnv_get_display_clock_speed;
14754 else if (IS_G33(dev) || IS_G4X(dev))
14755 dev_priv->display.get_display_clock_speed =
14756 g33_get_display_clock_speed;
14757 else if (IS_I915G(dev))
14758 dev_priv->display.get_display_clock_speed =
14759 i915_get_display_clock_speed;
14760 else if (IS_I945GM(dev) || IS_845G(dev))
14761 dev_priv->display.get_display_clock_speed =
14762 i9xx_misc_get_display_clock_speed;
14763 else if (IS_PINEVIEW(dev))
14764 dev_priv->display.get_display_clock_speed =
14765 pnv_get_display_clock_speed;
14766 else if (IS_I915GM(dev))
14767 dev_priv->display.get_display_clock_speed =
14768 i915gm_get_display_clock_speed;
14769 else if (IS_I865G(dev))
14770 dev_priv->display.get_display_clock_speed =
14771 i865_get_display_clock_speed;
14772 else if (IS_I85X(dev))
14773 dev_priv->display.get_display_clock_speed =
14774 i85x_get_display_clock_speed;
14775 else { /* 830 */
14776 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14777 dev_priv->display.get_display_clock_speed =
14778 i830_get_display_clock_speed;
14779 }
14780
14781 if (IS_GEN5(dev)) {
14782 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14783 } else if (IS_GEN6(dev)) {
14784 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14785 } else if (IS_IVYBRIDGE(dev)) {
14786 /* FIXME: detect B0+ stepping and use auto training */
14787 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14788 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14789 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14790 if (IS_BROADWELL(dev))
14791 dev_priv->display.modeset_global_resources =
14792 broadwell_modeset_global_resources;
14793 } else if (IS_VALLEYVIEW(dev)) {
14794 dev_priv->display.modeset_global_resources =
14795 valleyview_modeset_global_resources;
14796 } else if (IS_BROXTON(dev)) {
14797 dev_priv->display.modeset_global_resources =
14798 broxton_modeset_global_resources;
14799 }
14800
14801 switch (INTEL_INFO(dev)->gen) {
14802 case 2:
14803 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14804 break;
14805
14806 case 3:
14807 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14808 break;
14809
14810 case 4:
14811 case 5:
14812 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14813 break;
14814
14815 case 6:
14816 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14817 break;
14818 case 7:
14819 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14820 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14821 break;
14822 case 9:
14823 /* Drop through - unsupported since execlist only. */
14824 default:
14825 /* Default just returns -ENODEV to indicate unsupported */
14826 dev_priv->display.queue_flip = intel_default_queue_flip;
14827 }
14828
14829 intel_panel_init_backlight_funcs(dev);
14830
14831 mutex_init(&dev_priv->pps_mutex);
14832 }
14833
14834 /*
14835 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14836 * resume, or other times. This quirk makes sure that's the case for
14837 * affected systems.
14838 */
14839 static void quirk_pipea_force(struct drm_device *dev)
14840 {
14841 struct drm_i915_private *dev_priv = dev->dev_private;
14842
14843 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14844 DRM_INFO("applying pipe a force quirk\n");
14845 }
14846
14847 static void quirk_pipeb_force(struct drm_device *dev)
14848 {
14849 struct drm_i915_private *dev_priv = dev->dev_private;
14850
14851 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14852 DRM_INFO("applying pipe b force quirk\n");
14853 }
14854
14855 /*
14856 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14857 */
14858 static void quirk_ssc_force_disable(struct drm_device *dev)
14859 {
14860 struct drm_i915_private *dev_priv = dev->dev_private;
14861 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14862 DRM_INFO("applying lvds SSC disable quirk\n");
14863 }
14864
14865 /*
14866 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14867 * brightness value
14868 */
14869 static void quirk_invert_brightness(struct drm_device *dev)
14870 {
14871 struct drm_i915_private *dev_priv = dev->dev_private;
14872 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14873 DRM_INFO("applying inverted panel brightness quirk\n");
14874 }
14875
14876 /* Some VBT's incorrectly indicate no backlight is present */
14877 static void quirk_backlight_present(struct drm_device *dev)
14878 {
14879 struct drm_i915_private *dev_priv = dev->dev_private;
14880 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14881 DRM_INFO("applying backlight present quirk\n");
14882 }
14883
14884 struct intel_quirk {
14885 int device;
14886 int subsystem_vendor;
14887 int subsystem_device;
14888 void (*hook)(struct drm_device *dev);
14889 };
14890
14891 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14892 struct intel_dmi_quirk {
14893 void (*hook)(struct drm_device *dev);
14894 const struct dmi_system_id (*dmi_id_list)[];
14895 };
14896
14897 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14898 {
14899 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14900 return 1;
14901 }
14902
14903 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14904 {
14905 .dmi_id_list = &(const struct dmi_system_id[]) {
14906 {
14907 .callback = intel_dmi_reverse_brightness,
14908 .ident = "NCR Corporation",
14909 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14910 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14911 },
14912 },
14913 { } /* terminating entry */
14914 },
14915 .hook = quirk_invert_brightness,
14916 },
14917 };
14918
14919 static struct intel_quirk intel_quirks[] = {
14920 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14921 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14922
14923 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14924 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14925
14926 /* 830 needs to leave pipe A & dpll A up */
14927 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14928
14929 /* 830 needs to leave pipe B & dpll B up */
14930 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14931
14932 /* Lenovo U160 cannot use SSC on LVDS */
14933 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14934
14935 /* Sony Vaio Y cannot use SSC on LVDS */
14936 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14937
14938 /* Acer Aspire 5734Z must invert backlight brightness */
14939 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14940
14941 /* Acer/eMachines G725 */
14942 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14943
14944 /* Acer/eMachines e725 */
14945 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14946
14947 /* Acer/Packard Bell NCL20 */
14948 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14949
14950 /* Acer Aspire 4736Z */
14951 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14952
14953 /* Acer Aspire 5336 */
14954 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14955
14956 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14957 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14958
14959 /* Acer C720 Chromebook (Core i3 4005U) */
14960 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14961
14962 /* Apple Macbook 2,1 (Core 2 T7400) */
14963 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14964
14965 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14966 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14967
14968 /* HP Chromebook 14 (Celeron 2955U) */
14969 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14970
14971 /* Dell Chromebook 11 */
14972 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14973 };
14974
14975 static void intel_init_quirks(struct drm_device *dev)
14976 {
14977 struct pci_dev *d = dev->pdev;
14978 int i;
14979
14980 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14981 struct intel_quirk *q = &intel_quirks[i];
14982
14983 if (d->device == q->device &&
14984 (d->subsystem_vendor == q->subsystem_vendor ||
14985 q->subsystem_vendor == PCI_ANY_ID) &&
14986 (d->subsystem_device == q->subsystem_device ||
14987 q->subsystem_device == PCI_ANY_ID))
14988 q->hook(dev);
14989 }
14990 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14991 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14992 intel_dmi_quirks[i].hook(dev);
14993 }
14994 }
14995
14996 /* Disable the VGA plane that we never use */
14997 static void i915_disable_vga(struct drm_device *dev)
14998 {
14999 struct drm_i915_private *dev_priv = dev->dev_private;
15000 u8 sr1;
15001 u32 vga_reg = i915_vgacntrl_reg(dev);
15002
15003 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15004 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15005 outb(SR01, VGA_SR_INDEX);
15006 sr1 = inb(VGA_SR_DATA);
15007 outb(sr1 | 1<<5, VGA_SR_DATA);
15008 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15009 udelay(300);
15010
15011 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15012 POSTING_READ(vga_reg);
15013 }
15014
15015 void intel_modeset_init_hw(struct drm_device *dev)
15016 {
15017 intel_update_cdclk(dev);
15018 intel_prepare_ddi(dev);
15019 intel_init_clock_gating(dev);
15020 intel_enable_gt_powersave(dev);
15021 }
15022
15023 void intel_modeset_init(struct drm_device *dev)
15024 {
15025 struct drm_i915_private *dev_priv = dev->dev_private;
15026 int sprite, ret;
15027 enum pipe pipe;
15028 struct intel_crtc *crtc;
15029
15030 drm_mode_config_init(dev);
15031
15032 dev->mode_config.min_width = 0;
15033 dev->mode_config.min_height = 0;
15034
15035 dev->mode_config.preferred_depth = 24;
15036 dev->mode_config.prefer_shadow = 1;
15037
15038 dev->mode_config.allow_fb_modifiers = true;
15039
15040 dev->mode_config.funcs = &intel_mode_funcs;
15041
15042 intel_init_quirks(dev);
15043
15044 intel_init_pm(dev);
15045
15046 if (INTEL_INFO(dev)->num_pipes == 0)
15047 return;
15048
15049 intel_init_display(dev);
15050 intel_init_audio(dev);
15051
15052 if (IS_GEN2(dev)) {
15053 dev->mode_config.max_width = 2048;
15054 dev->mode_config.max_height = 2048;
15055 } else if (IS_GEN3(dev)) {
15056 dev->mode_config.max_width = 4096;
15057 dev->mode_config.max_height = 4096;
15058 } else {
15059 dev->mode_config.max_width = 8192;
15060 dev->mode_config.max_height = 8192;
15061 }
15062
15063 if (IS_845G(dev) || IS_I865G(dev)) {
15064 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15065 dev->mode_config.cursor_height = 1023;
15066 } else if (IS_GEN2(dev)) {
15067 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15068 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15069 } else {
15070 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15071 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15072 }
15073
15074 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15075
15076 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15077 INTEL_INFO(dev)->num_pipes,
15078 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15079
15080 for_each_pipe(dev_priv, pipe) {
15081 intel_crtc_init(dev, pipe);
15082 for_each_sprite(dev_priv, pipe, sprite) {
15083 ret = intel_plane_init(dev, pipe, sprite);
15084 if (ret)
15085 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15086 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15087 }
15088 }
15089
15090 intel_init_dpio(dev);
15091
15092 intel_shared_dpll_init(dev);
15093
15094 /* Just disable it once at startup */
15095 i915_disable_vga(dev);
15096 intel_setup_outputs(dev);
15097
15098 /* Just in case the BIOS is doing something questionable. */
15099 intel_fbc_disable(dev);
15100
15101 drm_modeset_lock_all(dev);
15102 intel_modeset_setup_hw_state(dev, false);
15103 drm_modeset_unlock_all(dev);
15104
15105 for_each_intel_crtc(dev, crtc) {
15106 if (!crtc->active)
15107 continue;
15108
15109 /*
15110 * Note that reserving the BIOS fb up front prevents us
15111 * from stuffing other stolen allocations like the ring
15112 * on top. This prevents some ugliness at boot time, and
15113 * can even allow for smooth boot transitions if the BIOS
15114 * fb is large enough for the active pipe configuration.
15115 */
15116 if (dev_priv->display.get_initial_plane_config) {
15117 dev_priv->display.get_initial_plane_config(crtc,
15118 &crtc->plane_config);
15119 /*
15120 * If the fb is shared between multiple heads, we'll
15121 * just get the first one.
15122 */
15123 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15124 }
15125 }
15126 }
15127
15128 static void intel_enable_pipe_a(struct drm_device *dev)
15129 {
15130 struct intel_connector *connector;
15131 struct drm_connector *crt = NULL;
15132 struct intel_load_detect_pipe load_detect_temp;
15133 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15134
15135 /* We can't just switch on the pipe A, we need to set things up with a
15136 * proper mode and output configuration. As a gross hack, enable pipe A
15137 * by enabling the load detect pipe once. */
15138 for_each_intel_connector(dev, connector) {
15139 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15140 crt = &connector->base;
15141 break;
15142 }
15143 }
15144
15145 if (!crt)
15146 return;
15147
15148 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15149 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15150 }
15151
15152 static bool
15153 intel_check_plane_mapping(struct intel_crtc *crtc)
15154 {
15155 struct drm_device *dev = crtc->base.dev;
15156 struct drm_i915_private *dev_priv = dev->dev_private;
15157 u32 reg, val;
15158
15159 if (INTEL_INFO(dev)->num_pipes == 1)
15160 return true;
15161
15162 reg = DSPCNTR(!crtc->plane);
15163 val = I915_READ(reg);
15164
15165 if ((val & DISPLAY_PLANE_ENABLE) &&
15166 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15167 return false;
15168
15169 return true;
15170 }
15171
15172 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15173 {
15174 struct drm_device *dev = crtc->base.dev;
15175 struct drm_i915_private *dev_priv = dev->dev_private;
15176 struct intel_encoder *encoder;
15177 u32 reg;
15178 bool enable;
15179
15180 /* Clear any frame start delays used for debugging left by the BIOS */
15181 reg = PIPECONF(crtc->config->cpu_transcoder);
15182 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15183
15184 /* restore vblank interrupts to correct state */
15185 drm_crtc_vblank_reset(&crtc->base);
15186 if (crtc->active) {
15187 update_scanline_offset(crtc);
15188 drm_crtc_vblank_on(&crtc->base);
15189 }
15190
15191 /* We need to sanitize the plane -> pipe mapping first because this will
15192 * disable the crtc (and hence change the state) if it is wrong. Note
15193 * that gen4+ has a fixed plane -> pipe mapping. */
15194 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15195 bool plane;
15196
15197 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15198 crtc->base.base.id);
15199
15200 /* Pipe has the wrong plane attached and the plane is active.
15201 * Temporarily change the plane mapping and disable everything
15202 * ... */
15203 plane = crtc->plane;
15204 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15205 crtc->plane = !plane;
15206 intel_crtc_disable_noatomic(&crtc->base);
15207 crtc->plane = plane;
15208 }
15209
15210 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15211 crtc->pipe == PIPE_A && !crtc->active) {
15212 /* BIOS forgot to enable pipe A, this mostly happens after
15213 * resume. Force-enable the pipe to fix this, the update_dpms
15214 * call below we restore the pipe to the right state, but leave
15215 * the required bits on. */
15216 intel_enable_pipe_a(dev);
15217 }
15218
15219 /* Adjust the state of the output pipe according to whether we
15220 * have active connectors/encoders. */
15221 enable = false;
15222 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15223 enable |= encoder->connectors_active;
15224
15225 if (!enable)
15226 intel_crtc_disable_noatomic(&crtc->base);
15227
15228 if (crtc->active != crtc->base.state->active) {
15229
15230 /* This can happen either due to bugs in the get_hw_state
15231 * functions or because of calls to intel_crtc_disable_noatomic,
15232 * or because the pipe is force-enabled due to the
15233 * pipe A quirk. */
15234 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15235 crtc->base.base.id,
15236 crtc->base.state->enable ? "enabled" : "disabled",
15237 crtc->active ? "enabled" : "disabled");
15238
15239 crtc->base.state->enable = crtc->active;
15240 crtc->base.state->active = crtc->active;
15241 crtc->base.enabled = crtc->active;
15242
15243 /* Because we only establish the connector -> encoder ->
15244 * crtc links if something is active, this means the
15245 * crtc is now deactivated. Break the links. connector
15246 * -> encoder links are only establish when things are
15247 * actually up, hence no need to break them. */
15248 WARN_ON(crtc->active);
15249
15250 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15251 WARN_ON(encoder->connectors_active);
15252 encoder->base.crtc = NULL;
15253 }
15254 }
15255
15256 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15257 /*
15258 * We start out with underrun reporting disabled to avoid races.
15259 * For correct bookkeeping mark this on active crtcs.
15260 *
15261 * Also on gmch platforms we dont have any hardware bits to
15262 * disable the underrun reporting. Which means we need to start
15263 * out with underrun reporting disabled also on inactive pipes,
15264 * since otherwise we'll complain about the garbage we read when
15265 * e.g. coming up after runtime pm.
15266 *
15267 * No protection against concurrent access is required - at
15268 * worst a fifo underrun happens which also sets this to false.
15269 */
15270 crtc->cpu_fifo_underrun_disabled = true;
15271 crtc->pch_fifo_underrun_disabled = true;
15272 }
15273 }
15274
15275 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15276 {
15277 struct intel_connector *connector;
15278 struct drm_device *dev = encoder->base.dev;
15279
15280 /* We need to check both for a crtc link (meaning that the
15281 * encoder is active and trying to read from a pipe) and the
15282 * pipe itself being active. */
15283 bool has_active_crtc = encoder->base.crtc &&
15284 to_intel_crtc(encoder->base.crtc)->active;
15285
15286 if (encoder->connectors_active && !has_active_crtc) {
15287 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15288 encoder->base.base.id,
15289 encoder->base.name);
15290
15291 /* Connector is active, but has no active pipe. This is
15292 * fallout from our resume register restoring. Disable
15293 * the encoder manually again. */
15294 if (encoder->base.crtc) {
15295 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15296 encoder->base.base.id,
15297 encoder->base.name);
15298 encoder->disable(encoder);
15299 if (encoder->post_disable)
15300 encoder->post_disable(encoder);
15301 }
15302 encoder->base.crtc = NULL;
15303 encoder->connectors_active = false;
15304
15305 /* Inconsistent output/port/pipe state happens presumably due to
15306 * a bug in one of the get_hw_state functions. Or someplace else
15307 * in our code, like the register restore mess on resume. Clamp
15308 * things to off as a safer default. */
15309 for_each_intel_connector(dev, connector) {
15310 if (connector->encoder != encoder)
15311 continue;
15312 connector->base.dpms = DRM_MODE_DPMS_OFF;
15313 connector->base.encoder = NULL;
15314 }
15315 }
15316 /* Enabled encoders without active connectors will be fixed in
15317 * the crtc fixup. */
15318 }
15319
15320 void i915_redisable_vga_power_on(struct drm_device *dev)
15321 {
15322 struct drm_i915_private *dev_priv = dev->dev_private;
15323 u32 vga_reg = i915_vgacntrl_reg(dev);
15324
15325 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15326 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15327 i915_disable_vga(dev);
15328 }
15329 }
15330
15331 void i915_redisable_vga(struct drm_device *dev)
15332 {
15333 struct drm_i915_private *dev_priv = dev->dev_private;
15334
15335 /* This function can be called both from intel_modeset_setup_hw_state or
15336 * at a very early point in our resume sequence, where the power well
15337 * structures are not yet restored. Since this function is at a very
15338 * paranoid "someone might have enabled VGA while we were not looking"
15339 * level, just check if the power well is enabled instead of trying to
15340 * follow the "don't touch the power well if we don't need it" policy
15341 * the rest of the driver uses. */
15342 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15343 return;
15344
15345 i915_redisable_vga_power_on(dev);
15346 }
15347
15348 static bool primary_get_hw_state(struct intel_crtc *crtc)
15349 {
15350 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15351
15352 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15353 }
15354
15355 static void readout_plane_state(struct intel_crtc *crtc,
15356 struct intel_crtc_state *crtc_state)
15357 {
15358 struct intel_plane *p;
15359 struct drm_plane_state *drm_plane_state;
15360 bool active = crtc_state->base.active;
15361
15362 if (active) {
15363 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15364
15365 /* apply to previous sw state too */
15366 to_intel_crtc_state(crtc->base.state)->quirks |=
15367 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15368 }
15369
15370 for_each_intel_plane(crtc->base.dev, p) {
15371 bool visible = active;
15372
15373 if (crtc->pipe != p->pipe)
15374 continue;
15375
15376 drm_plane_state = p->base.state;
15377 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15378 visible = primary_get_hw_state(crtc);
15379 to_intel_plane_state(drm_plane_state)->visible = visible;
15380 } else {
15381 /*
15382 * unknown state, assume it's off to force a transition
15383 * to on when calculating state changes.
15384 */
15385 to_intel_plane_state(drm_plane_state)->visible = false;
15386 }
15387
15388 if (visible) {
15389 crtc_state->base.plane_mask |=
15390 1 << drm_plane_index(&p->base);
15391 } else if (crtc_state->base.state) {
15392 /* Make this unconditional for atomic hw readout. */
15393 crtc_state->base.plane_mask &=
15394 ~(1 << drm_plane_index(&p->base));
15395 }
15396 }
15397 }
15398
15399 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15400 {
15401 struct drm_i915_private *dev_priv = dev->dev_private;
15402 enum pipe pipe;
15403 struct intel_crtc *crtc;
15404 struct intel_encoder *encoder;
15405 struct intel_connector *connector;
15406 int i;
15407
15408 for_each_intel_crtc(dev, crtc) {
15409 memset(crtc->config, 0, sizeof(*crtc->config));
15410 crtc->config->base.crtc = &crtc->base;
15411
15412 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15413
15414 crtc->active = dev_priv->display.get_pipe_config(crtc,
15415 crtc->config);
15416
15417 crtc->base.state->enable = crtc->active;
15418 crtc->base.state->active = crtc->active;
15419 crtc->base.enabled = crtc->active;
15420 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15421
15422 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15423
15424 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15425 crtc->base.base.id,
15426 crtc->active ? "enabled" : "disabled");
15427 }
15428
15429 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15430 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15431
15432 pll->on = pll->get_hw_state(dev_priv, pll,
15433 &pll->config.hw_state);
15434 pll->active = 0;
15435 pll->config.crtc_mask = 0;
15436 for_each_intel_crtc(dev, crtc) {
15437 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15438 pll->active++;
15439 pll->config.crtc_mask |= 1 << crtc->pipe;
15440 }
15441 }
15442
15443 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15444 pll->name, pll->config.crtc_mask, pll->on);
15445
15446 if (pll->config.crtc_mask)
15447 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15448 }
15449
15450 for_each_intel_encoder(dev, encoder) {
15451 pipe = 0;
15452
15453 if (encoder->get_hw_state(encoder, &pipe)) {
15454 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15455 encoder->base.crtc = &crtc->base;
15456 encoder->get_config(encoder, crtc->config);
15457 } else {
15458 encoder->base.crtc = NULL;
15459 }
15460
15461 encoder->connectors_active = false;
15462 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15463 encoder->base.base.id,
15464 encoder->base.name,
15465 encoder->base.crtc ? "enabled" : "disabled",
15466 pipe_name(pipe));
15467 }
15468
15469 for_each_intel_connector(dev, connector) {
15470 if (connector->get_hw_state(connector)) {
15471 connector->base.dpms = DRM_MODE_DPMS_ON;
15472 connector->encoder->connectors_active = true;
15473 connector->base.encoder = &connector->encoder->base;
15474 } else {
15475 connector->base.dpms = DRM_MODE_DPMS_OFF;
15476 connector->base.encoder = NULL;
15477 }
15478 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15479 connector->base.base.id,
15480 connector->base.name,
15481 connector->base.encoder ? "enabled" : "disabled");
15482 }
15483 }
15484
15485 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15486 * and i915 state tracking structures. */
15487 void intel_modeset_setup_hw_state(struct drm_device *dev,
15488 bool force_restore)
15489 {
15490 struct drm_i915_private *dev_priv = dev->dev_private;
15491 enum pipe pipe;
15492 struct intel_crtc *crtc;
15493 struct intel_encoder *encoder;
15494 int i;
15495
15496 intel_modeset_readout_hw_state(dev);
15497
15498 /*
15499 * Now that we have the config, copy it to each CRTC struct
15500 * Note that this could go away if we move to using crtc_config
15501 * checking everywhere.
15502 */
15503 for_each_intel_crtc(dev, crtc) {
15504 if (crtc->active && i915.fastboot) {
15505 intel_mode_from_pipe_config(&crtc->base.mode,
15506 crtc->config);
15507 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15508 crtc->base.base.id);
15509 drm_mode_debug_printmodeline(&crtc->base.mode);
15510 }
15511 }
15512
15513 /* HW state is read out, now we need to sanitize this mess. */
15514 for_each_intel_encoder(dev, encoder) {
15515 intel_sanitize_encoder(encoder);
15516 }
15517
15518 for_each_pipe(dev_priv, pipe) {
15519 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15520 intel_sanitize_crtc(crtc);
15521 intel_dump_pipe_config(crtc, crtc->config,
15522 "[setup_hw_state]");
15523 }
15524
15525 intel_modeset_update_connector_atomic_state(dev);
15526
15527 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15528 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15529
15530 if (!pll->on || pll->active)
15531 continue;
15532
15533 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15534
15535 pll->disable(dev_priv, pll);
15536 pll->on = false;
15537 }
15538
15539 if (IS_GEN9(dev))
15540 skl_wm_get_hw_state(dev);
15541 else if (HAS_PCH_SPLIT(dev))
15542 ilk_wm_get_hw_state(dev);
15543
15544 if (force_restore) {
15545 i915_redisable_vga(dev);
15546
15547 /*
15548 * We need to use raw interfaces for restoring state to avoid
15549 * checking (bogus) intermediate states.
15550 */
15551 for_each_pipe(dev_priv, pipe) {
15552 struct drm_crtc *crtc =
15553 dev_priv->pipe_to_crtc_mapping[pipe];
15554
15555 intel_crtc_restore_mode(crtc);
15556 }
15557 } else {
15558 intel_modeset_update_staged_output_state(dev);
15559 }
15560
15561 intel_modeset_check_state(dev);
15562 }
15563
15564 void intel_modeset_gem_init(struct drm_device *dev)
15565 {
15566 struct drm_i915_private *dev_priv = dev->dev_private;
15567 struct drm_crtc *c;
15568 struct drm_i915_gem_object *obj;
15569 int ret;
15570
15571 mutex_lock(&dev->struct_mutex);
15572 intel_init_gt_powersave(dev);
15573 mutex_unlock(&dev->struct_mutex);
15574
15575 /*
15576 * There may be no VBT; and if the BIOS enabled SSC we can
15577 * just keep using it to avoid unnecessary flicker. Whereas if the
15578 * BIOS isn't using it, don't assume it will work even if the VBT
15579 * indicates as much.
15580 */
15581 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15582 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15583 DREF_SSC1_ENABLE);
15584
15585 intel_modeset_init_hw(dev);
15586
15587 intel_setup_overlay(dev);
15588
15589 /*
15590 * Make sure any fbs we allocated at startup are properly
15591 * pinned & fenced. When we do the allocation it's too early
15592 * for this.
15593 */
15594 for_each_crtc(dev, c) {
15595 obj = intel_fb_obj(c->primary->fb);
15596 if (obj == NULL)
15597 continue;
15598
15599 mutex_lock(&dev->struct_mutex);
15600 ret = intel_pin_and_fence_fb_obj(c->primary,
15601 c->primary->fb,
15602 c->primary->state,
15603 NULL);
15604 mutex_unlock(&dev->struct_mutex);
15605 if (ret) {
15606 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15607 to_intel_crtc(c)->pipe);
15608 drm_framebuffer_unreference(c->primary->fb);
15609 c->primary->fb = NULL;
15610 c->primary->crtc = c->primary->state->crtc = NULL;
15611 update_state_fb(c->primary);
15612 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15613 }
15614 }
15615
15616 intel_backlight_register(dev);
15617 }
15618
15619 void intel_connector_unregister(struct intel_connector *intel_connector)
15620 {
15621 struct drm_connector *connector = &intel_connector->base;
15622
15623 intel_panel_destroy_backlight(connector);
15624 drm_connector_unregister(connector);
15625 }
15626
15627 void intel_modeset_cleanup(struct drm_device *dev)
15628 {
15629 struct drm_i915_private *dev_priv = dev->dev_private;
15630 struct drm_connector *connector;
15631
15632 intel_disable_gt_powersave(dev);
15633
15634 intel_backlight_unregister(dev);
15635
15636 /*
15637 * Interrupts and polling as the first thing to avoid creating havoc.
15638 * Too much stuff here (turning of connectors, ...) would
15639 * experience fancy races otherwise.
15640 */
15641 intel_irq_uninstall(dev_priv);
15642
15643 /*
15644 * Due to the hpd irq storm handling the hotplug work can re-arm the
15645 * poll handlers. Hence disable polling after hpd handling is shut down.
15646 */
15647 drm_kms_helper_poll_fini(dev);
15648
15649 mutex_lock(&dev->struct_mutex);
15650
15651 intel_unregister_dsm_handler();
15652
15653 intel_fbc_disable(dev);
15654
15655 mutex_unlock(&dev->struct_mutex);
15656
15657 /* flush any delayed tasks or pending work */
15658 flush_scheduled_work();
15659
15660 /* destroy the backlight and sysfs files before encoders/connectors */
15661 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15662 struct intel_connector *intel_connector;
15663
15664 intel_connector = to_intel_connector(connector);
15665 intel_connector->unregister(intel_connector);
15666 }
15667
15668 drm_mode_config_cleanup(dev);
15669
15670 intel_cleanup_overlay(dev);
15671
15672 mutex_lock(&dev->struct_mutex);
15673 intel_cleanup_gt_powersave(dev);
15674 mutex_unlock(&dev->struct_mutex);
15675 }
15676
15677 /*
15678 * Return which encoder is currently attached for connector.
15679 */
15680 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15681 {
15682 return &intel_attached_encoder(connector)->base;
15683 }
15684
15685 void intel_connector_attach_encoder(struct intel_connector *connector,
15686 struct intel_encoder *encoder)
15687 {
15688 connector->encoder = encoder;
15689 drm_mode_connector_attach_encoder(&connector->base,
15690 &encoder->base);
15691 }
15692
15693 /*
15694 * set vga decode state - true == enable VGA decode
15695 */
15696 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15697 {
15698 struct drm_i915_private *dev_priv = dev->dev_private;
15699 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15700 u16 gmch_ctrl;
15701
15702 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15703 DRM_ERROR("failed to read control word\n");
15704 return -EIO;
15705 }
15706
15707 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15708 return 0;
15709
15710 if (state)
15711 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15712 else
15713 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15714
15715 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15716 DRM_ERROR("failed to write control word\n");
15717 return -EIO;
15718 }
15719
15720 return 0;
15721 }
15722
15723 struct intel_display_error_state {
15724
15725 u32 power_well_driver;
15726
15727 int num_transcoders;
15728
15729 struct intel_cursor_error_state {
15730 u32 control;
15731 u32 position;
15732 u32 base;
15733 u32 size;
15734 } cursor[I915_MAX_PIPES];
15735
15736 struct intel_pipe_error_state {
15737 bool power_domain_on;
15738 u32 source;
15739 u32 stat;
15740 } pipe[I915_MAX_PIPES];
15741
15742 struct intel_plane_error_state {
15743 u32 control;
15744 u32 stride;
15745 u32 size;
15746 u32 pos;
15747 u32 addr;
15748 u32 surface;
15749 u32 tile_offset;
15750 } plane[I915_MAX_PIPES];
15751
15752 struct intel_transcoder_error_state {
15753 bool power_domain_on;
15754 enum transcoder cpu_transcoder;
15755
15756 u32 conf;
15757
15758 u32 htotal;
15759 u32 hblank;
15760 u32 hsync;
15761 u32 vtotal;
15762 u32 vblank;
15763 u32 vsync;
15764 } transcoder[4];
15765 };
15766
15767 struct intel_display_error_state *
15768 intel_display_capture_error_state(struct drm_device *dev)
15769 {
15770 struct drm_i915_private *dev_priv = dev->dev_private;
15771 struct intel_display_error_state *error;
15772 int transcoders[] = {
15773 TRANSCODER_A,
15774 TRANSCODER_B,
15775 TRANSCODER_C,
15776 TRANSCODER_EDP,
15777 };
15778 int i;
15779
15780 if (INTEL_INFO(dev)->num_pipes == 0)
15781 return NULL;
15782
15783 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15784 if (error == NULL)
15785 return NULL;
15786
15787 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15788 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15789
15790 for_each_pipe(dev_priv, i) {
15791 error->pipe[i].power_domain_on =
15792 __intel_display_power_is_enabled(dev_priv,
15793 POWER_DOMAIN_PIPE(i));
15794 if (!error->pipe[i].power_domain_on)
15795 continue;
15796
15797 error->cursor[i].control = I915_READ(CURCNTR(i));
15798 error->cursor[i].position = I915_READ(CURPOS(i));
15799 error->cursor[i].base = I915_READ(CURBASE(i));
15800
15801 error->plane[i].control = I915_READ(DSPCNTR(i));
15802 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15803 if (INTEL_INFO(dev)->gen <= 3) {
15804 error->plane[i].size = I915_READ(DSPSIZE(i));
15805 error->plane[i].pos = I915_READ(DSPPOS(i));
15806 }
15807 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15808 error->plane[i].addr = I915_READ(DSPADDR(i));
15809 if (INTEL_INFO(dev)->gen >= 4) {
15810 error->plane[i].surface = I915_READ(DSPSURF(i));
15811 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15812 }
15813
15814 error->pipe[i].source = I915_READ(PIPESRC(i));
15815
15816 if (HAS_GMCH_DISPLAY(dev))
15817 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15818 }
15819
15820 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15821 if (HAS_DDI(dev_priv->dev))
15822 error->num_transcoders++; /* Account for eDP. */
15823
15824 for (i = 0; i < error->num_transcoders; i++) {
15825 enum transcoder cpu_transcoder = transcoders[i];
15826
15827 error->transcoder[i].power_domain_on =
15828 __intel_display_power_is_enabled(dev_priv,
15829 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15830 if (!error->transcoder[i].power_domain_on)
15831 continue;
15832
15833 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15834
15835 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15836 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15837 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15838 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15839 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15840 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15841 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15842 }
15843
15844 return error;
15845 }
15846
15847 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15848
15849 void
15850 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15851 struct drm_device *dev,
15852 struct intel_display_error_state *error)
15853 {
15854 struct drm_i915_private *dev_priv = dev->dev_private;
15855 int i;
15856
15857 if (!error)
15858 return;
15859
15860 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15861 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15862 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15863 error->power_well_driver);
15864 for_each_pipe(dev_priv, i) {
15865 err_printf(m, "Pipe [%d]:\n", i);
15866 err_printf(m, " Power: %s\n",
15867 error->pipe[i].power_domain_on ? "on" : "off");
15868 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15869 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15870
15871 err_printf(m, "Plane [%d]:\n", i);
15872 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15873 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15874 if (INTEL_INFO(dev)->gen <= 3) {
15875 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15876 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15877 }
15878 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15879 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15880 if (INTEL_INFO(dev)->gen >= 4) {
15881 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15882 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15883 }
15884
15885 err_printf(m, "Cursor [%d]:\n", i);
15886 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15887 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15888 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15889 }
15890
15891 for (i = 0; i < error->num_transcoders; i++) {
15892 err_printf(m, "CPU transcoder: %c\n",
15893 transcoder_name(error->transcoder[i].cpu_transcoder));
15894 err_printf(m, " Power: %s\n",
15895 error->transcoder[i].power_domain_on ? "on" : "off");
15896 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15897 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15898 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15899 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15900 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15901 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15902 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15903 }
15904 }
15905
15906 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15907 {
15908 struct intel_crtc *crtc;
15909
15910 for_each_intel_crtc(dev, crtc) {
15911 struct intel_unpin_work *work;
15912
15913 spin_lock_irq(&dev->event_lock);
15914
15915 work = crtc->unpin_work;
15916
15917 if (work && work->event &&
15918 work->event->base.file_priv == file) {
15919 kfree(work->event);
15920 work->event = NULL;
15921 }
15922
15923 spin_unlock_irq(&dev->event_lock);
15924 }
15925 }
Linux kernel - Deliverables
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