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drm/i915/hsw: Avoid early timeout during LCPLL disable/restore
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_gem_dmabuf.h"
40 #include "intel_dsi.h"
41 #include "i915_trace.h"
42 #include <drm/drm_atomic.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_dp_helper.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_plane_helper.h>
47 #include <drm/drm_rect.h>
48 #include <linux/dma_remapping.h>
49 #include <linux/reservation.h>
50
51 static bool is_mmio_work(struct intel_flip_work *work)
52 {
53 return work->mmio_work.func;
54 }
55
56 /* Primary plane formats for gen <= 3 */
57 static const uint32_t i8xx_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB1555,
61 DRM_FORMAT_XRGB8888,
62 };
63
64 /* Primary plane formats for gen >= 4 */
65 static const uint32_t i965_primary_formats[] = {
66 DRM_FORMAT_C8,
67 DRM_FORMAT_RGB565,
68 DRM_FORMAT_XRGB8888,
69 DRM_FORMAT_XBGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 };
73
74 static const uint32_t skl_primary_formats[] = {
75 DRM_FORMAT_C8,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_XBGR8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_XRGB2101010,
82 DRM_FORMAT_XBGR2101010,
83 DRM_FORMAT_YUYV,
84 DRM_FORMAT_YVYU,
85 DRM_FORMAT_UYVY,
86 DRM_FORMAT_VYUY,
87 };
88
89 /* Cursor formats */
90 static const uint32_t intel_cursor_formats[] = {
91 DRM_FORMAT_ARGB8888,
92 };
93
94 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
95 struct intel_crtc_state *pipe_config);
96 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 struct intel_crtc_state *pipe_config);
98
99 static int intel_framebuffer_init(struct drm_device *dev,
100 struct intel_framebuffer *ifb,
101 struct drm_mode_fb_cmd2 *mode_cmd,
102 struct drm_i915_gem_object *obj);
103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
112 static void vlv_prepare_pll(struct intel_crtc *crtc,
113 const struct intel_crtc_state *pipe_config);
114 static void chv_prepare_pll(struct intel_crtc *crtc,
115 const struct intel_crtc_state *pipe_config);
116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
119 struct intel_crtc_state *crtc_state);
120 static void skylake_pfit_enable(struct intel_crtc *crtc);
121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
125 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
126 static int bxt_calc_cdclk(int max_pixclk);
127
128 struct intel_limit {
129 struct {
130 int min, max;
131 } dot, vco, n, m, m1, m2, p, p1;
132
133 struct {
134 int dot_limit;
135 int p2_slow, p2_fast;
136 } p2;
137 };
138
139 /* returns HPLL frequency in kHz */
140 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
141 {
142 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
143
144 /* Obtain SKU information */
145 mutex_lock(&dev_priv->sb_lock);
146 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
147 CCK_FUSE_HPLL_FREQ_MASK;
148 mutex_unlock(&dev_priv->sb_lock);
149
150 return vco_freq[hpll_freq] * 1000;
151 }
152
153 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
154 const char *name, u32 reg, int ref_freq)
155 {
156 u32 val;
157 int divider;
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
170 }
171
172 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
173 const char *name, u32 reg)
174 {
175 if (dev_priv->hpll_freq == 0)
176 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
177
178 return vlv_get_cck_clock(dev_priv, name, reg,
179 dev_priv->hpll_freq);
180 }
181
182 static int
183 intel_pch_rawclk(struct drm_i915_private *dev_priv)
184 {
185 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
186 }
187
188 static int
189 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
190 {
191 /* RAWCLK_FREQ_VLV register updated from power well code */
192 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
193 CCK_DISPLAY_REF_CLOCK_CONTROL);
194 }
195
196 static int
197 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
198 {
199 uint32_t clkcfg;
200
201 /* hrawclock is 1/4 the FSB frequency */
202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100000;
206 case CLKCFG_FSB_533:
207 return 133333;
208 case CLKCFG_FSB_667:
209 return 166667;
210 case CLKCFG_FSB_800:
211 return 200000;
212 case CLKCFG_FSB_1067:
213 return 266667;
214 case CLKCFG_FSB_1333:
215 return 333333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400000;
220 default:
221 return 133333;
222 }
223 }
224
225 void intel_update_rawclk(struct drm_i915_private *dev_priv)
226 {
227 if (HAS_PCH_SPLIT(dev_priv))
228 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
229 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
230 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
231 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
232 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
233 else
234 return; /* no rawclk on other platforms, or no need to know it */
235
236 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
237 }
238
239 static void intel_update_czclk(struct drm_i915_private *dev_priv)
240 {
241 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
242 return;
243
244 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
245 CCK_CZ_CLOCK_CONTROL);
246
247 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
248 }
249
250 static inline u32 /* units of 100MHz */
251 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
252 const struct intel_crtc_state *pipe_config)
253 {
254 if (HAS_DDI(dev_priv))
255 return pipe_config->port_clock; /* SPLL */
256 else if (IS_GEN5(dev_priv))
257 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
258 else
259 return 270000;
260 }
261
262 static const struct intel_limit intel_limits_i8xx_dac = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 2, .max = 33 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 4, .p2_fast = 2 },
273 };
274
275 static const struct intel_limit intel_limits_i8xx_dvo = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 908000, .max = 1512000 },
278 .n = { .min = 2, .max = 16 },
279 .m = { .min = 96, .max = 140 },
280 .m1 = { .min = 18, .max = 26 },
281 .m2 = { .min = 6, .max = 16 },
282 .p = { .min = 4, .max = 128 },
283 .p1 = { .min = 2, .max = 33 },
284 .p2 = { .dot_limit = 165000,
285 .p2_slow = 4, .p2_fast = 4 },
286 };
287
288 static const struct intel_limit intel_limits_i8xx_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 908000, .max = 1512000 },
291 .n = { .min = 2, .max = 16 },
292 .m = { .min = 96, .max = 140 },
293 .m1 = { .min = 18, .max = 26 },
294 .m2 = { .min = 6, .max = 16 },
295 .p = { .min = 4, .max = 128 },
296 .p1 = { .min = 1, .max = 6 },
297 .p2 = { .dot_limit = 165000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301 static const struct intel_limit intel_limits_i9xx_sdvo = {
302 .dot = { .min = 20000, .max = 400000 },
303 .vco = { .min = 1400000, .max = 2800000 },
304 .n = { .min = 1, .max = 6 },
305 .m = { .min = 70, .max = 120 },
306 .m1 = { .min = 8, .max = 18 },
307 .m2 = { .min = 3, .max = 7 },
308 .p = { .min = 5, .max = 80 },
309 .p1 = { .min = 1, .max = 8 },
310 .p2 = { .dot_limit = 200000,
311 .p2_slow = 10, .p2_fast = 5 },
312 };
313
314 static const struct intel_limit intel_limits_i9xx_lvds = {
315 .dot = { .min = 20000, .max = 400000 },
316 .vco = { .min = 1400000, .max = 2800000 },
317 .n = { .min = 1, .max = 6 },
318 .m = { .min = 70, .max = 120 },
319 .m1 = { .min = 8, .max = 18 },
320 .m2 = { .min = 3, .max = 7 },
321 .p = { .min = 7, .max = 98 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 112000,
324 .p2_slow = 14, .p2_fast = 7 },
325 };
326
327
328 static const struct intel_limit intel_limits_g4x_sdvo = {
329 .dot = { .min = 25000, .max = 270000 },
330 .vco = { .min = 1750000, .max = 3500000},
331 .n = { .min = 1, .max = 4 },
332 .m = { .min = 104, .max = 138 },
333 .m1 = { .min = 17, .max = 23 },
334 .m2 = { .min = 5, .max = 11 },
335 .p = { .min = 10, .max = 30 },
336 .p1 = { .min = 1, .max = 3},
337 .p2 = { .dot_limit = 270000,
338 .p2_slow = 10,
339 .p2_fast = 10
340 },
341 };
342
343 static const struct intel_limit intel_limits_g4x_hdmi = {
344 .dot = { .min = 22000, .max = 400000 },
345 .vco = { .min = 1750000, .max = 3500000},
346 .n = { .min = 1, .max = 4 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 16, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8},
352 .p2 = { .dot_limit = 165000,
353 .p2_slow = 10, .p2_fast = 5 },
354 };
355
356 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
357 .dot = { .min = 20000, .max = 115000 },
358 .vco = { .min = 1750000, .max = 3500000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 104, .max = 138 },
361 .m1 = { .min = 17, .max = 23 },
362 .m2 = { .min = 5, .max = 11 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 0,
366 .p2_slow = 14, .p2_fast = 14
367 },
368 };
369
370 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
371 .dot = { .min = 80000, .max = 224000 },
372 .vco = { .min = 1750000, .max = 3500000 },
373 .n = { .min = 1, .max = 3 },
374 .m = { .min = 104, .max = 138 },
375 .m1 = { .min = 17, .max = 23 },
376 .m2 = { .min = 5, .max = 11 },
377 .p = { .min = 14, .max = 42 },
378 .p1 = { .min = 2, .max = 6 },
379 .p2 = { .dot_limit = 0,
380 .p2_slow = 7, .p2_fast = 7
381 },
382 };
383
384 static const struct intel_limit intel_limits_pineview_sdvo = {
385 .dot = { .min = 20000, .max = 400000},
386 .vco = { .min = 1700000, .max = 3500000 },
387 /* Pineview's Ncounter is a ring counter */
388 .n = { .min = 3, .max = 6 },
389 .m = { .min = 2, .max = 256 },
390 /* Pineview only has one combined m divider, which we treat as m2. */
391 .m1 = { .min = 0, .max = 0 },
392 .m2 = { .min = 0, .max = 254 },
393 .p = { .min = 5, .max = 80 },
394 .p1 = { .min = 1, .max = 8 },
395 .p2 = { .dot_limit = 200000,
396 .p2_slow = 10, .p2_fast = 5 },
397 };
398
399 static const struct intel_limit intel_limits_pineview_lvds = {
400 .dot = { .min = 20000, .max = 400000 },
401 .vco = { .min = 1700000, .max = 3500000 },
402 .n = { .min = 3, .max = 6 },
403 .m = { .min = 2, .max = 256 },
404 .m1 = { .min = 0, .max = 0 },
405 .m2 = { .min = 0, .max = 254 },
406 .p = { .min = 7, .max = 112 },
407 .p1 = { .min = 1, .max = 8 },
408 .p2 = { .dot_limit = 112000,
409 .p2_slow = 14, .p2_fast = 14 },
410 };
411
412 /* Ironlake / Sandybridge
413 *
414 * We calculate clock using (register_value + 2) for N/M1/M2, so here
415 * the range value for them is (actual_value - 2).
416 */
417 static const struct intel_limit intel_limits_ironlake_dac = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 5 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 5, .max = 80 },
425 .p1 = { .min = 1, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 10, .p2_fast = 5 },
428 };
429
430 static const struct intel_limit intel_limits_ironlake_single_lvds = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 3 },
434 .m = { .min = 79, .max = 118 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 127 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 56 },
451 .p1 = { .min = 2, .max = 8 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 /* LVDS 100mhz refclk limits. */
457 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
458 .dot = { .min = 25000, .max = 350000 },
459 .vco = { .min = 1760000, .max = 3510000 },
460 .n = { .min = 1, .max = 2 },
461 .m = { .min = 79, .max = 126 },
462 .m1 = { .min = 12, .max = 22 },
463 .m2 = { .min = 5, .max = 9 },
464 .p = { .min = 28, .max = 112 },
465 .p1 = { .min = 2, .max = 8 },
466 .p2 = { .dot_limit = 225000,
467 .p2_slow = 14, .p2_fast = 14 },
468 };
469
470 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
471 .dot = { .min = 25000, .max = 350000 },
472 .vco = { .min = 1760000, .max = 3510000 },
473 .n = { .min = 1, .max = 3 },
474 .m = { .min = 79, .max = 126 },
475 .m1 = { .min = 12, .max = 22 },
476 .m2 = { .min = 5, .max = 9 },
477 .p = { .min = 14, .max = 42 },
478 .p1 = { .min = 2, .max = 6 },
479 .p2 = { .dot_limit = 225000,
480 .p2_slow = 7, .p2_fast = 7 },
481 };
482
483 static const struct intel_limit intel_limits_vlv = {
484 /*
485 * These are the data rate limits (measured in fast clocks)
486 * since those are the strictest limits we have. The fast
487 * clock and actual rate limits are more relaxed, so checking
488 * them would make no difference.
489 */
490 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
491 .vco = { .min = 4000000, .max = 6000000 },
492 .n = { .min = 1, .max = 7 },
493 .m1 = { .min = 2, .max = 3 },
494 .m2 = { .min = 11, .max = 156 },
495 .p1 = { .min = 2, .max = 3 },
496 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
497 };
498
499 static const struct intel_limit intel_limits_chv = {
500 /*
501 * These are the data rate limits (measured in fast clocks)
502 * since those are the strictest limits we have. The fast
503 * clock and actual rate limits are more relaxed, so checking
504 * them would make no difference.
505 */
506 .dot = { .min = 25000 * 5, .max = 540000 * 5},
507 .vco = { .min = 4800000, .max = 6480000 },
508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 .m2 = { .min = 24 << 22, .max = 175 << 22 },
511 .p1 = { .min = 2, .max = 4 },
512 .p2 = { .p2_slow = 1, .p2_fast = 14 },
513 };
514
515 static const struct intel_limit intel_limits_bxt = {
516 /* FIXME: find real dot limits */
517 .dot = { .min = 0, .max = INT_MAX },
518 .vco = { .min = 4800000, .max = 6700000 },
519 .n = { .min = 1, .max = 1 },
520 .m1 = { .min = 2, .max = 2 },
521 /* FIXME: find real m2 limits */
522 .m2 = { .min = 2 << 22, .max = 255 << 22 },
523 .p1 = { .min = 2, .max = 4 },
524 .p2 = { .p2_slow = 1, .p2_fast = 20 },
525 };
526
527 static bool
528 needs_modeset(struct drm_crtc_state *state)
529 {
530 return drm_atomic_crtc_needs_modeset(state);
531 }
532
533 /**
534 * Returns whether any output on the specified pipe is of the specified type
535 */
536 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
537 {
538 struct drm_device *dev = crtc->base.dev;
539 struct intel_encoder *encoder;
540
541 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
542 if (encoder->type == type)
543 return true;
544
545 return false;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe will have the specified
550 * type after a staged modeset is complete, i.e., the same as
551 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
552 * encoder->crtc.
553 */
554 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
555 int type)
556 {
557 struct drm_atomic_state *state = crtc_state->base.state;
558 struct drm_connector *connector;
559 struct drm_connector_state *connector_state;
560 struct intel_encoder *encoder;
561 int i, num_connectors = 0;
562
563 for_each_connector_in_state(state, connector, connector_state, i) {
564 if (connector_state->crtc != crtc_state->base.crtc)
565 continue;
566
567 num_connectors++;
568
569 encoder = to_intel_encoder(connector_state->best_encoder);
570 if (encoder->type == type)
571 return true;
572 }
573
574 WARN_ON(num_connectors == 0);
575
576 return false;
577 }
578
579 /*
580 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
581 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
582 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
583 * The helpers' return value is the rate of the clock that is fed to the
584 * display engine's pipe which can be the above fast dot clock rate or a
585 * divided-down version of it.
586 */
587 /* m1 is reserved as 0 in Pineview, n is a ring counter */
588 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
589 {
590 clock->m = clock->m2 + 2;
591 clock->p = clock->p1 * clock->p2;
592 if (WARN_ON(clock->n == 0 || clock->p == 0))
593 return 0;
594 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596
597 return clock->dot;
598 }
599
600 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
601 {
602 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
603 }
604
605 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
606 {
607 clock->m = i9xx_dpll_compute_m(clock);
608 clock->p = clock->p1 * clock->p2;
609 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
610 return 0;
611 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
612 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
613
614 return clock->dot;
615 }
616
617 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
618 {
619 clock->m = clock->m1 * clock->m2;
620 clock->p = clock->p1 * clock->p2;
621 if (WARN_ON(clock->n == 0 || clock->p == 0))
622 return 0;
623 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
624 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
625
626 return clock->dot / 5;
627 }
628
629 int chv_calc_dpll_params(int refclk, struct dpll *clock)
630 {
631 clock->m = clock->m1 * clock->m2;
632 clock->p = clock->p1 * clock->p2;
633 if (WARN_ON(clock->n == 0 || clock->p == 0))
634 return 0;
635 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
636 clock->n << 22);
637 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
638
639 return clock->dot / 5;
640 }
641
642 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
643 /**
644 * Returns whether the given set of divisors are valid for a given refclk with
645 * the given connectors.
646 */
647
648 static bool intel_PLL_is_valid(struct drm_device *dev,
649 const struct intel_limit *limit,
650 const struct dpll *clock)
651 {
652 if (clock->n < limit->n.min || limit->n.max < clock->n)
653 INTELPllInvalid("n out of range\n");
654 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
655 INTELPllInvalid("p1 out of range\n");
656 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
657 INTELPllInvalid("m2 out of range\n");
658 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
659 INTELPllInvalid("m1 out of range\n");
660
661 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
662 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
663 if (clock->m1 <= clock->m2)
664 INTELPllInvalid("m1 <= m2\n");
665
666 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
667 if (clock->p < limit->p.min || limit->p.max < clock->p)
668 INTELPllInvalid("p out of range\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 }
672
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static int
685 i9xx_select_p2_div(const struct intel_limit *limit,
686 const struct intel_crtc_state *crtc_state,
687 int target)
688 {
689 struct drm_device *dev = crtc_state->base.crtc->dev;
690
691 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
692 /*
693 * For LVDS just rely on its current settings for dual-channel.
694 * We haven't figured out how to reliably set up different
695 * single/dual channel state, if we even can.
696 */
697 if (intel_is_dual_link_lvds(dev))
698 return limit->p2.p2_fast;
699 else
700 return limit->p2.p2_slow;
701 } else {
702 if (target < limit->p2.dot_limit)
703 return limit->p2.p2_slow;
704 else
705 return limit->p2.p2_fast;
706 }
707 }
708
709 /*
710 * Returns a set of divisors for the desired target clock with the given
711 * refclk, or FALSE. The returned values represent the clock equation:
712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
713 *
714 * Target and reference clocks are specified in kHz.
715 *
716 * If match_clock is provided, then best_clock P divider must match the P
717 * divider from @match_clock used for LVDS downclocking.
718 */
719 static bool
720 i9xx_find_best_dpll(const struct intel_limit *limit,
721 struct intel_crtc_state *crtc_state,
722 int target, int refclk, struct dpll *match_clock,
723 struct dpll *best_clock)
724 {
725 struct drm_device *dev = crtc_state->base.crtc->dev;
726 struct dpll clock;
727 int err = target;
728
729 memset(best_clock, 0, sizeof(*best_clock));
730
731 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
732
733 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
734 clock.m1++) {
735 for (clock.m2 = limit->m2.min;
736 clock.m2 <= limit->m2.max; clock.m2++) {
737 if (clock.m2 >= clock.m1)
738 break;
739 for (clock.n = limit->n.min;
740 clock.n <= limit->n.max; clock.n++) {
741 for (clock.p1 = limit->p1.min;
742 clock.p1 <= limit->p1.max; clock.p1++) {
743 int this_err;
744
745 i9xx_calc_dpll_params(refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err) {
755 *best_clock = clock;
756 err = this_err;
757 }
758 }
759 }
760 }
761 }
762
763 return (err != target);
764 }
765
766 /*
767 * Returns a set of divisors for the desired target clock with the given
768 * refclk, or FALSE. The returned values represent the clock equation:
769 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
770 *
771 * Target and reference clocks are specified in kHz.
772 *
773 * If match_clock is provided, then best_clock P divider must match the P
774 * divider from @match_clock used for LVDS downclocking.
775 */
776 static bool
777 pnv_find_best_dpll(const struct intel_limit *limit,
778 struct intel_crtc_state *crtc_state,
779 int target, int refclk, struct dpll *match_clock,
780 struct dpll *best_clock)
781 {
782 struct drm_device *dev = crtc_state->base.crtc->dev;
783 struct dpll clock;
784 int err = target;
785
786 memset(best_clock, 0, sizeof(*best_clock));
787
788 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
789
790 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
791 clock.m1++) {
792 for (clock.m2 = limit->m2.min;
793 clock.m2 <= limit->m2.max; clock.m2++) {
794 for (clock.n = limit->n.min;
795 clock.n <= limit->n.max; clock.n++) {
796 for (clock.p1 = limit->p1.min;
797 clock.p1 <= limit->p1.max; clock.p1++) {
798 int this_err;
799
800 pnv_calc_dpll_params(refclk, &clock);
801 if (!intel_PLL_is_valid(dev, limit,
802 &clock))
803 continue;
804 if (match_clock &&
805 clock.p != match_clock->p)
806 continue;
807
808 this_err = abs(clock.dot - target);
809 if (this_err < err) {
810 *best_clock = clock;
811 err = this_err;
812 }
813 }
814 }
815 }
816 }
817
818 return (err != target);
819 }
820
821 /*
822 * Returns a set of divisors for the desired target clock with the given
823 * refclk, or FALSE. The returned values represent the clock equation:
824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
825 *
826 * Target and reference clocks are specified in kHz.
827 *
828 * If match_clock is provided, then best_clock P divider must match the P
829 * divider from @match_clock used for LVDS downclocking.
830 */
831 static bool
832 g4x_find_best_dpll(const struct intel_limit *limit,
833 struct intel_crtc_state *crtc_state,
834 int target, int refclk, struct dpll *match_clock,
835 struct dpll *best_clock)
836 {
837 struct drm_device *dev = crtc_state->base.crtc->dev;
838 struct dpll clock;
839 int max_n;
840 bool found = false;
841 /* approximately equals target * 0.00585 */
842 int err_most = (target >> 8) + (target >> 9);
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
847
848 max_n = limit->n.max;
849 /* based on hardware requirement, prefer smaller n to precision */
850 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
851 /* based on hardware requirement, prefere larger m1,m2 */
852 for (clock.m1 = limit->m1.max;
853 clock.m1 >= limit->m1.min; clock.m1--) {
854 for (clock.m2 = limit->m2.max;
855 clock.m2 >= limit->m2.min; clock.m2--) {
856 for (clock.p1 = limit->p1.max;
857 clock.p1 >= limit->p1.min; clock.p1--) {
858 int this_err;
859
860 i9xx_calc_dpll_params(refclk, &clock);
861 if (!intel_PLL_is_valid(dev, limit,
862 &clock))
863 continue;
864
865 this_err = abs(clock.dot - target);
866 if (this_err < err_most) {
867 *best_clock = clock;
868 err_most = this_err;
869 max_n = clock.n;
870 found = true;
871 }
872 }
873 }
874 }
875 }
876 return found;
877 }
878
879 /*
880 * Check if the calculated PLL configuration is more optimal compared to the
881 * best configuration and error found so far. Return the calculated error.
882 */
883 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
884 const struct dpll *calculated_clock,
885 const struct dpll *best_clock,
886 unsigned int best_error_ppm,
887 unsigned int *error_ppm)
888 {
889 /*
890 * For CHV ignore the error and consider only the P value.
891 * Prefer a bigger P value based on HW requirements.
892 */
893 if (IS_CHERRYVIEW(dev)) {
894 *error_ppm = 0;
895
896 return calculated_clock->p > best_clock->p;
897 }
898
899 if (WARN_ON_ONCE(!target_freq))
900 return false;
901
902 *error_ppm = div_u64(1000000ULL *
903 abs(target_freq - calculated_clock->dot),
904 target_freq);
905 /*
906 * Prefer a better P value over a better (smaller) error if the error
907 * is small. Ensure this preference for future configurations too by
908 * setting the error to 0.
909 */
910 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
911 *error_ppm = 0;
912
913 return true;
914 }
915
916 return *error_ppm + 10 < best_error_ppm;
917 }
918
919 /*
920 * Returns a set of divisors for the desired target clock with the given
921 * refclk, or FALSE. The returned values represent the clock equation:
922 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
923 */
924 static bool
925 vlv_find_best_dpll(const struct intel_limit *limit,
926 struct intel_crtc_state *crtc_state,
927 int target, int refclk, struct dpll *match_clock,
928 struct dpll *best_clock)
929 {
930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
931 struct drm_device *dev = crtc->base.dev;
932 struct dpll clock;
933 unsigned int bestppm = 1000000;
934 /* min update 19.2 MHz */
935 int max_n = min(limit->n.max, refclk / 19200);
936 bool found = false;
937
938 target *= 5; /* fast clock */
939
940 memset(best_clock, 0, sizeof(*best_clock));
941
942 /* based on hardware requirement, prefer smaller n to precision */
943 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
947 clock.p = clock.p1 * clock.p2;
948 /* based on hardware requirement, prefer bigger m1,m2 values */
949 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
950 unsigned int ppm;
951
952 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
953 refclk * clock.m1);
954
955 vlv_calc_dpll_params(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit,
958 &clock))
959 continue;
960
961 if (!vlv_PLL_is_optimal(dev, target,
962 &clock,
963 best_clock,
964 bestppm, &ppm))
965 continue;
966
967 *best_clock = clock;
968 bestppm = ppm;
969 found = true;
970 }
971 }
972 }
973 }
974
975 return found;
976 }
977
978 /*
979 * Returns a set of divisors for the desired target clock with the given
980 * refclk, or FALSE. The returned values represent the clock equation:
981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
982 */
983 static bool
984 chv_find_best_dpll(const struct intel_limit *limit,
985 struct intel_crtc_state *crtc_state,
986 int target, int refclk, struct dpll *match_clock,
987 struct dpll *best_clock)
988 {
989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
990 struct drm_device *dev = crtc->base.dev;
991 unsigned int best_error_ppm;
992 struct dpll clock;
993 uint64_t m2;
994 int found = false;
995
996 memset(best_clock, 0, sizeof(*best_clock));
997 best_error_ppm = 1000000;
998
999 /*
1000 * Based on hardware doc, the n always set to 1, and m1 always
1001 * set to 2. If requires to support 200Mhz refclk, we need to
1002 * revisit this because n may not 1 anymore.
1003 */
1004 clock.n = 1, clock.m1 = 2;
1005 target *= 5; /* fast clock */
1006
1007 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1008 for (clock.p2 = limit->p2.p2_fast;
1009 clock.p2 >= limit->p2.p2_slow;
1010 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1011 unsigned int error_ppm;
1012
1013 clock.p = clock.p1 * clock.p2;
1014
1015 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1016 clock.n) << 22, refclk * clock.m1);
1017
1018 if (m2 > INT_MAX/clock.m1)
1019 continue;
1020
1021 clock.m2 = m2;
1022
1023 chv_calc_dpll_params(refclk, &clock);
1024
1025 if (!intel_PLL_is_valid(dev, limit, &clock))
1026 continue;
1027
1028 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1029 best_error_ppm, &error_ppm))
1030 continue;
1031
1032 *best_clock = clock;
1033 best_error_ppm = error_ppm;
1034 found = true;
1035 }
1036 }
1037
1038 return found;
1039 }
1040
1041 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1042 struct dpll *best_clock)
1043 {
1044 int refclk = 100000;
1045 const struct intel_limit *limit = &intel_limits_bxt;
1046
1047 return chv_find_best_dpll(limit, crtc_state,
1048 target_clock, refclk, NULL, best_clock);
1049 }
1050
1051 bool intel_crtc_active(struct drm_crtc *crtc)
1052 {
1053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1054
1055 /* Be paranoid as we can arrive here with only partial
1056 * state retrieved from the hardware during setup.
1057 *
1058 * We can ditch the adjusted_mode.crtc_clock check as soon
1059 * as Haswell has gained clock readout/fastboot support.
1060 *
1061 * We can ditch the crtc->primary->fb check as soon as we can
1062 * properly reconstruct framebuffers.
1063 *
1064 * FIXME: The intel_crtc->active here should be switched to
1065 * crtc->state->active once we have proper CRTC states wired up
1066 * for atomic.
1067 */
1068 return intel_crtc->active && crtc->primary->state->fb &&
1069 intel_crtc->config->base.adjusted_mode.crtc_clock;
1070 }
1071
1072 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1073 enum pipe pipe)
1074 {
1075 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1077
1078 return intel_crtc->config->cpu_transcoder;
1079 }
1080
1081 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1082 {
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 i915_reg_t reg = PIPEDSL(pipe);
1085 u32 line1, line2;
1086 u32 line_mask;
1087
1088 if (IS_GEN2(dev))
1089 line_mask = DSL_LINEMASK_GEN2;
1090 else
1091 line_mask = DSL_LINEMASK_GEN3;
1092
1093 line1 = I915_READ(reg) & line_mask;
1094 msleep(5);
1095 line2 = I915_READ(reg) & line_mask;
1096
1097 return line1 == line2;
1098 }
1099
1100 /*
1101 * intel_wait_for_pipe_off - wait for pipe to turn off
1102 * @crtc: crtc whose pipe to wait for
1103 *
1104 * After disabling a pipe, we can't wait for vblank in the usual way,
1105 * spinning on the vblank interrupt status bit, since we won't actually
1106 * see an interrupt when the pipe is disabled.
1107 *
1108 * On Gen4 and above:
1109 * wait for the pipe register state bit to turn off
1110 *
1111 * Otherwise:
1112 * wait for the display line value to settle (it usually
1113 * ends up stopping at the start of the next frame).
1114 *
1115 */
1116 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1117 {
1118 struct drm_device *dev = crtc->base.dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1121 enum pipe pipe = crtc->pipe;
1122
1123 if (INTEL_INFO(dev)->gen >= 4) {
1124 i915_reg_t reg = PIPECONF(cpu_transcoder);
1125
1126 /* Wait for the Pipe State to go off */
1127 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1128 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 } else {
1131 /* Wait for the display line to settle */
1132 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1133 WARN(1, "pipe_off wait timed out\n");
1134 }
1135 }
1136
1137 /* Only for pre-ILK configs */
1138 void assert_pll(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 u32 val;
1142 bool cur_state;
1143
1144 val = I915_READ(DPLL(pipe));
1145 cur_state = !!(val & DPLL_VCO_ENABLE);
1146 I915_STATE_WARN(cur_state != state,
1147 "PLL state assertion failure (expected %s, current %s)\n",
1148 onoff(state), onoff(cur_state));
1149 }
1150
1151 /* XXX: the dsi pll is shared between MIPI DSI ports */
1152 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1153 {
1154 u32 val;
1155 bool cur_state;
1156
1157 mutex_lock(&dev_priv->sb_lock);
1158 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1159 mutex_unlock(&dev_priv->sb_lock);
1160
1161 cur_state = val & DSI_PLL_VCO_EN;
1162 I915_STATE_WARN(cur_state != state,
1163 "DSI PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1168 enum pipe pipe, bool state)
1169 {
1170 bool cur_state;
1171 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1172 pipe);
1173
1174 if (HAS_DDI(dev_priv)) {
1175 /* DDI does not have a specific FDI_TX register */
1176 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1177 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1178 } else {
1179 u32 val = I915_READ(FDI_TX_CTL(pipe));
1180 cur_state = !!(val & FDI_TX_ENABLE);
1181 }
1182 I915_STATE_WARN(cur_state != state,
1183 "FDI TX state assertion failure (expected %s, current %s)\n",
1184 onoff(state), onoff(cur_state));
1185 }
1186 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1187 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1188
1189 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191 {
1192 u32 val;
1193 bool cur_state;
1194
1195 val = I915_READ(FDI_RX_CTL(pipe));
1196 cur_state = !!(val & FDI_RX_ENABLE);
1197 I915_STATE_WARN(cur_state != state,
1198 "FDI RX state assertion failure (expected %s, current %s)\n",
1199 onoff(state), onoff(cur_state));
1200 }
1201 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1202 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1203
1204 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe)
1206 {
1207 u32 val;
1208
1209 /* ILK FDI PLL is always enabled */
1210 if (IS_GEN5(dev_priv))
1211 return;
1212
1213 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1214 if (HAS_DDI(dev_priv))
1215 return;
1216
1217 val = I915_READ(FDI_TX_CTL(pipe));
1218 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1219 }
1220
1221 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
1223 {
1224 u32 val;
1225 bool cur_state;
1226
1227 val = I915_READ(FDI_RX_CTL(pipe));
1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1229 I915_STATE_WARN(cur_state != state,
1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 onoff(state), onoff(cur_state));
1232 }
1233
1234 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
1236 {
1237 struct drm_device *dev = dev_priv->dev;
1238 i915_reg_t pp_reg;
1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
1241 bool locked = true;
1242
1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
1249 pp_reg = PCH_PP_CONTROL;
1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
1260 } else {
1261 pp_reg = PP_CONTROL;
1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1269 locked = false;
1270
1271 I915_STATE_WARN(panel_pipe == pipe && locked,
1272 "panel assertion failure, pipe %c regs locked\n",
1273 pipe_name(pipe));
1274 }
1275
1276 static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
1282 if (IS_845G(dev) || IS_I865G(dev))
1283 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1284 else
1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1286
1287 I915_STATE_WARN(cur_state != state,
1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), onoff(state), onoff(cur_state));
1290 }
1291 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
1294 void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
1296 {
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300 enum intel_display_power_domain power_domain;
1301
1302 /* if we need the pipe quirk it must be always on */
1303 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1304 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1305 state = true;
1306
1307 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1308 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1309 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1310 cur_state = !!(val & PIPECONF_ENABLE);
1311
1312 intel_display_power_put(dev_priv, power_domain);
1313 } else {
1314 cur_state = false;
1315 }
1316
1317 I915_STATE_WARN(cur_state != state,
1318 "pipe %c assertion failure (expected %s, current %s)\n",
1319 pipe_name(pipe), onoff(state), onoff(cur_state));
1320 }
1321
1322 static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
1324 {
1325 u32 val;
1326 bool cur_state;
1327
1328 val = I915_READ(DSPCNTR(plane));
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), onoff(state), onoff(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int i;
1343
1344 /* Primary planes are fixed to pipes on gen4+ */
1345 if (INTEL_INFO(dev)->gen >= 4) {
1346 u32 val = I915_READ(DSPCNTR(pipe));
1347 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1348 "plane %c assertion failure, should be disabled but not\n",
1349 plane_name(pipe));
1350 return;
1351 }
1352
1353 /* Need to check both planes against the pipe */
1354 for_each_pipe(dev_priv, i) {
1355 u32 val = I915_READ(DSPCNTR(i));
1356 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1357 DISPPLANE_SEL_PIPE_SHIFT;
1358 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1359 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1360 plane_name(i), pipe_name(pipe));
1361 }
1362 }
1363
1364 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 struct drm_device *dev = dev_priv->dev;
1368 int sprite;
1369
1370 if (INTEL_INFO(dev)->gen >= 9) {
1371 for_each_sprite(dev_priv, pipe, sprite) {
1372 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1373 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1374 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1375 sprite, pipe_name(pipe));
1376 }
1377 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1378 for_each_sprite(dev_priv, pipe, sprite) {
1379 u32 val = I915_READ(SPCNTR(pipe, sprite));
1380 I915_STATE_WARN(val & SP_ENABLE,
1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1382 sprite_name(pipe, sprite), pipe_name(pipe));
1383 }
1384 } else if (INTEL_INFO(dev)->gen >= 7) {
1385 u32 val = I915_READ(SPRCTL(pipe));
1386 I915_STATE_WARN(val & SPRITE_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 plane_name(pipe), pipe_name(pipe));
1389 } else if (INTEL_INFO(dev)->gen >= 5) {
1390 u32 val = I915_READ(DVSCNTR(pipe));
1391 I915_STATE_WARN(val & DVS_ENABLE,
1392 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(pipe), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_vblank_disabled(struct drm_crtc *crtc)
1398 {
1399 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1400 drm_crtc_vblank_put(crtc);
1401 }
1402
1403 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 u32 val;
1407 bool enabled;
1408
1409 val = I915_READ(PCH_TRANSCONF(pipe));
1410 enabled = !!(val & TRANS_ENABLE);
1411 I915_STATE_WARN(enabled,
1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 pipe_name(pipe));
1414 }
1415
1416 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 port_sel, u32 val)
1418 {
1419 if ((val & DP_PORT_EN) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv)) {
1423 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1424 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1425 return false;
1426 } else if (IS_CHERRYVIEW(dev_priv)) {
1427 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1428 return false;
1429 } else {
1430 if ((val & DP_PIPE_MASK) != (pipe << 30))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, u32 val)
1438 {
1439 if ((val & SDVO_ENABLE) == 0)
1440 return false;
1441
1442 if (HAS_PCH_CPT(dev_priv)) {
1443 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1444 return false;
1445 } else if (IS_CHERRYVIEW(dev_priv)) {
1446 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1447 return false;
1448 } else {
1449 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1450 return false;
1451 }
1452 return true;
1453 }
1454
1455 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe, u32 val)
1457 {
1458 if ((val & LVDS_PORT_EN) == 0)
1459 return false;
1460
1461 if (HAS_PCH_CPT(dev_priv)) {
1462 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1463 return false;
1464 } else {
1465 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1466 return false;
1467 }
1468 return true;
1469 }
1470
1471 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1472 enum pipe pipe, u32 val)
1473 {
1474 if ((val & ADPA_DAC_ENABLE) == 0)
1475 return false;
1476 if (HAS_PCH_CPT(dev_priv)) {
1477 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1478 return false;
1479 } else {
1480 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1481 return false;
1482 }
1483 return true;
1484 }
1485
1486 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, i915_reg_t reg,
1488 u32 port_sel)
1489 {
1490 u32 val = I915_READ(reg);
1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1493 i915_mmio_reg_offset(reg), pipe_name(pipe));
1494
1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1496 && (val & DP_PIPEB_SELECT),
1497 "IBX PCH dp port still using transcoder B\n");
1498 }
1499
1500 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, i915_reg_t reg)
1502 {
1503 u32 val = I915_READ(reg);
1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1506 i915_mmio_reg_offset(reg), pipe_name(pipe));
1507
1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1509 && (val & SDVO_PIPE_B_SELECT),
1510 "IBX PCH hdmi port still using transcoder B\n");
1511 }
1512
1513 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
1515 {
1516 u32 val;
1517
1518 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1521
1522 val = I915_READ(PCH_ADPA);
1523 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1524 "PCH VGA enabled on transcoder %c, should be disabled\n",
1525 pipe_name(pipe));
1526
1527 val = I915_READ(PCH_LVDS);
1528 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1529 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1530 pipe_name(pipe));
1531
1532 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1533 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1534 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1535 }
1536
1537 static void _vlv_enable_pll(struct intel_crtc *crtc,
1538 const struct intel_crtc_state *pipe_config)
1539 {
1540 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1541 enum pipe pipe = crtc->pipe;
1542
1543 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1544 POSTING_READ(DPLL(pipe));
1545 udelay(150);
1546
1547 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1548 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1549 }
1550
1551 static void vlv_enable_pll(struct intel_crtc *crtc,
1552 const struct intel_crtc_state *pipe_config)
1553 {
1554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1555 enum pipe pipe = crtc->pipe;
1556
1557 assert_pipe_disabled(dev_priv, pipe);
1558
1559 /* PLL is protected by panel, make sure we can write it */
1560 assert_panel_unlocked(dev_priv, pipe);
1561
1562 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1563 _vlv_enable_pll(crtc, pipe_config);
1564
1565 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1566 POSTING_READ(DPLL_MD(pipe));
1567 }
1568
1569
1570 static void _chv_enable_pll(struct intel_crtc *crtc,
1571 const struct intel_crtc_state *pipe_config)
1572 {
1573 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574 enum pipe pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 mutex_lock(&dev_priv->sb_lock);
1579
1580 /* Enable back the 10bit clock to display controller */
1581 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1582 tmp |= DPIO_DCLKP_EN;
1583 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1584
1585 mutex_unlock(&dev_priv->sb_lock);
1586
1587 /*
1588 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1589 */
1590 udelay(1);
1591
1592 /* Enable PLL */
1593 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1594
1595 /* Check PLL is locked */
1596 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1597 DRM_ERROR("PLL %d failed to lock\n", pipe);
1598 }
1599
1600 static void chv_enable_pll(struct intel_crtc *crtc,
1601 const struct intel_crtc_state *pipe_config)
1602 {
1603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604 enum pipe pipe = crtc->pipe;
1605
1606 assert_pipe_disabled(dev_priv, pipe);
1607
1608 /* PLL is protected by panel, make sure we can write it */
1609 assert_panel_unlocked(dev_priv, pipe);
1610
1611 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1612 _chv_enable_pll(crtc, pipe_config);
1613
1614 if (pipe != PIPE_A) {
1615 /*
1616 * WaPixelRepeatModeFixForC0:chv
1617 *
1618 * DPLLCMD is AWOL. Use chicken bits to propagate
1619 * the value from DPLLBMD to either pipe B or C.
1620 */
1621 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1622 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1623 I915_WRITE(CBR4_VLV, 0);
1624 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1625
1626 /*
1627 * DPLLB VGA mode also seems to cause problems.
1628 * We should always have it disabled.
1629 */
1630 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1631 } else {
1632 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(pipe));
1634 }
1635 }
1636
1637 static int intel_num_dvo_pipes(struct drm_device *dev)
1638 {
1639 struct intel_crtc *crtc;
1640 int count = 0;
1641
1642 for_each_intel_crtc(dev, crtc)
1643 count += crtc->base.state->active &&
1644 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1645
1646 return count;
1647 }
1648
1649 static void i9xx_enable_pll(struct intel_crtc *crtc)
1650 {
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 i915_reg_t reg = DPLL(crtc->pipe);
1654 u32 dpll = crtc->config->dpll_hw_state.dpll;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 /* PLL is protected by panel, make sure we can write it */
1659 if (IS_MOBILE(dev) && !IS_I830(dev))
1660 assert_panel_unlocked(dev_priv, crtc->pipe);
1661
1662 /* Enable DVO 2x clock on both PLLs if necessary */
1663 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1664 /*
1665 * It appears to be important that we don't enable this
1666 * for the current pipe before otherwise configuring the
1667 * PLL. No idea how this should be handled if multiple
1668 * DVO outputs are enabled simultaneosly.
1669 */
1670 dpll |= DPLL_DVO_2X_MODE;
1671 I915_WRITE(DPLL(!crtc->pipe),
1672 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1673 }
1674
1675 /*
1676 * Apparently we need to have VGA mode enabled prior to changing
1677 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1678 * dividers, even though the register value does change.
1679 */
1680 I915_WRITE(reg, 0);
1681
1682 I915_WRITE(reg, dpll);
1683
1684 /* Wait for the clocks to stabilize. */
1685 POSTING_READ(reg);
1686 udelay(150);
1687
1688 if (INTEL_INFO(dev)->gen >= 4) {
1689 I915_WRITE(DPLL_MD(crtc->pipe),
1690 crtc->config->dpll_hw_state.dpll_md);
1691 } else {
1692 /* The pixel multiplier can only be updated once the
1693 * DPLL is enabled and the clocks are stable.
1694 *
1695 * So write it again.
1696 */
1697 I915_WRITE(reg, dpll);
1698 }
1699
1700 /* We do this three times for luck */
1701 I915_WRITE(reg, dpll);
1702 POSTING_READ(reg);
1703 udelay(150); /* wait for warmup */
1704 I915_WRITE(reg, dpll);
1705 POSTING_READ(reg);
1706 udelay(150); /* wait for warmup */
1707 I915_WRITE(reg, dpll);
1708 POSTING_READ(reg);
1709 udelay(150); /* wait for warmup */
1710 }
1711
1712 /**
1713 * i9xx_disable_pll - disable a PLL
1714 * @dev_priv: i915 private structure
1715 * @pipe: pipe PLL to disable
1716 *
1717 * Disable the PLL for @pipe, making sure the pipe is off first.
1718 *
1719 * Note! This is for pre-ILK only.
1720 */
1721 static void i9xx_disable_pll(struct intel_crtc *crtc)
1722 {
1723 struct drm_device *dev = crtc->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 enum pipe pipe = crtc->pipe;
1726
1727 /* Disable DVO 2x clock on both PLLs if necessary */
1728 if (IS_I830(dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1730 !intel_num_dvo_pipes(dev)) {
1731 I915_WRITE(DPLL(PIPE_B),
1732 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1733 I915_WRITE(DPLL(PIPE_A),
1734 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1735 }
1736
1737 /* Don't disable pipe or pipe PLLs if needed */
1738 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1739 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1740 return;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
1745 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1746 POSTING_READ(DPLL(pipe));
1747 }
1748
1749 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1750 {
1751 u32 val;
1752
1753 /* Make sure the pipe isn't still relying on us */
1754 assert_pipe_disabled(dev_priv, pipe);
1755
1756 val = DPLL_INTEGRATED_REF_CLK_VLV |
1757 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1758 if (pipe != PIPE_A)
1759 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1760
1761 I915_WRITE(DPLL(pipe), val);
1762 POSTING_READ(DPLL(pipe));
1763 }
1764
1765 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1766 {
1767 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1768 u32 val;
1769
1770 /* Make sure the pipe isn't still relying on us */
1771 assert_pipe_disabled(dev_priv, pipe);
1772
1773 val = DPLL_SSC_REF_CLK_CHV |
1774 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1775 if (pipe != PIPE_A)
1776 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1777
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1780
1781 mutex_lock(&dev_priv->sb_lock);
1782
1783 /* Disable 10bit clock to display controller */
1784 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1785 val &= ~DPIO_DCLKP_EN;
1786 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1787
1788 mutex_unlock(&dev_priv->sb_lock);
1789 }
1790
1791 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1792 struct intel_digital_port *dport,
1793 unsigned int expected_mask)
1794 {
1795 u32 port_mask;
1796 i915_reg_t dpll_reg;
1797
1798 switch (dport->port) {
1799 case PORT_B:
1800 port_mask = DPLL_PORTB_READY_MASK;
1801 dpll_reg = DPLL(0);
1802 break;
1803 case PORT_C:
1804 port_mask = DPLL_PORTC_READY_MASK;
1805 dpll_reg = DPLL(0);
1806 expected_mask <<= 4;
1807 break;
1808 case PORT_D:
1809 port_mask = DPLL_PORTD_READY_MASK;
1810 dpll_reg = DPIO_PHY_STATUS;
1811 break;
1812 default:
1813 BUG();
1814 }
1815
1816 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1817 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1818 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1819 }
1820
1821 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1822 enum pipe pipe)
1823 {
1824 struct drm_device *dev = dev_priv->dev;
1825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1827 i915_reg_t reg;
1828 uint32_t val, pipeconf_val;
1829
1830 /* Make sure PCH DPLL is enabled */
1831 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1832
1833 /* FDI must be feeding us bits for PCH ports */
1834 assert_fdi_tx_enabled(dev_priv, pipe);
1835 assert_fdi_rx_enabled(dev_priv, pipe);
1836
1837 if (HAS_PCH_CPT(dev)) {
1838 /* Workaround: Set the timing override bit before enabling the
1839 * pch transcoder. */
1840 reg = TRANS_CHICKEN2(pipe);
1841 val = I915_READ(reg);
1842 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1843 I915_WRITE(reg, val);
1844 }
1845
1846 reg = PCH_TRANSCONF(pipe);
1847 val = I915_READ(reg);
1848 pipeconf_val = I915_READ(PIPECONF(pipe));
1849
1850 if (HAS_PCH_IBX(dev_priv)) {
1851 /*
1852 * Make the BPC in transcoder be consistent with
1853 * that in pipeconf reg. For HDMI we must use 8bpc
1854 * here for both 8bpc and 12bpc.
1855 */
1856 val &= ~PIPECONF_BPC_MASK;
1857 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1858 val |= PIPECONF_8BPC;
1859 else
1860 val |= pipeconf_val & PIPECONF_BPC_MASK;
1861 }
1862
1863 val &= ~TRANS_INTERLACE_MASK;
1864 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1865 if (HAS_PCH_IBX(dev_priv) &&
1866 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1867 val |= TRANS_LEGACY_INTERLACED_ILK;
1868 else
1869 val |= TRANS_INTERLACED;
1870 else
1871 val |= TRANS_PROGRESSIVE;
1872
1873 I915_WRITE(reg, val | TRANS_ENABLE);
1874 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1875 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1876 }
1877
1878 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1879 enum transcoder cpu_transcoder)
1880 {
1881 u32 val, pipeconf_val;
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1885 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1886
1887 /* Workaround: set timing override bit. */
1888 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1891
1892 val = TRANS_ENABLE;
1893 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1894
1895 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1896 PIPECONF_INTERLACED_ILK)
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(LPT_TRANSCONF, val);
1902 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("Failed to enable PCH transcoder\n");
1904 }
1905
1906 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum pipe pipe)
1908 {
1909 struct drm_device *dev = dev_priv->dev;
1910 i915_reg_t reg;
1911 uint32_t val;
1912
1913 /* FDI relies on the transcoder */
1914 assert_fdi_tx_disabled(dev_priv, pipe);
1915 assert_fdi_rx_disabled(dev_priv, pipe);
1916
1917 /* Ports must be off as well */
1918 assert_pch_ports_disabled(dev_priv, pipe);
1919
1920 reg = PCH_TRANSCONF(pipe);
1921 val = I915_READ(reg);
1922 val &= ~TRANS_ENABLE;
1923 I915_WRITE(reg, val);
1924 /* wait for PCH transcoder off, transcoder state */
1925 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1926 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1927
1928 if (HAS_PCH_CPT(dev)) {
1929 /* Workaround: Clear the timing override chicken bit again. */
1930 reg = TRANS_CHICKEN2(pipe);
1931 val = I915_READ(reg);
1932 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1933 I915_WRITE(reg, val);
1934 }
1935 }
1936
1937 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1938 {
1939 u32 val;
1940
1941 val = I915_READ(LPT_TRANSCONF);
1942 val &= ~TRANS_ENABLE;
1943 I915_WRITE(LPT_TRANSCONF, val);
1944 /* wait for PCH transcoder off, transcoder state */
1945 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1946 DRM_ERROR("Failed to disable PCH transcoder\n");
1947
1948 /* Workaround: clear timing override bit. */
1949 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1950 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1951 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1952 }
1953
1954 /**
1955 * intel_enable_pipe - enable a pipe, asserting requirements
1956 * @crtc: crtc responsible for the pipe
1957 *
1958 * Enable @crtc's pipe, making sure that various hardware specific requirements
1959 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1960 */
1961 static void intel_enable_pipe(struct intel_crtc *crtc)
1962 {
1963 struct drm_device *dev = crtc->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 enum pipe pipe = crtc->pipe;
1966 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1967 enum pipe pch_transcoder;
1968 i915_reg_t reg;
1969 u32 val;
1970
1971 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1972
1973 assert_planes_disabled(dev_priv, pipe);
1974 assert_cursor_disabled(dev_priv, pipe);
1975 assert_sprites_disabled(dev_priv, pipe);
1976
1977 if (HAS_PCH_LPT(dev_priv))
1978 pch_transcoder = TRANSCODER_A;
1979 else
1980 pch_transcoder = pipe;
1981
1982 /*
1983 * A pipe without a PLL won't actually be able to drive bits from
1984 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1985 * need the check.
1986 */
1987 if (HAS_GMCH_DISPLAY(dev_priv))
1988 if (crtc->config->has_dsi_encoder)
1989 assert_dsi_pll_enabled(dev_priv);
1990 else
1991 assert_pll_enabled(dev_priv, pipe);
1992 else {
1993 if (crtc->config->has_pch_encoder) {
1994 /* if driving the PCH, we need FDI enabled */
1995 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1996 assert_fdi_tx_pll_enabled(dev_priv,
1997 (enum pipe) cpu_transcoder);
1998 }
1999 /* FIXME: assert CPU port conditions for SNB+ */
2000 }
2001
2002 reg = PIPECONF(cpu_transcoder);
2003 val = I915_READ(reg);
2004 if (val & PIPECONF_ENABLE) {
2005 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2006 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2007 return;
2008 }
2009
2010 I915_WRITE(reg, val | PIPECONF_ENABLE);
2011 POSTING_READ(reg);
2012
2013 /*
2014 * Until the pipe starts DSL will read as 0, which would cause
2015 * an apparent vblank timestamp jump, which messes up also the
2016 * frame count when it's derived from the timestamps. So let's
2017 * wait for the pipe to start properly before we call
2018 * drm_crtc_vblank_on()
2019 */
2020 if (dev->max_vblank_count == 0 &&
2021 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2022 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2023 }
2024
2025 /**
2026 * intel_disable_pipe - disable a pipe, asserting requirements
2027 * @crtc: crtc whose pipes is to be disabled
2028 *
2029 * Disable the pipe of @crtc, making sure that various hardware
2030 * specific requirements are met, if applicable, e.g. plane
2031 * disabled, panel fitter off, etc.
2032 *
2033 * Will wait until the pipe has shut down before returning.
2034 */
2035 static void intel_disable_pipe(struct intel_crtc *crtc)
2036 {
2037 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2038 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2039 enum pipe pipe = crtc->pipe;
2040 i915_reg_t reg;
2041 u32 val;
2042
2043 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2044
2045 /*
2046 * Make sure planes won't keep trying to pump pixels to us,
2047 * or we might hang the display.
2048 */
2049 assert_planes_disabled(dev_priv, pipe);
2050 assert_cursor_disabled(dev_priv, pipe);
2051 assert_sprites_disabled(dev_priv, pipe);
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if ((val & PIPECONF_ENABLE) == 0)
2056 return;
2057
2058 /*
2059 * Double wide has implications for planes
2060 * so best keep it disabled when not needed.
2061 */
2062 if (crtc->config->double_wide)
2063 val &= ~PIPECONF_DOUBLE_WIDE;
2064
2065 /* Don't disable pipe or pipe PLLs if needed */
2066 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2067 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2068 val &= ~PIPECONF_ENABLE;
2069
2070 I915_WRITE(reg, val);
2071 if ((val & PIPECONF_ENABLE) == 0)
2072 intel_wait_for_pipe_off(crtc);
2073 }
2074
2075 static bool need_vtd_wa(struct drm_device *dev)
2076 {
2077 #ifdef CONFIG_INTEL_IOMMU
2078 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2079 return true;
2080 #endif
2081 return false;
2082 }
2083
2084 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2085 {
2086 return IS_GEN2(dev_priv) ? 2048 : 4096;
2087 }
2088
2089 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2090 uint64_t fb_modifier, unsigned int cpp)
2091 {
2092 switch (fb_modifier) {
2093 case DRM_FORMAT_MOD_NONE:
2094 return cpp;
2095 case I915_FORMAT_MOD_X_TILED:
2096 if (IS_GEN2(dev_priv))
2097 return 128;
2098 else
2099 return 512;
2100 case I915_FORMAT_MOD_Y_TILED:
2101 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2102 return 128;
2103 else
2104 return 512;
2105 case I915_FORMAT_MOD_Yf_TILED:
2106 switch (cpp) {
2107 case 1:
2108 return 64;
2109 case 2:
2110 case 4:
2111 return 128;
2112 case 8:
2113 case 16:
2114 return 256;
2115 default:
2116 MISSING_CASE(cpp);
2117 return cpp;
2118 }
2119 break;
2120 default:
2121 MISSING_CASE(fb_modifier);
2122 return cpp;
2123 }
2124 }
2125
2126 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2127 uint64_t fb_modifier, unsigned int cpp)
2128 {
2129 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2130 return 1;
2131 else
2132 return intel_tile_size(dev_priv) /
2133 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2134 }
2135
2136 /* Return the tile dimensions in pixel units */
2137 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2138 unsigned int *tile_width,
2139 unsigned int *tile_height,
2140 uint64_t fb_modifier,
2141 unsigned int cpp)
2142 {
2143 unsigned int tile_width_bytes =
2144 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2145
2146 *tile_width = tile_width_bytes / cpp;
2147 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2148 }
2149
2150 unsigned int
2151 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2152 uint32_t pixel_format, uint64_t fb_modifier)
2153 {
2154 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2155 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2156
2157 return ALIGN(height, tile_height);
2158 }
2159
2160 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2161 {
2162 unsigned int size = 0;
2163 int i;
2164
2165 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2166 size += rot_info->plane[i].width * rot_info->plane[i].height;
2167
2168 return size;
2169 }
2170
2171 static void
2172 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2173 const struct drm_framebuffer *fb,
2174 unsigned int rotation)
2175 {
2176 if (intel_rotation_90_or_270(rotation)) {
2177 *view = i915_ggtt_view_rotated;
2178 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2179 } else {
2180 *view = i915_ggtt_view_normal;
2181 }
2182 }
2183
2184 static void
2185 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2186 struct drm_framebuffer *fb)
2187 {
2188 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2189 unsigned int tile_size, tile_width, tile_height, cpp;
2190
2191 tile_size = intel_tile_size(dev_priv);
2192
2193 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2194 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2195 fb->modifier[0], cpp);
2196
2197 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2198 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2199
2200 if (info->pixel_format == DRM_FORMAT_NV12) {
2201 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2202 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2203 fb->modifier[1], cpp);
2204
2205 info->uv_offset = fb->offsets[1];
2206 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2207 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2208 }
2209 }
2210
2211 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2212 {
2213 if (INTEL_INFO(dev_priv)->gen >= 9)
2214 return 256 * 1024;
2215 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2216 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2217 return 128 * 1024;
2218 else if (INTEL_INFO(dev_priv)->gen >= 4)
2219 return 4 * 1024;
2220 else
2221 return 0;
2222 }
2223
2224 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2225 uint64_t fb_modifier)
2226 {
2227 switch (fb_modifier) {
2228 case DRM_FORMAT_MOD_NONE:
2229 return intel_linear_alignment(dev_priv);
2230 case I915_FORMAT_MOD_X_TILED:
2231 if (INTEL_INFO(dev_priv)->gen >= 9)
2232 return 256 * 1024;
2233 return 0;
2234 case I915_FORMAT_MOD_Y_TILED:
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 return 1 * 1024 * 1024;
2237 default:
2238 MISSING_CASE(fb_modifier);
2239 return 0;
2240 }
2241 }
2242
2243 int
2244 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2245 unsigned int rotation)
2246 {
2247 struct drm_device *dev = fb->dev;
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2250 struct i915_ggtt_view view;
2251 u32 alignment;
2252 int ret;
2253
2254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2255
2256 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2257
2258 intel_fill_fb_ggtt_view(&view, fb, rotation);
2259
2260 /* Note that the w/a also requires 64 PTE of padding following the
2261 * bo. We currently fill all unused PTE with the shadow page and so
2262 * we should always have valid PTE following the scanout preventing
2263 * the VT-d warning.
2264 */
2265 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2266 alignment = 256 * 1024;
2267
2268 /*
2269 * Global gtt pte registers are special registers which actually forward
2270 * writes to a chunk of system memory. Which means that there is no risk
2271 * that the register values disappear as soon as we call
2272 * intel_runtime_pm_put(), so it is correct to wrap only the
2273 * pin/unpin/fence and not more.
2274 */
2275 intel_runtime_pm_get(dev_priv);
2276
2277 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2278 &view);
2279 if (ret)
2280 goto err_pm;
2281
2282 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2283 * fence, whereas 965+ only requires a fence if using
2284 * framebuffer compression. For simplicity, we always install
2285 * a fence as the cost is not that onerous.
2286 */
2287 if (view.type == I915_GGTT_VIEW_NORMAL) {
2288 ret = i915_gem_object_get_fence(obj);
2289 if (ret == -EDEADLK) {
2290 /*
2291 * -EDEADLK means there are no free fences
2292 * no pending flips.
2293 *
2294 * This is propagated to atomic, but it uses
2295 * -EDEADLK to force a locking recovery, so
2296 * change the returned error to -EBUSY.
2297 */
2298 ret = -EBUSY;
2299 goto err_unpin;
2300 } else if (ret)
2301 goto err_unpin;
2302
2303 i915_gem_object_pin_fence(obj);
2304 }
2305
2306 intel_runtime_pm_put(dev_priv);
2307 return 0;
2308
2309 err_unpin:
2310 i915_gem_object_unpin_from_display_plane(obj, &view);
2311 err_pm:
2312 intel_runtime_pm_put(dev_priv);
2313 return ret;
2314 }
2315
2316 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2317 {
2318 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2319 struct i915_ggtt_view view;
2320
2321 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2322
2323 intel_fill_fb_ggtt_view(&view, fb, rotation);
2324
2325 if (view.type == I915_GGTT_VIEW_NORMAL)
2326 i915_gem_object_unpin_fence(obj);
2327
2328 i915_gem_object_unpin_from_display_plane(obj, &view);
2329 }
2330
2331 /*
2332 * Adjust the tile offset by moving the difference into
2333 * the x/y offsets.
2334 *
2335 * Input tile dimensions and pitch must already be
2336 * rotated to match x and y, and in pixel units.
2337 */
2338 static u32 intel_adjust_tile_offset(int *x, int *y,
2339 unsigned int tile_width,
2340 unsigned int tile_height,
2341 unsigned int tile_size,
2342 unsigned int pitch_tiles,
2343 u32 old_offset,
2344 u32 new_offset)
2345 {
2346 unsigned int tiles;
2347
2348 WARN_ON(old_offset & (tile_size - 1));
2349 WARN_ON(new_offset & (tile_size - 1));
2350 WARN_ON(new_offset > old_offset);
2351
2352 tiles = (old_offset - new_offset) / tile_size;
2353
2354 *y += tiles / pitch_tiles * tile_height;
2355 *x += tiles % pitch_tiles * tile_width;
2356
2357 return new_offset;
2358 }
2359
2360 /*
2361 * Computes the linear offset to the base tile and adjusts
2362 * x, y. bytes per pixel is assumed to be a power-of-two.
2363 *
2364 * In the 90/270 rotated case, x and y are assumed
2365 * to be already rotated to match the rotated GTT view, and
2366 * pitch is the tile_height aligned framebuffer height.
2367 */
2368 u32 intel_compute_tile_offset(int *x, int *y,
2369 const struct drm_framebuffer *fb, int plane,
2370 unsigned int pitch,
2371 unsigned int rotation)
2372 {
2373 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2374 uint64_t fb_modifier = fb->modifier[plane];
2375 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2376 u32 offset, offset_aligned, alignment;
2377
2378 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2379 if (alignment)
2380 alignment--;
2381
2382 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2383 unsigned int tile_size, tile_width, tile_height;
2384 unsigned int tile_rows, tiles, pitch_tiles;
2385
2386 tile_size = intel_tile_size(dev_priv);
2387 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2388 fb_modifier, cpp);
2389
2390 if (intel_rotation_90_or_270(rotation)) {
2391 pitch_tiles = pitch / tile_height;
2392 swap(tile_width, tile_height);
2393 } else {
2394 pitch_tiles = pitch / (tile_width * cpp);
2395 }
2396
2397 tile_rows = *y / tile_height;
2398 *y %= tile_height;
2399
2400 tiles = *x / tile_width;
2401 *x %= tile_width;
2402
2403 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2404 offset_aligned = offset & ~alignment;
2405
2406 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2407 tile_size, pitch_tiles,
2408 offset, offset_aligned);
2409 } else {
2410 offset = *y * pitch + *x * cpp;
2411 offset_aligned = offset & ~alignment;
2412
2413 *y = (offset & alignment) / pitch;
2414 *x = ((offset & alignment) - *y * pitch) / cpp;
2415 }
2416
2417 return offset_aligned;
2418 }
2419
2420 static int i9xx_format_to_fourcc(int format)
2421 {
2422 switch (format) {
2423 case DISPPLANE_8BPP:
2424 return DRM_FORMAT_C8;
2425 case DISPPLANE_BGRX555:
2426 return DRM_FORMAT_XRGB1555;
2427 case DISPPLANE_BGRX565:
2428 return DRM_FORMAT_RGB565;
2429 default:
2430 case DISPPLANE_BGRX888:
2431 return DRM_FORMAT_XRGB8888;
2432 case DISPPLANE_RGBX888:
2433 return DRM_FORMAT_XBGR8888;
2434 case DISPPLANE_BGRX101010:
2435 return DRM_FORMAT_XRGB2101010;
2436 case DISPPLANE_RGBX101010:
2437 return DRM_FORMAT_XBGR2101010;
2438 }
2439 }
2440
2441 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2442 {
2443 switch (format) {
2444 case PLANE_CTL_FORMAT_RGB_565:
2445 return DRM_FORMAT_RGB565;
2446 default:
2447 case PLANE_CTL_FORMAT_XRGB_8888:
2448 if (rgb_order) {
2449 if (alpha)
2450 return DRM_FORMAT_ABGR8888;
2451 else
2452 return DRM_FORMAT_XBGR8888;
2453 } else {
2454 if (alpha)
2455 return DRM_FORMAT_ARGB8888;
2456 else
2457 return DRM_FORMAT_XRGB8888;
2458 }
2459 case PLANE_CTL_FORMAT_XRGB_2101010:
2460 if (rgb_order)
2461 return DRM_FORMAT_XBGR2101010;
2462 else
2463 return DRM_FORMAT_XRGB2101010;
2464 }
2465 }
2466
2467 static bool
2468 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2469 struct intel_initial_plane_config *plane_config)
2470 {
2471 struct drm_device *dev = crtc->base.dev;
2472 struct drm_i915_private *dev_priv = to_i915(dev);
2473 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2474 struct drm_i915_gem_object *obj = NULL;
2475 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2476 struct drm_framebuffer *fb = &plane_config->fb->base;
2477 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2478 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2479 PAGE_SIZE);
2480
2481 size_aligned -= base_aligned;
2482
2483 if (plane_config->size == 0)
2484 return false;
2485
2486 /* If the FB is too big, just don't use it since fbdev is not very
2487 * important and we should probably use that space with FBC or other
2488 * features. */
2489 if (size_aligned * 2 > ggtt->stolen_usable_size)
2490 return false;
2491
2492 mutex_lock(&dev->struct_mutex);
2493
2494 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2495 base_aligned,
2496 base_aligned,
2497 size_aligned);
2498 if (!obj) {
2499 mutex_unlock(&dev->struct_mutex);
2500 return false;
2501 }
2502
2503 obj->tiling_mode = plane_config->tiling;
2504 if (obj->tiling_mode == I915_TILING_X)
2505 obj->stride = fb->pitches[0];
2506
2507 mode_cmd.pixel_format = fb->pixel_format;
2508 mode_cmd.width = fb->width;
2509 mode_cmd.height = fb->height;
2510 mode_cmd.pitches[0] = fb->pitches[0];
2511 mode_cmd.modifier[0] = fb->modifier[0];
2512 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2513
2514 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2515 &mode_cmd, obj)) {
2516 DRM_DEBUG_KMS("intel fb init failed\n");
2517 goto out_unref_obj;
2518 }
2519
2520 mutex_unlock(&dev->struct_mutex);
2521
2522 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2523 return true;
2524
2525 out_unref_obj:
2526 drm_gem_object_unreference(&obj->base);
2527 mutex_unlock(&dev->struct_mutex);
2528 return false;
2529 }
2530
2531 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2532 static void
2533 update_state_fb(struct drm_plane *plane)
2534 {
2535 if (plane->fb == plane->state->fb)
2536 return;
2537
2538 if (plane->state->fb)
2539 drm_framebuffer_unreference(plane->state->fb);
2540 plane->state->fb = plane->fb;
2541 if (plane->state->fb)
2542 drm_framebuffer_reference(plane->state->fb);
2543 }
2544
2545 static void
2546 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2547 struct intel_initial_plane_config *plane_config)
2548 {
2549 struct drm_device *dev = intel_crtc->base.dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct drm_crtc *c;
2552 struct intel_crtc *i;
2553 struct drm_i915_gem_object *obj;
2554 struct drm_plane *primary = intel_crtc->base.primary;
2555 struct drm_plane_state *plane_state = primary->state;
2556 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2557 struct intel_plane *intel_plane = to_intel_plane(primary);
2558 struct intel_plane_state *intel_state =
2559 to_intel_plane_state(plane_state);
2560 struct drm_framebuffer *fb;
2561
2562 if (!plane_config->fb)
2563 return;
2564
2565 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2566 fb = &plane_config->fb->base;
2567 goto valid_fb;
2568 }
2569
2570 kfree(plane_config->fb);
2571
2572 /*
2573 * Failed to alloc the obj, check to see if we should share
2574 * an fb with another CRTC instead
2575 */
2576 for_each_crtc(dev, c) {
2577 i = to_intel_crtc(c);
2578
2579 if (c == &intel_crtc->base)
2580 continue;
2581
2582 if (!i->active)
2583 continue;
2584
2585 fb = c->primary->fb;
2586 if (!fb)
2587 continue;
2588
2589 obj = intel_fb_obj(fb);
2590 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2591 drm_framebuffer_reference(fb);
2592 goto valid_fb;
2593 }
2594 }
2595
2596 /*
2597 * We've failed to reconstruct the BIOS FB. Current display state
2598 * indicates that the primary plane is visible, but has a NULL FB,
2599 * which will lead to problems later if we don't fix it up. The
2600 * simplest solution is to just disable the primary plane now and
2601 * pretend the BIOS never had it enabled.
2602 */
2603 to_intel_plane_state(plane_state)->visible = false;
2604 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2605 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2606 intel_plane->disable_plane(primary, &intel_crtc->base);
2607
2608 return;
2609
2610 valid_fb:
2611 plane_state->src_x = 0;
2612 plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2615
2616 plane_state->crtc_x = 0;
2617 plane_state->crtc_y = 0;
2618 plane_state->crtc_w = fb->width;
2619 plane_state->crtc_h = fb->height;
2620
2621 intel_state->src.x1 = plane_state->src_x;
2622 intel_state->src.y1 = plane_state->src_y;
2623 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2624 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2625 intel_state->dst.x1 = plane_state->crtc_x;
2626 intel_state->dst.y1 = plane_state->crtc_y;
2627 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2628 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2629
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 drm_framebuffer_reference(fb);
2635 primary->fb = primary->state->fb = fb;
2636 primary->crtc = primary->state->crtc = &intel_crtc->base;
2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2639 }
2640
2641 static void i9xx_update_primary_plane(struct drm_plane *primary,
2642 const struct intel_crtc_state *crtc_state,
2643 const struct intel_plane_state *plane_state)
2644 {
2645 struct drm_device *dev = primary->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2648 struct drm_framebuffer *fb = plane_state->base.fb;
2649 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2650 int plane = intel_crtc->plane;
2651 u32 linear_offset;
2652 u32 dspcntr;
2653 i915_reg_t reg = DSPCNTR(plane);
2654 unsigned int rotation = plane_state->base.rotation;
2655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2656 int x = plane_state->src.x1 >> 16;
2657 int y = plane_state->src.y1 >> 16;
2658
2659 dspcntr = DISPPLANE_GAMMA_ENABLE;
2660
2661 dspcntr |= DISPLAY_PLANE_ENABLE;
2662
2663 if (INTEL_INFO(dev)->gen < 4) {
2664 if (intel_crtc->pipe == PIPE_B)
2665 dspcntr |= DISPPLANE_SEL_PIPE_B;
2666
2667 /* pipesrc and dspsize control the size that is scaled from,
2668 * which should always be the user's requested size.
2669 */
2670 I915_WRITE(DSPSIZE(plane),
2671 ((crtc_state->pipe_src_h - 1) << 16) |
2672 (crtc_state->pipe_src_w - 1));
2673 I915_WRITE(DSPPOS(plane), 0);
2674 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2675 I915_WRITE(PRIMSIZE(plane),
2676 ((crtc_state->pipe_src_h - 1) << 16) |
2677 (crtc_state->pipe_src_w - 1));
2678 I915_WRITE(PRIMPOS(plane), 0);
2679 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2680 }
2681
2682 switch (fb->pixel_format) {
2683 case DRM_FORMAT_C8:
2684 dspcntr |= DISPPLANE_8BPP;
2685 break;
2686 case DRM_FORMAT_XRGB1555:
2687 dspcntr |= DISPPLANE_BGRX555;
2688 break;
2689 case DRM_FORMAT_RGB565:
2690 dspcntr |= DISPPLANE_BGRX565;
2691 break;
2692 case DRM_FORMAT_XRGB8888:
2693 dspcntr |= DISPPLANE_BGRX888;
2694 break;
2695 case DRM_FORMAT_XBGR8888:
2696 dspcntr |= DISPPLANE_RGBX888;
2697 break;
2698 case DRM_FORMAT_XRGB2101010:
2699 dspcntr |= DISPPLANE_BGRX101010;
2700 break;
2701 case DRM_FORMAT_XBGR2101010:
2702 dspcntr |= DISPPLANE_RGBX101010;
2703 break;
2704 default:
2705 BUG();
2706 }
2707
2708 if (INTEL_INFO(dev)->gen >= 4 &&
2709 obj->tiling_mode != I915_TILING_NONE)
2710 dspcntr |= DISPPLANE_TILED;
2711
2712 if (IS_G4X(dev))
2713 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2714
2715 linear_offset = y * fb->pitches[0] + x * cpp;
2716
2717 if (INTEL_INFO(dev)->gen >= 4) {
2718 intel_crtc->dspaddr_offset =
2719 intel_compute_tile_offset(&x, &y, fb, 0,
2720 fb->pitches[0], rotation);
2721 linear_offset -= intel_crtc->dspaddr_offset;
2722 } else {
2723 intel_crtc->dspaddr_offset = linear_offset;
2724 }
2725
2726 if (rotation == BIT(DRM_ROTATE_180)) {
2727 dspcntr |= DISPPLANE_ROTATE_180;
2728
2729 x += (crtc_state->pipe_src_w - 1);
2730 y += (crtc_state->pipe_src_h - 1);
2731
2732 /* Finding the last pixel of the last line of the display
2733 data and adding to linear_offset*/
2734 linear_offset +=
2735 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2736 (crtc_state->pipe_src_w - 1) * cpp;
2737 }
2738
2739 intel_crtc->adjusted_x = x;
2740 intel_crtc->adjusted_y = y;
2741
2742 I915_WRITE(reg, dspcntr);
2743
2744 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 I915_WRITE(DSPSURF(plane),
2747 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2748 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2749 I915_WRITE(DSPLINOFF(plane), linear_offset);
2750 } else
2751 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2752 POSTING_READ(reg);
2753 }
2754
2755 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2756 struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int plane = intel_crtc->plane;
2762
2763 I915_WRITE(DSPCNTR(plane), 0);
2764 if (INTEL_INFO(dev_priv)->gen >= 4)
2765 I915_WRITE(DSPSURF(plane), 0);
2766 else
2767 I915_WRITE(DSPADDR(plane), 0);
2768 POSTING_READ(DSPCNTR(plane));
2769 }
2770
2771 static void ironlake_update_primary_plane(struct drm_plane *primary,
2772 const struct intel_crtc_state *crtc_state,
2773 const struct intel_plane_state *plane_state)
2774 {
2775 struct drm_device *dev = primary->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2778 struct drm_framebuffer *fb = plane_state->base.fb;
2779 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2780 int plane = intel_crtc->plane;
2781 u32 linear_offset;
2782 u32 dspcntr;
2783 i915_reg_t reg = DSPCNTR(plane);
2784 unsigned int rotation = plane_state->base.rotation;
2785 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2786 int x = plane_state->src.x1 >> 16;
2787 int y = plane_state->src.y1 >> 16;
2788
2789 dspcntr = DISPPLANE_GAMMA_ENABLE;
2790 dspcntr |= DISPLAY_PLANE_ENABLE;
2791
2792 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2793 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2794
2795 switch (fb->pixel_format) {
2796 case DRM_FORMAT_C8:
2797 dspcntr |= DISPPLANE_8BPP;
2798 break;
2799 case DRM_FORMAT_RGB565:
2800 dspcntr |= DISPPLANE_BGRX565;
2801 break;
2802 case DRM_FORMAT_XRGB8888:
2803 dspcntr |= DISPPLANE_BGRX888;
2804 break;
2805 case DRM_FORMAT_XBGR8888:
2806 dspcntr |= DISPPLANE_RGBX888;
2807 break;
2808 case DRM_FORMAT_XRGB2101010:
2809 dspcntr |= DISPPLANE_BGRX101010;
2810 break;
2811 case DRM_FORMAT_XBGR2101010:
2812 dspcntr |= DISPPLANE_RGBX101010;
2813 break;
2814 default:
2815 BUG();
2816 }
2817
2818 if (obj->tiling_mode != I915_TILING_NONE)
2819 dspcntr |= DISPPLANE_TILED;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2822 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2823
2824 linear_offset = y * fb->pitches[0] + x * cpp;
2825 intel_crtc->dspaddr_offset =
2826 intel_compute_tile_offset(&x, &y, fb, 0,
2827 fb->pitches[0], rotation);
2828 linear_offset -= intel_crtc->dspaddr_offset;
2829 if (rotation == BIT(DRM_ROTATE_180)) {
2830 dspcntr |= DISPPLANE_ROTATE_180;
2831
2832 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2833 x += (crtc_state->pipe_src_w - 1);
2834 y += (crtc_state->pipe_src_h - 1);
2835
2836 /* Finding the last pixel of the last line of the display
2837 data and adding to linear_offset*/
2838 linear_offset +=
2839 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2840 (crtc_state->pipe_src_w - 1) * cpp;
2841 }
2842 }
2843
2844 intel_crtc->adjusted_x = x;
2845 intel_crtc->adjusted_y = y;
2846
2847 I915_WRITE(reg, dspcntr);
2848
2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
2858 POSTING_READ(reg);
2859 }
2860
2861 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2862 uint64_t fb_modifier, uint32_t pixel_format)
2863 {
2864 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2865 return 64;
2866 } else {
2867 int cpp = drm_format_plane_cpp(pixel_format, 0);
2868
2869 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2870 }
2871 }
2872
2873 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2874 struct drm_i915_gem_object *obj,
2875 unsigned int plane)
2876 {
2877 struct i915_ggtt_view view;
2878 struct i915_vma *vma;
2879 u64 offset;
2880
2881 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2882 intel_plane->base.state->rotation);
2883
2884 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2885 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2886 view.type))
2887 return -1;
2888
2889 offset = vma->node.start;
2890
2891 if (plane == 1) {
2892 offset += vma->ggtt_view.params.rotated.uv_start_page *
2893 PAGE_SIZE;
2894 }
2895
2896 WARN_ON(upper_32_bits(offset));
2897
2898 return lower_32_bits(offset);
2899 }
2900
2901 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2902 {
2903 struct drm_device *dev = intel_crtc->base.dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2907 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2908 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2909 }
2910
2911 /*
2912 * This function detaches (aka. unbinds) unused scalers in hardware
2913 */
2914 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2915 {
2916 struct intel_crtc_scaler_state *scaler_state;
2917 int i;
2918
2919 scaler_state = &intel_crtc->config->scaler_state;
2920
2921 /* loop through and disable scalers that aren't in use */
2922 for (i = 0; i < intel_crtc->num_scalers; i++) {
2923 if (!scaler_state->scalers[i].in_use)
2924 skl_detach_scaler(intel_crtc, i);
2925 }
2926 }
2927
2928 u32 skl_plane_ctl_format(uint32_t pixel_format)
2929 {
2930 switch (pixel_format) {
2931 case DRM_FORMAT_C8:
2932 return PLANE_CTL_FORMAT_INDEXED;
2933 case DRM_FORMAT_RGB565:
2934 return PLANE_CTL_FORMAT_RGB_565;
2935 case DRM_FORMAT_XBGR8888:
2936 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2937 case DRM_FORMAT_XRGB8888:
2938 return PLANE_CTL_FORMAT_XRGB_8888;
2939 /*
2940 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2941 * to be already pre-multiplied. We need to add a knob (or a different
2942 * DRM_FORMAT) for user-space to configure that.
2943 */
2944 case DRM_FORMAT_ABGR8888:
2945 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2946 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2947 case DRM_FORMAT_ARGB8888:
2948 return PLANE_CTL_FORMAT_XRGB_8888 |
2949 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2950 case DRM_FORMAT_XRGB2101010:
2951 return PLANE_CTL_FORMAT_XRGB_2101010;
2952 case DRM_FORMAT_XBGR2101010:
2953 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2954 case DRM_FORMAT_YUYV:
2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2956 case DRM_FORMAT_YVYU:
2957 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2958 case DRM_FORMAT_UYVY:
2959 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2960 case DRM_FORMAT_VYUY:
2961 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2962 default:
2963 MISSING_CASE(pixel_format);
2964 }
2965
2966 return 0;
2967 }
2968
2969 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2970 {
2971 switch (fb_modifier) {
2972 case DRM_FORMAT_MOD_NONE:
2973 break;
2974 case I915_FORMAT_MOD_X_TILED:
2975 return PLANE_CTL_TILED_X;
2976 case I915_FORMAT_MOD_Y_TILED:
2977 return PLANE_CTL_TILED_Y;
2978 case I915_FORMAT_MOD_Yf_TILED:
2979 return PLANE_CTL_TILED_YF;
2980 default:
2981 MISSING_CASE(fb_modifier);
2982 }
2983
2984 return 0;
2985 }
2986
2987 u32 skl_plane_ctl_rotation(unsigned int rotation)
2988 {
2989 switch (rotation) {
2990 case BIT(DRM_ROTATE_0):
2991 break;
2992 /*
2993 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2994 * while i915 HW rotation is clockwise, thats why this swapping.
2995 */
2996 case BIT(DRM_ROTATE_90):
2997 return PLANE_CTL_ROTATE_270;
2998 case BIT(DRM_ROTATE_180):
2999 return PLANE_CTL_ROTATE_180;
3000 case BIT(DRM_ROTATE_270):
3001 return PLANE_CTL_ROTATE_90;
3002 default:
3003 MISSING_CASE(rotation);
3004 }
3005
3006 return 0;
3007 }
3008
3009 static void skylake_update_primary_plane(struct drm_plane *plane,
3010 const struct intel_crtc_state *crtc_state,
3011 const struct intel_plane_state *plane_state)
3012 {
3013 struct drm_device *dev = plane->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3016 struct drm_framebuffer *fb = plane_state->base.fb;
3017 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3018 int pipe = intel_crtc->pipe;
3019 u32 plane_ctl, stride_div, stride;
3020 u32 tile_height, plane_offset, plane_size;
3021 unsigned int rotation = plane_state->base.rotation;
3022 int x_offset, y_offset;
3023 u32 surf_addr;
3024 int scaler_id = plane_state->scaler_id;
3025 int src_x = plane_state->src.x1 >> 16;
3026 int src_y = plane_state->src.y1 >> 16;
3027 int src_w = drm_rect_width(&plane_state->src) >> 16;
3028 int src_h = drm_rect_height(&plane_state->src) >> 16;
3029 int dst_x = plane_state->dst.x1;
3030 int dst_y = plane_state->dst.y1;
3031 int dst_w = drm_rect_width(&plane_state->dst);
3032 int dst_h = drm_rect_height(&plane_state->dst);
3033
3034 plane_ctl = PLANE_CTL_ENABLE |
3035 PLANE_CTL_PIPE_GAMMA_ENABLE |
3036 PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041 plane_ctl |= skl_plane_ctl_rotation(rotation);
3042
3043 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3044 fb->pixel_format);
3045 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3046
3047 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3048
3049 if (intel_rotation_90_or_270(rotation)) {
3050 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3051
3052 /* stride = Surface height in tiles */
3053 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3054 stride = DIV_ROUND_UP(fb->height, tile_height);
3055 x_offset = stride * tile_height - src_y - src_h;
3056 y_offset = src_x;
3057 plane_size = (src_w - 1) << 16 | (src_h - 1);
3058 } else {
3059 stride = fb->pitches[0] / stride_div;
3060 x_offset = src_x;
3061 y_offset = src_y;
3062 plane_size = (src_h - 1) << 16 | (src_w - 1);
3063 }
3064 plane_offset = y_offset << 16 | x_offset;
3065
3066 intel_crtc->adjusted_x = x_offset;
3067 intel_crtc->adjusted_y = y_offset;
3068
3069 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3070 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3071 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3072 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3073
3074 if (scaler_id >= 0) {
3075 uint32_t ps_ctrl = 0;
3076
3077 WARN_ON(!dst_w || !dst_h);
3078 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3079 crtc_state->scaler_state.scalers[scaler_id].mode;
3080 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3081 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3082 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3083 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3084 I915_WRITE(PLANE_POS(pipe, 0), 0);
3085 } else {
3086 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3087 }
3088
3089 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3090
3091 POSTING_READ(PLANE_SURF(pipe, 0));
3092 }
3093
3094 static void skylake_disable_primary_plane(struct drm_plane *primary,
3095 struct drm_crtc *crtc)
3096 {
3097 struct drm_device *dev = crtc->dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 int pipe = to_intel_crtc(crtc)->pipe;
3100
3101 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3102 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3103 POSTING_READ(PLANE_SURF(pipe, 0));
3104 }
3105
3106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3107 static int
3108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3109 int x, int y, enum mode_set_atomic state)
3110 {
3111 /* Support for kgdboc is disabled, this needs a major rework. */
3112 DRM_ERROR("legacy panic handler not supported any more.\n");
3113
3114 return -ENODEV;
3115 }
3116
3117 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3118 {
3119 struct intel_crtc *crtc;
3120
3121 for_each_intel_crtc(dev_priv->dev, crtc)
3122 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3123 }
3124
3125 static void intel_update_primary_planes(struct drm_device *dev)
3126 {
3127 struct drm_crtc *crtc;
3128
3129 for_each_crtc(dev, crtc) {
3130 struct intel_plane *plane = to_intel_plane(crtc->primary);
3131 struct intel_plane_state *plane_state;
3132
3133 drm_modeset_lock_crtc(crtc, &plane->base);
3134 plane_state = to_intel_plane_state(plane->base.state);
3135
3136 if (plane_state->visible)
3137 plane->update_plane(&plane->base,
3138 to_intel_crtc_state(crtc->state),
3139 plane_state);
3140
3141 drm_modeset_unlock_crtc(crtc);
3142 }
3143 }
3144
3145 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3146 {
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev_priv))
3149 return;
3150
3151 /* reset doesn't touch the display */
3152 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3153 return;
3154
3155 drm_modeset_lock_all(dev_priv->dev);
3156 /*
3157 * Disabling the crtcs gracefully seems nicer. Also the
3158 * g33 docs say we should at least disable all the planes.
3159 */
3160 intel_display_suspend(dev_priv->dev);
3161 }
3162
3163 void intel_finish_reset(struct drm_i915_private *dev_priv)
3164 {
3165 /*
3166 * Flips in the rings will be nuked by the reset,
3167 * so complete all pending flips so that user space
3168 * will get its events and not get stuck.
3169 */
3170 intel_complete_page_flips(dev_priv);
3171
3172 /* no reset support for gen2 */
3173 if (IS_GEN2(dev_priv))
3174 return;
3175
3176 /* reset doesn't touch the display */
3177 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3178 /*
3179 * Flips in the rings have been nuked by the reset,
3180 * so update the base address of all primary
3181 * planes to the the last fb to make sure we're
3182 * showing the correct fb after a reset.
3183 *
3184 * FIXME: Atomic will make this obsolete since we won't schedule
3185 * CS-based flips (which might get lost in gpu resets) any more.
3186 */
3187 intel_update_primary_planes(dev_priv->dev);
3188 return;
3189 }
3190
3191 /*
3192 * The display has been reset as well,
3193 * so need a full re-initialization.
3194 */
3195 intel_runtime_pm_disable_interrupts(dev_priv);
3196 intel_runtime_pm_enable_interrupts(dev_priv);
3197
3198 intel_modeset_init_hw(dev_priv->dev);
3199
3200 spin_lock_irq(&dev_priv->irq_lock);
3201 if (dev_priv->display.hpd_irq_setup)
3202 dev_priv->display.hpd_irq_setup(dev_priv);
3203 spin_unlock_irq(&dev_priv->irq_lock);
3204
3205 intel_display_resume(dev_priv->dev);
3206
3207 intel_hpd_init(dev_priv);
3208
3209 drm_modeset_unlock_all(dev_priv->dev);
3210 }
3211
3212 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3213 {
3214 struct drm_device *dev = crtc->dev;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 unsigned reset_counter;
3217 bool pending;
3218
3219 reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
3220 if (intel_crtc->reset_counter != reset_counter)
3221 return false;
3222
3223 spin_lock_irq(&dev->event_lock);
3224 pending = to_intel_crtc(crtc)->flip_work != NULL;
3225 spin_unlock_irq(&dev->event_lock);
3226
3227 return pending;
3228 }
3229
3230 static void intel_update_pipe_config(struct intel_crtc *crtc,
3231 struct intel_crtc_state *old_crtc_state)
3232 {
3233 struct drm_device *dev = crtc->base.dev;
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc_state *pipe_config =
3236 to_intel_crtc_state(crtc->base.state);
3237
3238 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3239 crtc->base.mode = crtc->base.state->mode;
3240
3241 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3242 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3243 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3244
3245 /*
3246 * Update pipe size and adjust fitter if needed: the reason for this is
3247 * that in compute_mode_changes we check the native mode (not the pfit
3248 * mode) to see if we can flip rather than do a full mode set. In the
3249 * fastboot case, we'll flip, but if we don't update the pipesrc and
3250 * pfit state, we'll end up with a big fb scanned out into the wrong
3251 * sized surface.
3252 */
3253
3254 I915_WRITE(PIPESRC(crtc->pipe),
3255 ((pipe_config->pipe_src_w - 1) << 16) |
3256 (pipe_config->pipe_src_h - 1));
3257
3258 /* on skylake this is done by detaching scalers */
3259 if (INTEL_INFO(dev)->gen >= 9) {
3260 skl_detach_scalers(crtc);
3261
3262 if (pipe_config->pch_pfit.enabled)
3263 skylake_pfit_enable(crtc);
3264 } else if (HAS_PCH_SPLIT(dev)) {
3265 if (pipe_config->pch_pfit.enabled)
3266 ironlake_pfit_enable(crtc);
3267 else if (old_crtc_state->pch_pfit.enabled)
3268 ironlake_pfit_disable(crtc, true);
3269 }
3270 }
3271
3272 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3273 {
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3278 i915_reg_t reg;
3279 u32 temp;
3280
3281 /* enable normal train */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 if (IS_IVYBRIDGE(dev)) {
3285 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3286 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3287 } else {
3288 temp &= ~FDI_LINK_TRAIN_NONE;
3289 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3290 }
3291 I915_WRITE(reg, temp);
3292
3293 reg = FDI_RX_CTL(pipe);
3294 temp = I915_READ(reg);
3295 if (HAS_PCH_CPT(dev)) {
3296 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3297 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3298 } else {
3299 temp &= ~FDI_LINK_TRAIN_NONE;
3300 temp |= FDI_LINK_TRAIN_NONE;
3301 }
3302 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3303
3304 /* wait one idle pattern time */
3305 POSTING_READ(reg);
3306 udelay(1000);
3307
3308 /* IVB wants error correction enabled */
3309 if (IS_IVYBRIDGE(dev))
3310 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3311 FDI_FE_ERRC_ENABLE);
3312 }
3313
3314 /* The FDI link training functions for ILK/Ibexpeak. */
3315 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3316 {
3317 struct drm_device *dev = crtc->dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320 int pipe = intel_crtc->pipe;
3321 i915_reg_t reg;
3322 u32 temp, tries;
3323
3324 /* FDI needs bits from pipe first */
3325 assert_pipe_enabled(dev_priv, pipe);
3326
3327 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3328 for train result */
3329 reg = FDI_RX_IMR(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~FDI_RX_SYMBOL_LOCK;
3332 temp &= ~FDI_RX_BIT_LOCK;
3333 I915_WRITE(reg, temp);
3334 I915_READ(reg);
3335 udelay(150);
3336
3337 /* enable CPU FDI TX and PCH FDI RX */
3338 reg = FDI_TX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3341 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3342 temp &= ~FDI_LINK_TRAIN_NONE;
3343 temp |= FDI_LINK_TRAIN_PATTERN_1;
3344 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3345
3346 reg = FDI_RX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_PATTERN_1;
3350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3351
3352 POSTING_READ(reg);
3353 udelay(150);
3354
3355 /* Ironlake workaround, enable clock pointer after FDI enable*/
3356 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3357 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3358 FDI_RX_PHASE_SYNC_POINTER_EN);
3359
3360 reg = FDI_RX_IIR(pipe);
3361 for (tries = 0; tries < 5; tries++) {
3362 temp = I915_READ(reg);
3363 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365 if ((temp & FDI_RX_BIT_LOCK)) {
3366 DRM_DEBUG_KMS("FDI train 1 done.\n");
3367 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3368 break;
3369 }
3370 }
3371 if (tries == 5)
3372 DRM_ERROR("FDI train 1 fail!\n");
3373
3374 /* Train 2 */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 I915_WRITE(reg, temp);
3380
3381 reg = FDI_RX_CTL(pipe);
3382 temp = I915_READ(reg);
3383 temp &= ~FDI_LINK_TRAIN_NONE;
3384 temp |= FDI_LINK_TRAIN_PATTERN_2;
3385 I915_WRITE(reg, temp);
3386
3387 POSTING_READ(reg);
3388 udelay(150);
3389
3390 reg = FDI_RX_IIR(pipe);
3391 for (tries = 0; tries < 5; tries++) {
3392 temp = I915_READ(reg);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if (temp & FDI_RX_SYMBOL_LOCK) {
3396 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3397 DRM_DEBUG_KMS("FDI train 2 done.\n");
3398 break;
3399 }
3400 }
3401 if (tries == 5)
3402 DRM_ERROR("FDI train 2 fail!\n");
3403
3404 DRM_DEBUG_KMS("FDI train done\n");
3405
3406 }
3407
3408 static const int snb_b_fdi_train_param[] = {
3409 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3410 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3411 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3412 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3413 };
3414
3415 /* The FDI link training functions for SNB/Cougarpoint. */
3416 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 i915_reg_t reg;
3423 u32 temp, i, retry;
3424
3425 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3426 for train result */
3427 reg = FDI_RX_IMR(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~FDI_RX_SYMBOL_LOCK;
3430 temp &= ~FDI_RX_BIT_LOCK;
3431 I915_WRITE(reg, temp);
3432
3433 POSTING_READ(reg);
3434 udelay(150);
3435
3436 /* enable CPU FDI TX and PCH FDI RX */
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3440 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_1;
3443 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3444 /* SNB-B */
3445 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3446 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3447
3448 I915_WRITE(FDI_RX_MISC(pipe),
3449 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 if (HAS_PCH_CPT(dev)) {
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3456 } else {
3457 temp &= ~FDI_LINK_TRAIN_NONE;
3458 temp |= FDI_LINK_TRAIN_PATTERN_1;
3459 }
3460 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(150);
3464
3465 for (i = 0; i < 4; i++) {
3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3469 temp |= snb_b_fdi_train_param[i];
3470 I915_WRITE(reg, temp);
3471
3472 POSTING_READ(reg);
3473 udelay(500);
3474
3475 for (retry = 0; retry < 5; retry++) {
3476 reg = FDI_RX_IIR(pipe);
3477 temp = I915_READ(reg);
3478 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3479 if (temp & FDI_RX_BIT_LOCK) {
3480 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3481 DRM_DEBUG_KMS("FDI train 1 done.\n");
3482 break;
3483 }
3484 udelay(50);
3485 }
3486 if (retry < 5)
3487 break;
3488 }
3489 if (i == 4)
3490 DRM_ERROR("FDI train 1 fail!\n");
3491
3492 /* Train 2 */
3493 reg = FDI_TX_CTL(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_LINK_TRAIN_NONE;
3496 temp |= FDI_LINK_TRAIN_PATTERN_2;
3497 if (IS_GEN6(dev)) {
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3501 }
3502 I915_WRITE(reg, temp);
3503
3504 reg = FDI_RX_CTL(pipe);
3505 temp = I915_READ(reg);
3506 if (HAS_PCH_CPT(dev)) {
3507 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3508 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3509 } else {
3510 temp &= ~FDI_LINK_TRAIN_NONE;
3511 temp |= FDI_LINK_TRAIN_PATTERN_2;
3512 }
3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
3516 udelay(150);
3517
3518 for (i = 0; i < 4; i++) {
3519 reg = FDI_TX_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= snb_b_fdi_train_param[i];
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(500);
3527
3528 for (retry = 0; retry < 5; retry++) {
3529 reg = FDI_RX_IIR(pipe);
3530 temp = I915_READ(reg);
3531 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3532 if (temp & FDI_RX_SYMBOL_LOCK) {
3533 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3534 DRM_DEBUG_KMS("FDI train 2 done.\n");
3535 break;
3536 }
3537 udelay(50);
3538 }
3539 if (retry < 5)
3540 break;
3541 }
3542 if (i == 4)
3543 DRM_ERROR("FDI train 2 fail!\n");
3544
3545 DRM_DEBUG_KMS("FDI train done.\n");
3546 }
3547
3548 /* Manual link training for Ivy Bridge A0 parts */
3549 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 int pipe = intel_crtc->pipe;
3555 i915_reg_t reg;
3556 u32 temp, i, j;
3557
3558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3559 for train result */
3560 reg = FDI_RX_IMR(pipe);
3561 temp = I915_READ(reg);
3562 temp &= ~FDI_RX_SYMBOL_LOCK;
3563 temp &= ~FDI_RX_BIT_LOCK;
3564 I915_WRITE(reg, temp);
3565
3566 POSTING_READ(reg);
3567 udelay(150);
3568
3569 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3570 I915_READ(FDI_RX_IIR(pipe)));
3571
3572 /* Try each vswing and preemphasis setting twice before moving on */
3573 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3574 /* disable first in case we need to retry */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3578 temp &= ~FDI_TX_ENABLE;
3579 I915_WRITE(reg, temp);
3580
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~FDI_LINK_TRAIN_AUTO;
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp &= ~FDI_RX_ENABLE;
3586 I915_WRITE(reg, temp);
3587
3588 /* enable CPU FDI TX and PCH FDI RX */
3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3593 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3595 temp |= snb_b_fdi_train_param[j/2];
3596 temp |= FDI_COMPOSITE_SYNC;
3597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3598
3599 I915_WRITE(FDI_RX_MISC(pipe),
3600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3601
3602 reg = FDI_RX_CTL(pipe);
3603 temp = I915_READ(reg);
3604 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3605 temp |= FDI_COMPOSITE_SYNC;
3606 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3607
3608 POSTING_READ(reg);
3609 udelay(1); /* should be 0.5us */
3610
3611 for (i = 0; i < 4; i++) {
3612 reg = FDI_RX_IIR(pipe);
3613 temp = I915_READ(reg);
3614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3615
3616 if (temp & FDI_RX_BIT_LOCK ||
3617 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3619 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3620 i);
3621 break;
3622 }
3623 udelay(1); /* should be 0.5us */
3624 }
3625 if (i == 4) {
3626 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3627 continue;
3628 }
3629
3630 /* Train 2 */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3635 I915_WRITE(reg, temp);
3636
3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3640 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3641 I915_WRITE(reg, temp);
3642
3643 POSTING_READ(reg);
3644 udelay(2); /* should be 1.5us */
3645
3646 for (i = 0; i < 4; i++) {
3647 reg = FDI_RX_IIR(pipe);
3648 temp = I915_READ(reg);
3649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3650
3651 if (temp & FDI_RX_SYMBOL_LOCK ||
3652 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3653 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3654 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3655 i);
3656 goto train_done;
3657 }
3658 udelay(2); /* should be 1.5us */
3659 }
3660 if (i == 4)
3661 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3662 }
3663
3664 train_done:
3665 DRM_DEBUG_KMS("FDI train done.\n");
3666 }
3667
3668 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3669 {
3670 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 int pipe = intel_crtc->pipe;
3673 i915_reg_t reg;
3674 u32 temp;
3675
3676 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3677 reg = FDI_RX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3682 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(200);
3686
3687 /* Switch from Rawclk to PCDclk */
3688 temp = I915_READ(reg);
3689 I915_WRITE(reg, temp | FDI_PCDCLK);
3690
3691 POSTING_READ(reg);
3692 udelay(200);
3693
3694 /* Enable CPU FDI TX PLL, always on for Ironlake */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3698 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3699
3700 POSTING_READ(reg);
3701 udelay(100);
3702 }
3703 }
3704
3705 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3706 {
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int pipe = intel_crtc->pipe;
3710 i915_reg_t reg;
3711 u32 temp;
3712
3713 /* Switch from PCDclk to Rawclk */
3714 reg = FDI_RX_CTL(pipe);
3715 temp = I915_READ(reg);
3716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3717
3718 /* Disable CPU FDI TX PLL */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3722
3723 POSTING_READ(reg);
3724 udelay(100);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3729
3730 /* Wait for the clocks to turn off. */
3731 POSTING_READ(reg);
3732 udelay(100);
3733 }
3734
3735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3736 {
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740 int pipe = intel_crtc->pipe;
3741 i915_reg_t reg;
3742 u32 temp;
3743
3744 /* disable CPU FDI tx and PCH FDI rx */
3745 reg = FDI_TX_CTL(pipe);
3746 temp = I915_READ(reg);
3747 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3748 POSTING_READ(reg);
3749
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~(0x7 << 16);
3753 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3754 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 /* Ironlake workaround, disable clock pointer after downing FDI */
3760 if (HAS_PCH_IBX(dev))
3761 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3762
3763 /* still set train pattern 1 */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 temp &= ~FDI_LINK_TRAIN_NONE;
3767 temp |= FDI_LINK_TRAIN_PATTERN_1;
3768 I915_WRITE(reg, temp);
3769
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 if (HAS_PCH_CPT(dev)) {
3773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3775 } else {
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_1;
3778 }
3779 /* BPC in FDI rx is consistent with that in PIPECONF */
3780 temp &= ~(0x07 << 16);
3781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3782 I915_WRITE(reg, temp);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786 }
3787
3788 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3789 {
3790 struct intel_crtc *crtc;
3791
3792 /* Note that we don't need to be called with mode_config.lock here
3793 * as our list of CRTC objects is static for the lifetime of the
3794 * device and so cannot disappear as we iterate. Similarly, we can
3795 * happily treat the predicates as racy, atomic checks as userspace
3796 * cannot claim and pin a new fb without at least acquring the
3797 * struct_mutex and so serialising with us.
3798 */
3799 for_each_intel_crtc(dev, crtc) {
3800 if (atomic_read(&crtc->unpin_work_count) == 0)
3801 continue;
3802
3803 if (crtc->flip_work)
3804 intel_wait_for_vblank(dev, crtc->pipe);
3805
3806 return true;
3807 }
3808
3809 return false;
3810 }
3811
3812 static void page_flip_completed(struct intel_crtc *intel_crtc)
3813 {
3814 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3815 struct intel_flip_work *work = intel_crtc->flip_work;
3816
3817 intel_crtc->flip_work = NULL;
3818
3819 if (work->event)
3820 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3821
3822 drm_crtc_vblank_put(&intel_crtc->base);
3823
3824 wake_up_all(&dev_priv->pending_flip_queue);
3825 queue_work(dev_priv->wq, &work->unpin_work);
3826
3827 trace_i915_flip_complete(intel_crtc->plane,
3828 work->pending_flip_obj);
3829 }
3830
3831 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3832 {
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 long ret;
3836
3837 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3838
3839 ret = wait_event_interruptible_timeout(
3840 dev_priv->pending_flip_queue,
3841 !intel_crtc_has_pending_flip(crtc),
3842 60*HZ);
3843
3844 if (ret < 0)
3845 return ret;
3846
3847 if (ret == 0) {
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 struct intel_flip_work *work;
3850
3851 spin_lock_irq(&dev->event_lock);
3852 work = intel_crtc->flip_work;
3853 if (work && !is_mmio_work(work)) {
3854 WARN_ONCE(1, "Removing stuck page flip\n");
3855 page_flip_completed(intel_crtc);
3856 }
3857 spin_unlock_irq(&dev->event_lock);
3858 }
3859
3860 return 0;
3861 }
3862
3863 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3864 {
3865 u32 temp;
3866
3867 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3868
3869 mutex_lock(&dev_priv->sb_lock);
3870
3871 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3872 temp |= SBI_SSCCTL_DISABLE;
3873 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3874
3875 mutex_unlock(&dev_priv->sb_lock);
3876 }
3877
3878 /* Program iCLKIP clock to the desired frequency */
3879 static void lpt_program_iclkip(struct drm_crtc *crtc)
3880 {
3881 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3882 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3883 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3884 u32 temp;
3885
3886 lpt_disable_iclkip(dev_priv);
3887
3888 /* The iCLK virtual clock root frequency is in MHz,
3889 * but the adjusted_mode->crtc_clock in in KHz. To get the
3890 * divisors, it is necessary to divide one by another, so we
3891 * convert the virtual clock precision to KHz here for higher
3892 * precision.
3893 */
3894 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3895 u32 iclk_virtual_root_freq = 172800 * 1000;
3896 u32 iclk_pi_range = 64;
3897 u32 desired_divisor;
3898
3899 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3900 clock << auxdiv);
3901 divsel = (desired_divisor / iclk_pi_range) - 2;
3902 phaseinc = desired_divisor % iclk_pi_range;
3903
3904 /*
3905 * Near 20MHz is a corner case which is
3906 * out of range for the 7-bit divisor
3907 */
3908 if (divsel <= 0x7f)
3909 break;
3910 }
3911
3912 /* This should not happen with any sane values */
3913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3917
3918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3919 clock,
3920 auxdiv,
3921 divsel,
3922 phasedir,
3923 phaseinc);
3924
3925 mutex_lock(&dev_priv->sb_lock);
3926
3927 /* Program SSCDIVINTPHASE6 */
3928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3936
3937 /* Program SSCAUXDIV */
3938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3942
3943 /* Enable modulator and associated divider */
3944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3945 temp &= ~SBI_SSCCTL_DISABLE;
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3947
3948 mutex_unlock(&dev_priv->sb_lock);
3949
3950 /* Wait for initialization time */
3951 udelay(24);
3952
3953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3954 }
3955
3956 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3957 {
3958 u32 divsel, phaseinc, auxdiv;
3959 u32 iclk_virtual_root_freq = 172800 * 1000;
3960 u32 iclk_pi_range = 64;
3961 u32 desired_divisor;
3962 u32 temp;
3963
3964 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3965 return 0;
3966
3967 mutex_lock(&dev_priv->sb_lock);
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3970 if (temp & SBI_SSCCTL_DISABLE) {
3971 mutex_unlock(&dev_priv->sb_lock);
3972 return 0;
3973 }
3974
3975 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3976 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3977 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3978 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3979 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3980
3981 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3982 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3983 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3984
3985 mutex_unlock(&dev_priv->sb_lock);
3986
3987 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3988
3989 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3990 desired_divisor << auxdiv);
3991 }
3992
3993 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3994 enum pipe pch_transcoder)
3995 {
3996 struct drm_device *dev = crtc->base.dev;
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3999
4000 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4001 I915_READ(HTOTAL(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4003 I915_READ(HBLANK(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4005 I915_READ(HSYNC(cpu_transcoder)));
4006
4007 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4008 I915_READ(VTOTAL(cpu_transcoder)));
4009 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4010 I915_READ(VBLANK(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4012 I915_READ(VSYNC(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4014 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4015 }
4016
4017 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4018 {
4019 struct drm_i915_private *dev_priv = dev->dev_private;
4020 uint32_t temp;
4021
4022 temp = I915_READ(SOUTH_CHICKEN1);
4023 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4024 return;
4025
4026 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4027 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4028
4029 temp &= ~FDI_BC_BIFURCATION_SELECT;
4030 if (enable)
4031 temp |= FDI_BC_BIFURCATION_SELECT;
4032
4033 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4034 I915_WRITE(SOUTH_CHICKEN1, temp);
4035 POSTING_READ(SOUTH_CHICKEN1);
4036 }
4037
4038 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4039 {
4040 struct drm_device *dev = intel_crtc->base.dev;
4041
4042 switch (intel_crtc->pipe) {
4043 case PIPE_A:
4044 break;
4045 case PIPE_B:
4046 if (intel_crtc->config->fdi_lanes > 2)
4047 cpt_set_fdi_bc_bifurcation(dev, false);
4048 else
4049 cpt_set_fdi_bc_bifurcation(dev, true);
4050
4051 break;
4052 case PIPE_C:
4053 cpt_set_fdi_bc_bifurcation(dev, true);
4054
4055 break;
4056 default:
4057 BUG();
4058 }
4059 }
4060
4061 /* Return which DP Port should be selected for Transcoder DP control */
4062 static enum port
4063 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4064 {
4065 struct drm_device *dev = crtc->dev;
4066 struct intel_encoder *encoder;
4067
4068 for_each_encoder_on_crtc(dev, crtc, encoder) {
4069 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4070 encoder->type == INTEL_OUTPUT_EDP)
4071 return enc_to_dig_port(&encoder->base)->port;
4072 }
4073
4074 return -1;
4075 }
4076
4077 /*
4078 * Enable PCH resources required for PCH ports:
4079 * - PCH PLLs
4080 * - FDI training & RX/TX
4081 * - update transcoder timings
4082 * - DP transcoding bits
4083 * - transcoder
4084 */
4085 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090 int pipe = intel_crtc->pipe;
4091 u32 temp;
4092
4093 assert_pch_transcoder_disabled(dev_priv, pipe);
4094
4095 if (IS_IVYBRIDGE(dev))
4096 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097
4098 /* Write the TU size bits before fdi link training, so that error
4099 * detection works. */
4100 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4101 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102
4103 /* For PCH output, training FDI link */
4104 dev_priv->display.fdi_link_train(crtc);
4105
4106 /* We need to program the right clock selection before writing the pixel
4107 * mutliplier into the DPLL. */
4108 if (HAS_PCH_CPT(dev)) {
4109 u32 sel;
4110
4111 temp = I915_READ(PCH_DPLL_SEL);
4112 temp |= TRANS_DPLL_ENABLE(pipe);
4113 sel = TRANS_DPLLB_SEL(pipe);
4114 if (intel_crtc->config->shared_dpll ==
4115 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4116 temp |= sel;
4117 else
4118 temp &= ~sel;
4119 I915_WRITE(PCH_DPLL_SEL, temp);
4120 }
4121
4122 /* XXX: pch pll's can be enabled any time before we enable the PCH
4123 * transcoder, and we actually should do this to not upset any PCH
4124 * transcoder that already use the clock when we share it.
4125 *
4126 * Note that enable_shared_dpll tries to do the right thing, but
4127 * get_shared_dpll unconditionally resets the pll - we need that to have
4128 * the right LVDS enable sequence. */
4129 intel_enable_shared_dpll(intel_crtc);
4130
4131 /* set transcoder timing, panel must allow it */
4132 assert_panel_unlocked(dev_priv, pipe);
4133 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4134
4135 intel_fdi_normal_train(crtc);
4136
4137 /* For PCH DP, enable TRANS_DP_CTL */
4138 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4139 const struct drm_display_mode *adjusted_mode =
4140 &intel_crtc->config->base.adjusted_mode;
4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4142 i915_reg_t reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
4147 temp |= TRANS_DP_OUTPUT_ENABLE;
4148 temp |= bpc << 9; /* same format but at 11:9 */
4149
4150 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4152 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PORT_B:
4157 temp |= TRANS_DP_PORT_SEL_B;
4158 break;
4159 case PORT_C:
4160 temp |= TRANS_DP_PORT_SEL_C;
4161 break;
4162 case PORT_D:
4163 temp |= TRANS_DP_PORT_SEL_D;
4164 break;
4165 default:
4166 BUG();
4167 }
4168
4169 I915_WRITE(reg, temp);
4170 }
4171
4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
4173 }
4174
4175 static void lpt_pch_enable(struct drm_crtc *crtc)
4176 {
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4181
4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4183
4184 lpt_program_iclkip(crtc);
4185
4186 /* Set transcoder timing. */
4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4188
4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4190 }
4191
4192 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4193 {
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 i915_reg_t dslreg = PIPEDSL(pipe);
4196 u32 temp;
4197
4198 temp = I915_READ(dslreg);
4199 udelay(500);
4200 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4201 if (wait_for(I915_READ(dslreg) != temp, 5))
4202 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4203 }
4204 }
4205
4206 static int
4207 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4208 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4209 int src_w, int src_h, int dst_w, int dst_h)
4210 {
4211 struct intel_crtc_scaler_state *scaler_state =
4212 &crtc_state->scaler_state;
4213 struct intel_crtc *intel_crtc =
4214 to_intel_crtc(crtc_state->base.crtc);
4215 int need_scaling;
4216
4217 need_scaling = intel_rotation_90_or_270(rotation) ?
4218 (src_h != dst_w || src_w != dst_h):
4219 (src_w != dst_w || src_h != dst_h);
4220
4221 /*
4222 * if plane is being disabled or scaler is no more required or force detach
4223 * - free scaler binded to this plane/crtc
4224 * - in order to do this, update crtc->scaler_usage
4225 *
4226 * Here scaler state in crtc_state is set free so that
4227 * scaler can be assigned to other user. Actual register
4228 * update to free the scaler is done in plane/panel-fit programming.
4229 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4230 */
4231 if (force_detach || !need_scaling) {
4232 if (*scaler_id >= 0) {
4233 scaler_state->scaler_users &= ~(1 << scaler_user);
4234 scaler_state->scalers[*scaler_id].in_use = 0;
4235
4236 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4237 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4238 intel_crtc->pipe, scaler_user, *scaler_id,
4239 scaler_state->scaler_users);
4240 *scaler_id = -1;
4241 }
4242 return 0;
4243 }
4244
4245 /* range checks */
4246 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4247 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4248
4249 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4250 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4251 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4252 "size is out of scaler range\n",
4253 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4254 return -EINVAL;
4255 }
4256
4257 /* mark this plane as a scaler user in crtc_state */
4258 scaler_state->scaler_users |= (1 << scaler_user);
4259 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4260 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4261 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4262 scaler_state->scaler_users);
4263
4264 return 0;
4265 }
4266
4267 /**
4268 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4269 *
4270 * @state: crtc's scaler state
4271 *
4272 * Return
4273 * 0 - scaler_usage updated successfully
4274 * error - requested scaling cannot be supported or other error condition
4275 */
4276 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4277 {
4278 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4279 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4280
4281 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4282 intel_crtc->base.base.id, intel_crtc->base.name,
4283 intel_crtc->pipe, SKL_CRTC_INDEX);
4284
4285 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4286 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4287 state->pipe_src_w, state->pipe_src_h,
4288 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4289 }
4290
4291 /**
4292 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4293 *
4294 * @state: crtc's scaler state
4295 * @plane_state: atomic plane state to update
4296 *
4297 * Return
4298 * 0 - scaler_usage updated successfully
4299 * error - requested scaling cannot be supported or other error condition
4300 */
4301 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4302 struct intel_plane_state *plane_state)
4303 {
4304
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4306 struct intel_plane *intel_plane =
4307 to_intel_plane(plane_state->base.plane);
4308 struct drm_framebuffer *fb = plane_state->base.fb;
4309 int ret;
4310
4311 bool force_detach = !fb || !plane_state->visible;
4312
4313 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4314 intel_plane->base.base.id, intel_plane->base.name,
4315 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4316
4317 ret = skl_update_scaler(crtc_state, force_detach,
4318 drm_plane_index(&intel_plane->base),
4319 &plane_state->scaler_id,
4320 plane_state->base.rotation,
4321 drm_rect_width(&plane_state->src) >> 16,
4322 drm_rect_height(&plane_state->src) >> 16,
4323 drm_rect_width(&plane_state->dst),
4324 drm_rect_height(&plane_state->dst));
4325
4326 if (ret || plane_state->scaler_id < 0)
4327 return ret;
4328
4329 /* check colorkey */
4330 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4331 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4332 intel_plane->base.base.id,
4333 intel_plane->base.name);
4334 return -EINVAL;
4335 }
4336
4337 /* Check src format */
4338 switch (fb->pixel_format) {
4339 case DRM_FORMAT_RGB565:
4340 case DRM_FORMAT_XBGR8888:
4341 case DRM_FORMAT_XRGB8888:
4342 case DRM_FORMAT_ABGR8888:
4343 case DRM_FORMAT_ARGB8888:
4344 case DRM_FORMAT_XRGB2101010:
4345 case DRM_FORMAT_XBGR2101010:
4346 case DRM_FORMAT_YUYV:
4347 case DRM_FORMAT_YVYU:
4348 case DRM_FORMAT_UYVY:
4349 case DRM_FORMAT_VYUY:
4350 break;
4351 default:
4352 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4353 intel_plane->base.base.id, intel_plane->base.name,
4354 fb->base.id, fb->pixel_format);
4355 return -EINVAL;
4356 }
4357
4358 return 0;
4359 }
4360
4361 static void skylake_scaler_disable(struct intel_crtc *crtc)
4362 {
4363 int i;
4364
4365 for (i = 0; i < crtc->num_scalers; i++)
4366 skl_detach_scaler(crtc, i);
4367 }
4368
4369 static void skylake_pfit_enable(struct intel_crtc *crtc)
4370 {
4371 struct drm_device *dev = crtc->base.dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int pipe = crtc->pipe;
4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc->config->scaler_state;
4376
4377 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4378
4379 if (crtc->config->pch_pfit.enabled) {
4380 int id;
4381
4382 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4383 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4384 return;
4385 }
4386
4387 id = scaler_state->scaler_id;
4388 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4389 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4390 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4391 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4392
4393 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4394 }
4395 }
4396
4397 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4398 {
4399 struct drm_device *dev = crtc->base.dev;
4400 struct drm_i915_private *dev_priv = dev->dev_private;
4401 int pipe = crtc->pipe;
4402
4403 if (crtc->config->pch_pfit.enabled) {
4404 /* Force use of hard-coded filter coefficients
4405 * as some pre-programmed values are broken,
4406 * e.g. x201.
4407 */
4408 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4409 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4410 PF_PIPE_SEL_IVB(pipe));
4411 else
4412 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4413 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4414 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4415 }
4416 }
4417
4418 void hsw_enable_ips(struct intel_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422
4423 if (!crtc->config->ips_enabled)
4424 return;
4425
4426 /*
4427 * We can only enable IPS after we enable a plane and wait for a vblank
4428 * This function is called from post_plane_update, which is run after
4429 * a vblank wait.
4430 */
4431
4432 assert_plane_enabled(dev_priv, crtc->plane);
4433 if (IS_BROADWELL(dev)) {
4434 mutex_lock(&dev_priv->rps.hw_lock);
4435 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4436 mutex_unlock(&dev_priv->rps.hw_lock);
4437 /* Quoting Art Runyan: "its not safe to expect any particular
4438 * value in IPS_CTL bit 31 after enabling IPS through the
4439 * mailbox." Moreover, the mailbox may return a bogus state,
4440 * so we need to just enable it and continue on.
4441 */
4442 } else {
4443 I915_WRITE(IPS_CTL, IPS_ENABLE);
4444 /* The bit only becomes 1 in the next vblank, so this wait here
4445 * is essentially intel_wait_for_vblank. If we don't have this
4446 * and don't wait for vblanks until the end of crtc_enable, then
4447 * the HW state readout code will complain that the expected
4448 * IPS_CTL value is not the one we read. */
4449 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4450 DRM_ERROR("Timed out waiting for IPS enable\n");
4451 }
4452 }
4453
4454 void hsw_disable_ips(struct intel_crtc *crtc)
4455 {
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458
4459 if (!crtc->config->ips_enabled)
4460 return;
4461
4462 assert_plane_enabled(dev_priv, crtc->plane);
4463 if (IS_BROADWELL(dev)) {
4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4468 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4469 DRM_ERROR("Timed out waiting for IPS disable\n");
4470 } else {
4471 I915_WRITE(IPS_CTL, 0);
4472 POSTING_READ(IPS_CTL);
4473 }
4474
4475 /* We need to wait for a vblank before we can disable the plane. */
4476 intel_wait_for_vblank(dev, crtc->pipe);
4477 }
4478
4479 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4480 {
4481 if (intel_crtc->overlay) {
4482 struct drm_device *dev = intel_crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484
4485 mutex_lock(&dev->struct_mutex);
4486 dev_priv->mm.interruptible = false;
4487 (void) intel_overlay_switch_off(intel_crtc->overlay);
4488 dev_priv->mm.interruptible = true;
4489 mutex_unlock(&dev->struct_mutex);
4490 }
4491
4492 /* Let userspace switch the overlay on again. In most cases userspace
4493 * has to recompute where to put it anyway.
4494 */
4495 }
4496
4497 /**
4498 * intel_post_enable_primary - Perform operations after enabling primary plane
4499 * @crtc: the CRTC whose primary plane was just enabled
4500 *
4501 * Performs potentially sleeping operations that must be done after the primary
4502 * plane is enabled, such as updating FBC and IPS. Note that this may be
4503 * called due to an explicit primary plane update, or due to an implicit
4504 * re-enable that is caused when a sprite plane is updated to no longer
4505 * completely hide the primary plane.
4506 */
4507 static void
4508 intel_post_enable_primary(struct drm_crtc *crtc)
4509 {
4510 struct drm_device *dev = crtc->dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4513 int pipe = intel_crtc->pipe;
4514
4515 /*
4516 * FIXME IPS should be fine as long as one plane is
4517 * enabled, but in practice it seems to have problems
4518 * when going from primary only to sprite only and vice
4519 * versa.
4520 */
4521 hsw_enable_ips(intel_crtc);
4522
4523 /*
4524 * Gen2 reports pipe underruns whenever all planes are disabled.
4525 * So don't enable underrun reporting before at least some planes
4526 * are enabled.
4527 * FIXME: Need to fix the logic to work when we turn off all planes
4528 * but leave the pipe running.
4529 */
4530 if (IS_GEN2(dev))
4531 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4532
4533 /* Underruns don't always raise interrupts, so check manually. */
4534 intel_check_cpu_fifo_underruns(dev_priv);
4535 intel_check_pch_fifo_underruns(dev_priv);
4536 }
4537
4538 /* FIXME move all this to pre_plane_update() with proper state tracking */
4539 static void
4540 intel_pre_disable_primary(struct drm_crtc *crtc)
4541 {
4542 struct drm_device *dev = crtc->dev;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4545 int pipe = intel_crtc->pipe;
4546
4547 /*
4548 * Gen2 reports pipe underruns whenever all planes are disabled.
4549 * So diasble underrun reporting before all the planes get disabled.
4550 * FIXME: Need to fix the logic to work when we turn off all planes
4551 * but leave the pipe running.
4552 */
4553 if (IS_GEN2(dev))
4554 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 /*
4557 * FIXME IPS should be fine as long as one plane is
4558 * enabled, but in practice it seems to have problems
4559 * when going from primary only to sprite only and vice
4560 * versa.
4561 */
4562 hsw_disable_ips(intel_crtc);
4563 }
4564
4565 /* FIXME get rid of this and use pre_plane_update */
4566 static void
4567 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe;
4573
4574 intel_pre_disable_primary(crtc);
4575
4576 /*
4577 * Vblank time updates from the shadow to live plane control register
4578 * are blocked if the memory self-refresh mode is active at that
4579 * moment. So to make sure the plane gets truly disabled, disable
4580 * first the self-refresh mode. The self-refresh enable bit in turn
4581 * will be checked/applied by the HW only at the next frame start
4582 * event which is after the vblank start event, so we need to have a
4583 * wait-for-vblank between disabling the plane and the pipe.
4584 */
4585 if (HAS_GMCH_DISPLAY(dev)) {
4586 intel_set_memory_cxsr(dev_priv, false);
4587 dev_priv->wm.vlv.cxsr = false;
4588 intel_wait_for_vblank(dev, pipe);
4589 }
4590 }
4591
4592 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4593 {
4594 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4595 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4596 struct intel_crtc_state *pipe_config =
4597 to_intel_crtc_state(crtc->base.state);
4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_plane *primary = crtc->base.primary;
4600 struct drm_plane_state *old_pri_state =
4601 drm_atomic_get_existing_plane_state(old_state, primary);
4602
4603 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4604
4605 crtc->wm.cxsr_allowed = true;
4606
4607 if (pipe_config->update_wm_post && pipe_config->base.active)
4608 intel_update_watermarks(&crtc->base);
4609
4610 if (old_pri_state) {
4611 struct intel_plane_state *primary_state =
4612 to_intel_plane_state(primary->state);
4613 struct intel_plane_state *old_primary_state =
4614 to_intel_plane_state(old_pri_state);
4615
4616 intel_fbc_post_update(crtc);
4617
4618 if (primary_state->visible &&
4619 (needs_modeset(&pipe_config->base) ||
4620 !old_primary_state->visible))
4621 intel_post_enable_primary(&crtc->base);
4622 }
4623 }
4624
4625 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4626 {
4627 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc_state *pipe_config =
4631 to_intel_crtc_state(crtc->base.state);
4632 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4633 struct drm_plane *primary = crtc->base.primary;
4634 struct drm_plane_state *old_pri_state =
4635 drm_atomic_get_existing_plane_state(old_state, primary);
4636 bool modeset = needs_modeset(&pipe_config->base);
4637
4638 if (old_pri_state) {
4639 struct intel_plane_state *primary_state =
4640 to_intel_plane_state(primary->state);
4641 struct intel_plane_state *old_primary_state =
4642 to_intel_plane_state(old_pri_state);
4643
4644 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4645
4646 if (old_primary_state->visible &&
4647 (modeset || !primary_state->visible))
4648 intel_pre_disable_primary(&crtc->base);
4649 }
4650
4651 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
4652 crtc->wm.cxsr_allowed = false;
4653
4654 /*
4655 * Vblank time updates from the shadow to live plane control register
4656 * are blocked if the memory self-refresh mode is active at that
4657 * moment. So to make sure the plane gets truly disabled, disable
4658 * first the self-refresh mode. The self-refresh enable bit in turn
4659 * will be checked/applied by the HW only at the next frame start
4660 * event which is after the vblank start event, so we need to have a
4661 * wait-for-vblank between disabling the plane and the pipe.
4662 */
4663 if (old_crtc_state->base.active) {
4664 intel_set_memory_cxsr(dev_priv, false);
4665 dev_priv->wm.vlv.cxsr = false;
4666 intel_wait_for_vblank(dev, crtc->pipe);
4667 }
4668 }
4669
4670 /*
4671 * IVB workaround: must disable low power watermarks for at least
4672 * one frame before enabling scaling. LP watermarks can be re-enabled
4673 * when scaling is disabled.
4674 *
4675 * WaCxSRDisabledForSpriteScaling:ivb
4676 */
4677 if (pipe_config->disable_lp_wm) {
4678 ilk_disable_lp_wm(dev);
4679 intel_wait_for_vblank(dev, crtc->pipe);
4680 }
4681
4682 /*
4683 * If we're doing a modeset, we're done. No need to do any pre-vblank
4684 * watermark programming here.
4685 */
4686 if (needs_modeset(&pipe_config->base))
4687 return;
4688
4689 /*
4690 * For platforms that support atomic watermarks, program the
4691 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4692 * will be the intermediate values that are safe for both pre- and
4693 * post- vblank; when vblank happens, the 'active' values will be set
4694 * to the final 'target' values and we'll do this again to get the
4695 * optimal watermarks. For gen9+ platforms, the values we program here
4696 * will be the final target values which will get automatically latched
4697 * at vblank time; no further programming will be necessary.
4698 *
4699 * If a platform hasn't been transitioned to atomic watermarks yet,
4700 * we'll continue to update watermarks the old way, if flags tell
4701 * us to.
4702 */
4703 if (dev_priv->display.initial_watermarks != NULL)
4704 dev_priv->display.initial_watermarks(pipe_config);
4705 else if (pipe_config->update_wm_pre)
4706 intel_update_watermarks(&crtc->base);
4707 }
4708
4709 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4710 {
4711 struct drm_device *dev = crtc->dev;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct drm_plane *p;
4714 int pipe = intel_crtc->pipe;
4715
4716 intel_crtc_dpms_overlay_disable(intel_crtc);
4717
4718 drm_for_each_plane_mask(p, dev, plane_mask)
4719 to_intel_plane(p)->disable_plane(p, crtc);
4720
4721 /*
4722 * FIXME: Once we grow proper nuclear flip support out of this we need
4723 * to compute the mask of flip planes precisely. For the time being
4724 * consider this a flip to a NULL plane.
4725 */
4726 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4727 }
4728
4729 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 struct intel_encoder *encoder;
4735 int pipe = intel_crtc->pipe;
4736 struct intel_crtc_state *pipe_config =
4737 to_intel_crtc_state(crtc->state);
4738
4739 if (WARN_ON(intel_crtc->active))
4740 return;
4741
4742 /*
4743 * Sometimes spurious CPU pipe underruns happen during FDI
4744 * training, at least with VGA+HDMI cloning. Suppress them.
4745 *
4746 * On ILK we get an occasional spurious CPU pipe underruns
4747 * between eDP port A enable and vdd enable. Also PCH port
4748 * enable seems to result in the occasional CPU pipe underrun.
4749 *
4750 * Spurious PCH underruns also occur during PCH enabling.
4751 */
4752 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4753 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 if (intel_crtc->config->has_pch_encoder)
4758 intel_prepare_shared_dpll(intel_crtc);
4759
4760 if (intel_crtc->config->has_dp_encoder)
4761 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763 intel_set_pipe_timings(intel_crtc);
4764 intel_set_pipe_src_size(intel_crtc);
4765
4766 if (intel_crtc->config->has_pch_encoder) {
4767 intel_cpu_transcoder_set_m_n(intel_crtc,
4768 &intel_crtc->config->fdi_m_n, NULL);
4769 }
4770
4771 ironlake_set_pipeconf(crtc);
4772
4773 intel_crtc->active = true;
4774
4775 for_each_encoder_on_crtc(dev, crtc, encoder)
4776 if (encoder->pre_enable)
4777 encoder->pre_enable(encoder);
4778
4779 if (intel_crtc->config->has_pch_encoder) {
4780 /* Note: FDI PLL enabling _must_ be done before we enable the
4781 * cpu pipes, hence this is separate from all the other fdi/pch
4782 * enabling. */
4783 ironlake_fdi_pll_enable(intel_crtc);
4784 } else {
4785 assert_fdi_tx_disabled(dev_priv, pipe);
4786 assert_fdi_rx_disabled(dev_priv, pipe);
4787 }
4788
4789 ironlake_pfit_enable(intel_crtc);
4790
4791 /*
4792 * On ILK+ LUT must be loaded before the pipe is running but with
4793 * clocks enabled
4794 */
4795 intel_color_load_luts(&pipe_config->base);
4796
4797 if (dev_priv->display.initial_watermarks != NULL)
4798 dev_priv->display.initial_watermarks(intel_crtc->config);
4799 intel_enable_pipe(intel_crtc);
4800
4801 if (intel_crtc->config->has_pch_encoder)
4802 ironlake_pch_enable(crtc);
4803
4804 assert_vblank_disabled(crtc);
4805 drm_crtc_vblank_on(crtc);
4806
4807 for_each_encoder_on_crtc(dev, crtc, encoder)
4808 encoder->enable(encoder);
4809
4810 if (HAS_PCH_CPT(dev))
4811 cpt_verify_modeset(dev, intel_crtc->pipe);
4812
4813 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4814 if (intel_crtc->config->has_pch_encoder)
4815 intel_wait_for_vblank(dev, pipe);
4816 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4817 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4818 }
4819
4820 /* IPS only exists on ULT machines and is tied to pipe A. */
4821 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4822 {
4823 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4824 }
4825
4826 static void haswell_crtc_enable(struct drm_crtc *crtc)
4827 {
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4831 struct intel_encoder *encoder;
4832 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4833 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4834 struct intel_crtc_state *pipe_config =
4835 to_intel_crtc_state(crtc->state);
4836
4837 if (WARN_ON(intel_crtc->active))
4838 return;
4839
4840 if (intel_crtc->config->has_pch_encoder)
4841 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4842 false);
4843
4844 for_each_encoder_on_crtc(dev, crtc, encoder)
4845 if (encoder->pre_pll_enable)
4846 encoder->pre_pll_enable(encoder);
4847
4848 if (intel_crtc->config->shared_dpll)
4849 intel_enable_shared_dpll(intel_crtc);
4850
4851 if (intel_crtc->config->has_dp_encoder)
4852 intel_dp_set_m_n(intel_crtc, M1_N1);
4853
4854 if (!intel_crtc->config->has_dsi_encoder)
4855 intel_set_pipe_timings(intel_crtc);
4856
4857 intel_set_pipe_src_size(intel_crtc);
4858
4859 if (cpu_transcoder != TRANSCODER_EDP &&
4860 !transcoder_is_dsi(cpu_transcoder)) {
4861 I915_WRITE(PIPE_MULT(cpu_transcoder),
4862 intel_crtc->config->pixel_multiplier - 1);
4863 }
4864
4865 if (intel_crtc->config->has_pch_encoder) {
4866 intel_cpu_transcoder_set_m_n(intel_crtc,
4867 &intel_crtc->config->fdi_m_n, NULL);
4868 }
4869
4870 if (!intel_crtc->config->has_dsi_encoder)
4871 haswell_set_pipeconf(crtc);
4872
4873 haswell_set_pipemisc(crtc);
4874
4875 intel_color_set_csc(&pipe_config->base);
4876
4877 intel_crtc->active = true;
4878
4879 if (intel_crtc->config->has_pch_encoder)
4880 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4881 else
4882 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4883
4884 for_each_encoder_on_crtc(dev, crtc, encoder) {
4885 if (encoder->pre_enable)
4886 encoder->pre_enable(encoder);
4887 }
4888
4889 if (intel_crtc->config->has_pch_encoder)
4890 dev_priv->display.fdi_link_train(crtc);
4891
4892 if (!intel_crtc->config->has_dsi_encoder)
4893 intel_ddi_enable_pipe_clock(intel_crtc);
4894
4895 if (INTEL_INFO(dev)->gen >= 9)
4896 skylake_pfit_enable(intel_crtc);
4897 else
4898 ironlake_pfit_enable(intel_crtc);
4899
4900 /*
4901 * On ILK+ LUT must be loaded before the pipe is running but with
4902 * clocks enabled
4903 */
4904 intel_color_load_luts(&pipe_config->base);
4905
4906 intel_ddi_set_pipe_settings(crtc);
4907 if (!intel_crtc->config->has_dsi_encoder)
4908 intel_ddi_enable_transcoder_func(crtc);
4909
4910 if (dev_priv->display.initial_watermarks != NULL)
4911 dev_priv->display.initial_watermarks(pipe_config);
4912 else
4913 intel_update_watermarks(crtc);
4914
4915 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4916 if (!intel_crtc->config->has_dsi_encoder)
4917 intel_enable_pipe(intel_crtc);
4918
4919 if (intel_crtc->config->has_pch_encoder)
4920 lpt_pch_enable(crtc);
4921
4922 if (intel_crtc->config->dp_encoder_is_mst)
4923 intel_ddi_set_vc_payload_alloc(crtc, true);
4924
4925 assert_vblank_disabled(crtc);
4926 drm_crtc_vblank_on(crtc);
4927
4928 for_each_encoder_on_crtc(dev, crtc, encoder) {
4929 encoder->enable(encoder);
4930 intel_opregion_notify_encoder(encoder, true);
4931 }
4932
4933 if (intel_crtc->config->has_pch_encoder) {
4934 intel_wait_for_vblank(dev, pipe);
4935 intel_wait_for_vblank(dev, pipe);
4936 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4937 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4938 true);
4939 }
4940
4941 /* If we change the relative order between pipe/planes enabling, we need
4942 * to change the workaround. */
4943 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4944 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4945 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4946 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4947 }
4948 }
4949
4950 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4951 {
4952 struct drm_device *dev = crtc->base.dev;
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4954 int pipe = crtc->pipe;
4955
4956 /* To avoid upsetting the power well on haswell only disable the pfit if
4957 * it's in use. The hw state code will make sure we get this right. */
4958 if (force || crtc->config->pch_pfit.enabled) {
4959 I915_WRITE(PF_CTL(pipe), 0);
4960 I915_WRITE(PF_WIN_POS(pipe), 0);
4961 I915_WRITE(PF_WIN_SZ(pipe), 0);
4962 }
4963 }
4964
4965 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4966 {
4967 struct drm_device *dev = crtc->dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970 struct intel_encoder *encoder;
4971 int pipe = intel_crtc->pipe;
4972
4973 /*
4974 * Sometimes spurious CPU pipe underruns happen when the
4975 * pipe is already disabled, but FDI RX/TX is still enabled.
4976 * Happens at least with VGA+HDMI cloning. Suppress them.
4977 */
4978 if (intel_crtc->config->has_pch_encoder) {
4979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4980 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4981 }
4982
4983 for_each_encoder_on_crtc(dev, crtc, encoder)
4984 encoder->disable(encoder);
4985
4986 drm_crtc_vblank_off(crtc);
4987 assert_vblank_disabled(crtc);
4988
4989 intel_disable_pipe(intel_crtc);
4990
4991 ironlake_pfit_disable(intel_crtc, false);
4992
4993 if (intel_crtc->config->has_pch_encoder)
4994 ironlake_fdi_disable(crtc);
4995
4996 for_each_encoder_on_crtc(dev, crtc, encoder)
4997 if (encoder->post_disable)
4998 encoder->post_disable(encoder);
4999
5000 if (intel_crtc->config->has_pch_encoder) {
5001 ironlake_disable_pch_transcoder(dev_priv, pipe);
5002
5003 if (HAS_PCH_CPT(dev)) {
5004 i915_reg_t reg;
5005 u32 temp;
5006
5007 /* disable TRANS_DP_CTL */
5008 reg = TRANS_DP_CTL(pipe);
5009 temp = I915_READ(reg);
5010 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5011 TRANS_DP_PORT_SEL_MASK);
5012 temp |= TRANS_DP_PORT_SEL_NONE;
5013 I915_WRITE(reg, temp);
5014
5015 /* disable DPLL_SEL */
5016 temp = I915_READ(PCH_DPLL_SEL);
5017 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5018 I915_WRITE(PCH_DPLL_SEL, temp);
5019 }
5020
5021 ironlake_fdi_pll_disable(intel_crtc);
5022 }
5023
5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5026 }
5027
5028 static void haswell_crtc_disable(struct drm_crtc *crtc)
5029 {
5030 struct drm_device *dev = crtc->dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033 struct intel_encoder *encoder;
5034 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5035
5036 if (intel_crtc->config->has_pch_encoder)
5037 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5038 false);
5039
5040 for_each_encoder_on_crtc(dev, crtc, encoder) {
5041 intel_opregion_notify_encoder(encoder, false);
5042 encoder->disable(encoder);
5043 }
5044
5045 drm_crtc_vblank_off(crtc);
5046 assert_vblank_disabled(crtc);
5047
5048 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5049 if (!intel_crtc->config->has_dsi_encoder)
5050 intel_disable_pipe(intel_crtc);
5051
5052 if (intel_crtc->config->dp_encoder_is_mst)
5053 intel_ddi_set_vc_payload_alloc(crtc, false);
5054
5055 if (!intel_crtc->config->has_dsi_encoder)
5056 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5057
5058 if (INTEL_INFO(dev)->gen >= 9)
5059 skylake_scaler_disable(intel_crtc);
5060 else
5061 ironlake_pfit_disable(intel_crtc, false);
5062
5063 if (!intel_crtc->config->has_dsi_encoder)
5064 intel_ddi_disable_pipe_clock(intel_crtc);
5065
5066 for_each_encoder_on_crtc(dev, crtc, encoder)
5067 if (encoder->post_disable)
5068 encoder->post_disable(encoder);
5069
5070 if (intel_crtc->config->has_pch_encoder) {
5071 lpt_disable_pch_transcoder(dev_priv);
5072 lpt_disable_iclkip(dev_priv);
5073 intel_ddi_fdi_disable(crtc);
5074
5075 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5076 true);
5077 }
5078 }
5079
5080 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5081 {
5082 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 struct intel_crtc_state *pipe_config = crtc->config;
5085
5086 if (!pipe_config->gmch_pfit.control)
5087 return;
5088
5089 /*
5090 * The panel fitter should only be adjusted whilst the pipe is disabled,
5091 * according to register description and PRM.
5092 */
5093 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5094 assert_pipe_disabled(dev_priv, crtc->pipe);
5095
5096 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5097 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5098
5099 /* Border color in case we don't scale up to the full screen. Black by
5100 * default, change to something else for debugging. */
5101 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5102 }
5103
5104 static enum intel_display_power_domain port_to_power_domain(enum port port)
5105 {
5106 switch (port) {
5107 case PORT_A:
5108 return POWER_DOMAIN_PORT_DDI_A_LANES;
5109 case PORT_B:
5110 return POWER_DOMAIN_PORT_DDI_B_LANES;
5111 case PORT_C:
5112 return POWER_DOMAIN_PORT_DDI_C_LANES;
5113 case PORT_D:
5114 return POWER_DOMAIN_PORT_DDI_D_LANES;
5115 case PORT_E:
5116 return POWER_DOMAIN_PORT_DDI_E_LANES;
5117 default:
5118 MISSING_CASE(port);
5119 return POWER_DOMAIN_PORT_OTHER;
5120 }
5121 }
5122
5123 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5124 {
5125 switch (port) {
5126 case PORT_A:
5127 return POWER_DOMAIN_AUX_A;
5128 case PORT_B:
5129 return POWER_DOMAIN_AUX_B;
5130 case PORT_C:
5131 return POWER_DOMAIN_AUX_C;
5132 case PORT_D:
5133 return POWER_DOMAIN_AUX_D;
5134 case PORT_E:
5135 /* FIXME: Check VBT for actual wiring of PORT E */
5136 return POWER_DOMAIN_AUX_D;
5137 default:
5138 MISSING_CASE(port);
5139 return POWER_DOMAIN_AUX_A;
5140 }
5141 }
5142
5143 enum intel_display_power_domain
5144 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5145 {
5146 struct drm_device *dev = intel_encoder->base.dev;
5147 struct intel_digital_port *intel_dig_port;
5148
5149 switch (intel_encoder->type) {
5150 case INTEL_OUTPUT_UNKNOWN:
5151 /* Only DDI platforms should ever use this output type */
5152 WARN_ON_ONCE(!HAS_DDI(dev));
5153 case INTEL_OUTPUT_DISPLAYPORT:
5154 case INTEL_OUTPUT_HDMI:
5155 case INTEL_OUTPUT_EDP:
5156 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5157 return port_to_power_domain(intel_dig_port->port);
5158 case INTEL_OUTPUT_DP_MST:
5159 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5160 return port_to_power_domain(intel_dig_port->port);
5161 case INTEL_OUTPUT_ANALOG:
5162 return POWER_DOMAIN_PORT_CRT;
5163 case INTEL_OUTPUT_DSI:
5164 return POWER_DOMAIN_PORT_DSI;
5165 default:
5166 return POWER_DOMAIN_PORT_OTHER;
5167 }
5168 }
5169
5170 enum intel_display_power_domain
5171 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5172 {
5173 struct drm_device *dev = intel_encoder->base.dev;
5174 struct intel_digital_port *intel_dig_port;
5175
5176 switch (intel_encoder->type) {
5177 case INTEL_OUTPUT_UNKNOWN:
5178 case INTEL_OUTPUT_HDMI:
5179 /*
5180 * Only DDI platforms should ever use these output types.
5181 * We can get here after the HDMI detect code has already set
5182 * the type of the shared encoder. Since we can't be sure
5183 * what's the status of the given connectors, play safe and
5184 * run the DP detection too.
5185 */
5186 WARN_ON_ONCE(!HAS_DDI(dev));
5187 case INTEL_OUTPUT_DISPLAYPORT:
5188 case INTEL_OUTPUT_EDP:
5189 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5190 return port_to_aux_power_domain(intel_dig_port->port);
5191 case INTEL_OUTPUT_DP_MST:
5192 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5193 return port_to_aux_power_domain(intel_dig_port->port);
5194 default:
5195 MISSING_CASE(intel_encoder->type);
5196 return POWER_DOMAIN_AUX_A;
5197 }
5198 }
5199
5200 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5201 struct intel_crtc_state *crtc_state)
5202 {
5203 struct drm_device *dev = crtc->dev;
5204 struct drm_encoder *encoder;
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 enum pipe pipe = intel_crtc->pipe;
5207 unsigned long mask;
5208 enum transcoder transcoder = crtc_state->cpu_transcoder;
5209
5210 if (!crtc_state->base.active)
5211 return 0;
5212
5213 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5214 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5215 if (crtc_state->pch_pfit.enabled ||
5216 crtc_state->pch_pfit.force_thru)
5217 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5218
5219 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5220 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5221
5222 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5223 }
5224
5225 if (crtc_state->shared_dpll)
5226 mask |= BIT(POWER_DOMAIN_PLLS);
5227
5228 return mask;
5229 }
5230
5231 static unsigned long
5232 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5233 struct intel_crtc_state *crtc_state)
5234 {
5235 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 enum intel_display_power_domain domain;
5238 unsigned long domains, new_domains, old_domains;
5239
5240 old_domains = intel_crtc->enabled_power_domains;
5241 intel_crtc->enabled_power_domains = new_domains =
5242 get_crtc_power_domains(crtc, crtc_state);
5243
5244 domains = new_domains & ~old_domains;
5245
5246 for_each_power_domain(domain, domains)
5247 intel_display_power_get(dev_priv, domain);
5248
5249 return old_domains & ~new_domains;
5250 }
5251
5252 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5253 unsigned long domains)
5254 {
5255 enum intel_display_power_domain domain;
5256
5257 for_each_power_domain(domain, domains)
5258 intel_display_power_put(dev_priv, domain);
5259 }
5260
5261 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5262 {
5263 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5264
5265 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5266 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5267 return max_cdclk_freq;
5268 else if (IS_CHERRYVIEW(dev_priv))
5269 return max_cdclk_freq*95/100;
5270 else if (INTEL_INFO(dev_priv)->gen < 4)
5271 return 2*max_cdclk_freq*90/100;
5272 else
5273 return max_cdclk_freq*90/100;
5274 }
5275
5276 static int skl_calc_cdclk(int max_pixclk, int vco);
5277
5278 static void intel_update_max_cdclk(struct drm_device *dev)
5279 {
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281
5282 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5283 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5284 int max_cdclk, vco;
5285
5286 vco = dev_priv->skl_preferred_vco_freq;
5287 WARN_ON(vco != 8100000 && vco != 8640000);
5288
5289 /*
5290 * Use the lower (vco 8640) cdclk values as a
5291 * first guess. skl_calc_cdclk() will correct it
5292 * if the preferred vco is 8100 instead.
5293 */
5294 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5295 max_cdclk = 617143;
5296 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5297 max_cdclk = 540000;
5298 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5299 max_cdclk = 432000;
5300 else
5301 max_cdclk = 308571;
5302
5303 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5304 } else if (IS_BROXTON(dev)) {
5305 dev_priv->max_cdclk_freq = 624000;
5306 } else if (IS_BROADWELL(dev)) {
5307 /*
5308 * FIXME with extra cooling we can allow
5309 * 540 MHz for ULX and 675 Mhz for ULT.
5310 * How can we know if extra cooling is
5311 * available? PCI ID, VTB, something else?
5312 */
5313 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5314 dev_priv->max_cdclk_freq = 450000;
5315 else if (IS_BDW_ULX(dev))
5316 dev_priv->max_cdclk_freq = 450000;
5317 else if (IS_BDW_ULT(dev))
5318 dev_priv->max_cdclk_freq = 540000;
5319 else
5320 dev_priv->max_cdclk_freq = 675000;
5321 } else if (IS_CHERRYVIEW(dev)) {
5322 dev_priv->max_cdclk_freq = 320000;
5323 } else if (IS_VALLEYVIEW(dev)) {
5324 dev_priv->max_cdclk_freq = 400000;
5325 } else {
5326 /* otherwise assume cdclk is fixed */
5327 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5328 }
5329
5330 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5331
5332 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5333 dev_priv->max_cdclk_freq);
5334
5335 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5336 dev_priv->max_dotclk_freq);
5337 }
5338
5339 static void intel_update_cdclk(struct drm_device *dev)
5340 {
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5344
5345 if (INTEL_GEN(dev_priv) >= 9)
5346 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5347 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5348 dev_priv->cdclk_pll.ref);
5349 else
5350 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5351 dev_priv->cdclk_freq);
5352
5353 /*
5354 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5355 * Programmng [sic] note: bit[9:2] should be programmed to the number
5356 * of cdclk that generates 4MHz reference clock freq which is used to
5357 * generate GMBus clock. This will vary with the cdclk freq.
5358 */
5359 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5360 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5361 }
5362
5363 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5364 static int skl_cdclk_decimal(int cdclk)
5365 {
5366 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5367 }
5368
5369 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5370 {
5371 int ratio;
5372
5373 if (cdclk == dev_priv->cdclk_pll.ref)
5374 return 0;
5375
5376 switch (cdclk) {
5377 default:
5378 MISSING_CASE(cdclk);
5379 case 144000:
5380 case 288000:
5381 case 384000:
5382 case 576000:
5383 ratio = 60;
5384 break;
5385 case 624000:
5386 ratio = 65;
5387 break;
5388 }
5389
5390 return dev_priv->cdclk_pll.ref * ratio;
5391 }
5392
5393 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5394 {
5395 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5396
5397 /* Timeout 200us */
5398 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5399 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5400
5401 dev_priv->cdclk_pll.vco = 0;
5402 }
5403
5404 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5405 {
5406 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5407 u32 val;
5408
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5411 val |= BXT_DE_PLL_RATIO(ratio);
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415
5416 /* Timeout 200us */
5417 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5418 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419
5420 dev_priv->cdclk_pll.vco = vco;
5421 }
5422
5423 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5424 {
5425 u32 val, divider;
5426 int vco, ret;
5427
5428 vco = bxt_de_pll_vco(dev_priv, cdclk);
5429
5430 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5431
5432 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5433 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5434 case 8:
5435 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5436 break;
5437 case 4:
5438 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5439 break;
5440 case 3:
5441 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5442 break;
5443 case 2:
5444 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5445 break;
5446 default:
5447 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
5448 WARN_ON(vco != 0);
5449
5450 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5451 break;
5452 }
5453
5454 /* Inform power controller of upcoming frequency change */
5455 mutex_lock(&dev_priv->rps.hw_lock);
5456 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5457 0x80000000);
5458 mutex_unlock(&dev_priv->rps.hw_lock);
5459
5460 if (ret) {
5461 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5462 ret, cdclk);
5463 return;
5464 }
5465
5466 if (dev_priv->cdclk_pll.vco != 0 &&
5467 dev_priv->cdclk_pll.vco != vco)
5468 bxt_de_pll_disable(dev_priv);
5469
5470 if (dev_priv->cdclk_pll.vco != vco)
5471 bxt_de_pll_enable(dev_priv, vco);
5472
5473 val = divider | skl_cdclk_decimal(cdclk);
5474 /*
5475 * FIXME if only the cd2x divider needs changing, it could be done
5476 * without shutting off the pipe (if only one pipe is active).
5477 */
5478 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5479 /*
5480 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5481 * enable otherwise.
5482 */
5483 if (cdclk >= 500000)
5484 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5485 I915_WRITE(CDCLK_CTL, val);
5486
5487 mutex_lock(&dev_priv->rps.hw_lock);
5488 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5489 DIV_ROUND_UP(cdclk, 25000));
5490 mutex_unlock(&dev_priv->rps.hw_lock);
5491
5492 if (ret) {
5493 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5494 ret, cdclk);
5495 return;
5496 }
5497
5498 intel_update_cdclk(dev_priv->dev);
5499 }
5500
5501 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
5502 {
5503 u32 cdctl, expected;
5504
5505 intel_update_cdclk(dev_priv->dev);
5506
5507 if (dev_priv->cdclk_pll.vco == 0 ||
5508 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5509 goto sanitize;
5510
5511 /* DPLL okay; verify the cdclock
5512 *
5513 * Some BIOS versions leave an incorrect decimal frequency value and
5514 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
5515 * so sanitize this register.
5516 */
5517 cdctl = I915_READ(CDCLK_CTL);
5518 /*
5519 * Let's ignore the pipe field, since BIOS could have configured the
5520 * dividers both synching to an active pipe, or asynchronously
5521 * (PIPE_NONE).
5522 */
5523 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
5524
5525 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
5526 skl_cdclk_decimal(dev_priv->cdclk_freq);
5527 /*
5528 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5529 * enable otherwise.
5530 */
5531 if (dev_priv->cdclk_freq >= 500000)
5532 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5533
5534 if (cdctl == expected)
5535 /* All well; nothing to sanitize */
5536 return;
5537
5538 sanitize:
5539 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5540
5541 /* force cdclk programming */
5542 dev_priv->cdclk_freq = 0;
5543
5544 /* force full PLL disable + enable */
5545 dev_priv->cdclk_pll.vco = -1;
5546 }
5547
5548 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
5549 {
5550 bxt_sanitize_cdclk(dev_priv);
5551
5552 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
5553 return;
5554
5555 /*
5556 * FIXME:
5557 * - The initial CDCLK needs to be read from VBT.
5558 * Need to make this change after VBT has changes for BXT.
5559 */
5560 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
5561 }
5562
5563 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
5564 {
5565 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
5566 }
5567
5568 static int skl_calc_cdclk(int max_pixclk, int vco)
5569 {
5570 if (vco == 8640000) {
5571 if (max_pixclk > 540000)
5572 return 617143;
5573 else if (max_pixclk > 432000)
5574 return 540000;
5575 else if (max_pixclk > 308571)
5576 return 432000;
5577 else
5578 return 308571;
5579 } else {
5580 if (max_pixclk > 540000)
5581 return 675000;
5582 else if (max_pixclk > 450000)
5583 return 540000;
5584 else if (max_pixclk > 337500)
5585 return 450000;
5586 else
5587 return 337500;
5588 }
5589 }
5590
5591 static void
5592 skl_dpll0_update(struct drm_i915_private *dev_priv)
5593 {
5594 u32 val;
5595
5596 dev_priv->cdclk_pll.ref = 24000;
5597 dev_priv->cdclk_pll.vco = 0;
5598
5599 val = I915_READ(LCPLL1_CTL);
5600 if ((val & LCPLL_PLL_ENABLE) == 0)
5601 return;
5602
5603 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
5604 return;
5605
5606 val = I915_READ(DPLL_CTRL1);
5607
5608 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5609 DPLL_CTRL1_SSC(SKL_DPLL0) |
5610 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5611 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
5612 return;
5613
5614 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5615 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5616 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5617 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5618 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5619 dev_priv->cdclk_pll.vco = 8100000;
5620 break;
5621 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5622 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5623 dev_priv->cdclk_pll.vco = 8640000;
5624 break;
5625 default:
5626 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5627 break;
5628 }
5629 }
5630
5631 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5632 {
5633 bool changed = dev_priv->skl_preferred_vco_freq != vco;
5634
5635 dev_priv->skl_preferred_vco_freq = vco;
5636
5637 if (changed)
5638 intel_update_max_cdclk(dev_priv->dev);
5639 }
5640
5641 static void
5642 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5643 {
5644 int min_cdclk = skl_calc_cdclk(0, vco);
5645 u32 val;
5646
5647 WARN_ON(vco != 8100000 && vco != 8640000);
5648
5649 /* select the minimum CDCLK before enabling DPLL 0 */
5650 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5651 I915_WRITE(CDCLK_CTL, val);
5652 POSTING_READ(CDCLK_CTL);
5653
5654 /*
5655 * We always enable DPLL0 with the lowest link rate possible, but still
5656 * taking into account the VCO required to operate the eDP panel at the
5657 * desired frequency. The usual DP link rates operate with a VCO of
5658 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5659 * The modeset code is responsible for the selection of the exact link
5660 * rate later on, with the constraint of choosing a frequency that
5661 * works with vco.
5662 */
5663 val = I915_READ(DPLL_CTRL1);
5664
5665 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5666 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5667 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5668 if (vco == 8640000)
5669 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5670 SKL_DPLL0);
5671 else
5672 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5673 SKL_DPLL0);
5674
5675 I915_WRITE(DPLL_CTRL1, val);
5676 POSTING_READ(DPLL_CTRL1);
5677
5678 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5679
5680 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5681 DRM_ERROR("DPLL0 not locked\n");
5682
5683 dev_priv->cdclk_pll.vco = vco;
5684
5685 /* We'll want to keep using the current vco from now on. */
5686 skl_set_preferred_cdclk_vco(dev_priv, vco);
5687 }
5688
5689 static void
5690 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5691 {
5692 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5693 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5694 DRM_ERROR("Couldn't disable DPLL0\n");
5695
5696 dev_priv->cdclk_pll.vco = 0;
5697 }
5698
5699 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5700 {
5701 int ret;
5702 u32 val;
5703
5704 /* inform PCU we want to change CDCLK */
5705 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5706 mutex_lock(&dev_priv->rps.hw_lock);
5707 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5708 mutex_unlock(&dev_priv->rps.hw_lock);
5709
5710 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5711 }
5712
5713 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5714 {
5715 unsigned int i;
5716
5717 for (i = 0; i < 15; i++) {
5718 if (skl_cdclk_pcu_ready(dev_priv))
5719 return true;
5720 udelay(10);
5721 }
5722
5723 return false;
5724 }
5725
5726 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5727 {
5728 struct drm_device *dev = dev_priv->dev;
5729 u32 freq_select, pcu_ack;
5730
5731 WARN_ON((cdclk == 24000) != (vco == 0));
5732
5733 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5734
5735 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5736 DRM_ERROR("failed to inform PCU about cdclk change\n");
5737 return;
5738 }
5739
5740 /* set CDCLK_CTL */
5741 switch (cdclk) {
5742 case 450000:
5743 case 432000:
5744 freq_select = CDCLK_FREQ_450_432;
5745 pcu_ack = 1;
5746 break;
5747 case 540000:
5748 freq_select = CDCLK_FREQ_540;
5749 pcu_ack = 2;
5750 break;
5751 case 308571:
5752 case 337500:
5753 default:
5754 freq_select = CDCLK_FREQ_337_308;
5755 pcu_ack = 0;
5756 break;
5757 case 617143:
5758 case 675000:
5759 freq_select = CDCLK_FREQ_675_617;
5760 pcu_ack = 3;
5761 break;
5762 }
5763
5764 if (dev_priv->cdclk_pll.vco != 0 &&
5765 dev_priv->cdclk_pll.vco != vco)
5766 skl_dpll0_disable(dev_priv);
5767
5768 if (dev_priv->cdclk_pll.vco != vco)
5769 skl_dpll0_enable(dev_priv, vco);
5770
5771 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5772 POSTING_READ(CDCLK_CTL);
5773
5774 /* inform PCU of the change */
5775 mutex_lock(&dev_priv->rps.hw_lock);
5776 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5777 mutex_unlock(&dev_priv->rps.hw_lock);
5778
5779 intel_update_cdclk(dev);
5780 }
5781
5782 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5783
5784 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5785 {
5786 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5787 }
5788
5789 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5790 {
5791 int cdclk, vco;
5792
5793 skl_sanitize_cdclk(dev_priv);
5794
5795 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5796 /*
5797 * Use the current vco as our initial
5798 * guess as to what the preferred vco is.
5799 */
5800 if (dev_priv->skl_preferred_vco_freq == 0)
5801 skl_set_preferred_cdclk_vco(dev_priv,
5802 dev_priv->cdclk_pll.vco);
5803 return;
5804 }
5805
5806 vco = dev_priv->skl_preferred_vco_freq;
5807 if (vco == 0)
5808 vco = 8100000;
5809 cdclk = skl_calc_cdclk(0, vco);
5810
5811 skl_set_cdclk(dev_priv, cdclk, vco);
5812 }
5813
5814 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5815 {
5816 uint32_t cdctl, expected;
5817
5818 /*
5819 * check if the pre-os intialized the display
5820 * There is SWF18 scratchpad register defined which is set by the
5821 * pre-os which can be used by the OS drivers to check the status
5822 */
5823 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5824 goto sanitize;
5825
5826 intel_update_cdclk(dev_priv->dev);
5827 /* Is PLL enabled and locked ? */
5828 if (dev_priv->cdclk_pll.vco == 0 ||
5829 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
5830 goto sanitize;
5831
5832 /* DPLL okay; verify the cdclock
5833 *
5834 * Noticed in some instances that the freq selection is correct but
5835 * decimal part is programmed wrong from BIOS where pre-os does not
5836 * enable display. Verify the same as well.
5837 */
5838 cdctl = I915_READ(CDCLK_CTL);
5839 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5840 skl_cdclk_decimal(dev_priv->cdclk_freq);
5841 if (cdctl == expected)
5842 /* All well; nothing to sanitize */
5843 return;
5844
5845 sanitize:
5846 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5847
5848 /* force cdclk programming */
5849 dev_priv->cdclk_freq = 0;
5850 /* force full PLL disable + enable */
5851 dev_priv->cdclk_pll.vco = -1;
5852 }
5853
5854 /* Adjust CDclk dividers to allow high res or save power if possible */
5855 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5856 {
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 u32 val, cmd;
5859
5860 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5861 != dev_priv->cdclk_freq);
5862
5863 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5864 cmd = 2;
5865 else if (cdclk == 266667)
5866 cmd = 1;
5867 else
5868 cmd = 0;
5869
5870 mutex_lock(&dev_priv->rps.hw_lock);
5871 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5872 val &= ~DSPFREQGUAR_MASK;
5873 val |= (cmd << DSPFREQGUAR_SHIFT);
5874 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5875 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5876 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5877 50)) {
5878 DRM_ERROR("timed out waiting for CDclk change\n");
5879 }
5880 mutex_unlock(&dev_priv->rps.hw_lock);
5881
5882 mutex_lock(&dev_priv->sb_lock);
5883
5884 if (cdclk == 400000) {
5885 u32 divider;
5886
5887 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5888
5889 /* adjust cdclk divider */
5890 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5891 val &= ~CCK_FREQUENCY_VALUES;
5892 val |= divider;
5893 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5894
5895 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5896 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5897 50))
5898 DRM_ERROR("timed out waiting for CDclk change\n");
5899 }
5900
5901 /* adjust self-refresh exit latency value */
5902 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5903 val &= ~0x7f;
5904
5905 /*
5906 * For high bandwidth configs, we set a higher latency in the bunit
5907 * so that the core display fetch happens in time to avoid underruns.
5908 */
5909 if (cdclk == 400000)
5910 val |= 4500 / 250; /* 4.5 usec */
5911 else
5912 val |= 3000 / 250; /* 3.0 usec */
5913 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5914
5915 mutex_unlock(&dev_priv->sb_lock);
5916
5917 intel_update_cdclk(dev);
5918 }
5919
5920 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5921 {
5922 struct drm_i915_private *dev_priv = dev->dev_private;
5923 u32 val, cmd;
5924
5925 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5926 != dev_priv->cdclk_freq);
5927
5928 switch (cdclk) {
5929 case 333333:
5930 case 320000:
5931 case 266667:
5932 case 200000:
5933 break;
5934 default:
5935 MISSING_CASE(cdclk);
5936 return;
5937 }
5938
5939 /*
5940 * Specs are full of misinformation, but testing on actual
5941 * hardware has shown that we just need to write the desired
5942 * CCK divider into the Punit register.
5943 */
5944 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5945
5946 mutex_lock(&dev_priv->rps.hw_lock);
5947 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5948 val &= ~DSPFREQGUAR_MASK_CHV;
5949 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5950 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5951 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5952 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5953 50)) {
5954 DRM_ERROR("timed out waiting for CDclk change\n");
5955 }
5956 mutex_unlock(&dev_priv->rps.hw_lock);
5957
5958 intel_update_cdclk(dev);
5959 }
5960
5961 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5962 int max_pixclk)
5963 {
5964 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5965 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5966
5967 /*
5968 * Really only a few cases to deal with, as only 4 CDclks are supported:
5969 * 200MHz
5970 * 267MHz
5971 * 320/333MHz (depends on HPLL freq)
5972 * 400MHz (VLV only)
5973 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5974 * of the lower bin and adjust if needed.
5975 *
5976 * We seem to get an unstable or solid color picture at 200MHz.
5977 * Not sure what's wrong. For now use 200MHz only when all pipes
5978 * are off.
5979 */
5980 if (!IS_CHERRYVIEW(dev_priv) &&
5981 max_pixclk > freq_320*limit/100)
5982 return 400000;
5983 else if (max_pixclk > 266667*limit/100)
5984 return freq_320;
5985 else if (max_pixclk > 0)
5986 return 266667;
5987 else
5988 return 200000;
5989 }
5990
5991 static int bxt_calc_cdclk(int max_pixclk)
5992 {
5993 if (max_pixclk > 576000)
5994 return 624000;
5995 else if (max_pixclk > 384000)
5996 return 576000;
5997 else if (max_pixclk > 288000)
5998 return 384000;
5999 else if (max_pixclk > 144000)
6000 return 288000;
6001 else
6002 return 144000;
6003 }
6004
6005 /* Compute the max pixel clock for new configuration. */
6006 static int intel_mode_max_pixclk(struct drm_device *dev,
6007 struct drm_atomic_state *state)
6008 {
6009 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct drm_crtc *crtc;
6012 struct drm_crtc_state *crtc_state;
6013 unsigned max_pixclk = 0, i;
6014 enum pipe pipe;
6015
6016 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6017 sizeof(intel_state->min_pixclk));
6018
6019 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6020 int pixclk = 0;
6021
6022 if (crtc_state->enable)
6023 pixclk = crtc_state->adjusted_mode.crtc_clock;
6024
6025 intel_state->min_pixclk[i] = pixclk;
6026 }
6027
6028 for_each_pipe(dev_priv, pipe)
6029 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6030
6031 return max_pixclk;
6032 }
6033
6034 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6035 {
6036 struct drm_device *dev = state->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 int max_pixclk = intel_mode_max_pixclk(dev, state);
6039 struct intel_atomic_state *intel_state =
6040 to_intel_atomic_state(state);
6041
6042 intel_state->cdclk = intel_state->dev_cdclk =
6043 valleyview_calc_cdclk(dev_priv, max_pixclk);
6044
6045 if (!intel_state->active_crtcs)
6046 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6047
6048 return 0;
6049 }
6050
6051 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6052 {
6053 int max_pixclk = ilk_max_pixel_rate(state);
6054 struct intel_atomic_state *intel_state =
6055 to_intel_atomic_state(state);
6056
6057 intel_state->cdclk = intel_state->dev_cdclk =
6058 bxt_calc_cdclk(max_pixclk);
6059
6060 if (!intel_state->active_crtcs)
6061 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6062
6063 return 0;
6064 }
6065
6066 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6067 {
6068 unsigned int credits, default_credits;
6069
6070 if (IS_CHERRYVIEW(dev_priv))
6071 default_credits = PFI_CREDIT(12);
6072 else
6073 default_credits = PFI_CREDIT(8);
6074
6075 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6076 /* CHV suggested value is 31 or 63 */
6077 if (IS_CHERRYVIEW(dev_priv))
6078 credits = PFI_CREDIT_63;
6079 else
6080 credits = PFI_CREDIT(15);
6081 } else {
6082 credits = default_credits;
6083 }
6084
6085 /*
6086 * WA - write default credits before re-programming
6087 * FIXME: should we also set the resend bit here?
6088 */
6089 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6090 default_credits);
6091
6092 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6093 credits | PFI_CREDIT_RESEND);
6094
6095 /*
6096 * FIXME is this guaranteed to clear
6097 * immediately or should we poll for it?
6098 */
6099 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6100 }
6101
6102 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6103 {
6104 struct drm_device *dev = old_state->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106 struct intel_atomic_state *old_intel_state =
6107 to_intel_atomic_state(old_state);
6108 unsigned req_cdclk = old_intel_state->dev_cdclk;
6109
6110 /*
6111 * FIXME: We can end up here with all power domains off, yet
6112 * with a CDCLK frequency other than the minimum. To account
6113 * for this take the PIPE-A power domain, which covers the HW
6114 * blocks needed for the following programming. This can be
6115 * removed once it's guaranteed that we get here either with
6116 * the minimum CDCLK set, or the required power domains
6117 * enabled.
6118 */
6119 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6120
6121 if (IS_CHERRYVIEW(dev))
6122 cherryview_set_cdclk(dev, req_cdclk);
6123 else
6124 valleyview_set_cdclk(dev, req_cdclk);
6125
6126 vlv_program_pfi_credits(dev_priv);
6127
6128 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6129 }
6130
6131 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6132 {
6133 struct drm_device *dev = crtc->dev;
6134 struct drm_i915_private *dev_priv = to_i915(dev);
6135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6136 struct intel_encoder *encoder;
6137 struct intel_crtc_state *pipe_config =
6138 to_intel_crtc_state(crtc->state);
6139 int pipe = intel_crtc->pipe;
6140
6141 if (WARN_ON(intel_crtc->active))
6142 return;
6143
6144 if (intel_crtc->config->has_dp_encoder)
6145 intel_dp_set_m_n(intel_crtc, M1_N1);
6146
6147 intel_set_pipe_timings(intel_crtc);
6148 intel_set_pipe_src_size(intel_crtc);
6149
6150 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6154 I915_WRITE(CHV_CANVAS(pipe), 0);
6155 }
6156
6157 i9xx_set_pipeconf(intel_crtc);
6158
6159 intel_crtc->active = true;
6160
6161 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6162
6163 for_each_encoder_on_crtc(dev, crtc, encoder)
6164 if (encoder->pre_pll_enable)
6165 encoder->pre_pll_enable(encoder);
6166
6167 if (IS_CHERRYVIEW(dev)) {
6168 chv_prepare_pll(intel_crtc, intel_crtc->config);
6169 chv_enable_pll(intel_crtc, intel_crtc->config);
6170 } else {
6171 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6172 vlv_enable_pll(intel_crtc, intel_crtc->config);
6173 }
6174
6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 if (encoder->pre_enable)
6177 encoder->pre_enable(encoder);
6178
6179 i9xx_pfit_enable(intel_crtc);
6180
6181 intel_color_load_luts(&pipe_config->base);
6182
6183 intel_update_watermarks(crtc);
6184 intel_enable_pipe(intel_crtc);
6185
6186 assert_vblank_disabled(crtc);
6187 drm_crtc_vblank_on(crtc);
6188
6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 encoder->enable(encoder);
6191 }
6192
6193 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6194 {
6195 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197
6198 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6199 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6200 }
6201
6202 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6203 {
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = to_i915(dev);
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 struct intel_encoder *encoder;
6208 struct intel_crtc_state *pipe_config =
6209 to_intel_crtc_state(crtc->state);
6210 enum pipe pipe = intel_crtc->pipe;
6211
6212 if (WARN_ON(intel_crtc->active))
6213 return;
6214
6215 i9xx_set_pll_dividers(intel_crtc);
6216
6217 if (intel_crtc->config->has_dp_encoder)
6218 intel_dp_set_m_n(intel_crtc, M1_N1);
6219
6220 intel_set_pipe_timings(intel_crtc);
6221 intel_set_pipe_src_size(intel_crtc);
6222
6223 i9xx_set_pipeconf(intel_crtc);
6224
6225 intel_crtc->active = true;
6226
6227 if (!IS_GEN2(dev))
6228 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6229
6230 for_each_encoder_on_crtc(dev, crtc, encoder)
6231 if (encoder->pre_enable)
6232 encoder->pre_enable(encoder);
6233
6234 i9xx_enable_pll(intel_crtc);
6235
6236 i9xx_pfit_enable(intel_crtc);
6237
6238 intel_color_load_luts(&pipe_config->base);
6239
6240 intel_update_watermarks(crtc);
6241 intel_enable_pipe(intel_crtc);
6242
6243 assert_vblank_disabled(crtc);
6244 drm_crtc_vblank_on(crtc);
6245
6246 for_each_encoder_on_crtc(dev, crtc, encoder)
6247 encoder->enable(encoder);
6248 }
6249
6250 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6251 {
6252 struct drm_device *dev = crtc->base.dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254
6255 if (!crtc->config->gmch_pfit.control)
6256 return;
6257
6258 assert_pipe_disabled(dev_priv, crtc->pipe);
6259
6260 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6261 I915_READ(PFIT_CONTROL));
6262 I915_WRITE(PFIT_CONTROL, 0);
6263 }
6264
6265 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6266 {
6267 struct drm_device *dev = crtc->dev;
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270 struct intel_encoder *encoder;
6271 int pipe = intel_crtc->pipe;
6272
6273 /*
6274 * On gen2 planes are double buffered but the pipe isn't, so we must
6275 * wait for planes to fully turn off before disabling the pipe.
6276 */
6277 if (IS_GEN2(dev))
6278 intel_wait_for_vblank(dev, pipe);
6279
6280 for_each_encoder_on_crtc(dev, crtc, encoder)
6281 encoder->disable(encoder);
6282
6283 drm_crtc_vblank_off(crtc);
6284 assert_vblank_disabled(crtc);
6285
6286 intel_disable_pipe(intel_crtc);
6287
6288 i9xx_pfit_disable(intel_crtc);
6289
6290 for_each_encoder_on_crtc(dev, crtc, encoder)
6291 if (encoder->post_disable)
6292 encoder->post_disable(encoder);
6293
6294 if (!intel_crtc->config->has_dsi_encoder) {
6295 if (IS_CHERRYVIEW(dev))
6296 chv_disable_pll(dev_priv, pipe);
6297 else if (IS_VALLEYVIEW(dev))
6298 vlv_disable_pll(dev_priv, pipe);
6299 else
6300 i9xx_disable_pll(intel_crtc);
6301 }
6302
6303 for_each_encoder_on_crtc(dev, crtc, encoder)
6304 if (encoder->post_pll_disable)
6305 encoder->post_pll_disable(encoder);
6306
6307 if (!IS_GEN2(dev))
6308 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6309 }
6310
6311 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6312 {
6313 struct intel_encoder *encoder;
6314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6316 enum intel_display_power_domain domain;
6317 unsigned long domains;
6318
6319 if (!intel_crtc->active)
6320 return;
6321
6322 if (to_intel_plane_state(crtc->primary->state)->visible) {
6323 WARN_ON(intel_crtc->flip_work);
6324
6325 intel_pre_disable_primary_noatomic(crtc);
6326
6327 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6328 to_intel_plane_state(crtc->primary->state)->visible = false;
6329 }
6330
6331 dev_priv->display.crtc_disable(crtc);
6332
6333 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6334 crtc->base.id, crtc->name);
6335
6336 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6337 crtc->state->active = false;
6338 intel_crtc->active = false;
6339 crtc->enabled = false;
6340 crtc->state->connector_mask = 0;
6341 crtc->state->encoder_mask = 0;
6342
6343 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6344 encoder->base.crtc = NULL;
6345
6346 intel_fbc_disable(intel_crtc);
6347 intel_update_watermarks(crtc);
6348 intel_disable_shared_dpll(intel_crtc);
6349
6350 domains = intel_crtc->enabled_power_domains;
6351 for_each_power_domain(domain, domains)
6352 intel_display_power_put(dev_priv, domain);
6353 intel_crtc->enabled_power_domains = 0;
6354
6355 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6356 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6357 }
6358
6359 /*
6360 * turn all crtc's off, but do not adjust state
6361 * This has to be paired with a call to intel_modeset_setup_hw_state.
6362 */
6363 int intel_display_suspend(struct drm_device *dev)
6364 {
6365 struct drm_i915_private *dev_priv = to_i915(dev);
6366 struct drm_atomic_state *state;
6367 int ret;
6368
6369 state = drm_atomic_helper_suspend(dev);
6370 ret = PTR_ERR_OR_ZERO(state);
6371 if (ret)
6372 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6373 else
6374 dev_priv->modeset_restore_state = state;
6375 return ret;
6376 }
6377
6378 void intel_encoder_destroy(struct drm_encoder *encoder)
6379 {
6380 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6381
6382 drm_encoder_cleanup(encoder);
6383 kfree(intel_encoder);
6384 }
6385
6386 /* Cross check the actual hw state with our own modeset state tracking (and it's
6387 * internal consistency). */
6388 static void intel_connector_verify_state(struct intel_connector *connector)
6389 {
6390 struct drm_crtc *crtc = connector->base.state->crtc;
6391
6392 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6393 connector->base.base.id,
6394 connector->base.name);
6395
6396 if (connector->get_hw_state(connector)) {
6397 struct intel_encoder *encoder = connector->encoder;
6398 struct drm_connector_state *conn_state = connector->base.state;
6399
6400 I915_STATE_WARN(!crtc,
6401 "connector enabled without attached crtc\n");
6402
6403 if (!crtc)
6404 return;
6405
6406 I915_STATE_WARN(!crtc->state->active,
6407 "connector is active, but attached crtc isn't\n");
6408
6409 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6410 return;
6411
6412 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6413 "atomic encoder doesn't match attached encoder\n");
6414
6415 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6416 "attached encoder crtc differs from connector crtc\n");
6417 } else {
6418 I915_STATE_WARN(crtc && crtc->state->active,
6419 "attached crtc is active, but connector isn't\n");
6420 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6421 "best encoder set without crtc!\n");
6422 }
6423 }
6424
6425 int intel_connector_init(struct intel_connector *connector)
6426 {
6427 drm_atomic_helper_connector_reset(&connector->base);
6428
6429 if (!connector->base.state)
6430 return -ENOMEM;
6431
6432 return 0;
6433 }
6434
6435 struct intel_connector *intel_connector_alloc(void)
6436 {
6437 struct intel_connector *connector;
6438
6439 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6440 if (!connector)
6441 return NULL;
6442
6443 if (intel_connector_init(connector) < 0) {
6444 kfree(connector);
6445 return NULL;
6446 }
6447
6448 return connector;
6449 }
6450
6451 /* Simple connector->get_hw_state implementation for encoders that support only
6452 * one connector and no cloning and hence the encoder state determines the state
6453 * of the connector. */
6454 bool intel_connector_get_hw_state(struct intel_connector *connector)
6455 {
6456 enum pipe pipe = 0;
6457 struct intel_encoder *encoder = connector->encoder;
6458
6459 return encoder->get_hw_state(encoder, &pipe);
6460 }
6461
6462 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6463 {
6464 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6465 return crtc_state->fdi_lanes;
6466
6467 return 0;
6468 }
6469
6470 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6471 struct intel_crtc_state *pipe_config)
6472 {
6473 struct drm_atomic_state *state = pipe_config->base.state;
6474 struct intel_crtc *other_crtc;
6475 struct intel_crtc_state *other_crtc_state;
6476
6477 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6478 pipe_name(pipe), pipe_config->fdi_lanes);
6479 if (pipe_config->fdi_lanes > 4) {
6480 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6481 pipe_name(pipe), pipe_config->fdi_lanes);
6482 return -EINVAL;
6483 }
6484
6485 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6486 if (pipe_config->fdi_lanes > 2) {
6487 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6488 pipe_config->fdi_lanes);
6489 return -EINVAL;
6490 } else {
6491 return 0;
6492 }
6493 }
6494
6495 if (INTEL_INFO(dev)->num_pipes == 2)
6496 return 0;
6497
6498 /* Ivybridge 3 pipe is really complicated */
6499 switch (pipe) {
6500 case PIPE_A:
6501 return 0;
6502 case PIPE_B:
6503 if (pipe_config->fdi_lanes <= 2)
6504 return 0;
6505
6506 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6507 other_crtc_state =
6508 intel_atomic_get_crtc_state(state, other_crtc);
6509 if (IS_ERR(other_crtc_state))
6510 return PTR_ERR(other_crtc_state);
6511
6512 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6513 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6514 pipe_name(pipe), pipe_config->fdi_lanes);
6515 return -EINVAL;
6516 }
6517 return 0;
6518 case PIPE_C:
6519 if (pipe_config->fdi_lanes > 2) {
6520 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6521 pipe_name(pipe), pipe_config->fdi_lanes);
6522 return -EINVAL;
6523 }
6524
6525 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6526 other_crtc_state =
6527 intel_atomic_get_crtc_state(state, other_crtc);
6528 if (IS_ERR(other_crtc_state))
6529 return PTR_ERR(other_crtc_state);
6530
6531 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6532 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6533 return -EINVAL;
6534 }
6535 return 0;
6536 default:
6537 BUG();
6538 }
6539 }
6540
6541 #define RETRY 1
6542 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6543 struct intel_crtc_state *pipe_config)
6544 {
6545 struct drm_device *dev = intel_crtc->base.dev;
6546 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6547 int lane, link_bw, fdi_dotclock, ret;
6548 bool needs_recompute = false;
6549
6550 retry:
6551 /* FDI is a binary signal running at ~2.7GHz, encoding
6552 * each output octet as 10 bits. The actual frequency
6553 * is stored as a divider into a 100MHz clock, and the
6554 * mode pixel clock is stored in units of 1KHz.
6555 * Hence the bw of each lane in terms of the mode signal
6556 * is:
6557 */
6558 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6559
6560 fdi_dotclock = adjusted_mode->crtc_clock;
6561
6562 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6563 pipe_config->pipe_bpp);
6564
6565 pipe_config->fdi_lanes = lane;
6566
6567 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6568 link_bw, &pipe_config->fdi_m_n);
6569
6570 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6571 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6572 pipe_config->pipe_bpp -= 2*3;
6573 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574 pipe_config->pipe_bpp);
6575 needs_recompute = true;
6576 pipe_config->bw_constrained = true;
6577
6578 goto retry;
6579 }
6580
6581 if (needs_recompute)
6582 return RETRY;
6583
6584 return ret;
6585 }
6586
6587 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588 struct intel_crtc_state *pipe_config)
6589 {
6590 if (pipe_config->pipe_bpp > 24)
6591 return false;
6592
6593 /* HSW can handle pixel rate up to cdclk? */
6594 if (IS_HASWELL(dev_priv))
6595 return true;
6596
6597 /*
6598 * We compare against max which means we must take
6599 * the increased cdclk requirement into account when
6600 * calculating the new cdclk.
6601 *
6602 * Should measure whether using a lower cdclk w/o IPS
6603 */
6604 return ilk_pipe_pixel_rate(pipe_config) <=
6605 dev_priv->max_cdclk_freq * 95 / 100;
6606 }
6607
6608 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6609 struct intel_crtc_state *pipe_config)
6610 {
6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613
6614 pipe_config->ips_enabled = i915.enable_ips &&
6615 hsw_crtc_supports_ips(crtc) &&
6616 pipe_config_supports_ips(dev_priv, pipe_config);
6617 }
6618
6619 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6620 {
6621 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6622
6623 /* GDG double wide on either pipe, otherwise pipe A only */
6624 return INTEL_INFO(dev_priv)->gen < 4 &&
6625 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6626 }
6627
6628 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6629 struct intel_crtc_state *pipe_config)
6630 {
6631 struct drm_device *dev = crtc->base.dev;
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6634 int clock_limit = dev_priv->max_dotclk_freq;
6635
6636 if (INTEL_INFO(dev)->gen < 4) {
6637 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6638
6639 /*
6640 * Enable double wide mode when the dot clock
6641 * is > 90% of the (display) core speed.
6642 */
6643 if (intel_crtc_supports_double_wide(crtc) &&
6644 adjusted_mode->crtc_clock > clock_limit) {
6645 clock_limit = dev_priv->max_dotclk_freq;
6646 pipe_config->double_wide = true;
6647 }
6648 }
6649
6650 if (adjusted_mode->crtc_clock > clock_limit) {
6651 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6652 adjusted_mode->crtc_clock, clock_limit,
6653 yesno(pipe_config->double_wide));
6654 return -EINVAL;
6655 }
6656
6657 /*
6658 * Pipe horizontal size must be even in:
6659 * - DVO ganged mode
6660 * - LVDS dual channel mode
6661 * - Double wide pipe
6662 */
6663 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6664 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6665 pipe_config->pipe_src_w &= ~1;
6666
6667 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6668 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6669 */
6670 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6671 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6672 return -EINVAL;
6673
6674 if (HAS_IPS(dev))
6675 hsw_compute_ips_config(crtc, pipe_config);
6676
6677 if (pipe_config->has_pch_encoder)
6678 return ironlake_fdi_compute_config(crtc, pipe_config);
6679
6680 return 0;
6681 }
6682
6683 static int skylake_get_display_clock_speed(struct drm_device *dev)
6684 {
6685 struct drm_i915_private *dev_priv = to_i915(dev);
6686 uint32_t cdctl;
6687
6688 skl_dpll0_update(dev_priv);
6689
6690 if (dev_priv->cdclk_pll.vco == 0)
6691 return dev_priv->cdclk_pll.ref;
6692
6693 cdctl = I915_READ(CDCLK_CTL);
6694
6695 if (dev_priv->cdclk_pll.vco == 8640000) {
6696 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6697 case CDCLK_FREQ_450_432:
6698 return 432000;
6699 case CDCLK_FREQ_337_308:
6700 return 308571;
6701 case CDCLK_FREQ_540:
6702 return 540000;
6703 case CDCLK_FREQ_675_617:
6704 return 617143;
6705 default:
6706 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6707 }
6708 } else {
6709 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6710 case CDCLK_FREQ_450_432:
6711 return 450000;
6712 case CDCLK_FREQ_337_308:
6713 return 337500;
6714 case CDCLK_FREQ_540:
6715 return 540000;
6716 case CDCLK_FREQ_675_617:
6717 return 675000;
6718 default:
6719 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6720 }
6721 }
6722
6723 return dev_priv->cdclk_pll.ref;
6724 }
6725
6726 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
6727 {
6728 u32 val;
6729
6730 dev_priv->cdclk_pll.ref = 19200;
6731 dev_priv->cdclk_pll.vco = 0;
6732
6733 val = I915_READ(BXT_DE_PLL_ENABLE);
6734 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
6735 return;
6736
6737 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
6738 return;
6739
6740 val = I915_READ(BXT_DE_PLL_CTL);
6741 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
6742 dev_priv->cdclk_pll.ref;
6743 }
6744
6745 static int broxton_get_display_clock_speed(struct drm_device *dev)
6746 {
6747 struct drm_i915_private *dev_priv = to_i915(dev);
6748 u32 divider;
6749 int div, vco;
6750
6751 bxt_de_pll_update(dev_priv);
6752
6753 vco = dev_priv->cdclk_pll.vco;
6754 if (vco == 0)
6755 return dev_priv->cdclk_pll.ref;
6756
6757 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
6758
6759 switch (divider) {
6760 case BXT_CDCLK_CD2X_DIV_SEL_1:
6761 div = 2;
6762 break;
6763 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6764 div = 3;
6765 break;
6766 case BXT_CDCLK_CD2X_DIV_SEL_2:
6767 div = 4;
6768 break;
6769 case BXT_CDCLK_CD2X_DIV_SEL_4:
6770 div = 8;
6771 break;
6772 default:
6773 MISSING_CASE(divider);
6774 return dev_priv->cdclk_pll.ref;
6775 }
6776
6777 return DIV_ROUND_CLOSEST(vco, div);
6778 }
6779
6780 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6781 {
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783 uint32_t lcpll = I915_READ(LCPLL_CTL);
6784 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6785
6786 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6787 return 800000;
6788 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6789 return 450000;
6790 else if (freq == LCPLL_CLK_FREQ_450)
6791 return 450000;
6792 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6793 return 540000;
6794 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6795 return 337500;
6796 else
6797 return 675000;
6798 }
6799
6800 static int haswell_get_display_clock_speed(struct drm_device *dev)
6801 {
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t lcpll = I915_READ(LCPLL_CTL);
6804 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6805
6806 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6807 return 800000;
6808 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6809 return 450000;
6810 else if (freq == LCPLL_CLK_FREQ_450)
6811 return 450000;
6812 else if (IS_HSW_ULT(dev))
6813 return 337500;
6814 else
6815 return 540000;
6816 }
6817
6818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6819 {
6820 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6821 CCK_DISPLAY_CLOCK_CONTROL);
6822 }
6823
6824 static int ilk_get_display_clock_speed(struct drm_device *dev)
6825 {
6826 return 450000;
6827 }
6828
6829 static int i945_get_display_clock_speed(struct drm_device *dev)
6830 {
6831 return 400000;
6832 }
6833
6834 static int i915_get_display_clock_speed(struct drm_device *dev)
6835 {
6836 return 333333;
6837 }
6838
6839 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6840 {
6841 return 200000;
6842 }
6843
6844 static int pnv_get_display_clock_speed(struct drm_device *dev)
6845 {
6846 u16 gcfgc = 0;
6847
6848 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6849
6850 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6851 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6852 return 266667;
6853 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6854 return 333333;
6855 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6856 return 444444;
6857 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6858 return 200000;
6859 default:
6860 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6861 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6862 return 133333;
6863 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6864 return 166667;
6865 }
6866 }
6867
6868 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6869 {
6870 u16 gcfgc = 0;
6871
6872 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6873
6874 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6875 return 133333;
6876 else {
6877 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6878 case GC_DISPLAY_CLOCK_333_MHZ:
6879 return 333333;
6880 default:
6881 case GC_DISPLAY_CLOCK_190_200_MHZ:
6882 return 190000;
6883 }
6884 }
6885 }
6886
6887 static int i865_get_display_clock_speed(struct drm_device *dev)
6888 {
6889 return 266667;
6890 }
6891
6892 static int i85x_get_display_clock_speed(struct drm_device *dev)
6893 {
6894 u16 hpllcc = 0;
6895
6896 /*
6897 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6898 * encoding is different :(
6899 * FIXME is this the right way to detect 852GM/852GMV?
6900 */
6901 if (dev->pdev->revision == 0x1)
6902 return 133333;
6903
6904 pci_bus_read_config_word(dev->pdev->bus,
6905 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6906
6907 /* Assume that the hardware is in the high speed state. This
6908 * should be the default.
6909 */
6910 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6911 case GC_CLOCK_133_200:
6912 case GC_CLOCK_133_200_2:
6913 case GC_CLOCK_100_200:
6914 return 200000;
6915 case GC_CLOCK_166_250:
6916 return 250000;
6917 case GC_CLOCK_100_133:
6918 return 133333;
6919 case GC_CLOCK_133_266:
6920 case GC_CLOCK_133_266_2:
6921 case GC_CLOCK_166_266:
6922 return 266667;
6923 }
6924
6925 /* Shouldn't happen */
6926 return 0;
6927 }
6928
6929 static int i830_get_display_clock_speed(struct drm_device *dev)
6930 {
6931 return 133333;
6932 }
6933
6934 static unsigned int intel_hpll_vco(struct drm_device *dev)
6935 {
6936 struct drm_i915_private *dev_priv = dev->dev_private;
6937 static const unsigned int blb_vco[8] = {
6938 [0] = 3200000,
6939 [1] = 4000000,
6940 [2] = 5333333,
6941 [3] = 4800000,
6942 [4] = 6400000,
6943 };
6944 static const unsigned int pnv_vco[8] = {
6945 [0] = 3200000,
6946 [1] = 4000000,
6947 [2] = 5333333,
6948 [3] = 4800000,
6949 [4] = 2666667,
6950 };
6951 static const unsigned int cl_vco[8] = {
6952 [0] = 3200000,
6953 [1] = 4000000,
6954 [2] = 5333333,
6955 [3] = 6400000,
6956 [4] = 3333333,
6957 [5] = 3566667,
6958 [6] = 4266667,
6959 };
6960 static const unsigned int elk_vco[8] = {
6961 [0] = 3200000,
6962 [1] = 4000000,
6963 [2] = 5333333,
6964 [3] = 4800000,
6965 };
6966 static const unsigned int ctg_vco[8] = {
6967 [0] = 3200000,
6968 [1] = 4000000,
6969 [2] = 5333333,
6970 [3] = 6400000,
6971 [4] = 2666667,
6972 [5] = 4266667,
6973 };
6974 const unsigned int *vco_table;
6975 unsigned int vco;
6976 uint8_t tmp = 0;
6977
6978 /* FIXME other chipsets? */
6979 if (IS_GM45(dev))
6980 vco_table = ctg_vco;
6981 else if (IS_G4X(dev))
6982 vco_table = elk_vco;
6983 else if (IS_CRESTLINE(dev))
6984 vco_table = cl_vco;
6985 else if (IS_PINEVIEW(dev))
6986 vco_table = pnv_vco;
6987 else if (IS_G33(dev))
6988 vco_table = blb_vco;
6989 else
6990 return 0;
6991
6992 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6993
6994 vco = vco_table[tmp & 0x7];
6995 if (vco == 0)
6996 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6997 else
6998 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6999
7000 return vco;
7001 }
7002
7003 static int gm45_get_display_clock_speed(struct drm_device *dev)
7004 {
7005 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7006 uint16_t tmp = 0;
7007
7008 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7009
7010 cdclk_sel = (tmp >> 12) & 0x1;
7011
7012 switch (vco) {
7013 case 2666667:
7014 case 4000000:
7015 case 5333333:
7016 return cdclk_sel ? 333333 : 222222;
7017 case 3200000:
7018 return cdclk_sel ? 320000 : 228571;
7019 default:
7020 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7021 return 222222;
7022 }
7023 }
7024
7025 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7026 {
7027 static const uint8_t div_3200[] = { 16, 10, 8 };
7028 static const uint8_t div_4000[] = { 20, 12, 10 };
7029 static const uint8_t div_5333[] = { 24, 16, 14 };
7030 const uint8_t *div_table;
7031 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7032 uint16_t tmp = 0;
7033
7034 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7035
7036 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7037
7038 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7039 goto fail;
7040
7041 switch (vco) {
7042 case 3200000:
7043 div_table = div_3200;
7044 break;
7045 case 4000000:
7046 div_table = div_4000;
7047 break;
7048 case 5333333:
7049 div_table = div_5333;
7050 break;
7051 default:
7052 goto fail;
7053 }
7054
7055 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7056
7057 fail:
7058 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7059 return 200000;
7060 }
7061
7062 static int g33_get_display_clock_speed(struct drm_device *dev)
7063 {
7064 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7065 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7066 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7067 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7068 const uint8_t *div_table;
7069 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7070 uint16_t tmp = 0;
7071
7072 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7073
7074 cdclk_sel = (tmp >> 4) & 0x7;
7075
7076 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7077 goto fail;
7078
7079 switch (vco) {
7080 case 3200000:
7081 div_table = div_3200;
7082 break;
7083 case 4000000:
7084 div_table = div_4000;
7085 break;
7086 case 4800000:
7087 div_table = div_4800;
7088 break;
7089 case 5333333:
7090 div_table = div_5333;
7091 break;
7092 default:
7093 goto fail;
7094 }
7095
7096 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7097
7098 fail:
7099 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7100 return 190476;
7101 }
7102
7103 static void
7104 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7105 {
7106 while (*num > DATA_LINK_M_N_MASK ||
7107 *den > DATA_LINK_M_N_MASK) {
7108 *num >>= 1;
7109 *den >>= 1;
7110 }
7111 }
7112
7113 static void compute_m_n(unsigned int m, unsigned int n,
7114 uint32_t *ret_m, uint32_t *ret_n)
7115 {
7116 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7117 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7118 intel_reduce_m_n_ratio(ret_m, ret_n);
7119 }
7120
7121 void
7122 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7123 int pixel_clock, int link_clock,
7124 struct intel_link_m_n *m_n)
7125 {
7126 m_n->tu = 64;
7127
7128 compute_m_n(bits_per_pixel * pixel_clock,
7129 link_clock * nlanes * 8,
7130 &m_n->gmch_m, &m_n->gmch_n);
7131
7132 compute_m_n(pixel_clock, link_clock,
7133 &m_n->link_m, &m_n->link_n);
7134 }
7135
7136 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7137 {
7138 if (i915.panel_use_ssc >= 0)
7139 return i915.panel_use_ssc != 0;
7140 return dev_priv->vbt.lvds_use_ssc
7141 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7142 }
7143
7144 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7145 {
7146 return (1 << dpll->n) << 16 | dpll->m2;
7147 }
7148
7149 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7150 {
7151 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7152 }
7153
7154 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7155 struct intel_crtc_state *crtc_state,
7156 struct dpll *reduced_clock)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 u32 fp, fp2 = 0;
7160
7161 if (IS_PINEVIEW(dev)) {
7162 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7163 if (reduced_clock)
7164 fp2 = pnv_dpll_compute_fp(reduced_clock);
7165 } else {
7166 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7167 if (reduced_clock)
7168 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7169 }
7170
7171 crtc_state->dpll_hw_state.fp0 = fp;
7172
7173 crtc->lowfreq_avail = false;
7174 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7175 reduced_clock) {
7176 crtc_state->dpll_hw_state.fp1 = fp2;
7177 crtc->lowfreq_avail = true;
7178 } else {
7179 crtc_state->dpll_hw_state.fp1 = fp;
7180 }
7181 }
7182
7183 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7184 pipe)
7185 {
7186 u32 reg_val;
7187
7188 /*
7189 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7190 * and set it to a reasonable value instead.
7191 */
7192 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7193 reg_val &= 0xffffff00;
7194 reg_val |= 0x00000030;
7195 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7196
7197 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7198 reg_val &= 0x8cffffff;
7199 reg_val = 0x8c000000;
7200 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7201
7202 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7203 reg_val &= 0xffffff00;
7204 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7205
7206 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7207 reg_val &= 0x00ffffff;
7208 reg_val |= 0xb0000000;
7209 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7210 }
7211
7212 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7213 struct intel_link_m_n *m_n)
7214 {
7215 struct drm_device *dev = crtc->base.dev;
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217 int pipe = crtc->pipe;
7218
7219 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7220 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7221 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7222 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7223 }
7224
7225 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7226 struct intel_link_m_n *m_n,
7227 struct intel_link_m_n *m2_n2)
7228 {
7229 struct drm_device *dev = crtc->base.dev;
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231 int pipe = crtc->pipe;
7232 enum transcoder transcoder = crtc->config->cpu_transcoder;
7233
7234 if (INTEL_INFO(dev)->gen >= 5) {
7235 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7236 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7237 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7238 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7239 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7240 * for gen < 8) and if DRRS is supported (to make sure the
7241 * registers are not unnecessarily accessed).
7242 */
7243 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7244 crtc->config->has_drrs) {
7245 I915_WRITE(PIPE_DATA_M2(transcoder),
7246 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7247 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7248 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7249 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7250 }
7251 } else {
7252 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7253 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7254 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7255 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7256 }
7257 }
7258
7259 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7260 {
7261 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7262
7263 if (m_n == M1_N1) {
7264 dp_m_n = &crtc->config->dp_m_n;
7265 dp_m2_n2 = &crtc->config->dp_m2_n2;
7266 } else if (m_n == M2_N2) {
7267
7268 /*
7269 * M2_N2 registers are not supported. Hence m2_n2 divider value
7270 * needs to be programmed into M1_N1.
7271 */
7272 dp_m_n = &crtc->config->dp_m2_n2;
7273 } else {
7274 DRM_ERROR("Unsupported divider value\n");
7275 return;
7276 }
7277
7278 if (crtc->config->has_pch_encoder)
7279 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7280 else
7281 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7282 }
7283
7284 static void vlv_compute_dpll(struct intel_crtc *crtc,
7285 struct intel_crtc_state *pipe_config)
7286 {
7287 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7288 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7289 if (crtc->pipe != PIPE_A)
7290 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7291
7292 /* DPLL not used with DSI, but still need the rest set up */
7293 if (!pipe_config->has_dsi_encoder)
7294 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7295 DPLL_EXT_BUFFER_ENABLE_VLV;
7296
7297 pipe_config->dpll_hw_state.dpll_md =
7298 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7299 }
7300
7301 static void chv_compute_dpll(struct intel_crtc *crtc,
7302 struct intel_crtc_state *pipe_config)
7303 {
7304 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7305 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7306 if (crtc->pipe != PIPE_A)
7307 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7308
7309 /* DPLL not used with DSI, but still need the rest set up */
7310 if (!pipe_config->has_dsi_encoder)
7311 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7312
7313 pipe_config->dpll_hw_state.dpll_md =
7314 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7315 }
7316
7317 static void vlv_prepare_pll(struct intel_crtc *crtc,
7318 const struct intel_crtc_state *pipe_config)
7319 {
7320 struct drm_device *dev = crtc->base.dev;
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322 enum pipe pipe = crtc->pipe;
7323 u32 mdiv;
7324 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7325 u32 coreclk, reg_val;
7326
7327 /* Enable Refclk */
7328 I915_WRITE(DPLL(pipe),
7329 pipe_config->dpll_hw_state.dpll &
7330 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7331
7332 /* No need to actually set up the DPLL with DSI */
7333 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7334 return;
7335
7336 mutex_lock(&dev_priv->sb_lock);
7337
7338 bestn = pipe_config->dpll.n;
7339 bestm1 = pipe_config->dpll.m1;
7340 bestm2 = pipe_config->dpll.m2;
7341 bestp1 = pipe_config->dpll.p1;
7342 bestp2 = pipe_config->dpll.p2;
7343
7344 /* See eDP HDMI DPIO driver vbios notes doc */
7345
7346 /* PLL B needs special handling */
7347 if (pipe == PIPE_B)
7348 vlv_pllb_recal_opamp(dev_priv, pipe);
7349
7350 /* Set up Tx target for periodic Rcomp update */
7351 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7352
7353 /* Disable target IRef on PLL */
7354 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7355 reg_val &= 0x00ffffff;
7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7357
7358 /* Disable fast lock */
7359 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7360
7361 /* Set idtafcrecal before PLL is enabled */
7362 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7363 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7364 mdiv |= ((bestn << DPIO_N_SHIFT));
7365 mdiv |= (1 << DPIO_K_SHIFT);
7366
7367 /*
7368 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7369 * but we don't support that).
7370 * Note: don't use the DAC post divider as it seems unstable.
7371 */
7372 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7374
7375 mdiv |= DPIO_ENABLE_CALIBRATION;
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7377
7378 /* Set HBR and RBR LPF coefficients */
7379 if (pipe_config->port_clock == 162000 ||
7380 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7381 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7383 0x009f0003);
7384 else
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7386 0x00d0000f);
7387
7388 if (pipe_config->has_dp_encoder) {
7389 /* Use SSC source */
7390 if (pipe == PIPE_A)
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7392 0x0df40000);
7393 else
7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7395 0x0df70000);
7396 } else { /* HDMI or VGA */
7397 /* Use bend source */
7398 if (pipe == PIPE_A)
7399 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7400 0x0df70000);
7401 else
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7403 0x0df40000);
7404 }
7405
7406 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7407 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7409 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7410 coreclk |= 0x01000000;
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7412
7413 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7414 mutex_unlock(&dev_priv->sb_lock);
7415 }
7416
7417 static void chv_prepare_pll(struct intel_crtc *crtc,
7418 const struct intel_crtc_state *pipe_config)
7419 {
7420 struct drm_device *dev = crtc->base.dev;
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7422 enum pipe pipe = crtc->pipe;
7423 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7424 u32 loopfilter, tribuf_calcntr;
7425 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7426 u32 dpio_val;
7427 int vco;
7428
7429 /* Enable Refclk and SSC */
7430 I915_WRITE(DPLL(pipe),
7431 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7432
7433 /* No need to actually set up the DPLL with DSI */
7434 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7435 return;
7436
7437 bestn = pipe_config->dpll.n;
7438 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7439 bestm1 = pipe_config->dpll.m1;
7440 bestm2 = pipe_config->dpll.m2 >> 22;
7441 bestp1 = pipe_config->dpll.p1;
7442 bestp2 = pipe_config->dpll.p2;
7443 vco = pipe_config->dpll.vco;
7444 dpio_val = 0;
7445 loopfilter = 0;
7446
7447 mutex_lock(&dev_priv->sb_lock);
7448
7449 /* p1 and p2 divider */
7450 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7451 5 << DPIO_CHV_S1_DIV_SHIFT |
7452 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7453 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7454 1 << DPIO_CHV_K_DIV_SHIFT);
7455
7456 /* Feedback post-divider - m2 */
7457 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7458
7459 /* Feedback refclk divider - n and m1 */
7460 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7461 DPIO_CHV_M1_DIV_BY_2 |
7462 1 << DPIO_CHV_N_DIV_SHIFT);
7463
7464 /* M2 fraction division */
7465 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7466
7467 /* M2 fraction division enable */
7468 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7469 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7470 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7471 if (bestm2_frac)
7472 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7473 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7474
7475 /* Program digital lock detect threshold */
7476 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7477 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7478 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7479 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7480 if (!bestm2_frac)
7481 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7482 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7483
7484 /* Loop filter */
7485 if (vco == 5400000) {
7486 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7487 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7488 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7489 tribuf_calcntr = 0x9;
7490 } else if (vco <= 6200000) {
7491 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7492 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7493 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7494 tribuf_calcntr = 0x9;
7495 } else if (vco <= 6480000) {
7496 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7497 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7498 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7499 tribuf_calcntr = 0x8;
7500 } else {
7501 /* Not supported. Apply the same limits as in the max case */
7502 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7503 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7504 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7505 tribuf_calcntr = 0;
7506 }
7507 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7508
7509 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7510 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7511 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7512 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7513
7514 /* AFC Recal */
7515 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7516 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7517 DPIO_AFC_RECAL);
7518
7519 mutex_unlock(&dev_priv->sb_lock);
7520 }
7521
7522 /**
7523 * vlv_force_pll_on - forcibly enable just the PLL
7524 * @dev_priv: i915 private structure
7525 * @pipe: pipe PLL to enable
7526 * @dpll: PLL configuration
7527 *
7528 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7529 * in cases where we need the PLL enabled even when @pipe is not going to
7530 * be enabled.
7531 */
7532 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7533 const struct dpll *dpll)
7534 {
7535 struct intel_crtc *crtc =
7536 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7537 struct intel_crtc_state *pipe_config;
7538
7539 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7540 if (!pipe_config)
7541 return -ENOMEM;
7542
7543 pipe_config->base.crtc = &crtc->base;
7544 pipe_config->pixel_multiplier = 1;
7545 pipe_config->dpll = *dpll;
7546
7547 if (IS_CHERRYVIEW(dev)) {
7548 chv_compute_dpll(crtc, pipe_config);
7549 chv_prepare_pll(crtc, pipe_config);
7550 chv_enable_pll(crtc, pipe_config);
7551 } else {
7552 vlv_compute_dpll(crtc, pipe_config);
7553 vlv_prepare_pll(crtc, pipe_config);
7554 vlv_enable_pll(crtc, pipe_config);
7555 }
7556
7557 kfree(pipe_config);
7558
7559 return 0;
7560 }
7561
7562 /**
7563 * vlv_force_pll_off - forcibly disable just the PLL
7564 * @dev_priv: i915 private structure
7565 * @pipe: pipe PLL to disable
7566 *
7567 * Disable the PLL for @pipe. To be used in cases where we need
7568 * the PLL enabled even when @pipe is not going to be enabled.
7569 */
7570 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7571 {
7572 if (IS_CHERRYVIEW(dev))
7573 chv_disable_pll(to_i915(dev), pipe);
7574 else
7575 vlv_disable_pll(to_i915(dev), pipe);
7576 }
7577
7578 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7579 struct intel_crtc_state *crtc_state,
7580 struct dpll *reduced_clock)
7581 {
7582 struct drm_device *dev = crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 u32 dpll;
7585 bool is_sdvo;
7586 struct dpll *clock = &crtc_state->dpll;
7587
7588 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7589
7590 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7591 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7592
7593 dpll = DPLL_VGA_MODE_DIS;
7594
7595 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7596 dpll |= DPLLB_MODE_LVDS;
7597 else
7598 dpll |= DPLLB_MODE_DAC_SERIAL;
7599
7600 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7601 dpll |= (crtc_state->pixel_multiplier - 1)
7602 << SDVO_MULTIPLIER_SHIFT_HIRES;
7603 }
7604
7605 if (is_sdvo)
7606 dpll |= DPLL_SDVO_HIGH_SPEED;
7607
7608 if (crtc_state->has_dp_encoder)
7609 dpll |= DPLL_SDVO_HIGH_SPEED;
7610
7611 /* compute bitmask from p1 value */
7612 if (IS_PINEVIEW(dev))
7613 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7614 else {
7615 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7616 if (IS_G4X(dev) && reduced_clock)
7617 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7618 }
7619 switch (clock->p2) {
7620 case 5:
7621 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7622 break;
7623 case 7:
7624 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7625 break;
7626 case 10:
7627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7628 break;
7629 case 14:
7630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7631 break;
7632 }
7633 if (INTEL_INFO(dev)->gen >= 4)
7634 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7635
7636 if (crtc_state->sdvo_tv_clock)
7637 dpll |= PLL_REF_INPUT_TVCLKINBC;
7638 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7639 intel_panel_use_ssc(dev_priv))
7640 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7641 else
7642 dpll |= PLL_REF_INPUT_DREFCLK;
7643
7644 dpll |= DPLL_VCO_ENABLE;
7645 crtc_state->dpll_hw_state.dpll = dpll;
7646
7647 if (INTEL_INFO(dev)->gen >= 4) {
7648 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7649 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7650 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7651 }
7652 }
7653
7654 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7655 struct intel_crtc_state *crtc_state,
7656 struct dpll *reduced_clock)
7657 {
7658 struct drm_device *dev = crtc->base.dev;
7659 struct drm_i915_private *dev_priv = dev->dev_private;
7660 u32 dpll;
7661 struct dpll *clock = &crtc_state->dpll;
7662
7663 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7664
7665 dpll = DPLL_VGA_MODE_DIS;
7666
7667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7669 } else {
7670 if (clock->p1 == 2)
7671 dpll |= PLL_P1_DIVIDE_BY_TWO;
7672 else
7673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7674 if (clock->p2 == 4)
7675 dpll |= PLL_P2_DIVIDE_BY_4;
7676 }
7677
7678 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7679 dpll |= DPLL_DVO_2X_MODE;
7680
7681 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7682 intel_panel_use_ssc(dev_priv))
7683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7684 else
7685 dpll |= PLL_REF_INPUT_DREFCLK;
7686
7687 dpll |= DPLL_VCO_ENABLE;
7688 crtc_state->dpll_hw_state.dpll = dpll;
7689 }
7690
7691 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7692 {
7693 struct drm_device *dev = intel_crtc->base.dev;
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 enum pipe pipe = intel_crtc->pipe;
7696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7697 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7698 uint32_t crtc_vtotal, crtc_vblank_end;
7699 int vsyncshift = 0;
7700
7701 /* We need to be careful not to changed the adjusted mode, for otherwise
7702 * the hw state checker will get angry at the mismatch. */
7703 crtc_vtotal = adjusted_mode->crtc_vtotal;
7704 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7705
7706 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7707 /* the chip adds 2 halflines automatically */
7708 crtc_vtotal -= 1;
7709 crtc_vblank_end -= 1;
7710
7711 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7712 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7713 else
7714 vsyncshift = adjusted_mode->crtc_hsync_start -
7715 adjusted_mode->crtc_htotal / 2;
7716 if (vsyncshift < 0)
7717 vsyncshift += adjusted_mode->crtc_htotal;
7718 }
7719
7720 if (INTEL_INFO(dev)->gen > 3)
7721 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7722
7723 I915_WRITE(HTOTAL(cpu_transcoder),
7724 (adjusted_mode->crtc_hdisplay - 1) |
7725 ((adjusted_mode->crtc_htotal - 1) << 16));
7726 I915_WRITE(HBLANK(cpu_transcoder),
7727 (adjusted_mode->crtc_hblank_start - 1) |
7728 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7729 I915_WRITE(HSYNC(cpu_transcoder),
7730 (adjusted_mode->crtc_hsync_start - 1) |
7731 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7732
7733 I915_WRITE(VTOTAL(cpu_transcoder),
7734 (adjusted_mode->crtc_vdisplay - 1) |
7735 ((crtc_vtotal - 1) << 16));
7736 I915_WRITE(VBLANK(cpu_transcoder),
7737 (adjusted_mode->crtc_vblank_start - 1) |
7738 ((crtc_vblank_end - 1) << 16));
7739 I915_WRITE(VSYNC(cpu_transcoder),
7740 (adjusted_mode->crtc_vsync_start - 1) |
7741 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7742
7743 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7744 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7745 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7746 * bits. */
7747 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7748 (pipe == PIPE_B || pipe == PIPE_C))
7749 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7750
7751 }
7752
7753 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7754 {
7755 struct drm_device *dev = intel_crtc->base.dev;
7756 struct drm_i915_private *dev_priv = dev->dev_private;
7757 enum pipe pipe = intel_crtc->pipe;
7758
7759 /* pipesrc controls the size that is scaled from, which should
7760 * always be the user's requested size.
7761 */
7762 I915_WRITE(PIPESRC(pipe),
7763 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7764 (intel_crtc->config->pipe_src_h - 1));
7765 }
7766
7767 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7768 struct intel_crtc_state *pipe_config)
7769 {
7770 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7773 uint32_t tmp;
7774
7775 tmp = I915_READ(HTOTAL(cpu_transcoder));
7776 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7777 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7778 tmp = I915_READ(HBLANK(cpu_transcoder));
7779 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7780 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7781 tmp = I915_READ(HSYNC(cpu_transcoder));
7782 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7783 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7784
7785 tmp = I915_READ(VTOTAL(cpu_transcoder));
7786 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7787 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7788 tmp = I915_READ(VBLANK(cpu_transcoder));
7789 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7790 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7791 tmp = I915_READ(VSYNC(cpu_transcoder));
7792 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7793 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7794
7795 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7796 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7797 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7798 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7799 }
7800 }
7801
7802 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7803 struct intel_crtc_state *pipe_config)
7804 {
7805 struct drm_device *dev = crtc->base.dev;
7806 struct drm_i915_private *dev_priv = dev->dev_private;
7807 u32 tmp;
7808
7809 tmp = I915_READ(PIPESRC(crtc->pipe));
7810 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7811 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7812
7813 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7814 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7815 }
7816
7817 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7818 struct intel_crtc_state *pipe_config)
7819 {
7820 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7821 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7822 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7823 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7824
7825 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7826 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7827 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7828 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7829
7830 mode->flags = pipe_config->base.adjusted_mode.flags;
7831 mode->type = DRM_MODE_TYPE_DRIVER;
7832
7833 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7834 mode->flags |= pipe_config->base.adjusted_mode.flags;
7835
7836 mode->hsync = drm_mode_hsync(mode);
7837 mode->vrefresh = drm_mode_vrefresh(mode);
7838 drm_mode_set_name(mode);
7839 }
7840
7841 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7842 {
7843 struct drm_device *dev = intel_crtc->base.dev;
7844 struct drm_i915_private *dev_priv = dev->dev_private;
7845 uint32_t pipeconf;
7846
7847 pipeconf = 0;
7848
7849 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7850 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7851 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7852
7853 if (intel_crtc->config->double_wide)
7854 pipeconf |= PIPECONF_DOUBLE_WIDE;
7855
7856 /* only g4x and later have fancy bpc/dither controls */
7857 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7858 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7859 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7860 pipeconf |= PIPECONF_DITHER_EN |
7861 PIPECONF_DITHER_TYPE_SP;
7862
7863 switch (intel_crtc->config->pipe_bpp) {
7864 case 18:
7865 pipeconf |= PIPECONF_6BPC;
7866 break;
7867 case 24:
7868 pipeconf |= PIPECONF_8BPC;
7869 break;
7870 case 30:
7871 pipeconf |= PIPECONF_10BPC;
7872 break;
7873 default:
7874 /* Case prevented by intel_choose_pipe_bpp_dither. */
7875 BUG();
7876 }
7877 }
7878
7879 if (HAS_PIPE_CXSR(dev)) {
7880 if (intel_crtc->lowfreq_avail) {
7881 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7882 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7883 } else {
7884 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7885 }
7886 }
7887
7888 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7889 if (INTEL_INFO(dev)->gen < 4 ||
7890 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7891 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7892 else
7893 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7894 } else
7895 pipeconf |= PIPECONF_PROGRESSIVE;
7896
7897 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7898 intel_crtc->config->limited_color_range)
7899 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7900
7901 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7902 POSTING_READ(PIPECONF(intel_crtc->pipe));
7903 }
7904
7905 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7906 struct intel_crtc_state *crtc_state)
7907 {
7908 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 const struct intel_limit *limit;
7911 int refclk = 48000;
7912
7913 memset(&crtc_state->dpll_hw_state, 0,
7914 sizeof(crtc_state->dpll_hw_state));
7915
7916 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7917 if (intel_panel_use_ssc(dev_priv)) {
7918 refclk = dev_priv->vbt.lvds_ssc_freq;
7919 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7920 }
7921
7922 limit = &intel_limits_i8xx_lvds;
7923 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7924 limit = &intel_limits_i8xx_dvo;
7925 } else {
7926 limit = &intel_limits_i8xx_dac;
7927 }
7928
7929 if (!crtc_state->clock_set &&
7930 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7931 refclk, NULL, &crtc_state->dpll)) {
7932 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7933 return -EINVAL;
7934 }
7935
7936 i8xx_compute_dpll(crtc, crtc_state, NULL);
7937
7938 return 0;
7939 }
7940
7941 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7942 struct intel_crtc_state *crtc_state)
7943 {
7944 struct drm_device *dev = crtc->base.dev;
7945 struct drm_i915_private *dev_priv = dev->dev_private;
7946 const struct intel_limit *limit;
7947 int refclk = 96000;
7948
7949 memset(&crtc_state->dpll_hw_state, 0,
7950 sizeof(crtc_state->dpll_hw_state));
7951
7952 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7953 if (intel_panel_use_ssc(dev_priv)) {
7954 refclk = dev_priv->vbt.lvds_ssc_freq;
7955 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7956 }
7957
7958 if (intel_is_dual_link_lvds(dev))
7959 limit = &intel_limits_g4x_dual_channel_lvds;
7960 else
7961 limit = &intel_limits_g4x_single_channel_lvds;
7962 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7963 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7964 limit = &intel_limits_g4x_hdmi;
7965 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7966 limit = &intel_limits_g4x_sdvo;
7967 } else {
7968 /* The option is for other outputs */
7969 limit = &intel_limits_i9xx_sdvo;
7970 }
7971
7972 if (!crtc_state->clock_set &&
7973 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7974 refclk, NULL, &crtc_state->dpll)) {
7975 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7976 return -EINVAL;
7977 }
7978
7979 i9xx_compute_dpll(crtc, crtc_state, NULL);
7980
7981 return 0;
7982 }
7983
7984 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7985 struct intel_crtc_state *crtc_state)
7986 {
7987 struct drm_device *dev = crtc->base.dev;
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7989 const struct intel_limit *limit;
7990 int refclk = 96000;
7991
7992 memset(&crtc_state->dpll_hw_state, 0,
7993 sizeof(crtc_state->dpll_hw_state));
7994
7995 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7996 if (intel_panel_use_ssc(dev_priv)) {
7997 refclk = dev_priv->vbt.lvds_ssc_freq;
7998 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7999 }
8000
8001 limit = &intel_limits_pineview_lvds;
8002 } else {
8003 limit = &intel_limits_pineview_sdvo;
8004 }
8005
8006 if (!crtc_state->clock_set &&
8007 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8008 refclk, NULL, &crtc_state->dpll)) {
8009 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8010 return -EINVAL;
8011 }
8012
8013 i9xx_compute_dpll(crtc, crtc_state, NULL);
8014
8015 return 0;
8016 }
8017
8018 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8019 struct intel_crtc_state *crtc_state)
8020 {
8021 struct drm_device *dev = crtc->base.dev;
8022 struct drm_i915_private *dev_priv = dev->dev_private;
8023 const struct intel_limit *limit;
8024 int refclk = 96000;
8025
8026 memset(&crtc_state->dpll_hw_state, 0,
8027 sizeof(crtc_state->dpll_hw_state));
8028
8029 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8030 if (intel_panel_use_ssc(dev_priv)) {
8031 refclk = dev_priv->vbt.lvds_ssc_freq;
8032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8033 }
8034
8035 limit = &intel_limits_i9xx_lvds;
8036 } else {
8037 limit = &intel_limits_i9xx_sdvo;
8038 }
8039
8040 if (!crtc_state->clock_set &&
8041 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8042 refclk, NULL, &crtc_state->dpll)) {
8043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8044 return -EINVAL;
8045 }
8046
8047 i9xx_compute_dpll(crtc, crtc_state, NULL);
8048
8049 return 0;
8050 }
8051
8052 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8053 struct intel_crtc_state *crtc_state)
8054 {
8055 int refclk = 100000;
8056 const struct intel_limit *limit = &intel_limits_chv;
8057
8058 memset(&crtc_state->dpll_hw_state, 0,
8059 sizeof(crtc_state->dpll_hw_state));
8060
8061 if (!crtc_state->clock_set &&
8062 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8063 refclk, NULL, &crtc_state->dpll)) {
8064 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8065 return -EINVAL;
8066 }
8067
8068 chv_compute_dpll(crtc, crtc_state);
8069
8070 return 0;
8071 }
8072
8073 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8074 struct intel_crtc_state *crtc_state)
8075 {
8076 int refclk = 100000;
8077 const struct intel_limit *limit = &intel_limits_vlv;
8078
8079 memset(&crtc_state->dpll_hw_state, 0,
8080 sizeof(crtc_state->dpll_hw_state));
8081
8082 if (!crtc_state->clock_set &&
8083 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8084 refclk, NULL, &crtc_state->dpll)) {
8085 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8086 return -EINVAL;
8087 }
8088
8089 vlv_compute_dpll(crtc, crtc_state);
8090
8091 return 0;
8092 }
8093
8094 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8095 struct intel_crtc_state *pipe_config)
8096 {
8097 struct drm_device *dev = crtc->base.dev;
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 uint32_t tmp;
8100
8101 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8102 return;
8103
8104 tmp = I915_READ(PFIT_CONTROL);
8105 if (!(tmp & PFIT_ENABLE))
8106 return;
8107
8108 /* Check whether the pfit is attached to our pipe. */
8109 if (INTEL_INFO(dev)->gen < 4) {
8110 if (crtc->pipe != PIPE_B)
8111 return;
8112 } else {
8113 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8114 return;
8115 }
8116
8117 pipe_config->gmch_pfit.control = tmp;
8118 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8119 }
8120
8121 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8122 struct intel_crtc_state *pipe_config)
8123 {
8124 struct drm_device *dev = crtc->base.dev;
8125 struct drm_i915_private *dev_priv = dev->dev_private;
8126 int pipe = pipe_config->cpu_transcoder;
8127 struct dpll clock;
8128 u32 mdiv;
8129 int refclk = 100000;
8130
8131 /* In case of DSI, DPLL will not be used */
8132 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8133 return;
8134
8135 mutex_lock(&dev_priv->sb_lock);
8136 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8137 mutex_unlock(&dev_priv->sb_lock);
8138
8139 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8140 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8141 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8142 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8143 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8144
8145 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8146 }
8147
8148 static void
8149 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8150 struct intel_initial_plane_config *plane_config)
8151 {
8152 struct drm_device *dev = crtc->base.dev;
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8154 u32 val, base, offset;
8155 int pipe = crtc->pipe, plane = crtc->plane;
8156 int fourcc, pixel_format;
8157 unsigned int aligned_height;
8158 struct drm_framebuffer *fb;
8159 struct intel_framebuffer *intel_fb;
8160
8161 val = I915_READ(DSPCNTR(plane));
8162 if (!(val & DISPLAY_PLANE_ENABLE))
8163 return;
8164
8165 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8166 if (!intel_fb) {
8167 DRM_DEBUG_KMS("failed to alloc fb\n");
8168 return;
8169 }
8170
8171 fb = &intel_fb->base;
8172
8173 if (INTEL_INFO(dev)->gen >= 4) {
8174 if (val & DISPPLANE_TILED) {
8175 plane_config->tiling = I915_TILING_X;
8176 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8177 }
8178 }
8179
8180 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8181 fourcc = i9xx_format_to_fourcc(pixel_format);
8182 fb->pixel_format = fourcc;
8183 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8184
8185 if (INTEL_INFO(dev)->gen >= 4) {
8186 if (plane_config->tiling)
8187 offset = I915_READ(DSPTILEOFF(plane));
8188 else
8189 offset = I915_READ(DSPLINOFF(plane));
8190 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8191 } else {
8192 base = I915_READ(DSPADDR(plane));
8193 }
8194 plane_config->base = base;
8195
8196 val = I915_READ(PIPESRC(pipe));
8197 fb->width = ((val >> 16) & 0xfff) + 1;
8198 fb->height = ((val >> 0) & 0xfff) + 1;
8199
8200 val = I915_READ(DSPSTRIDE(pipe));
8201 fb->pitches[0] = val & 0xffffffc0;
8202
8203 aligned_height = intel_fb_align_height(dev, fb->height,
8204 fb->pixel_format,
8205 fb->modifier[0]);
8206
8207 plane_config->size = fb->pitches[0] * aligned_height;
8208
8209 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8210 pipe_name(pipe), plane, fb->width, fb->height,
8211 fb->bits_per_pixel, base, fb->pitches[0],
8212 plane_config->size);
8213
8214 plane_config->fb = intel_fb;
8215 }
8216
8217 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8218 struct intel_crtc_state *pipe_config)
8219 {
8220 struct drm_device *dev = crtc->base.dev;
8221 struct drm_i915_private *dev_priv = dev->dev_private;
8222 int pipe = pipe_config->cpu_transcoder;
8223 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8224 struct dpll clock;
8225 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8226 int refclk = 100000;
8227
8228 /* In case of DSI, DPLL will not be used */
8229 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8230 return;
8231
8232 mutex_lock(&dev_priv->sb_lock);
8233 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8234 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8235 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8236 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8237 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8238 mutex_unlock(&dev_priv->sb_lock);
8239
8240 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8241 clock.m2 = (pll_dw0 & 0xff) << 22;
8242 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8243 clock.m2 |= pll_dw2 & 0x3fffff;
8244 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8245 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8246 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8247
8248 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8249 }
8250
8251 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8252 struct intel_crtc_state *pipe_config)
8253 {
8254 struct drm_device *dev = crtc->base.dev;
8255 struct drm_i915_private *dev_priv = dev->dev_private;
8256 enum intel_display_power_domain power_domain;
8257 uint32_t tmp;
8258 bool ret;
8259
8260 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8261 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8262 return false;
8263
8264 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8265 pipe_config->shared_dpll = NULL;
8266
8267 ret = false;
8268
8269 tmp = I915_READ(PIPECONF(crtc->pipe));
8270 if (!(tmp & PIPECONF_ENABLE))
8271 goto out;
8272
8273 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8274 switch (tmp & PIPECONF_BPC_MASK) {
8275 case PIPECONF_6BPC:
8276 pipe_config->pipe_bpp = 18;
8277 break;
8278 case PIPECONF_8BPC:
8279 pipe_config->pipe_bpp = 24;
8280 break;
8281 case PIPECONF_10BPC:
8282 pipe_config->pipe_bpp = 30;
8283 break;
8284 default:
8285 break;
8286 }
8287 }
8288
8289 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8290 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8291 pipe_config->limited_color_range = true;
8292
8293 if (INTEL_INFO(dev)->gen < 4)
8294 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8295
8296 intel_get_pipe_timings(crtc, pipe_config);
8297 intel_get_pipe_src_size(crtc, pipe_config);
8298
8299 i9xx_get_pfit_config(crtc, pipe_config);
8300
8301 if (INTEL_INFO(dev)->gen >= 4) {
8302 /* No way to read it out on pipes B and C */
8303 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8304 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8305 else
8306 tmp = I915_READ(DPLL_MD(crtc->pipe));
8307 pipe_config->pixel_multiplier =
8308 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8309 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8310 pipe_config->dpll_hw_state.dpll_md = tmp;
8311 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8312 tmp = I915_READ(DPLL(crtc->pipe));
8313 pipe_config->pixel_multiplier =
8314 ((tmp & SDVO_MULTIPLIER_MASK)
8315 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8316 } else {
8317 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8318 * port and will be fixed up in the encoder->get_config
8319 * function. */
8320 pipe_config->pixel_multiplier = 1;
8321 }
8322 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8323 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8324 /*
8325 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8326 * on 830. Filter it out here so that we don't
8327 * report errors due to that.
8328 */
8329 if (IS_I830(dev))
8330 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8331
8332 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8333 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8334 } else {
8335 /* Mask out read-only status bits. */
8336 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8337 DPLL_PORTC_READY_MASK |
8338 DPLL_PORTB_READY_MASK);
8339 }
8340
8341 if (IS_CHERRYVIEW(dev))
8342 chv_crtc_clock_get(crtc, pipe_config);
8343 else if (IS_VALLEYVIEW(dev))
8344 vlv_crtc_clock_get(crtc, pipe_config);
8345 else
8346 i9xx_crtc_clock_get(crtc, pipe_config);
8347
8348 /*
8349 * Normally the dotclock is filled in by the encoder .get_config()
8350 * but in case the pipe is enabled w/o any ports we need a sane
8351 * default.
8352 */
8353 pipe_config->base.adjusted_mode.crtc_clock =
8354 pipe_config->port_clock / pipe_config->pixel_multiplier;
8355
8356 ret = true;
8357
8358 out:
8359 intel_display_power_put(dev_priv, power_domain);
8360
8361 return ret;
8362 }
8363
8364 static void ironlake_init_pch_refclk(struct drm_device *dev)
8365 {
8366 struct drm_i915_private *dev_priv = dev->dev_private;
8367 struct intel_encoder *encoder;
8368 int i;
8369 u32 val, final;
8370 bool has_lvds = false;
8371 bool has_cpu_edp = false;
8372 bool has_panel = false;
8373 bool has_ck505 = false;
8374 bool can_ssc = false;
8375 bool using_ssc_source = false;
8376
8377 /* We need to take the global config into account */
8378 for_each_intel_encoder(dev, encoder) {
8379 switch (encoder->type) {
8380 case INTEL_OUTPUT_LVDS:
8381 has_panel = true;
8382 has_lvds = true;
8383 break;
8384 case INTEL_OUTPUT_EDP:
8385 has_panel = true;
8386 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8387 has_cpu_edp = true;
8388 break;
8389 default:
8390 break;
8391 }
8392 }
8393
8394 if (HAS_PCH_IBX(dev)) {
8395 has_ck505 = dev_priv->vbt.display_clock_mode;
8396 can_ssc = has_ck505;
8397 } else {
8398 has_ck505 = false;
8399 can_ssc = true;
8400 }
8401
8402 /* Check if any DPLLs are using the SSC source */
8403 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8404 u32 temp = I915_READ(PCH_DPLL(i));
8405
8406 if (!(temp & DPLL_VCO_ENABLE))
8407 continue;
8408
8409 if ((temp & PLL_REF_INPUT_MASK) ==
8410 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8411 using_ssc_source = true;
8412 break;
8413 }
8414 }
8415
8416 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8417 has_panel, has_lvds, has_ck505, using_ssc_source);
8418
8419 /* Ironlake: try to setup display ref clock before DPLL
8420 * enabling. This is only under driver's control after
8421 * PCH B stepping, previous chipset stepping should be
8422 * ignoring this setting.
8423 */
8424 val = I915_READ(PCH_DREF_CONTROL);
8425
8426 /* As we must carefully and slowly disable/enable each source in turn,
8427 * compute the final state we want first and check if we need to
8428 * make any changes at all.
8429 */
8430 final = val;
8431 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8432 if (has_ck505)
8433 final |= DREF_NONSPREAD_CK505_ENABLE;
8434 else
8435 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8436
8437 final &= ~DREF_SSC_SOURCE_MASK;
8438 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8439 final &= ~DREF_SSC1_ENABLE;
8440
8441 if (has_panel) {
8442 final |= DREF_SSC_SOURCE_ENABLE;
8443
8444 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8445 final |= DREF_SSC1_ENABLE;
8446
8447 if (has_cpu_edp) {
8448 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8449 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8450 else
8451 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8452 } else
8453 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8454 } else if (using_ssc_source) {
8455 final |= DREF_SSC_SOURCE_ENABLE;
8456 final |= DREF_SSC1_ENABLE;
8457 }
8458
8459 if (final == val)
8460 return;
8461
8462 /* Always enable nonspread source */
8463 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8464
8465 if (has_ck505)
8466 val |= DREF_NONSPREAD_CK505_ENABLE;
8467 else
8468 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8469
8470 if (has_panel) {
8471 val &= ~DREF_SSC_SOURCE_MASK;
8472 val |= DREF_SSC_SOURCE_ENABLE;
8473
8474 /* SSC must be turned on before enabling the CPU output */
8475 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8476 DRM_DEBUG_KMS("Using SSC on panel\n");
8477 val |= DREF_SSC1_ENABLE;
8478 } else
8479 val &= ~DREF_SSC1_ENABLE;
8480
8481 /* Get SSC going before enabling the outputs */
8482 I915_WRITE(PCH_DREF_CONTROL, val);
8483 POSTING_READ(PCH_DREF_CONTROL);
8484 udelay(200);
8485
8486 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8487
8488 /* Enable CPU source on CPU attached eDP */
8489 if (has_cpu_edp) {
8490 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8491 DRM_DEBUG_KMS("Using SSC on eDP\n");
8492 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8493 } else
8494 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8495 } else
8496 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8497
8498 I915_WRITE(PCH_DREF_CONTROL, val);
8499 POSTING_READ(PCH_DREF_CONTROL);
8500 udelay(200);
8501 } else {
8502 DRM_DEBUG_KMS("Disabling CPU source output\n");
8503
8504 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8505
8506 /* Turn off CPU output */
8507 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8508
8509 I915_WRITE(PCH_DREF_CONTROL, val);
8510 POSTING_READ(PCH_DREF_CONTROL);
8511 udelay(200);
8512
8513 if (!using_ssc_source) {
8514 DRM_DEBUG_KMS("Disabling SSC source\n");
8515
8516 /* Turn off the SSC source */
8517 val &= ~DREF_SSC_SOURCE_MASK;
8518 val |= DREF_SSC_SOURCE_DISABLE;
8519
8520 /* Turn off SSC1 */
8521 val &= ~DREF_SSC1_ENABLE;
8522
8523 I915_WRITE(PCH_DREF_CONTROL, val);
8524 POSTING_READ(PCH_DREF_CONTROL);
8525 udelay(200);
8526 }
8527 }
8528
8529 BUG_ON(val != final);
8530 }
8531
8532 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8533 {
8534 uint32_t tmp;
8535
8536 tmp = I915_READ(SOUTH_CHICKEN2);
8537 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8538 I915_WRITE(SOUTH_CHICKEN2, tmp);
8539
8540 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8541 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8542 DRM_ERROR("FDI mPHY reset assert timeout\n");
8543
8544 tmp = I915_READ(SOUTH_CHICKEN2);
8545 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8546 I915_WRITE(SOUTH_CHICKEN2, tmp);
8547
8548 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8549 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8550 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8551 }
8552
8553 /* WaMPhyProgramming:hsw */
8554 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8555 {
8556 uint32_t tmp;
8557
8558 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8559 tmp &= ~(0xFF << 24);
8560 tmp |= (0x12 << 24);
8561 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8562
8563 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8564 tmp |= (1 << 11);
8565 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8566
8567 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8568 tmp |= (1 << 11);
8569 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8570
8571 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8572 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8573 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8574
8575 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8576 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8577 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8578
8579 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8580 tmp &= ~(7 << 13);
8581 tmp |= (5 << 13);
8582 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8583
8584 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8585 tmp &= ~(7 << 13);
8586 tmp |= (5 << 13);
8587 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8588
8589 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8590 tmp &= ~0xFF;
8591 tmp |= 0x1C;
8592 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8593
8594 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8595 tmp &= ~0xFF;
8596 tmp |= 0x1C;
8597 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8598
8599 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8600 tmp &= ~(0xFF << 16);
8601 tmp |= (0x1C << 16);
8602 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8603
8604 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8605 tmp &= ~(0xFF << 16);
8606 tmp |= (0x1C << 16);
8607 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8608
8609 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8610 tmp |= (1 << 27);
8611 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8612
8613 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8614 tmp |= (1 << 27);
8615 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8616
8617 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8618 tmp &= ~(0xF << 28);
8619 tmp |= (4 << 28);
8620 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8621
8622 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8623 tmp &= ~(0xF << 28);
8624 tmp |= (4 << 28);
8625 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8626 }
8627
8628 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8629 * Programming" based on the parameters passed:
8630 * - Sequence to enable CLKOUT_DP
8631 * - Sequence to enable CLKOUT_DP without spread
8632 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8633 */
8634 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8635 bool with_fdi)
8636 {
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 uint32_t reg, tmp;
8639
8640 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8641 with_spread = true;
8642 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8643 with_fdi = false;
8644
8645 mutex_lock(&dev_priv->sb_lock);
8646
8647 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8648 tmp &= ~SBI_SSCCTL_DISABLE;
8649 tmp |= SBI_SSCCTL_PATHALT;
8650 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8651
8652 udelay(24);
8653
8654 if (with_spread) {
8655 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8656 tmp &= ~SBI_SSCCTL_PATHALT;
8657 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8658
8659 if (with_fdi) {
8660 lpt_reset_fdi_mphy(dev_priv);
8661 lpt_program_fdi_mphy(dev_priv);
8662 }
8663 }
8664
8665 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8666 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8667 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8668 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8669
8670 mutex_unlock(&dev_priv->sb_lock);
8671 }
8672
8673 /* Sequence to disable CLKOUT_DP */
8674 static void lpt_disable_clkout_dp(struct drm_device *dev)
8675 {
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 uint32_t reg, tmp;
8678
8679 mutex_lock(&dev_priv->sb_lock);
8680
8681 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8682 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8683 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8684 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8685
8686 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8687 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8688 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8689 tmp |= SBI_SSCCTL_PATHALT;
8690 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8691 udelay(32);
8692 }
8693 tmp |= SBI_SSCCTL_DISABLE;
8694 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8695 }
8696
8697 mutex_unlock(&dev_priv->sb_lock);
8698 }
8699
8700 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8701
8702 static const uint16_t sscdivintphase[] = {
8703 [BEND_IDX( 50)] = 0x3B23,
8704 [BEND_IDX( 45)] = 0x3B23,
8705 [BEND_IDX( 40)] = 0x3C23,
8706 [BEND_IDX( 35)] = 0x3C23,
8707 [BEND_IDX( 30)] = 0x3D23,
8708 [BEND_IDX( 25)] = 0x3D23,
8709 [BEND_IDX( 20)] = 0x3E23,
8710 [BEND_IDX( 15)] = 0x3E23,
8711 [BEND_IDX( 10)] = 0x3F23,
8712 [BEND_IDX( 5)] = 0x3F23,
8713 [BEND_IDX( 0)] = 0x0025,
8714 [BEND_IDX( -5)] = 0x0025,
8715 [BEND_IDX(-10)] = 0x0125,
8716 [BEND_IDX(-15)] = 0x0125,
8717 [BEND_IDX(-20)] = 0x0225,
8718 [BEND_IDX(-25)] = 0x0225,
8719 [BEND_IDX(-30)] = 0x0325,
8720 [BEND_IDX(-35)] = 0x0325,
8721 [BEND_IDX(-40)] = 0x0425,
8722 [BEND_IDX(-45)] = 0x0425,
8723 [BEND_IDX(-50)] = 0x0525,
8724 };
8725
8726 /*
8727 * Bend CLKOUT_DP
8728 * steps -50 to 50 inclusive, in steps of 5
8729 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8730 * change in clock period = -(steps / 10) * 5.787 ps
8731 */
8732 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8733 {
8734 uint32_t tmp;
8735 int idx = BEND_IDX(steps);
8736
8737 if (WARN_ON(steps % 5 != 0))
8738 return;
8739
8740 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8741 return;
8742
8743 mutex_lock(&dev_priv->sb_lock);
8744
8745 if (steps % 10 != 0)
8746 tmp = 0xAAAAAAAB;
8747 else
8748 tmp = 0x00000000;
8749 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8750
8751 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8752 tmp &= 0xffff0000;
8753 tmp |= sscdivintphase[idx];
8754 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8755
8756 mutex_unlock(&dev_priv->sb_lock);
8757 }
8758
8759 #undef BEND_IDX
8760
8761 static void lpt_init_pch_refclk(struct drm_device *dev)
8762 {
8763 struct intel_encoder *encoder;
8764 bool has_vga = false;
8765
8766 for_each_intel_encoder(dev, encoder) {
8767 switch (encoder->type) {
8768 case INTEL_OUTPUT_ANALOG:
8769 has_vga = true;
8770 break;
8771 default:
8772 break;
8773 }
8774 }
8775
8776 if (has_vga) {
8777 lpt_bend_clkout_dp(to_i915(dev), 0);
8778 lpt_enable_clkout_dp(dev, true, true);
8779 } else {
8780 lpt_disable_clkout_dp(dev);
8781 }
8782 }
8783
8784 /*
8785 * Initialize reference clocks when the driver loads
8786 */
8787 void intel_init_pch_refclk(struct drm_device *dev)
8788 {
8789 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8790 ironlake_init_pch_refclk(dev);
8791 else if (HAS_PCH_LPT(dev))
8792 lpt_init_pch_refclk(dev);
8793 }
8794
8795 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8796 {
8797 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8799 int pipe = intel_crtc->pipe;
8800 uint32_t val;
8801
8802 val = 0;
8803
8804 switch (intel_crtc->config->pipe_bpp) {
8805 case 18:
8806 val |= PIPECONF_6BPC;
8807 break;
8808 case 24:
8809 val |= PIPECONF_8BPC;
8810 break;
8811 case 30:
8812 val |= PIPECONF_10BPC;
8813 break;
8814 case 36:
8815 val |= PIPECONF_12BPC;
8816 break;
8817 default:
8818 /* Case prevented by intel_choose_pipe_bpp_dither. */
8819 BUG();
8820 }
8821
8822 if (intel_crtc->config->dither)
8823 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8824
8825 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8826 val |= PIPECONF_INTERLACED_ILK;
8827 else
8828 val |= PIPECONF_PROGRESSIVE;
8829
8830 if (intel_crtc->config->limited_color_range)
8831 val |= PIPECONF_COLOR_RANGE_SELECT;
8832
8833 I915_WRITE(PIPECONF(pipe), val);
8834 POSTING_READ(PIPECONF(pipe));
8835 }
8836
8837 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8838 {
8839 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8841 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8842 u32 val = 0;
8843
8844 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8845 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8846
8847 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8848 val |= PIPECONF_INTERLACED_ILK;
8849 else
8850 val |= PIPECONF_PROGRESSIVE;
8851
8852 I915_WRITE(PIPECONF(cpu_transcoder), val);
8853 POSTING_READ(PIPECONF(cpu_transcoder));
8854 }
8855
8856 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8857 {
8858 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8860
8861 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8862 u32 val = 0;
8863
8864 switch (intel_crtc->config->pipe_bpp) {
8865 case 18:
8866 val |= PIPEMISC_DITHER_6_BPC;
8867 break;
8868 case 24:
8869 val |= PIPEMISC_DITHER_8_BPC;
8870 break;
8871 case 30:
8872 val |= PIPEMISC_DITHER_10_BPC;
8873 break;
8874 case 36:
8875 val |= PIPEMISC_DITHER_12_BPC;
8876 break;
8877 default:
8878 /* Case prevented by pipe_config_set_bpp. */
8879 BUG();
8880 }
8881
8882 if (intel_crtc->config->dither)
8883 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8884
8885 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8886 }
8887 }
8888
8889 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8890 {
8891 /*
8892 * Account for spread spectrum to avoid
8893 * oversubscribing the link. Max center spread
8894 * is 2.5%; use 5% for safety's sake.
8895 */
8896 u32 bps = target_clock * bpp * 21 / 20;
8897 return DIV_ROUND_UP(bps, link_bw * 8);
8898 }
8899
8900 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8901 {
8902 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8903 }
8904
8905 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8906 struct intel_crtc_state *crtc_state,
8907 struct dpll *reduced_clock)
8908 {
8909 struct drm_crtc *crtc = &intel_crtc->base;
8910 struct drm_device *dev = crtc->dev;
8911 struct drm_i915_private *dev_priv = dev->dev_private;
8912 struct drm_atomic_state *state = crtc_state->base.state;
8913 struct drm_connector *connector;
8914 struct drm_connector_state *connector_state;
8915 struct intel_encoder *encoder;
8916 u32 dpll, fp, fp2;
8917 int factor, i;
8918 bool is_lvds = false, is_sdvo = false;
8919
8920 for_each_connector_in_state(state, connector, connector_state, i) {
8921 if (connector_state->crtc != crtc_state->base.crtc)
8922 continue;
8923
8924 encoder = to_intel_encoder(connector_state->best_encoder);
8925
8926 switch (encoder->type) {
8927 case INTEL_OUTPUT_LVDS:
8928 is_lvds = true;
8929 break;
8930 case INTEL_OUTPUT_SDVO:
8931 case INTEL_OUTPUT_HDMI:
8932 is_sdvo = true;
8933 break;
8934 default:
8935 break;
8936 }
8937 }
8938
8939 /* Enable autotuning of the PLL clock (if permissible) */
8940 factor = 21;
8941 if (is_lvds) {
8942 if ((intel_panel_use_ssc(dev_priv) &&
8943 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8944 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8945 factor = 25;
8946 } else if (crtc_state->sdvo_tv_clock)
8947 factor = 20;
8948
8949 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8950
8951 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8952 fp |= FP_CB_TUNE;
8953
8954 if (reduced_clock) {
8955 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8956
8957 if (reduced_clock->m < factor * reduced_clock->n)
8958 fp2 |= FP_CB_TUNE;
8959 } else {
8960 fp2 = fp;
8961 }
8962
8963 dpll = 0;
8964
8965 if (is_lvds)
8966 dpll |= DPLLB_MODE_LVDS;
8967 else
8968 dpll |= DPLLB_MODE_DAC_SERIAL;
8969
8970 dpll |= (crtc_state->pixel_multiplier - 1)
8971 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8972
8973 if (is_sdvo)
8974 dpll |= DPLL_SDVO_HIGH_SPEED;
8975 if (crtc_state->has_dp_encoder)
8976 dpll |= DPLL_SDVO_HIGH_SPEED;
8977
8978 /* compute bitmask from p1 value */
8979 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8980 /* also FPA1 */
8981 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8982
8983 switch (crtc_state->dpll.p2) {
8984 case 5:
8985 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8986 break;
8987 case 7:
8988 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8989 break;
8990 case 10:
8991 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8992 break;
8993 case 14:
8994 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8995 break;
8996 }
8997
8998 if (is_lvds && intel_panel_use_ssc(dev_priv))
8999 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9000 else
9001 dpll |= PLL_REF_INPUT_DREFCLK;
9002
9003 dpll |= DPLL_VCO_ENABLE;
9004
9005 crtc_state->dpll_hw_state.dpll = dpll;
9006 crtc_state->dpll_hw_state.fp0 = fp;
9007 crtc_state->dpll_hw_state.fp1 = fp2;
9008 }
9009
9010 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9011 struct intel_crtc_state *crtc_state)
9012 {
9013 struct drm_device *dev = crtc->base.dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private;
9015 struct dpll reduced_clock;
9016 bool has_reduced_clock = false;
9017 struct intel_shared_dpll *pll;
9018 const struct intel_limit *limit;
9019 int refclk = 120000;
9020
9021 memset(&crtc_state->dpll_hw_state, 0,
9022 sizeof(crtc_state->dpll_hw_state));
9023
9024 crtc->lowfreq_avail = false;
9025
9026 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9027 if (!crtc_state->has_pch_encoder)
9028 return 0;
9029
9030 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9031 if (intel_panel_use_ssc(dev_priv)) {
9032 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9033 dev_priv->vbt.lvds_ssc_freq);
9034 refclk = dev_priv->vbt.lvds_ssc_freq;
9035 }
9036
9037 if (intel_is_dual_link_lvds(dev)) {
9038 if (refclk == 100000)
9039 limit = &intel_limits_ironlake_dual_lvds_100m;
9040 else
9041 limit = &intel_limits_ironlake_dual_lvds;
9042 } else {
9043 if (refclk == 100000)
9044 limit = &intel_limits_ironlake_single_lvds_100m;
9045 else
9046 limit = &intel_limits_ironlake_single_lvds;
9047 }
9048 } else {
9049 limit = &intel_limits_ironlake_dac;
9050 }
9051
9052 if (!crtc_state->clock_set &&
9053 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9054 refclk, NULL, &crtc_state->dpll)) {
9055 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9056 return -EINVAL;
9057 }
9058
9059 ironlake_compute_dpll(crtc, crtc_state,
9060 has_reduced_clock ? &reduced_clock : NULL);
9061
9062 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9063 if (pll == NULL) {
9064 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9065 pipe_name(crtc->pipe));
9066 return -EINVAL;
9067 }
9068
9069 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9070 has_reduced_clock)
9071 crtc->lowfreq_avail = true;
9072
9073 return 0;
9074 }
9075
9076 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9077 struct intel_link_m_n *m_n)
9078 {
9079 struct drm_device *dev = crtc->base.dev;
9080 struct drm_i915_private *dev_priv = dev->dev_private;
9081 enum pipe pipe = crtc->pipe;
9082
9083 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9084 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9085 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9086 & ~TU_SIZE_MASK;
9087 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9088 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9089 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9090 }
9091
9092 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9093 enum transcoder transcoder,
9094 struct intel_link_m_n *m_n,
9095 struct intel_link_m_n *m2_n2)
9096 {
9097 struct drm_device *dev = crtc->base.dev;
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9099 enum pipe pipe = crtc->pipe;
9100
9101 if (INTEL_INFO(dev)->gen >= 5) {
9102 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9103 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9104 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9105 & ~TU_SIZE_MASK;
9106 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9107 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9108 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9109 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9110 * gen < 8) and if DRRS is supported (to make sure the
9111 * registers are not unnecessarily read).
9112 */
9113 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9114 crtc->config->has_drrs) {
9115 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9116 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9117 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9118 & ~TU_SIZE_MASK;
9119 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9120 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9121 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9122 }
9123 } else {
9124 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9125 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9126 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9127 & ~TU_SIZE_MASK;
9128 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9129 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9130 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9131 }
9132 }
9133
9134 void intel_dp_get_m_n(struct intel_crtc *crtc,
9135 struct intel_crtc_state *pipe_config)
9136 {
9137 if (pipe_config->has_pch_encoder)
9138 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9139 else
9140 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9141 &pipe_config->dp_m_n,
9142 &pipe_config->dp_m2_n2);
9143 }
9144
9145 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9146 struct intel_crtc_state *pipe_config)
9147 {
9148 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9149 &pipe_config->fdi_m_n, NULL);
9150 }
9151
9152 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9153 struct intel_crtc_state *pipe_config)
9154 {
9155 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9158 uint32_t ps_ctrl = 0;
9159 int id = -1;
9160 int i;
9161
9162 /* find scaler attached to this pipe */
9163 for (i = 0; i < crtc->num_scalers; i++) {
9164 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9165 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9166 id = i;
9167 pipe_config->pch_pfit.enabled = true;
9168 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9169 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9170 break;
9171 }
9172 }
9173
9174 scaler_state->scaler_id = id;
9175 if (id >= 0) {
9176 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9177 } else {
9178 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9179 }
9180 }
9181
9182 static void
9183 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9184 struct intel_initial_plane_config *plane_config)
9185 {
9186 struct drm_device *dev = crtc->base.dev;
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 u32 val, base, offset, stride_mult, tiling;
9189 int pipe = crtc->pipe;
9190 int fourcc, pixel_format;
9191 unsigned int aligned_height;
9192 struct drm_framebuffer *fb;
9193 struct intel_framebuffer *intel_fb;
9194
9195 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9196 if (!intel_fb) {
9197 DRM_DEBUG_KMS("failed to alloc fb\n");
9198 return;
9199 }
9200
9201 fb = &intel_fb->base;
9202
9203 val = I915_READ(PLANE_CTL(pipe, 0));
9204 if (!(val & PLANE_CTL_ENABLE))
9205 goto error;
9206
9207 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9208 fourcc = skl_format_to_fourcc(pixel_format,
9209 val & PLANE_CTL_ORDER_RGBX,
9210 val & PLANE_CTL_ALPHA_MASK);
9211 fb->pixel_format = fourcc;
9212 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9213
9214 tiling = val & PLANE_CTL_TILED_MASK;
9215 switch (tiling) {
9216 case PLANE_CTL_TILED_LINEAR:
9217 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9218 break;
9219 case PLANE_CTL_TILED_X:
9220 plane_config->tiling = I915_TILING_X;
9221 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9222 break;
9223 case PLANE_CTL_TILED_Y:
9224 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9225 break;
9226 case PLANE_CTL_TILED_YF:
9227 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9228 break;
9229 default:
9230 MISSING_CASE(tiling);
9231 goto error;
9232 }
9233
9234 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9235 plane_config->base = base;
9236
9237 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9238
9239 val = I915_READ(PLANE_SIZE(pipe, 0));
9240 fb->height = ((val >> 16) & 0xfff) + 1;
9241 fb->width = ((val >> 0) & 0x1fff) + 1;
9242
9243 val = I915_READ(PLANE_STRIDE(pipe, 0));
9244 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9245 fb->pixel_format);
9246 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9247
9248 aligned_height = intel_fb_align_height(dev, fb->height,
9249 fb->pixel_format,
9250 fb->modifier[0]);
9251
9252 plane_config->size = fb->pitches[0] * aligned_height;
9253
9254 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9255 pipe_name(pipe), fb->width, fb->height,
9256 fb->bits_per_pixel, base, fb->pitches[0],
9257 plane_config->size);
9258
9259 plane_config->fb = intel_fb;
9260 return;
9261
9262 error:
9263 kfree(fb);
9264 }
9265
9266 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9267 struct intel_crtc_state *pipe_config)
9268 {
9269 struct drm_device *dev = crtc->base.dev;
9270 struct drm_i915_private *dev_priv = dev->dev_private;
9271 uint32_t tmp;
9272
9273 tmp = I915_READ(PF_CTL(crtc->pipe));
9274
9275 if (tmp & PF_ENABLE) {
9276 pipe_config->pch_pfit.enabled = true;
9277 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9278 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9279
9280 /* We currently do not free assignements of panel fitters on
9281 * ivb/hsw (since we don't use the higher upscaling modes which
9282 * differentiates them) so just WARN about this case for now. */
9283 if (IS_GEN7(dev)) {
9284 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9285 PF_PIPE_SEL_IVB(crtc->pipe));
9286 }
9287 }
9288 }
9289
9290 static void
9291 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9292 struct intel_initial_plane_config *plane_config)
9293 {
9294 struct drm_device *dev = crtc->base.dev;
9295 struct drm_i915_private *dev_priv = dev->dev_private;
9296 u32 val, base, offset;
9297 int pipe = crtc->pipe;
9298 int fourcc, pixel_format;
9299 unsigned int aligned_height;
9300 struct drm_framebuffer *fb;
9301 struct intel_framebuffer *intel_fb;
9302
9303 val = I915_READ(DSPCNTR(pipe));
9304 if (!(val & DISPLAY_PLANE_ENABLE))
9305 return;
9306
9307 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9308 if (!intel_fb) {
9309 DRM_DEBUG_KMS("failed to alloc fb\n");
9310 return;
9311 }
9312
9313 fb = &intel_fb->base;
9314
9315 if (INTEL_INFO(dev)->gen >= 4) {
9316 if (val & DISPPLANE_TILED) {
9317 plane_config->tiling = I915_TILING_X;
9318 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9319 }
9320 }
9321
9322 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9323 fourcc = i9xx_format_to_fourcc(pixel_format);
9324 fb->pixel_format = fourcc;
9325 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9326
9327 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9328 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9329 offset = I915_READ(DSPOFFSET(pipe));
9330 } else {
9331 if (plane_config->tiling)
9332 offset = I915_READ(DSPTILEOFF(pipe));
9333 else
9334 offset = I915_READ(DSPLINOFF(pipe));
9335 }
9336 plane_config->base = base;
9337
9338 val = I915_READ(PIPESRC(pipe));
9339 fb->width = ((val >> 16) & 0xfff) + 1;
9340 fb->height = ((val >> 0) & 0xfff) + 1;
9341
9342 val = I915_READ(DSPSTRIDE(pipe));
9343 fb->pitches[0] = val & 0xffffffc0;
9344
9345 aligned_height = intel_fb_align_height(dev, fb->height,
9346 fb->pixel_format,
9347 fb->modifier[0]);
9348
9349 plane_config->size = fb->pitches[0] * aligned_height;
9350
9351 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9352 pipe_name(pipe), fb->width, fb->height,
9353 fb->bits_per_pixel, base, fb->pitches[0],
9354 plane_config->size);
9355
9356 plane_config->fb = intel_fb;
9357 }
9358
9359 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9360 struct intel_crtc_state *pipe_config)
9361 {
9362 struct drm_device *dev = crtc->base.dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 enum intel_display_power_domain power_domain;
9365 uint32_t tmp;
9366 bool ret;
9367
9368 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9369 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9370 return false;
9371
9372 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9373 pipe_config->shared_dpll = NULL;
9374
9375 ret = false;
9376 tmp = I915_READ(PIPECONF(crtc->pipe));
9377 if (!(tmp & PIPECONF_ENABLE))
9378 goto out;
9379
9380 switch (tmp & PIPECONF_BPC_MASK) {
9381 case PIPECONF_6BPC:
9382 pipe_config->pipe_bpp = 18;
9383 break;
9384 case PIPECONF_8BPC:
9385 pipe_config->pipe_bpp = 24;
9386 break;
9387 case PIPECONF_10BPC:
9388 pipe_config->pipe_bpp = 30;
9389 break;
9390 case PIPECONF_12BPC:
9391 pipe_config->pipe_bpp = 36;
9392 break;
9393 default:
9394 break;
9395 }
9396
9397 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9398 pipe_config->limited_color_range = true;
9399
9400 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9401 struct intel_shared_dpll *pll;
9402 enum intel_dpll_id pll_id;
9403
9404 pipe_config->has_pch_encoder = true;
9405
9406 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9407 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9408 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9409
9410 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9411
9412 if (HAS_PCH_IBX(dev_priv)) {
9413 /*
9414 * The pipe->pch transcoder and pch transcoder->pll
9415 * mapping is fixed.
9416 */
9417 pll_id = (enum intel_dpll_id) crtc->pipe;
9418 } else {
9419 tmp = I915_READ(PCH_DPLL_SEL);
9420 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9421 pll_id = DPLL_ID_PCH_PLL_B;
9422 else
9423 pll_id= DPLL_ID_PCH_PLL_A;
9424 }
9425
9426 pipe_config->shared_dpll =
9427 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9428 pll = pipe_config->shared_dpll;
9429
9430 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9431 &pipe_config->dpll_hw_state));
9432
9433 tmp = pipe_config->dpll_hw_state.dpll;
9434 pipe_config->pixel_multiplier =
9435 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9436 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9437
9438 ironlake_pch_clock_get(crtc, pipe_config);
9439 } else {
9440 pipe_config->pixel_multiplier = 1;
9441 }
9442
9443 intel_get_pipe_timings(crtc, pipe_config);
9444 intel_get_pipe_src_size(crtc, pipe_config);
9445
9446 ironlake_get_pfit_config(crtc, pipe_config);
9447
9448 ret = true;
9449
9450 out:
9451 intel_display_power_put(dev_priv, power_domain);
9452
9453 return ret;
9454 }
9455
9456 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9457 {
9458 struct drm_device *dev = dev_priv->dev;
9459 struct intel_crtc *crtc;
9460
9461 for_each_intel_crtc(dev, crtc)
9462 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9463 pipe_name(crtc->pipe));
9464
9465 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9466 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9467 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9468 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9469 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9470 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9471 "CPU PWM1 enabled\n");
9472 if (IS_HASWELL(dev))
9473 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9474 "CPU PWM2 enabled\n");
9475 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9476 "PCH PWM1 enabled\n");
9477 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9478 "Utility pin enabled\n");
9479 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9480
9481 /*
9482 * In theory we can still leave IRQs enabled, as long as only the HPD
9483 * interrupts remain enabled. We used to check for that, but since it's
9484 * gen-specific and since we only disable LCPLL after we fully disable
9485 * the interrupts, the check below should be enough.
9486 */
9487 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9488 }
9489
9490 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9491 {
9492 struct drm_device *dev = dev_priv->dev;
9493
9494 if (IS_HASWELL(dev))
9495 return I915_READ(D_COMP_HSW);
9496 else
9497 return I915_READ(D_COMP_BDW);
9498 }
9499
9500 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9501 {
9502 struct drm_device *dev = dev_priv->dev;
9503
9504 if (IS_HASWELL(dev)) {
9505 mutex_lock(&dev_priv->rps.hw_lock);
9506 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9507 val))
9508 DRM_ERROR("Failed to write to D_COMP\n");
9509 mutex_unlock(&dev_priv->rps.hw_lock);
9510 } else {
9511 I915_WRITE(D_COMP_BDW, val);
9512 POSTING_READ(D_COMP_BDW);
9513 }
9514 }
9515
9516 /*
9517 * This function implements pieces of two sequences from BSpec:
9518 * - Sequence for display software to disable LCPLL
9519 * - Sequence for display software to allow package C8+
9520 * The steps implemented here are just the steps that actually touch the LCPLL
9521 * register. Callers should take care of disabling all the display engine
9522 * functions, doing the mode unset, fixing interrupts, etc.
9523 */
9524 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9525 bool switch_to_fclk, bool allow_power_down)
9526 {
9527 uint32_t val;
9528
9529 assert_can_disable_lcpll(dev_priv);
9530
9531 val = I915_READ(LCPLL_CTL);
9532
9533 if (switch_to_fclk) {
9534 val |= LCPLL_CD_SOURCE_FCLK;
9535 I915_WRITE(LCPLL_CTL, val);
9536
9537 if (wait_for_us(I915_READ(LCPLL_CTL) &
9538 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9539 DRM_ERROR("Switching to FCLK failed\n");
9540
9541 val = I915_READ(LCPLL_CTL);
9542 }
9543
9544 val |= LCPLL_PLL_DISABLE;
9545 I915_WRITE(LCPLL_CTL, val);
9546 POSTING_READ(LCPLL_CTL);
9547
9548 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9549 DRM_ERROR("LCPLL still locked\n");
9550
9551 val = hsw_read_dcomp(dev_priv);
9552 val |= D_COMP_COMP_DISABLE;
9553 hsw_write_dcomp(dev_priv, val);
9554 ndelay(100);
9555
9556 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9557 1))
9558 DRM_ERROR("D_COMP RCOMP still in progress\n");
9559
9560 if (allow_power_down) {
9561 val = I915_READ(LCPLL_CTL);
9562 val |= LCPLL_POWER_DOWN_ALLOW;
9563 I915_WRITE(LCPLL_CTL, val);
9564 POSTING_READ(LCPLL_CTL);
9565 }
9566 }
9567
9568 /*
9569 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9570 * source.
9571 */
9572 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9573 {
9574 uint32_t val;
9575
9576 val = I915_READ(LCPLL_CTL);
9577
9578 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9579 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9580 return;
9581
9582 /*
9583 * Make sure we're not on PC8 state before disabling PC8, otherwise
9584 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9585 */
9586 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9587
9588 if (val & LCPLL_POWER_DOWN_ALLOW) {
9589 val &= ~LCPLL_POWER_DOWN_ALLOW;
9590 I915_WRITE(LCPLL_CTL, val);
9591 POSTING_READ(LCPLL_CTL);
9592 }
9593
9594 val = hsw_read_dcomp(dev_priv);
9595 val |= D_COMP_COMP_FORCE;
9596 val &= ~D_COMP_COMP_DISABLE;
9597 hsw_write_dcomp(dev_priv, val);
9598
9599 val = I915_READ(LCPLL_CTL);
9600 val &= ~LCPLL_PLL_DISABLE;
9601 I915_WRITE(LCPLL_CTL, val);
9602
9603 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9604 DRM_ERROR("LCPLL not locked yet\n");
9605
9606 if (val & LCPLL_CD_SOURCE_FCLK) {
9607 val = I915_READ(LCPLL_CTL);
9608 val &= ~LCPLL_CD_SOURCE_FCLK;
9609 I915_WRITE(LCPLL_CTL, val);
9610
9611 if (wait_for_us((I915_READ(LCPLL_CTL) &
9612 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9613 DRM_ERROR("Switching back to LCPLL failed\n");
9614 }
9615
9616 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9617 intel_update_cdclk(dev_priv->dev);
9618 }
9619
9620 /*
9621 * Package states C8 and deeper are really deep PC states that can only be
9622 * reached when all the devices on the system allow it, so even if the graphics
9623 * device allows PC8+, it doesn't mean the system will actually get to these
9624 * states. Our driver only allows PC8+ when going into runtime PM.
9625 *
9626 * The requirements for PC8+ are that all the outputs are disabled, the power
9627 * well is disabled and most interrupts are disabled, and these are also
9628 * requirements for runtime PM. When these conditions are met, we manually do
9629 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9630 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9631 * hang the machine.
9632 *
9633 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9634 * the state of some registers, so when we come back from PC8+ we need to
9635 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9636 * need to take care of the registers kept by RC6. Notice that this happens even
9637 * if we don't put the device in PCI D3 state (which is what currently happens
9638 * because of the runtime PM support).
9639 *
9640 * For more, read "Display Sequences for Package C8" on the hardware
9641 * documentation.
9642 */
9643 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9644 {
9645 struct drm_device *dev = dev_priv->dev;
9646 uint32_t val;
9647
9648 DRM_DEBUG_KMS("Enabling package C8+\n");
9649
9650 if (HAS_PCH_LPT_LP(dev)) {
9651 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9652 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9653 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9654 }
9655
9656 lpt_disable_clkout_dp(dev);
9657 hsw_disable_lcpll(dev_priv, true, true);
9658 }
9659
9660 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9661 {
9662 struct drm_device *dev = dev_priv->dev;
9663 uint32_t val;
9664
9665 DRM_DEBUG_KMS("Disabling package C8+\n");
9666
9667 hsw_restore_lcpll(dev_priv);
9668 lpt_init_pch_refclk(dev);
9669
9670 if (HAS_PCH_LPT_LP(dev)) {
9671 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9672 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9673 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9674 }
9675 }
9676
9677 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9678 {
9679 struct drm_device *dev = old_state->dev;
9680 struct intel_atomic_state *old_intel_state =
9681 to_intel_atomic_state(old_state);
9682 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9683
9684 bxt_set_cdclk(to_i915(dev), req_cdclk);
9685 }
9686
9687 /* compute the max rate for new configuration */
9688 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9689 {
9690 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9691 struct drm_i915_private *dev_priv = state->dev->dev_private;
9692 struct drm_crtc *crtc;
9693 struct drm_crtc_state *cstate;
9694 struct intel_crtc_state *crtc_state;
9695 unsigned max_pixel_rate = 0, i;
9696 enum pipe pipe;
9697
9698 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9699 sizeof(intel_state->min_pixclk));
9700
9701 for_each_crtc_in_state(state, crtc, cstate, i) {
9702 int pixel_rate;
9703
9704 crtc_state = to_intel_crtc_state(cstate);
9705 if (!crtc_state->base.enable) {
9706 intel_state->min_pixclk[i] = 0;
9707 continue;
9708 }
9709
9710 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9711
9712 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9713 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9714 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9715
9716 intel_state->min_pixclk[i] = pixel_rate;
9717 }
9718
9719 for_each_pipe(dev_priv, pipe)
9720 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9721
9722 return max_pixel_rate;
9723 }
9724
9725 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9726 {
9727 struct drm_i915_private *dev_priv = dev->dev_private;
9728 uint32_t val, data;
9729 int ret;
9730
9731 if (WARN((I915_READ(LCPLL_CTL) &
9732 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9733 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9734 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9735 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9736 "trying to change cdclk frequency with cdclk not enabled\n"))
9737 return;
9738
9739 mutex_lock(&dev_priv->rps.hw_lock);
9740 ret = sandybridge_pcode_write(dev_priv,
9741 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9742 mutex_unlock(&dev_priv->rps.hw_lock);
9743 if (ret) {
9744 DRM_ERROR("failed to inform pcode about cdclk change\n");
9745 return;
9746 }
9747
9748 val = I915_READ(LCPLL_CTL);
9749 val |= LCPLL_CD_SOURCE_FCLK;
9750 I915_WRITE(LCPLL_CTL, val);
9751
9752 if (wait_for_us(I915_READ(LCPLL_CTL) &
9753 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9754 DRM_ERROR("Switching to FCLK failed\n");
9755
9756 val = I915_READ(LCPLL_CTL);
9757 val &= ~LCPLL_CLK_FREQ_MASK;
9758
9759 switch (cdclk) {
9760 case 450000:
9761 val |= LCPLL_CLK_FREQ_450;
9762 data = 0;
9763 break;
9764 case 540000:
9765 val |= LCPLL_CLK_FREQ_54O_BDW;
9766 data = 1;
9767 break;
9768 case 337500:
9769 val |= LCPLL_CLK_FREQ_337_5_BDW;
9770 data = 2;
9771 break;
9772 case 675000:
9773 val |= LCPLL_CLK_FREQ_675_BDW;
9774 data = 3;
9775 break;
9776 default:
9777 WARN(1, "invalid cdclk frequency\n");
9778 return;
9779 }
9780
9781 I915_WRITE(LCPLL_CTL, val);
9782
9783 val = I915_READ(LCPLL_CTL);
9784 val &= ~LCPLL_CD_SOURCE_FCLK;
9785 I915_WRITE(LCPLL_CTL, val);
9786
9787 if (wait_for_us((I915_READ(LCPLL_CTL) &
9788 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9789 DRM_ERROR("Switching back to LCPLL failed\n");
9790
9791 mutex_lock(&dev_priv->rps.hw_lock);
9792 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9793 mutex_unlock(&dev_priv->rps.hw_lock);
9794
9795 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9796
9797 intel_update_cdclk(dev);
9798
9799 WARN(cdclk != dev_priv->cdclk_freq,
9800 "cdclk requested %d kHz but got %d kHz\n",
9801 cdclk, dev_priv->cdclk_freq);
9802 }
9803
9804 static int broadwell_calc_cdclk(int max_pixclk)
9805 {
9806 if (max_pixclk > 540000)
9807 return 675000;
9808 else if (max_pixclk > 450000)
9809 return 540000;
9810 else if (max_pixclk > 337500)
9811 return 450000;
9812 else
9813 return 337500;
9814 }
9815
9816 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9817 {
9818 struct drm_i915_private *dev_priv = to_i915(state->dev);
9819 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9820 int max_pixclk = ilk_max_pixel_rate(state);
9821 int cdclk;
9822
9823 /*
9824 * FIXME should also account for plane ratio
9825 * once 64bpp pixel formats are supported.
9826 */
9827 cdclk = broadwell_calc_cdclk(max_pixclk);
9828
9829 if (cdclk > dev_priv->max_cdclk_freq) {
9830 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9831 cdclk, dev_priv->max_cdclk_freq);
9832 return -EINVAL;
9833 }
9834
9835 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9836 if (!intel_state->active_crtcs)
9837 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9838
9839 return 0;
9840 }
9841
9842 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9843 {
9844 struct drm_device *dev = old_state->dev;
9845 struct intel_atomic_state *old_intel_state =
9846 to_intel_atomic_state(old_state);
9847 unsigned req_cdclk = old_intel_state->dev_cdclk;
9848
9849 broadwell_set_cdclk(dev, req_cdclk);
9850 }
9851
9852 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9853 {
9854 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9855 struct drm_i915_private *dev_priv = to_i915(state->dev);
9856 const int max_pixclk = ilk_max_pixel_rate(state);
9857 int vco = intel_state->cdclk_pll_vco;
9858 int cdclk;
9859
9860 /*
9861 * FIXME should also account for plane ratio
9862 * once 64bpp pixel formats are supported.
9863 */
9864 cdclk = skl_calc_cdclk(max_pixclk, vco);
9865
9866 /*
9867 * FIXME move the cdclk caclulation to
9868 * compute_config() so we can fail gracegully.
9869 */
9870 if (cdclk > dev_priv->max_cdclk_freq) {
9871 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9872 cdclk, dev_priv->max_cdclk_freq);
9873 cdclk = dev_priv->max_cdclk_freq;
9874 }
9875
9876 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9877 if (!intel_state->active_crtcs)
9878 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9879
9880 return 0;
9881 }
9882
9883 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9884 {
9885 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9886 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9887 unsigned int req_cdclk = intel_state->dev_cdclk;
9888 unsigned int req_vco = intel_state->cdclk_pll_vco;
9889
9890 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9891 }
9892
9893 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9894 struct intel_crtc_state *crtc_state)
9895 {
9896 struct intel_encoder *intel_encoder =
9897 intel_ddi_get_crtc_new_encoder(crtc_state);
9898
9899 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9900 if (!intel_ddi_pll_select(crtc, crtc_state))
9901 return -EINVAL;
9902 }
9903
9904 crtc->lowfreq_avail = false;
9905
9906 return 0;
9907 }
9908
9909 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9910 enum port port,
9911 struct intel_crtc_state *pipe_config)
9912 {
9913 enum intel_dpll_id id;
9914
9915 switch (port) {
9916 case PORT_A:
9917 pipe_config->ddi_pll_sel = SKL_DPLL0;
9918 id = DPLL_ID_SKL_DPLL0;
9919 break;
9920 case PORT_B:
9921 pipe_config->ddi_pll_sel = SKL_DPLL1;
9922 id = DPLL_ID_SKL_DPLL1;
9923 break;
9924 case PORT_C:
9925 pipe_config->ddi_pll_sel = SKL_DPLL2;
9926 id = DPLL_ID_SKL_DPLL2;
9927 break;
9928 default:
9929 DRM_ERROR("Incorrect port type\n");
9930 return;
9931 }
9932
9933 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9934 }
9935
9936 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9937 enum port port,
9938 struct intel_crtc_state *pipe_config)
9939 {
9940 enum intel_dpll_id id;
9941 u32 temp;
9942
9943 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9944 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9945
9946 switch (pipe_config->ddi_pll_sel) {
9947 case SKL_DPLL0:
9948 id = DPLL_ID_SKL_DPLL0;
9949 break;
9950 case SKL_DPLL1:
9951 id = DPLL_ID_SKL_DPLL1;
9952 break;
9953 case SKL_DPLL2:
9954 id = DPLL_ID_SKL_DPLL2;
9955 break;
9956 case SKL_DPLL3:
9957 id = DPLL_ID_SKL_DPLL3;
9958 break;
9959 default:
9960 MISSING_CASE(pipe_config->ddi_pll_sel);
9961 return;
9962 }
9963
9964 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9965 }
9966
9967 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9968 enum port port,
9969 struct intel_crtc_state *pipe_config)
9970 {
9971 enum intel_dpll_id id;
9972
9973 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9974
9975 switch (pipe_config->ddi_pll_sel) {
9976 case PORT_CLK_SEL_WRPLL1:
9977 id = DPLL_ID_WRPLL1;
9978 break;
9979 case PORT_CLK_SEL_WRPLL2:
9980 id = DPLL_ID_WRPLL2;
9981 break;
9982 case PORT_CLK_SEL_SPLL:
9983 id = DPLL_ID_SPLL;
9984 break;
9985 case PORT_CLK_SEL_LCPLL_810:
9986 id = DPLL_ID_LCPLL_810;
9987 break;
9988 case PORT_CLK_SEL_LCPLL_1350:
9989 id = DPLL_ID_LCPLL_1350;
9990 break;
9991 case PORT_CLK_SEL_LCPLL_2700:
9992 id = DPLL_ID_LCPLL_2700;
9993 break;
9994 default:
9995 MISSING_CASE(pipe_config->ddi_pll_sel);
9996 /* fall through */
9997 case PORT_CLK_SEL_NONE:
9998 return;
9999 }
10000
10001 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10002 }
10003
10004 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10005 struct intel_crtc_state *pipe_config,
10006 unsigned long *power_domain_mask)
10007 {
10008 struct drm_device *dev = crtc->base.dev;
10009 struct drm_i915_private *dev_priv = dev->dev_private;
10010 enum intel_display_power_domain power_domain;
10011 u32 tmp;
10012
10013 /*
10014 * The pipe->transcoder mapping is fixed with the exception of the eDP
10015 * transcoder handled below.
10016 */
10017 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10018
10019 /*
10020 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10021 * consistency and less surprising code; it's in always on power).
10022 */
10023 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10024 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10025 enum pipe trans_edp_pipe;
10026 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10027 default:
10028 WARN(1, "unknown pipe linked to edp transcoder\n");
10029 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10030 case TRANS_DDI_EDP_INPUT_A_ON:
10031 trans_edp_pipe = PIPE_A;
10032 break;
10033 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10034 trans_edp_pipe = PIPE_B;
10035 break;
10036 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10037 trans_edp_pipe = PIPE_C;
10038 break;
10039 }
10040
10041 if (trans_edp_pipe == crtc->pipe)
10042 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10043 }
10044
10045 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10046 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10047 return false;
10048 *power_domain_mask |= BIT(power_domain);
10049
10050 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10051
10052 return tmp & PIPECONF_ENABLE;
10053 }
10054
10055 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10056 struct intel_crtc_state *pipe_config,
10057 unsigned long *power_domain_mask)
10058 {
10059 struct drm_device *dev = crtc->base.dev;
10060 struct drm_i915_private *dev_priv = dev->dev_private;
10061 enum intel_display_power_domain power_domain;
10062 enum port port;
10063 enum transcoder cpu_transcoder;
10064 u32 tmp;
10065
10066 pipe_config->has_dsi_encoder = false;
10067
10068 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10069 if (port == PORT_A)
10070 cpu_transcoder = TRANSCODER_DSI_A;
10071 else
10072 cpu_transcoder = TRANSCODER_DSI_C;
10073
10074 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10075 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10076 continue;
10077 *power_domain_mask |= BIT(power_domain);
10078
10079 /*
10080 * The PLL needs to be enabled with a valid divider
10081 * configuration, otherwise accessing DSI registers will hang
10082 * the machine. See BSpec North Display Engine
10083 * registers/MIPI[BXT]. We can break out here early, since we
10084 * need the same DSI PLL to be enabled for both DSI ports.
10085 */
10086 if (!intel_dsi_pll_is_enabled(dev_priv))
10087 break;
10088
10089 /* XXX: this works for video mode only */
10090 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10091 if (!(tmp & DPI_ENABLE))
10092 continue;
10093
10094 tmp = I915_READ(MIPI_CTRL(port));
10095 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10096 continue;
10097
10098 pipe_config->cpu_transcoder = cpu_transcoder;
10099 pipe_config->has_dsi_encoder = true;
10100 break;
10101 }
10102
10103 return pipe_config->has_dsi_encoder;
10104 }
10105
10106 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10107 struct intel_crtc_state *pipe_config)
10108 {
10109 struct drm_device *dev = crtc->base.dev;
10110 struct drm_i915_private *dev_priv = dev->dev_private;
10111 struct intel_shared_dpll *pll;
10112 enum port port;
10113 uint32_t tmp;
10114
10115 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10116
10117 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10118
10119 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10120 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10121 else if (IS_BROXTON(dev))
10122 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10123 else
10124 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10125
10126 pll = pipe_config->shared_dpll;
10127 if (pll) {
10128 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10129 &pipe_config->dpll_hw_state));
10130 }
10131
10132 /*
10133 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10134 * DDI E. So just check whether this pipe is wired to DDI E and whether
10135 * the PCH transcoder is on.
10136 */
10137 if (INTEL_INFO(dev)->gen < 9 &&
10138 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10139 pipe_config->has_pch_encoder = true;
10140
10141 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10142 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10143 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10144
10145 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10146 }
10147 }
10148
10149 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10150 struct intel_crtc_state *pipe_config)
10151 {
10152 struct drm_device *dev = crtc->base.dev;
10153 struct drm_i915_private *dev_priv = dev->dev_private;
10154 enum intel_display_power_domain power_domain;
10155 unsigned long power_domain_mask;
10156 bool active;
10157
10158 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10159 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10160 return false;
10161 power_domain_mask = BIT(power_domain);
10162
10163 pipe_config->shared_dpll = NULL;
10164
10165 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10166
10167 if (IS_BROXTON(dev_priv)) {
10168 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10169 &power_domain_mask);
10170 WARN_ON(active && pipe_config->has_dsi_encoder);
10171 if (pipe_config->has_dsi_encoder)
10172 active = true;
10173 }
10174
10175 if (!active)
10176 goto out;
10177
10178 if (!pipe_config->has_dsi_encoder) {
10179 haswell_get_ddi_port_state(crtc, pipe_config);
10180 intel_get_pipe_timings(crtc, pipe_config);
10181 }
10182
10183 intel_get_pipe_src_size(crtc, pipe_config);
10184
10185 pipe_config->gamma_mode =
10186 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10187
10188 if (INTEL_INFO(dev)->gen >= 9) {
10189 skl_init_scalers(dev, crtc, pipe_config);
10190 }
10191
10192 if (INTEL_INFO(dev)->gen >= 9) {
10193 pipe_config->scaler_state.scaler_id = -1;
10194 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10195 }
10196
10197 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10198 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10199 power_domain_mask |= BIT(power_domain);
10200 if (INTEL_INFO(dev)->gen >= 9)
10201 skylake_get_pfit_config(crtc, pipe_config);
10202 else
10203 ironlake_get_pfit_config(crtc, pipe_config);
10204 }
10205
10206 if (IS_HASWELL(dev))
10207 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10208 (I915_READ(IPS_CTL) & IPS_ENABLE);
10209
10210 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10211 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10212 pipe_config->pixel_multiplier =
10213 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10214 } else {
10215 pipe_config->pixel_multiplier = 1;
10216 }
10217
10218 out:
10219 for_each_power_domain(power_domain, power_domain_mask)
10220 intel_display_power_put(dev_priv, power_domain);
10221
10222 return active;
10223 }
10224
10225 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10226 const struct intel_plane_state *plane_state)
10227 {
10228 struct drm_device *dev = crtc->dev;
10229 struct drm_i915_private *dev_priv = dev->dev_private;
10230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10231 uint32_t cntl = 0, size = 0;
10232
10233 if (plane_state && plane_state->visible) {
10234 unsigned int width = plane_state->base.crtc_w;
10235 unsigned int height = plane_state->base.crtc_h;
10236 unsigned int stride = roundup_pow_of_two(width) * 4;
10237
10238 switch (stride) {
10239 default:
10240 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10241 width, stride);
10242 stride = 256;
10243 /* fallthrough */
10244 case 256:
10245 case 512:
10246 case 1024:
10247 case 2048:
10248 break;
10249 }
10250
10251 cntl |= CURSOR_ENABLE |
10252 CURSOR_GAMMA_ENABLE |
10253 CURSOR_FORMAT_ARGB |
10254 CURSOR_STRIDE(stride);
10255
10256 size = (height << 12) | width;
10257 }
10258
10259 if (intel_crtc->cursor_cntl != 0 &&
10260 (intel_crtc->cursor_base != base ||
10261 intel_crtc->cursor_size != size ||
10262 intel_crtc->cursor_cntl != cntl)) {
10263 /* On these chipsets we can only modify the base/size/stride
10264 * whilst the cursor is disabled.
10265 */
10266 I915_WRITE(CURCNTR(PIPE_A), 0);
10267 POSTING_READ(CURCNTR(PIPE_A));
10268 intel_crtc->cursor_cntl = 0;
10269 }
10270
10271 if (intel_crtc->cursor_base != base) {
10272 I915_WRITE(CURBASE(PIPE_A), base);
10273 intel_crtc->cursor_base = base;
10274 }
10275
10276 if (intel_crtc->cursor_size != size) {
10277 I915_WRITE(CURSIZE, size);
10278 intel_crtc->cursor_size = size;
10279 }
10280
10281 if (intel_crtc->cursor_cntl != cntl) {
10282 I915_WRITE(CURCNTR(PIPE_A), cntl);
10283 POSTING_READ(CURCNTR(PIPE_A));
10284 intel_crtc->cursor_cntl = cntl;
10285 }
10286 }
10287
10288 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10289 const struct intel_plane_state *plane_state)
10290 {
10291 struct drm_device *dev = crtc->dev;
10292 struct drm_i915_private *dev_priv = dev->dev_private;
10293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10294 int pipe = intel_crtc->pipe;
10295 uint32_t cntl = 0;
10296
10297 if (plane_state && plane_state->visible) {
10298 cntl = MCURSOR_GAMMA_ENABLE;
10299 switch (plane_state->base.crtc_w) {
10300 case 64:
10301 cntl |= CURSOR_MODE_64_ARGB_AX;
10302 break;
10303 case 128:
10304 cntl |= CURSOR_MODE_128_ARGB_AX;
10305 break;
10306 case 256:
10307 cntl |= CURSOR_MODE_256_ARGB_AX;
10308 break;
10309 default:
10310 MISSING_CASE(plane_state->base.crtc_w);
10311 return;
10312 }
10313 cntl |= pipe << 28; /* Connect to correct pipe */
10314
10315 if (HAS_DDI(dev))
10316 cntl |= CURSOR_PIPE_CSC_ENABLE;
10317
10318 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10319 cntl |= CURSOR_ROTATE_180;
10320 }
10321
10322 if (intel_crtc->cursor_cntl != cntl) {
10323 I915_WRITE(CURCNTR(pipe), cntl);
10324 POSTING_READ(CURCNTR(pipe));
10325 intel_crtc->cursor_cntl = cntl;
10326 }
10327
10328 /* and commit changes on next vblank */
10329 I915_WRITE(CURBASE(pipe), base);
10330 POSTING_READ(CURBASE(pipe));
10331
10332 intel_crtc->cursor_base = base;
10333 }
10334
10335 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10336 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10337 const struct intel_plane_state *plane_state)
10338 {
10339 struct drm_device *dev = crtc->dev;
10340 struct drm_i915_private *dev_priv = dev->dev_private;
10341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10342 int pipe = intel_crtc->pipe;
10343 u32 base = intel_crtc->cursor_addr;
10344 u32 pos = 0;
10345
10346 if (plane_state) {
10347 int x = plane_state->base.crtc_x;
10348 int y = plane_state->base.crtc_y;
10349
10350 if (x < 0) {
10351 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10352 x = -x;
10353 }
10354 pos |= x << CURSOR_X_SHIFT;
10355
10356 if (y < 0) {
10357 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10358 y = -y;
10359 }
10360 pos |= y << CURSOR_Y_SHIFT;
10361
10362 /* ILK+ do this automagically */
10363 if (HAS_GMCH_DISPLAY(dev) &&
10364 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10365 base += (plane_state->base.crtc_h *
10366 plane_state->base.crtc_w - 1) * 4;
10367 }
10368 }
10369
10370 I915_WRITE(CURPOS(pipe), pos);
10371
10372 if (IS_845G(dev) || IS_I865G(dev))
10373 i845_update_cursor(crtc, base, plane_state);
10374 else
10375 i9xx_update_cursor(crtc, base, plane_state);
10376 }
10377
10378 static bool cursor_size_ok(struct drm_device *dev,
10379 uint32_t width, uint32_t height)
10380 {
10381 if (width == 0 || height == 0)
10382 return false;
10383
10384 /*
10385 * 845g/865g are special in that they are only limited by
10386 * the width of their cursors, the height is arbitrary up to
10387 * the precision of the register. Everything else requires
10388 * square cursors, limited to a few power-of-two sizes.
10389 */
10390 if (IS_845G(dev) || IS_I865G(dev)) {
10391 if ((width & 63) != 0)
10392 return false;
10393
10394 if (width > (IS_845G(dev) ? 64 : 512))
10395 return false;
10396
10397 if (height > 1023)
10398 return false;
10399 } else {
10400 switch (width | height) {
10401 case 256:
10402 case 128:
10403 if (IS_GEN2(dev))
10404 return false;
10405 case 64:
10406 break;
10407 default:
10408 return false;
10409 }
10410 }
10411
10412 return true;
10413 }
10414
10415 /* VESA 640x480x72Hz mode to set on the pipe */
10416 static struct drm_display_mode load_detect_mode = {
10417 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10418 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10419 };
10420
10421 struct drm_framebuffer *
10422 __intel_framebuffer_create(struct drm_device *dev,
10423 struct drm_mode_fb_cmd2 *mode_cmd,
10424 struct drm_i915_gem_object *obj)
10425 {
10426 struct intel_framebuffer *intel_fb;
10427 int ret;
10428
10429 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10430 if (!intel_fb)
10431 return ERR_PTR(-ENOMEM);
10432
10433 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10434 if (ret)
10435 goto err;
10436
10437 return &intel_fb->base;
10438
10439 err:
10440 kfree(intel_fb);
10441 return ERR_PTR(ret);
10442 }
10443
10444 static struct drm_framebuffer *
10445 intel_framebuffer_create(struct drm_device *dev,
10446 struct drm_mode_fb_cmd2 *mode_cmd,
10447 struct drm_i915_gem_object *obj)
10448 {
10449 struct drm_framebuffer *fb;
10450 int ret;
10451
10452 ret = i915_mutex_lock_interruptible(dev);
10453 if (ret)
10454 return ERR_PTR(ret);
10455 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10456 mutex_unlock(&dev->struct_mutex);
10457
10458 return fb;
10459 }
10460
10461 static u32
10462 intel_framebuffer_pitch_for_width(int width, int bpp)
10463 {
10464 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10465 return ALIGN(pitch, 64);
10466 }
10467
10468 static u32
10469 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10470 {
10471 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10472 return PAGE_ALIGN(pitch * mode->vdisplay);
10473 }
10474
10475 static struct drm_framebuffer *
10476 intel_framebuffer_create_for_mode(struct drm_device *dev,
10477 struct drm_display_mode *mode,
10478 int depth, int bpp)
10479 {
10480 struct drm_framebuffer *fb;
10481 struct drm_i915_gem_object *obj;
10482 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10483
10484 obj = i915_gem_object_create(dev,
10485 intel_framebuffer_size_for_mode(mode, bpp));
10486 if (IS_ERR(obj))
10487 return ERR_CAST(obj);
10488
10489 mode_cmd.width = mode->hdisplay;
10490 mode_cmd.height = mode->vdisplay;
10491 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10492 bpp);
10493 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10494
10495 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10496 if (IS_ERR(fb))
10497 drm_gem_object_unreference_unlocked(&obj->base);
10498
10499 return fb;
10500 }
10501
10502 static struct drm_framebuffer *
10503 mode_fits_in_fbdev(struct drm_device *dev,
10504 struct drm_display_mode *mode)
10505 {
10506 #ifdef CONFIG_DRM_FBDEV_EMULATION
10507 struct drm_i915_private *dev_priv = dev->dev_private;
10508 struct drm_i915_gem_object *obj;
10509 struct drm_framebuffer *fb;
10510
10511 if (!dev_priv->fbdev)
10512 return NULL;
10513
10514 if (!dev_priv->fbdev->fb)
10515 return NULL;
10516
10517 obj = dev_priv->fbdev->fb->obj;
10518 BUG_ON(!obj);
10519
10520 fb = &dev_priv->fbdev->fb->base;
10521 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10522 fb->bits_per_pixel))
10523 return NULL;
10524
10525 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10526 return NULL;
10527
10528 drm_framebuffer_reference(fb);
10529 return fb;
10530 #else
10531 return NULL;
10532 #endif
10533 }
10534
10535 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10536 struct drm_crtc *crtc,
10537 struct drm_display_mode *mode,
10538 struct drm_framebuffer *fb,
10539 int x, int y)
10540 {
10541 struct drm_plane_state *plane_state;
10542 int hdisplay, vdisplay;
10543 int ret;
10544
10545 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10546 if (IS_ERR(plane_state))
10547 return PTR_ERR(plane_state);
10548
10549 if (mode)
10550 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10551 else
10552 hdisplay = vdisplay = 0;
10553
10554 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10555 if (ret)
10556 return ret;
10557 drm_atomic_set_fb_for_plane(plane_state, fb);
10558 plane_state->crtc_x = 0;
10559 plane_state->crtc_y = 0;
10560 plane_state->crtc_w = hdisplay;
10561 plane_state->crtc_h = vdisplay;
10562 plane_state->src_x = x << 16;
10563 plane_state->src_y = y << 16;
10564 plane_state->src_w = hdisplay << 16;
10565 plane_state->src_h = vdisplay << 16;
10566
10567 return 0;
10568 }
10569
10570 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10571 struct drm_display_mode *mode,
10572 struct intel_load_detect_pipe *old,
10573 struct drm_modeset_acquire_ctx *ctx)
10574 {
10575 struct intel_crtc *intel_crtc;
10576 struct intel_encoder *intel_encoder =
10577 intel_attached_encoder(connector);
10578 struct drm_crtc *possible_crtc;
10579 struct drm_encoder *encoder = &intel_encoder->base;
10580 struct drm_crtc *crtc = NULL;
10581 struct drm_device *dev = encoder->dev;
10582 struct drm_framebuffer *fb;
10583 struct drm_mode_config *config = &dev->mode_config;
10584 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10585 struct drm_connector_state *connector_state;
10586 struct intel_crtc_state *crtc_state;
10587 int ret, i = -1;
10588
10589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10590 connector->base.id, connector->name,
10591 encoder->base.id, encoder->name);
10592
10593 old->restore_state = NULL;
10594
10595 retry:
10596 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10597 if (ret)
10598 goto fail;
10599
10600 /*
10601 * Algorithm gets a little messy:
10602 *
10603 * - if the connector already has an assigned crtc, use it (but make
10604 * sure it's on first)
10605 *
10606 * - try to find the first unused crtc that can drive this connector,
10607 * and use that if we find one
10608 */
10609
10610 /* See if we already have a CRTC for this connector */
10611 if (connector->state->crtc) {
10612 crtc = connector->state->crtc;
10613
10614 ret = drm_modeset_lock(&crtc->mutex, ctx);
10615 if (ret)
10616 goto fail;
10617
10618 /* Make sure the crtc and connector are running */
10619 goto found;
10620 }
10621
10622 /* Find an unused one (if possible) */
10623 for_each_crtc(dev, possible_crtc) {
10624 i++;
10625 if (!(encoder->possible_crtcs & (1 << i)))
10626 continue;
10627
10628 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10629 if (ret)
10630 goto fail;
10631
10632 if (possible_crtc->state->enable) {
10633 drm_modeset_unlock(&possible_crtc->mutex);
10634 continue;
10635 }
10636
10637 crtc = possible_crtc;
10638 break;
10639 }
10640
10641 /*
10642 * If we didn't find an unused CRTC, don't use any.
10643 */
10644 if (!crtc) {
10645 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10646 goto fail;
10647 }
10648
10649 found:
10650 intel_crtc = to_intel_crtc(crtc);
10651
10652 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10653 if (ret)
10654 goto fail;
10655
10656 state = drm_atomic_state_alloc(dev);
10657 restore_state = drm_atomic_state_alloc(dev);
10658 if (!state || !restore_state) {
10659 ret = -ENOMEM;
10660 goto fail;
10661 }
10662
10663 state->acquire_ctx = ctx;
10664 restore_state->acquire_ctx = ctx;
10665
10666 connector_state = drm_atomic_get_connector_state(state, connector);
10667 if (IS_ERR(connector_state)) {
10668 ret = PTR_ERR(connector_state);
10669 goto fail;
10670 }
10671
10672 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10673 if (ret)
10674 goto fail;
10675
10676 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10677 if (IS_ERR(crtc_state)) {
10678 ret = PTR_ERR(crtc_state);
10679 goto fail;
10680 }
10681
10682 crtc_state->base.active = crtc_state->base.enable = true;
10683
10684 if (!mode)
10685 mode = &load_detect_mode;
10686
10687 /* We need a framebuffer large enough to accommodate all accesses
10688 * that the plane may generate whilst we perform load detection.
10689 * We can not rely on the fbcon either being present (we get called
10690 * during its initialisation to detect all boot displays, or it may
10691 * not even exist) or that it is large enough to satisfy the
10692 * requested mode.
10693 */
10694 fb = mode_fits_in_fbdev(dev, mode);
10695 if (fb == NULL) {
10696 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10697 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10698 } else
10699 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10700 if (IS_ERR(fb)) {
10701 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10702 goto fail;
10703 }
10704
10705 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10706 if (ret)
10707 goto fail;
10708
10709 drm_framebuffer_unreference(fb);
10710
10711 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10712 if (ret)
10713 goto fail;
10714
10715 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10716 if (!ret)
10717 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10718 if (!ret)
10719 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10720 if (ret) {
10721 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10722 goto fail;
10723 }
10724
10725 ret = drm_atomic_commit(state);
10726 if (ret) {
10727 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10728 goto fail;
10729 }
10730
10731 old->restore_state = restore_state;
10732
10733 /* let the connector get through one full cycle before testing */
10734 intel_wait_for_vblank(dev, intel_crtc->pipe);
10735 return true;
10736
10737 fail:
10738 drm_atomic_state_free(state);
10739 drm_atomic_state_free(restore_state);
10740 restore_state = state = NULL;
10741
10742 if (ret == -EDEADLK) {
10743 drm_modeset_backoff(ctx);
10744 goto retry;
10745 }
10746
10747 return false;
10748 }
10749
10750 void intel_release_load_detect_pipe(struct drm_connector *connector,
10751 struct intel_load_detect_pipe *old,
10752 struct drm_modeset_acquire_ctx *ctx)
10753 {
10754 struct intel_encoder *intel_encoder =
10755 intel_attached_encoder(connector);
10756 struct drm_encoder *encoder = &intel_encoder->base;
10757 struct drm_atomic_state *state = old->restore_state;
10758 int ret;
10759
10760 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10761 connector->base.id, connector->name,
10762 encoder->base.id, encoder->name);
10763
10764 if (!state)
10765 return;
10766
10767 ret = drm_atomic_commit(state);
10768 if (ret) {
10769 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10770 drm_atomic_state_free(state);
10771 }
10772 }
10773
10774 static int i9xx_pll_refclk(struct drm_device *dev,
10775 const struct intel_crtc_state *pipe_config)
10776 {
10777 struct drm_i915_private *dev_priv = dev->dev_private;
10778 u32 dpll = pipe_config->dpll_hw_state.dpll;
10779
10780 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10781 return dev_priv->vbt.lvds_ssc_freq;
10782 else if (HAS_PCH_SPLIT(dev))
10783 return 120000;
10784 else if (!IS_GEN2(dev))
10785 return 96000;
10786 else
10787 return 48000;
10788 }
10789
10790 /* Returns the clock of the currently programmed mode of the given pipe. */
10791 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10792 struct intel_crtc_state *pipe_config)
10793 {
10794 struct drm_device *dev = crtc->base.dev;
10795 struct drm_i915_private *dev_priv = dev->dev_private;
10796 int pipe = pipe_config->cpu_transcoder;
10797 u32 dpll = pipe_config->dpll_hw_state.dpll;
10798 u32 fp;
10799 struct dpll clock;
10800 int port_clock;
10801 int refclk = i9xx_pll_refclk(dev, pipe_config);
10802
10803 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10804 fp = pipe_config->dpll_hw_state.fp0;
10805 else
10806 fp = pipe_config->dpll_hw_state.fp1;
10807
10808 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10809 if (IS_PINEVIEW(dev)) {
10810 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10811 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10812 } else {
10813 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10814 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10815 }
10816
10817 if (!IS_GEN2(dev)) {
10818 if (IS_PINEVIEW(dev))
10819 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10820 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10821 else
10822 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10823 DPLL_FPA01_P1_POST_DIV_SHIFT);
10824
10825 switch (dpll & DPLL_MODE_MASK) {
10826 case DPLLB_MODE_DAC_SERIAL:
10827 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10828 5 : 10;
10829 break;
10830 case DPLLB_MODE_LVDS:
10831 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10832 7 : 14;
10833 break;
10834 default:
10835 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10836 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10837 return;
10838 }
10839
10840 if (IS_PINEVIEW(dev))
10841 port_clock = pnv_calc_dpll_params(refclk, &clock);
10842 else
10843 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10844 } else {
10845 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10846 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10847
10848 if (is_lvds) {
10849 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10850 DPLL_FPA01_P1_POST_DIV_SHIFT);
10851
10852 if (lvds & LVDS_CLKB_POWER_UP)
10853 clock.p2 = 7;
10854 else
10855 clock.p2 = 14;
10856 } else {
10857 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10858 clock.p1 = 2;
10859 else {
10860 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10861 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10862 }
10863 if (dpll & PLL_P2_DIVIDE_BY_4)
10864 clock.p2 = 4;
10865 else
10866 clock.p2 = 2;
10867 }
10868
10869 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10870 }
10871
10872 /*
10873 * This value includes pixel_multiplier. We will use
10874 * port_clock to compute adjusted_mode.crtc_clock in the
10875 * encoder's get_config() function.
10876 */
10877 pipe_config->port_clock = port_clock;
10878 }
10879
10880 int intel_dotclock_calculate(int link_freq,
10881 const struct intel_link_m_n *m_n)
10882 {
10883 /*
10884 * The calculation for the data clock is:
10885 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10886 * But we want to avoid losing precison if possible, so:
10887 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10888 *
10889 * and the link clock is simpler:
10890 * link_clock = (m * link_clock) / n
10891 */
10892
10893 if (!m_n->link_n)
10894 return 0;
10895
10896 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10897 }
10898
10899 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10900 struct intel_crtc_state *pipe_config)
10901 {
10902 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10903
10904 /* read out port_clock from the DPLL */
10905 i9xx_crtc_clock_get(crtc, pipe_config);
10906
10907 /*
10908 * In case there is an active pipe without active ports,
10909 * we may need some idea for the dotclock anyway.
10910 * Calculate one based on the FDI configuration.
10911 */
10912 pipe_config->base.adjusted_mode.crtc_clock =
10913 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10914 &pipe_config->fdi_m_n);
10915 }
10916
10917 /** Returns the currently programmed mode of the given pipe. */
10918 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10919 struct drm_crtc *crtc)
10920 {
10921 struct drm_i915_private *dev_priv = dev->dev_private;
10922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10923 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10924 struct drm_display_mode *mode;
10925 struct intel_crtc_state *pipe_config;
10926 int htot = I915_READ(HTOTAL(cpu_transcoder));
10927 int hsync = I915_READ(HSYNC(cpu_transcoder));
10928 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10929 int vsync = I915_READ(VSYNC(cpu_transcoder));
10930 enum pipe pipe = intel_crtc->pipe;
10931
10932 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10933 if (!mode)
10934 return NULL;
10935
10936 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10937 if (!pipe_config) {
10938 kfree(mode);
10939 return NULL;
10940 }
10941
10942 /*
10943 * Construct a pipe_config sufficient for getting the clock info
10944 * back out of crtc_clock_get.
10945 *
10946 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10947 * to use a real value here instead.
10948 */
10949 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10950 pipe_config->pixel_multiplier = 1;
10951 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10952 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10953 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10954 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10955
10956 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10957 mode->hdisplay = (htot & 0xffff) + 1;
10958 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10959 mode->hsync_start = (hsync & 0xffff) + 1;
10960 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10961 mode->vdisplay = (vtot & 0xffff) + 1;
10962 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10963 mode->vsync_start = (vsync & 0xffff) + 1;
10964 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10965
10966 drm_mode_set_name(mode);
10967
10968 kfree(pipe_config);
10969
10970 return mode;
10971 }
10972
10973 void intel_mark_busy(struct drm_i915_private *dev_priv)
10974 {
10975 if (dev_priv->mm.busy)
10976 return;
10977
10978 intel_runtime_pm_get(dev_priv);
10979 i915_update_gfx_val(dev_priv);
10980 if (INTEL_GEN(dev_priv) >= 6)
10981 gen6_rps_busy(dev_priv);
10982 dev_priv->mm.busy = true;
10983 }
10984
10985 void intel_mark_idle(struct drm_i915_private *dev_priv)
10986 {
10987 if (!dev_priv->mm.busy)
10988 return;
10989
10990 dev_priv->mm.busy = false;
10991
10992 if (INTEL_GEN(dev_priv) >= 6)
10993 gen6_rps_idle(dev_priv);
10994
10995 intel_runtime_pm_put(dev_priv);
10996 }
10997
10998 static void intel_crtc_destroy(struct drm_crtc *crtc)
10999 {
11000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11001 struct drm_device *dev = crtc->dev;
11002 struct intel_flip_work *work;
11003
11004 spin_lock_irq(&dev->event_lock);
11005 work = intel_crtc->flip_work;
11006 intel_crtc->flip_work = NULL;
11007 spin_unlock_irq(&dev->event_lock);
11008
11009 if (work) {
11010 cancel_work_sync(&work->mmio_work);
11011 cancel_work_sync(&work->unpin_work);
11012 kfree(work);
11013 }
11014
11015 drm_crtc_cleanup(crtc);
11016
11017 kfree(intel_crtc);
11018 }
11019
11020 static void intel_unpin_work_fn(struct work_struct *__work)
11021 {
11022 struct intel_flip_work *work =
11023 container_of(__work, struct intel_flip_work, unpin_work);
11024 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11025 struct drm_device *dev = crtc->base.dev;
11026 struct drm_plane *primary = crtc->base.primary;
11027
11028 if (is_mmio_work(work))
11029 flush_work(&work->mmio_work);
11030
11031 mutex_lock(&dev->struct_mutex);
11032 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11033 drm_gem_object_unreference(&work->pending_flip_obj->base);
11034
11035 if (work->flip_queued_req)
11036 i915_gem_request_assign(&work->flip_queued_req, NULL);
11037 mutex_unlock(&dev->struct_mutex);
11038
11039 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
11040 intel_fbc_post_update(crtc);
11041 drm_framebuffer_unreference(work->old_fb);
11042
11043 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11044 atomic_dec(&crtc->unpin_work_count);
11045
11046 kfree(work);
11047 }
11048
11049 /* Is 'a' after or equal to 'b'? */
11050 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11051 {
11052 return !((a - b) & 0x80000000);
11053 }
11054
11055 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11056 struct intel_flip_work *work)
11057 {
11058 struct drm_device *dev = crtc->base.dev;
11059 struct drm_i915_private *dev_priv = dev->dev_private;
11060 unsigned reset_counter;
11061
11062 reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11063 if (crtc->reset_counter != reset_counter)
11064 return true;
11065
11066 /*
11067 * The relevant registers doen't exist on pre-ctg.
11068 * As the flip done interrupt doesn't trigger for mmio
11069 * flips on gmch platforms, a flip count check isn't
11070 * really needed there. But since ctg has the registers,
11071 * include it in the check anyway.
11072 */
11073 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11074 return true;
11075
11076 /*
11077 * BDW signals flip done immediately if the plane
11078 * is disabled, even if the plane enable is already
11079 * armed to occur at the next vblank :(
11080 */
11081
11082 /*
11083 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11084 * used the same base address. In that case the mmio flip might
11085 * have completed, but the CS hasn't even executed the flip yet.
11086 *
11087 * A flip count check isn't enough as the CS might have updated
11088 * the base address just after start of vblank, but before we
11089 * managed to process the interrupt. This means we'd complete the
11090 * CS flip too soon.
11091 *
11092 * Combining both checks should get us a good enough result. It may
11093 * still happen that the CS flip has been executed, but has not
11094 * yet actually completed. But in case the base address is the same
11095 * anyway, we don't really care.
11096 */
11097 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11098 crtc->flip_work->gtt_offset &&
11099 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11100 crtc->flip_work->flip_count);
11101 }
11102
11103 static bool
11104 __pageflip_finished_mmio(struct intel_crtc *crtc,
11105 struct intel_flip_work *work)
11106 {
11107 /*
11108 * MMIO work completes when vblank is different from
11109 * flip_queued_vblank.
11110 *
11111 * Reset counter value doesn't matter, this is handled by
11112 * i915_wait_request finishing early, so no need to handle
11113 * reset here.
11114 */
11115 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11116 }
11117
11118
11119 static bool pageflip_finished(struct intel_crtc *crtc,
11120 struct intel_flip_work *work)
11121 {
11122 if (!atomic_read(&work->pending))
11123 return false;
11124
11125 smp_rmb();
11126
11127 if (is_mmio_work(work))
11128 return __pageflip_finished_mmio(crtc, work);
11129 else
11130 return __pageflip_finished_cs(crtc, work);
11131 }
11132
11133 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11134 {
11135 struct drm_device *dev = dev_priv->dev;
11136 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11138 struct intel_flip_work *work;
11139 unsigned long flags;
11140
11141 /* Ignore early vblank irqs */
11142 if (!crtc)
11143 return;
11144
11145 /*
11146 * This is called both by irq handlers and the reset code (to complete
11147 * lost pageflips) so needs the full irqsave spinlocks.
11148 */
11149 spin_lock_irqsave(&dev->event_lock, flags);
11150 work = intel_crtc->flip_work;
11151
11152 if (work != NULL &&
11153 !is_mmio_work(work) &&
11154 pageflip_finished(intel_crtc, work))
11155 page_flip_completed(intel_crtc);
11156
11157 spin_unlock_irqrestore(&dev->event_lock, flags);
11158 }
11159
11160 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11161 {
11162 struct drm_device *dev = dev_priv->dev;
11163 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11165 struct intel_flip_work *work;
11166 unsigned long flags;
11167
11168 /* Ignore early vblank irqs */
11169 if (!crtc)
11170 return;
11171
11172 /*
11173 * This is called both by irq handlers and the reset code (to complete
11174 * lost pageflips) so needs the full irqsave spinlocks.
11175 */
11176 spin_lock_irqsave(&dev->event_lock, flags);
11177 work = intel_crtc->flip_work;
11178
11179 if (work != NULL &&
11180 is_mmio_work(work) &&
11181 pageflip_finished(intel_crtc, work))
11182 page_flip_completed(intel_crtc);
11183
11184 spin_unlock_irqrestore(&dev->event_lock, flags);
11185 }
11186
11187 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11188 struct intel_flip_work *work)
11189 {
11190 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11191
11192 /* Ensure that the work item is consistent when activating it ... */
11193 smp_mb__before_atomic();
11194 atomic_set(&work->pending, 1);
11195 }
11196
11197 static int intel_gen2_queue_flip(struct drm_device *dev,
11198 struct drm_crtc *crtc,
11199 struct drm_framebuffer *fb,
11200 struct drm_i915_gem_object *obj,
11201 struct drm_i915_gem_request *req,
11202 uint32_t flags)
11203 {
11204 struct intel_engine_cs *engine = req->engine;
11205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11206 u32 flip_mask;
11207 int ret;
11208
11209 ret = intel_ring_begin(req, 6);
11210 if (ret)
11211 return ret;
11212
11213 /* Can't queue multiple flips, so wait for the previous
11214 * one to finish before executing the next.
11215 */
11216 if (intel_crtc->plane)
11217 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11218 else
11219 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11220 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11221 intel_ring_emit(engine, MI_NOOP);
11222 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11223 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11224 intel_ring_emit(engine, fb->pitches[0]);
11225 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11226 intel_ring_emit(engine, 0); /* aux display base address, unused */
11227
11228 return 0;
11229 }
11230
11231 static int intel_gen3_queue_flip(struct drm_device *dev,
11232 struct drm_crtc *crtc,
11233 struct drm_framebuffer *fb,
11234 struct drm_i915_gem_object *obj,
11235 struct drm_i915_gem_request *req,
11236 uint32_t flags)
11237 {
11238 struct intel_engine_cs *engine = req->engine;
11239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11240 u32 flip_mask;
11241 int ret;
11242
11243 ret = intel_ring_begin(req, 6);
11244 if (ret)
11245 return ret;
11246
11247 if (intel_crtc->plane)
11248 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11249 else
11250 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11251 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11252 intel_ring_emit(engine, MI_NOOP);
11253 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11254 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11255 intel_ring_emit(engine, fb->pitches[0]);
11256 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11257 intel_ring_emit(engine, MI_NOOP);
11258
11259 return 0;
11260 }
11261
11262 static int intel_gen4_queue_flip(struct drm_device *dev,
11263 struct drm_crtc *crtc,
11264 struct drm_framebuffer *fb,
11265 struct drm_i915_gem_object *obj,
11266 struct drm_i915_gem_request *req,
11267 uint32_t flags)
11268 {
11269 struct intel_engine_cs *engine = req->engine;
11270 struct drm_i915_private *dev_priv = dev->dev_private;
11271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11272 uint32_t pf, pipesrc;
11273 int ret;
11274
11275 ret = intel_ring_begin(req, 4);
11276 if (ret)
11277 return ret;
11278
11279 /* i965+ uses the linear or tiled offsets from the
11280 * Display Registers (which do not change across a page-flip)
11281 * so we need only reprogram the base address.
11282 */
11283 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11284 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11285 intel_ring_emit(engine, fb->pitches[0]);
11286 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |
11287 obj->tiling_mode);
11288
11289 /* XXX Enabling the panel-fitter across page-flip is so far
11290 * untested on non-native modes, so ignore it for now.
11291 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11292 */
11293 pf = 0;
11294 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11295 intel_ring_emit(engine, pf | pipesrc);
11296
11297 return 0;
11298 }
11299
11300 static int intel_gen6_queue_flip(struct drm_device *dev,
11301 struct drm_crtc *crtc,
11302 struct drm_framebuffer *fb,
11303 struct drm_i915_gem_object *obj,
11304 struct drm_i915_gem_request *req,
11305 uint32_t flags)
11306 {
11307 struct intel_engine_cs *engine = req->engine;
11308 struct drm_i915_private *dev_priv = dev->dev_private;
11309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11310 uint32_t pf, pipesrc;
11311 int ret;
11312
11313 ret = intel_ring_begin(req, 4);
11314 if (ret)
11315 return ret;
11316
11317 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11318 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11319 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11320 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11321
11322 /* Contrary to the suggestions in the documentation,
11323 * "Enable Panel Fitter" does not seem to be required when page
11324 * flipping with a non-native mode, and worse causes a normal
11325 * modeset to fail.
11326 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11327 */
11328 pf = 0;
11329 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11330 intel_ring_emit(engine, pf | pipesrc);
11331
11332 return 0;
11333 }
11334
11335 static int intel_gen7_queue_flip(struct drm_device *dev,
11336 struct drm_crtc *crtc,
11337 struct drm_framebuffer *fb,
11338 struct drm_i915_gem_object *obj,
11339 struct drm_i915_gem_request *req,
11340 uint32_t flags)
11341 {
11342 struct intel_engine_cs *engine = req->engine;
11343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11344 uint32_t plane_bit = 0;
11345 int len, ret;
11346
11347 switch (intel_crtc->plane) {
11348 case PLANE_A:
11349 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11350 break;
11351 case PLANE_B:
11352 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11353 break;
11354 case PLANE_C:
11355 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11356 break;
11357 default:
11358 WARN_ONCE(1, "unknown plane in flip command\n");
11359 return -ENODEV;
11360 }
11361
11362 len = 4;
11363 if (engine->id == RCS) {
11364 len += 6;
11365 /*
11366 * On Gen 8, SRM is now taking an extra dword to accommodate
11367 * 48bits addresses, and we need a NOOP for the batch size to
11368 * stay even.
11369 */
11370 if (IS_GEN8(dev))
11371 len += 2;
11372 }
11373
11374 /*
11375 * BSpec MI_DISPLAY_FLIP for IVB:
11376 * "The full packet must be contained within the same cache line."
11377 *
11378 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11379 * cacheline, if we ever start emitting more commands before
11380 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11381 * then do the cacheline alignment, and finally emit the
11382 * MI_DISPLAY_FLIP.
11383 */
11384 ret = intel_ring_cacheline_align(req);
11385 if (ret)
11386 return ret;
11387
11388 ret = intel_ring_begin(req, len);
11389 if (ret)
11390 return ret;
11391
11392 /* Unmask the flip-done completion message. Note that the bspec says that
11393 * we should do this for both the BCS and RCS, and that we must not unmask
11394 * more than one flip event at any time (or ensure that one flip message
11395 * can be sent by waiting for flip-done prior to queueing new flips).
11396 * Experimentation says that BCS works despite DERRMR masking all
11397 * flip-done completion events and that unmasking all planes at once
11398 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11399 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11400 */
11401 if (engine->id == RCS) {
11402 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11403 intel_ring_emit_reg(engine, DERRMR);
11404 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11405 DERRMR_PIPEB_PRI_FLIP_DONE |
11406 DERRMR_PIPEC_PRI_FLIP_DONE));
11407 if (IS_GEN8(dev))
11408 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11409 MI_SRM_LRM_GLOBAL_GTT);
11410 else
11411 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11412 MI_SRM_LRM_GLOBAL_GTT);
11413 intel_ring_emit_reg(engine, DERRMR);
11414 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11415 if (IS_GEN8(dev)) {
11416 intel_ring_emit(engine, 0);
11417 intel_ring_emit(engine, MI_NOOP);
11418 }
11419 }
11420
11421 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11422 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11423 intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);
11424 intel_ring_emit(engine, (MI_NOOP));
11425
11426 return 0;
11427 }
11428
11429 static bool use_mmio_flip(struct intel_engine_cs *engine,
11430 struct drm_i915_gem_object *obj)
11431 {
11432 struct reservation_object *resv;
11433
11434 /*
11435 * This is not being used for older platforms, because
11436 * non-availability of flip done interrupt forces us to use
11437 * CS flips. Older platforms derive flip done using some clever
11438 * tricks involving the flip_pending status bits and vblank irqs.
11439 * So using MMIO flips there would disrupt this mechanism.
11440 */
11441
11442 if (engine == NULL)
11443 return true;
11444
11445 if (INTEL_GEN(engine->i915) < 5)
11446 return false;
11447
11448 if (i915.use_mmio_flip < 0)
11449 return false;
11450 else if (i915.use_mmio_flip > 0)
11451 return true;
11452 else if (i915.enable_execlists)
11453 return true;
11454
11455 resv = i915_gem_object_get_dmabuf_resv(obj);
11456 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11457 return true;
11458
11459 return engine != i915_gem_request_get_engine(obj->last_write_req);
11460 }
11461
11462 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11463 unsigned int rotation,
11464 struct intel_flip_work *work)
11465 {
11466 struct drm_device *dev = intel_crtc->base.dev;
11467 struct drm_i915_private *dev_priv = dev->dev_private;
11468 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11469 const enum pipe pipe = intel_crtc->pipe;
11470 u32 ctl, stride, tile_height;
11471
11472 ctl = I915_READ(PLANE_CTL(pipe, 0));
11473 ctl &= ~PLANE_CTL_TILED_MASK;
11474 switch (fb->modifier[0]) {
11475 case DRM_FORMAT_MOD_NONE:
11476 break;
11477 case I915_FORMAT_MOD_X_TILED:
11478 ctl |= PLANE_CTL_TILED_X;
11479 break;
11480 case I915_FORMAT_MOD_Y_TILED:
11481 ctl |= PLANE_CTL_TILED_Y;
11482 break;
11483 case I915_FORMAT_MOD_Yf_TILED:
11484 ctl |= PLANE_CTL_TILED_YF;
11485 break;
11486 default:
11487 MISSING_CASE(fb->modifier[0]);
11488 }
11489
11490 /*
11491 * The stride is either expressed as a multiple of 64 bytes chunks for
11492 * linear buffers or in number of tiles for tiled buffers.
11493 */
11494 if (intel_rotation_90_or_270(rotation)) {
11495 /* stride = Surface height in tiles */
11496 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11497 stride = DIV_ROUND_UP(fb->height, tile_height);
11498 } else {
11499 stride = fb->pitches[0] /
11500 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11501 fb->pixel_format);
11502 }
11503
11504 /*
11505 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11506 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11507 */
11508 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11509 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11510
11511 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11512 POSTING_READ(PLANE_SURF(pipe, 0));
11513 }
11514
11515 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11516 struct intel_flip_work *work)
11517 {
11518 struct drm_device *dev = intel_crtc->base.dev;
11519 struct drm_i915_private *dev_priv = dev->dev_private;
11520 struct intel_framebuffer *intel_fb =
11521 to_intel_framebuffer(intel_crtc->base.primary->fb);
11522 struct drm_i915_gem_object *obj = intel_fb->obj;
11523 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11524 u32 dspcntr;
11525
11526 dspcntr = I915_READ(reg);
11527
11528 if (obj->tiling_mode != I915_TILING_NONE)
11529 dspcntr |= DISPPLANE_TILED;
11530 else
11531 dspcntr &= ~DISPPLANE_TILED;
11532
11533 I915_WRITE(reg, dspcntr);
11534
11535 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11536 POSTING_READ(DSPSURF(intel_crtc->plane));
11537 }
11538
11539 static void intel_mmio_flip_work_func(struct work_struct *w)
11540 {
11541 struct intel_flip_work *work =
11542 container_of(w, struct intel_flip_work, mmio_work);
11543 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11545 struct intel_framebuffer *intel_fb =
11546 to_intel_framebuffer(crtc->base.primary->fb);
11547 struct drm_i915_gem_object *obj = intel_fb->obj;
11548 struct reservation_object *resv;
11549
11550 if (work->flip_queued_req)
11551 WARN_ON(__i915_wait_request(work->flip_queued_req,
11552 false, NULL,
11553 &dev_priv->rps.mmioflips));
11554
11555 /* For framebuffer backed by dmabuf, wait for fence */
11556 resv = i915_gem_object_get_dmabuf_resv(obj);
11557 if (resv)
11558 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
11559 MAX_SCHEDULE_TIMEOUT) < 0);
11560
11561 intel_pipe_update_start(crtc);
11562
11563 if (INTEL_GEN(dev_priv) >= 9)
11564 skl_do_mmio_flip(crtc, work->rotation, work);
11565 else
11566 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11567 ilk_do_mmio_flip(crtc, work);
11568
11569 intel_pipe_update_end(crtc, work);
11570 }
11571
11572 static int intel_default_queue_flip(struct drm_device *dev,
11573 struct drm_crtc *crtc,
11574 struct drm_framebuffer *fb,
11575 struct drm_i915_gem_object *obj,
11576 struct drm_i915_gem_request *req,
11577 uint32_t flags)
11578 {
11579 return -ENODEV;
11580 }
11581
11582 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
11583 struct intel_crtc *intel_crtc,
11584 struct intel_flip_work *work)
11585 {
11586 u32 addr, vblank;
11587
11588 if (!atomic_read(&work->pending))
11589 return false;
11590
11591 smp_rmb();
11592
11593 vblank = intel_crtc_get_vblank_counter(intel_crtc);
11594 if (work->flip_ready_vblank == 0) {
11595 if (work->flip_queued_req &&
11596 !i915_gem_request_completed(work->flip_queued_req, true))
11597 return false;
11598
11599 work->flip_ready_vblank = vblank;
11600 }
11601
11602 if (vblank - work->flip_ready_vblank < 3)
11603 return false;
11604
11605 /* Potential stall - if we see that the flip has happened,
11606 * assume a missed interrupt. */
11607 if (INTEL_GEN(dev_priv) >= 4)
11608 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11609 else
11610 addr = I915_READ(DSPADDR(intel_crtc->plane));
11611
11612 /* There is a potential issue here with a false positive after a flip
11613 * to the same address. We could address this by checking for a
11614 * non-incrementing frame counter.
11615 */
11616 return addr == work->gtt_offset;
11617 }
11618
11619 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
11620 {
11621 struct drm_device *dev = dev_priv->dev;
11622 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11624 struct intel_flip_work *work;
11625
11626 WARN_ON(!in_interrupt());
11627
11628 if (crtc == NULL)
11629 return;
11630
11631 spin_lock(&dev->event_lock);
11632 work = intel_crtc->flip_work;
11633
11634 if (work != NULL && !is_mmio_work(work) &&
11635 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
11636 WARN_ONCE(1,
11637 "Kicking stuck page flip: queued at %d, now %d\n",
11638 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
11639 page_flip_completed(intel_crtc);
11640 work = NULL;
11641 }
11642
11643 if (work != NULL && !is_mmio_work(work) &&
11644 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
11645 intel_queue_rps_boost_for_request(work->flip_queued_req);
11646 spin_unlock(&dev->event_lock);
11647 }
11648
11649 __maybe_unused
11650 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11651 struct drm_framebuffer *fb,
11652 struct drm_pending_vblank_event *event,
11653 uint32_t page_flip_flags)
11654 {
11655 struct drm_device *dev = crtc->dev;
11656 struct drm_i915_private *dev_priv = dev->dev_private;
11657 struct drm_framebuffer *old_fb = crtc->primary->fb;
11658 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11660 struct drm_plane *primary = crtc->primary;
11661 enum pipe pipe = intel_crtc->pipe;
11662 struct intel_flip_work *work;
11663 struct intel_engine_cs *engine;
11664 bool mmio_flip;
11665 struct drm_i915_gem_request *request = NULL;
11666 int ret;
11667
11668 /*
11669 * drm_mode_page_flip_ioctl() should already catch this, but double
11670 * check to be safe. In the future we may enable pageflipping from
11671 * a disabled primary plane.
11672 */
11673 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11674 return -EBUSY;
11675
11676 /* Can't change pixel format via MI display flips. */
11677 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11678 return -EINVAL;
11679
11680 /*
11681 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11682 * Note that pitch changes could also affect these register.
11683 */
11684 if (INTEL_INFO(dev)->gen > 3 &&
11685 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11686 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11687 return -EINVAL;
11688
11689 if (i915_terminally_wedged(&dev_priv->gpu_error))
11690 goto out_hang;
11691
11692 work = kzalloc(sizeof(*work), GFP_KERNEL);
11693 if (work == NULL)
11694 return -ENOMEM;
11695
11696 work->event = event;
11697 work->crtc = crtc;
11698 work->old_fb = old_fb;
11699 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
11700
11701 ret = drm_crtc_vblank_get(crtc);
11702 if (ret)
11703 goto free_work;
11704
11705 /* We borrow the event spin lock for protecting flip_work */
11706 spin_lock_irq(&dev->event_lock);
11707 if (intel_crtc->flip_work) {
11708 /* Before declaring the flip queue wedged, check if
11709 * the hardware completed the operation behind our backs.
11710 */
11711 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
11712 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11713 page_flip_completed(intel_crtc);
11714 } else {
11715 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11716 spin_unlock_irq(&dev->event_lock);
11717
11718 drm_crtc_vblank_put(crtc);
11719 kfree(work);
11720 return -EBUSY;
11721 }
11722 }
11723 intel_crtc->flip_work = work;
11724 spin_unlock_irq(&dev->event_lock);
11725
11726 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11727 flush_workqueue(dev_priv->wq);
11728
11729 /* Reference the objects for the scheduled work. */
11730 drm_framebuffer_reference(work->old_fb);
11731 drm_gem_object_reference(&obj->base);
11732
11733 crtc->primary->fb = fb;
11734 update_state_fb(crtc->primary);
11735
11736 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
11737 to_intel_plane_state(primary->state));
11738
11739 work->pending_flip_obj = obj;
11740
11741 ret = i915_mutex_lock_interruptible(dev);
11742 if (ret)
11743 goto cleanup;
11744
11745 intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
11746 if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
11747 ret = -EIO;
11748 goto cleanup;
11749 }
11750
11751 atomic_inc(&intel_crtc->unpin_work_count);
11752
11753 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11754 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11755
11756 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11757 engine = &dev_priv->engine[BCS];
11758 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11759 /* vlv: DISPLAY_FLIP fails to change tiling */
11760 engine = NULL;
11761 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11762 engine = &dev_priv->engine[BCS];
11763 } else if (INTEL_INFO(dev)->gen >= 7) {
11764 engine = i915_gem_request_get_engine(obj->last_write_req);
11765 if (engine == NULL || engine->id != RCS)
11766 engine = &dev_priv->engine[BCS];
11767 } else {
11768 engine = &dev_priv->engine[RCS];
11769 }
11770
11771 mmio_flip = use_mmio_flip(engine, obj);
11772
11773 /* When using CS flips, we want to emit semaphores between rings.
11774 * However, when using mmio flips we will create a task to do the
11775 * synchronisation, so all we want here is to pin the framebuffer
11776 * into the display plane and skip any waits.
11777 */
11778 if (!mmio_flip) {
11779 ret = i915_gem_object_sync(obj, engine, &request);
11780 if (!ret && !request) {
11781 request = i915_gem_request_alloc(engine, NULL);
11782 ret = PTR_ERR_OR_ZERO(request);
11783 }
11784
11785 if (ret)
11786 goto cleanup_pending;
11787 }
11788
11789 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11790 if (ret)
11791 goto cleanup_pending;
11792
11793 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11794 obj, 0);
11795 work->gtt_offset += intel_crtc->dspaddr_offset;
11796 work->rotation = crtc->primary->state->rotation;
11797
11798 if (mmio_flip) {
11799 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
11800
11801 i915_gem_request_assign(&work->flip_queued_req,
11802 obj->last_write_req);
11803
11804 schedule_work(&work->mmio_work);
11805 } else {
11806 i915_gem_request_assign(&work->flip_queued_req, request);
11807 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11808 page_flip_flags);
11809 if (ret)
11810 goto cleanup_unpin;
11811
11812 intel_mark_page_flip_active(intel_crtc, work);
11813
11814 i915_add_request_no_flush(request);
11815 }
11816
11817 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
11818 to_intel_plane(primary)->frontbuffer_bit);
11819 mutex_unlock(&dev->struct_mutex);
11820
11821 intel_frontbuffer_flip_prepare(dev,
11822 to_intel_plane(primary)->frontbuffer_bit);
11823
11824 trace_i915_flip_request(intel_crtc->plane, obj);
11825
11826 return 0;
11827
11828 cleanup_unpin:
11829 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11830 cleanup_pending:
11831 if (!IS_ERR_OR_NULL(request))
11832 i915_add_request_no_flush(request);
11833 atomic_dec(&intel_crtc->unpin_work_count);
11834 mutex_unlock(&dev->struct_mutex);
11835 cleanup:
11836 crtc->primary->fb = old_fb;
11837 update_state_fb(crtc->primary);
11838
11839 drm_gem_object_unreference_unlocked(&obj->base);
11840 drm_framebuffer_unreference(work->old_fb);
11841
11842 spin_lock_irq(&dev->event_lock);
11843 intel_crtc->flip_work = NULL;
11844 spin_unlock_irq(&dev->event_lock);
11845
11846 drm_crtc_vblank_put(crtc);
11847 free_work:
11848 kfree(work);
11849
11850 if (ret == -EIO) {
11851 struct drm_atomic_state *state;
11852 struct drm_plane_state *plane_state;
11853
11854 out_hang:
11855 state = drm_atomic_state_alloc(dev);
11856 if (!state)
11857 return -ENOMEM;
11858 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11859
11860 retry:
11861 plane_state = drm_atomic_get_plane_state(state, primary);
11862 ret = PTR_ERR_OR_ZERO(plane_state);
11863 if (!ret) {
11864 drm_atomic_set_fb_for_plane(plane_state, fb);
11865
11866 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11867 if (!ret)
11868 ret = drm_atomic_commit(state);
11869 }
11870
11871 if (ret == -EDEADLK) {
11872 drm_modeset_backoff(state->acquire_ctx);
11873 drm_atomic_state_clear(state);
11874 goto retry;
11875 }
11876
11877 if (ret)
11878 drm_atomic_state_free(state);
11879
11880 if (ret == 0 && event) {
11881 spin_lock_irq(&dev->event_lock);
11882 drm_crtc_send_vblank_event(crtc, event);
11883 spin_unlock_irq(&dev->event_lock);
11884 }
11885 }
11886 return ret;
11887 }
11888
11889
11890 /**
11891 * intel_wm_need_update - Check whether watermarks need updating
11892 * @plane: drm plane
11893 * @state: new plane state
11894 *
11895 * Check current plane state versus the new one to determine whether
11896 * watermarks need to be recalculated.
11897 *
11898 * Returns true or false.
11899 */
11900 static bool intel_wm_need_update(struct drm_plane *plane,
11901 struct drm_plane_state *state)
11902 {
11903 struct intel_plane_state *new = to_intel_plane_state(state);
11904 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11905
11906 /* Update watermarks on tiling or size changes. */
11907 if (new->visible != cur->visible)
11908 return true;
11909
11910 if (!cur->base.fb || !new->base.fb)
11911 return false;
11912
11913 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11914 cur->base.rotation != new->base.rotation ||
11915 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11916 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11917 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11918 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11919 return true;
11920
11921 return false;
11922 }
11923
11924 static bool needs_scaling(struct intel_plane_state *state)
11925 {
11926 int src_w = drm_rect_width(&state->src) >> 16;
11927 int src_h = drm_rect_height(&state->src) >> 16;
11928 int dst_w = drm_rect_width(&state->dst);
11929 int dst_h = drm_rect_height(&state->dst);
11930
11931 return (src_w != dst_w || src_h != dst_h);
11932 }
11933
11934 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11935 struct drm_plane_state *plane_state)
11936 {
11937 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11938 struct drm_crtc *crtc = crtc_state->crtc;
11939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11940 struct drm_plane *plane = plane_state->plane;
11941 struct drm_device *dev = crtc->dev;
11942 struct drm_i915_private *dev_priv = to_i915(dev);
11943 struct intel_plane_state *old_plane_state =
11944 to_intel_plane_state(plane->state);
11945 bool mode_changed = needs_modeset(crtc_state);
11946 bool was_crtc_enabled = crtc->state->active;
11947 bool is_crtc_enabled = crtc_state->active;
11948 bool turn_off, turn_on, visible, was_visible;
11949 struct drm_framebuffer *fb = plane_state->fb;
11950 int ret;
11951
11952 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11953 plane->type != DRM_PLANE_TYPE_CURSOR) {
11954 ret = skl_update_scaler_plane(
11955 to_intel_crtc_state(crtc_state),
11956 to_intel_plane_state(plane_state));
11957 if (ret)
11958 return ret;
11959 }
11960
11961 was_visible = old_plane_state->visible;
11962 visible = to_intel_plane_state(plane_state)->visible;
11963
11964 if (!was_crtc_enabled && WARN_ON(was_visible))
11965 was_visible = false;
11966
11967 /*
11968 * Visibility is calculated as if the crtc was on, but
11969 * after scaler setup everything depends on it being off
11970 * when the crtc isn't active.
11971 *
11972 * FIXME this is wrong for watermarks. Watermarks should also
11973 * be computed as if the pipe would be active. Perhaps move
11974 * per-plane wm computation to the .check_plane() hook, and
11975 * only combine the results from all planes in the current place?
11976 */
11977 if (!is_crtc_enabled)
11978 to_intel_plane_state(plane_state)->visible = visible = false;
11979
11980 if (!was_visible && !visible)
11981 return 0;
11982
11983 if (fb != old_plane_state->base.fb)
11984 pipe_config->fb_changed = true;
11985
11986 turn_off = was_visible && (!visible || mode_changed);
11987 turn_on = visible && (!was_visible || mode_changed);
11988
11989 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11990 intel_crtc->base.base.id,
11991 intel_crtc->base.name,
11992 plane->base.id, plane->name,
11993 fb ? fb->base.id : -1);
11994
11995 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
11996 plane->base.id, plane->name,
11997 was_visible, visible,
11998 turn_off, turn_on, mode_changed);
11999
12000 if (turn_on) {
12001 pipe_config->update_wm_pre = true;
12002
12003 /* must disable cxsr around plane enable/disable */
12004 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12005 pipe_config->disable_cxsr = true;
12006 } else if (turn_off) {
12007 pipe_config->update_wm_post = true;
12008
12009 /* must disable cxsr around plane enable/disable */
12010 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12011 pipe_config->disable_cxsr = true;
12012 } else if (intel_wm_need_update(plane, plane_state)) {
12013 /* FIXME bollocks */
12014 pipe_config->update_wm_pre = true;
12015 pipe_config->update_wm_post = true;
12016 }
12017
12018 /* Pre-gen9 platforms need two-step watermark updates */
12019 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12020 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12021 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12022
12023 if (visible || was_visible)
12024 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12025
12026 /*
12027 * WaCxSRDisabledForSpriteScaling:ivb
12028 *
12029 * cstate->update_wm was already set above, so this flag will
12030 * take effect when we commit and program watermarks.
12031 */
12032 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12033 needs_scaling(to_intel_plane_state(plane_state)) &&
12034 !needs_scaling(old_plane_state))
12035 pipe_config->disable_lp_wm = true;
12036
12037 return 0;
12038 }
12039
12040 static bool encoders_cloneable(const struct intel_encoder *a,
12041 const struct intel_encoder *b)
12042 {
12043 /* masks could be asymmetric, so check both ways */
12044 return a == b || (a->cloneable & (1 << b->type) &&
12045 b->cloneable & (1 << a->type));
12046 }
12047
12048 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12049 struct intel_crtc *crtc,
12050 struct intel_encoder *encoder)
12051 {
12052 struct intel_encoder *source_encoder;
12053 struct drm_connector *connector;
12054 struct drm_connector_state *connector_state;
12055 int i;
12056
12057 for_each_connector_in_state(state, connector, connector_state, i) {
12058 if (connector_state->crtc != &crtc->base)
12059 continue;
12060
12061 source_encoder =
12062 to_intel_encoder(connector_state->best_encoder);
12063 if (!encoders_cloneable(encoder, source_encoder))
12064 return false;
12065 }
12066
12067 return true;
12068 }
12069
12070 static bool check_encoder_cloning(struct drm_atomic_state *state,
12071 struct intel_crtc *crtc)
12072 {
12073 struct intel_encoder *encoder;
12074 struct drm_connector *connector;
12075 struct drm_connector_state *connector_state;
12076 int i;
12077
12078 for_each_connector_in_state(state, connector, connector_state, i) {
12079 if (connector_state->crtc != &crtc->base)
12080 continue;
12081
12082 encoder = to_intel_encoder(connector_state->best_encoder);
12083 if (!check_single_encoder_cloning(state, crtc, encoder))
12084 return false;
12085 }
12086
12087 return true;
12088 }
12089
12090 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12091 struct drm_crtc_state *crtc_state)
12092 {
12093 struct drm_device *dev = crtc->dev;
12094 struct drm_i915_private *dev_priv = dev->dev_private;
12095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12096 struct intel_crtc_state *pipe_config =
12097 to_intel_crtc_state(crtc_state);
12098 struct drm_atomic_state *state = crtc_state->state;
12099 int ret;
12100 bool mode_changed = needs_modeset(crtc_state);
12101
12102 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12103 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12104 return -EINVAL;
12105 }
12106
12107 if (mode_changed && !crtc_state->active)
12108 pipe_config->update_wm_post = true;
12109
12110 if (mode_changed && crtc_state->enable &&
12111 dev_priv->display.crtc_compute_clock &&
12112 !WARN_ON(pipe_config->shared_dpll)) {
12113 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12114 pipe_config);
12115 if (ret)
12116 return ret;
12117 }
12118
12119 if (crtc_state->color_mgmt_changed) {
12120 ret = intel_color_check(crtc, crtc_state);
12121 if (ret)
12122 return ret;
12123 }
12124
12125 ret = 0;
12126 if (dev_priv->display.compute_pipe_wm) {
12127 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12128 if (ret) {
12129 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12130 return ret;
12131 }
12132 }
12133
12134 if (dev_priv->display.compute_intermediate_wm &&
12135 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12136 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12137 return 0;
12138
12139 /*
12140 * Calculate 'intermediate' watermarks that satisfy both the
12141 * old state and the new state. We can program these
12142 * immediately.
12143 */
12144 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12145 intel_crtc,
12146 pipe_config);
12147 if (ret) {
12148 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12149 return ret;
12150 }
12151 } else if (dev_priv->display.compute_intermediate_wm) {
12152 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12153 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12154 }
12155
12156 if (INTEL_INFO(dev)->gen >= 9) {
12157 if (mode_changed)
12158 ret = skl_update_scaler_crtc(pipe_config);
12159
12160 if (!ret)
12161 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12162 pipe_config);
12163 }
12164
12165 return ret;
12166 }
12167
12168 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12169 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12170 .atomic_begin = intel_begin_crtc_commit,
12171 .atomic_flush = intel_finish_crtc_commit,
12172 .atomic_check = intel_crtc_atomic_check,
12173 };
12174
12175 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12176 {
12177 struct intel_connector *connector;
12178
12179 for_each_intel_connector(dev, connector) {
12180 if (connector->base.state->crtc)
12181 drm_connector_unreference(&connector->base);
12182
12183 if (connector->base.encoder) {
12184 connector->base.state->best_encoder =
12185 connector->base.encoder;
12186 connector->base.state->crtc =
12187 connector->base.encoder->crtc;
12188
12189 drm_connector_reference(&connector->base);
12190 } else {
12191 connector->base.state->best_encoder = NULL;
12192 connector->base.state->crtc = NULL;
12193 }
12194 }
12195 }
12196
12197 static void
12198 connected_sink_compute_bpp(struct intel_connector *connector,
12199 struct intel_crtc_state *pipe_config)
12200 {
12201 int bpp = pipe_config->pipe_bpp;
12202
12203 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12204 connector->base.base.id,
12205 connector->base.name);
12206
12207 /* Don't use an invalid EDID bpc value */
12208 if (connector->base.display_info.bpc &&
12209 connector->base.display_info.bpc * 3 < bpp) {
12210 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12211 bpp, connector->base.display_info.bpc*3);
12212 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12213 }
12214
12215 /* Clamp bpp to default limit on screens without EDID 1.4 */
12216 if (connector->base.display_info.bpc == 0) {
12217 int type = connector->base.connector_type;
12218 int clamp_bpp = 24;
12219
12220 /* Fall back to 18 bpp when DP sink capability is unknown. */
12221 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12222 type == DRM_MODE_CONNECTOR_eDP)
12223 clamp_bpp = 18;
12224
12225 if (bpp > clamp_bpp) {
12226 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12227 bpp, clamp_bpp);
12228 pipe_config->pipe_bpp = clamp_bpp;
12229 }
12230 }
12231 }
12232
12233 static int
12234 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12235 struct intel_crtc_state *pipe_config)
12236 {
12237 struct drm_device *dev = crtc->base.dev;
12238 struct drm_atomic_state *state;
12239 struct drm_connector *connector;
12240 struct drm_connector_state *connector_state;
12241 int bpp, i;
12242
12243 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12244 bpp = 10*3;
12245 else if (INTEL_INFO(dev)->gen >= 5)
12246 bpp = 12*3;
12247 else
12248 bpp = 8*3;
12249
12250
12251 pipe_config->pipe_bpp = bpp;
12252
12253 state = pipe_config->base.state;
12254
12255 /* Clamp display bpp to EDID value */
12256 for_each_connector_in_state(state, connector, connector_state, i) {
12257 if (connector_state->crtc != &crtc->base)
12258 continue;
12259
12260 connected_sink_compute_bpp(to_intel_connector(connector),
12261 pipe_config);
12262 }
12263
12264 return bpp;
12265 }
12266
12267 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12268 {
12269 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12270 "type: 0x%x flags: 0x%x\n",
12271 mode->crtc_clock,
12272 mode->crtc_hdisplay, mode->crtc_hsync_start,
12273 mode->crtc_hsync_end, mode->crtc_htotal,
12274 mode->crtc_vdisplay, mode->crtc_vsync_start,
12275 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12276 }
12277
12278 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12279 struct intel_crtc_state *pipe_config,
12280 const char *context)
12281 {
12282 struct drm_device *dev = crtc->base.dev;
12283 struct drm_plane *plane;
12284 struct intel_plane *intel_plane;
12285 struct intel_plane_state *state;
12286 struct drm_framebuffer *fb;
12287
12288 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12289 crtc->base.base.id, crtc->base.name,
12290 context, pipe_config, pipe_name(crtc->pipe));
12291
12292 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12293 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12294 pipe_config->pipe_bpp, pipe_config->dither);
12295 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12296 pipe_config->has_pch_encoder,
12297 pipe_config->fdi_lanes,
12298 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12299 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12300 pipe_config->fdi_m_n.tu);
12301 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12302 pipe_config->has_dp_encoder,
12303 pipe_config->lane_count,
12304 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12305 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12306 pipe_config->dp_m_n.tu);
12307
12308 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12309 pipe_config->has_dp_encoder,
12310 pipe_config->lane_count,
12311 pipe_config->dp_m2_n2.gmch_m,
12312 pipe_config->dp_m2_n2.gmch_n,
12313 pipe_config->dp_m2_n2.link_m,
12314 pipe_config->dp_m2_n2.link_n,
12315 pipe_config->dp_m2_n2.tu);
12316
12317 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12318 pipe_config->has_audio,
12319 pipe_config->has_infoframe);
12320
12321 DRM_DEBUG_KMS("requested mode:\n");
12322 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12323 DRM_DEBUG_KMS("adjusted mode:\n");
12324 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12325 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12326 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12327 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12328 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12329 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12330 crtc->num_scalers,
12331 pipe_config->scaler_state.scaler_users,
12332 pipe_config->scaler_state.scaler_id);
12333 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12334 pipe_config->gmch_pfit.control,
12335 pipe_config->gmch_pfit.pgm_ratios,
12336 pipe_config->gmch_pfit.lvds_border_bits);
12337 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12338 pipe_config->pch_pfit.pos,
12339 pipe_config->pch_pfit.size,
12340 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12341 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12342 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12343
12344 if (IS_BROXTON(dev)) {
12345 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12346 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12347 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12348 pipe_config->ddi_pll_sel,
12349 pipe_config->dpll_hw_state.ebb0,
12350 pipe_config->dpll_hw_state.ebb4,
12351 pipe_config->dpll_hw_state.pll0,
12352 pipe_config->dpll_hw_state.pll1,
12353 pipe_config->dpll_hw_state.pll2,
12354 pipe_config->dpll_hw_state.pll3,
12355 pipe_config->dpll_hw_state.pll6,
12356 pipe_config->dpll_hw_state.pll8,
12357 pipe_config->dpll_hw_state.pll9,
12358 pipe_config->dpll_hw_state.pll10,
12359 pipe_config->dpll_hw_state.pcsdw12);
12360 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12361 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12362 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12363 pipe_config->ddi_pll_sel,
12364 pipe_config->dpll_hw_state.ctrl1,
12365 pipe_config->dpll_hw_state.cfgcr1,
12366 pipe_config->dpll_hw_state.cfgcr2);
12367 } else if (HAS_DDI(dev)) {
12368 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12369 pipe_config->ddi_pll_sel,
12370 pipe_config->dpll_hw_state.wrpll,
12371 pipe_config->dpll_hw_state.spll);
12372 } else {
12373 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12374 "fp0: 0x%x, fp1: 0x%x\n",
12375 pipe_config->dpll_hw_state.dpll,
12376 pipe_config->dpll_hw_state.dpll_md,
12377 pipe_config->dpll_hw_state.fp0,
12378 pipe_config->dpll_hw_state.fp1);
12379 }
12380
12381 DRM_DEBUG_KMS("planes on this crtc\n");
12382 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12383 intel_plane = to_intel_plane(plane);
12384 if (intel_plane->pipe != crtc->pipe)
12385 continue;
12386
12387 state = to_intel_plane_state(plane->state);
12388 fb = state->base.fb;
12389 if (!fb) {
12390 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12391 plane->base.id, plane->name, state->scaler_id);
12392 continue;
12393 }
12394
12395 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12396 plane->base.id, plane->name);
12397 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12398 fb->base.id, fb->width, fb->height,
12399 drm_get_format_name(fb->pixel_format));
12400 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12401 state->scaler_id,
12402 state->src.x1 >> 16, state->src.y1 >> 16,
12403 drm_rect_width(&state->src) >> 16,
12404 drm_rect_height(&state->src) >> 16,
12405 state->dst.x1, state->dst.y1,
12406 drm_rect_width(&state->dst),
12407 drm_rect_height(&state->dst));
12408 }
12409 }
12410
12411 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12412 {
12413 struct drm_device *dev = state->dev;
12414 struct drm_connector *connector;
12415 unsigned int used_ports = 0;
12416
12417 /*
12418 * Walk the connector list instead of the encoder
12419 * list to detect the problem on ddi platforms
12420 * where there's just one encoder per digital port.
12421 */
12422 drm_for_each_connector(connector, dev) {
12423 struct drm_connector_state *connector_state;
12424 struct intel_encoder *encoder;
12425
12426 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12427 if (!connector_state)
12428 connector_state = connector->state;
12429
12430 if (!connector_state->best_encoder)
12431 continue;
12432
12433 encoder = to_intel_encoder(connector_state->best_encoder);
12434
12435 WARN_ON(!connector_state->crtc);
12436
12437 switch (encoder->type) {
12438 unsigned int port_mask;
12439 case INTEL_OUTPUT_UNKNOWN:
12440 if (WARN_ON(!HAS_DDI(dev)))
12441 break;
12442 case INTEL_OUTPUT_DISPLAYPORT:
12443 case INTEL_OUTPUT_HDMI:
12444 case INTEL_OUTPUT_EDP:
12445 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12446
12447 /* the same port mustn't appear more than once */
12448 if (used_ports & port_mask)
12449 return false;
12450
12451 used_ports |= port_mask;
12452 default:
12453 break;
12454 }
12455 }
12456
12457 return true;
12458 }
12459
12460 static void
12461 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12462 {
12463 struct drm_crtc_state tmp_state;
12464 struct intel_crtc_scaler_state scaler_state;
12465 struct intel_dpll_hw_state dpll_hw_state;
12466 struct intel_shared_dpll *shared_dpll;
12467 uint32_t ddi_pll_sel;
12468 bool force_thru;
12469
12470 /* FIXME: before the switch to atomic started, a new pipe_config was
12471 * kzalloc'd. Code that depends on any field being zero should be
12472 * fixed, so that the crtc_state can be safely duplicated. For now,
12473 * only fields that are know to not cause problems are preserved. */
12474
12475 tmp_state = crtc_state->base;
12476 scaler_state = crtc_state->scaler_state;
12477 shared_dpll = crtc_state->shared_dpll;
12478 dpll_hw_state = crtc_state->dpll_hw_state;
12479 ddi_pll_sel = crtc_state->ddi_pll_sel;
12480 force_thru = crtc_state->pch_pfit.force_thru;
12481
12482 memset(crtc_state, 0, sizeof *crtc_state);
12483
12484 crtc_state->base = tmp_state;
12485 crtc_state->scaler_state = scaler_state;
12486 crtc_state->shared_dpll = shared_dpll;
12487 crtc_state->dpll_hw_state = dpll_hw_state;
12488 crtc_state->ddi_pll_sel = ddi_pll_sel;
12489 crtc_state->pch_pfit.force_thru = force_thru;
12490 }
12491
12492 static int
12493 intel_modeset_pipe_config(struct drm_crtc *crtc,
12494 struct intel_crtc_state *pipe_config)
12495 {
12496 struct drm_atomic_state *state = pipe_config->base.state;
12497 struct intel_encoder *encoder;
12498 struct drm_connector *connector;
12499 struct drm_connector_state *connector_state;
12500 int base_bpp, ret = -EINVAL;
12501 int i;
12502 bool retry = true;
12503
12504 clear_intel_crtc_state(pipe_config);
12505
12506 pipe_config->cpu_transcoder =
12507 (enum transcoder) to_intel_crtc(crtc)->pipe;
12508
12509 /*
12510 * Sanitize sync polarity flags based on requested ones. If neither
12511 * positive or negative polarity is requested, treat this as meaning
12512 * negative polarity.
12513 */
12514 if (!(pipe_config->base.adjusted_mode.flags &
12515 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12516 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12517
12518 if (!(pipe_config->base.adjusted_mode.flags &
12519 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12520 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12521
12522 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12523 pipe_config);
12524 if (base_bpp < 0)
12525 goto fail;
12526
12527 /*
12528 * Determine the real pipe dimensions. Note that stereo modes can
12529 * increase the actual pipe size due to the frame doubling and
12530 * insertion of additional space for blanks between the frame. This
12531 * is stored in the crtc timings. We use the requested mode to do this
12532 * computation to clearly distinguish it from the adjusted mode, which
12533 * can be changed by the connectors in the below retry loop.
12534 */
12535 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12536 &pipe_config->pipe_src_w,
12537 &pipe_config->pipe_src_h);
12538
12539 encoder_retry:
12540 /* Ensure the port clock defaults are reset when retrying. */
12541 pipe_config->port_clock = 0;
12542 pipe_config->pixel_multiplier = 1;
12543
12544 /* Fill in default crtc timings, allow encoders to overwrite them. */
12545 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12546 CRTC_STEREO_DOUBLE);
12547
12548 /* Pass our mode to the connectors and the CRTC to give them a chance to
12549 * adjust it according to limitations or connector properties, and also
12550 * a chance to reject the mode entirely.
12551 */
12552 for_each_connector_in_state(state, connector, connector_state, i) {
12553 if (connector_state->crtc != crtc)
12554 continue;
12555
12556 encoder = to_intel_encoder(connector_state->best_encoder);
12557
12558 if (!(encoder->compute_config(encoder, pipe_config))) {
12559 DRM_DEBUG_KMS("Encoder config failure\n");
12560 goto fail;
12561 }
12562 }
12563
12564 /* Set default port clock if not overwritten by the encoder. Needs to be
12565 * done afterwards in case the encoder adjusts the mode. */
12566 if (!pipe_config->port_clock)
12567 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12568 * pipe_config->pixel_multiplier;
12569
12570 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12571 if (ret < 0) {
12572 DRM_DEBUG_KMS("CRTC fixup failed\n");
12573 goto fail;
12574 }
12575
12576 if (ret == RETRY) {
12577 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12578 ret = -EINVAL;
12579 goto fail;
12580 }
12581
12582 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12583 retry = false;
12584 goto encoder_retry;
12585 }
12586
12587 /* Dithering seems to not pass-through bits correctly when it should, so
12588 * only enable it on 6bpc panels. */
12589 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12590 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12591 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12592
12593 fail:
12594 return ret;
12595 }
12596
12597 static void
12598 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12599 {
12600 struct drm_crtc *crtc;
12601 struct drm_crtc_state *crtc_state;
12602 int i;
12603
12604 /* Double check state. */
12605 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12606 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12607
12608 /* Update hwmode for vblank functions */
12609 if (crtc->state->active)
12610 crtc->hwmode = crtc->state->adjusted_mode;
12611 else
12612 crtc->hwmode.crtc_clock = 0;
12613
12614 /*
12615 * Update legacy state to satisfy fbc code. This can
12616 * be removed when fbc uses the atomic state.
12617 */
12618 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12619 struct drm_plane_state *plane_state = crtc->primary->state;
12620
12621 crtc->primary->fb = plane_state->fb;
12622 crtc->x = plane_state->src_x >> 16;
12623 crtc->y = plane_state->src_y >> 16;
12624 }
12625 }
12626 }
12627
12628 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12629 {
12630 int diff;
12631
12632 if (clock1 == clock2)
12633 return true;
12634
12635 if (!clock1 || !clock2)
12636 return false;
12637
12638 diff = abs(clock1 - clock2);
12639
12640 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12641 return true;
12642
12643 return false;
12644 }
12645
12646 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12647 list_for_each_entry((intel_crtc), \
12648 &(dev)->mode_config.crtc_list, \
12649 base.head) \
12650 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12651
12652 static bool
12653 intel_compare_m_n(unsigned int m, unsigned int n,
12654 unsigned int m2, unsigned int n2,
12655 bool exact)
12656 {
12657 if (m == m2 && n == n2)
12658 return true;
12659
12660 if (exact || !m || !n || !m2 || !n2)
12661 return false;
12662
12663 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12664
12665 if (n > n2) {
12666 while (n > n2) {
12667 m2 <<= 1;
12668 n2 <<= 1;
12669 }
12670 } else if (n < n2) {
12671 while (n < n2) {
12672 m <<= 1;
12673 n <<= 1;
12674 }
12675 }
12676
12677 if (n != n2)
12678 return false;
12679
12680 return intel_fuzzy_clock_check(m, m2);
12681 }
12682
12683 static bool
12684 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12685 struct intel_link_m_n *m2_n2,
12686 bool adjust)
12687 {
12688 if (m_n->tu == m2_n2->tu &&
12689 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12690 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12691 intel_compare_m_n(m_n->link_m, m_n->link_n,
12692 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12693 if (adjust)
12694 *m2_n2 = *m_n;
12695
12696 return true;
12697 }
12698
12699 return false;
12700 }
12701
12702 static bool
12703 intel_pipe_config_compare(struct drm_device *dev,
12704 struct intel_crtc_state *current_config,
12705 struct intel_crtc_state *pipe_config,
12706 bool adjust)
12707 {
12708 bool ret = true;
12709
12710 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12711 do { \
12712 if (!adjust) \
12713 DRM_ERROR(fmt, ##__VA_ARGS__); \
12714 else \
12715 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12716 } while (0)
12717
12718 #define PIPE_CONF_CHECK_X(name) \
12719 if (current_config->name != pipe_config->name) { \
12720 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12721 "(expected 0x%08x, found 0x%08x)\n", \
12722 current_config->name, \
12723 pipe_config->name); \
12724 ret = false; \
12725 }
12726
12727 #define PIPE_CONF_CHECK_I(name) \
12728 if (current_config->name != pipe_config->name) { \
12729 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12730 "(expected %i, found %i)\n", \
12731 current_config->name, \
12732 pipe_config->name); \
12733 ret = false; \
12734 }
12735
12736 #define PIPE_CONF_CHECK_P(name) \
12737 if (current_config->name != pipe_config->name) { \
12738 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12739 "(expected %p, found %p)\n", \
12740 current_config->name, \
12741 pipe_config->name); \
12742 ret = false; \
12743 }
12744
12745 #define PIPE_CONF_CHECK_M_N(name) \
12746 if (!intel_compare_link_m_n(&current_config->name, \
12747 &pipe_config->name,\
12748 adjust)) { \
12749 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12750 "(expected tu %i gmch %i/%i link %i/%i, " \
12751 "found tu %i, gmch %i/%i link %i/%i)\n", \
12752 current_config->name.tu, \
12753 current_config->name.gmch_m, \
12754 current_config->name.gmch_n, \
12755 current_config->name.link_m, \
12756 current_config->name.link_n, \
12757 pipe_config->name.tu, \
12758 pipe_config->name.gmch_m, \
12759 pipe_config->name.gmch_n, \
12760 pipe_config->name.link_m, \
12761 pipe_config->name.link_n); \
12762 ret = false; \
12763 }
12764
12765 /* This is required for BDW+ where there is only one set of registers for
12766 * switching between high and low RR.
12767 * This macro can be used whenever a comparison has to be made between one
12768 * hw state and multiple sw state variables.
12769 */
12770 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12771 if (!intel_compare_link_m_n(&current_config->name, \
12772 &pipe_config->name, adjust) && \
12773 !intel_compare_link_m_n(&current_config->alt_name, \
12774 &pipe_config->name, adjust)) { \
12775 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12776 "(expected tu %i gmch %i/%i link %i/%i, " \
12777 "or tu %i gmch %i/%i link %i/%i, " \
12778 "found tu %i, gmch %i/%i link %i/%i)\n", \
12779 current_config->name.tu, \
12780 current_config->name.gmch_m, \
12781 current_config->name.gmch_n, \
12782 current_config->name.link_m, \
12783 current_config->name.link_n, \
12784 current_config->alt_name.tu, \
12785 current_config->alt_name.gmch_m, \
12786 current_config->alt_name.gmch_n, \
12787 current_config->alt_name.link_m, \
12788 current_config->alt_name.link_n, \
12789 pipe_config->name.tu, \
12790 pipe_config->name.gmch_m, \
12791 pipe_config->name.gmch_n, \
12792 pipe_config->name.link_m, \
12793 pipe_config->name.link_n); \
12794 ret = false; \
12795 }
12796
12797 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12798 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12799 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12800 "(expected %i, found %i)\n", \
12801 current_config->name & (mask), \
12802 pipe_config->name & (mask)); \
12803 ret = false; \
12804 }
12805
12806 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12807 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12808 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12809 "(expected %i, found %i)\n", \
12810 current_config->name, \
12811 pipe_config->name); \
12812 ret = false; \
12813 }
12814
12815 #define PIPE_CONF_QUIRK(quirk) \
12816 ((current_config->quirks | pipe_config->quirks) & (quirk))
12817
12818 PIPE_CONF_CHECK_I(cpu_transcoder);
12819
12820 PIPE_CONF_CHECK_I(has_pch_encoder);
12821 PIPE_CONF_CHECK_I(fdi_lanes);
12822 PIPE_CONF_CHECK_M_N(fdi_m_n);
12823
12824 PIPE_CONF_CHECK_I(has_dp_encoder);
12825 PIPE_CONF_CHECK_I(lane_count);
12826 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
12827
12828 if (INTEL_INFO(dev)->gen < 8) {
12829 PIPE_CONF_CHECK_M_N(dp_m_n);
12830
12831 if (current_config->has_drrs)
12832 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12833 } else
12834 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12835
12836 PIPE_CONF_CHECK_I(has_dsi_encoder);
12837
12838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12840 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12841 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12842 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12843 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12844
12845 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12846 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12847 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12848 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12849 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12850 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12851
12852 PIPE_CONF_CHECK_I(pixel_multiplier);
12853 PIPE_CONF_CHECK_I(has_hdmi_sink);
12854 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12855 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12856 PIPE_CONF_CHECK_I(limited_color_range);
12857 PIPE_CONF_CHECK_I(has_infoframe);
12858
12859 PIPE_CONF_CHECK_I(has_audio);
12860
12861 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12862 DRM_MODE_FLAG_INTERLACE);
12863
12864 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12865 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12866 DRM_MODE_FLAG_PHSYNC);
12867 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12868 DRM_MODE_FLAG_NHSYNC);
12869 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12870 DRM_MODE_FLAG_PVSYNC);
12871 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12872 DRM_MODE_FLAG_NVSYNC);
12873 }
12874
12875 PIPE_CONF_CHECK_X(gmch_pfit.control);
12876 /* pfit ratios are autocomputed by the hw on gen4+ */
12877 if (INTEL_INFO(dev)->gen < 4)
12878 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12879 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12880
12881 if (!adjust) {
12882 PIPE_CONF_CHECK_I(pipe_src_w);
12883 PIPE_CONF_CHECK_I(pipe_src_h);
12884
12885 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12886 if (current_config->pch_pfit.enabled) {
12887 PIPE_CONF_CHECK_X(pch_pfit.pos);
12888 PIPE_CONF_CHECK_X(pch_pfit.size);
12889 }
12890
12891 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12892 }
12893
12894 /* BDW+ don't expose a synchronous way to read the state */
12895 if (IS_HASWELL(dev))
12896 PIPE_CONF_CHECK_I(ips_enabled);
12897
12898 PIPE_CONF_CHECK_I(double_wide);
12899
12900 PIPE_CONF_CHECK_X(ddi_pll_sel);
12901
12902 PIPE_CONF_CHECK_P(shared_dpll);
12903 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12904 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12905 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12906 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12907 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12908 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12909 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12910 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12911 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12912
12913 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12914 PIPE_CONF_CHECK_X(dsi_pll.div);
12915
12916 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12917 PIPE_CONF_CHECK_I(pipe_bpp);
12918
12919 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12920 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12921
12922 #undef PIPE_CONF_CHECK_X
12923 #undef PIPE_CONF_CHECK_I
12924 #undef PIPE_CONF_CHECK_P
12925 #undef PIPE_CONF_CHECK_FLAGS
12926 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12927 #undef PIPE_CONF_QUIRK
12928 #undef INTEL_ERR_OR_DBG_KMS
12929
12930 return ret;
12931 }
12932
12933 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12934 const struct intel_crtc_state *pipe_config)
12935 {
12936 if (pipe_config->has_pch_encoder) {
12937 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12938 &pipe_config->fdi_m_n);
12939 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12940
12941 /*
12942 * FDI already provided one idea for the dotclock.
12943 * Yell if the encoder disagrees.
12944 */
12945 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12946 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12947 fdi_dotclock, dotclock);
12948 }
12949 }
12950
12951 static void verify_wm_state(struct drm_crtc *crtc,
12952 struct drm_crtc_state *new_state)
12953 {
12954 struct drm_device *dev = crtc->dev;
12955 struct drm_i915_private *dev_priv = dev->dev_private;
12956 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12957 struct skl_ddb_entry *hw_entry, *sw_entry;
12958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12959 const enum pipe pipe = intel_crtc->pipe;
12960 int plane;
12961
12962 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12963 return;
12964
12965 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12966 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12967
12968 /* planes */
12969 for_each_plane(dev_priv, pipe, plane) {
12970 hw_entry = &hw_ddb.plane[pipe][plane];
12971 sw_entry = &sw_ddb->plane[pipe][plane];
12972
12973 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12974 continue;
12975
12976 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12977 "(expected (%u,%u), found (%u,%u))\n",
12978 pipe_name(pipe), plane + 1,
12979 sw_entry->start, sw_entry->end,
12980 hw_entry->start, hw_entry->end);
12981 }
12982
12983 /* cursor */
12984 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12985 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12986
12987 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12988 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12989 "(expected (%u,%u), found (%u,%u))\n",
12990 pipe_name(pipe),
12991 sw_entry->start, sw_entry->end,
12992 hw_entry->start, hw_entry->end);
12993 }
12994 }
12995
12996 static void
12997 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12998 {
12999 struct drm_connector *connector;
13000
13001 drm_for_each_connector(connector, dev) {
13002 struct drm_encoder *encoder = connector->encoder;
13003 struct drm_connector_state *state = connector->state;
13004
13005 if (state->crtc != crtc)
13006 continue;
13007
13008 intel_connector_verify_state(to_intel_connector(connector));
13009
13010 I915_STATE_WARN(state->best_encoder != encoder,
13011 "connector's atomic encoder doesn't match legacy encoder\n");
13012 }
13013 }
13014
13015 static void
13016 verify_encoder_state(struct drm_device *dev)
13017 {
13018 struct intel_encoder *encoder;
13019 struct intel_connector *connector;
13020
13021 for_each_intel_encoder(dev, encoder) {
13022 bool enabled = false;
13023 enum pipe pipe;
13024
13025 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13026 encoder->base.base.id,
13027 encoder->base.name);
13028
13029 for_each_intel_connector(dev, connector) {
13030 if (connector->base.state->best_encoder != &encoder->base)
13031 continue;
13032 enabled = true;
13033
13034 I915_STATE_WARN(connector->base.state->crtc !=
13035 encoder->base.crtc,
13036 "connector's crtc doesn't match encoder crtc\n");
13037 }
13038
13039 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13040 "encoder's enabled state mismatch "
13041 "(expected %i, found %i)\n",
13042 !!encoder->base.crtc, enabled);
13043
13044 if (!encoder->base.crtc) {
13045 bool active;
13046
13047 active = encoder->get_hw_state(encoder, &pipe);
13048 I915_STATE_WARN(active,
13049 "encoder detached but still enabled on pipe %c.\n",
13050 pipe_name(pipe));
13051 }
13052 }
13053 }
13054
13055 static void
13056 verify_crtc_state(struct drm_crtc *crtc,
13057 struct drm_crtc_state *old_crtc_state,
13058 struct drm_crtc_state *new_crtc_state)
13059 {
13060 struct drm_device *dev = crtc->dev;
13061 struct drm_i915_private *dev_priv = dev->dev_private;
13062 struct intel_encoder *encoder;
13063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13064 struct intel_crtc_state *pipe_config, *sw_config;
13065 struct drm_atomic_state *old_state;
13066 bool active;
13067
13068 old_state = old_crtc_state->state;
13069 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13070 pipe_config = to_intel_crtc_state(old_crtc_state);
13071 memset(pipe_config, 0, sizeof(*pipe_config));
13072 pipe_config->base.crtc = crtc;
13073 pipe_config->base.state = old_state;
13074
13075 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13076
13077 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13078
13079 /* hw state is inconsistent with the pipe quirk */
13080 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13081 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13082 active = new_crtc_state->active;
13083
13084 I915_STATE_WARN(new_crtc_state->active != active,
13085 "crtc active state doesn't match with hw state "
13086 "(expected %i, found %i)\n", new_crtc_state->active, active);
13087
13088 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13089 "transitional active state does not match atomic hw state "
13090 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13091
13092 for_each_encoder_on_crtc(dev, crtc, encoder) {
13093 enum pipe pipe;
13094
13095 active = encoder->get_hw_state(encoder, &pipe);
13096 I915_STATE_WARN(active != new_crtc_state->active,
13097 "[ENCODER:%i] active %i with crtc active %i\n",
13098 encoder->base.base.id, active, new_crtc_state->active);
13099
13100 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13101 "Encoder connected to wrong pipe %c\n",
13102 pipe_name(pipe));
13103
13104 if (active)
13105 encoder->get_config(encoder, pipe_config);
13106 }
13107
13108 if (!new_crtc_state->active)
13109 return;
13110
13111 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13112
13113 sw_config = to_intel_crtc_state(crtc->state);
13114 if (!intel_pipe_config_compare(dev, sw_config,
13115 pipe_config, false)) {
13116 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13117 intel_dump_pipe_config(intel_crtc, pipe_config,
13118 "[hw state]");
13119 intel_dump_pipe_config(intel_crtc, sw_config,
13120 "[sw state]");
13121 }
13122 }
13123
13124 static void
13125 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13126 struct intel_shared_dpll *pll,
13127 struct drm_crtc *crtc,
13128 struct drm_crtc_state *new_state)
13129 {
13130 struct intel_dpll_hw_state dpll_hw_state;
13131 unsigned crtc_mask;
13132 bool active;
13133
13134 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13135
13136 DRM_DEBUG_KMS("%s\n", pll->name);
13137
13138 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13139
13140 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13141 I915_STATE_WARN(!pll->on && pll->active_mask,
13142 "pll in active use but not on in sw tracking\n");
13143 I915_STATE_WARN(pll->on && !pll->active_mask,
13144 "pll is on but not used by any active crtc\n");
13145 I915_STATE_WARN(pll->on != active,
13146 "pll on state mismatch (expected %i, found %i)\n",
13147 pll->on, active);
13148 }
13149
13150 if (!crtc) {
13151 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13152 "more active pll users than references: %x vs %x\n",
13153 pll->active_mask, pll->config.crtc_mask);
13154
13155 return;
13156 }
13157
13158 crtc_mask = 1 << drm_crtc_index(crtc);
13159
13160 if (new_state->active)
13161 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13162 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13163 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13164 else
13165 I915_STATE_WARN(pll->active_mask & crtc_mask,
13166 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13167 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13168
13169 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13170 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13171 crtc_mask, pll->config.crtc_mask);
13172
13173 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13174 &dpll_hw_state,
13175 sizeof(dpll_hw_state)),
13176 "pll hw state mismatch\n");
13177 }
13178
13179 static void
13180 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13181 struct drm_crtc_state *old_crtc_state,
13182 struct drm_crtc_state *new_crtc_state)
13183 {
13184 struct drm_i915_private *dev_priv = dev->dev_private;
13185 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13186 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13187
13188 if (new_state->shared_dpll)
13189 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13190
13191 if (old_state->shared_dpll &&
13192 old_state->shared_dpll != new_state->shared_dpll) {
13193 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13194 struct intel_shared_dpll *pll = old_state->shared_dpll;
13195
13196 I915_STATE_WARN(pll->active_mask & crtc_mask,
13197 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13198 pipe_name(drm_crtc_index(crtc)));
13199 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13200 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13201 pipe_name(drm_crtc_index(crtc)));
13202 }
13203 }
13204
13205 static void
13206 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13207 struct drm_crtc_state *old_state,
13208 struct drm_crtc_state *new_state)
13209 {
13210 if (!needs_modeset(new_state) &&
13211 !to_intel_crtc_state(new_state)->update_pipe)
13212 return;
13213
13214 verify_wm_state(crtc, new_state);
13215 verify_connector_state(crtc->dev, crtc);
13216 verify_crtc_state(crtc, old_state, new_state);
13217 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13218 }
13219
13220 static void
13221 verify_disabled_dpll_state(struct drm_device *dev)
13222 {
13223 struct drm_i915_private *dev_priv = dev->dev_private;
13224 int i;
13225
13226 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13227 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13228 }
13229
13230 static void
13231 intel_modeset_verify_disabled(struct drm_device *dev)
13232 {
13233 verify_encoder_state(dev);
13234 verify_connector_state(dev, NULL);
13235 verify_disabled_dpll_state(dev);
13236 }
13237
13238 static void update_scanline_offset(struct intel_crtc *crtc)
13239 {
13240 struct drm_device *dev = crtc->base.dev;
13241
13242 /*
13243 * The scanline counter increments at the leading edge of hsync.
13244 *
13245 * On most platforms it starts counting from vtotal-1 on the
13246 * first active line. That means the scanline counter value is
13247 * always one less than what we would expect. Ie. just after
13248 * start of vblank, which also occurs at start of hsync (on the
13249 * last active line), the scanline counter will read vblank_start-1.
13250 *
13251 * On gen2 the scanline counter starts counting from 1 instead
13252 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13253 * to keep the value positive), instead of adding one.
13254 *
13255 * On HSW+ the behaviour of the scanline counter depends on the output
13256 * type. For DP ports it behaves like most other platforms, but on HDMI
13257 * there's an extra 1 line difference. So we need to add two instead of
13258 * one to the value.
13259 */
13260 if (IS_GEN2(dev)) {
13261 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13262 int vtotal;
13263
13264 vtotal = adjusted_mode->crtc_vtotal;
13265 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13266 vtotal /= 2;
13267
13268 crtc->scanline_offset = vtotal - 1;
13269 } else if (HAS_DDI(dev) &&
13270 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13271 crtc->scanline_offset = 2;
13272 } else
13273 crtc->scanline_offset = 1;
13274 }
13275
13276 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13277 {
13278 struct drm_device *dev = state->dev;
13279 struct drm_i915_private *dev_priv = to_i915(dev);
13280 struct intel_shared_dpll_config *shared_dpll = NULL;
13281 struct drm_crtc *crtc;
13282 struct drm_crtc_state *crtc_state;
13283 int i;
13284
13285 if (!dev_priv->display.crtc_compute_clock)
13286 return;
13287
13288 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13290 struct intel_shared_dpll *old_dpll =
13291 to_intel_crtc_state(crtc->state)->shared_dpll;
13292
13293 if (!needs_modeset(crtc_state))
13294 continue;
13295
13296 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13297
13298 if (!old_dpll)
13299 continue;
13300
13301 if (!shared_dpll)
13302 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13303
13304 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13305 }
13306 }
13307
13308 /*
13309 * This implements the workaround described in the "notes" section of the mode
13310 * set sequence documentation. When going from no pipes or single pipe to
13311 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13312 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13313 */
13314 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13315 {
13316 struct drm_crtc_state *crtc_state;
13317 struct intel_crtc *intel_crtc;
13318 struct drm_crtc *crtc;
13319 struct intel_crtc_state *first_crtc_state = NULL;
13320 struct intel_crtc_state *other_crtc_state = NULL;
13321 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13322 int i;
13323
13324 /* look at all crtc's that are going to be enabled in during modeset */
13325 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13326 intel_crtc = to_intel_crtc(crtc);
13327
13328 if (!crtc_state->active || !needs_modeset(crtc_state))
13329 continue;
13330
13331 if (first_crtc_state) {
13332 other_crtc_state = to_intel_crtc_state(crtc_state);
13333 break;
13334 } else {
13335 first_crtc_state = to_intel_crtc_state(crtc_state);
13336 first_pipe = intel_crtc->pipe;
13337 }
13338 }
13339
13340 /* No workaround needed? */
13341 if (!first_crtc_state)
13342 return 0;
13343
13344 /* w/a possibly needed, check how many crtc's are already enabled. */
13345 for_each_intel_crtc(state->dev, intel_crtc) {
13346 struct intel_crtc_state *pipe_config;
13347
13348 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13349 if (IS_ERR(pipe_config))
13350 return PTR_ERR(pipe_config);
13351
13352 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13353
13354 if (!pipe_config->base.active ||
13355 needs_modeset(&pipe_config->base))
13356 continue;
13357
13358 /* 2 or more enabled crtcs means no need for w/a */
13359 if (enabled_pipe != INVALID_PIPE)
13360 return 0;
13361
13362 enabled_pipe = intel_crtc->pipe;
13363 }
13364
13365 if (enabled_pipe != INVALID_PIPE)
13366 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13367 else if (other_crtc_state)
13368 other_crtc_state->hsw_workaround_pipe = first_pipe;
13369
13370 return 0;
13371 }
13372
13373 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13374 {
13375 struct drm_crtc *crtc;
13376 struct drm_crtc_state *crtc_state;
13377 int ret = 0;
13378
13379 /* add all active pipes to the state */
13380 for_each_crtc(state->dev, crtc) {
13381 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13382 if (IS_ERR(crtc_state))
13383 return PTR_ERR(crtc_state);
13384
13385 if (!crtc_state->active || needs_modeset(crtc_state))
13386 continue;
13387
13388 crtc_state->mode_changed = true;
13389
13390 ret = drm_atomic_add_affected_connectors(state, crtc);
13391 if (ret)
13392 break;
13393
13394 ret = drm_atomic_add_affected_planes(state, crtc);
13395 if (ret)
13396 break;
13397 }
13398
13399 return ret;
13400 }
13401
13402 static int intel_modeset_checks(struct drm_atomic_state *state)
13403 {
13404 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13405 struct drm_i915_private *dev_priv = state->dev->dev_private;
13406 struct drm_crtc *crtc;
13407 struct drm_crtc_state *crtc_state;
13408 int ret = 0, i;
13409
13410 if (!check_digital_port_conflicts(state)) {
13411 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13412 return -EINVAL;
13413 }
13414
13415 intel_state->modeset = true;
13416 intel_state->active_crtcs = dev_priv->active_crtcs;
13417
13418 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13419 if (crtc_state->active)
13420 intel_state->active_crtcs |= 1 << i;
13421 else
13422 intel_state->active_crtcs &= ~(1 << i);
13423
13424 if (crtc_state->active != crtc->state->active)
13425 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13426 }
13427
13428 /*
13429 * See if the config requires any additional preparation, e.g.
13430 * to adjust global state with pipes off. We need to do this
13431 * here so we can get the modeset_pipe updated config for the new
13432 * mode set on this crtc. For other crtcs we need to use the
13433 * adjusted_mode bits in the crtc directly.
13434 */
13435 if (dev_priv->display.modeset_calc_cdclk) {
13436 if (!intel_state->cdclk_pll_vco)
13437 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13438 if (!intel_state->cdclk_pll_vco)
13439 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13440
13441 ret = dev_priv->display.modeset_calc_cdclk(state);
13442 if (ret < 0)
13443 return ret;
13444
13445 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13446 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13447 ret = intel_modeset_all_pipes(state);
13448
13449 if (ret < 0)
13450 return ret;
13451
13452 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13453 intel_state->cdclk, intel_state->dev_cdclk);
13454 } else
13455 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13456
13457 intel_modeset_clear_plls(state);
13458
13459 if (IS_HASWELL(dev_priv))
13460 return haswell_mode_set_planes_workaround(state);
13461
13462 return 0;
13463 }
13464
13465 /*
13466 * Handle calculation of various watermark data at the end of the atomic check
13467 * phase. The code here should be run after the per-crtc and per-plane 'check'
13468 * handlers to ensure that all derived state has been updated.
13469 */
13470 static int calc_watermark_data(struct drm_atomic_state *state)
13471 {
13472 struct drm_device *dev = state->dev;
13473 struct drm_i915_private *dev_priv = to_i915(dev);
13474
13475 /* Is there platform-specific watermark information to calculate? */
13476 if (dev_priv->display.compute_global_watermarks)
13477 return dev_priv->display.compute_global_watermarks(state);
13478
13479 return 0;
13480 }
13481
13482 /**
13483 * intel_atomic_check - validate state object
13484 * @dev: drm device
13485 * @state: state to validate
13486 */
13487 static int intel_atomic_check(struct drm_device *dev,
13488 struct drm_atomic_state *state)
13489 {
13490 struct drm_i915_private *dev_priv = to_i915(dev);
13491 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13492 struct drm_crtc *crtc;
13493 struct drm_crtc_state *crtc_state;
13494 int ret, i;
13495 bool any_ms = false;
13496
13497 ret = drm_atomic_helper_check_modeset(dev, state);
13498 if (ret)
13499 return ret;
13500
13501 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13502 struct intel_crtc_state *pipe_config =
13503 to_intel_crtc_state(crtc_state);
13504
13505 /* Catch I915_MODE_FLAG_INHERITED */
13506 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13507 crtc_state->mode_changed = true;
13508
13509 if (!needs_modeset(crtc_state))
13510 continue;
13511
13512 if (!crtc_state->enable) {
13513 any_ms = true;
13514 continue;
13515 }
13516
13517 /* FIXME: For only active_changed we shouldn't need to do any
13518 * state recomputation at all. */
13519
13520 ret = drm_atomic_add_affected_connectors(state, crtc);
13521 if (ret)
13522 return ret;
13523
13524 ret = intel_modeset_pipe_config(crtc, pipe_config);
13525 if (ret) {
13526 intel_dump_pipe_config(to_intel_crtc(crtc),
13527 pipe_config, "[failed]");
13528 return ret;
13529 }
13530
13531 if (i915.fastboot &&
13532 intel_pipe_config_compare(dev,
13533 to_intel_crtc_state(crtc->state),
13534 pipe_config, true)) {
13535 crtc_state->mode_changed = false;
13536 to_intel_crtc_state(crtc_state)->update_pipe = true;
13537 }
13538
13539 if (needs_modeset(crtc_state))
13540 any_ms = true;
13541
13542 ret = drm_atomic_add_affected_planes(state, crtc);
13543 if (ret)
13544 return ret;
13545
13546 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13547 needs_modeset(crtc_state) ?
13548 "[modeset]" : "[fastset]");
13549 }
13550
13551 if (any_ms) {
13552 ret = intel_modeset_checks(state);
13553
13554 if (ret)
13555 return ret;
13556 } else
13557 intel_state->cdclk = dev_priv->cdclk_freq;
13558
13559 ret = drm_atomic_helper_check_planes(dev, state);
13560 if (ret)
13561 return ret;
13562
13563 intel_fbc_choose_crtc(dev_priv, state);
13564 return calc_watermark_data(state);
13565 }
13566
13567 static int intel_atomic_prepare_commit(struct drm_device *dev,
13568 struct drm_atomic_state *state,
13569 bool nonblock)
13570 {
13571 struct drm_i915_private *dev_priv = dev->dev_private;
13572 struct drm_plane_state *plane_state;
13573 struct drm_crtc_state *crtc_state;
13574 struct drm_plane *plane;
13575 struct drm_crtc *crtc;
13576 int i, ret;
13577
13578 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13579 if (state->legacy_cursor_update)
13580 continue;
13581
13582 ret = intel_crtc_wait_for_pending_flips(crtc);
13583 if (ret)
13584 return ret;
13585
13586 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13587 flush_workqueue(dev_priv->wq);
13588 }
13589
13590 ret = mutex_lock_interruptible(&dev->struct_mutex);
13591 if (ret)
13592 return ret;
13593
13594 ret = drm_atomic_helper_prepare_planes(dev, state);
13595 mutex_unlock(&dev->struct_mutex);
13596
13597 if (!ret && !nonblock) {
13598 for_each_plane_in_state(state, plane, plane_state, i) {
13599 struct intel_plane_state *intel_plane_state =
13600 to_intel_plane_state(plane_state);
13601
13602 if (!intel_plane_state->wait_req)
13603 continue;
13604
13605 ret = __i915_wait_request(intel_plane_state->wait_req,
13606 true, NULL, NULL);
13607 if (ret) {
13608 /* Any hang should be swallowed by the wait */
13609 WARN_ON(ret == -EIO);
13610 mutex_lock(&dev->struct_mutex);
13611 drm_atomic_helper_cleanup_planes(dev, state);
13612 mutex_unlock(&dev->struct_mutex);
13613 break;
13614 }
13615 }
13616 }
13617
13618 return ret;
13619 }
13620
13621 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
13622 {
13623 struct drm_device *dev = crtc->base.dev;
13624
13625 if (!dev->max_vblank_count)
13626 return drm_accurate_vblank_count(&crtc->base);
13627
13628 return dev->driver->get_vblank_counter(dev, crtc->pipe);
13629 }
13630
13631 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13632 struct drm_i915_private *dev_priv,
13633 unsigned crtc_mask)
13634 {
13635 unsigned last_vblank_count[I915_MAX_PIPES];
13636 enum pipe pipe;
13637 int ret;
13638
13639 if (!crtc_mask)
13640 return;
13641
13642 for_each_pipe(dev_priv, pipe) {
13643 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13644
13645 if (!((1 << pipe) & crtc_mask))
13646 continue;
13647
13648 ret = drm_crtc_vblank_get(crtc);
13649 if (WARN_ON(ret != 0)) {
13650 crtc_mask &= ~(1 << pipe);
13651 continue;
13652 }
13653
13654 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13655 }
13656
13657 for_each_pipe(dev_priv, pipe) {
13658 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13659 long lret;
13660
13661 if (!((1 << pipe) & crtc_mask))
13662 continue;
13663
13664 lret = wait_event_timeout(dev->vblank[pipe].queue,
13665 last_vblank_count[pipe] !=
13666 drm_crtc_vblank_count(crtc),
13667 msecs_to_jiffies(50));
13668
13669 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
13670
13671 drm_crtc_vblank_put(crtc);
13672 }
13673 }
13674
13675 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13676 {
13677 /* fb updated, need to unpin old fb */
13678 if (crtc_state->fb_changed)
13679 return true;
13680
13681 /* wm changes, need vblank before final wm's */
13682 if (crtc_state->update_wm_post)
13683 return true;
13684
13685 /*
13686 * cxsr is re-enabled after vblank.
13687 * This is already handled by crtc_state->update_wm_post,
13688 * but added for clarity.
13689 */
13690 if (crtc_state->disable_cxsr)
13691 return true;
13692
13693 return false;
13694 }
13695
13696 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
13697 {
13698 struct drm_device *dev = state->dev;
13699 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13700 struct drm_i915_private *dev_priv = dev->dev_private;
13701 struct drm_crtc_state *old_crtc_state;
13702 struct drm_crtc *crtc;
13703 struct intel_crtc_state *intel_cstate;
13704 struct drm_plane *plane;
13705 struct drm_plane_state *plane_state;
13706 bool hw_check = intel_state->modeset;
13707 unsigned long put_domains[I915_MAX_PIPES] = {};
13708 unsigned crtc_vblank_mask = 0;
13709 int i, ret;
13710
13711 for_each_plane_in_state(state, plane, plane_state, i) {
13712 struct intel_plane_state *intel_plane_state =
13713 to_intel_plane_state(plane_state);
13714
13715 if (!intel_plane_state->wait_req)
13716 continue;
13717
13718 ret = __i915_wait_request(intel_plane_state->wait_req,
13719 true, NULL, NULL);
13720 /* EIO should be eaten, and we can't get interrupted in the
13721 * worker, and blocking commits have waited already. */
13722 WARN_ON(ret);
13723 }
13724
13725 drm_atomic_helper_wait_for_dependencies(state);
13726
13727 if (intel_state->modeset) {
13728 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13729 sizeof(intel_state->min_pixclk));
13730 dev_priv->active_crtcs = intel_state->active_crtcs;
13731 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13732
13733 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13734 }
13735
13736 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13738
13739 if (needs_modeset(crtc->state) ||
13740 to_intel_crtc_state(crtc->state)->update_pipe) {
13741 hw_check = true;
13742
13743 put_domains[to_intel_crtc(crtc)->pipe] =
13744 modeset_get_crtc_power_domains(crtc,
13745 to_intel_crtc_state(crtc->state));
13746 }
13747
13748 if (!needs_modeset(crtc->state))
13749 continue;
13750
13751 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13752
13753 if (old_crtc_state->active) {
13754 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13755 dev_priv->display.crtc_disable(crtc);
13756 intel_crtc->active = false;
13757 intel_fbc_disable(intel_crtc);
13758 intel_disable_shared_dpll(intel_crtc);
13759
13760 /*
13761 * Underruns don't always raise
13762 * interrupts, so check manually.
13763 */
13764 intel_check_cpu_fifo_underruns(dev_priv);
13765 intel_check_pch_fifo_underruns(dev_priv);
13766
13767 if (!crtc->state->active)
13768 intel_update_watermarks(crtc);
13769 }
13770 }
13771
13772 /* Only after disabling all output pipelines that will be changed can we
13773 * update the the output configuration. */
13774 intel_modeset_update_crtc_state(state);
13775
13776 if (intel_state->modeset) {
13777 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13778
13779 if (dev_priv->display.modeset_commit_cdclk &&
13780 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13781 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13782 dev_priv->display.modeset_commit_cdclk(state);
13783
13784 intel_modeset_verify_disabled(dev);
13785 }
13786
13787 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13788 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13790 bool modeset = needs_modeset(crtc->state);
13791 struct intel_crtc_state *pipe_config =
13792 to_intel_crtc_state(crtc->state);
13793
13794 if (modeset && crtc->state->active) {
13795 update_scanline_offset(to_intel_crtc(crtc));
13796 dev_priv->display.crtc_enable(crtc);
13797 }
13798
13799 /* Complete events for now disable pipes here. */
13800 if (modeset && !crtc->state->active && crtc->state->event) {
13801 spin_lock_irq(&dev->event_lock);
13802 drm_crtc_send_vblank_event(crtc, crtc->state->event);
13803 spin_unlock_irq(&dev->event_lock);
13804
13805 crtc->state->event = NULL;
13806 }
13807
13808 if (!modeset)
13809 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13810
13811 if (crtc->state->active &&
13812 drm_atomic_get_existing_plane_state(state, crtc->primary))
13813 intel_fbc_enable(intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state));
13814
13815 if (crtc->state->active)
13816 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13817
13818 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13819 crtc_vblank_mask |= 1 << i;
13820 }
13821
13822 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13823 * already, but still need the state for the delayed optimization. To
13824 * fix this:
13825 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
13826 * - schedule that vblank worker _before_ calling hw_done
13827 * - at the start of commit_tail, cancel it _synchrously
13828 * - switch over to the vblank wait helper in the core after that since
13829 * we don't need out special handling any more.
13830 */
13831 if (!state->legacy_cursor_update)
13832 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13833
13834 /*
13835 * Now that the vblank has passed, we can go ahead and program the
13836 * optimal watermarks on platforms that need two-step watermark
13837 * programming.
13838 *
13839 * TODO: Move this (and other cleanup) to an async worker eventually.
13840 */
13841 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13842 intel_cstate = to_intel_crtc_state(crtc->state);
13843
13844 if (dev_priv->display.optimize_watermarks)
13845 dev_priv->display.optimize_watermarks(intel_cstate);
13846 }
13847
13848 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13849 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13850
13851 if (put_domains[i])
13852 modeset_put_power_domains(dev_priv, put_domains[i]);
13853
13854 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
13855 }
13856
13857 drm_atomic_helper_commit_hw_done(state);
13858
13859 if (intel_state->modeset)
13860 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13861
13862 mutex_lock(&dev->struct_mutex);
13863 drm_atomic_helper_cleanup_planes(dev, state);
13864 mutex_unlock(&dev->struct_mutex);
13865
13866 drm_atomic_helper_commit_cleanup_done(state);
13867
13868 drm_atomic_state_free(state);
13869
13870 /* As one of the primary mmio accessors, KMS has a high likelihood
13871 * of triggering bugs in unclaimed access. After we finish
13872 * modesetting, see if an error has been flagged, and if so
13873 * enable debugging for the next modeset - and hope we catch
13874 * the culprit.
13875 *
13876 * XXX note that we assume display power is on at this point.
13877 * This might hold true now but we need to add pm helper to check
13878 * unclaimed only when the hardware is on, as atomic commits
13879 * can happen also when the device is completely off.
13880 */
13881 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13882 }
13883
13884 static void intel_atomic_commit_work(struct work_struct *work)
13885 {
13886 struct drm_atomic_state *state = container_of(work,
13887 struct drm_atomic_state,
13888 commit_work);
13889 intel_atomic_commit_tail(state);
13890 }
13891
13892 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13893 {
13894 struct drm_plane_state *old_plane_state;
13895 struct drm_plane *plane;
13896 struct drm_i915_gem_object *obj, *old_obj;
13897 struct intel_plane *intel_plane;
13898 int i;
13899
13900 mutex_lock(&state->dev->struct_mutex);
13901 for_each_plane_in_state(state, plane, old_plane_state, i) {
13902 obj = intel_fb_obj(plane->state->fb);
13903 old_obj = intel_fb_obj(old_plane_state->fb);
13904 intel_plane = to_intel_plane(plane);
13905
13906 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13907 }
13908 mutex_unlock(&state->dev->struct_mutex);
13909 }
13910
13911 /**
13912 * intel_atomic_commit - commit validated state object
13913 * @dev: DRM device
13914 * @state: the top-level driver state object
13915 * @nonblock: nonblocking commit
13916 *
13917 * This function commits a top-level state object that has been validated
13918 * with drm_atomic_helper_check().
13919 *
13920 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13921 * nonblocking commits are only safe for pure plane updates. Everything else
13922 * should work though.
13923 *
13924 * RETURNS
13925 * Zero for success or -errno.
13926 */
13927 static int intel_atomic_commit(struct drm_device *dev,
13928 struct drm_atomic_state *state,
13929 bool nonblock)
13930 {
13931 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13932 struct drm_i915_private *dev_priv = dev->dev_private;
13933 int ret = 0;
13934
13935 if (intel_state->modeset && nonblock) {
13936 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
13937 return -EINVAL;
13938 }
13939
13940 ret = drm_atomic_helper_setup_commit(state, nonblock);
13941 if (ret)
13942 return ret;
13943
13944 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
13945
13946 ret = intel_atomic_prepare_commit(dev, state, nonblock);
13947 if (ret) {
13948 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13949 return ret;
13950 }
13951
13952 drm_atomic_helper_swap_state(state, true);
13953 dev_priv->wm.distrust_bios_wm = false;
13954 dev_priv->wm.skl_results = intel_state->wm_results;
13955 intel_shared_dpll_commit(state);
13956 intel_atomic_track_fbs(state);
13957
13958 if (nonblock)
13959 queue_work(system_unbound_wq, &state->commit_work);
13960 else
13961 intel_atomic_commit_tail(state);
13962
13963 return 0;
13964 }
13965
13966 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13967 {
13968 struct drm_device *dev = crtc->dev;
13969 struct drm_atomic_state *state;
13970 struct drm_crtc_state *crtc_state;
13971 int ret;
13972
13973 state = drm_atomic_state_alloc(dev);
13974 if (!state) {
13975 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13976 crtc->base.id, crtc->name);
13977 return;
13978 }
13979
13980 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13981
13982 retry:
13983 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13984 ret = PTR_ERR_OR_ZERO(crtc_state);
13985 if (!ret) {
13986 if (!crtc_state->active)
13987 goto out;
13988
13989 crtc_state->mode_changed = true;
13990 ret = drm_atomic_commit(state);
13991 }
13992
13993 if (ret == -EDEADLK) {
13994 drm_atomic_state_clear(state);
13995 drm_modeset_backoff(state->acquire_ctx);
13996 goto retry;
13997 }
13998
13999 if (ret)
14000 out:
14001 drm_atomic_state_free(state);
14002 }
14003
14004 #undef for_each_intel_crtc_masked
14005
14006 static const struct drm_crtc_funcs intel_crtc_funcs = {
14007 .gamma_set = drm_atomic_helper_legacy_gamma_set,
14008 .set_config = drm_atomic_helper_set_config,
14009 .set_property = drm_atomic_helper_crtc_set_property,
14010 .destroy = intel_crtc_destroy,
14011 .page_flip = drm_atomic_helper_page_flip,
14012 .atomic_duplicate_state = intel_crtc_duplicate_state,
14013 .atomic_destroy_state = intel_crtc_destroy_state,
14014 };
14015
14016 /**
14017 * intel_prepare_plane_fb - Prepare fb for usage on plane
14018 * @plane: drm plane to prepare for
14019 * @fb: framebuffer to prepare for presentation
14020 *
14021 * Prepares a framebuffer for usage on a display plane. Generally this
14022 * involves pinning the underlying object and updating the frontbuffer tracking
14023 * bits. Some older platforms need special physical address handling for
14024 * cursor planes.
14025 *
14026 * Must be called with struct_mutex held.
14027 *
14028 * Returns 0 on success, negative error code on failure.
14029 */
14030 int
14031 intel_prepare_plane_fb(struct drm_plane *plane,
14032 const struct drm_plane_state *new_state)
14033 {
14034 struct drm_device *dev = plane->dev;
14035 struct drm_framebuffer *fb = new_state->fb;
14036 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14037 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14038 struct reservation_object *resv;
14039 int ret = 0;
14040
14041 if (!obj && !old_obj)
14042 return 0;
14043
14044 if (old_obj) {
14045 struct drm_crtc_state *crtc_state =
14046 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14047
14048 /* Big Hammer, we also need to ensure that any pending
14049 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14050 * current scanout is retired before unpinning the old
14051 * framebuffer. Note that we rely on userspace rendering
14052 * into the buffer attached to the pipe they are waiting
14053 * on. If not, userspace generates a GPU hang with IPEHR
14054 * point to the MI_WAIT_FOR_EVENT.
14055 *
14056 * This should only fail upon a hung GPU, in which case we
14057 * can safely continue.
14058 */
14059 if (needs_modeset(crtc_state))
14060 ret = i915_gem_object_wait_rendering(old_obj, true);
14061 if (ret) {
14062 /* GPU hangs should have been swallowed by the wait */
14063 WARN_ON(ret == -EIO);
14064 return ret;
14065 }
14066 }
14067
14068 if (!obj)
14069 return 0;
14070
14071 /* For framebuffer backed by dmabuf, wait for fence */
14072 resv = i915_gem_object_get_dmabuf_resv(obj);
14073 if (resv) {
14074 long lret;
14075
14076 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14077 MAX_SCHEDULE_TIMEOUT);
14078 if (lret == -ERESTARTSYS)
14079 return lret;
14080
14081 WARN(lret < 0, "waiting returns %li\n", lret);
14082 }
14083
14084 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14085 INTEL_INFO(dev)->cursor_needs_physical) {
14086 int align = IS_I830(dev) ? 16 * 1024 : 256;
14087 ret = i915_gem_object_attach_phys(obj, align);
14088 if (ret)
14089 DRM_DEBUG_KMS("failed to attach phys object\n");
14090 } else {
14091 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14092 }
14093
14094 if (ret == 0) {
14095 struct intel_plane_state *plane_state =
14096 to_intel_plane_state(new_state);
14097
14098 i915_gem_request_assign(&plane_state->wait_req,
14099 obj->last_write_req);
14100 }
14101
14102 return ret;
14103 }
14104
14105 /**
14106 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14107 * @plane: drm plane to clean up for
14108 * @fb: old framebuffer that was on plane
14109 *
14110 * Cleans up a framebuffer that has just been removed from a plane.
14111 *
14112 * Must be called with struct_mutex held.
14113 */
14114 void
14115 intel_cleanup_plane_fb(struct drm_plane *plane,
14116 const struct drm_plane_state *old_state)
14117 {
14118 struct drm_device *dev = plane->dev;
14119 struct intel_plane_state *old_intel_state;
14120 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14121 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14122
14123 old_intel_state = to_intel_plane_state(old_state);
14124
14125 if (!obj && !old_obj)
14126 return;
14127
14128 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14129 !INTEL_INFO(dev)->cursor_needs_physical))
14130 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14131
14132 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14133 }
14134
14135 int
14136 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14137 {
14138 int max_scale;
14139 struct drm_device *dev;
14140 struct drm_i915_private *dev_priv;
14141 int crtc_clock, cdclk;
14142
14143 if (!intel_crtc || !crtc_state->base.enable)
14144 return DRM_PLANE_HELPER_NO_SCALING;
14145
14146 dev = intel_crtc->base.dev;
14147 dev_priv = dev->dev_private;
14148 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14149 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14150
14151 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14152 return DRM_PLANE_HELPER_NO_SCALING;
14153
14154 /*
14155 * skl max scale is lower of:
14156 * close to 3 but not 3, -1 is for that purpose
14157 * or
14158 * cdclk/crtc_clock
14159 */
14160 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14161
14162 return max_scale;
14163 }
14164
14165 static int
14166 intel_check_primary_plane(struct drm_plane *plane,
14167 struct intel_crtc_state *crtc_state,
14168 struct intel_plane_state *state)
14169 {
14170 struct drm_crtc *crtc = state->base.crtc;
14171 struct drm_framebuffer *fb = state->base.fb;
14172 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14173 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14174 bool can_position = false;
14175
14176 if (INTEL_INFO(plane->dev)->gen >= 9) {
14177 /* use scaler when colorkey is not required */
14178 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14179 min_scale = 1;
14180 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14181 }
14182 can_position = true;
14183 }
14184
14185 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14186 &state->dst, &state->clip,
14187 state->base.rotation,
14188 min_scale, max_scale,
14189 can_position, true,
14190 &state->visible);
14191 }
14192
14193 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14194 struct drm_crtc_state *old_crtc_state)
14195 {
14196 struct drm_device *dev = crtc->dev;
14197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14198 struct intel_crtc_state *old_intel_state =
14199 to_intel_crtc_state(old_crtc_state);
14200 bool modeset = needs_modeset(crtc->state);
14201
14202 /* Perform vblank evasion around commit operation */
14203 intel_pipe_update_start(intel_crtc);
14204
14205 if (modeset)
14206 return;
14207
14208 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14209 intel_color_set_csc(crtc->state);
14210 intel_color_load_luts(crtc->state);
14211 }
14212
14213 if (to_intel_crtc_state(crtc->state)->update_pipe)
14214 intel_update_pipe_config(intel_crtc, old_intel_state);
14215 else if (INTEL_INFO(dev)->gen >= 9)
14216 skl_detach_scalers(intel_crtc);
14217 }
14218
14219 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14220 struct drm_crtc_state *old_crtc_state)
14221 {
14222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14223
14224 intel_pipe_update_end(intel_crtc, NULL);
14225 }
14226
14227 /**
14228 * intel_plane_destroy - destroy a plane
14229 * @plane: plane to destroy
14230 *
14231 * Common destruction function for all types of planes (primary, cursor,
14232 * sprite).
14233 */
14234 void intel_plane_destroy(struct drm_plane *plane)
14235 {
14236 if (!plane)
14237 return;
14238
14239 drm_plane_cleanup(plane);
14240 kfree(to_intel_plane(plane));
14241 }
14242
14243 const struct drm_plane_funcs intel_plane_funcs = {
14244 .update_plane = drm_atomic_helper_update_plane,
14245 .disable_plane = drm_atomic_helper_disable_plane,
14246 .destroy = intel_plane_destroy,
14247 .set_property = drm_atomic_helper_plane_set_property,
14248 .atomic_get_property = intel_plane_atomic_get_property,
14249 .atomic_set_property = intel_plane_atomic_set_property,
14250 .atomic_duplicate_state = intel_plane_duplicate_state,
14251 .atomic_destroy_state = intel_plane_destroy_state,
14252
14253 };
14254
14255 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14256 int pipe)
14257 {
14258 struct intel_plane *primary = NULL;
14259 struct intel_plane_state *state = NULL;
14260 const uint32_t *intel_primary_formats;
14261 unsigned int num_formats;
14262 int ret;
14263
14264 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14265 if (!primary)
14266 goto fail;
14267
14268 state = intel_create_plane_state(&primary->base);
14269 if (!state)
14270 goto fail;
14271 primary->base.state = &state->base;
14272
14273 primary->can_scale = false;
14274 primary->max_downscale = 1;
14275 if (INTEL_INFO(dev)->gen >= 9) {
14276 primary->can_scale = true;
14277 state->scaler_id = -1;
14278 }
14279 primary->pipe = pipe;
14280 primary->plane = pipe;
14281 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14282 primary->check_plane = intel_check_primary_plane;
14283 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14284 primary->plane = !pipe;
14285
14286 if (INTEL_INFO(dev)->gen >= 9) {
14287 intel_primary_formats = skl_primary_formats;
14288 num_formats = ARRAY_SIZE(skl_primary_formats);
14289
14290 primary->update_plane = skylake_update_primary_plane;
14291 primary->disable_plane = skylake_disable_primary_plane;
14292 } else if (HAS_PCH_SPLIT(dev)) {
14293 intel_primary_formats = i965_primary_formats;
14294 num_formats = ARRAY_SIZE(i965_primary_formats);
14295
14296 primary->update_plane = ironlake_update_primary_plane;
14297 primary->disable_plane = i9xx_disable_primary_plane;
14298 } else if (INTEL_INFO(dev)->gen >= 4) {
14299 intel_primary_formats = i965_primary_formats;
14300 num_formats = ARRAY_SIZE(i965_primary_formats);
14301
14302 primary->update_plane = i9xx_update_primary_plane;
14303 primary->disable_plane = i9xx_disable_primary_plane;
14304 } else {
14305 intel_primary_formats = i8xx_primary_formats;
14306 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14307
14308 primary->update_plane = i9xx_update_primary_plane;
14309 primary->disable_plane = i9xx_disable_primary_plane;
14310 }
14311
14312 if (INTEL_INFO(dev)->gen >= 9)
14313 ret = drm_universal_plane_init(dev, &primary->base, 0,
14314 &intel_plane_funcs,
14315 intel_primary_formats, num_formats,
14316 DRM_PLANE_TYPE_PRIMARY,
14317 "plane 1%c", pipe_name(pipe));
14318 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14319 ret = drm_universal_plane_init(dev, &primary->base, 0,
14320 &intel_plane_funcs,
14321 intel_primary_formats, num_formats,
14322 DRM_PLANE_TYPE_PRIMARY,
14323 "primary %c", pipe_name(pipe));
14324 else
14325 ret = drm_universal_plane_init(dev, &primary->base, 0,
14326 &intel_plane_funcs,
14327 intel_primary_formats, num_formats,
14328 DRM_PLANE_TYPE_PRIMARY,
14329 "plane %c", plane_name(primary->plane));
14330 if (ret)
14331 goto fail;
14332
14333 if (INTEL_INFO(dev)->gen >= 4)
14334 intel_create_rotation_property(dev, primary);
14335
14336 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14337
14338 return &primary->base;
14339
14340 fail:
14341 kfree(state);
14342 kfree(primary);
14343
14344 return NULL;
14345 }
14346
14347 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14348 {
14349 if (!dev->mode_config.rotation_property) {
14350 unsigned long flags = BIT(DRM_ROTATE_0) |
14351 BIT(DRM_ROTATE_180);
14352
14353 if (INTEL_INFO(dev)->gen >= 9)
14354 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14355
14356 dev->mode_config.rotation_property =
14357 drm_mode_create_rotation_property(dev, flags);
14358 }
14359 if (dev->mode_config.rotation_property)
14360 drm_object_attach_property(&plane->base.base,
14361 dev->mode_config.rotation_property,
14362 plane->base.state->rotation);
14363 }
14364
14365 static int
14366 intel_check_cursor_plane(struct drm_plane *plane,
14367 struct intel_crtc_state *crtc_state,
14368 struct intel_plane_state *state)
14369 {
14370 struct drm_crtc *crtc = crtc_state->base.crtc;
14371 struct drm_framebuffer *fb = state->base.fb;
14372 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14373 enum pipe pipe = to_intel_plane(plane)->pipe;
14374 unsigned stride;
14375 int ret;
14376
14377 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14378 &state->dst, &state->clip,
14379 state->base.rotation,
14380 DRM_PLANE_HELPER_NO_SCALING,
14381 DRM_PLANE_HELPER_NO_SCALING,
14382 true, true, &state->visible);
14383 if (ret)
14384 return ret;
14385
14386 /* if we want to turn off the cursor ignore width and height */
14387 if (!obj)
14388 return 0;
14389
14390 /* Check for which cursor types we support */
14391 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14392 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14393 state->base.crtc_w, state->base.crtc_h);
14394 return -EINVAL;
14395 }
14396
14397 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14398 if (obj->base.size < stride * state->base.crtc_h) {
14399 DRM_DEBUG_KMS("buffer is too small\n");
14400 return -ENOMEM;
14401 }
14402
14403 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14404 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14405 return -EINVAL;
14406 }
14407
14408 /*
14409 * There's something wrong with the cursor on CHV pipe C.
14410 * If it straddles the left edge of the screen then
14411 * moving it away from the edge or disabling it often
14412 * results in a pipe underrun, and often that can lead to
14413 * dead pipe (constant underrun reported, and it scans
14414 * out just a solid color). To recover from that, the
14415 * display power well must be turned off and on again.
14416 * Refuse the put the cursor into that compromised position.
14417 */
14418 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14419 state->visible && state->base.crtc_x < 0) {
14420 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14421 return -EINVAL;
14422 }
14423
14424 return 0;
14425 }
14426
14427 static void
14428 intel_disable_cursor_plane(struct drm_plane *plane,
14429 struct drm_crtc *crtc)
14430 {
14431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14432
14433 intel_crtc->cursor_addr = 0;
14434 intel_crtc_update_cursor(crtc, NULL);
14435 }
14436
14437 static void
14438 intel_update_cursor_plane(struct drm_plane *plane,
14439 const struct intel_crtc_state *crtc_state,
14440 const struct intel_plane_state *state)
14441 {
14442 struct drm_crtc *crtc = crtc_state->base.crtc;
14443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14444 struct drm_device *dev = plane->dev;
14445 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14446 uint32_t addr;
14447
14448 if (!obj)
14449 addr = 0;
14450 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14451 addr = i915_gem_obj_ggtt_offset(obj);
14452 else
14453 addr = obj->phys_handle->busaddr;
14454
14455 intel_crtc->cursor_addr = addr;
14456 intel_crtc_update_cursor(crtc, state);
14457 }
14458
14459 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14460 int pipe)
14461 {
14462 struct intel_plane *cursor = NULL;
14463 struct intel_plane_state *state = NULL;
14464 int ret;
14465
14466 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14467 if (!cursor)
14468 goto fail;
14469
14470 state = intel_create_plane_state(&cursor->base);
14471 if (!state)
14472 goto fail;
14473 cursor->base.state = &state->base;
14474
14475 cursor->can_scale = false;
14476 cursor->max_downscale = 1;
14477 cursor->pipe = pipe;
14478 cursor->plane = pipe;
14479 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14480 cursor->check_plane = intel_check_cursor_plane;
14481 cursor->update_plane = intel_update_cursor_plane;
14482 cursor->disable_plane = intel_disable_cursor_plane;
14483
14484 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14485 &intel_plane_funcs,
14486 intel_cursor_formats,
14487 ARRAY_SIZE(intel_cursor_formats),
14488 DRM_PLANE_TYPE_CURSOR,
14489 "cursor %c", pipe_name(pipe));
14490 if (ret)
14491 goto fail;
14492
14493 if (INTEL_INFO(dev)->gen >= 4) {
14494 if (!dev->mode_config.rotation_property)
14495 dev->mode_config.rotation_property =
14496 drm_mode_create_rotation_property(dev,
14497 BIT(DRM_ROTATE_0) |
14498 BIT(DRM_ROTATE_180));
14499 if (dev->mode_config.rotation_property)
14500 drm_object_attach_property(&cursor->base.base,
14501 dev->mode_config.rotation_property,
14502 state->base.rotation);
14503 }
14504
14505 if (INTEL_INFO(dev)->gen >=9)
14506 state->scaler_id = -1;
14507
14508 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14509
14510 return &cursor->base;
14511
14512 fail:
14513 kfree(state);
14514 kfree(cursor);
14515
14516 return NULL;
14517 }
14518
14519 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14520 struct intel_crtc_state *crtc_state)
14521 {
14522 int i;
14523 struct intel_scaler *intel_scaler;
14524 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14525
14526 for (i = 0; i < intel_crtc->num_scalers; i++) {
14527 intel_scaler = &scaler_state->scalers[i];
14528 intel_scaler->in_use = 0;
14529 intel_scaler->mode = PS_SCALER_MODE_DYN;
14530 }
14531
14532 scaler_state->scaler_id = -1;
14533 }
14534
14535 static void intel_crtc_init(struct drm_device *dev, int pipe)
14536 {
14537 struct drm_i915_private *dev_priv = dev->dev_private;
14538 struct intel_crtc *intel_crtc;
14539 struct intel_crtc_state *crtc_state = NULL;
14540 struct drm_plane *primary = NULL;
14541 struct drm_plane *cursor = NULL;
14542 int ret;
14543
14544 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14545 if (intel_crtc == NULL)
14546 return;
14547
14548 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14549 if (!crtc_state)
14550 goto fail;
14551 intel_crtc->config = crtc_state;
14552 intel_crtc->base.state = &crtc_state->base;
14553 crtc_state->base.crtc = &intel_crtc->base;
14554
14555 /* initialize shared scalers */
14556 if (INTEL_INFO(dev)->gen >= 9) {
14557 if (pipe == PIPE_C)
14558 intel_crtc->num_scalers = 1;
14559 else
14560 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14561
14562 skl_init_scalers(dev, intel_crtc, crtc_state);
14563 }
14564
14565 primary = intel_primary_plane_create(dev, pipe);
14566 if (!primary)
14567 goto fail;
14568
14569 cursor = intel_cursor_plane_create(dev, pipe);
14570 if (!cursor)
14571 goto fail;
14572
14573 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14574 cursor, &intel_crtc_funcs,
14575 "pipe %c", pipe_name(pipe));
14576 if (ret)
14577 goto fail;
14578
14579 /*
14580 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14581 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14582 */
14583 intel_crtc->pipe = pipe;
14584 intel_crtc->plane = pipe;
14585 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14586 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14587 intel_crtc->plane = !pipe;
14588 }
14589
14590 intel_crtc->cursor_base = ~0;
14591 intel_crtc->cursor_cntl = ~0;
14592 intel_crtc->cursor_size = ~0;
14593
14594 intel_crtc->wm.cxsr_allowed = true;
14595
14596 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14597 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14598 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14599 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14600
14601 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14602
14603 intel_color_init(&intel_crtc->base);
14604
14605 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14606 return;
14607
14608 fail:
14609 intel_plane_destroy(primary);
14610 intel_plane_destroy(cursor);
14611 kfree(crtc_state);
14612 kfree(intel_crtc);
14613 }
14614
14615 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14616 {
14617 struct drm_encoder *encoder = connector->base.encoder;
14618 struct drm_device *dev = connector->base.dev;
14619
14620 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14621
14622 if (!encoder || WARN_ON(!encoder->crtc))
14623 return INVALID_PIPE;
14624
14625 return to_intel_crtc(encoder->crtc)->pipe;
14626 }
14627
14628 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14629 struct drm_file *file)
14630 {
14631 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14632 struct drm_crtc *drmmode_crtc;
14633 struct intel_crtc *crtc;
14634
14635 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14636 if (!drmmode_crtc)
14637 return -ENOENT;
14638
14639 crtc = to_intel_crtc(drmmode_crtc);
14640 pipe_from_crtc_id->pipe = crtc->pipe;
14641
14642 return 0;
14643 }
14644
14645 static int intel_encoder_clones(struct intel_encoder *encoder)
14646 {
14647 struct drm_device *dev = encoder->base.dev;
14648 struct intel_encoder *source_encoder;
14649 int index_mask = 0;
14650 int entry = 0;
14651
14652 for_each_intel_encoder(dev, source_encoder) {
14653 if (encoders_cloneable(encoder, source_encoder))
14654 index_mask |= (1 << entry);
14655
14656 entry++;
14657 }
14658
14659 return index_mask;
14660 }
14661
14662 static bool has_edp_a(struct drm_device *dev)
14663 {
14664 struct drm_i915_private *dev_priv = dev->dev_private;
14665
14666 if (!IS_MOBILE(dev))
14667 return false;
14668
14669 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14670 return false;
14671
14672 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14673 return false;
14674
14675 return true;
14676 }
14677
14678 static bool intel_crt_present(struct drm_device *dev)
14679 {
14680 struct drm_i915_private *dev_priv = dev->dev_private;
14681
14682 if (INTEL_INFO(dev)->gen >= 9)
14683 return false;
14684
14685 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14686 return false;
14687
14688 if (IS_CHERRYVIEW(dev))
14689 return false;
14690
14691 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14692 return false;
14693
14694 /* DDI E can't be used if DDI A requires 4 lanes */
14695 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14696 return false;
14697
14698 if (!dev_priv->vbt.int_crt_support)
14699 return false;
14700
14701 return true;
14702 }
14703
14704 static void intel_setup_outputs(struct drm_device *dev)
14705 {
14706 struct drm_i915_private *dev_priv = dev->dev_private;
14707 struct intel_encoder *encoder;
14708 bool dpd_is_edp = false;
14709
14710 /*
14711 * intel_edp_init_connector() depends on this completing first, to
14712 * prevent the registeration of both eDP and LVDS and the incorrect
14713 * sharing of the PPS.
14714 */
14715 intel_lvds_init(dev);
14716
14717 if (intel_crt_present(dev))
14718 intel_crt_init(dev);
14719
14720 if (IS_BROXTON(dev)) {
14721 /*
14722 * FIXME: Broxton doesn't support port detection via the
14723 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14724 * detect the ports.
14725 */
14726 intel_ddi_init(dev, PORT_A);
14727 intel_ddi_init(dev, PORT_B);
14728 intel_ddi_init(dev, PORT_C);
14729
14730 intel_dsi_init(dev);
14731 } else if (HAS_DDI(dev)) {
14732 int found;
14733
14734 /*
14735 * Haswell uses DDI functions to detect digital outputs.
14736 * On SKL pre-D0 the strap isn't connected, so we assume
14737 * it's there.
14738 */
14739 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14740 /* WaIgnoreDDIAStrap: skl */
14741 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14742 intel_ddi_init(dev, PORT_A);
14743
14744 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14745 * register */
14746 found = I915_READ(SFUSE_STRAP);
14747
14748 if (found & SFUSE_STRAP_DDIB_DETECTED)
14749 intel_ddi_init(dev, PORT_B);
14750 if (found & SFUSE_STRAP_DDIC_DETECTED)
14751 intel_ddi_init(dev, PORT_C);
14752 if (found & SFUSE_STRAP_DDID_DETECTED)
14753 intel_ddi_init(dev, PORT_D);
14754 /*
14755 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14756 */
14757 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14758 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14759 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14760 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14761 intel_ddi_init(dev, PORT_E);
14762
14763 } else if (HAS_PCH_SPLIT(dev)) {
14764 int found;
14765 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14766
14767 if (has_edp_a(dev))
14768 intel_dp_init(dev, DP_A, PORT_A);
14769
14770 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14771 /* PCH SDVOB multiplex with HDMIB */
14772 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14773 if (!found)
14774 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14775 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14776 intel_dp_init(dev, PCH_DP_B, PORT_B);
14777 }
14778
14779 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14780 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14781
14782 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14783 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14784
14785 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14786 intel_dp_init(dev, PCH_DP_C, PORT_C);
14787
14788 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14789 intel_dp_init(dev, PCH_DP_D, PORT_D);
14790 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14791 bool has_edp, has_port;
14792
14793 /*
14794 * The DP_DETECTED bit is the latched state of the DDC
14795 * SDA pin at boot. However since eDP doesn't require DDC
14796 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14797 * eDP ports may have been muxed to an alternate function.
14798 * Thus we can't rely on the DP_DETECTED bit alone to detect
14799 * eDP ports. Consult the VBT as well as DP_DETECTED to
14800 * detect eDP ports.
14801 *
14802 * Sadly the straps seem to be missing sometimes even for HDMI
14803 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14804 * and VBT for the presence of the port. Additionally we can't
14805 * trust the port type the VBT declares as we've seen at least
14806 * HDMI ports that the VBT claim are DP or eDP.
14807 */
14808 has_edp = intel_dp_is_edp(dev, PORT_B);
14809 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14810 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14811 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
14812 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14813 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14814
14815 has_edp = intel_dp_is_edp(dev, PORT_C);
14816 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14817 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14818 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
14819 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14820 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14821
14822 if (IS_CHERRYVIEW(dev)) {
14823 /*
14824 * eDP not supported on port D,
14825 * so no need to worry about it
14826 */
14827 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14828 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14829 intel_dp_init(dev, CHV_DP_D, PORT_D);
14830 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14831 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14832 }
14833
14834 intel_dsi_init(dev);
14835 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14836 bool found = false;
14837
14838 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14839 DRM_DEBUG_KMS("probing SDVOB\n");
14840 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14841 if (!found && IS_G4X(dev)) {
14842 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14843 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14844 }
14845
14846 if (!found && IS_G4X(dev))
14847 intel_dp_init(dev, DP_B, PORT_B);
14848 }
14849
14850 /* Before G4X SDVOC doesn't have its own detect register */
14851
14852 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14853 DRM_DEBUG_KMS("probing SDVOC\n");
14854 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14855 }
14856
14857 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14858
14859 if (IS_G4X(dev)) {
14860 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14861 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14862 }
14863 if (IS_G4X(dev))
14864 intel_dp_init(dev, DP_C, PORT_C);
14865 }
14866
14867 if (IS_G4X(dev) &&
14868 (I915_READ(DP_D) & DP_DETECTED))
14869 intel_dp_init(dev, DP_D, PORT_D);
14870 } else if (IS_GEN2(dev))
14871 intel_dvo_init(dev);
14872
14873 if (SUPPORTS_TV(dev))
14874 intel_tv_init(dev);
14875
14876 intel_psr_init(dev);
14877
14878 for_each_intel_encoder(dev, encoder) {
14879 encoder->base.possible_crtcs = encoder->crtc_mask;
14880 encoder->base.possible_clones =
14881 intel_encoder_clones(encoder);
14882 }
14883
14884 intel_init_pch_refclk(dev);
14885
14886 drm_helper_move_panel_connectors_to_head(dev);
14887 }
14888
14889 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14890 {
14891 struct drm_device *dev = fb->dev;
14892 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14893
14894 drm_framebuffer_cleanup(fb);
14895 mutex_lock(&dev->struct_mutex);
14896 WARN_ON(!intel_fb->obj->framebuffer_references--);
14897 drm_gem_object_unreference(&intel_fb->obj->base);
14898 mutex_unlock(&dev->struct_mutex);
14899 kfree(intel_fb);
14900 }
14901
14902 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14903 struct drm_file *file,
14904 unsigned int *handle)
14905 {
14906 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14907 struct drm_i915_gem_object *obj = intel_fb->obj;
14908
14909 if (obj->userptr.mm) {
14910 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14911 return -EINVAL;
14912 }
14913
14914 return drm_gem_handle_create(file, &obj->base, handle);
14915 }
14916
14917 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14918 struct drm_file *file,
14919 unsigned flags, unsigned color,
14920 struct drm_clip_rect *clips,
14921 unsigned num_clips)
14922 {
14923 struct drm_device *dev = fb->dev;
14924 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14925 struct drm_i915_gem_object *obj = intel_fb->obj;
14926
14927 mutex_lock(&dev->struct_mutex);
14928 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14929 mutex_unlock(&dev->struct_mutex);
14930
14931 return 0;
14932 }
14933
14934 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14935 .destroy = intel_user_framebuffer_destroy,
14936 .create_handle = intel_user_framebuffer_create_handle,
14937 .dirty = intel_user_framebuffer_dirty,
14938 };
14939
14940 static
14941 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14942 uint32_t pixel_format)
14943 {
14944 u32 gen = INTEL_INFO(dev)->gen;
14945
14946 if (gen >= 9) {
14947 int cpp = drm_format_plane_cpp(pixel_format, 0);
14948
14949 /* "The stride in bytes must not exceed the of the size of 8K
14950 * pixels and 32K bytes."
14951 */
14952 return min(8192 * cpp, 32768);
14953 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14954 return 32*1024;
14955 } else if (gen >= 4) {
14956 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14957 return 16*1024;
14958 else
14959 return 32*1024;
14960 } else if (gen >= 3) {
14961 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14962 return 8*1024;
14963 else
14964 return 16*1024;
14965 } else {
14966 /* XXX DSPC is limited to 4k tiled */
14967 return 8*1024;
14968 }
14969 }
14970
14971 static int intel_framebuffer_init(struct drm_device *dev,
14972 struct intel_framebuffer *intel_fb,
14973 struct drm_mode_fb_cmd2 *mode_cmd,
14974 struct drm_i915_gem_object *obj)
14975 {
14976 struct drm_i915_private *dev_priv = to_i915(dev);
14977 unsigned int aligned_height;
14978 int ret;
14979 u32 pitch_limit, stride_alignment;
14980
14981 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14982
14983 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14984 /* Enforce that fb modifier and tiling mode match, but only for
14985 * X-tiled. This is needed for FBC. */
14986 if (!!(obj->tiling_mode == I915_TILING_X) !=
14987 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14988 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14989 return -EINVAL;
14990 }
14991 } else {
14992 if (obj->tiling_mode == I915_TILING_X)
14993 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14994 else if (obj->tiling_mode == I915_TILING_Y) {
14995 DRM_DEBUG("No Y tiling for legacy addfb\n");
14996 return -EINVAL;
14997 }
14998 }
14999
15000 /* Passed in modifier sanity checking. */
15001 switch (mode_cmd->modifier[0]) {
15002 case I915_FORMAT_MOD_Y_TILED:
15003 case I915_FORMAT_MOD_Yf_TILED:
15004 if (INTEL_INFO(dev)->gen < 9) {
15005 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15006 mode_cmd->modifier[0]);
15007 return -EINVAL;
15008 }
15009 case DRM_FORMAT_MOD_NONE:
15010 case I915_FORMAT_MOD_X_TILED:
15011 break;
15012 default:
15013 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15014 mode_cmd->modifier[0]);
15015 return -EINVAL;
15016 }
15017
15018 stride_alignment = intel_fb_stride_alignment(dev_priv,
15019 mode_cmd->modifier[0],
15020 mode_cmd->pixel_format);
15021 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15022 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15023 mode_cmd->pitches[0], stride_alignment);
15024 return -EINVAL;
15025 }
15026
15027 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15028 mode_cmd->pixel_format);
15029 if (mode_cmd->pitches[0] > pitch_limit) {
15030 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15031 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15032 "tiled" : "linear",
15033 mode_cmd->pitches[0], pitch_limit);
15034 return -EINVAL;
15035 }
15036
15037 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
15038 mode_cmd->pitches[0] != obj->stride) {
15039 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15040 mode_cmd->pitches[0], obj->stride);
15041 return -EINVAL;
15042 }
15043
15044 /* Reject formats not supported by any plane early. */
15045 switch (mode_cmd->pixel_format) {
15046 case DRM_FORMAT_C8:
15047 case DRM_FORMAT_RGB565:
15048 case DRM_FORMAT_XRGB8888:
15049 case DRM_FORMAT_ARGB8888:
15050 break;
15051 case DRM_FORMAT_XRGB1555:
15052 if (INTEL_INFO(dev)->gen > 3) {
15053 DRM_DEBUG("unsupported pixel format: %s\n",
15054 drm_get_format_name(mode_cmd->pixel_format));
15055 return -EINVAL;
15056 }
15057 break;
15058 case DRM_FORMAT_ABGR8888:
15059 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15060 INTEL_INFO(dev)->gen < 9) {
15061 DRM_DEBUG("unsupported pixel format: %s\n",
15062 drm_get_format_name(mode_cmd->pixel_format));
15063 return -EINVAL;
15064 }
15065 break;
15066 case DRM_FORMAT_XBGR8888:
15067 case DRM_FORMAT_XRGB2101010:
15068 case DRM_FORMAT_XBGR2101010:
15069 if (INTEL_INFO(dev)->gen < 4) {
15070 DRM_DEBUG("unsupported pixel format: %s\n",
15071 drm_get_format_name(mode_cmd->pixel_format));
15072 return -EINVAL;
15073 }
15074 break;
15075 case DRM_FORMAT_ABGR2101010:
15076 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15077 DRM_DEBUG("unsupported pixel format: %s\n",
15078 drm_get_format_name(mode_cmd->pixel_format));
15079 return -EINVAL;
15080 }
15081 break;
15082 case DRM_FORMAT_YUYV:
15083 case DRM_FORMAT_UYVY:
15084 case DRM_FORMAT_YVYU:
15085 case DRM_FORMAT_VYUY:
15086 if (INTEL_INFO(dev)->gen < 5) {
15087 DRM_DEBUG("unsupported pixel format: %s\n",
15088 drm_get_format_name(mode_cmd->pixel_format));
15089 return -EINVAL;
15090 }
15091 break;
15092 default:
15093 DRM_DEBUG("unsupported pixel format: %s\n",
15094 drm_get_format_name(mode_cmd->pixel_format));
15095 return -EINVAL;
15096 }
15097
15098 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15099 if (mode_cmd->offsets[0] != 0)
15100 return -EINVAL;
15101
15102 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
15103 mode_cmd->pixel_format,
15104 mode_cmd->modifier[0]);
15105 /* FIXME drm helper for size checks (especially planar formats)? */
15106 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
15107 return -EINVAL;
15108
15109 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15110 intel_fb->obj = obj;
15111
15112 intel_fill_fb_info(dev_priv, &intel_fb->base);
15113
15114 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15115 if (ret) {
15116 DRM_ERROR("framebuffer init failed %d\n", ret);
15117 return ret;
15118 }
15119
15120 intel_fb->obj->framebuffer_references++;
15121
15122 return 0;
15123 }
15124
15125 static struct drm_framebuffer *
15126 intel_user_framebuffer_create(struct drm_device *dev,
15127 struct drm_file *filp,
15128 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15129 {
15130 struct drm_framebuffer *fb;
15131 struct drm_i915_gem_object *obj;
15132 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15133
15134 obj = to_intel_bo(drm_gem_object_lookup(filp, mode_cmd.handles[0]));
15135 if (&obj->base == NULL)
15136 return ERR_PTR(-ENOENT);
15137
15138 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15139 if (IS_ERR(fb))
15140 drm_gem_object_unreference_unlocked(&obj->base);
15141
15142 return fb;
15143 }
15144
15145 #ifndef CONFIG_DRM_FBDEV_EMULATION
15146 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15147 {
15148 }
15149 #endif
15150
15151 static const struct drm_mode_config_funcs intel_mode_funcs = {
15152 .fb_create = intel_user_framebuffer_create,
15153 .output_poll_changed = intel_fbdev_output_poll_changed,
15154 .atomic_check = intel_atomic_check,
15155 .atomic_commit = intel_atomic_commit,
15156 .atomic_state_alloc = intel_atomic_state_alloc,
15157 .atomic_state_clear = intel_atomic_state_clear,
15158 };
15159
15160 /**
15161 * intel_init_display_hooks - initialize the display modesetting hooks
15162 * @dev_priv: device private
15163 */
15164 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15165 {
15166 if (INTEL_INFO(dev_priv)->gen >= 9) {
15167 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15168 dev_priv->display.get_initial_plane_config =
15169 skylake_get_initial_plane_config;
15170 dev_priv->display.crtc_compute_clock =
15171 haswell_crtc_compute_clock;
15172 dev_priv->display.crtc_enable = haswell_crtc_enable;
15173 dev_priv->display.crtc_disable = haswell_crtc_disable;
15174 } else if (HAS_DDI(dev_priv)) {
15175 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15176 dev_priv->display.get_initial_plane_config =
15177 ironlake_get_initial_plane_config;
15178 dev_priv->display.crtc_compute_clock =
15179 haswell_crtc_compute_clock;
15180 dev_priv->display.crtc_enable = haswell_crtc_enable;
15181 dev_priv->display.crtc_disable = haswell_crtc_disable;
15182 } else if (HAS_PCH_SPLIT(dev_priv)) {
15183 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15184 dev_priv->display.get_initial_plane_config =
15185 ironlake_get_initial_plane_config;
15186 dev_priv->display.crtc_compute_clock =
15187 ironlake_crtc_compute_clock;
15188 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15189 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15190 } else if (IS_CHERRYVIEW(dev_priv)) {
15191 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15192 dev_priv->display.get_initial_plane_config =
15193 i9xx_get_initial_plane_config;
15194 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15195 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15196 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15197 } else if (IS_VALLEYVIEW(dev_priv)) {
15198 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15199 dev_priv->display.get_initial_plane_config =
15200 i9xx_get_initial_plane_config;
15201 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15202 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15203 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15204 } else if (IS_G4X(dev_priv)) {
15205 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15206 dev_priv->display.get_initial_plane_config =
15207 i9xx_get_initial_plane_config;
15208 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15209 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15210 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15211 } else if (IS_PINEVIEW(dev_priv)) {
15212 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15213 dev_priv->display.get_initial_plane_config =
15214 i9xx_get_initial_plane_config;
15215 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15216 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15217 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15218 } else if (!IS_GEN2(dev_priv)) {
15219 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15220 dev_priv->display.get_initial_plane_config =
15221 i9xx_get_initial_plane_config;
15222 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15223 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15224 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15225 } else {
15226 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15227 dev_priv->display.get_initial_plane_config =
15228 i9xx_get_initial_plane_config;
15229 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15230 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15231 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15232 }
15233
15234 /* Returns the core display clock speed */
15235 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15236 dev_priv->display.get_display_clock_speed =
15237 skylake_get_display_clock_speed;
15238 else if (IS_BROXTON(dev_priv))
15239 dev_priv->display.get_display_clock_speed =
15240 broxton_get_display_clock_speed;
15241 else if (IS_BROADWELL(dev_priv))
15242 dev_priv->display.get_display_clock_speed =
15243 broadwell_get_display_clock_speed;
15244 else if (IS_HASWELL(dev_priv))
15245 dev_priv->display.get_display_clock_speed =
15246 haswell_get_display_clock_speed;
15247 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15248 dev_priv->display.get_display_clock_speed =
15249 valleyview_get_display_clock_speed;
15250 else if (IS_GEN5(dev_priv))
15251 dev_priv->display.get_display_clock_speed =
15252 ilk_get_display_clock_speed;
15253 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15254 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15255 dev_priv->display.get_display_clock_speed =
15256 i945_get_display_clock_speed;
15257 else if (IS_GM45(dev_priv))
15258 dev_priv->display.get_display_clock_speed =
15259 gm45_get_display_clock_speed;
15260 else if (IS_CRESTLINE(dev_priv))
15261 dev_priv->display.get_display_clock_speed =
15262 i965gm_get_display_clock_speed;
15263 else if (IS_PINEVIEW(dev_priv))
15264 dev_priv->display.get_display_clock_speed =
15265 pnv_get_display_clock_speed;
15266 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15267 dev_priv->display.get_display_clock_speed =
15268 g33_get_display_clock_speed;
15269 else if (IS_I915G(dev_priv))
15270 dev_priv->display.get_display_clock_speed =
15271 i915_get_display_clock_speed;
15272 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
15273 dev_priv->display.get_display_clock_speed =
15274 i9xx_misc_get_display_clock_speed;
15275 else if (IS_I915GM(dev_priv))
15276 dev_priv->display.get_display_clock_speed =
15277 i915gm_get_display_clock_speed;
15278 else if (IS_I865G(dev_priv))
15279 dev_priv->display.get_display_clock_speed =
15280 i865_get_display_clock_speed;
15281 else if (IS_I85X(dev_priv))
15282 dev_priv->display.get_display_clock_speed =
15283 i85x_get_display_clock_speed;
15284 else { /* 830 */
15285 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
15286 dev_priv->display.get_display_clock_speed =
15287 i830_get_display_clock_speed;
15288 }
15289
15290 if (IS_GEN5(dev_priv)) {
15291 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15292 } else if (IS_GEN6(dev_priv)) {
15293 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15294 } else if (IS_IVYBRIDGE(dev_priv)) {
15295 /* FIXME: detect B0+ stepping and use auto training */
15296 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15297 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
15298 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15299 }
15300
15301 if (IS_BROADWELL(dev_priv)) {
15302 dev_priv->display.modeset_commit_cdclk =
15303 broadwell_modeset_commit_cdclk;
15304 dev_priv->display.modeset_calc_cdclk =
15305 broadwell_modeset_calc_cdclk;
15306 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15307 dev_priv->display.modeset_commit_cdclk =
15308 valleyview_modeset_commit_cdclk;
15309 dev_priv->display.modeset_calc_cdclk =
15310 valleyview_modeset_calc_cdclk;
15311 } else if (IS_BROXTON(dev_priv)) {
15312 dev_priv->display.modeset_commit_cdclk =
15313 bxt_modeset_commit_cdclk;
15314 dev_priv->display.modeset_calc_cdclk =
15315 bxt_modeset_calc_cdclk;
15316 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
15317 dev_priv->display.modeset_commit_cdclk =
15318 skl_modeset_commit_cdclk;
15319 dev_priv->display.modeset_calc_cdclk =
15320 skl_modeset_calc_cdclk;
15321 }
15322
15323 switch (INTEL_INFO(dev_priv)->gen) {
15324 case 2:
15325 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15326 break;
15327
15328 case 3:
15329 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15330 break;
15331
15332 case 4:
15333 case 5:
15334 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15335 break;
15336
15337 case 6:
15338 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15339 break;
15340 case 7:
15341 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15342 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15343 break;
15344 case 9:
15345 /* Drop through - unsupported since execlist only. */
15346 default:
15347 /* Default just returns -ENODEV to indicate unsupported */
15348 dev_priv->display.queue_flip = intel_default_queue_flip;
15349 }
15350 }
15351
15352 /*
15353 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15354 * resume, or other times. This quirk makes sure that's the case for
15355 * affected systems.
15356 */
15357 static void quirk_pipea_force(struct drm_device *dev)
15358 {
15359 struct drm_i915_private *dev_priv = dev->dev_private;
15360
15361 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15362 DRM_INFO("applying pipe a force quirk\n");
15363 }
15364
15365 static void quirk_pipeb_force(struct drm_device *dev)
15366 {
15367 struct drm_i915_private *dev_priv = dev->dev_private;
15368
15369 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15370 DRM_INFO("applying pipe b force quirk\n");
15371 }
15372
15373 /*
15374 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15375 */
15376 static void quirk_ssc_force_disable(struct drm_device *dev)
15377 {
15378 struct drm_i915_private *dev_priv = dev->dev_private;
15379 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15380 DRM_INFO("applying lvds SSC disable quirk\n");
15381 }
15382
15383 /*
15384 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15385 * brightness value
15386 */
15387 static void quirk_invert_brightness(struct drm_device *dev)
15388 {
15389 struct drm_i915_private *dev_priv = dev->dev_private;
15390 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15391 DRM_INFO("applying inverted panel brightness quirk\n");
15392 }
15393
15394 /* Some VBT's incorrectly indicate no backlight is present */
15395 static void quirk_backlight_present(struct drm_device *dev)
15396 {
15397 struct drm_i915_private *dev_priv = dev->dev_private;
15398 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15399 DRM_INFO("applying backlight present quirk\n");
15400 }
15401
15402 struct intel_quirk {
15403 int device;
15404 int subsystem_vendor;
15405 int subsystem_device;
15406 void (*hook)(struct drm_device *dev);
15407 };
15408
15409 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15410 struct intel_dmi_quirk {
15411 void (*hook)(struct drm_device *dev);
15412 const struct dmi_system_id (*dmi_id_list)[];
15413 };
15414
15415 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15416 {
15417 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15418 return 1;
15419 }
15420
15421 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15422 {
15423 .dmi_id_list = &(const struct dmi_system_id[]) {
15424 {
15425 .callback = intel_dmi_reverse_brightness,
15426 .ident = "NCR Corporation",
15427 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15428 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15429 },
15430 },
15431 { } /* terminating entry */
15432 },
15433 .hook = quirk_invert_brightness,
15434 },
15435 };
15436
15437 static struct intel_quirk intel_quirks[] = {
15438 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15439 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15440
15441 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15442 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15443
15444 /* 830 needs to leave pipe A & dpll A up */
15445 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15446
15447 /* 830 needs to leave pipe B & dpll B up */
15448 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15449
15450 /* Lenovo U160 cannot use SSC on LVDS */
15451 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15452
15453 /* Sony Vaio Y cannot use SSC on LVDS */
15454 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15455
15456 /* Acer Aspire 5734Z must invert backlight brightness */
15457 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15458
15459 /* Acer/eMachines G725 */
15460 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15461
15462 /* Acer/eMachines e725 */
15463 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15464
15465 /* Acer/Packard Bell NCL20 */
15466 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15467
15468 /* Acer Aspire 4736Z */
15469 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15470
15471 /* Acer Aspire 5336 */
15472 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15473
15474 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15475 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15476
15477 /* Acer C720 Chromebook (Core i3 4005U) */
15478 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15479
15480 /* Apple Macbook 2,1 (Core 2 T7400) */
15481 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15482
15483 /* Apple Macbook 4,1 */
15484 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15485
15486 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15487 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15488
15489 /* HP Chromebook 14 (Celeron 2955U) */
15490 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15491
15492 /* Dell Chromebook 11 */
15493 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15494
15495 /* Dell Chromebook 11 (2015 version) */
15496 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15497 };
15498
15499 static void intel_init_quirks(struct drm_device *dev)
15500 {
15501 struct pci_dev *d = dev->pdev;
15502 int i;
15503
15504 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15505 struct intel_quirk *q = &intel_quirks[i];
15506
15507 if (d->device == q->device &&
15508 (d->subsystem_vendor == q->subsystem_vendor ||
15509 q->subsystem_vendor == PCI_ANY_ID) &&
15510 (d->subsystem_device == q->subsystem_device ||
15511 q->subsystem_device == PCI_ANY_ID))
15512 q->hook(dev);
15513 }
15514 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15515 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15516 intel_dmi_quirks[i].hook(dev);
15517 }
15518 }
15519
15520 /* Disable the VGA plane that we never use */
15521 static void i915_disable_vga(struct drm_device *dev)
15522 {
15523 struct drm_i915_private *dev_priv = dev->dev_private;
15524 u8 sr1;
15525 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15526
15527 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15528 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15529 outb(SR01, VGA_SR_INDEX);
15530 sr1 = inb(VGA_SR_DATA);
15531 outb(sr1 | 1<<5, VGA_SR_DATA);
15532 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15533 udelay(300);
15534
15535 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15536 POSTING_READ(vga_reg);
15537 }
15538
15539 void intel_modeset_init_hw(struct drm_device *dev)
15540 {
15541 struct drm_i915_private *dev_priv = dev->dev_private;
15542
15543 intel_update_cdclk(dev);
15544
15545 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15546
15547 intel_init_clock_gating(dev);
15548 intel_enable_gt_powersave(dev_priv);
15549 }
15550
15551 /*
15552 * Calculate what we think the watermarks should be for the state we've read
15553 * out of the hardware and then immediately program those watermarks so that
15554 * we ensure the hardware settings match our internal state.
15555 *
15556 * We can calculate what we think WM's should be by creating a duplicate of the
15557 * current state (which was constructed during hardware readout) and running it
15558 * through the atomic check code to calculate new watermark values in the
15559 * state object.
15560 */
15561 static void sanitize_watermarks(struct drm_device *dev)
15562 {
15563 struct drm_i915_private *dev_priv = to_i915(dev);
15564 struct drm_atomic_state *state;
15565 struct drm_crtc *crtc;
15566 struct drm_crtc_state *cstate;
15567 struct drm_modeset_acquire_ctx ctx;
15568 int ret;
15569 int i;
15570
15571 /* Only supported on platforms that use atomic watermark design */
15572 if (!dev_priv->display.optimize_watermarks)
15573 return;
15574
15575 /*
15576 * We need to hold connection_mutex before calling duplicate_state so
15577 * that the connector loop is protected.
15578 */
15579 drm_modeset_acquire_init(&ctx, 0);
15580 retry:
15581 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15582 if (ret == -EDEADLK) {
15583 drm_modeset_backoff(&ctx);
15584 goto retry;
15585 } else if (WARN_ON(ret)) {
15586 goto fail;
15587 }
15588
15589 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15590 if (WARN_ON(IS_ERR(state)))
15591 goto fail;
15592
15593 /*
15594 * Hardware readout is the only time we don't want to calculate
15595 * intermediate watermarks (since we don't trust the current
15596 * watermarks).
15597 */
15598 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15599
15600 ret = intel_atomic_check(dev, state);
15601 if (ret) {
15602 /*
15603 * If we fail here, it means that the hardware appears to be
15604 * programmed in a way that shouldn't be possible, given our
15605 * understanding of watermark requirements. This might mean a
15606 * mistake in the hardware readout code or a mistake in the
15607 * watermark calculations for a given platform. Raise a WARN
15608 * so that this is noticeable.
15609 *
15610 * If this actually happens, we'll have to just leave the
15611 * BIOS-programmed watermarks untouched and hope for the best.
15612 */
15613 WARN(true, "Could not determine valid watermarks for inherited state\n");
15614 goto fail;
15615 }
15616
15617 /* Write calculated watermark values back */
15618 for_each_crtc_in_state(state, crtc, cstate, i) {
15619 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15620
15621 cs->wm.need_postvbl_update = true;
15622 dev_priv->display.optimize_watermarks(cs);
15623 }
15624
15625 drm_atomic_state_free(state);
15626 fail:
15627 drm_modeset_drop_locks(&ctx);
15628 drm_modeset_acquire_fini(&ctx);
15629 }
15630
15631 void intel_modeset_init(struct drm_device *dev)
15632 {
15633 struct drm_i915_private *dev_priv = to_i915(dev);
15634 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15635 int sprite, ret;
15636 enum pipe pipe;
15637 struct intel_crtc *crtc;
15638
15639 drm_mode_config_init(dev);
15640
15641 dev->mode_config.min_width = 0;
15642 dev->mode_config.min_height = 0;
15643
15644 dev->mode_config.preferred_depth = 24;
15645 dev->mode_config.prefer_shadow = 1;
15646
15647 dev->mode_config.allow_fb_modifiers = true;
15648
15649 dev->mode_config.funcs = &intel_mode_funcs;
15650
15651 intel_init_quirks(dev);
15652
15653 intel_init_pm(dev);
15654
15655 if (INTEL_INFO(dev)->num_pipes == 0)
15656 return;
15657
15658 /*
15659 * There may be no VBT; and if the BIOS enabled SSC we can
15660 * just keep using it to avoid unnecessary flicker. Whereas if the
15661 * BIOS isn't using it, don't assume it will work even if the VBT
15662 * indicates as much.
15663 */
15664 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15665 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15666 DREF_SSC1_ENABLE);
15667
15668 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15669 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15670 bios_lvds_use_ssc ? "en" : "dis",
15671 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15672 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15673 }
15674 }
15675
15676 if (IS_GEN2(dev)) {
15677 dev->mode_config.max_width = 2048;
15678 dev->mode_config.max_height = 2048;
15679 } else if (IS_GEN3(dev)) {
15680 dev->mode_config.max_width = 4096;
15681 dev->mode_config.max_height = 4096;
15682 } else {
15683 dev->mode_config.max_width = 8192;
15684 dev->mode_config.max_height = 8192;
15685 }
15686
15687 if (IS_845G(dev) || IS_I865G(dev)) {
15688 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15689 dev->mode_config.cursor_height = 1023;
15690 } else if (IS_GEN2(dev)) {
15691 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15692 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15693 } else {
15694 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15695 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15696 }
15697
15698 dev->mode_config.fb_base = ggtt->mappable_base;
15699
15700 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15701 INTEL_INFO(dev)->num_pipes,
15702 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15703
15704 for_each_pipe(dev_priv, pipe) {
15705 intel_crtc_init(dev, pipe);
15706 for_each_sprite(dev_priv, pipe, sprite) {
15707 ret = intel_plane_init(dev, pipe, sprite);
15708 if (ret)
15709 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15710 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15711 }
15712 }
15713
15714 intel_update_czclk(dev_priv);
15715 intel_update_cdclk(dev);
15716
15717 intel_shared_dpll_init(dev);
15718
15719 if (dev_priv->max_cdclk_freq == 0)
15720 intel_update_max_cdclk(dev);
15721
15722 /* Just disable it once at startup */
15723 i915_disable_vga(dev);
15724 intel_setup_outputs(dev);
15725
15726 drm_modeset_lock_all(dev);
15727 intel_modeset_setup_hw_state(dev);
15728 drm_modeset_unlock_all(dev);
15729
15730 for_each_intel_crtc(dev, crtc) {
15731 struct intel_initial_plane_config plane_config = {};
15732
15733 if (!crtc->active)
15734 continue;
15735
15736 /*
15737 * Note that reserving the BIOS fb up front prevents us
15738 * from stuffing other stolen allocations like the ring
15739 * on top. This prevents some ugliness at boot time, and
15740 * can even allow for smooth boot transitions if the BIOS
15741 * fb is large enough for the active pipe configuration.
15742 */
15743 dev_priv->display.get_initial_plane_config(crtc,
15744 &plane_config);
15745
15746 /*
15747 * If the fb is shared between multiple heads, we'll
15748 * just get the first one.
15749 */
15750 intel_find_initial_plane_obj(crtc, &plane_config);
15751 }
15752
15753 /*
15754 * Make sure hardware watermarks really match the state we read out.
15755 * Note that we need to do this after reconstructing the BIOS fb's
15756 * since the watermark calculation done here will use pstate->fb.
15757 */
15758 sanitize_watermarks(dev);
15759 }
15760
15761 static void intel_enable_pipe_a(struct drm_device *dev)
15762 {
15763 struct intel_connector *connector;
15764 struct drm_connector *crt = NULL;
15765 struct intel_load_detect_pipe load_detect_temp;
15766 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15767
15768 /* We can't just switch on the pipe A, we need to set things up with a
15769 * proper mode and output configuration. As a gross hack, enable pipe A
15770 * by enabling the load detect pipe once. */
15771 for_each_intel_connector(dev, connector) {
15772 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15773 crt = &connector->base;
15774 break;
15775 }
15776 }
15777
15778 if (!crt)
15779 return;
15780
15781 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15782 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15783 }
15784
15785 static bool
15786 intel_check_plane_mapping(struct intel_crtc *crtc)
15787 {
15788 struct drm_device *dev = crtc->base.dev;
15789 struct drm_i915_private *dev_priv = dev->dev_private;
15790 u32 val;
15791
15792 if (INTEL_INFO(dev)->num_pipes == 1)
15793 return true;
15794
15795 val = I915_READ(DSPCNTR(!crtc->plane));
15796
15797 if ((val & DISPLAY_PLANE_ENABLE) &&
15798 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15799 return false;
15800
15801 return true;
15802 }
15803
15804 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15805 {
15806 struct drm_device *dev = crtc->base.dev;
15807 struct intel_encoder *encoder;
15808
15809 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15810 return true;
15811
15812 return false;
15813 }
15814
15815 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15816 {
15817 struct drm_device *dev = encoder->base.dev;
15818 struct intel_connector *connector;
15819
15820 for_each_connector_on_encoder(dev, &encoder->base, connector)
15821 return true;
15822
15823 return false;
15824 }
15825
15826 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15827 {
15828 struct drm_device *dev = crtc->base.dev;
15829 struct drm_i915_private *dev_priv = dev->dev_private;
15830 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15831
15832 /* Clear any frame start delays used for debugging left by the BIOS */
15833 if (!transcoder_is_dsi(cpu_transcoder)) {
15834 i915_reg_t reg = PIPECONF(cpu_transcoder);
15835
15836 I915_WRITE(reg,
15837 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15838 }
15839
15840 /* restore vblank interrupts to correct state */
15841 drm_crtc_vblank_reset(&crtc->base);
15842 if (crtc->active) {
15843 struct intel_plane *plane;
15844
15845 drm_crtc_vblank_on(&crtc->base);
15846
15847 /* Disable everything but the primary plane */
15848 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15849 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15850 continue;
15851
15852 plane->disable_plane(&plane->base, &crtc->base);
15853 }
15854 }
15855
15856 /* We need to sanitize the plane -> pipe mapping first because this will
15857 * disable the crtc (and hence change the state) if it is wrong. Note
15858 * that gen4+ has a fixed plane -> pipe mapping. */
15859 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15860 bool plane;
15861
15862 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15863 crtc->base.base.id, crtc->base.name);
15864
15865 /* Pipe has the wrong plane attached and the plane is active.
15866 * Temporarily change the plane mapping and disable everything
15867 * ... */
15868 plane = crtc->plane;
15869 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15870 crtc->plane = !plane;
15871 intel_crtc_disable_noatomic(&crtc->base);
15872 crtc->plane = plane;
15873 }
15874
15875 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15876 crtc->pipe == PIPE_A && !crtc->active) {
15877 /* BIOS forgot to enable pipe A, this mostly happens after
15878 * resume. Force-enable the pipe to fix this, the update_dpms
15879 * call below we restore the pipe to the right state, but leave
15880 * the required bits on. */
15881 intel_enable_pipe_a(dev);
15882 }
15883
15884 /* Adjust the state of the output pipe according to whether we
15885 * have active connectors/encoders. */
15886 if (crtc->active && !intel_crtc_has_encoders(crtc))
15887 intel_crtc_disable_noatomic(&crtc->base);
15888
15889 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15890 /*
15891 * We start out with underrun reporting disabled to avoid races.
15892 * For correct bookkeeping mark this on active crtcs.
15893 *
15894 * Also on gmch platforms we dont have any hardware bits to
15895 * disable the underrun reporting. Which means we need to start
15896 * out with underrun reporting disabled also on inactive pipes,
15897 * since otherwise we'll complain about the garbage we read when
15898 * e.g. coming up after runtime pm.
15899 *
15900 * No protection against concurrent access is required - at
15901 * worst a fifo underrun happens which also sets this to false.
15902 */
15903 crtc->cpu_fifo_underrun_disabled = true;
15904 crtc->pch_fifo_underrun_disabled = true;
15905 }
15906 }
15907
15908 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15909 {
15910 struct intel_connector *connector;
15911 struct drm_device *dev = encoder->base.dev;
15912
15913 /* We need to check both for a crtc link (meaning that the
15914 * encoder is active and trying to read from a pipe) and the
15915 * pipe itself being active. */
15916 bool has_active_crtc = encoder->base.crtc &&
15917 to_intel_crtc(encoder->base.crtc)->active;
15918
15919 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15920 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15921 encoder->base.base.id,
15922 encoder->base.name);
15923
15924 /* Connector is active, but has no active pipe. This is
15925 * fallout from our resume register restoring. Disable
15926 * the encoder manually again. */
15927 if (encoder->base.crtc) {
15928 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15929 encoder->base.base.id,
15930 encoder->base.name);
15931 encoder->disable(encoder);
15932 if (encoder->post_disable)
15933 encoder->post_disable(encoder);
15934 }
15935 encoder->base.crtc = NULL;
15936
15937 /* Inconsistent output/port/pipe state happens presumably due to
15938 * a bug in one of the get_hw_state functions. Or someplace else
15939 * in our code, like the register restore mess on resume. Clamp
15940 * things to off as a safer default. */
15941 for_each_intel_connector(dev, connector) {
15942 if (connector->encoder != encoder)
15943 continue;
15944 connector->base.dpms = DRM_MODE_DPMS_OFF;
15945 connector->base.encoder = NULL;
15946 }
15947 }
15948 /* Enabled encoders without active connectors will be fixed in
15949 * the crtc fixup. */
15950 }
15951
15952 void i915_redisable_vga_power_on(struct drm_device *dev)
15953 {
15954 struct drm_i915_private *dev_priv = dev->dev_private;
15955 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15956
15957 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15958 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15959 i915_disable_vga(dev);
15960 }
15961 }
15962
15963 void i915_redisable_vga(struct drm_device *dev)
15964 {
15965 struct drm_i915_private *dev_priv = dev->dev_private;
15966
15967 /* This function can be called both from intel_modeset_setup_hw_state or
15968 * at a very early point in our resume sequence, where the power well
15969 * structures are not yet restored. Since this function is at a very
15970 * paranoid "someone might have enabled VGA while we were not looking"
15971 * level, just check if the power well is enabled instead of trying to
15972 * follow the "don't touch the power well if we don't need it" policy
15973 * the rest of the driver uses. */
15974 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15975 return;
15976
15977 i915_redisable_vga_power_on(dev);
15978
15979 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15980 }
15981
15982 static bool primary_get_hw_state(struct intel_plane *plane)
15983 {
15984 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15985
15986 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15987 }
15988
15989 /* FIXME read out full plane state for all planes */
15990 static void readout_plane_state(struct intel_crtc *crtc)
15991 {
15992 struct drm_plane *primary = crtc->base.primary;
15993 struct intel_plane_state *plane_state =
15994 to_intel_plane_state(primary->state);
15995
15996 plane_state->visible = crtc->active &&
15997 primary_get_hw_state(to_intel_plane(primary));
15998
15999 if (plane_state->visible)
16000 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16001 }
16002
16003 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16004 {
16005 struct drm_i915_private *dev_priv = dev->dev_private;
16006 enum pipe pipe;
16007 struct intel_crtc *crtc;
16008 struct intel_encoder *encoder;
16009 struct intel_connector *connector;
16010 int i;
16011
16012 dev_priv->active_crtcs = 0;
16013
16014 for_each_intel_crtc(dev, crtc) {
16015 struct intel_crtc_state *crtc_state = crtc->config;
16016 int pixclk = 0;
16017
16018 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16019 memset(crtc_state, 0, sizeof(*crtc_state));
16020 crtc_state->base.crtc = &crtc->base;
16021
16022 crtc_state->base.active = crtc_state->base.enable =
16023 dev_priv->display.get_pipe_config(crtc, crtc_state);
16024
16025 crtc->base.enabled = crtc_state->base.enable;
16026 crtc->active = crtc_state->base.active;
16027
16028 if (crtc_state->base.active) {
16029 dev_priv->active_crtcs |= 1 << crtc->pipe;
16030
16031 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16032 pixclk = ilk_pipe_pixel_rate(crtc_state);
16033 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16034 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
16035 else
16036 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16037
16038 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16039 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
16040 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16041 }
16042
16043 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16044
16045 readout_plane_state(crtc);
16046
16047 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16048 crtc->base.base.id, crtc->base.name,
16049 crtc->active ? "enabled" : "disabled");
16050 }
16051
16052 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16053 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16054
16055 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16056 &pll->config.hw_state);
16057 pll->config.crtc_mask = 0;
16058 for_each_intel_crtc(dev, crtc) {
16059 if (crtc->active && crtc->config->shared_dpll == pll)
16060 pll->config.crtc_mask |= 1 << crtc->pipe;
16061 }
16062 pll->active_mask = pll->config.crtc_mask;
16063
16064 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16065 pll->name, pll->config.crtc_mask, pll->on);
16066 }
16067
16068 for_each_intel_encoder(dev, encoder) {
16069 pipe = 0;
16070
16071 if (encoder->get_hw_state(encoder, &pipe)) {
16072 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16073 encoder->base.crtc = &crtc->base;
16074 encoder->get_config(encoder, crtc->config);
16075 } else {
16076 encoder->base.crtc = NULL;
16077 }
16078
16079 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16080 encoder->base.base.id,
16081 encoder->base.name,
16082 encoder->base.crtc ? "enabled" : "disabled",
16083 pipe_name(pipe));
16084 }
16085
16086 for_each_intel_connector(dev, connector) {
16087 if (connector->get_hw_state(connector)) {
16088 connector->base.dpms = DRM_MODE_DPMS_ON;
16089
16090 encoder = connector->encoder;
16091 connector->base.encoder = &encoder->base;
16092
16093 if (encoder->base.crtc &&
16094 encoder->base.crtc->state->active) {
16095 /*
16096 * This has to be done during hardware readout
16097 * because anything calling .crtc_disable may
16098 * rely on the connector_mask being accurate.
16099 */
16100 encoder->base.crtc->state->connector_mask |=
16101 1 << drm_connector_index(&connector->base);
16102 encoder->base.crtc->state->encoder_mask |=
16103 1 << drm_encoder_index(&encoder->base);
16104 }
16105
16106 } else {
16107 connector->base.dpms = DRM_MODE_DPMS_OFF;
16108 connector->base.encoder = NULL;
16109 }
16110 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16111 connector->base.base.id,
16112 connector->base.name,
16113 connector->base.encoder ? "enabled" : "disabled");
16114 }
16115
16116 for_each_intel_crtc(dev, crtc) {
16117 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16118
16119 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16120 if (crtc->base.state->active) {
16121 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16122 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16123 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16124
16125 /*
16126 * The initial mode needs to be set in order to keep
16127 * the atomic core happy. It wants a valid mode if the
16128 * crtc's enabled, so we do the above call.
16129 *
16130 * At this point some state updated by the connectors
16131 * in their ->detect() callback has not run yet, so
16132 * no recalculation can be done yet.
16133 *
16134 * Even if we could do a recalculation and modeset
16135 * right now it would cause a double modeset if
16136 * fbdev or userspace chooses a different initial mode.
16137 *
16138 * If that happens, someone indicated they wanted a
16139 * mode change, which means it's safe to do a full
16140 * recalculation.
16141 */
16142 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16143
16144 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16145 update_scanline_offset(crtc);
16146 }
16147
16148 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16149 }
16150 }
16151
16152 /* Scan out the current hw modeset state,
16153 * and sanitizes it to the current state
16154 */
16155 static void
16156 intel_modeset_setup_hw_state(struct drm_device *dev)
16157 {
16158 struct drm_i915_private *dev_priv = dev->dev_private;
16159 enum pipe pipe;
16160 struct intel_crtc *crtc;
16161 struct intel_encoder *encoder;
16162 int i;
16163
16164 intel_modeset_readout_hw_state(dev);
16165
16166 /* HW state is read out, now we need to sanitize this mess. */
16167 for_each_intel_encoder(dev, encoder) {
16168 intel_sanitize_encoder(encoder);
16169 }
16170
16171 for_each_pipe(dev_priv, pipe) {
16172 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16173 intel_sanitize_crtc(crtc);
16174 intel_dump_pipe_config(crtc, crtc->config,
16175 "[setup_hw_state]");
16176 }
16177
16178 intel_modeset_update_connector_atomic_state(dev);
16179
16180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16181 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16182
16183 if (!pll->on || pll->active_mask)
16184 continue;
16185
16186 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16187
16188 pll->funcs.disable(dev_priv, pll);
16189 pll->on = false;
16190 }
16191
16192 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16193 vlv_wm_get_hw_state(dev);
16194 else if (IS_GEN9(dev))
16195 skl_wm_get_hw_state(dev);
16196 else if (HAS_PCH_SPLIT(dev))
16197 ilk_wm_get_hw_state(dev);
16198
16199 for_each_intel_crtc(dev, crtc) {
16200 unsigned long put_domains;
16201
16202 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16203 if (WARN_ON(put_domains))
16204 modeset_put_power_domains(dev_priv, put_domains);
16205 }
16206 intel_display_set_init_power(dev_priv, false);
16207
16208 intel_fbc_init_pipe_state(dev_priv);
16209 }
16210
16211 void intel_display_resume(struct drm_device *dev)
16212 {
16213 struct drm_i915_private *dev_priv = to_i915(dev);
16214 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16215 struct drm_modeset_acquire_ctx ctx;
16216 int ret;
16217 bool setup = false;
16218
16219 dev_priv->modeset_restore_state = NULL;
16220
16221 /*
16222 * This is a cludge because with real atomic modeset mode_config.mutex
16223 * won't be taken. Unfortunately some probed state like
16224 * audio_codec_enable is still protected by mode_config.mutex, so lock
16225 * it here for now.
16226 */
16227 mutex_lock(&dev->mode_config.mutex);
16228 drm_modeset_acquire_init(&ctx, 0);
16229
16230 retry:
16231 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16232
16233 if (ret == 0 && !setup) {
16234 setup = true;
16235
16236 intel_modeset_setup_hw_state(dev);
16237 i915_redisable_vga(dev);
16238 }
16239
16240 if (ret == 0 && state) {
16241 struct drm_crtc_state *crtc_state;
16242 struct drm_crtc *crtc;
16243 int i;
16244
16245 state->acquire_ctx = &ctx;
16246
16247 /* ignore any reset values/BIOS leftovers in the WM registers */
16248 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16249
16250 for_each_crtc_in_state(state, crtc, crtc_state, i) {
16251 /*
16252 * Force recalculation even if we restore
16253 * current state. With fast modeset this may not result
16254 * in a modeset when the state is compatible.
16255 */
16256 crtc_state->mode_changed = true;
16257 }
16258
16259 ret = drm_atomic_commit(state);
16260 }
16261
16262 if (ret == -EDEADLK) {
16263 drm_modeset_backoff(&ctx);
16264 goto retry;
16265 }
16266
16267 drm_modeset_drop_locks(&ctx);
16268 drm_modeset_acquire_fini(&ctx);
16269 mutex_unlock(&dev->mode_config.mutex);
16270
16271 if (ret) {
16272 DRM_ERROR("Restoring old state failed with %i\n", ret);
16273 drm_atomic_state_free(state);
16274 }
16275 }
16276
16277 void intel_modeset_gem_init(struct drm_device *dev)
16278 {
16279 struct drm_i915_private *dev_priv = to_i915(dev);
16280 struct drm_crtc *c;
16281 struct drm_i915_gem_object *obj;
16282 int ret;
16283
16284 intel_init_gt_powersave(dev_priv);
16285
16286 intel_modeset_init_hw(dev);
16287
16288 intel_setup_overlay(dev_priv);
16289
16290 /*
16291 * Make sure any fbs we allocated at startup are properly
16292 * pinned & fenced. When we do the allocation it's too early
16293 * for this.
16294 */
16295 for_each_crtc(dev, c) {
16296 obj = intel_fb_obj(c->primary->fb);
16297 if (obj == NULL)
16298 continue;
16299
16300 mutex_lock(&dev->struct_mutex);
16301 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
16302 c->primary->state->rotation);
16303 mutex_unlock(&dev->struct_mutex);
16304 if (ret) {
16305 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16306 to_intel_crtc(c)->pipe);
16307 drm_framebuffer_unreference(c->primary->fb);
16308 c->primary->fb = NULL;
16309 c->primary->crtc = c->primary->state->crtc = NULL;
16310 update_state_fb(c->primary);
16311 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16312 }
16313 }
16314 }
16315
16316 int intel_connector_register(struct drm_connector *connector)
16317 {
16318 struct intel_connector *intel_connector = to_intel_connector(connector);
16319 int ret;
16320
16321 ret = intel_backlight_device_register(intel_connector);
16322 if (ret)
16323 goto err;
16324
16325 return 0;
16326
16327 err:
16328 return ret;
16329 }
16330
16331 void intel_connector_unregister(struct drm_connector *connector)
16332 {
16333 struct intel_connector *intel_connector = to_intel_connector(connector);
16334
16335 intel_backlight_device_unregister(intel_connector);
16336 intel_panel_destroy_backlight(connector);
16337 }
16338
16339 void intel_modeset_cleanup(struct drm_device *dev)
16340 {
16341 struct drm_i915_private *dev_priv = dev->dev_private;
16342
16343 intel_disable_gt_powersave(dev_priv);
16344
16345 /*
16346 * Interrupts and polling as the first thing to avoid creating havoc.
16347 * Too much stuff here (turning of connectors, ...) would
16348 * experience fancy races otherwise.
16349 */
16350 intel_irq_uninstall(dev_priv);
16351
16352 /*
16353 * Due to the hpd irq storm handling the hotplug work can re-arm the
16354 * poll handlers. Hence disable polling after hpd handling is shut down.
16355 */
16356 drm_kms_helper_poll_fini(dev);
16357
16358 intel_unregister_dsm_handler();
16359
16360 intel_fbc_global_disable(dev_priv);
16361
16362 /* flush any delayed tasks or pending work */
16363 flush_scheduled_work();
16364
16365 drm_mode_config_cleanup(dev);
16366
16367 intel_cleanup_overlay(dev_priv);
16368
16369 intel_cleanup_gt_powersave(dev_priv);
16370
16371 intel_teardown_gmbus(dev);
16372 }
16373
16374 void intel_connector_attach_encoder(struct intel_connector *connector,
16375 struct intel_encoder *encoder)
16376 {
16377 connector->encoder = encoder;
16378 drm_mode_connector_attach_encoder(&connector->base,
16379 &encoder->base);
16380 }
16381
16382 /*
16383 * set vga decode state - true == enable VGA decode
16384 */
16385 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16386 {
16387 struct drm_i915_private *dev_priv = dev->dev_private;
16388 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16389 u16 gmch_ctrl;
16390
16391 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16392 DRM_ERROR("failed to read control word\n");
16393 return -EIO;
16394 }
16395
16396 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16397 return 0;
16398
16399 if (state)
16400 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16401 else
16402 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16403
16404 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16405 DRM_ERROR("failed to write control word\n");
16406 return -EIO;
16407 }
16408
16409 return 0;
16410 }
16411
16412 struct intel_display_error_state {
16413
16414 u32 power_well_driver;
16415
16416 int num_transcoders;
16417
16418 struct intel_cursor_error_state {
16419 u32 control;
16420 u32 position;
16421 u32 base;
16422 u32 size;
16423 } cursor[I915_MAX_PIPES];
16424
16425 struct intel_pipe_error_state {
16426 bool power_domain_on;
16427 u32 source;
16428 u32 stat;
16429 } pipe[I915_MAX_PIPES];
16430
16431 struct intel_plane_error_state {
16432 u32 control;
16433 u32 stride;
16434 u32 size;
16435 u32 pos;
16436 u32 addr;
16437 u32 surface;
16438 u32 tile_offset;
16439 } plane[I915_MAX_PIPES];
16440
16441 struct intel_transcoder_error_state {
16442 bool power_domain_on;
16443 enum transcoder cpu_transcoder;
16444
16445 u32 conf;
16446
16447 u32 htotal;
16448 u32 hblank;
16449 u32 hsync;
16450 u32 vtotal;
16451 u32 vblank;
16452 u32 vsync;
16453 } transcoder[4];
16454 };
16455
16456 struct intel_display_error_state *
16457 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
16458 {
16459 struct intel_display_error_state *error;
16460 int transcoders[] = {
16461 TRANSCODER_A,
16462 TRANSCODER_B,
16463 TRANSCODER_C,
16464 TRANSCODER_EDP,
16465 };
16466 int i;
16467
16468 if (INTEL_INFO(dev_priv)->num_pipes == 0)
16469 return NULL;
16470
16471 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16472 if (error == NULL)
16473 return NULL;
16474
16475 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
16476 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16477
16478 for_each_pipe(dev_priv, i) {
16479 error->pipe[i].power_domain_on =
16480 __intel_display_power_is_enabled(dev_priv,
16481 POWER_DOMAIN_PIPE(i));
16482 if (!error->pipe[i].power_domain_on)
16483 continue;
16484
16485 error->cursor[i].control = I915_READ(CURCNTR(i));
16486 error->cursor[i].position = I915_READ(CURPOS(i));
16487 error->cursor[i].base = I915_READ(CURBASE(i));
16488
16489 error->plane[i].control = I915_READ(DSPCNTR(i));
16490 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16491 if (INTEL_GEN(dev_priv) <= 3) {
16492 error->plane[i].size = I915_READ(DSPSIZE(i));
16493 error->plane[i].pos = I915_READ(DSPPOS(i));
16494 }
16495 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
16496 error->plane[i].addr = I915_READ(DSPADDR(i));
16497 if (INTEL_GEN(dev_priv) >= 4) {
16498 error->plane[i].surface = I915_READ(DSPSURF(i));
16499 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16500 }
16501
16502 error->pipe[i].source = I915_READ(PIPESRC(i));
16503
16504 if (HAS_GMCH_DISPLAY(dev_priv))
16505 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16506 }
16507
16508 /* Note: this does not include DSI transcoders. */
16509 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
16510 if (HAS_DDI(dev_priv))
16511 error->num_transcoders++; /* Account for eDP. */
16512
16513 for (i = 0; i < error->num_transcoders; i++) {
16514 enum transcoder cpu_transcoder = transcoders[i];
16515
16516 error->transcoder[i].power_domain_on =
16517 __intel_display_power_is_enabled(dev_priv,
16518 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16519 if (!error->transcoder[i].power_domain_on)
16520 continue;
16521
16522 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16523
16524 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16525 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16526 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16527 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16528 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16529 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16530 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16531 }
16532
16533 return error;
16534 }
16535
16536 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16537
16538 void
16539 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16540 struct drm_device *dev,
16541 struct intel_display_error_state *error)
16542 {
16543 struct drm_i915_private *dev_priv = dev->dev_private;
16544 int i;
16545
16546 if (!error)
16547 return;
16548
16549 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16551 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16552 error->power_well_driver);
16553 for_each_pipe(dev_priv, i) {
16554 err_printf(m, "Pipe [%d]:\n", i);
16555 err_printf(m, " Power: %s\n",
16556 onoff(error->pipe[i].power_domain_on));
16557 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16558 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16559
16560 err_printf(m, "Plane [%d]:\n", i);
16561 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16562 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16563 if (INTEL_INFO(dev)->gen <= 3) {
16564 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16565 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16566 }
16567 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16568 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16569 if (INTEL_INFO(dev)->gen >= 4) {
16570 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16571 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16572 }
16573
16574 err_printf(m, "Cursor [%d]:\n", i);
16575 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16576 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16577 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16578 }
16579
16580 for (i = 0; i < error->num_transcoders; i++) {
16581 err_printf(m, "CPU transcoder: %s\n",
16582 transcoder_name(error->transcoder[i].cpu_transcoder));
16583 err_printf(m, " Power: %s\n",
16584 onoff(error->transcoder[i].power_domain_on));
16585 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16586 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16587 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16588 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16589 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16590 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16591 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16592 }
16593 }
Linux kernel - Deliverables
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