2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv
= {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
320 .vco
= { .min
= 4000000, .max
= 6000000 },
321 .n
= { .min
= 1, .max
= 7 },
322 .m1
= { .min
= 2, .max
= 3 },
323 .m2
= { .min
= 11, .max
= 156 },
324 .p1
= { .min
= 2, .max
= 3 },
325 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
330 clock
->m
= clock
->m1
* clock
->m2
;
331 clock
->p
= clock
->p1
* clock
->p2
;
332 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
333 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
337 * Returns whether any output on the specified pipe is of the specified type
339 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
341 struct drm_device
*dev
= crtc
->dev
;
342 struct intel_encoder
*encoder
;
344 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
345 if (encoder
->type
== type
)
351 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
354 struct drm_device
*dev
= crtc
->dev
;
355 const intel_limit_t
*limit
;
357 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
358 if (intel_is_dual_link_lvds(dev
)) {
359 if (refclk
== 100000)
360 limit
= &intel_limits_ironlake_dual_lvds_100m
;
362 limit
= &intel_limits_ironlake_dual_lvds
;
364 if (refclk
== 100000)
365 limit
= &intel_limits_ironlake_single_lvds_100m
;
367 limit
= &intel_limits_ironlake_single_lvds
;
370 limit
= &intel_limits_ironlake_dac
;
375 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
377 struct drm_device
*dev
= crtc
->dev
;
378 const intel_limit_t
*limit
;
380 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
381 if (intel_is_dual_link_lvds(dev
))
382 limit
= &intel_limits_g4x_dual_channel_lvds
;
384 limit
= &intel_limits_g4x_single_channel_lvds
;
385 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
386 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
387 limit
= &intel_limits_g4x_hdmi
;
388 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
389 limit
= &intel_limits_g4x_sdvo
;
390 } else /* The option is for other outputs */
391 limit
= &intel_limits_i9xx_sdvo
;
396 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
398 struct drm_device
*dev
= crtc
->dev
;
399 const intel_limit_t
*limit
;
401 if (HAS_PCH_SPLIT(dev
))
402 limit
= intel_ironlake_limit(crtc
, refclk
);
403 else if (IS_G4X(dev
)) {
404 limit
= intel_g4x_limit(crtc
);
405 } else if (IS_PINEVIEW(dev
)) {
406 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
407 limit
= &intel_limits_pineview_lvds
;
409 limit
= &intel_limits_pineview_sdvo
;
410 } else if (IS_VALLEYVIEW(dev
)) {
411 limit
= &intel_limits_vlv
;
412 } else if (!IS_GEN2(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
414 limit
= &intel_limits_i9xx_lvds
;
416 limit
= &intel_limits_i9xx_sdvo
;
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i8xx_lvds
;
420 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
421 limit
= &intel_limits_i8xx_dvo
;
423 limit
= &intel_limits_i8xx_dac
;
428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
429 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
431 clock
->m
= clock
->m2
+ 2;
432 clock
->p
= clock
->p1
* clock
->p2
;
433 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
434 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
437 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
439 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
442 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
444 clock
->m
= i9xx_dpll_compute_m(clock
);
445 clock
->p
= clock
->p1
* clock
->p2
;
446 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
447 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
450 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
456 static bool intel_PLL_is_valid(struct drm_device
*dev
,
457 const intel_limit_t
*limit
,
458 const intel_clock_t
*clock
)
460 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
461 INTELPllInvalid("n out of range\n");
462 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
463 INTELPllInvalid("p1 out of range\n");
464 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
465 INTELPllInvalid("m2 out of range\n");
466 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
467 INTELPllInvalid("m1 out of range\n");
469 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
470 if (clock
->m1
<= clock
->m2
)
471 INTELPllInvalid("m1 <= m2\n");
473 if (!IS_VALLEYVIEW(dev
)) {
474 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
475 INTELPllInvalid("p out of range\n");
476 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
477 INTELPllInvalid("m out of range\n");
480 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
493 int target
, int refclk
, intel_clock_t
*match_clock
,
494 intel_clock_t
*best_clock
)
496 struct drm_device
*dev
= crtc
->dev
;
500 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev
))
507 clock
.p2
= limit
->p2
.p2_fast
;
509 clock
.p2
= limit
->p2
.p2_slow
;
511 if (target
< limit
->p2
.dot_limit
)
512 clock
.p2
= limit
->p2
.p2_slow
;
514 clock
.p2
= limit
->p2
.p2_fast
;
517 memset(best_clock
, 0, sizeof(*best_clock
));
519 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
521 for (clock
.m2
= limit
->m2
.min
;
522 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
523 if (clock
.m2
>= clock
.m1
)
525 for (clock
.n
= limit
->n
.min
;
526 clock
.n
<= limit
->n
.max
; clock
.n
++) {
527 for (clock
.p1
= limit
->p1
.min
;
528 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
531 i9xx_clock(refclk
, &clock
);
532 if (!intel_PLL_is_valid(dev
, limit
,
536 clock
.p
!= match_clock
->p
)
539 this_err
= abs(clock
.dot
- target
);
540 if (this_err
< err
) {
549 return (err
!= target
);
553 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
554 int target
, int refclk
, intel_clock_t
*match_clock
,
555 intel_clock_t
*best_clock
)
557 struct drm_device
*dev
= crtc
->dev
;
561 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev
))
568 clock
.p2
= limit
->p2
.p2_fast
;
570 clock
.p2
= limit
->p2
.p2_slow
;
572 if (target
< limit
->p2
.dot_limit
)
573 clock
.p2
= limit
->p2
.p2_slow
;
575 clock
.p2
= limit
->p2
.p2_fast
;
578 memset(best_clock
, 0, sizeof(*best_clock
));
580 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
582 for (clock
.m2
= limit
->m2
.min
;
583 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
584 for (clock
.n
= limit
->n
.min
;
585 clock
.n
<= limit
->n
.max
; clock
.n
++) {
586 for (clock
.p1
= limit
->p1
.min
;
587 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
590 pineview_clock(refclk
, &clock
);
591 if (!intel_PLL_is_valid(dev
, limit
,
595 clock
.p
!= match_clock
->p
)
598 this_err
= abs(clock
.dot
- target
);
599 if (this_err
< err
) {
608 return (err
!= target
);
612 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
613 int target
, int refclk
, intel_clock_t
*match_clock
,
614 intel_clock_t
*best_clock
)
616 struct drm_device
*dev
= crtc
->dev
;
620 /* approximately equals target * 0.00585 */
621 int err_most
= (target
>> 8) + (target
>> 9);
624 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
625 if (intel_is_dual_link_lvds(dev
))
626 clock
.p2
= limit
->p2
.p2_fast
;
628 clock
.p2
= limit
->p2
.p2_slow
;
630 if (target
< limit
->p2
.dot_limit
)
631 clock
.p2
= limit
->p2
.p2_slow
;
633 clock
.p2
= limit
->p2
.p2_fast
;
636 memset(best_clock
, 0, sizeof(*best_clock
));
637 max_n
= limit
->n
.max
;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock
.m1
= limit
->m1
.max
;
642 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
643 for (clock
.m2
= limit
->m2
.max
;
644 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
645 for (clock
.p1
= limit
->p1
.max
;
646 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
649 i9xx_clock(refclk
, &clock
);
650 if (!intel_PLL_is_valid(dev
, limit
,
654 this_err
= abs(clock
.dot
- target
);
655 if (this_err
< err_most
) {
669 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
670 int target
, int refclk
, intel_clock_t
*match_clock
,
671 intel_clock_t
*best_clock
)
673 struct drm_device
*dev
= crtc
->dev
;
675 unsigned int bestppm
= 1000000;
676 /* min update 19.2 MHz */
677 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
680 target
*= 5; /* fast clock */
682 memset(best_clock
, 0, sizeof(*best_clock
));
684 /* based on hardware requirement, prefer smaller n to precision */
685 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
686 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
687 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
688 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
689 clock
.p
= clock
.p1
* clock
.p2
;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
692 unsigned int ppm
, diff
;
694 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
697 vlv_clock(refclk
, &clock
);
699 if (!intel_PLL_is_valid(dev
, limit
,
703 diff
= abs(clock
.dot
- target
);
704 ppm
= div_u64(1000000ULL * diff
, target
);
706 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
712 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
725 bool intel_crtc_active(struct drm_crtc
*crtc
)
727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
732 * We can ditch the adjusted_mode.crtc_clock check as soon
733 * as Haswell has gained clock readout/fastboot support.
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
738 return intel_crtc
->active
&& crtc
->fb
&&
739 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
742 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
745 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
748 return intel_crtc
->config
.cpu_transcoder
;
751 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
754 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
756 frame
= I915_READ(frame_reg
);
758 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
763 * intel_wait_for_vblank - wait for vblank on a given pipe
765 * @pipe: pipe to wait for
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
770 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
773 int pipestat_reg
= PIPESTAT(pipe
);
775 if (INTEL_INFO(dev
)->gen
>= 5) {
776 ironlake_wait_for_vblank(dev
, pipe
);
780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
793 I915_WRITE(pipestat_reg
,
794 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
796 /* Wait for vblank interrupt bit to set */
797 if (wait_for(I915_READ(pipestat_reg
) &
798 PIPE_VBLANK_INTERRUPT_STATUS
,
800 DRM_DEBUG_KMS("vblank wait timed out\n");
803 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
806 u32 reg
= PIPEDSL(pipe
);
811 line_mask
= DSL_LINEMASK_GEN2
;
813 line_mask
= DSL_LINEMASK_GEN3
;
815 line1
= I915_READ(reg
) & line_mask
;
817 line2
= I915_READ(reg
) & line_mask
;
819 return line1
== line2
;
823 * intel_wait_for_pipe_off - wait for pipe to turn off
825 * @pipe: pipe to wait for
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
832 * wait for the pipe register state bit to turn off
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
839 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
842 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
845 if (INTEL_INFO(dev
)->gen
>= 4) {
846 int reg
= PIPECONF(cpu_transcoder
);
848 /* Wait for the Pipe State to go off */
849 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
851 WARN(1, "pipe_off wait timed out\n");
853 /* Wait for the display line to settle */
854 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
855 WARN(1, "pipe_off wait timed out\n");
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
864 * Returns true if @port is connected, false otherwise.
866 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
867 struct intel_digital_port
*port
)
871 if (HAS_PCH_IBX(dev_priv
->dev
)) {
874 bit
= SDE_PORTB_HOTPLUG
;
877 bit
= SDE_PORTC_HOTPLUG
;
880 bit
= SDE_PORTD_HOTPLUG
;
888 bit
= SDE_PORTB_HOTPLUG_CPT
;
891 bit
= SDE_PORTC_HOTPLUG_CPT
;
894 bit
= SDE_PORTD_HOTPLUG_CPT
;
901 return I915_READ(SDEISR
) & bit
;
904 static const char *state_string(bool enabled
)
906 return enabled
? "on" : "off";
909 /* Only for pre-ILK configs */
910 void assert_pll(struct drm_i915_private
*dev_priv
,
911 enum pipe pipe
, bool state
)
918 val
= I915_READ(reg
);
919 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
920 WARN(cur_state
!= state
,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state
), state_string(cur_state
));
925 /* XXX: the dsi pll is shared between MIPI DSI ports */
926 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
931 mutex_lock(&dev_priv
->dpio_lock
);
932 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
933 mutex_unlock(&dev_priv
->dpio_lock
);
935 cur_state
= val
& DSI_PLL_VCO_EN
;
936 WARN(cur_state
!= state
,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state
), state_string(cur_state
));
940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
943 struct intel_shared_dpll
*
944 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
946 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
948 if (crtc
->config
.shared_dpll
< 0)
951 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
955 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
956 struct intel_shared_dpll
*pll
,
960 struct intel_dpll_hw_state hw_state
;
962 if (HAS_PCH_LPT(dev_priv
->dev
)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
968 "asserting DPLL %s with no DPLL\n", state_string(state
)))
971 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
972 WARN(cur_state
!= state
,
973 "%s assertion failure (expected %s, current %s)\n",
974 pll
->name
, state_string(state
), state_string(cur_state
));
977 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
978 enum pipe pipe
, bool state
)
983 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
986 if (HAS_DDI(dev_priv
->dev
)) {
987 /* DDI does not have a specific FDI_TX register */
988 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
989 val
= I915_READ(reg
);
990 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
992 reg
= FDI_TX_CTL(pipe
);
993 val
= I915_READ(reg
);
994 cur_state
= !!(val
& FDI_TX_ENABLE
);
996 WARN(cur_state
!= state
,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state
), state_string(cur_state
));
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1003 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1004 enum pipe pipe
, bool state
)
1010 reg
= FDI_RX_CTL(pipe
);
1011 val
= I915_READ(reg
);
1012 cur_state
= !!(val
& FDI_RX_ENABLE
);
1013 WARN(cur_state
!= state
,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state
), state_string(cur_state
));
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv
->info
->gen
== 5)
1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031 if (HAS_DDI(dev_priv
->dev
))
1034 reg
= FDI_TX_CTL(pipe
);
1035 val
= I915_READ(reg
);
1036 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1039 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1040 enum pipe pipe
, bool state
)
1046 reg
= FDI_RX_CTL(pipe
);
1047 val
= I915_READ(reg
);
1048 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1049 WARN(cur_state
!= state
,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state
), state_string(cur_state
));
1054 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1057 int pp_reg
, lvds_reg
;
1059 enum pipe panel_pipe
= PIPE_A
;
1062 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1063 pp_reg
= PCH_PP_CONTROL
;
1064 lvds_reg
= PCH_LVDS
;
1066 pp_reg
= PP_CONTROL
;
1070 val
= I915_READ(pp_reg
);
1071 if (!(val
& PANEL_POWER_ON
) ||
1072 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1075 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1076 panel_pipe
= PIPE_B
;
1078 WARN(panel_pipe
== pipe
&& locked
,
1079 "panel assertion failure, pipe %c regs locked\n",
1083 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1084 enum pipe pipe
, bool state
)
1086 struct drm_device
*dev
= dev_priv
->dev
;
1089 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1090 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1091 else if (IS_845G(dev
) || IS_I865G(dev
))
1092 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1094 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1096 WARN(cur_state
!= state
,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1103 void assert_pipe(struct drm_i915_private
*dev_priv
,
1104 enum pipe pipe
, bool state
)
1109 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1116 if (!intel_display_power_enabled(dev_priv
->dev
,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1120 reg
= PIPECONF(cpu_transcoder
);
1121 val
= I915_READ(reg
);
1122 cur_state
= !!(val
& PIPECONF_ENABLE
);
1125 WARN(cur_state
!= state
,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
1127 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1130 static void assert_plane(struct drm_i915_private
*dev_priv
,
1131 enum plane plane
, bool state
)
1137 reg
= DSPCNTR(plane
);
1138 val
= I915_READ(reg
);
1139 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1140 WARN(cur_state
!= state
,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane
), state_string(state
), state_string(cur_state
));
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1148 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1151 struct drm_device
*dev
= dev_priv
->dev
;
1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev
)->gen
>= 4) {
1158 reg
= DSPCNTR(pipe
);
1159 val
= I915_READ(reg
);
1160 WARN((val
& DISPLAY_PLANE_ENABLE
),
1161 "plane %c assertion failure, should be disabled but not\n",
1166 /* Need to check both planes against the pipe */
1169 val
= I915_READ(reg
);
1170 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1171 DISPPLANE_SEL_PIPE_SHIFT
;
1172 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i
), pipe_name(pipe
));
1178 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1181 struct drm_device
*dev
= dev_priv
->dev
;
1185 if (IS_VALLEYVIEW(dev
)) {
1186 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1187 reg
= SPCNTR(pipe
, i
);
1188 val
= I915_READ(reg
);
1189 WARN((val
& SP_ENABLE
),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe
, i
), pipe_name(pipe
));
1193 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1195 val
= I915_READ(reg
);
1196 WARN((val
& SPRITE_ENABLE
),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 plane_name(pipe
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1200 reg
= DVSCNTR(pipe
);
1201 val
= I915_READ(reg
);
1202 WARN((val
& DVS_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1208 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1213 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1218 val
= I915_READ(PCH_DREF_CONTROL
);
1219 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1220 DREF_SUPERSPREAD_SOURCE_MASK
));
1221 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1231 reg
= PCH_TRANSCONF(pipe
);
1232 val
= I915_READ(reg
);
1233 enabled
= !!(val
& TRANS_ENABLE
);
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1239 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1240 enum pipe pipe
, u32 port_sel
, u32 val
)
1242 if ((val
& DP_PORT_EN
) == 0)
1245 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1246 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1247 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1248 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1251 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1257 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1258 enum pipe pipe
, u32 val
)
1260 if ((val
& SDVO_ENABLE
) == 0)
1263 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1264 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1267 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1273 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1274 enum pipe pipe
, u32 val
)
1276 if ((val
& LVDS_PORT_EN
) == 0)
1279 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1280 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1283 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1289 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1290 enum pipe pipe
, u32 val
)
1292 if ((val
& ADPA_DAC_ENABLE
) == 0)
1294 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1295 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1298 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1304 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1305 enum pipe pipe
, int reg
, u32 port_sel
)
1307 u32 val
= I915_READ(reg
);
1308 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310 reg
, pipe_name(pipe
));
1312 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1313 && (val
& DP_PIPEB_SELECT
),
1314 "IBX PCH dp port still using transcoder B\n");
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1318 enum pipe pipe
, int reg
)
1320 u32 val
= I915_READ(reg
);
1321 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323 reg
, pipe_name(pipe
));
1325 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1326 && (val
& SDVO_PIPE_B_SELECT
),
1327 "IBX PCH hdmi port still using transcoder B\n");
1330 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1336 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1337 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1338 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1341 val
= I915_READ(reg
);
1342 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
1347 val
= I915_READ(reg
);
1348 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1352 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1353 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1354 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1357 static void intel_init_dpio(struct drm_device
*dev
)
1359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1361 if (!IS_VALLEYVIEW(dev
))
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1374 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1377 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1379 struct drm_device
*dev
= crtc
->base
.dev
;
1380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1381 int reg
= DPLL(crtc
->pipe
);
1382 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1384 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1391 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1393 I915_WRITE(reg
, dpll
);
1397 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1400 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1401 POSTING_READ(DPLL_MD(crtc
->pipe
));
1403 /* We do this three times for luck */
1404 I915_WRITE(reg
, dpll
);
1406 udelay(150); /* wait for warmup */
1407 I915_WRITE(reg
, dpll
);
1409 udelay(150); /* wait for warmup */
1410 I915_WRITE(reg
, dpll
);
1412 udelay(150); /* wait for warmup */
1415 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1417 struct drm_device
*dev
= crtc
->base
.dev
;
1418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1419 int reg
= DPLL(crtc
->pipe
);
1420 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1422 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1424 /* No really, not for ILK+ */
1425 BUG_ON(dev_priv
->info
->gen
>= 5);
1427 /* PLL is protected by panel, make sure we can write it */
1428 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1429 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1431 I915_WRITE(reg
, dpll
);
1433 /* Wait for the clocks to stabilize. */
1437 if (INTEL_INFO(dev
)->gen
>= 4) {
1438 I915_WRITE(DPLL_MD(crtc
->pipe
),
1439 crtc
->config
.dpll_hw_state
.dpll_md
);
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1444 * So write it again.
1446 I915_WRITE(reg
, dpll
);
1449 /* We do this three times for luck */
1450 I915_WRITE(reg
, dpll
);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg
, dpll
);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg
, dpll
);
1458 udelay(150); /* wait for warmup */
1462 * i9xx_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 * Note! This is for pre-ILK only.
1470 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv
, pipe
);
1479 I915_WRITE(DPLL(pipe
), 0);
1480 POSTING_READ(DPLL(pipe
));
1483 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv
, pipe
);
1490 /* Leave integrated clock source enabled */
1492 val
= DPLL_INTEGRATED_CRI_CLK_VLV
;
1493 I915_WRITE(DPLL(pipe
), val
);
1494 POSTING_READ(DPLL(pipe
));
1497 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1502 port_mask
= DPLL_PORTB_READY_MASK
;
1504 port_mask
= DPLL_PORTC_READY_MASK
;
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port
, I915_READ(DPLL(0)));
1512 * ironlake_enable_shared_dpll - enable PCH PLL
1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1519 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1521 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1522 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1524 /* PCH PLLs only available on ILK, SNB and IVB */
1525 BUG_ON(dev_priv
->info
->gen
< 5);
1526 if (WARN_ON(pll
== NULL
))
1529 if (WARN_ON(pll
->refcount
== 0))
1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll
->name
, pll
->active
, pll
->on
,
1534 crtc
->base
.base
.id
);
1536 if (pll
->active
++) {
1538 assert_shared_dpll_enabled(dev_priv
, pll
);
1543 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1544 pll
->enable(dev_priv
, pll
);
1548 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1550 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1551 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv
->info
->gen
< 5);
1555 if (WARN_ON(pll
== NULL
))
1558 if (WARN_ON(pll
->refcount
== 0))
1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll
->name
, pll
->active
, pll
->on
,
1563 crtc
->base
.base
.id
);
1565 if (WARN_ON(pll
->active
== 0)) {
1566 assert_shared_dpll_disabled(dev_priv
, pll
);
1570 assert_shared_dpll_enabled(dev_priv
, pll
);
1575 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1576 pll
->disable(dev_priv
, pll
);
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1583 struct drm_device
*dev
= dev_priv
->dev
;
1584 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1585 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1586 uint32_t reg
, val
, pipeconf_val
;
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv
->info
->gen
< 5);
1591 /* Make sure PCH DPLL is enabled */
1592 assert_shared_dpll_enabled(dev_priv
,
1593 intel_crtc_to_shared_dpll(intel_crtc
));
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv
, pipe
);
1597 assert_fdi_rx_enabled(dev_priv
, pipe
);
1599 if (HAS_PCH_CPT(dev
)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg
= TRANS_CHICKEN2(pipe
);
1603 val
= I915_READ(reg
);
1604 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1605 I915_WRITE(reg
, val
);
1608 reg
= PCH_TRANSCONF(pipe
);
1609 val
= I915_READ(reg
);
1610 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1612 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1617 val
&= ~PIPECONF_BPC_MASK
;
1618 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1621 val
&= ~TRANS_INTERLACE_MASK
;
1622 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1623 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1624 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1625 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1627 val
|= TRANS_INTERLACED
;
1629 val
|= TRANS_PROGRESSIVE
;
1631 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1632 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1637 enum transcoder cpu_transcoder
)
1639 u32 val
, pipeconf_val
;
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv
->info
->gen
< 5);
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1646 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1648 /* Workaround: set timing override bit. */
1649 val
= I915_READ(_TRANSA_CHICKEN2
);
1650 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1651 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1654 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1656 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1657 PIPECONF_INTERLACED_ILK
)
1658 val
|= TRANS_INTERLACED
;
1660 val
|= TRANS_PROGRESSIVE
;
1662 I915_WRITE(LPT_TRANSCONF
, val
);
1663 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1670 struct drm_device
*dev
= dev_priv
->dev
;
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv
, pipe
);
1675 assert_fdi_rx_disabled(dev_priv
, pipe
);
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv
, pipe
);
1680 reg
= PCH_TRANSCONF(pipe
);
1681 val
= I915_READ(reg
);
1682 val
&= ~TRANS_ENABLE
;
1683 I915_WRITE(reg
, val
);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1688 if (!HAS_PCH_IBX(dev
)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg
= TRANS_CHICKEN2(pipe
);
1691 val
= I915_READ(reg
);
1692 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1693 I915_WRITE(reg
, val
);
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1701 val
= I915_READ(LPT_TRANSCONF
);
1702 val
&= ~TRANS_ENABLE
;
1703 I915_WRITE(LPT_TRANSCONF
, val
);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1708 /* Workaround: clear timing override bit. */
1709 val
= I915_READ(_TRANSA_CHICKEN2
);
1710 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1711 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1723 * @pipe should be %PIPE_A or %PIPE_B.
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1728 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1729 bool pch_port
, bool dsi
)
1731 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1733 enum pipe pch_transcoder
;
1737 assert_planes_disabled(dev_priv
, pipe
);
1738 assert_cursor_disabled(dev_priv
, pipe
);
1739 assert_sprites_disabled(dev_priv
, pipe
);
1741 if (HAS_PCH_LPT(dev_priv
->dev
))
1742 pch_transcoder
= TRANSCODER_A
;
1744 pch_transcoder
= pipe
;
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1751 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1753 assert_dsi_pll_enabled(dev_priv
);
1755 assert_pll_enabled(dev_priv
, pipe
);
1758 /* if driving the PCH, we need FDI enabled */
1759 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1760 assert_fdi_tx_pll_enabled(dev_priv
,
1761 (enum pipe
) cpu_transcoder
);
1763 /* FIXME: assert CPU port conditions for SNB+ */
1766 reg
= PIPECONF(cpu_transcoder
);
1767 val
= I915_READ(reg
);
1768 if (val
& PIPECONF_ENABLE
)
1771 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1772 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1776 * intel_disable_pipe - disable a pipe, asserting requirements
1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1783 * @pipe should be %PIPE_A or %PIPE_B.
1785 * Will wait until the pipe has shut down before returning.
1787 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1790 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1799 assert_planes_disabled(dev_priv
, pipe
);
1800 assert_cursor_disabled(dev_priv
, pipe
);
1801 assert_sprites_disabled(dev_priv
, pipe
);
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1807 reg
= PIPECONF(cpu_transcoder
);
1808 val
= I915_READ(reg
);
1809 if ((val
& PIPECONF_ENABLE
) == 0)
1812 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1813 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1820 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1823 u32 reg
= dev_priv
->info
->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
1825 I915_WRITE(reg
, I915_READ(reg
));
1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1837 static void intel_enable_primary_plane(struct drm_i915_private
*dev_priv
,
1838 enum plane plane
, enum pipe pipe
)
1840 struct intel_crtc
*intel_crtc
=
1841 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv
, pipe
);
1848 WARN(intel_crtc
->primary_enabled
, "Primary plane already enabled\n");
1850 intel_crtc
->primary_enabled
= true;
1852 reg
= DSPCNTR(plane
);
1853 val
= I915_READ(reg
);
1854 if (val
& DISPLAY_PLANE_ENABLE
)
1857 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1858 intel_flush_primary_plane(dev_priv
, plane
);
1859 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1863 * intel_disable_primary_plane - disable the primary plane
1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1868 * Disable @plane; should be an independent operation.
1870 static void intel_disable_primary_plane(struct drm_i915_private
*dev_priv
,
1871 enum plane plane
, enum pipe pipe
)
1873 struct intel_crtc
*intel_crtc
=
1874 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1878 WARN(!intel_crtc
->primary_enabled
, "Primary plane already disabled\n");
1880 intel_crtc
->primary_enabled
= false;
1882 reg
= DSPCNTR(plane
);
1883 val
= I915_READ(reg
);
1884 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1887 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1888 intel_flush_primary_plane(dev_priv
, plane
);
1889 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1892 static bool need_vtd_wa(struct drm_device
*dev
)
1894 #ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1902 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1903 struct drm_i915_gem_object
*obj
,
1904 struct intel_ring_buffer
*pipelined
)
1906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1910 switch (obj
->tiling_mode
) {
1911 case I915_TILING_NONE
:
1912 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1913 alignment
= 128 * 1024;
1914 else if (INTEL_INFO(dev
)->gen
>= 4)
1915 alignment
= 4 * 1024;
1917 alignment
= 64 * 1024;
1920 /* pin() will align the object as required by fence */
1924 /* Despite that we check this in framebuffer_init userspace can
1925 * screw us over and change the tiling after the fact. Only
1926 * pinned buffers can't change their tiling. */
1927 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1933 /* Note that the w/a also requires 64 PTE of padding following the
1934 * bo. We currently fill all unused PTE with the shadow page and so
1935 * we should always have valid PTE following the scanout preventing
1938 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1939 alignment
= 256 * 1024;
1941 dev_priv
->mm
.interruptible
= false;
1942 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1944 goto err_interruptible
;
1946 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1947 * fence, whereas 965+ only requires a fence if using
1948 * framebuffer compression. For simplicity, we always install
1949 * a fence as the cost is not that onerous.
1951 ret
= i915_gem_object_get_fence(obj
);
1955 i915_gem_object_pin_fence(obj
);
1957 dev_priv
->mm
.interruptible
= true;
1961 i915_gem_object_unpin_from_display_plane(obj
);
1963 dev_priv
->mm
.interruptible
= true;
1967 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1969 i915_gem_object_unpin_fence(obj
);
1970 i915_gem_object_unpin_from_display_plane(obj
);
1973 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1974 * is assumed to be a power-of-two. */
1975 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1976 unsigned int tiling_mode
,
1980 if (tiling_mode
!= I915_TILING_NONE
) {
1981 unsigned int tile_rows
, tiles
;
1986 tiles
= *x
/ (512/cpp
);
1989 return tile_rows
* pitch
* 8 + tiles
* 4096;
1991 unsigned int offset
;
1993 offset
= *y
* pitch
+ *x
* cpp
;
1995 *x
= (offset
& 4095) / cpp
;
1996 return offset
& -4096;
2000 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2003 struct drm_device
*dev
= crtc
->dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2006 struct intel_framebuffer
*intel_fb
;
2007 struct drm_i915_gem_object
*obj
;
2008 int plane
= intel_crtc
->plane
;
2009 unsigned long linear_offset
;
2018 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2022 intel_fb
= to_intel_framebuffer(fb
);
2023 obj
= intel_fb
->obj
;
2025 reg
= DSPCNTR(plane
);
2026 dspcntr
= I915_READ(reg
);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2029 switch (fb
->pixel_format
) {
2031 dspcntr
|= DISPPLANE_8BPP
;
2033 case DRM_FORMAT_XRGB1555
:
2034 case DRM_FORMAT_ARGB1555
:
2035 dspcntr
|= DISPPLANE_BGRX555
;
2037 case DRM_FORMAT_RGB565
:
2038 dspcntr
|= DISPPLANE_BGRX565
;
2040 case DRM_FORMAT_XRGB8888
:
2041 case DRM_FORMAT_ARGB8888
:
2042 dspcntr
|= DISPPLANE_BGRX888
;
2044 case DRM_FORMAT_XBGR8888
:
2045 case DRM_FORMAT_ABGR8888
:
2046 dspcntr
|= DISPPLANE_RGBX888
;
2048 case DRM_FORMAT_XRGB2101010
:
2049 case DRM_FORMAT_ARGB2101010
:
2050 dspcntr
|= DISPPLANE_BGRX101010
;
2052 case DRM_FORMAT_XBGR2101010
:
2053 case DRM_FORMAT_ABGR2101010
:
2054 dspcntr
|= DISPPLANE_RGBX101010
;
2060 if (INTEL_INFO(dev
)->gen
>= 4) {
2061 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2062 dspcntr
|= DISPPLANE_TILED
;
2064 dspcntr
&= ~DISPPLANE_TILED
;
2068 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2070 I915_WRITE(reg
, dspcntr
);
2072 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2074 if (INTEL_INFO(dev
)->gen
>= 4) {
2075 intel_crtc
->dspaddr_offset
=
2076 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2077 fb
->bits_per_pixel
/ 8,
2079 linear_offset
-= intel_crtc
->dspaddr_offset
;
2081 intel_crtc
->dspaddr_offset
= linear_offset
;
2084 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2085 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2087 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2088 if (INTEL_INFO(dev
)->gen
>= 4) {
2089 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2090 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2091 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2092 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2094 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2100 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2101 struct drm_framebuffer
*fb
, int x
, int y
)
2103 struct drm_device
*dev
= crtc
->dev
;
2104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2105 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2106 struct intel_framebuffer
*intel_fb
;
2107 struct drm_i915_gem_object
*obj
;
2108 int plane
= intel_crtc
->plane
;
2109 unsigned long linear_offset
;
2119 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2123 intel_fb
= to_intel_framebuffer(fb
);
2124 obj
= intel_fb
->obj
;
2126 reg
= DSPCNTR(plane
);
2127 dspcntr
= I915_READ(reg
);
2128 /* Mask out pixel format bits in case we change it */
2129 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2130 switch (fb
->pixel_format
) {
2132 dspcntr
|= DISPPLANE_8BPP
;
2134 case DRM_FORMAT_RGB565
:
2135 dspcntr
|= DISPPLANE_BGRX565
;
2137 case DRM_FORMAT_XRGB8888
:
2138 case DRM_FORMAT_ARGB8888
:
2139 dspcntr
|= DISPPLANE_BGRX888
;
2141 case DRM_FORMAT_XBGR8888
:
2142 case DRM_FORMAT_ABGR8888
:
2143 dspcntr
|= DISPPLANE_RGBX888
;
2145 case DRM_FORMAT_XRGB2101010
:
2146 case DRM_FORMAT_ARGB2101010
:
2147 dspcntr
|= DISPPLANE_BGRX101010
;
2149 case DRM_FORMAT_XBGR2101010
:
2150 case DRM_FORMAT_ABGR2101010
:
2151 dspcntr
|= DISPPLANE_RGBX101010
;
2157 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2158 dspcntr
|= DISPPLANE_TILED
;
2160 dspcntr
&= ~DISPPLANE_TILED
;
2162 if (IS_HASWELL(dev
))
2163 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2165 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2167 I915_WRITE(reg
, dspcntr
);
2169 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2170 intel_crtc
->dspaddr_offset
=
2171 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2172 fb
->bits_per_pixel
/ 8,
2174 linear_offset
-= intel_crtc
->dspaddr_offset
;
2176 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2177 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2179 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2180 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2181 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2182 if (IS_HASWELL(dev
)) {
2183 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2185 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2186 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2193 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2195 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2196 int x
, int y
, enum mode_set_atomic state
)
2198 struct drm_device
*dev
= crtc
->dev
;
2199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2201 if (dev_priv
->display
.disable_fbc
)
2202 dev_priv
->display
.disable_fbc(dev
);
2203 intel_increase_pllclock(crtc
);
2205 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2208 void intel_display_handle_reset(struct drm_device
*dev
)
2210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2211 struct drm_crtc
*crtc
;
2214 * Flips in the rings have been nuked by the reset,
2215 * so complete all pending flips so that user space
2216 * will get its events and not get stuck.
2218 * Also update the base address of all primary
2219 * planes to the the last fb to make sure we're
2220 * showing the correct fb after a reset.
2222 * Need to make two loops over the crtcs so that we
2223 * don't try to grab a crtc mutex before the
2224 * pending_flip_queue really got woken up.
2227 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2229 enum plane plane
= intel_crtc
->plane
;
2231 intel_prepare_page_flip(dev
, plane
);
2232 intel_finish_page_flip_plane(dev
, plane
);
2235 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2238 mutex_lock(&crtc
->mutex
);
2239 if (intel_crtc
->active
)
2240 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2242 mutex_unlock(&crtc
->mutex
);
2247 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2249 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2250 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2251 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2254 /* Big Hammer, we also need to ensure that any pending
2255 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2256 * current scanout is retired before unpinning the old
2259 * This should only fail upon a hung GPU, in which case we
2260 * can safely continue.
2262 dev_priv
->mm
.interruptible
= false;
2263 ret
= i915_gem_object_finish_gpu(obj
);
2264 dev_priv
->mm
.interruptible
= was_interruptible
;
2269 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2271 struct drm_device
*dev
= crtc
->dev
;
2272 struct drm_i915_master_private
*master_priv
;
2273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2275 if (!dev
->primary
->master
)
2278 master_priv
= dev
->primary
->master
->driver_priv
;
2279 if (!master_priv
->sarea_priv
)
2282 switch (intel_crtc
->pipe
) {
2284 master_priv
->sarea_priv
->pipeA_x
= x
;
2285 master_priv
->sarea_priv
->pipeA_y
= y
;
2288 master_priv
->sarea_priv
->pipeB_x
= x
;
2289 master_priv
->sarea_priv
->pipeB_y
= y
;
2297 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2298 struct drm_framebuffer
*fb
)
2300 struct drm_device
*dev
= crtc
->dev
;
2301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2302 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2303 struct drm_framebuffer
*old_fb
;
2308 DRM_ERROR("No FB bound\n");
2312 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2313 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2314 plane_name(intel_crtc
->plane
),
2315 INTEL_INFO(dev
)->num_pipes
);
2319 mutex_lock(&dev
->struct_mutex
);
2320 ret
= intel_pin_and_fence_fb_obj(dev
,
2321 to_intel_framebuffer(fb
)->obj
,
2324 mutex_unlock(&dev
->struct_mutex
);
2325 DRM_ERROR("pin & fence failed\n");
2330 * Update pipe size and adjust fitter if needed: the reason for this is
2331 * that in compute_mode_changes we check the native mode (not the pfit
2332 * mode) to see if we can flip rather than do a full mode set. In the
2333 * fastboot case, we'll flip, but if we don't update the pipesrc and
2334 * pfit state, we'll end up with a big fb scanned out into the wrong
2337 * To fix this properly, we need to hoist the checks up into
2338 * compute_mode_changes (or above), check the actual pfit state and
2339 * whether the platform allows pfit disable with pipe active, and only
2340 * then update the pipesrc and pfit state, even on the flip path.
2342 if (i915_fastboot
) {
2343 const struct drm_display_mode
*adjusted_mode
=
2344 &intel_crtc
->config
.adjusted_mode
;
2346 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2347 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2348 (adjusted_mode
->crtc_vdisplay
- 1));
2349 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2350 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2351 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2352 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2353 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2354 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2358 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2360 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2361 mutex_unlock(&dev
->struct_mutex
);
2362 DRM_ERROR("failed to update base address\n");
2372 if (intel_crtc
->active
&& old_fb
!= fb
)
2373 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2374 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2377 intel_update_fbc(dev
);
2378 intel_edp_psr_update(dev
);
2379 mutex_unlock(&dev
->struct_mutex
);
2381 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2386 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2388 struct drm_device
*dev
= crtc
->dev
;
2389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2391 int pipe
= intel_crtc
->pipe
;
2394 /* enable normal train */
2395 reg
= FDI_TX_CTL(pipe
);
2396 temp
= I915_READ(reg
);
2397 if (IS_IVYBRIDGE(dev
)) {
2398 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2399 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2401 temp
&= ~FDI_LINK_TRAIN_NONE
;
2402 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2404 I915_WRITE(reg
, temp
);
2406 reg
= FDI_RX_CTL(pipe
);
2407 temp
= I915_READ(reg
);
2408 if (HAS_PCH_CPT(dev
)) {
2409 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2410 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2412 temp
&= ~FDI_LINK_TRAIN_NONE
;
2413 temp
|= FDI_LINK_TRAIN_NONE
;
2415 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2417 /* wait one idle pattern time */
2421 /* IVB wants error correction enabled */
2422 if (IS_IVYBRIDGE(dev
))
2423 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2424 FDI_FE_ERRC_ENABLE
);
2427 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2429 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2432 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_crtc
*pipe_B_crtc
=
2436 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2437 struct intel_crtc
*pipe_C_crtc
=
2438 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2442 * When everything is off disable fdi C so that we could enable fdi B
2443 * with all lanes. Note that we don't care about enabled pipes without
2444 * an enabled pch encoder.
2446 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2447 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2448 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2449 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2451 temp
= I915_READ(SOUTH_CHICKEN1
);
2452 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2453 DRM_DEBUG_KMS("disabling fdi C rx\n");
2454 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2458 /* The FDI link training functions for ILK/Ibexpeak. */
2459 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2461 struct drm_device
*dev
= crtc
->dev
;
2462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2464 int pipe
= intel_crtc
->pipe
;
2465 int plane
= intel_crtc
->plane
;
2466 u32 reg
, temp
, tries
;
2468 /* FDI needs bits from pipe & plane first */
2469 assert_pipe_enabled(dev_priv
, pipe
);
2470 assert_plane_enabled(dev_priv
, plane
);
2472 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 reg
= FDI_RX_IMR(pipe
);
2475 temp
= I915_READ(reg
);
2476 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2477 temp
&= ~FDI_RX_BIT_LOCK
;
2478 I915_WRITE(reg
, temp
);
2482 /* enable CPU FDI TX and PCH FDI RX */
2483 reg
= FDI_TX_CTL(pipe
);
2484 temp
= I915_READ(reg
);
2485 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2486 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2487 temp
&= ~FDI_LINK_TRAIN_NONE
;
2488 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2489 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2491 reg
= FDI_RX_CTL(pipe
);
2492 temp
= I915_READ(reg
);
2493 temp
&= ~FDI_LINK_TRAIN_NONE
;
2494 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2495 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2500 /* Ironlake workaround, enable clock pointer after FDI enable*/
2501 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2502 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2503 FDI_RX_PHASE_SYNC_POINTER_EN
);
2505 reg
= FDI_RX_IIR(pipe
);
2506 for (tries
= 0; tries
< 5; tries
++) {
2507 temp
= I915_READ(reg
);
2508 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2510 if ((temp
& FDI_RX_BIT_LOCK
)) {
2511 DRM_DEBUG_KMS("FDI train 1 done.\n");
2512 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2517 DRM_ERROR("FDI train 1 fail!\n");
2520 reg
= FDI_TX_CTL(pipe
);
2521 temp
= I915_READ(reg
);
2522 temp
&= ~FDI_LINK_TRAIN_NONE
;
2523 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2524 I915_WRITE(reg
, temp
);
2526 reg
= FDI_RX_CTL(pipe
);
2527 temp
= I915_READ(reg
);
2528 temp
&= ~FDI_LINK_TRAIN_NONE
;
2529 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2530 I915_WRITE(reg
, temp
);
2535 reg
= FDI_RX_IIR(pipe
);
2536 for (tries
= 0; tries
< 5; tries
++) {
2537 temp
= I915_READ(reg
);
2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2540 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2541 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2542 DRM_DEBUG_KMS("FDI train 2 done.\n");
2547 DRM_ERROR("FDI train 2 fail!\n");
2549 DRM_DEBUG_KMS("FDI train done\n");
2553 static const int snb_b_fdi_train_param
[] = {
2554 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2555 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2556 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2557 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2560 /* The FDI link training functions for SNB/Cougarpoint. */
2561 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2563 struct drm_device
*dev
= crtc
->dev
;
2564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2565 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2566 int pipe
= intel_crtc
->pipe
;
2567 u32 reg
, temp
, i
, retry
;
2569 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2571 reg
= FDI_RX_IMR(pipe
);
2572 temp
= I915_READ(reg
);
2573 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2574 temp
&= ~FDI_RX_BIT_LOCK
;
2575 I915_WRITE(reg
, temp
);
2580 /* enable CPU FDI TX and PCH FDI RX */
2581 reg
= FDI_TX_CTL(pipe
);
2582 temp
= I915_READ(reg
);
2583 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2584 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2585 temp
&= ~FDI_LINK_TRAIN_NONE
;
2586 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2587 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2589 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2590 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2592 I915_WRITE(FDI_RX_MISC(pipe
),
2593 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2595 reg
= FDI_RX_CTL(pipe
);
2596 temp
= I915_READ(reg
);
2597 if (HAS_PCH_CPT(dev
)) {
2598 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2599 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2601 temp
&= ~FDI_LINK_TRAIN_NONE
;
2602 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2604 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2609 for (i
= 0; i
< 4; i
++) {
2610 reg
= FDI_TX_CTL(pipe
);
2611 temp
= I915_READ(reg
);
2612 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2613 temp
|= snb_b_fdi_train_param
[i
];
2614 I915_WRITE(reg
, temp
);
2619 for (retry
= 0; retry
< 5; retry
++) {
2620 reg
= FDI_RX_IIR(pipe
);
2621 temp
= I915_READ(reg
);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2623 if (temp
& FDI_RX_BIT_LOCK
) {
2624 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2625 DRM_DEBUG_KMS("FDI train 1 done.\n");
2634 DRM_ERROR("FDI train 1 fail!\n");
2637 reg
= FDI_TX_CTL(pipe
);
2638 temp
= I915_READ(reg
);
2639 temp
&= ~FDI_LINK_TRAIN_NONE
;
2640 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2642 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2644 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2646 I915_WRITE(reg
, temp
);
2648 reg
= FDI_RX_CTL(pipe
);
2649 temp
= I915_READ(reg
);
2650 if (HAS_PCH_CPT(dev
)) {
2651 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2652 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2654 temp
&= ~FDI_LINK_TRAIN_NONE
;
2655 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2657 I915_WRITE(reg
, temp
);
2662 for (i
= 0; i
< 4; i
++) {
2663 reg
= FDI_TX_CTL(pipe
);
2664 temp
= I915_READ(reg
);
2665 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2666 temp
|= snb_b_fdi_train_param
[i
];
2667 I915_WRITE(reg
, temp
);
2672 for (retry
= 0; retry
< 5; retry
++) {
2673 reg
= FDI_RX_IIR(pipe
);
2674 temp
= I915_READ(reg
);
2675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2676 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2677 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2678 DRM_DEBUG_KMS("FDI train 2 done.\n");
2687 DRM_ERROR("FDI train 2 fail!\n");
2689 DRM_DEBUG_KMS("FDI train done.\n");
2692 /* Manual link training for Ivy Bridge A0 parts */
2693 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2695 struct drm_device
*dev
= crtc
->dev
;
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2698 int pipe
= intel_crtc
->pipe
;
2699 u32 reg
, temp
, i
, j
;
2701 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2703 reg
= FDI_RX_IMR(pipe
);
2704 temp
= I915_READ(reg
);
2705 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2706 temp
&= ~FDI_RX_BIT_LOCK
;
2707 I915_WRITE(reg
, temp
);
2712 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2713 I915_READ(FDI_RX_IIR(pipe
)));
2715 /* Try each vswing and preemphasis setting twice before moving on */
2716 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2717 /* disable first in case we need to retry */
2718 reg
= FDI_TX_CTL(pipe
);
2719 temp
= I915_READ(reg
);
2720 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2721 temp
&= ~FDI_TX_ENABLE
;
2722 I915_WRITE(reg
, temp
);
2724 reg
= FDI_RX_CTL(pipe
);
2725 temp
= I915_READ(reg
);
2726 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2727 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2728 temp
&= ~FDI_RX_ENABLE
;
2729 I915_WRITE(reg
, temp
);
2731 /* enable CPU FDI TX and PCH FDI RX */
2732 reg
= FDI_TX_CTL(pipe
);
2733 temp
= I915_READ(reg
);
2734 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2735 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2736 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2737 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2738 temp
|= snb_b_fdi_train_param
[j
/2];
2739 temp
|= FDI_COMPOSITE_SYNC
;
2740 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2742 I915_WRITE(FDI_RX_MISC(pipe
),
2743 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2745 reg
= FDI_RX_CTL(pipe
);
2746 temp
= I915_READ(reg
);
2747 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2748 temp
|= FDI_COMPOSITE_SYNC
;
2749 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2752 udelay(1); /* should be 0.5us */
2754 for (i
= 0; i
< 4; i
++) {
2755 reg
= FDI_RX_IIR(pipe
);
2756 temp
= I915_READ(reg
);
2757 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2759 if (temp
& FDI_RX_BIT_LOCK
||
2760 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2761 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2762 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2766 udelay(1); /* should be 0.5us */
2769 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2774 reg
= FDI_TX_CTL(pipe
);
2775 temp
= I915_READ(reg
);
2776 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2777 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2778 I915_WRITE(reg
, temp
);
2780 reg
= FDI_RX_CTL(pipe
);
2781 temp
= I915_READ(reg
);
2782 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2783 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2784 I915_WRITE(reg
, temp
);
2787 udelay(2); /* should be 1.5us */
2789 for (i
= 0; i
< 4; i
++) {
2790 reg
= FDI_RX_IIR(pipe
);
2791 temp
= I915_READ(reg
);
2792 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2794 if (temp
& FDI_RX_SYMBOL_LOCK
||
2795 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2796 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2797 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2801 udelay(2); /* should be 1.5us */
2804 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2808 DRM_DEBUG_KMS("FDI train done.\n");
2811 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2813 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 int pipe
= intel_crtc
->pipe
;
2819 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820 reg
= FDI_RX_CTL(pipe
);
2821 temp
= I915_READ(reg
);
2822 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2823 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2824 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2825 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2830 /* Switch from Rawclk to PCDclk */
2831 temp
= I915_READ(reg
);
2832 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2837 /* Enable CPU FDI TX PLL, always on for Ironlake */
2838 reg
= FDI_TX_CTL(pipe
);
2839 temp
= I915_READ(reg
);
2840 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2841 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2848 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2850 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2852 int pipe
= intel_crtc
->pipe
;
2855 /* Switch from PCDclk to Rawclk */
2856 reg
= FDI_RX_CTL(pipe
);
2857 temp
= I915_READ(reg
);
2858 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2860 /* Disable CPU FDI TX PLL */
2861 reg
= FDI_TX_CTL(pipe
);
2862 temp
= I915_READ(reg
);
2863 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2868 reg
= FDI_RX_CTL(pipe
);
2869 temp
= I915_READ(reg
);
2870 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2872 /* Wait for the clocks to turn off. */
2877 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2879 struct drm_device
*dev
= crtc
->dev
;
2880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2881 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2882 int pipe
= intel_crtc
->pipe
;
2885 /* disable CPU FDI tx and PCH FDI rx */
2886 reg
= FDI_TX_CTL(pipe
);
2887 temp
= I915_READ(reg
);
2888 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2891 reg
= FDI_RX_CTL(pipe
);
2892 temp
= I915_READ(reg
);
2893 temp
&= ~(0x7 << 16);
2894 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2895 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2900 /* Ironlake workaround, disable clock pointer after downing FDI */
2901 if (HAS_PCH_IBX(dev
)) {
2902 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2905 /* still set train pattern 1 */
2906 reg
= FDI_TX_CTL(pipe
);
2907 temp
= I915_READ(reg
);
2908 temp
&= ~FDI_LINK_TRAIN_NONE
;
2909 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2910 I915_WRITE(reg
, temp
);
2912 reg
= FDI_RX_CTL(pipe
);
2913 temp
= I915_READ(reg
);
2914 if (HAS_PCH_CPT(dev
)) {
2915 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2916 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2918 temp
&= ~FDI_LINK_TRAIN_NONE
;
2919 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2921 /* BPC in FDI rx is consistent with that in PIPECONF */
2922 temp
&= ~(0x07 << 16);
2923 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2924 I915_WRITE(reg
, temp
);
2930 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2932 struct drm_device
*dev
= crtc
->dev
;
2933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2935 unsigned long flags
;
2938 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2939 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2942 spin_lock_irqsave(&dev
->event_lock
, flags
);
2943 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2944 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2949 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2951 struct drm_device
*dev
= crtc
->dev
;
2952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2954 if (crtc
->fb
== NULL
)
2957 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2959 wait_event(dev_priv
->pending_flip_queue
,
2960 !intel_crtc_has_pending_flip(crtc
));
2962 mutex_lock(&dev
->struct_mutex
);
2963 intel_finish_fb(crtc
->fb
);
2964 mutex_unlock(&dev
->struct_mutex
);
2967 /* Program iCLKIP clock to the desired frequency */
2968 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2970 struct drm_device
*dev
= crtc
->dev
;
2971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2972 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2973 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2976 mutex_lock(&dev_priv
->dpio_lock
);
2978 /* It is necessary to ungate the pixclk gate prior to programming
2979 * the divisors, and gate it back when it is done.
2981 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2983 /* Disable SSCCTL */
2984 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2985 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2989 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2990 if (clock
== 20000) {
2995 /* The iCLK virtual clock root frequency is in MHz,
2996 * but the adjusted_mode->crtc_clock in in KHz. To get the
2997 * divisors, it is necessary to divide one by another, so we
2998 * convert the virtual clock precision to KHz here for higher
3001 u32 iclk_virtual_root_freq
= 172800 * 1000;
3002 u32 iclk_pi_range
= 64;
3003 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3005 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3006 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3007 pi_value
= desired_divisor
% iclk_pi_range
;
3010 divsel
= msb_divisor_value
- 2;
3011 phaseinc
= pi_value
;
3014 /* This should not happen with any sane values */
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3016 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3017 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3018 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3020 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3027 /* Program SSCDIVINTPHASE6 */
3028 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3029 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3030 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3031 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3032 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3033 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3034 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3035 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3037 /* Program SSCAUXDIV */
3038 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3039 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3040 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3041 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3043 /* Enable modulator and associated divider */
3044 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3045 temp
&= ~SBI_SSCCTL_DISABLE
;
3046 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3048 /* Wait for initialization time */
3051 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3053 mutex_unlock(&dev_priv
->dpio_lock
);
3056 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3057 enum pipe pch_transcoder
)
3059 struct drm_device
*dev
= crtc
->base
.dev
;
3060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3063 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3064 I915_READ(HTOTAL(cpu_transcoder
)));
3065 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3066 I915_READ(HBLANK(cpu_transcoder
)));
3067 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3068 I915_READ(HSYNC(cpu_transcoder
)));
3070 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3071 I915_READ(VTOTAL(cpu_transcoder
)));
3072 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3073 I915_READ(VBLANK(cpu_transcoder
)));
3074 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3075 I915_READ(VSYNC(cpu_transcoder
)));
3076 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3077 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3081 * Enable PCH resources required for PCH ports:
3083 * - FDI training & RX/TX
3084 * - update transcoder timings
3085 * - DP transcoding bits
3088 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3090 struct drm_device
*dev
= crtc
->dev
;
3091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3092 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3093 int pipe
= intel_crtc
->pipe
;
3096 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3098 /* Write the TU size bits before fdi link training, so that error
3099 * detection works. */
3100 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3101 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3103 /* For PCH output, training FDI link */
3104 dev_priv
->display
.fdi_link_train(crtc
);
3106 /* We need to program the right clock selection before writing the pixel
3107 * mutliplier into the DPLL. */
3108 if (HAS_PCH_CPT(dev
)) {
3111 temp
= I915_READ(PCH_DPLL_SEL
);
3112 temp
|= TRANS_DPLL_ENABLE(pipe
);
3113 sel
= TRANS_DPLLB_SEL(pipe
);
3114 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3118 I915_WRITE(PCH_DPLL_SEL
, temp
);
3121 /* XXX: pch pll's can be enabled any time before we enable the PCH
3122 * transcoder, and we actually should do this to not upset any PCH
3123 * transcoder that already use the clock when we share it.
3125 * Note that enable_shared_dpll tries to do the right thing, but
3126 * get_shared_dpll unconditionally resets the pll - we need that to have
3127 * the right LVDS enable sequence. */
3128 ironlake_enable_shared_dpll(intel_crtc
);
3130 /* set transcoder timing, panel must allow it */
3131 assert_panel_unlocked(dev_priv
, pipe
);
3132 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3134 intel_fdi_normal_train(crtc
);
3136 /* For PCH DP, enable TRANS_DP_CTL */
3137 if (HAS_PCH_CPT(dev
) &&
3138 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3139 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3140 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3141 reg
= TRANS_DP_CTL(pipe
);
3142 temp
= I915_READ(reg
);
3143 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3144 TRANS_DP_SYNC_MASK
|
3146 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3147 TRANS_DP_ENH_FRAMING
);
3148 temp
|= bpc
<< 9; /* same format but at 11:9 */
3150 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3151 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3152 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3153 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3155 switch (intel_trans_dp_port_sel(crtc
)) {
3157 temp
|= TRANS_DP_PORT_SEL_B
;
3160 temp
|= TRANS_DP_PORT_SEL_C
;
3163 temp
|= TRANS_DP_PORT_SEL_D
;
3169 I915_WRITE(reg
, temp
);
3172 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3175 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3177 struct drm_device
*dev
= crtc
->dev
;
3178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3180 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3182 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3184 lpt_program_iclkip(crtc
);
3186 /* Set transcoder timing. */
3187 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3189 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3192 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3194 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3199 if (pll
->refcount
== 0) {
3200 WARN(1, "bad %s refcount\n", pll
->name
);
3204 if (--pll
->refcount
== 0) {
3206 WARN_ON(pll
->active
);
3209 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3212 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3214 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3215 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3216 enum intel_dpll_id i
;
3219 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3220 crtc
->base
.base
.id
, pll
->name
);
3221 intel_put_shared_dpll(crtc
);
3224 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3225 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3226 i
= (enum intel_dpll_id
) crtc
->pipe
;
3227 pll
= &dev_priv
->shared_dplls
[i
];
3229 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3230 crtc
->base
.base
.id
, pll
->name
);
3235 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3236 pll
= &dev_priv
->shared_dplls
[i
];
3238 /* Only want to check enabled timings first */
3239 if (pll
->refcount
== 0)
3242 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3243 sizeof(pll
->hw_state
)) == 0) {
3244 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3246 pll
->name
, pll
->refcount
, pll
->active
);
3252 /* Ok no matching timings, maybe there's a free one? */
3253 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3254 pll
= &dev_priv
->shared_dplls
[i
];
3255 if (pll
->refcount
== 0) {
3256 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3257 crtc
->base
.base
.id
, pll
->name
);
3265 crtc
->config
.shared_dpll
= i
;
3266 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3267 pipe_name(crtc
->pipe
));
3269 if (pll
->active
== 0) {
3270 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3271 sizeof(pll
->hw_state
));
3273 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3275 assert_shared_dpll_disabled(dev_priv
, pll
);
3277 pll
->mode_set(dev_priv
, pll
);
3284 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3287 int dslreg
= PIPEDSL(pipe
);
3290 temp
= I915_READ(dslreg
);
3292 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3293 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3294 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3298 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3300 struct drm_device
*dev
= crtc
->base
.dev
;
3301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3302 int pipe
= crtc
->pipe
;
3304 if (crtc
->config
.pch_pfit
.enabled
) {
3305 /* Force use of hard-coded filter coefficients
3306 * as some pre-programmed values are broken,
3309 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3310 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3311 PF_PIPE_SEL_IVB(pipe
));
3313 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3314 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3315 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3319 static void intel_enable_planes(struct drm_crtc
*crtc
)
3321 struct drm_device
*dev
= crtc
->dev
;
3322 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3323 struct intel_plane
*intel_plane
;
3325 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3326 if (intel_plane
->pipe
== pipe
)
3327 intel_plane_restore(&intel_plane
->base
);
3330 static void intel_disable_planes(struct drm_crtc
*crtc
)
3332 struct drm_device
*dev
= crtc
->dev
;
3333 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3334 struct intel_plane
*intel_plane
;
3336 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3337 if (intel_plane
->pipe
== pipe
)
3338 intel_plane_disable(&intel_plane
->base
);
3341 void hsw_enable_ips(struct intel_crtc
*crtc
)
3343 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3345 if (!crtc
->config
.ips_enabled
)
3348 /* We can only enable IPS after we enable a plane and wait for a vblank.
3349 * We guarantee that the plane is enabled by calling intel_enable_ips
3350 * only after intel_enable_plane. And intel_enable_plane already waits
3351 * for a vblank, so all we need to do here is to enable the IPS bit. */
3352 assert_plane_enabled(dev_priv
, crtc
->plane
);
3353 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3355 /* The bit only becomes 1 in the next vblank, so this wait here is
3356 * essentially intel_wait_for_vblank. If we don't have this and don't
3357 * wait for vblanks until the end of crtc_enable, then the HW state
3358 * readout code will complain that the expected IPS_CTL value is not the
3360 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3361 DRM_ERROR("Timed out waiting for IPS enable\n");
3364 void hsw_disable_ips(struct intel_crtc
*crtc
)
3366 struct drm_device
*dev
= crtc
->base
.dev
;
3367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 if (!crtc
->config
.ips_enabled
)
3372 assert_plane_enabled(dev_priv
, crtc
->plane
);
3373 I915_WRITE(IPS_CTL
, 0);
3374 POSTING_READ(IPS_CTL
);
3376 /* We need to wait for a vblank before we can disable the plane. */
3377 intel_wait_for_vblank(dev
, crtc
->pipe
);
3380 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3381 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3383 struct drm_device
*dev
= crtc
->dev
;
3384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3386 enum pipe pipe
= intel_crtc
->pipe
;
3387 int palreg
= PALETTE(pipe
);
3389 bool reenable_ips
= false;
3391 /* The clocks have to be on to load the palette. */
3392 if (!crtc
->enabled
|| !intel_crtc
->active
)
3395 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3396 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3397 assert_dsi_pll_enabled(dev_priv
);
3399 assert_pll_enabled(dev_priv
, pipe
);
3402 /* use legacy palette for Ironlake */
3403 if (HAS_PCH_SPLIT(dev
))
3404 palreg
= LGC_PALETTE(pipe
);
3406 /* Workaround : Do not read or write the pipe palette/gamma data while
3407 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3409 if (intel_crtc
->config
.ips_enabled
&&
3410 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3411 GAMMA_MODE_MODE_SPLIT
)) {
3412 hsw_disable_ips(intel_crtc
);
3413 reenable_ips
= true;
3416 for (i
= 0; i
< 256; i
++) {
3417 I915_WRITE(palreg
+ 4 * i
,
3418 (intel_crtc
->lut_r
[i
] << 16) |
3419 (intel_crtc
->lut_g
[i
] << 8) |
3420 intel_crtc
->lut_b
[i
]);
3424 hsw_enable_ips(intel_crtc
);
3427 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3429 struct drm_device
*dev
= crtc
->dev
;
3430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3431 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3432 struct intel_encoder
*encoder
;
3433 int pipe
= intel_crtc
->pipe
;
3434 int plane
= intel_crtc
->plane
;
3436 WARN_ON(!crtc
->enabled
);
3438 if (intel_crtc
->active
)
3441 intel_crtc
->active
= true;
3443 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3444 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3446 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3447 if (encoder
->pre_enable
)
3448 encoder
->pre_enable(encoder
);
3450 if (intel_crtc
->config
.has_pch_encoder
) {
3451 /* Note: FDI PLL enabling _must_ be done before we enable the
3452 * cpu pipes, hence this is separate from all the other fdi/pch
3454 ironlake_fdi_pll_enable(intel_crtc
);
3456 assert_fdi_tx_disabled(dev_priv
, pipe
);
3457 assert_fdi_rx_disabled(dev_priv
, pipe
);
3460 ironlake_pfit_enable(intel_crtc
);
3463 * On ILK+ LUT must be loaded before the pipe is running but with
3466 intel_crtc_load_lut(crtc
);
3468 intel_update_watermarks(crtc
);
3469 intel_enable_pipe(dev_priv
, pipe
,
3470 intel_crtc
->config
.has_pch_encoder
, false);
3471 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3472 intel_enable_planes(crtc
);
3473 intel_crtc_update_cursor(crtc
, true);
3475 if (intel_crtc
->config
.has_pch_encoder
)
3476 ironlake_pch_enable(crtc
);
3478 mutex_lock(&dev
->struct_mutex
);
3479 intel_update_fbc(dev
);
3480 mutex_unlock(&dev
->struct_mutex
);
3482 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3483 encoder
->enable(encoder
);
3485 if (HAS_PCH_CPT(dev
))
3486 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3489 * There seems to be a race in PCH platform hw (at least on some
3490 * outputs) where an enabled pipe still completes any pageflip right
3491 * away (as if the pipe is off) instead of waiting for vblank. As soon
3492 * as the first vblank happend, everything works as expected. Hence just
3493 * wait for one vblank before returning to avoid strange things
3496 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3499 /* IPS only exists on ULT machines and is tied to pipe A. */
3500 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3502 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3505 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3507 struct drm_device
*dev
= crtc
->dev
;
3508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3509 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3510 int pipe
= intel_crtc
->pipe
;
3511 int plane
= intel_crtc
->plane
;
3513 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3514 intel_enable_planes(crtc
);
3515 intel_crtc_update_cursor(crtc
, true);
3517 hsw_enable_ips(intel_crtc
);
3519 mutex_lock(&dev
->struct_mutex
);
3520 intel_update_fbc(dev
);
3521 mutex_unlock(&dev
->struct_mutex
);
3524 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3526 struct drm_device
*dev
= crtc
->dev
;
3527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3528 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3529 int pipe
= intel_crtc
->pipe
;
3530 int plane
= intel_crtc
->plane
;
3532 intel_crtc_wait_for_pending_flips(crtc
);
3533 drm_vblank_off(dev
, pipe
);
3535 /* FBC must be disabled before disabling the plane on HSW. */
3536 if (dev_priv
->fbc
.plane
== plane
)
3537 intel_disable_fbc(dev
);
3539 hsw_disable_ips(intel_crtc
);
3541 intel_crtc_update_cursor(crtc
, false);
3542 intel_disable_planes(crtc
);
3543 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3547 * This implements the workaround described in the "notes" section of the mode
3548 * set sequence documentation. When going from no pipes or single pipe to
3549 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3550 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3552 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3554 struct drm_device
*dev
= crtc
->base
.dev
;
3555 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3557 /* We want to get the other_active_crtc only if there's only 1 other
3559 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3560 if (!crtc_it
->active
|| crtc_it
== crtc
)
3563 if (other_active_crtc
)
3566 other_active_crtc
= crtc_it
;
3568 if (!other_active_crtc
)
3571 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3572 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3575 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3577 struct drm_device
*dev
= crtc
->dev
;
3578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3579 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3580 struct intel_encoder
*encoder
;
3581 int pipe
= intel_crtc
->pipe
;
3583 WARN_ON(!crtc
->enabled
);
3585 if (intel_crtc
->active
)
3588 intel_crtc
->active
= true;
3590 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3591 if (intel_crtc
->config
.has_pch_encoder
)
3592 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3594 if (intel_crtc
->config
.has_pch_encoder
)
3595 dev_priv
->display
.fdi_link_train(crtc
);
3597 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3598 if (encoder
->pre_enable
)
3599 encoder
->pre_enable(encoder
);
3601 intel_ddi_enable_pipe_clock(intel_crtc
);
3603 ironlake_pfit_enable(intel_crtc
);
3606 * On ILK+ LUT must be loaded before the pipe is running but with
3609 intel_crtc_load_lut(crtc
);
3611 intel_ddi_set_pipe_settings(crtc
);
3612 intel_ddi_enable_transcoder_func(crtc
);
3614 intel_update_watermarks(crtc
);
3615 intel_enable_pipe(dev_priv
, pipe
,
3616 intel_crtc
->config
.has_pch_encoder
, false);
3618 if (intel_crtc
->config
.has_pch_encoder
)
3619 lpt_pch_enable(crtc
);
3621 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3622 encoder
->enable(encoder
);
3623 intel_opregion_notify_encoder(encoder
, true);
3626 /* If we change the relative order between pipe/planes enabling, we need
3627 * to change the workaround. */
3628 haswell_mode_set_planes_workaround(intel_crtc
);
3629 haswell_crtc_enable_planes(crtc
);
3632 * There seems to be a race in PCH platform hw (at least on some
3633 * outputs) where an enabled pipe still completes any pageflip right
3634 * away (as if the pipe is off) instead of waiting for vblank. As soon
3635 * as the first vblank happend, everything works as expected. Hence just
3636 * wait for one vblank before returning to avoid strange things
3639 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3642 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3644 struct drm_device
*dev
= crtc
->base
.dev
;
3645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3646 int pipe
= crtc
->pipe
;
3648 /* To avoid upsetting the power well on haswell only disable the pfit if
3649 * it's in use. The hw state code will make sure we get this right. */
3650 if (crtc
->config
.pch_pfit
.enabled
) {
3651 I915_WRITE(PF_CTL(pipe
), 0);
3652 I915_WRITE(PF_WIN_POS(pipe
), 0);
3653 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3657 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3659 struct drm_device
*dev
= crtc
->dev
;
3660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3662 struct intel_encoder
*encoder
;
3663 int pipe
= intel_crtc
->pipe
;
3664 int plane
= intel_crtc
->plane
;
3668 if (!intel_crtc
->active
)
3671 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3672 encoder
->disable(encoder
);
3674 intel_crtc_wait_for_pending_flips(crtc
);
3675 drm_vblank_off(dev
, pipe
);
3677 if (dev_priv
->fbc
.plane
== plane
)
3678 intel_disable_fbc(dev
);
3680 intel_crtc_update_cursor(crtc
, false);
3681 intel_disable_planes(crtc
);
3682 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3684 if (intel_crtc
->config
.has_pch_encoder
)
3685 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3687 intel_disable_pipe(dev_priv
, pipe
);
3689 ironlake_pfit_disable(intel_crtc
);
3691 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3692 if (encoder
->post_disable
)
3693 encoder
->post_disable(encoder
);
3695 if (intel_crtc
->config
.has_pch_encoder
) {
3696 ironlake_fdi_disable(crtc
);
3698 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3699 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3701 if (HAS_PCH_CPT(dev
)) {
3702 /* disable TRANS_DP_CTL */
3703 reg
= TRANS_DP_CTL(pipe
);
3704 temp
= I915_READ(reg
);
3705 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3706 TRANS_DP_PORT_SEL_MASK
);
3707 temp
|= TRANS_DP_PORT_SEL_NONE
;
3708 I915_WRITE(reg
, temp
);
3710 /* disable DPLL_SEL */
3711 temp
= I915_READ(PCH_DPLL_SEL
);
3712 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3713 I915_WRITE(PCH_DPLL_SEL
, temp
);
3716 /* disable PCH DPLL */
3717 intel_disable_shared_dpll(intel_crtc
);
3719 ironlake_fdi_pll_disable(intel_crtc
);
3722 intel_crtc
->active
= false;
3723 intel_update_watermarks(crtc
);
3725 mutex_lock(&dev
->struct_mutex
);
3726 intel_update_fbc(dev
);
3727 mutex_unlock(&dev
->struct_mutex
);
3730 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3732 struct drm_device
*dev
= crtc
->dev
;
3733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3734 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3735 struct intel_encoder
*encoder
;
3736 int pipe
= intel_crtc
->pipe
;
3737 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3739 if (!intel_crtc
->active
)
3742 haswell_crtc_disable_planes(crtc
);
3744 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3745 intel_opregion_notify_encoder(encoder
, false);
3746 encoder
->disable(encoder
);
3749 if (intel_crtc
->config
.has_pch_encoder
)
3750 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3751 intel_disable_pipe(dev_priv
, pipe
);
3753 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3755 ironlake_pfit_disable(intel_crtc
);
3757 intel_ddi_disable_pipe_clock(intel_crtc
);
3759 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3760 if (encoder
->post_disable
)
3761 encoder
->post_disable(encoder
);
3763 if (intel_crtc
->config
.has_pch_encoder
) {
3764 lpt_disable_pch_transcoder(dev_priv
);
3765 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3766 intel_ddi_fdi_disable(crtc
);
3769 intel_crtc
->active
= false;
3770 intel_update_watermarks(crtc
);
3772 mutex_lock(&dev
->struct_mutex
);
3773 intel_update_fbc(dev
);
3774 mutex_unlock(&dev
->struct_mutex
);
3777 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3779 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3780 intel_put_shared_dpll(intel_crtc
);
3783 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3785 intel_ddi_put_crtc_pll(crtc
);
3788 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3790 if (!enable
&& intel_crtc
->overlay
) {
3791 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3794 mutex_lock(&dev
->struct_mutex
);
3795 dev_priv
->mm
.interruptible
= false;
3796 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3797 dev_priv
->mm
.interruptible
= true;
3798 mutex_unlock(&dev
->struct_mutex
);
3801 /* Let userspace switch the overlay on again. In most cases userspace
3802 * has to recompute where to put it anyway.
3807 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3808 * cursor plane briefly if not already running after enabling the display
3810 * This workaround avoids occasional blank screens when self refresh is
3814 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3816 u32 cntl
= I915_READ(CURCNTR(pipe
));
3818 if ((cntl
& CURSOR_MODE
) == 0) {
3819 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3821 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3822 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3823 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3824 I915_WRITE(CURCNTR(pipe
), cntl
);
3825 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3826 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3830 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3832 struct drm_device
*dev
= crtc
->base
.dev
;
3833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3834 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3836 if (!crtc
->config
.gmch_pfit
.control
)
3840 * The panel fitter should only be adjusted whilst the pipe is disabled,
3841 * according to register description and PRM.
3843 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3844 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3846 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3847 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3849 /* Border color in case we don't scale up to the full screen. Black by
3850 * default, change to something else for debugging. */
3851 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3854 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3856 struct drm_device
*dev
= crtc
->dev
;
3857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3859 struct intel_encoder
*encoder
;
3860 int pipe
= intel_crtc
->pipe
;
3861 int plane
= intel_crtc
->plane
;
3864 WARN_ON(!crtc
->enabled
);
3866 if (intel_crtc
->active
)
3869 intel_crtc
->active
= true;
3871 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3872 if (encoder
->pre_pll_enable
)
3873 encoder
->pre_pll_enable(encoder
);
3875 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3878 vlv_enable_pll(intel_crtc
);
3880 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3881 if (encoder
->pre_enable
)
3882 encoder
->pre_enable(encoder
);
3884 i9xx_pfit_enable(intel_crtc
);
3886 intel_crtc_load_lut(crtc
);
3888 intel_update_watermarks(crtc
);
3889 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3890 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3891 intel_enable_planes(crtc
);
3892 intel_crtc_update_cursor(crtc
, true);
3894 intel_update_fbc(dev
);
3896 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3897 encoder
->enable(encoder
);
3900 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3902 struct drm_device
*dev
= crtc
->dev
;
3903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3904 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3905 struct intel_encoder
*encoder
;
3906 int pipe
= intel_crtc
->pipe
;
3907 int plane
= intel_crtc
->plane
;
3909 WARN_ON(!crtc
->enabled
);
3911 if (intel_crtc
->active
)
3914 intel_crtc
->active
= true;
3916 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3917 if (encoder
->pre_enable
)
3918 encoder
->pre_enable(encoder
);
3920 i9xx_enable_pll(intel_crtc
);
3922 i9xx_pfit_enable(intel_crtc
);
3924 intel_crtc_load_lut(crtc
);
3926 intel_update_watermarks(crtc
);
3927 intel_enable_pipe(dev_priv
, pipe
, false, false);
3928 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3929 intel_enable_planes(crtc
);
3930 /* The fixup needs to happen before cursor is enabled */
3932 g4x_fixup_plane(dev_priv
, pipe
);
3933 intel_crtc_update_cursor(crtc
, true);
3935 /* Give the overlay scaler a chance to enable if it's on this pipe */
3936 intel_crtc_dpms_overlay(intel_crtc
, true);
3938 intel_update_fbc(dev
);
3940 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3941 encoder
->enable(encoder
);
3944 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3946 struct drm_device
*dev
= crtc
->base
.dev
;
3947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3949 if (!crtc
->config
.gmch_pfit
.control
)
3952 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3954 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3955 I915_READ(PFIT_CONTROL
));
3956 I915_WRITE(PFIT_CONTROL
, 0);
3959 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3961 struct drm_device
*dev
= crtc
->dev
;
3962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3964 struct intel_encoder
*encoder
;
3965 int pipe
= intel_crtc
->pipe
;
3966 int plane
= intel_crtc
->plane
;
3968 if (!intel_crtc
->active
)
3971 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3972 encoder
->disable(encoder
);
3974 /* Give the overlay scaler a chance to disable if it's on this pipe */
3975 intel_crtc_wait_for_pending_flips(crtc
);
3976 drm_vblank_off(dev
, pipe
);
3978 if (dev_priv
->fbc
.plane
== plane
)
3979 intel_disable_fbc(dev
);
3981 intel_crtc_dpms_overlay(intel_crtc
, false);
3982 intel_crtc_update_cursor(crtc
, false);
3983 intel_disable_planes(crtc
);
3984 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3986 intel_disable_pipe(dev_priv
, pipe
);
3988 i9xx_pfit_disable(intel_crtc
);
3990 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3991 if (encoder
->post_disable
)
3992 encoder
->post_disable(encoder
);
3994 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3995 vlv_disable_pll(dev_priv
, pipe
);
3996 else if (!IS_VALLEYVIEW(dev
))
3997 i9xx_disable_pll(dev_priv
, pipe
);
3999 intel_crtc
->active
= false;
4000 intel_update_watermarks(crtc
);
4002 intel_update_fbc(dev
);
4005 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4009 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4012 struct drm_device
*dev
= crtc
->dev
;
4013 struct drm_i915_master_private
*master_priv
;
4014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4015 int pipe
= intel_crtc
->pipe
;
4017 if (!dev
->primary
->master
)
4020 master_priv
= dev
->primary
->master
->driver_priv
;
4021 if (!master_priv
->sarea_priv
)
4026 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4027 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4030 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4031 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4034 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4040 * Sets the power management mode of the pipe and plane.
4042 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4044 struct drm_device
*dev
= crtc
->dev
;
4045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4046 struct intel_encoder
*intel_encoder
;
4047 bool enable
= false;
4049 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4050 enable
|= intel_encoder
->connectors_active
;
4053 dev_priv
->display
.crtc_enable(crtc
);
4055 dev_priv
->display
.crtc_disable(crtc
);
4057 intel_crtc_update_sarea(crtc
, enable
);
4060 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4062 struct drm_device
*dev
= crtc
->dev
;
4063 struct drm_connector
*connector
;
4064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4067 /* crtc should still be enabled when we disable it. */
4068 WARN_ON(!crtc
->enabled
);
4070 dev_priv
->display
.crtc_disable(crtc
);
4071 intel_crtc
->eld_vld
= false;
4072 intel_crtc_update_sarea(crtc
, false);
4073 dev_priv
->display
.off(crtc
);
4075 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4076 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4077 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4080 mutex_lock(&dev
->struct_mutex
);
4081 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4082 mutex_unlock(&dev
->struct_mutex
);
4086 /* Update computed state. */
4087 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4088 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4091 if (connector
->encoder
->crtc
!= crtc
)
4094 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4095 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4099 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4101 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4103 drm_encoder_cleanup(encoder
);
4104 kfree(intel_encoder
);
4107 /* Simple dpms helper for encoders with just one connector, no cloning and only
4108 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4109 * state of the entire output pipe. */
4110 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4112 if (mode
== DRM_MODE_DPMS_ON
) {
4113 encoder
->connectors_active
= true;
4115 intel_crtc_update_dpms(encoder
->base
.crtc
);
4117 encoder
->connectors_active
= false;
4119 intel_crtc_update_dpms(encoder
->base
.crtc
);
4123 /* Cross check the actual hw state with our own modeset state tracking (and it's
4124 * internal consistency). */
4125 static void intel_connector_check_state(struct intel_connector
*connector
)
4127 if (connector
->get_hw_state(connector
)) {
4128 struct intel_encoder
*encoder
= connector
->encoder
;
4129 struct drm_crtc
*crtc
;
4130 bool encoder_enabled
;
4133 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4134 connector
->base
.base
.id
,
4135 drm_get_connector_name(&connector
->base
));
4137 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4138 "wrong connector dpms state\n");
4139 WARN(connector
->base
.encoder
!= &encoder
->base
,
4140 "active connector not linked to encoder\n");
4141 WARN(!encoder
->connectors_active
,
4142 "encoder->connectors_active not set\n");
4144 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4145 WARN(!encoder_enabled
, "encoder not enabled\n");
4146 if (WARN_ON(!encoder
->base
.crtc
))
4149 crtc
= encoder
->base
.crtc
;
4151 WARN(!crtc
->enabled
, "crtc not enabled\n");
4152 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4153 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4154 "encoder active on the wrong pipe\n");
4158 /* Even simpler default implementation, if there's really no special case to
4160 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4162 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4164 /* All the simple cases only support two dpms states. */
4165 if (mode
!= DRM_MODE_DPMS_ON
)
4166 mode
= DRM_MODE_DPMS_OFF
;
4168 if (mode
== connector
->dpms
)
4171 connector
->dpms
= mode
;
4173 /* Only need to change hw state when actually enabled */
4174 if (encoder
->base
.crtc
)
4175 intel_encoder_dpms(encoder
, mode
);
4177 WARN_ON(encoder
->connectors_active
!= false);
4179 intel_modeset_check_state(connector
->dev
);
4182 /* Simple connector->get_hw_state implementation for encoders that support only
4183 * one connector and no cloning and hence the encoder state determines the state
4184 * of the connector. */
4185 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4188 struct intel_encoder
*encoder
= connector
->encoder
;
4190 return encoder
->get_hw_state(encoder
, &pipe
);
4193 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4194 struct intel_crtc_config
*pipe_config
)
4196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4197 struct intel_crtc
*pipe_B_crtc
=
4198 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4200 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4201 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4202 if (pipe_config
->fdi_lanes
> 4) {
4203 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4204 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4208 if (IS_HASWELL(dev
)) {
4209 if (pipe_config
->fdi_lanes
> 2) {
4210 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4211 pipe_config
->fdi_lanes
);
4218 if (INTEL_INFO(dev
)->num_pipes
== 2)
4221 /* Ivybridge 3 pipe is really complicated */
4226 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4227 pipe_config
->fdi_lanes
> 2) {
4228 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4229 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4234 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4235 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4236 if (pipe_config
->fdi_lanes
> 2) {
4237 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4238 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4242 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4252 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4253 struct intel_crtc_config
*pipe_config
)
4255 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4256 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4257 int lane
, link_bw
, fdi_dotclock
;
4258 bool setup_ok
, needs_recompute
= false;
4261 /* FDI is a binary signal running at ~2.7GHz, encoding
4262 * each output octet as 10 bits. The actual frequency
4263 * is stored as a divider into a 100MHz clock, and the
4264 * mode pixel clock is stored in units of 1KHz.
4265 * Hence the bw of each lane in terms of the mode signal
4268 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4270 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4272 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4273 pipe_config
->pipe_bpp
);
4275 pipe_config
->fdi_lanes
= lane
;
4277 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4278 link_bw
, &pipe_config
->fdi_m_n
);
4280 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4281 intel_crtc
->pipe
, pipe_config
);
4282 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4283 pipe_config
->pipe_bpp
-= 2*3;
4284 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4285 pipe_config
->pipe_bpp
);
4286 needs_recompute
= true;
4287 pipe_config
->bw_constrained
= true;
4292 if (needs_recompute
)
4295 return setup_ok
? 0 : -EINVAL
;
4298 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4299 struct intel_crtc_config
*pipe_config
)
4301 pipe_config
->ips_enabled
= i915_enable_ips
&&
4302 hsw_crtc_supports_ips(crtc
) &&
4303 pipe_config
->pipe_bpp
<= 24;
4306 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4307 struct intel_crtc_config
*pipe_config
)
4309 struct drm_device
*dev
= crtc
->base
.dev
;
4310 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4312 /* FIXME should check pixel clock limits on all platforms */
4313 if (INTEL_INFO(dev
)->gen
< 4) {
4314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4316 dev_priv
->display
.get_display_clock_speed(dev
);
4319 * Enable pixel doubling when the dot clock
4320 * is > 90% of the (display) core speed.
4322 * GDG double wide on either pipe,
4323 * otherwise pipe A only.
4325 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4326 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4328 pipe_config
->double_wide
= true;
4331 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4336 * Pipe horizontal size must be even in:
4338 * - LVDS dual channel mode
4339 * - Double wide pipe
4341 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4342 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4343 pipe_config
->pipe_src_w
&= ~1;
4345 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4346 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4348 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4349 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4352 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4353 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4354 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4355 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4357 pipe_config
->pipe_bpp
= 8*3;
4361 hsw_compute_ips_config(crtc
, pipe_config
);
4363 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4364 * clock survives for now. */
4365 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4366 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4368 if (pipe_config
->has_pch_encoder
)
4369 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4374 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4376 return 400000; /* FIXME */
4379 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4384 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4389 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4394 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4398 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4400 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4401 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4403 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4405 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4407 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4410 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4411 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4413 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4418 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4422 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4424 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4427 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4428 case GC_DISPLAY_CLOCK_333_MHZ
:
4431 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4437 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4442 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4445 /* Assume that the hardware is in the high speed state. This
4446 * should be the default.
4448 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4449 case GC_CLOCK_133_200
:
4450 case GC_CLOCK_100_200
:
4452 case GC_CLOCK_166_250
:
4454 case GC_CLOCK_100_133
:
4458 /* Shouldn't happen */
4462 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4468 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4470 while (*num
> DATA_LINK_M_N_MASK
||
4471 *den
> DATA_LINK_M_N_MASK
) {
4477 static void compute_m_n(unsigned int m
, unsigned int n
,
4478 uint32_t *ret_m
, uint32_t *ret_n
)
4480 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4481 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4482 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4486 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4487 int pixel_clock
, int link_clock
,
4488 struct intel_link_m_n
*m_n
)
4492 compute_m_n(bits_per_pixel
* pixel_clock
,
4493 link_clock
* nlanes
* 8,
4494 &m_n
->gmch_m
, &m_n
->gmch_n
);
4496 compute_m_n(pixel_clock
, link_clock
,
4497 &m_n
->link_m
, &m_n
->link_n
);
4500 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4502 if (i915_panel_use_ssc
>= 0)
4503 return i915_panel_use_ssc
!= 0;
4504 return dev_priv
->vbt
.lvds_use_ssc
4505 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4508 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4510 struct drm_device
*dev
= crtc
->dev
;
4511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4514 if (IS_VALLEYVIEW(dev
)) {
4516 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4517 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4518 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4519 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4521 } else if (!IS_GEN2(dev
)) {
4530 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4532 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4535 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4537 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4540 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4541 intel_clock_t
*reduced_clock
)
4543 struct drm_device
*dev
= crtc
->base
.dev
;
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4545 int pipe
= crtc
->pipe
;
4548 if (IS_PINEVIEW(dev
)) {
4549 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4551 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4553 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4555 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4558 I915_WRITE(FP0(pipe
), fp
);
4559 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4561 crtc
->lowfreq_avail
= false;
4562 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4563 reduced_clock
&& i915_powersave
) {
4564 I915_WRITE(FP1(pipe
), fp2
);
4565 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4566 crtc
->lowfreq_avail
= true;
4568 I915_WRITE(FP1(pipe
), fp
);
4569 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4573 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4579 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4580 * and set it to a reasonable value instead.
4582 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4583 reg_val
&= 0xffffff00;
4584 reg_val
|= 0x00000030;
4585 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4587 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4588 reg_val
&= 0x8cffffff;
4589 reg_val
= 0x8c000000;
4590 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4592 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4593 reg_val
&= 0xffffff00;
4594 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4596 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4597 reg_val
&= 0x00ffffff;
4598 reg_val
|= 0xb0000000;
4599 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4602 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4603 struct intel_link_m_n
*m_n
)
4605 struct drm_device
*dev
= crtc
->base
.dev
;
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 int pipe
= crtc
->pipe
;
4609 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4610 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4611 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4612 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4615 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4616 struct intel_link_m_n
*m_n
)
4618 struct drm_device
*dev
= crtc
->base
.dev
;
4619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4620 int pipe
= crtc
->pipe
;
4621 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4623 if (INTEL_INFO(dev
)->gen
>= 5) {
4624 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4625 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4626 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4627 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4629 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4630 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4631 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4632 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4636 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4638 if (crtc
->config
.has_pch_encoder
)
4639 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4641 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4644 static void vlv_update_pll(struct intel_crtc
*crtc
)
4646 struct drm_device
*dev
= crtc
->base
.dev
;
4647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4648 int pipe
= crtc
->pipe
;
4650 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4651 u32 coreclk
, reg_val
, dpll_md
;
4653 mutex_lock(&dev_priv
->dpio_lock
);
4655 bestn
= crtc
->config
.dpll
.n
;
4656 bestm1
= crtc
->config
.dpll
.m1
;
4657 bestm2
= crtc
->config
.dpll
.m2
;
4658 bestp1
= crtc
->config
.dpll
.p1
;
4659 bestp2
= crtc
->config
.dpll
.p2
;
4661 /* See eDP HDMI DPIO driver vbios notes doc */
4663 /* PLL B needs special handling */
4665 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4667 /* Set up Tx target for periodic Rcomp update */
4668 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4670 /* Disable target IRef on PLL */
4671 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4672 reg_val
&= 0x00ffffff;
4673 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4675 /* Disable fast lock */
4676 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4678 /* Set idtafcrecal before PLL is enabled */
4679 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4680 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4681 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4682 mdiv
|= (1 << DPIO_K_SHIFT
);
4685 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4686 * but we don't support that).
4687 * Note: don't use the DAC post divider as it seems unstable.
4689 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4690 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4692 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4693 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4695 /* Set HBR and RBR LPF coefficients */
4696 if (crtc
->config
.port_clock
== 162000 ||
4697 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4698 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4699 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4702 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4705 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4706 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4707 /* Use SSC source */
4709 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4712 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4714 } else { /* HDMI or VGA */
4715 /* Use bend source */
4717 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4720 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4724 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4725 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4726 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4727 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4728 coreclk
|= 0x01000000;
4729 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4731 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4733 /* Enable DPIO clock input */
4734 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4735 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4736 /* We should never disable this, set it here for state tracking */
4738 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4739 dpll
|= DPLL_VCO_ENABLE
;
4740 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4742 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4743 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4744 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4746 if (crtc
->config
.has_dp_encoder
)
4747 intel_dp_set_m_n(crtc
);
4749 mutex_unlock(&dev_priv
->dpio_lock
);
4752 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4753 intel_clock_t
*reduced_clock
,
4756 struct drm_device
*dev
= crtc
->base
.dev
;
4757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4760 struct dpll
*clock
= &crtc
->config
.dpll
;
4762 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4764 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4765 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4767 dpll
= DPLL_VGA_MODE_DIS
;
4769 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4770 dpll
|= DPLLB_MODE_LVDS
;
4772 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4774 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4775 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4776 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4780 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4782 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4783 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4785 /* compute bitmask from p1 value */
4786 if (IS_PINEVIEW(dev
))
4787 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4789 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4790 if (IS_G4X(dev
) && reduced_clock
)
4791 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4793 switch (clock
->p2
) {
4795 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4798 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4801 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4804 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4807 if (INTEL_INFO(dev
)->gen
>= 4)
4808 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4810 if (crtc
->config
.sdvo_tv_clock
)
4811 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4812 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4813 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4814 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4816 dpll
|= PLL_REF_INPUT_DREFCLK
;
4818 dpll
|= DPLL_VCO_ENABLE
;
4819 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4821 if (INTEL_INFO(dev
)->gen
>= 4) {
4822 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4823 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4824 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4827 if (crtc
->config
.has_dp_encoder
)
4828 intel_dp_set_m_n(crtc
);
4831 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4832 intel_clock_t
*reduced_clock
,
4835 struct drm_device
*dev
= crtc
->base
.dev
;
4836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4838 struct dpll
*clock
= &crtc
->config
.dpll
;
4840 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4842 dpll
= DPLL_VGA_MODE_DIS
;
4844 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4845 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4848 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4850 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4852 dpll
|= PLL_P2_DIVIDE_BY_4
;
4855 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4856 dpll
|= DPLL_DVO_2X_MODE
;
4858 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4859 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4860 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4862 dpll
|= PLL_REF_INPUT_DREFCLK
;
4864 dpll
|= DPLL_VCO_ENABLE
;
4865 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4868 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4870 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4872 enum pipe pipe
= intel_crtc
->pipe
;
4873 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4874 struct drm_display_mode
*adjusted_mode
=
4875 &intel_crtc
->config
.adjusted_mode
;
4876 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4878 /* We need to be careful not to changed the adjusted mode, for otherwise
4879 * the hw state checker will get angry at the mismatch. */
4880 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4881 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4883 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4884 /* the chip adds 2 halflines automatically */
4886 crtc_vblank_end
-= 1;
4887 vsyncshift
= adjusted_mode
->crtc_hsync_start
4888 - adjusted_mode
->crtc_htotal
/ 2;
4893 if (INTEL_INFO(dev
)->gen
> 3)
4894 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4896 I915_WRITE(HTOTAL(cpu_transcoder
),
4897 (adjusted_mode
->crtc_hdisplay
- 1) |
4898 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4899 I915_WRITE(HBLANK(cpu_transcoder
),
4900 (adjusted_mode
->crtc_hblank_start
- 1) |
4901 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4902 I915_WRITE(HSYNC(cpu_transcoder
),
4903 (adjusted_mode
->crtc_hsync_start
- 1) |
4904 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4906 I915_WRITE(VTOTAL(cpu_transcoder
),
4907 (adjusted_mode
->crtc_vdisplay
- 1) |
4908 ((crtc_vtotal
- 1) << 16));
4909 I915_WRITE(VBLANK(cpu_transcoder
),
4910 (adjusted_mode
->crtc_vblank_start
- 1) |
4911 ((crtc_vblank_end
- 1) << 16));
4912 I915_WRITE(VSYNC(cpu_transcoder
),
4913 (adjusted_mode
->crtc_vsync_start
- 1) |
4914 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4916 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4917 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4918 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4920 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4921 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4922 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4924 /* pipesrc controls the size that is scaled from, which should
4925 * always be the user's requested size.
4927 I915_WRITE(PIPESRC(pipe
),
4928 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4929 (intel_crtc
->config
.pipe_src_h
- 1));
4932 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4933 struct intel_crtc_config
*pipe_config
)
4935 struct drm_device
*dev
= crtc
->base
.dev
;
4936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4937 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4940 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4941 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4942 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4943 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4944 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4945 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4946 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4947 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4948 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4950 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4951 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4952 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4953 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4954 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4955 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4956 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4957 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4958 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4960 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4961 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4962 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4963 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4966 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4967 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4968 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4970 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4971 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4974 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4975 struct intel_crtc_config
*pipe_config
)
4977 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4979 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4980 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4981 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4982 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4984 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4985 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4986 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4987 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4989 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4991 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
4992 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4995 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4997 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5004 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5005 pipeconf
|= PIPECONF_ENABLE
;
5007 if (intel_crtc
->config
.double_wide
)
5008 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5010 /* only g4x and later have fancy bpc/dither controls */
5011 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5012 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5013 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5014 pipeconf
|= PIPECONF_DITHER_EN
|
5015 PIPECONF_DITHER_TYPE_SP
;
5017 switch (intel_crtc
->config
.pipe_bpp
) {
5019 pipeconf
|= PIPECONF_6BPC
;
5022 pipeconf
|= PIPECONF_8BPC
;
5025 pipeconf
|= PIPECONF_10BPC
;
5028 /* Case prevented by intel_choose_pipe_bpp_dither. */
5033 if (HAS_PIPE_CXSR(dev
)) {
5034 if (intel_crtc
->lowfreq_avail
) {
5035 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5036 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5038 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5042 if (!IS_GEN2(dev
) &&
5043 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5044 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5046 pipeconf
|= PIPECONF_PROGRESSIVE
;
5048 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5049 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5051 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5052 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5055 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5057 struct drm_framebuffer
*fb
)
5059 struct drm_device
*dev
= crtc
->dev
;
5060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5062 int pipe
= intel_crtc
->pipe
;
5063 int plane
= intel_crtc
->plane
;
5064 int refclk
, num_connectors
= 0;
5065 intel_clock_t clock
, reduced_clock
;
5067 bool ok
, has_reduced_clock
= false;
5068 bool is_lvds
= false, is_dsi
= false;
5069 struct intel_encoder
*encoder
;
5070 const intel_limit_t
*limit
;
5073 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5074 switch (encoder
->type
) {
5075 case INTEL_OUTPUT_LVDS
:
5078 case INTEL_OUTPUT_DSI
:
5089 if (!intel_crtc
->config
.clock_set
) {
5090 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5093 * Returns a set of divisors for the desired target clock with
5094 * the given refclk, or FALSE. The returned values represent
5095 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5098 limit
= intel_limit(crtc
, refclk
);
5099 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5100 intel_crtc
->config
.port_clock
,
5101 refclk
, NULL
, &clock
);
5103 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5107 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5109 * Ensure we match the reduced clock's P to the target
5110 * clock. If the clocks don't match, we can't switch
5111 * the display clock by using the FP0/FP1. In such case
5112 * we will disable the LVDS downclock feature.
5115 dev_priv
->display
.find_dpll(limit
, crtc
,
5116 dev_priv
->lvds_downclock
,
5120 /* Compat-code for transition, will disappear. */
5121 intel_crtc
->config
.dpll
.n
= clock
.n
;
5122 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5123 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5124 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5125 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5129 i8xx_update_pll(intel_crtc
,
5130 has_reduced_clock
? &reduced_clock
: NULL
,
5132 } else if (IS_VALLEYVIEW(dev
)) {
5133 vlv_update_pll(intel_crtc
);
5135 i9xx_update_pll(intel_crtc
,
5136 has_reduced_clock
? &reduced_clock
: NULL
,
5141 /* Set up the display plane register */
5142 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5144 if (!IS_VALLEYVIEW(dev
)) {
5146 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5148 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5151 intel_set_pipe_timings(intel_crtc
);
5153 /* pipesrc and dspsize control the size that is scaled from,
5154 * which should always be the user's requested size.
5156 I915_WRITE(DSPSIZE(plane
),
5157 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5158 (intel_crtc
->config
.pipe_src_w
- 1));
5159 I915_WRITE(DSPPOS(plane
), 0);
5161 i9xx_set_pipeconf(intel_crtc
);
5163 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5164 POSTING_READ(DSPCNTR(plane
));
5166 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5171 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5172 struct intel_crtc_config
*pipe_config
)
5174 struct drm_device
*dev
= crtc
->base
.dev
;
5175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5178 tmp
= I915_READ(PFIT_CONTROL
);
5179 if (!(tmp
& PFIT_ENABLE
))
5182 /* Check whether the pfit is attached to our pipe. */
5183 if (INTEL_INFO(dev
)->gen
< 4) {
5184 if (crtc
->pipe
!= PIPE_B
)
5187 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5191 pipe_config
->gmch_pfit
.control
= tmp
;
5192 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5193 if (INTEL_INFO(dev
)->gen
< 5)
5194 pipe_config
->gmch_pfit
.lvds_border_bits
=
5195 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5198 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5199 struct intel_crtc_config
*pipe_config
)
5201 struct drm_device
*dev
= crtc
->base
.dev
;
5202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5203 int pipe
= pipe_config
->cpu_transcoder
;
5204 intel_clock_t clock
;
5206 int refclk
= 100000;
5208 mutex_lock(&dev_priv
->dpio_lock
);
5209 mdiv
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DIV(pipe
));
5210 mutex_unlock(&dev_priv
->dpio_lock
);
5212 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5213 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5214 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5215 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5216 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5218 vlv_clock(refclk
, &clock
);
5220 /* clock.dot is the fast clock */
5221 pipe_config
->port_clock
= clock
.dot
/ 5;
5224 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5225 struct intel_crtc_config
*pipe_config
)
5227 struct drm_device
*dev
= crtc
->base
.dev
;
5228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5231 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5232 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5234 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5235 if (!(tmp
& PIPECONF_ENABLE
))
5238 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5239 switch (tmp
& PIPECONF_BPC_MASK
) {
5241 pipe_config
->pipe_bpp
= 18;
5244 pipe_config
->pipe_bpp
= 24;
5246 case PIPECONF_10BPC
:
5247 pipe_config
->pipe_bpp
= 30;
5254 if (INTEL_INFO(dev
)->gen
< 4)
5255 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5257 intel_get_pipe_timings(crtc
, pipe_config
);
5259 i9xx_get_pfit_config(crtc
, pipe_config
);
5261 if (INTEL_INFO(dev
)->gen
>= 4) {
5262 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5263 pipe_config
->pixel_multiplier
=
5264 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5265 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5266 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5267 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5268 tmp
= I915_READ(DPLL(crtc
->pipe
));
5269 pipe_config
->pixel_multiplier
=
5270 ((tmp
& SDVO_MULTIPLIER_MASK
)
5271 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5273 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5274 * port and will be fixed up in the encoder->get_config
5276 pipe_config
->pixel_multiplier
= 1;
5278 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5279 if (!IS_VALLEYVIEW(dev
)) {
5280 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5281 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5283 /* Mask out read-only status bits. */
5284 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5285 DPLL_PORTC_READY_MASK
|
5286 DPLL_PORTB_READY_MASK
);
5289 if (IS_VALLEYVIEW(dev
))
5290 vlv_crtc_clock_get(crtc
, pipe_config
);
5292 i9xx_crtc_clock_get(crtc
, pipe_config
);
5297 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5300 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5301 struct intel_encoder
*encoder
;
5303 bool has_lvds
= false;
5304 bool has_cpu_edp
= false;
5305 bool has_panel
= false;
5306 bool has_ck505
= false;
5307 bool can_ssc
= false;
5309 /* We need to take the global config into account */
5310 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5312 switch (encoder
->type
) {
5313 case INTEL_OUTPUT_LVDS
:
5317 case INTEL_OUTPUT_EDP
:
5319 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5325 if (HAS_PCH_IBX(dev
)) {
5326 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5327 can_ssc
= has_ck505
;
5333 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5334 has_panel
, has_lvds
, has_ck505
);
5336 /* Ironlake: try to setup display ref clock before DPLL
5337 * enabling. This is only under driver's control after
5338 * PCH B stepping, previous chipset stepping should be
5339 * ignoring this setting.
5341 val
= I915_READ(PCH_DREF_CONTROL
);
5343 /* As we must carefully and slowly disable/enable each source in turn,
5344 * compute the final state we want first and check if we need to
5345 * make any changes at all.
5348 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5350 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5352 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5354 final
&= ~DREF_SSC_SOURCE_MASK
;
5355 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5356 final
&= ~DREF_SSC1_ENABLE
;
5359 final
|= DREF_SSC_SOURCE_ENABLE
;
5361 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5362 final
|= DREF_SSC1_ENABLE
;
5365 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5366 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5368 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5370 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5372 final
|= DREF_SSC_SOURCE_DISABLE
;
5373 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5379 /* Always enable nonspread source */
5380 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5383 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5385 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5388 val
&= ~DREF_SSC_SOURCE_MASK
;
5389 val
|= DREF_SSC_SOURCE_ENABLE
;
5391 /* SSC must be turned on before enabling the CPU output */
5392 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5393 DRM_DEBUG_KMS("Using SSC on panel\n");
5394 val
|= DREF_SSC1_ENABLE
;
5396 val
&= ~DREF_SSC1_ENABLE
;
5398 /* Get SSC going before enabling the outputs */
5399 I915_WRITE(PCH_DREF_CONTROL
, val
);
5400 POSTING_READ(PCH_DREF_CONTROL
);
5403 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5405 /* Enable CPU source on CPU attached eDP */
5407 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5408 DRM_DEBUG_KMS("Using SSC on eDP\n");
5409 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5412 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5414 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5416 I915_WRITE(PCH_DREF_CONTROL
, val
);
5417 POSTING_READ(PCH_DREF_CONTROL
);
5420 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5422 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5424 /* Turn off CPU output */
5425 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5427 I915_WRITE(PCH_DREF_CONTROL
, val
);
5428 POSTING_READ(PCH_DREF_CONTROL
);
5431 /* Turn off the SSC source */
5432 val
&= ~DREF_SSC_SOURCE_MASK
;
5433 val
|= DREF_SSC_SOURCE_DISABLE
;
5436 val
&= ~DREF_SSC1_ENABLE
;
5438 I915_WRITE(PCH_DREF_CONTROL
, val
);
5439 POSTING_READ(PCH_DREF_CONTROL
);
5443 BUG_ON(val
!= final
);
5446 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5450 tmp
= I915_READ(SOUTH_CHICKEN2
);
5451 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5452 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5454 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5455 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5456 DRM_ERROR("FDI mPHY reset assert timeout\n");
5458 tmp
= I915_READ(SOUTH_CHICKEN2
);
5459 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5460 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5462 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5463 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5464 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5467 /* WaMPhyProgramming:hsw */
5468 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5472 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5473 tmp
&= ~(0xFF << 24);
5474 tmp
|= (0x12 << 24);
5475 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5477 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5479 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5481 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5483 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5485 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5486 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5487 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5489 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5490 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5491 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5493 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5496 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5498 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5501 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5503 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5506 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5508 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5511 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5513 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5514 tmp
&= ~(0xFF << 16);
5515 tmp
|= (0x1C << 16);
5516 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5518 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5519 tmp
&= ~(0xFF << 16);
5520 tmp
|= (0x1C << 16);
5521 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5523 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5525 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5527 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5529 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5531 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5532 tmp
&= ~(0xF << 28);
5534 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5536 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5537 tmp
&= ~(0xF << 28);
5539 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5542 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5543 * Programming" based on the parameters passed:
5544 * - Sequence to enable CLKOUT_DP
5545 * - Sequence to enable CLKOUT_DP without spread
5546 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5548 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5556 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5557 with_fdi
, "LP PCH doesn't have FDI\n"))
5560 mutex_lock(&dev_priv
->dpio_lock
);
5562 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5563 tmp
&= ~SBI_SSCCTL_DISABLE
;
5564 tmp
|= SBI_SSCCTL_PATHALT
;
5565 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5570 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5571 tmp
&= ~SBI_SSCCTL_PATHALT
;
5572 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5575 lpt_reset_fdi_mphy(dev_priv
);
5576 lpt_program_fdi_mphy(dev_priv
);
5580 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5581 SBI_GEN0
: SBI_DBUFF0
;
5582 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5583 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5584 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5586 mutex_unlock(&dev_priv
->dpio_lock
);
5589 /* Sequence to disable CLKOUT_DP */
5590 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5595 mutex_lock(&dev_priv
->dpio_lock
);
5597 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5598 SBI_GEN0
: SBI_DBUFF0
;
5599 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5600 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5601 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5603 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5604 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5605 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5606 tmp
|= SBI_SSCCTL_PATHALT
;
5607 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5610 tmp
|= SBI_SSCCTL_DISABLE
;
5611 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5614 mutex_unlock(&dev_priv
->dpio_lock
);
5617 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5619 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5620 struct intel_encoder
*encoder
;
5621 bool has_vga
= false;
5623 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5624 switch (encoder
->type
) {
5625 case INTEL_OUTPUT_ANALOG
:
5632 lpt_enable_clkout_dp(dev
, true, true);
5634 lpt_disable_clkout_dp(dev
);
5638 * Initialize reference clocks when the driver loads
5640 void intel_init_pch_refclk(struct drm_device
*dev
)
5642 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5643 ironlake_init_pch_refclk(dev
);
5644 else if (HAS_PCH_LPT(dev
))
5645 lpt_init_pch_refclk(dev
);
5648 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5650 struct drm_device
*dev
= crtc
->dev
;
5651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5652 struct intel_encoder
*encoder
;
5653 int num_connectors
= 0;
5654 bool is_lvds
= false;
5656 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5657 switch (encoder
->type
) {
5658 case INTEL_OUTPUT_LVDS
:
5665 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5666 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5667 dev_priv
->vbt
.lvds_ssc_freq
);
5668 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5674 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5676 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5678 int pipe
= intel_crtc
->pipe
;
5683 switch (intel_crtc
->config
.pipe_bpp
) {
5685 val
|= PIPECONF_6BPC
;
5688 val
|= PIPECONF_8BPC
;
5691 val
|= PIPECONF_10BPC
;
5694 val
|= PIPECONF_12BPC
;
5697 /* Case prevented by intel_choose_pipe_bpp_dither. */
5701 if (intel_crtc
->config
.dither
)
5702 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5704 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5705 val
|= PIPECONF_INTERLACED_ILK
;
5707 val
|= PIPECONF_PROGRESSIVE
;
5709 if (intel_crtc
->config
.limited_color_range
)
5710 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5712 I915_WRITE(PIPECONF(pipe
), val
);
5713 POSTING_READ(PIPECONF(pipe
));
5717 * Set up the pipe CSC unit.
5719 * Currently only full range RGB to limited range RGB conversion
5720 * is supported, but eventually this should handle various
5721 * RGB<->YCbCr scenarios as well.
5723 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5725 struct drm_device
*dev
= crtc
->dev
;
5726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5727 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5728 int pipe
= intel_crtc
->pipe
;
5729 uint16_t coeff
= 0x7800; /* 1.0 */
5732 * TODO: Check what kind of values actually come out of the pipe
5733 * with these coeff/postoff values and adjust to get the best
5734 * accuracy. Perhaps we even need to take the bpc value into
5738 if (intel_crtc
->config
.limited_color_range
)
5739 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5742 * GY/GU and RY/RU should be the other way around according
5743 * to BSpec, but reality doesn't agree. Just set them up in
5744 * a way that results in the correct picture.
5746 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5747 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5749 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5750 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5752 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5753 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5755 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5756 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5757 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5759 if (INTEL_INFO(dev
)->gen
> 6) {
5760 uint16_t postoff
= 0;
5762 if (intel_crtc
->config
.limited_color_range
)
5763 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5765 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5766 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5767 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5769 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5771 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5773 if (intel_crtc
->config
.limited_color_range
)
5774 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5776 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5780 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5782 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5783 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5784 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5789 if (intel_crtc
->config
.dither
)
5790 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5792 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5793 val
|= PIPECONF_INTERLACED_ILK
;
5795 val
|= PIPECONF_PROGRESSIVE
;
5797 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5798 POSTING_READ(PIPECONF(cpu_transcoder
));
5800 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5801 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5804 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5805 intel_clock_t
*clock
,
5806 bool *has_reduced_clock
,
5807 intel_clock_t
*reduced_clock
)
5809 struct drm_device
*dev
= crtc
->dev
;
5810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5811 struct intel_encoder
*intel_encoder
;
5813 const intel_limit_t
*limit
;
5814 bool ret
, is_lvds
= false;
5816 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5817 switch (intel_encoder
->type
) {
5818 case INTEL_OUTPUT_LVDS
:
5824 refclk
= ironlake_get_refclk(crtc
);
5827 * Returns a set of divisors for the desired target clock with the given
5828 * refclk, or FALSE. The returned values represent the clock equation:
5829 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5831 limit
= intel_limit(crtc
, refclk
);
5832 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5833 to_intel_crtc(crtc
)->config
.port_clock
,
5834 refclk
, NULL
, clock
);
5838 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5840 * Ensure we match the reduced clock's P to the target clock.
5841 * If the clocks don't match, we can't switch the display clock
5842 * by using the FP0/FP1. In such case we will disable the LVDS
5843 * downclock feature.
5845 *has_reduced_clock
=
5846 dev_priv
->display
.find_dpll(limit
, crtc
,
5847 dev_priv
->lvds_downclock
,
5855 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5860 temp
= I915_READ(SOUTH_CHICKEN1
);
5861 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5864 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5865 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5867 temp
|= FDI_BC_BIFURCATION_SELECT
;
5868 DRM_DEBUG_KMS("enabling fdi C rx\n");
5869 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5870 POSTING_READ(SOUTH_CHICKEN1
);
5873 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5875 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5878 switch (intel_crtc
->pipe
) {
5882 if (intel_crtc
->config
.fdi_lanes
> 2)
5883 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5885 cpt_enable_fdi_bc_bifurcation(dev
);
5889 cpt_enable_fdi_bc_bifurcation(dev
);
5897 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5900 * Account for spread spectrum to avoid
5901 * oversubscribing the link. Max center spread
5902 * is 2.5%; use 5% for safety's sake.
5904 u32 bps
= target_clock
* bpp
* 21 / 20;
5905 return bps
/ (link_bw
* 8) + 1;
5908 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5910 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5913 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5915 intel_clock_t
*reduced_clock
, u32
*fp2
)
5917 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5918 struct drm_device
*dev
= crtc
->dev
;
5919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5920 struct intel_encoder
*intel_encoder
;
5922 int factor
, num_connectors
= 0;
5923 bool is_lvds
= false, is_sdvo
= false;
5925 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5926 switch (intel_encoder
->type
) {
5927 case INTEL_OUTPUT_LVDS
:
5930 case INTEL_OUTPUT_SDVO
:
5931 case INTEL_OUTPUT_HDMI
:
5939 /* Enable autotuning of the PLL clock (if permissible) */
5942 if ((intel_panel_use_ssc(dev_priv
) &&
5943 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5944 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5946 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5949 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5952 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5958 dpll
|= DPLLB_MODE_LVDS
;
5960 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5962 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5963 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5966 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5967 if (intel_crtc
->config
.has_dp_encoder
)
5968 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5970 /* compute bitmask from p1 value */
5971 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5973 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5975 switch (intel_crtc
->config
.dpll
.p2
) {
5977 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5980 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5983 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5986 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5990 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5991 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5993 dpll
|= PLL_REF_INPUT_DREFCLK
;
5995 return dpll
| DPLL_VCO_ENABLE
;
5998 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
6000 struct drm_framebuffer
*fb
)
6002 struct drm_device
*dev
= crtc
->dev
;
6003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6004 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6005 int pipe
= intel_crtc
->pipe
;
6006 int plane
= intel_crtc
->plane
;
6007 int num_connectors
= 0;
6008 intel_clock_t clock
, reduced_clock
;
6009 u32 dpll
= 0, fp
= 0, fp2
= 0;
6010 bool ok
, has_reduced_clock
= false;
6011 bool is_lvds
= false;
6012 struct intel_encoder
*encoder
;
6013 struct intel_shared_dpll
*pll
;
6016 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6017 switch (encoder
->type
) {
6018 case INTEL_OUTPUT_LVDS
:
6026 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6027 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6029 ok
= ironlake_compute_clocks(crtc
, &clock
,
6030 &has_reduced_clock
, &reduced_clock
);
6031 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6032 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6035 /* Compat-code for transition, will disappear. */
6036 if (!intel_crtc
->config
.clock_set
) {
6037 intel_crtc
->config
.dpll
.n
= clock
.n
;
6038 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6039 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6040 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6041 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6044 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6045 if (intel_crtc
->config
.has_pch_encoder
) {
6046 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6047 if (has_reduced_clock
)
6048 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6050 dpll
= ironlake_compute_dpll(intel_crtc
,
6051 &fp
, &reduced_clock
,
6052 has_reduced_clock
? &fp2
: NULL
);
6054 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6055 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6056 if (has_reduced_clock
)
6057 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6059 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6061 pll
= intel_get_shared_dpll(intel_crtc
);
6063 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6068 intel_put_shared_dpll(intel_crtc
);
6070 if (intel_crtc
->config
.has_dp_encoder
)
6071 intel_dp_set_m_n(intel_crtc
);
6073 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6074 intel_crtc
->lowfreq_avail
= true;
6076 intel_crtc
->lowfreq_avail
= false;
6078 if (intel_crtc
->config
.has_pch_encoder
) {
6079 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
6083 intel_set_pipe_timings(intel_crtc
);
6085 if (intel_crtc
->config
.has_pch_encoder
) {
6086 intel_cpu_transcoder_set_m_n(intel_crtc
,
6087 &intel_crtc
->config
.fdi_m_n
);
6090 if (IS_IVYBRIDGE(dev
))
6091 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
6093 ironlake_set_pipeconf(crtc
);
6095 /* Set up the display plane register */
6096 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6097 POSTING_READ(DSPCNTR(plane
));
6099 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6104 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6105 struct intel_link_m_n
*m_n
)
6107 struct drm_device
*dev
= crtc
->base
.dev
;
6108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6109 enum pipe pipe
= crtc
->pipe
;
6111 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6112 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6113 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6115 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6116 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6117 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6120 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6121 enum transcoder transcoder
,
6122 struct intel_link_m_n
*m_n
)
6124 struct drm_device
*dev
= crtc
->base
.dev
;
6125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6126 enum pipe pipe
= crtc
->pipe
;
6128 if (INTEL_INFO(dev
)->gen
>= 5) {
6129 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6130 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6131 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6133 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6134 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6135 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6137 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6138 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6139 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6141 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6142 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6143 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6147 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6148 struct intel_crtc_config
*pipe_config
)
6150 if (crtc
->config
.has_pch_encoder
)
6151 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6153 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6154 &pipe_config
->dp_m_n
);
6157 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6158 struct intel_crtc_config
*pipe_config
)
6160 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6161 &pipe_config
->fdi_m_n
);
6164 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6165 struct intel_crtc_config
*pipe_config
)
6167 struct drm_device
*dev
= crtc
->base
.dev
;
6168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6171 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6173 if (tmp
& PF_ENABLE
) {
6174 pipe_config
->pch_pfit
.enabled
= true;
6175 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6176 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6178 /* We currently do not free assignements of panel fitters on
6179 * ivb/hsw (since we don't use the higher upscaling modes which
6180 * differentiates them) so just WARN about this case for now. */
6182 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6183 PF_PIPE_SEL_IVB(crtc
->pipe
));
6188 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6189 struct intel_crtc_config
*pipe_config
)
6191 struct drm_device
*dev
= crtc
->base
.dev
;
6192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6195 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6196 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6198 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6199 if (!(tmp
& PIPECONF_ENABLE
))
6202 switch (tmp
& PIPECONF_BPC_MASK
) {
6204 pipe_config
->pipe_bpp
= 18;
6207 pipe_config
->pipe_bpp
= 24;
6209 case PIPECONF_10BPC
:
6210 pipe_config
->pipe_bpp
= 30;
6212 case PIPECONF_12BPC
:
6213 pipe_config
->pipe_bpp
= 36;
6219 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6220 struct intel_shared_dpll
*pll
;
6222 pipe_config
->has_pch_encoder
= true;
6224 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6225 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6226 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6228 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6230 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6231 pipe_config
->shared_dpll
=
6232 (enum intel_dpll_id
) crtc
->pipe
;
6234 tmp
= I915_READ(PCH_DPLL_SEL
);
6235 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6236 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6238 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6241 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6243 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6244 &pipe_config
->dpll_hw_state
));
6246 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6247 pipe_config
->pixel_multiplier
=
6248 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6249 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6251 ironlake_pch_clock_get(crtc
, pipe_config
);
6253 pipe_config
->pixel_multiplier
= 1;
6256 intel_get_pipe_timings(crtc
, pipe_config
);
6258 ironlake_get_pfit_config(crtc
, pipe_config
);
6263 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6265 struct drm_device
*dev
= dev_priv
->dev
;
6266 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6267 struct intel_crtc
*crtc
;
6268 unsigned long irqflags
;
6271 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6272 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6273 pipe_name(crtc
->pipe
));
6275 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6276 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6277 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6278 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6279 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6280 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6281 "CPU PWM1 enabled\n");
6282 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6283 "CPU PWM2 enabled\n");
6284 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6285 "PCH PWM1 enabled\n");
6286 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6287 "Utility pin enabled\n");
6288 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6290 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6291 val
= I915_READ(DEIMR
);
6292 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6293 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6294 val
= I915_READ(SDEIMR
);
6295 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6296 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6297 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6301 * This function implements pieces of two sequences from BSpec:
6302 * - Sequence for display software to disable LCPLL
6303 * - Sequence for display software to allow package C8+
6304 * The steps implemented here are just the steps that actually touch the LCPLL
6305 * register. Callers should take care of disabling all the display engine
6306 * functions, doing the mode unset, fixing interrupts, etc.
6308 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6309 bool switch_to_fclk
, bool allow_power_down
)
6313 assert_can_disable_lcpll(dev_priv
);
6315 val
= I915_READ(LCPLL_CTL
);
6317 if (switch_to_fclk
) {
6318 val
|= LCPLL_CD_SOURCE_FCLK
;
6319 I915_WRITE(LCPLL_CTL
, val
);
6321 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6322 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6323 DRM_ERROR("Switching to FCLK failed\n");
6325 val
= I915_READ(LCPLL_CTL
);
6328 val
|= LCPLL_PLL_DISABLE
;
6329 I915_WRITE(LCPLL_CTL
, val
);
6330 POSTING_READ(LCPLL_CTL
);
6332 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6333 DRM_ERROR("LCPLL still locked\n");
6335 val
= I915_READ(D_COMP
);
6336 val
|= D_COMP_COMP_DISABLE
;
6337 mutex_lock(&dev_priv
->rps
.hw_lock
);
6338 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6339 DRM_ERROR("Failed to disable D_COMP\n");
6340 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6341 POSTING_READ(D_COMP
);
6344 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6345 DRM_ERROR("D_COMP RCOMP still in progress\n");
6347 if (allow_power_down
) {
6348 val
= I915_READ(LCPLL_CTL
);
6349 val
|= LCPLL_POWER_DOWN_ALLOW
;
6350 I915_WRITE(LCPLL_CTL
, val
);
6351 POSTING_READ(LCPLL_CTL
);
6356 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6359 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6363 val
= I915_READ(LCPLL_CTL
);
6365 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6366 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6369 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6370 * we'll hang the machine! */
6371 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6373 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6374 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6375 I915_WRITE(LCPLL_CTL
, val
);
6376 POSTING_READ(LCPLL_CTL
);
6379 val
= I915_READ(D_COMP
);
6380 val
|= D_COMP_COMP_FORCE
;
6381 val
&= ~D_COMP_COMP_DISABLE
;
6382 mutex_lock(&dev_priv
->rps
.hw_lock
);
6383 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6384 DRM_ERROR("Failed to enable D_COMP\n");
6385 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6386 POSTING_READ(D_COMP
);
6388 val
= I915_READ(LCPLL_CTL
);
6389 val
&= ~LCPLL_PLL_DISABLE
;
6390 I915_WRITE(LCPLL_CTL
, val
);
6392 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6393 DRM_ERROR("LCPLL not locked yet\n");
6395 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6396 val
= I915_READ(LCPLL_CTL
);
6397 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6398 I915_WRITE(LCPLL_CTL
, val
);
6400 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6401 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6402 DRM_ERROR("Switching back to LCPLL failed\n");
6405 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6408 void hsw_enable_pc8_work(struct work_struct
*__work
)
6410 struct drm_i915_private
*dev_priv
=
6411 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6413 struct drm_device
*dev
= dev_priv
->dev
;
6416 if (dev_priv
->pc8
.enabled
)
6419 DRM_DEBUG_KMS("Enabling package C8+\n");
6421 dev_priv
->pc8
.enabled
= true;
6423 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6424 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6425 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6426 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6429 lpt_disable_clkout_dp(dev
);
6430 hsw_pc8_disable_interrupts(dev
);
6431 hsw_disable_lcpll(dev_priv
, true, true);
6434 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6436 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6437 WARN(dev_priv
->pc8
.disable_count
< 1,
6438 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6440 dev_priv
->pc8
.disable_count
--;
6441 if (dev_priv
->pc8
.disable_count
!= 0)
6444 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6445 msecs_to_jiffies(i915_pc8_timeout
));
6448 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6450 struct drm_device
*dev
= dev_priv
->dev
;
6453 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6454 WARN(dev_priv
->pc8
.disable_count
< 0,
6455 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6457 dev_priv
->pc8
.disable_count
++;
6458 if (dev_priv
->pc8
.disable_count
!= 1)
6461 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6462 if (!dev_priv
->pc8
.enabled
)
6465 DRM_DEBUG_KMS("Disabling package C8+\n");
6467 hsw_restore_lcpll(dev_priv
);
6468 hsw_pc8_restore_interrupts(dev
);
6469 lpt_init_pch_refclk(dev
);
6471 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6472 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6473 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6474 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6477 intel_prepare_ddi(dev
);
6478 i915_gem_init_swizzling(dev
);
6479 mutex_lock(&dev_priv
->rps
.hw_lock
);
6480 gen6_update_ring_freq(dev
);
6481 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6482 dev_priv
->pc8
.enabled
= false;
6485 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6487 mutex_lock(&dev_priv
->pc8
.lock
);
6488 __hsw_enable_package_c8(dev_priv
);
6489 mutex_unlock(&dev_priv
->pc8
.lock
);
6492 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6494 mutex_lock(&dev_priv
->pc8
.lock
);
6495 __hsw_disable_package_c8(dev_priv
);
6496 mutex_unlock(&dev_priv
->pc8
.lock
);
6499 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6501 struct drm_device
*dev
= dev_priv
->dev
;
6502 struct intel_crtc
*crtc
;
6505 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6506 if (crtc
->base
.enabled
)
6509 /* This case is still possible since we have the i915.disable_power_well
6510 * parameter and also the KVMr or something else might be requesting the
6512 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6514 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6521 /* Since we're called from modeset_global_resources there's no way to
6522 * symmetrically increase and decrease the refcount, so we use
6523 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6526 static void hsw_update_package_c8(struct drm_device
*dev
)
6528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6531 if (!i915_enable_pc8
)
6534 mutex_lock(&dev_priv
->pc8
.lock
);
6536 allow
= hsw_can_enable_package_c8(dev_priv
);
6538 if (allow
== dev_priv
->pc8
.requirements_met
)
6541 dev_priv
->pc8
.requirements_met
= allow
;
6544 __hsw_enable_package_c8(dev_priv
);
6546 __hsw_disable_package_c8(dev_priv
);
6549 mutex_unlock(&dev_priv
->pc8
.lock
);
6552 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6554 if (!dev_priv
->pc8
.gpu_idle
) {
6555 dev_priv
->pc8
.gpu_idle
= true;
6556 hsw_enable_package_c8(dev_priv
);
6560 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6562 if (dev_priv
->pc8
.gpu_idle
) {
6563 dev_priv
->pc8
.gpu_idle
= false;
6564 hsw_disable_package_c8(dev_priv
);
6568 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6570 bool enable
= false;
6571 struct intel_crtc
*crtc
;
6573 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6574 if (!crtc
->base
.enabled
)
6577 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6578 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6582 intel_set_power_well(dev
, enable
);
6584 hsw_update_package_c8(dev
);
6587 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6589 struct drm_framebuffer
*fb
)
6591 struct drm_device
*dev
= crtc
->dev
;
6592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6593 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6594 int plane
= intel_crtc
->plane
;
6597 if (!intel_ddi_pll_mode_set(crtc
))
6600 if (intel_crtc
->config
.has_dp_encoder
)
6601 intel_dp_set_m_n(intel_crtc
);
6603 intel_crtc
->lowfreq_avail
= false;
6605 intel_set_pipe_timings(intel_crtc
);
6607 if (intel_crtc
->config
.has_pch_encoder
) {
6608 intel_cpu_transcoder_set_m_n(intel_crtc
,
6609 &intel_crtc
->config
.fdi_m_n
);
6612 haswell_set_pipeconf(crtc
);
6614 intel_set_pipe_csc(crtc
);
6616 /* Set up the display plane register */
6617 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6618 POSTING_READ(DSPCNTR(plane
));
6620 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6625 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6626 struct intel_crtc_config
*pipe_config
)
6628 struct drm_device
*dev
= crtc
->base
.dev
;
6629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6630 enum intel_display_power_domain pfit_domain
;
6633 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6634 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6636 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6637 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6638 enum pipe trans_edp_pipe
;
6639 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6641 WARN(1, "unknown pipe linked to edp transcoder\n");
6642 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6643 case TRANS_DDI_EDP_INPUT_A_ON
:
6644 trans_edp_pipe
= PIPE_A
;
6646 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6647 trans_edp_pipe
= PIPE_B
;
6649 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6650 trans_edp_pipe
= PIPE_C
;
6654 if (trans_edp_pipe
== crtc
->pipe
)
6655 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6658 if (!intel_display_power_enabled(dev
,
6659 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6662 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6663 if (!(tmp
& PIPECONF_ENABLE
))
6667 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6668 * DDI E. So just check whether this pipe is wired to DDI E and whether
6669 * the PCH transcoder is on.
6671 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6672 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6673 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6674 pipe_config
->has_pch_encoder
= true;
6676 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6677 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6678 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6680 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6683 intel_get_pipe_timings(crtc
, pipe_config
);
6685 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6686 if (intel_display_power_enabled(dev
, pfit_domain
))
6687 ironlake_get_pfit_config(crtc
, pipe_config
);
6689 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6690 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6692 pipe_config
->pixel_multiplier
= 1;
6697 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6699 struct drm_framebuffer
*fb
)
6701 struct drm_device
*dev
= crtc
->dev
;
6702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6703 struct intel_encoder
*encoder
;
6704 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6705 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6706 int pipe
= intel_crtc
->pipe
;
6709 drm_vblank_pre_modeset(dev
, pipe
);
6711 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6713 drm_vblank_post_modeset(dev
, pipe
);
6718 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6719 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6720 encoder
->base
.base
.id
,
6721 drm_get_encoder_name(&encoder
->base
),
6722 mode
->base
.id
, mode
->name
);
6723 encoder
->mode_set(encoder
);
6729 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6730 int reg_eldv
, uint32_t bits_eldv
,
6731 int reg_elda
, uint32_t bits_elda
,
6734 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6735 uint8_t *eld
= connector
->eld
;
6738 i
= I915_READ(reg_eldv
);
6747 i
= I915_READ(reg_elda
);
6749 I915_WRITE(reg_elda
, i
);
6751 for (i
= 0; i
< eld
[2]; i
++)
6752 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6758 static void g4x_write_eld(struct drm_connector
*connector
,
6759 struct drm_crtc
*crtc
)
6761 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6762 uint8_t *eld
= connector
->eld
;
6767 i
= I915_READ(G4X_AUD_VID_DID
);
6769 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6770 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6772 eldv
= G4X_ELDV_DEVCTG
;
6774 if (intel_eld_uptodate(connector
,
6775 G4X_AUD_CNTL_ST
, eldv
,
6776 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6777 G4X_HDMIW_HDMIEDID
))
6780 i
= I915_READ(G4X_AUD_CNTL_ST
);
6781 i
&= ~(eldv
| G4X_ELD_ADDR
);
6782 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6783 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6788 len
= min_t(uint8_t, eld
[2], len
);
6789 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6790 for (i
= 0; i
< len
; i
++)
6791 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6793 i
= I915_READ(G4X_AUD_CNTL_ST
);
6795 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6798 static void haswell_write_eld(struct drm_connector
*connector
,
6799 struct drm_crtc
*crtc
)
6801 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6802 uint8_t *eld
= connector
->eld
;
6803 struct drm_device
*dev
= crtc
->dev
;
6804 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6808 int pipe
= to_intel_crtc(crtc
)->pipe
;
6811 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6812 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6813 int aud_config
= HSW_AUD_CFG(pipe
);
6814 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6817 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6819 /* Audio output enable */
6820 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6821 tmp
= I915_READ(aud_cntrl_st2
);
6822 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6823 I915_WRITE(aud_cntrl_st2
, tmp
);
6825 /* Wait for 1 vertical blank */
6826 intel_wait_for_vblank(dev
, pipe
);
6828 /* Set ELD valid state */
6829 tmp
= I915_READ(aud_cntrl_st2
);
6830 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6831 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6832 I915_WRITE(aud_cntrl_st2
, tmp
);
6833 tmp
= I915_READ(aud_cntrl_st2
);
6834 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6836 /* Enable HDMI mode */
6837 tmp
= I915_READ(aud_config
);
6838 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6839 /* clear N_programing_enable and N_value_index */
6840 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6841 I915_WRITE(aud_config
, tmp
);
6843 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6845 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6846 intel_crtc
->eld_vld
= true;
6848 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6849 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6850 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6851 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6853 I915_WRITE(aud_config
, 0);
6855 if (intel_eld_uptodate(connector
,
6856 aud_cntrl_st2
, eldv
,
6857 aud_cntl_st
, IBX_ELD_ADDRESS
,
6861 i
= I915_READ(aud_cntrl_st2
);
6863 I915_WRITE(aud_cntrl_st2
, i
);
6868 i
= I915_READ(aud_cntl_st
);
6869 i
&= ~IBX_ELD_ADDRESS
;
6870 I915_WRITE(aud_cntl_st
, i
);
6871 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6872 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6874 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6875 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6876 for (i
= 0; i
< len
; i
++)
6877 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6879 i
= I915_READ(aud_cntrl_st2
);
6881 I915_WRITE(aud_cntrl_st2
, i
);
6885 static void ironlake_write_eld(struct drm_connector
*connector
,
6886 struct drm_crtc
*crtc
)
6888 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6889 uint8_t *eld
= connector
->eld
;
6897 int pipe
= to_intel_crtc(crtc
)->pipe
;
6899 if (HAS_PCH_IBX(connector
->dev
)) {
6900 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6901 aud_config
= IBX_AUD_CFG(pipe
);
6902 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6903 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6905 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6906 aud_config
= CPT_AUD_CFG(pipe
);
6907 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6908 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6911 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6913 i
= I915_READ(aud_cntl_st
);
6914 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6916 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6917 /* operate blindly on all ports */
6918 eldv
= IBX_ELD_VALIDB
;
6919 eldv
|= IBX_ELD_VALIDB
<< 4;
6920 eldv
|= IBX_ELD_VALIDB
<< 8;
6922 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6923 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6926 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6927 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6928 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6929 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6931 I915_WRITE(aud_config
, 0);
6933 if (intel_eld_uptodate(connector
,
6934 aud_cntrl_st2
, eldv
,
6935 aud_cntl_st
, IBX_ELD_ADDRESS
,
6939 i
= I915_READ(aud_cntrl_st2
);
6941 I915_WRITE(aud_cntrl_st2
, i
);
6946 i
= I915_READ(aud_cntl_st
);
6947 i
&= ~IBX_ELD_ADDRESS
;
6948 I915_WRITE(aud_cntl_st
, i
);
6950 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6951 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6952 for (i
= 0; i
< len
; i
++)
6953 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6955 i
= I915_READ(aud_cntrl_st2
);
6957 I915_WRITE(aud_cntrl_st2
, i
);
6960 void intel_write_eld(struct drm_encoder
*encoder
,
6961 struct drm_display_mode
*mode
)
6963 struct drm_crtc
*crtc
= encoder
->crtc
;
6964 struct drm_connector
*connector
;
6965 struct drm_device
*dev
= encoder
->dev
;
6966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6968 connector
= drm_select_eld(encoder
, mode
);
6972 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6974 drm_get_connector_name(connector
),
6975 connector
->encoder
->base
.id
,
6976 drm_get_encoder_name(connector
->encoder
));
6978 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6980 if (dev_priv
->display
.write_eld
)
6981 dev_priv
->display
.write_eld(connector
, crtc
);
6984 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6986 struct drm_device
*dev
= crtc
->dev
;
6987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6988 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6989 bool visible
= base
!= 0;
6992 if (intel_crtc
->cursor_visible
== visible
)
6995 cntl
= I915_READ(_CURACNTR
);
6997 /* On these chipsets we can only modify the base whilst
6998 * the cursor is disabled.
7000 I915_WRITE(_CURABASE
, base
);
7002 cntl
&= ~(CURSOR_FORMAT_MASK
);
7003 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7004 cntl
|= CURSOR_ENABLE
|
7005 CURSOR_GAMMA_ENABLE
|
7008 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
7009 I915_WRITE(_CURACNTR
, cntl
);
7011 intel_crtc
->cursor_visible
= visible
;
7014 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7016 struct drm_device
*dev
= crtc
->dev
;
7017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7018 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7019 int pipe
= intel_crtc
->pipe
;
7020 bool visible
= base
!= 0;
7022 if (intel_crtc
->cursor_visible
!= visible
) {
7023 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7025 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7026 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7027 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7029 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7030 cntl
|= CURSOR_MODE_DISABLE
;
7032 I915_WRITE(CURCNTR(pipe
), cntl
);
7034 intel_crtc
->cursor_visible
= visible
;
7036 /* and commit changes on next vblank */
7037 I915_WRITE(CURBASE(pipe
), base
);
7040 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7042 struct drm_device
*dev
= crtc
->dev
;
7043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7045 int pipe
= intel_crtc
->pipe
;
7046 bool visible
= base
!= 0;
7048 if (intel_crtc
->cursor_visible
!= visible
) {
7049 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7051 cntl
&= ~CURSOR_MODE
;
7052 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7054 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7055 cntl
|= CURSOR_MODE_DISABLE
;
7057 if (IS_HASWELL(dev
)) {
7058 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7059 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7061 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7063 intel_crtc
->cursor_visible
= visible
;
7065 /* and commit changes on next vblank */
7066 I915_WRITE(CURBASE_IVB(pipe
), base
);
7069 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7070 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7073 struct drm_device
*dev
= crtc
->dev
;
7074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7076 int pipe
= intel_crtc
->pipe
;
7077 int x
= intel_crtc
->cursor_x
;
7078 int y
= intel_crtc
->cursor_y
;
7079 u32 base
= 0, pos
= 0;
7083 base
= intel_crtc
->cursor_addr
;
7085 if (x
>= intel_crtc
->config
.pipe_src_w
)
7088 if (y
>= intel_crtc
->config
.pipe_src_h
)
7092 if (x
+ intel_crtc
->cursor_width
<= 0)
7095 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7098 pos
|= x
<< CURSOR_X_SHIFT
;
7101 if (y
+ intel_crtc
->cursor_height
<= 0)
7104 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7107 pos
|= y
<< CURSOR_Y_SHIFT
;
7109 visible
= base
!= 0;
7110 if (!visible
&& !intel_crtc
->cursor_visible
)
7113 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
7114 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7115 ivb_update_cursor(crtc
, base
);
7117 I915_WRITE(CURPOS(pipe
), pos
);
7118 if (IS_845G(dev
) || IS_I865G(dev
))
7119 i845_update_cursor(crtc
, base
);
7121 i9xx_update_cursor(crtc
, base
);
7125 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7126 struct drm_file
*file
,
7128 uint32_t width
, uint32_t height
)
7130 struct drm_device
*dev
= crtc
->dev
;
7131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7133 struct drm_i915_gem_object
*obj
;
7137 /* if we want to turn off the cursor ignore width and height */
7139 DRM_DEBUG_KMS("cursor off\n");
7142 mutex_lock(&dev
->struct_mutex
);
7146 /* Currently we only support 64x64 cursors */
7147 if (width
!= 64 || height
!= 64) {
7148 DRM_ERROR("we currently only support 64x64 cursors\n");
7152 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7153 if (&obj
->base
== NULL
)
7156 if (obj
->base
.size
< width
* height
* 4) {
7157 DRM_ERROR("buffer is to small\n");
7162 /* we only need to pin inside GTT if cursor is non-phy */
7163 mutex_lock(&dev
->struct_mutex
);
7164 if (!dev_priv
->info
->cursor_needs_physical
) {
7167 if (obj
->tiling_mode
) {
7168 DRM_ERROR("cursor cannot be tiled\n");
7173 /* Note that the w/a also requires 2 PTE of padding following
7174 * the bo. We currently fill all unused PTE with the shadow
7175 * page and so we should always have valid PTE following the
7176 * cursor preventing the VT-d warning.
7179 if (need_vtd_wa(dev
))
7180 alignment
= 64*1024;
7182 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7184 DRM_ERROR("failed to move cursor bo into the GTT\n");
7188 ret
= i915_gem_object_put_fence(obj
);
7190 DRM_ERROR("failed to release fence for cursor");
7194 addr
= i915_gem_obj_ggtt_offset(obj
);
7196 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7197 ret
= i915_gem_attach_phys_object(dev
, obj
,
7198 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7201 DRM_ERROR("failed to attach phys object\n");
7204 addr
= obj
->phys_obj
->handle
->busaddr
;
7208 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7211 if (intel_crtc
->cursor_bo
) {
7212 if (dev_priv
->info
->cursor_needs_physical
) {
7213 if (intel_crtc
->cursor_bo
!= obj
)
7214 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7216 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7217 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7220 mutex_unlock(&dev
->struct_mutex
);
7222 intel_crtc
->cursor_addr
= addr
;
7223 intel_crtc
->cursor_bo
= obj
;
7224 intel_crtc
->cursor_width
= width
;
7225 intel_crtc
->cursor_height
= height
;
7227 if (intel_crtc
->active
)
7228 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7232 i915_gem_object_unpin_from_display_plane(obj
);
7234 mutex_unlock(&dev
->struct_mutex
);
7236 drm_gem_object_unreference_unlocked(&obj
->base
);
7240 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7244 intel_crtc
->cursor_x
= x
;
7245 intel_crtc
->cursor_y
= y
;
7247 if (intel_crtc
->active
)
7248 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7253 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7254 u16
*blue
, uint32_t start
, uint32_t size
)
7256 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7259 for (i
= start
; i
< end
; i
++) {
7260 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7261 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7262 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7265 intel_crtc_load_lut(crtc
);
7268 /* VESA 640x480x72Hz mode to set on the pipe */
7269 static struct drm_display_mode load_detect_mode
= {
7270 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7271 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7274 static struct drm_framebuffer
*
7275 intel_framebuffer_create(struct drm_device
*dev
,
7276 struct drm_mode_fb_cmd2
*mode_cmd
,
7277 struct drm_i915_gem_object
*obj
)
7279 struct intel_framebuffer
*intel_fb
;
7282 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7284 drm_gem_object_unreference_unlocked(&obj
->base
);
7285 return ERR_PTR(-ENOMEM
);
7288 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7290 drm_gem_object_unreference_unlocked(&obj
->base
);
7292 return ERR_PTR(ret
);
7295 return &intel_fb
->base
;
7299 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7301 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7302 return ALIGN(pitch
, 64);
7306 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7308 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7309 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7312 static struct drm_framebuffer
*
7313 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7314 struct drm_display_mode
*mode
,
7317 struct drm_i915_gem_object
*obj
;
7318 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7320 obj
= i915_gem_alloc_object(dev
,
7321 intel_framebuffer_size_for_mode(mode
, bpp
));
7323 return ERR_PTR(-ENOMEM
);
7325 mode_cmd
.width
= mode
->hdisplay
;
7326 mode_cmd
.height
= mode
->vdisplay
;
7327 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7329 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7331 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7334 static struct drm_framebuffer
*
7335 mode_fits_in_fbdev(struct drm_device
*dev
,
7336 struct drm_display_mode
*mode
)
7338 #ifdef CONFIG_DRM_I915_FBDEV
7339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7340 struct drm_i915_gem_object
*obj
;
7341 struct drm_framebuffer
*fb
;
7343 if (dev_priv
->fbdev
== NULL
)
7346 obj
= dev_priv
->fbdev
->ifb
.obj
;
7350 fb
= &dev_priv
->fbdev
->ifb
.base
;
7351 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7352 fb
->bits_per_pixel
))
7355 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7364 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7365 struct drm_display_mode
*mode
,
7366 struct intel_load_detect_pipe
*old
)
7368 struct intel_crtc
*intel_crtc
;
7369 struct intel_encoder
*intel_encoder
=
7370 intel_attached_encoder(connector
);
7371 struct drm_crtc
*possible_crtc
;
7372 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7373 struct drm_crtc
*crtc
= NULL
;
7374 struct drm_device
*dev
= encoder
->dev
;
7375 struct drm_framebuffer
*fb
;
7378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7379 connector
->base
.id
, drm_get_connector_name(connector
),
7380 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7383 * Algorithm gets a little messy:
7385 * - if the connector already has an assigned crtc, use it (but make
7386 * sure it's on first)
7388 * - try to find the first unused crtc that can drive this connector,
7389 * and use that if we find one
7392 /* See if we already have a CRTC for this connector */
7393 if (encoder
->crtc
) {
7394 crtc
= encoder
->crtc
;
7396 mutex_lock(&crtc
->mutex
);
7398 old
->dpms_mode
= connector
->dpms
;
7399 old
->load_detect_temp
= false;
7401 /* Make sure the crtc and connector are running */
7402 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7403 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7408 /* Find an unused one (if possible) */
7409 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7411 if (!(encoder
->possible_crtcs
& (1 << i
)))
7413 if (!possible_crtc
->enabled
) {
7414 crtc
= possible_crtc
;
7420 * If we didn't find an unused CRTC, don't use any.
7423 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7427 mutex_lock(&crtc
->mutex
);
7428 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7429 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7431 intel_crtc
= to_intel_crtc(crtc
);
7432 old
->dpms_mode
= connector
->dpms
;
7433 old
->load_detect_temp
= true;
7434 old
->release_fb
= NULL
;
7437 mode
= &load_detect_mode
;
7439 /* We need a framebuffer large enough to accommodate all accesses
7440 * that the plane may generate whilst we perform load detection.
7441 * We can not rely on the fbcon either being present (we get called
7442 * during its initialisation to detect all boot displays, or it may
7443 * not even exist) or that it is large enough to satisfy the
7446 fb
= mode_fits_in_fbdev(dev
, mode
);
7448 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7449 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7450 old
->release_fb
= fb
;
7452 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7454 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7455 mutex_unlock(&crtc
->mutex
);
7459 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7460 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7461 if (old
->release_fb
)
7462 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7463 mutex_unlock(&crtc
->mutex
);
7467 /* let the connector get through one full cycle before testing */
7468 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7472 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7473 struct intel_load_detect_pipe
*old
)
7475 struct intel_encoder
*intel_encoder
=
7476 intel_attached_encoder(connector
);
7477 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7478 struct drm_crtc
*crtc
= encoder
->crtc
;
7480 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7481 connector
->base
.id
, drm_get_connector_name(connector
),
7482 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7484 if (old
->load_detect_temp
) {
7485 to_intel_connector(connector
)->new_encoder
= NULL
;
7486 intel_encoder
->new_crtc
= NULL
;
7487 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7489 if (old
->release_fb
) {
7490 drm_framebuffer_unregister_private(old
->release_fb
);
7491 drm_framebuffer_unreference(old
->release_fb
);
7494 mutex_unlock(&crtc
->mutex
);
7498 /* Switch crtc and encoder back off if necessary */
7499 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7500 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7502 mutex_unlock(&crtc
->mutex
);
7505 static int i9xx_pll_refclk(struct drm_device
*dev
,
7506 const struct intel_crtc_config
*pipe_config
)
7508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7509 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7511 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7512 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7513 else if (HAS_PCH_SPLIT(dev
))
7515 else if (!IS_GEN2(dev
))
7521 /* Returns the clock of the currently programmed mode of the given pipe. */
7522 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7523 struct intel_crtc_config
*pipe_config
)
7525 struct drm_device
*dev
= crtc
->base
.dev
;
7526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7527 int pipe
= pipe_config
->cpu_transcoder
;
7528 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7530 intel_clock_t clock
;
7531 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7533 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7534 fp
= pipe_config
->dpll_hw_state
.fp0
;
7536 fp
= pipe_config
->dpll_hw_state
.fp1
;
7538 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7539 if (IS_PINEVIEW(dev
)) {
7540 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7541 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7543 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7544 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7547 if (!IS_GEN2(dev
)) {
7548 if (IS_PINEVIEW(dev
))
7549 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7550 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7552 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7553 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7555 switch (dpll
& DPLL_MODE_MASK
) {
7556 case DPLLB_MODE_DAC_SERIAL
:
7557 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7560 case DPLLB_MODE_LVDS
:
7561 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7565 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7566 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7570 if (IS_PINEVIEW(dev
))
7571 pineview_clock(refclk
, &clock
);
7573 i9xx_clock(refclk
, &clock
);
7575 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7578 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7579 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7582 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7585 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7586 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7588 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7594 i9xx_clock(refclk
, &clock
);
7598 * This value includes pixel_multiplier. We will use
7599 * port_clock to compute adjusted_mode.crtc_clock in the
7600 * encoder's get_config() function.
7602 pipe_config
->port_clock
= clock
.dot
;
7605 int intel_dotclock_calculate(int link_freq
,
7606 const struct intel_link_m_n
*m_n
)
7609 * The calculation for the data clock is:
7610 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7611 * But we want to avoid losing precison if possible, so:
7612 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7614 * and the link clock is simpler:
7615 * link_clock = (m * link_clock) / n
7621 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7624 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7625 struct intel_crtc_config
*pipe_config
)
7627 struct drm_device
*dev
= crtc
->base
.dev
;
7629 /* read out port_clock from the DPLL */
7630 i9xx_crtc_clock_get(crtc
, pipe_config
);
7633 * This value does not include pixel_multiplier.
7634 * We will check that port_clock and adjusted_mode.crtc_clock
7635 * agree once we know their relationship in the encoder's
7636 * get_config() function.
7638 pipe_config
->adjusted_mode
.crtc_clock
=
7639 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7640 &pipe_config
->fdi_m_n
);
7643 /** Returns the currently programmed mode of the given pipe. */
7644 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7645 struct drm_crtc
*crtc
)
7647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7648 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7649 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7650 struct drm_display_mode
*mode
;
7651 struct intel_crtc_config pipe_config
;
7652 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7653 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7654 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7655 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7656 enum pipe pipe
= intel_crtc
->pipe
;
7658 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7663 * Construct a pipe_config sufficient for getting the clock info
7664 * back out of crtc_clock_get.
7666 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7667 * to use a real value here instead.
7669 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7670 pipe_config
.pixel_multiplier
= 1;
7671 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7672 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7673 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7674 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7676 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7677 mode
->hdisplay
= (htot
& 0xffff) + 1;
7678 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7679 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7680 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7681 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7682 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7683 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7684 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7686 drm_mode_set_name(mode
);
7691 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7693 struct drm_device
*dev
= crtc
->dev
;
7694 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7695 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7696 int pipe
= intel_crtc
->pipe
;
7697 int dpll_reg
= DPLL(pipe
);
7700 if (HAS_PCH_SPLIT(dev
))
7703 if (!dev_priv
->lvds_downclock_avail
)
7706 dpll
= I915_READ(dpll_reg
);
7707 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7708 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7710 assert_panel_unlocked(dev_priv
, pipe
);
7712 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7713 I915_WRITE(dpll_reg
, dpll
);
7714 intel_wait_for_vblank(dev
, pipe
);
7716 dpll
= I915_READ(dpll_reg
);
7717 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7718 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7722 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7724 struct drm_device
*dev
= crtc
->dev
;
7725 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7726 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7728 if (HAS_PCH_SPLIT(dev
))
7731 if (!dev_priv
->lvds_downclock_avail
)
7735 * Since this is called by a timer, we should never get here in
7738 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7739 int pipe
= intel_crtc
->pipe
;
7740 int dpll_reg
= DPLL(pipe
);
7743 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7745 assert_panel_unlocked(dev_priv
, pipe
);
7747 dpll
= I915_READ(dpll_reg
);
7748 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7749 I915_WRITE(dpll_reg
, dpll
);
7750 intel_wait_for_vblank(dev
, pipe
);
7751 dpll
= I915_READ(dpll_reg
);
7752 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7753 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7758 void intel_mark_busy(struct drm_device
*dev
)
7760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7762 hsw_package_c8_gpu_busy(dev_priv
);
7763 i915_update_gfx_val(dev_priv
);
7766 void intel_mark_idle(struct drm_device
*dev
)
7768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7769 struct drm_crtc
*crtc
;
7771 hsw_package_c8_gpu_idle(dev_priv
);
7773 if (!i915_powersave
)
7776 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7780 intel_decrease_pllclock(crtc
);
7783 if (dev_priv
->info
->gen
>= 6)
7784 gen6_rps_idle(dev
->dev_private
);
7787 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7788 struct intel_ring_buffer
*ring
)
7790 struct drm_device
*dev
= obj
->base
.dev
;
7791 struct drm_crtc
*crtc
;
7793 if (!i915_powersave
)
7796 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7800 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7803 intel_increase_pllclock(crtc
);
7804 if (ring
&& intel_fbc_enabled(dev
))
7805 ring
->fbc_dirty
= true;
7809 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7811 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7812 struct drm_device
*dev
= crtc
->dev
;
7813 struct intel_unpin_work
*work
;
7814 unsigned long flags
;
7816 spin_lock_irqsave(&dev
->event_lock
, flags
);
7817 work
= intel_crtc
->unpin_work
;
7818 intel_crtc
->unpin_work
= NULL
;
7819 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7822 cancel_work_sync(&work
->work
);
7826 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7828 drm_crtc_cleanup(crtc
);
7833 static void intel_unpin_work_fn(struct work_struct
*__work
)
7835 struct intel_unpin_work
*work
=
7836 container_of(__work
, struct intel_unpin_work
, work
);
7837 struct drm_device
*dev
= work
->crtc
->dev
;
7839 mutex_lock(&dev
->struct_mutex
);
7840 intel_unpin_fb_obj(work
->old_fb_obj
);
7841 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7842 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7844 intel_update_fbc(dev
);
7845 mutex_unlock(&dev
->struct_mutex
);
7847 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7848 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7853 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7854 struct drm_crtc
*crtc
)
7856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7858 struct intel_unpin_work
*work
;
7859 unsigned long flags
;
7861 /* Ignore early vblank irqs */
7862 if (intel_crtc
== NULL
)
7865 spin_lock_irqsave(&dev
->event_lock
, flags
);
7866 work
= intel_crtc
->unpin_work
;
7868 /* Ensure we don't miss a work->pending update ... */
7871 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7872 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7876 /* and that the unpin work is consistent wrt ->pending. */
7879 intel_crtc
->unpin_work
= NULL
;
7882 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7884 drm_vblank_put(dev
, intel_crtc
->pipe
);
7886 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7888 wake_up_all(&dev_priv
->pending_flip_queue
);
7890 queue_work(dev_priv
->wq
, &work
->work
);
7892 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7895 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7897 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7898 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7900 do_intel_finish_page_flip(dev
, crtc
);
7903 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7905 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7906 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7908 do_intel_finish_page_flip(dev
, crtc
);
7911 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7914 struct intel_crtc
*intel_crtc
=
7915 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7916 unsigned long flags
;
7918 /* NB: An MMIO update of the plane base pointer will also
7919 * generate a page-flip completion irq, i.e. every modeset
7920 * is also accompanied by a spurious intel_prepare_page_flip().
7922 spin_lock_irqsave(&dev
->event_lock
, flags
);
7923 if (intel_crtc
->unpin_work
)
7924 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7925 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7928 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7930 /* Ensure that the work item is consistent when activating it ... */
7932 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7933 /* and that it is marked active as soon as the irq could fire. */
7937 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7938 struct drm_crtc
*crtc
,
7939 struct drm_framebuffer
*fb
,
7940 struct drm_i915_gem_object
*obj
,
7943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7946 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7949 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7953 ret
= intel_ring_begin(ring
, 6);
7957 /* Can't queue multiple flips, so wait for the previous
7958 * one to finish before executing the next.
7960 if (intel_crtc
->plane
)
7961 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7963 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7964 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7965 intel_ring_emit(ring
, MI_NOOP
);
7966 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7967 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7968 intel_ring_emit(ring
, fb
->pitches
[0]);
7969 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7970 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7972 intel_mark_page_flip_active(intel_crtc
);
7973 __intel_ring_advance(ring
);
7977 intel_unpin_fb_obj(obj
);
7982 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7983 struct drm_crtc
*crtc
,
7984 struct drm_framebuffer
*fb
,
7985 struct drm_i915_gem_object
*obj
,
7988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7991 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7994 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7998 ret
= intel_ring_begin(ring
, 6);
8002 if (intel_crtc
->plane
)
8003 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8005 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8006 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8007 intel_ring_emit(ring
, MI_NOOP
);
8008 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
8009 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8010 intel_ring_emit(ring
, fb
->pitches
[0]);
8011 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8012 intel_ring_emit(ring
, MI_NOOP
);
8014 intel_mark_page_flip_active(intel_crtc
);
8015 __intel_ring_advance(ring
);
8019 intel_unpin_fb_obj(obj
);
8024 static int intel_gen4_queue_flip(struct drm_device
*dev
,
8025 struct drm_crtc
*crtc
,
8026 struct drm_framebuffer
*fb
,
8027 struct drm_i915_gem_object
*obj
,
8030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8031 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8032 uint32_t pf
, pipesrc
;
8033 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8036 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8040 ret
= intel_ring_begin(ring
, 4);
8044 /* i965+ uses the linear or tiled offsets from the
8045 * Display Registers (which do not change across a page-flip)
8046 * so we need only reprogram the base address.
8048 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8049 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8050 intel_ring_emit(ring
, fb
->pitches
[0]);
8051 intel_ring_emit(ring
,
8052 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8055 /* XXX Enabling the panel-fitter across page-flip is so far
8056 * untested on non-native modes, so ignore it for now.
8057 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8060 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8061 intel_ring_emit(ring
, pf
| pipesrc
);
8063 intel_mark_page_flip_active(intel_crtc
);
8064 __intel_ring_advance(ring
);
8068 intel_unpin_fb_obj(obj
);
8073 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8074 struct drm_crtc
*crtc
,
8075 struct drm_framebuffer
*fb
,
8076 struct drm_i915_gem_object
*obj
,
8079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8080 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8081 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8082 uint32_t pf
, pipesrc
;
8085 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8089 ret
= intel_ring_begin(ring
, 4);
8093 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8094 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8095 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8096 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8098 /* Contrary to the suggestions in the documentation,
8099 * "Enable Panel Fitter" does not seem to be required when page
8100 * flipping with a non-native mode, and worse causes a normal
8102 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8105 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8106 intel_ring_emit(ring
, pf
| pipesrc
);
8108 intel_mark_page_flip_active(intel_crtc
);
8109 __intel_ring_advance(ring
);
8113 intel_unpin_fb_obj(obj
);
8118 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8119 struct drm_crtc
*crtc
,
8120 struct drm_framebuffer
*fb
,
8121 struct drm_i915_gem_object
*obj
,
8124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8126 struct intel_ring_buffer
*ring
;
8127 uint32_t plane_bit
= 0;
8131 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8132 ring
= &dev_priv
->ring
[BCS
];
8134 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8138 switch(intel_crtc
->plane
) {
8140 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8143 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8146 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8149 WARN_ONCE(1, "unknown plane in flip command\n");
8155 if (ring
->id
== RCS
)
8158 ret
= intel_ring_begin(ring
, len
);
8162 /* Unmask the flip-done completion message. Note that the bspec says that
8163 * we should do this for both the BCS and RCS, and that we must not unmask
8164 * more than one flip event at any time (or ensure that one flip message
8165 * can be sent by waiting for flip-done prior to queueing new flips).
8166 * Experimentation says that BCS works despite DERRMR masking all
8167 * flip-done completion events and that unmasking all planes at once
8168 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8169 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8171 if (ring
->id
== RCS
) {
8172 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8173 intel_ring_emit(ring
, DERRMR
);
8174 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8175 DERRMR_PIPEB_PRI_FLIP_DONE
|
8176 DERRMR_PIPEC_PRI_FLIP_DONE
));
8177 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8178 intel_ring_emit(ring
, DERRMR
);
8179 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8182 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8183 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8184 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8185 intel_ring_emit(ring
, (MI_NOOP
));
8187 intel_mark_page_flip_active(intel_crtc
);
8188 __intel_ring_advance(ring
);
8192 intel_unpin_fb_obj(obj
);
8197 static int intel_default_queue_flip(struct drm_device
*dev
,
8198 struct drm_crtc
*crtc
,
8199 struct drm_framebuffer
*fb
,
8200 struct drm_i915_gem_object
*obj
,
8206 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8207 struct drm_framebuffer
*fb
,
8208 struct drm_pending_vblank_event
*event
,
8209 uint32_t page_flip_flags
)
8211 struct drm_device
*dev
= crtc
->dev
;
8212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8213 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8214 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8215 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8216 struct intel_unpin_work
*work
;
8217 unsigned long flags
;
8220 /* Can't change pixel format via MI display flips. */
8221 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8225 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8226 * Note that pitch changes could also affect these register.
8228 if (INTEL_INFO(dev
)->gen
> 3 &&
8229 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8230 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8233 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8237 work
->event
= event
;
8239 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8240 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8242 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8246 /* We borrow the event spin lock for protecting unpin_work */
8247 spin_lock_irqsave(&dev
->event_lock
, flags
);
8248 if (intel_crtc
->unpin_work
) {
8249 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8251 drm_vblank_put(dev
, intel_crtc
->pipe
);
8253 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8256 intel_crtc
->unpin_work
= work
;
8257 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8259 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8260 flush_workqueue(dev_priv
->wq
);
8262 ret
= i915_mutex_lock_interruptible(dev
);
8266 /* Reference the objects for the scheduled work. */
8267 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8268 drm_gem_object_reference(&obj
->base
);
8272 work
->pending_flip_obj
= obj
;
8274 work
->enable_stall_check
= true;
8276 atomic_inc(&intel_crtc
->unpin_work_count
);
8277 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8279 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8281 goto cleanup_pending
;
8283 intel_disable_fbc(dev
);
8284 intel_mark_fb_busy(obj
, NULL
);
8285 mutex_unlock(&dev
->struct_mutex
);
8287 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8292 atomic_dec(&intel_crtc
->unpin_work_count
);
8294 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8295 drm_gem_object_unreference(&obj
->base
);
8296 mutex_unlock(&dev
->struct_mutex
);
8299 spin_lock_irqsave(&dev
->event_lock
, flags
);
8300 intel_crtc
->unpin_work
= NULL
;
8301 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8303 drm_vblank_put(dev
, intel_crtc
->pipe
);
8310 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8311 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8312 .load_lut
= intel_crtc_load_lut
,
8315 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8316 struct drm_crtc
*crtc
)
8318 struct drm_device
*dev
;
8319 struct drm_crtc
*tmp
;
8322 WARN(!crtc
, "checking null crtc?\n");
8326 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8332 if (encoder
->possible_crtcs
& crtc_mask
)
8338 * intel_modeset_update_staged_output_state
8340 * Updates the staged output configuration state, e.g. after we've read out the
8343 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8345 struct intel_encoder
*encoder
;
8346 struct intel_connector
*connector
;
8348 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8350 connector
->new_encoder
=
8351 to_intel_encoder(connector
->base
.encoder
);
8354 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8357 to_intel_crtc(encoder
->base
.crtc
);
8362 * intel_modeset_commit_output_state
8364 * This function copies the stage display pipe configuration to the real one.
8366 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8368 struct intel_encoder
*encoder
;
8369 struct intel_connector
*connector
;
8371 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8373 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8376 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8378 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8383 connected_sink_compute_bpp(struct intel_connector
* connector
,
8384 struct intel_crtc_config
*pipe_config
)
8386 int bpp
= pipe_config
->pipe_bpp
;
8388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8389 connector
->base
.base
.id
,
8390 drm_get_connector_name(&connector
->base
));
8392 /* Don't use an invalid EDID bpc value */
8393 if (connector
->base
.display_info
.bpc
&&
8394 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8395 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8396 bpp
, connector
->base
.display_info
.bpc
*3);
8397 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8400 /* Clamp bpp to 8 on screens without EDID 1.4 */
8401 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8402 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8404 pipe_config
->pipe_bpp
= 24;
8409 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8410 struct drm_framebuffer
*fb
,
8411 struct intel_crtc_config
*pipe_config
)
8413 struct drm_device
*dev
= crtc
->base
.dev
;
8414 struct intel_connector
*connector
;
8417 switch (fb
->pixel_format
) {
8419 bpp
= 8*3; /* since we go through a colormap */
8421 case DRM_FORMAT_XRGB1555
:
8422 case DRM_FORMAT_ARGB1555
:
8423 /* checked in intel_framebuffer_init already */
8424 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8426 case DRM_FORMAT_RGB565
:
8427 bpp
= 6*3; /* min is 18bpp */
8429 case DRM_FORMAT_XBGR8888
:
8430 case DRM_FORMAT_ABGR8888
:
8431 /* checked in intel_framebuffer_init already */
8432 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8434 case DRM_FORMAT_XRGB8888
:
8435 case DRM_FORMAT_ARGB8888
:
8438 case DRM_FORMAT_XRGB2101010
:
8439 case DRM_FORMAT_ARGB2101010
:
8440 case DRM_FORMAT_XBGR2101010
:
8441 case DRM_FORMAT_ABGR2101010
:
8442 /* checked in intel_framebuffer_init already */
8443 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8447 /* TODO: gen4+ supports 16 bpc floating point, too. */
8449 DRM_DEBUG_KMS("unsupported depth\n");
8453 pipe_config
->pipe_bpp
= bpp
;
8455 /* Clamp display bpp to EDID value */
8456 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8458 if (!connector
->new_encoder
||
8459 connector
->new_encoder
->new_crtc
!= crtc
)
8462 connected_sink_compute_bpp(connector
, pipe_config
);
8468 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8470 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8471 "type: 0x%x flags: 0x%x\n",
8473 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8474 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8475 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8476 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8479 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8480 struct intel_crtc_config
*pipe_config
,
8481 const char *context
)
8483 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8484 context
, pipe_name(crtc
->pipe
));
8486 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8487 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8488 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8489 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8490 pipe_config
->has_pch_encoder
,
8491 pipe_config
->fdi_lanes
,
8492 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8493 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8494 pipe_config
->fdi_m_n
.tu
);
8495 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8496 pipe_config
->has_dp_encoder
,
8497 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8498 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8499 pipe_config
->dp_m_n
.tu
);
8500 DRM_DEBUG_KMS("requested mode:\n");
8501 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8502 DRM_DEBUG_KMS("adjusted mode:\n");
8503 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8504 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8505 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8506 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8507 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8508 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8509 pipe_config
->gmch_pfit
.control
,
8510 pipe_config
->gmch_pfit
.pgm_ratios
,
8511 pipe_config
->gmch_pfit
.lvds_border_bits
);
8512 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8513 pipe_config
->pch_pfit
.pos
,
8514 pipe_config
->pch_pfit
.size
,
8515 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8516 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8517 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8520 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8522 int num_encoders
= 0;
8523 bool uncloneable_encoders
= false;
8524 struct intel_encoder
*encoder
;
8526 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8528 if (&encoder
->new_crtc
->base
!= crtc
)
8532 if (!encoder
->cloneable
)
8533 uncloneable_encoders
= true;
8536 return !(num_encoders
> 1 && uncloneable_encoders
);
8539 static struct intel_crtc_config
*
8540 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8541 struct drm_framebuffer
*fb
,
8542 struct drm_display_mode
*mode
)
8544 struct drm_device
*dev
= crtc
->dev
;
8545 struct intel_encoder
*encoder
;
8546 struct intel_crtc_config
*pipe_config
;
8547 int plane_bpp
, ret
= -EINVAL
;
8550 if (!check_encoder_cloning(crtc
)) {
8551 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8552 return ERR_PTR(-EINVAL
);
8555 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8557 return ERR_PTR(-ENOMEM
);
8559 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8560 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8562 pipe_config
->cpu_transcoder
=
8563 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8564 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8567 * Sanitize sync polarity flags based on requested ones. If neither
8568 * positive or negative polarity is requested, treat this as meaning
8569 * negative polarity.
8571 if (!(pipe_config
->adjusted_mode
.flags
&
8572 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8573 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8575 if (!(pipe_config
->adjusted_mode
.flags
&
8576 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8577 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8579 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8580 * plane pixel format and any sink constraints into account. Returns the
8581 * source plane bpp so that dithering can be selected on mismatches
8582 * after encoders and crtc also have had their say. */
8583 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8589 * Determine the real pipe dimensions. Note that stereo modes can
8590 * increase the actual pipe size due to the frame doubling and
8591 * insertion of additional space for blanks between the frame. This
8592 * is stored in the crtc timings. We use the requested mode to do this
8593 * computation to clearly distinguish it from the adjusted mode, which
8594 * can be changed by the connectors in the below retry loop.
8596 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
8597 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
8598 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
8601 /* Ensure the port clock defaults are reset when retrying. */
8602 pipe_config
->port_clock
= 0;
8603 pipe_config
->pixel_multiplier
= 1;
8605 /* Fill in default crtc timings, allow encoders to overwrite them. */
8606 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8608 /* Pass our mode to the connectors and the CRTC to give them a chance to
8609 * adjust it according to limitations or connector properties, and also
8610 * a chance to reject the mode entirely.
8612 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8615 if (&encoder
->new_crtc
->base
!= crtc
)
8618 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8619 DRM_DEBUG_KMS("Encoder config failure\n");
8624 /* Set default port clock if not overwritten by the encoder. Needs to be
8625 * done afterwards in case the encoder adjusts the mode. */
8626 if (!pipe_config
->port_clock
)
8627 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8628 * pipe_config
->pixel_multiplier
;
8630 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8632 DRM_DEBUG_KMS("CRTC fixup failed\n");
8637 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8642 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8647 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8648 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8649 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8654 return ERR_PTR(ret
);
8657 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8658 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8660 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8661 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8663 struct intel_crtc
*intel_crtc
;
8664 struct drm_device
*dev
= crtc
->dev
;
8665 struct intel_encoder
*encoder
;
8666 struct intel_connector
*connector
;
8667 struct drm_crtc
*tmp_crtc
;
8669 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8671 /* Check which crtcs have changed outputs connected to them, these need
8672 * to be part of the prepare_pipes mask. We don't (yet) support global
8673 * modeset across multiple crtcs, so modeset_pipes will only have one
8674 * bit set at most. */
8675 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8677 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8680 if (connector
->base
.encoder
) {
8681 tmp_crtc
= connector
->base
.encoder
->crtc
;
8683 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8686 if (connector
->new_encoder
)
8688 1 << connector
->new_encoder
->new_crtc
->pipe
;
8691 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8693 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8696 if (encoder
->base
.crtc
) {
8697 tmp_crtc
= encoder
->base
.crtc
;
8699 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8702 if (encoder
->new_crtc
)
8703 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8706 /* Check for any pipes that will be fully disabled ... */
8707 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8711 /* Don't try to disable disabled crtcs. */
8712 if (!intel_crtc
->base
.enabled
)
8715 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8717 if (encoder
->new_crtc
== intel_crtc
)
8722 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8726 /* set_mode is also used to update properties on life display pipes. */
8727 intel_crtc
= to_intel_crtc(crtc
);
8729 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8732 * For simplicity do a full modeset on any pipe where the output routing
8733 * changed. We could be more clever, but that would require us to be
8734 * more careful with calling the relevant encoder->mode_set functions.
8737 *modeset_pipes
= *prepare_pipes
;
8739 /* ... and mask these out. */
8740 *modeset_pipes
&= ~(*disable_pipes
);
8741 *prepare_pipes
&= ~(*disable_pipes
);
8744 * HACK: We don't (yet) fully support global modesets. intel_set_config
8745 * obies this rule, but the modeset restore mode of
8746 * intel_modeset_setup_hw_state does not.
8748 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8749 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8751 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8752 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8755 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8757 struct drm_encoder
*encoder
;
8758 struct drm_device
*dev
= crtc
->dev
;
8760 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8761 if (encoder
->crtc
== crtc
)
8768 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8770 struct intel_encoder
*intel_encoder
;
8771 struct intel_crtc
*intel_crtc
;
8772 struct drm_connector
*connector
;
8774 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8776 if (!intel_encoder
->base
.crtc
)
8779 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8781 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8782 intel_encoder
->connectors_active
= false;
8785 intel_modeset_commit_output_state(dev
);
8787 /* Update computed state. */
8788 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8790 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8793 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8794 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8797 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8799 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8800 struct drm_property
*dpms_property
=
8801 dev
->mode_config
.dpms_property
;
8803 connector
->dpms
= DRM_MODE_DPMS_ON
;
8804 drm_object_property_set_value(&connector
->base
,
8808 intel_encoder
= to_intel_encoder(connector
->encoder
);
8809 intel_encoder
->connectors_active
= true;
8815 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8819 if (clock1
== clock2
)
8822 if (!clock1
|| !clock2
)
8825 diff
= abs(clock1
- clock2
);
8827 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8833 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8834 list_for_each_entry((intel_crtc), \
8835 &(dev)->mode_config.crtc_list, \
8837 if (mask & (1 <<(intel_crtc)->pipe))
8840 intel_pipe_config_compare(struct drm_device
*dev
,
8841 struct intel_crtc_config
*current_config
,
8842 struct intel_crtc_config
*pipe_config
)
8844 #define PIPE_CONF_CHECK_X(name) \
8845 if (current_config->name != pipe_config->name) { \
8846 DRM_ERROR("mismatch in " #name " " \
8847 "(expected 0x%08x, found 0x%08x)\n", \
8848 current_config->name, \
8849 pipe_config->name); \
8853 #define PIPE_CONF_CHECK_I(name) \
8854 if (current_config->name != pipe_config->name) { \
8855 DRM_ERROR("mismatch in " #name " " \
8856 "(expected %i, found %i)\n", \
8857 current_config->name, \
8858 pipe_config->name); \
8862 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8863 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8864 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8865 "(expected %i, found %i)\n", \
8866 current_config->name & (mask), \
8867 pipe_config->name & (mask)); \
8871 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8872 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8873 DRM_ERROR("mismatch in " #name " " \
8874 "(expected %i, found %i)\n", \
8875 current_config->name, \
8876 pipe_config->name); \
8880 #define PIPE_CONF_QUIRK(quirk) \
8881 ((current_config->quirks | pipe_config->quirks) & (quirk))
8883 PIPE_CONF_CHECK_I(cpu_transcoder
);
8885 PIPE_CONF_CHECK_I(has_pch_encoder
);
8886 PIPE_CONF_CHECK_I(fdi_lanes
);
8887 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8888 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8889 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8890 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8891 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8893 PIPE_CONF_CHECK_I(has_dp_encoder
);
8894 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8895 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8896 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8897 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8898 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8900 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8901 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8902 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8903 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8904 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8905 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8907 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8908 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8909 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8910 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8911 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8912 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8914 PIPE_CONF_CHECK_I(pixel_multiplier
);
8916 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8917 DRM_MODE_FLAG_INTERLACE
);
8919 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8920 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8921 DRM_MODE_FLAG_PHSYNC
);
8922 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8923 DRM_MODE_FLAG_NHSYNC
);
8924 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8925 DRM_MODE_FLAG_PVSYNC
);
8926 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8927 DRM_MODE_FLAG_NVSYNC
);
8930 PIPE_CONF_CHECK_I(pipe_src_w
);
8931 PIPE_CONF_CHECK_I(pipe_src_h
);
8933 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8934 /* pfit ratios are autocomputed by the hw on gen4+ */
8935 if (INTEL_INFO(dev
)->gen
< 4)
8936 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8937 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8938 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8939 if (current_config
->pch_pfit
.enabled
) {
8940 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8941 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8944 PIPE_CONF_CHECK_I(ips_enabled
);
8946 PIPE_CONF_CHECK_I(double_wide
);
8948 PIPE_CONF_CHECK_I(shared_dpll
);
8949 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8950 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8951 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8952 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8954 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8955 PIPE_CONF_CHECK_I(pipe_bpp
);
8957 if (!IS_HASWELL(dev
)) {
8958 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
8959 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8962 #undef PIPE_CONF_CHECK_X
8963 #undef PIPE_CONF_CHECK_I
8964 #undef PIPE_CONF_CHECK_FLAGS
8965 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8966 #undef PIPE_CONF_QUIRK
8972 check_connector_state(struct drm_device
*dev
)
8974 struct intel_connector
*connector
;
8976 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8978 /* This also checks the encoder/connector hw state with the
8979 * ->get_hw_state callbacks. */
8980 intel_connector_check_state(connector
);
8982 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8983 "connector's staged encoder doesn't match current encoder\n");
8988 check_encoder_state(struct drm_device
*dev
)
8990 struct intel_encoder
*encoder
;
8991 struct intel_connector
*connector
;
8993 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8995 bool enabled
= false;
8996 bool active
= false;
8997 enum pipe pipe
, tracked_pipe
;
8999 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9000 encoder
->base
.base
.id
,
9001 drm_get_encoder_name(&encoder
->base
));
9003 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
9004 "encoder's stage crtc doesn't match current crtc\n");
9005 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
9006 "encoder's active_connectors set, but no crtc\n");
9008 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9010 if (connector
->base
.encoder
!= &encoder
->base
)
9013 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
9016 WARN(!!encoder
->base
.crtc
!= enabled
,
9017 "encoder's enabled state mismatch "
9018 "(expected %i, found %i)\n",
9019 !!encoder
->base
.crtc
, enabled
);
9020 WARN(active
&& !encoder
->base
.crtc
,
9021 "active encoder with no crtc\n");
9023 WARN(encoder
->connectors_active
!= active
,
9024 "encoder's computed active state doesn't match tracked active state "
9025 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
9027 active
= encoder
->get_hw_state(encoder
, &pipe
);
9028 WARN(active
!= encoder
->connectors_active
,
9029 "encoder's hw state doesn't match sw tracking "
9030 "(expected %i, found %i)\n",
9031 encoder
->connectors_active
, active
);
9033 if (!encoder
->base
.crtc
)
9036 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9037 WARN(active
&& pipe
!= tracked_pipe
,
9038 "active encoder's pipe doesn't match"
9039 "(expected %i, found %i)\n",
9040 tracked_pipe
, pipe
);
9046 check_crtc_state(struct drm_device
*dev
)
9048 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9049 struct intel_crtc
*crtc
;
9050 struct intel_encoder
*encoder
;
9051 struct intel_crtc_config pipe_config
;
9053 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9055 bool enabled
= false;
9056 bool active
= false;
9058 memset(&pipe_config
, 0, sizeof(pipe_config
));
9060 DRM_DEBUG_KMS("[CRTC:%d]\n",
9061 crtc
->base
.base
.id
);
9063 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9064 "active crtc, but not enabled in sw tracking\n");
9066 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9068 if (encoder
->base
.crtc
!= &crtc
->base
)
9071 if (encoder
->connectors_active
)
9075 WARN(active
!= crtc
->active
,
9076 "crtc's computed active state doesn't match tracked active state "
9077 "(expected %i, found %i)\n", active
, crtc
->active
);
9078 WARN(enabled
!= crtc
->base
.enabled
,
9079 "crtc's computed enabled state doesn't match tracked enabled state "
9080 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9082 active
= dev_priv
->display
.get_pipe_config(crtc
,
9085 /* hw state is inconsistent with the pipe A quirk */
9086 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9087 active
= crtc
->active
;
9089 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9092 if (encoder
->base
.crtc
!= &crtc
->base
)
9094 if (encoder
->get_config
&&
9095 encoder
->get_hw_state(encoder
, &pipe
))
9096 encoder
->get_config(encoder
, &pipe_config
);
9099 WARN(crtc
->active
!= active
,
9100 "crtc active state doesn't match with hw state "
9101 "(expected %i, found %i)\n", crtc
->active
, active
);
9104 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9105 WARN(1, "pipe state doesn't match!\n");
9106 intel_dump_pipe_config(crtc
, &pipe_config
,
9108 intel_dump_pipe_config(crtc
, &crtc
->config
,
9115 check_shared_dpll_state(struct drm_device
*dev
)
9117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9118 struct intel_crtc
*crtc
;
9119 struct intel_dpll_hw_state dpll_hw_state
;
9122 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9123 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9124 int enabled_crtcs
= 0, active_crtcs
= 0;
9127 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9129 DRM_DEBUG_KMS("%s\n", pll
->name
);
9131 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9133 WARN(pll
->active
> pll
->refcount
,
9134 "more active pll users than references: %i vs %i\n",
9135 pll
->active
, pll
->refcount
);
9136 WARN(pll
->active
&& !pll
->on
,
9137 "pll in active use but not on in sw tracking\n");
9138 WARN(pll
->on
&& !pll
->active
,
9139 "pll in on but not on in use in sw tracking\n");
9140 WARN(pll
->on
!= active
,
9141 "pll on state mismatch (expected %i, found %i)\n",
9144 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9146 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9148 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9151 WARN(pll
->active
!= active_crtcs
,
9152 "pll active crtcs mismatch (expected %i, found %i)\n",
9153 pll
->active
, active_crtcs
);
9154 WARN(pll
->refcount
!= enabled_crtcs
,
9155 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9156 pll
->refcount
, enabled_crtcs
);
9158 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9159 sizeof(dpll_hw_state
)),
9160 "pll hw state mismatch\n");
9165 intel_modeset_check_state(struct drm_device
*dev
)
9167 check_connector_state(dev
);
9168 check_encoder_state(dev
);
9169 check_crtc_state(dev
);
9170 check_shared_dpll_state(dev
);
9173 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9177 * FDI already provided one idea for the dotclock.
9178 * Yell if the encoder disagrees.
9180 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9181 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9182 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9185 static int __intel_set_mode(struct drm_crtc
*crtc
,
9186 struct drm_display_mode
*mode
,
9187 int x
, int y
, struct drm_framebuffer
*fb
)
9189 struct drm_device
*dev
= crtc
->dev
;
9190 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9191 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9192 struct intel_crtc_config
*pipe_config
= NULL
;
9193 struct intel_crtc
*intel_crtc
;
9194 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9197 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9200 saved_hwmode
= saved_mode
+ 1;
9202 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9203 &prepare_pipes
, &disable_pipes
);
9205 *saved_hwmode
= crtc
->hwmode
;
9206 *saved_mode
= crtc
->mode
;
9208 /* Hack: Because we don't (yet) support global modeset on multiple
9209 * crtcs, we don't keep track of the new mode for more than one crtc.
9210 * Hence simply check whether any bit is set in modeset_pipes in all the
9211 * pieces of code that are not yet converted to deal with mutliple crtcs
9212 * changing their mode at the same time. */
9213 if (modeset_pipes
) {
9214 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9215 if (IS_ERR(pipe_config
)) {
9216 ret
= PTR_ERR(pipe_config
);
9221 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9225 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9226 intel_crtc_disable(&intel_crtc
->base
);
9228 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9229 if (intel_crtc
->base
.enabled
)
9230 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9233 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9234 * to set it here already despite that we pass it down the callchain.
9236 if (modeset_pipes
) {
9238 /* mode_set/enable/disable functions rely on a correct pipe
9240 to_intel_crtc(crtc
)->config
= *pipe_config
;
9243 /* Only after disabling all output pipelines that will be changed can we
9244 * update the the output configuration. */
9245 intel_modeset_update_state(dev
, prepare_pipes
);
9247 if (dev_priv
->display
.modeset_global_resources
)
9248 dev_priv
->display
.modeset_global_resources(dev
);
9250 /* Set up the DPLL and any encoders state that needs to adjust or depend
9253 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9254 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9260 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9261 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9262 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9264 if (modeset_pipes
) {
9265 /* Store real post-adjustment hardware mode. */
9266 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9268 /* Calculate and store various constants which
9269 * are later needed by vblank and swap-completion
9270 * timestamping. They are derived from true hwmode.
9272 drm_calc_timestamping_constants(crtc
);
9275 /* FIXME: add subpixel order */
9277 if (ret
&& crtc
->enabled
) {
9278 crtc
->hwmode
= *saved_hwmode
;
9279 crtc
->mode
= *saved_mode
;
9288 static int intel_set_mode(struct drm_crtc
*crtc
,
9289 struct drm_display_mode
*mode
,
9290 int x
, int y
, struct drm_framebuffer
*fb
)
9294 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9297 intel_modeset_check_state(crtc
->dev
);
9302 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9304 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9307 #undef for_each_intel_crtc_masked
9309 static void intel_set_config_free(struct intel_set_config
*config
)
9314 kfree(config
->save_connector_encoders
);
9315 kfree(config
->save_encoder_crtcs
);
9319 static int intel_set_config_save_state(struct drm_device
*dev
,
9320 struct intel_set_config
*config
)
9322 struct drm_encoder
*encoder
;
9323 struct drm_connector
*connector
;
9326 config
->save_encoder_crtcs
=
9327 kcalloc(dev
->mode_config
.num_encoder
,
9328 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9329 if (!config
->save_encoder_crtcs
)
9332 config
->save_connector_encoders
=
9333 kcalloc(dev
->mode_config
.num_connector
,
9334 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9335 if (!config
->save_connector_encoders
)
9338 /* Copy data. Note that driver private data is not affected.
9339 * Should anything bad happen only the expected state is
9340 * restored, not the drivers personal bookkeeping.
9343 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9344 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9348 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9349 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9355 static void intel_set_config_restore_state(struct drm_device
*dev
,
9356 struct intel_set_config
*config
)
9358 struct intel_encoder
*encoder
;
9359 struct intel_connector
*connector
;
9363 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9365 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9369 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9370 connector
->new_encoder
=
9371 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9376 is_crtc_connector_off(struct drm_mode_set
*set
)
9380 if (set
->num_connectors
== 0)
9383 if (WARN_ON(set
->connectors
== NULL
))
9386 for (i
= 0; i
< set
->num_connectors
; i
++)
9387 if (set
->connectors
[i
]->encoder
&&
9388 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9389 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9396 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9397 struct intel_set_config
*config
)
9400 /* We should be able to check here if the fb has the same properties
9401 * and then just flip_or_move it */
9402 if (is_crtc_connector_off(set
)) {
9403 config
->mode_changed
= true;
9404 } else if (set
->crtc
->fb
!= set
->fb
) {
9405 /* If we have no fb then treat it as a full mode set */
9406 if (set
->crtc
->fb
== NULL
) {
9407 struct intel_crtc
*intel_crtc
=
9408 to_intel_crtc(set
->crtc
);
9410 if (intel_crtc
->active
&& i915_fastboot
) {
9411 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9412 config
->fb_changed
= true;
9414 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9415 config
->mode_changed
= true;
9417 } else if (set
->fb
== NULL
) {
9418 config
->mode_changed
= true;
9419 } else if (set
->fb
->pixel_format
!=
9420 set
->crtc
->fb
->pixel_format
) {
9421 config
->mode_changed
= true;
9423 config
->fb_changed
= true;
9427 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9428 config
->fb_changed
= true;
9430 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9431 DRM_DEBUG_KMS("modes are different, full mode set\n");
9432 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9433 drm_mode_debug_printmodeline(set
->mode
);
9434 config
->mode_changed
= true;
9437 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9438 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9442 intel_modeset_stage_output_state(struct drm_device
*dev
,
9443 struct drm_mode_set
*set
,
9444 struct intel_set_config
*config
)
9446 struct drm_crtc
*new_crtc
;
9447 struct intel_connector
*connector
;
9448 struct intel_encoder
*encoder
;
9451 /* The upper layers ensure that we either disable a crtc or have a list
9452 * of connectors. For paranoia, double-check this. */
9453 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9454 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9456 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9458 /* Otherwise traverse passed in connector list and get encoders
9460 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9461 if (set
->connectors
[ro
] == &connector
->base
) {
9462 connector
->new_encoder
= connector
->encoder
;
9467 /* If we disable the crtc, disable all its connectors. Also, if
9468 * the connector is on the changing crtc but not on the new
9469 * connector list, disable it. */
9470 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9471 connector
->base
.encoder
&&
9472 connector
->base
.encoder
->crtc
== set
->crtc
) {
9473 connector
->new_encoder
= NULL
;
9475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9476 connector
->base
.base
.id
,
9477 drm_get_connector_name(&connector
->base
));
9481 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9482 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9483 config
->mode_changed
= true;
9486 /* connector->new_encoder is now updated for all connectors. */
9488 /* Update crtc of enabled connectors. */
9489 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9491 if (!connector
->new_encoder
)
9494 new_crtc
= connector
->new_encoder
->base
.crtc
;
9496 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9497 if (set
->connectors
[ro
] == &connector
->base
)
9498 new_crtc
= set
->crtc
;
9501 /* Make sure the new CRTC will work with the encoder */
9502 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9506 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9509 connector
->base
.base
.id
,
9510 drm_get_connector_name(&connector
->base
),
9514 /* Check for any encoders that needs to be disabled. */
9515 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9517 list_for_each_entry(connector
,
9518 &dev
->mode_config
.connector_list
,
9520 if (connector
->new_encoder
== encoder
) {
9521 WARN_ON(!connector
->new_encoder
->new_crtc
);
9526 encoder
->new_crtc
= NULL
;
9528 /* Only now check for crtc changes so we don't miss encoders
9529 * that will be disabled. */
9530 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9531 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9532 config
->mode_changed
= true;
9535 /* Now we've also updated encoder->new_crtc for all encoders. */
9540 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9542 struct drm_device
*dev
;
9543 struct drm_mode_set save_set
;
9544 struct intel_set_config
*config
;
9549 BUG_ON(!set
->crtc
->helper_private
);
9551 /* Enforce sane interface api - has been abused by the fb helper. */
9552 BUG_ON(!set
->mode
&& set
->fb
);
9553 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9556 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9557 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9558 (int)set
->num_connectors
, set
->x
, set
->y
);
9560 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9563 dev
= set
->crtc
->dev
;
9566 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9570 ret
= intel_set_config_save_state(dev
, config
);
9574 save_set
.crtc
= set
->crtc
;
9575 save_set
.mode
= &set
->crtc
->mode
;
9576 save_set
.x
= set
->crtc
->x
;
9577 save_set
.y
= set
->crtc
->y
;
9578 save_set
.fb
= set
->crtc
->fb
;
9580 /* Compute whether we need a full modeset, only an fb base update or no
9581 * change at all. In the future we might also check whether only the
9582 * mode changed, e.g. for LVDS where we only change the panel fitter in
9584 intel_set_config_compute_mode_changes(set
, config
);
9586 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9590 if (config
->mode_changed
) {
9591 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9592 set
->x
, set
->y
, set
->fb
);
9593 } else if (config
->fb_changed
) {
9594 intel_crtc_wait_for_pending_flips(set
->crtc
);
9596 ret
= intel_pipe_set_base(set
->crtc
,
9597 set
->x
, set
->y
, set
->fb
);
9601 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9602 set
->crtc
->base
.id
, ret
);
9604 intel_set_config_restore_state(dev
, config
);
9606 /* Try to restore the config */
9607 if (config
->mode_changed
&&
9608 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9609 save_set
.x
, save_set
.y
, save_set
.fb
))
9610 DRM_ERROR("failed to restore config after modeset failure\n");
9614 intel_set_config_free(config
);
9618 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9619 .cursor_set
= intel_crtc_cursor_set
,
9620 .cursor_move
= intel_crtc_cursor_move
,
9621 .gamma_set
= intel_crtc_gamma_set
,
9622 .set_config
= intel_crtc_set_config
,
9623 .destroy
= intel_crtc_destroy
,
9624 .page_flip
= intel_crtc_page_flip
,
9627 static void intel_cpu_pll_init(struct drm_device
*dev
)
9630 intel_ddi_pll_init(dev
);
9633 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9634 struct intel_shared_dpll
*pll
,
9635 struct intel_dpll_hw_state
*hw_state
)
9639 val
= I915_READ(PCH_DPLL(pll
->id
));
9640 hw_state
->dpll
= val
;
9641 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9642 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9644 return val
& DPLL_VCO_ENABLE
;
9647 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9648 struct intel_shared_dpll
*pll
)
9650 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9651 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9654 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9655 struct intel_shared_dpll
*pll
)
9657 /* PCH refclock must be enabled first */
9658 assert_pch_refclk_enabled(dev_priv
);
9660 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9662 /* Wait for the clocks to stabilize. */
9663 POSTING_READ(PCH_DPLL(pll
->id
));
9666 /* The pixel multiplier can only be updated once the
9667 * DPLL is enabled and the clocks are stable.
9669 * So write it again.
9671 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9672 POSTING_READ(PCH_DPLL(pll
->id
));
9676 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9677 struct intel_shared_dpll
*pll
)
9679 struct drm_device
*dev
= dev_priv
->dev
;
9680 struct intel_crtc
*crtc
;
9682 /* Make sure no transcoder isn't still depending on us. */
9683 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9684 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9685 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9688 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9689 POSTING_READ(PCH_DPLL(pll
->id
));
9693 static char *ibx_pch_dpll_names
[] = {
9698 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9703 dev_priv
->num_shared_dpll
= 2;
9705 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9706 dev_priv
->shared_dplls
[i
].id
= i
;
9707 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9708 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9709 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9710 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9711 dev_priv
->shared_dplls
[i
].get_hw_state
=
9712 ibx_pch_dpll_get_hw_state
;
9716 static void intel_shared_dpll_init(struct drm_device
*dev
)
9718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9720 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9721 ibx_pch_dpll_init(dev
);
9723 dev_priv
->num_shared_dpll
= 0;
9725 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9726 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9727 dev_priv
->num_shared_dpll
);
9730 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9732 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9733 struct intel_crtc
*intel_crtc
;
9736 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9737 if (intel_crtc
== NULL
)
9740 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9742 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9743 for (i
= 0; i
< 256; i
++) {
9744 intel_crtc
->lut_r
[i
] = i
;
9745 intel_crtc
->lut_g
[i
] = i
;
9746 intel_crtc
->lut_b
[i
] = i
;
9749 /* Swap pipes & planes for FBC on pre-965 */
9750 intel_crtc
->pipe
= pipe
;
9751 intel_crtc
->plane
= pipe
;
9752 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9753 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9754 intel_crtc
->plane
= !pipe
;
9757 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9758 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9759 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9760 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9762 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9765 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9766 struct drm_file
*file
)
9768 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9769 struct drm_mode_object
*drmmode_obj
;
9770 struct intel_crtc
*crtc
;
9772 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9775 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9776 DRM_MODE_OBJECT_CRTC
);
9779 DRM_ERROR("no such CRTC id\n");
9783 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9784 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9789 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9791 struct drm_device
*dev
= encoder
->base
.dev
;
9792 struct intel_encoder
*source_encoder
;
9796 list_for_each_entry(source_encoder
,
9797 &dev
->mode_config
.encoder_list
, base
.head
) {
9799 if (encoder
== source_encoder
)
9800 index_mask
|= (1 << entry
);
9802 /* Intel hw has only one MUX where enocoders could be cloned. */
9803 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9804 index_mask
|= (1 << entry
);
9812 static bool has_edp_a(struct drm_device
*dev
)
9814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9816 if (!IS_MOBILE(dev
))
9819 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9823 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9829 static void intel_setup_outputs(struct drm_device
*dev
)
9831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9832 struct intel_encoder
*encoder
;
9833 bool dpd_is_edp
= false;
9835 intel_lvds_init(dev
);
9838 intel_crt_init(dev
);
9843 /* Haswell uses DDI functions to detect digital outputs */
9844 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9845 /* DDI A only supports eDP */
9847 intel_ddi_init(dev
, PORT_A
);
9849 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9851 found
= I915_READ(SFUSE_STRAP
);
9853 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9854 intel_ddi_init(dev
, PORT_B
);
9855 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9856 intel_ddi_init(dev
, PORT_C
);
9857 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9858 intel_ddi_init(dev
, PORT_D
);
9859 } else if (HAS_PCH_SPLIT(dev
)) {
9861 dpd_is_edp
= intel_dpd_is_edp(dev
);
9864 intel_dp_init(dev
, DP_A
, PORT_A
);
9866 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9867 /* PCH SDVOB multiplex with HDMIB */
9868 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9870 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9871 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9872 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9875 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9876 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9878 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9879 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9881 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9882 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9884 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9885 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9886 } else if (IS_VALLEYVIEW(dev
)) {
9887 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9888 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9889 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9891 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9892 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9896 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9897 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9899 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9900 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9903 intel_dsi_init(dev
);
9904 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9907 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9908 DRM_DEBUG_KMS("probing SDVOB\n");
9909 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9910 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9911 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9912 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9915 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9916 intel_dp_init(dev
, DP_B
, PORT_B
);
9919 /* Before G4X SDVOC doesn't have its own detect register */
9921 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9922 DRM_DEBUG_KMS("probing SDVOC\n");
9923 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9926 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9928 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9929 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9930 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9932 if (SUPPORTS_INTEGRATED_DP(dev
))
9933 intel_dp_init(dev
, DP_C
, PORT_C
);
9936 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9937 (I915_READ(DP_D
) & DP_DETECTED
))
9938 intel_dp_init(dev
, DP_D
, PORT_D
);
9939 } else if (IS_GEN2(dev
))
9940 intel_dvo_init(dev
);
9942 if (SUPPORTS_TV(dev
))
9945 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9946 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9947 encoder
->base
.possible_clones
=
9948 intel_encoder_clones(encoder
);
9951 intel_init_pch_refclk(dev
);
9953 drm_helper_move_panel_connectors_to_head(dev
);
9956 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9958 drm_framebuffer_cleanup(&fb
->base
);
9959 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9962 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9964 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9966 intel_framebuffer_fini(intel_fb
);
9970 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9971 struct drm_file
*file
,
9972 unsigned int *handle
)
9974 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9975 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9977 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9980 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9981 .destroy
= intel_user_framebuffer_destroy
,
9982 .create_handle
= intel_user_framebuffer_create_handle
,
9985 int intel_framebuffer_init(struct drm_device
*dev
,
9986 struct intel_framebuffer
*intel_fb
,
9987 struct drm_mode_fb_cmd2
*mode_cmd
,
9988 struct drm_i915_gem_object
*obj
)
9993 if (obj
->tiling_mode
== I915_TILING_Y
) {
9994 DRM_DEBUG("hardware does not support tiling Y\n");
9998 if (mode_cmd
->pitches
[0] & 63) {
9999 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10000 mode_cmd
->pitches
[0]);
10004 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
10005 pitch_limit
= 32*1024;
10006 } else if (INTEL_INFO(dev
)->gen
>= 4) {
10007 if (obj
->tiling_mode
)
10008 pitch_limit
= 16*1024;
10010 pitch_limit
= 32*1024;
10011 } else if (INTEL_INFO(dev
)->gen
>= 3) {
10012 if (obj
->tiling_mode
)
10013 pitch_limit
= 8*1024;
10015 pitch_limit
= 16*1024;
10017 /* XXX DSPC is limited to 4k tiled */
10018 pitch_limit
= 8*1024;
10020 if (mode_cmd
->pitches
[0] > pitch_limit
) {
10021 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10022 obj
->tiling_mode
? "tiled" : "linear",
10023 mode_cmd
->pitches
[0], pitch_limit
);
10027 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
10028 mode_cmd
->pitches
[0] != obj
->stride
) {
10029 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10030 mode_cmd
->pitches
[0], obj
->stride
);
10034 /* Reject formats not supported by any plane early. */
10035 switch (mode_cmd
->pixel_format
) {
10036 case DRM_FORMAT_C8
:
10037 case DRM_FORMAT_RGB565
:
10038 case DRM_FORMAT_XRGB8888
:
10039 case DRM_FORMAT_ARGB8888
:
10041 case DRM_FORMAT_XRGB1555
:
10042 case DRM_FORMAT_ARGB1555
:
10043 if (INTEL_INFO(dev
)->gen
> 3) {
10044 DRM_DEBUG("unsupported pixel format: %s\n",
10045 drm_get_format_name(mode_cmd
->pixel_format
));
10049 case DRM_FORMAT_XBGR8888
:
10050 case DRM_FORMAT_ABGR8888
:
10051 case DRM_FORMAT_XRGB2101010
:
10052 case DRM_FORMAT_ARGB2101010
:
10053 case DRM_FORMAT_XBGR2101010
:
10054 case DRM_FORMAT_ABGR2101010
:
10055 if (INTEL_INFO(dev
)->gen
< 4) {
10056 DRM_DEBUG("unsupported pixel format: %s\n",
10057 drm_get_format_name(mode_cmd
->pixel_format
));
10061 case DRM_FORMAT_YUYV
:
10062 case DRM_FORMAT_UYVY
:
10063 case DRM_FORMAT_YVYU
:
10064 case DRM_FORMAT_VYUY
:
10065 if (INTEL_INFO(dev
)->gen
< 5) {
10066 DRM_DEBUG("unsupported pixel format: %s\n",
10067 drm_get_format_name(mode_cmd
->pixel_format
));
10072 DRM_DEBUG("unsupported pixel format: %s\n",
10073 drm_get_format_name(mode_cmd
->pixel_format
));
10077 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10078 if (mode_cmd
->offsets
[0] != 0)
10081 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10082 intel_fb
->obj
= obj
;
10084 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10086 DRM_ERROR("framebuffer init failed %d\n", ret
);
10093 static struct drm_framebuffer
*
10094 intel_user_framebuffer_create(struct drm_device
*dev
,
10095 struct drm_file
*filp
,
10096 struct drm_mode_fb_cmd2
*mode_cmd
)
10098 struct drm_i915_gem_object
*obj
;
10100 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10101 mode_cmd
->handles
[0]));
10102 if (&obj
->base
== NULL
)
10103 return ERR_PTR(-ENOENT
);
10105 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10108 #ifndef CONFIG_DRM_I915_FBDEV
10109 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
10114 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10115 .fb_create
= intel_user_framebuffer_create
,
10116 .output_poll_changed
= intel_fbdev_output_poll_changed
,
10119 /* Set up chip specific display functions */
10120 static void intel_init_display(struct drm_device
*dev
)
10122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10124 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10125 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10126 else if (IS_VALLEYVIEW(dev
))
10127 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10128 else if (IS_PINEVIEW(dev
))
10129 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10131 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10133 if (HAS_DDI(dev
)) {
10134 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10135 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10136 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10137 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10138 dev_priv
->display
.off
= haswell_crtc_off
;
10139 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10140 } else if (HAS_PCH_SPLIT(dev
)) {
10141 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10142 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10143 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10144 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10145 dev_priv
->display
.off
= ironlake_crtc_off
;
10146 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10147 } else if (IS_VALLEYVIEW(dev
)) {
10148 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10149 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10150 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10151 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10152 dev_priv
->display
.off
= i9xx_crtc_off
;
10153 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10155 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10156 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10157 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10158 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10159 dev_priv
->display
.off
= i9xx_crtc_off
;
10160 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10163 /* Returns the core display clock speed */
10164 if (IS_VALLEYVIEW(dev
))
10165 dev_priv
->display
.get_display_clock_speed
=
10166 valleyview_get_display_clock_speed
;
10167 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10168 dev_priv
->display
.get_display_clock_speed
=
10169 i945_get_display_clock_speed
;
10170 else if (IS_I915G(dev
))
10171 dev_priv
->display
.get_display_clock_speed
=
10172 i915_get_display_clock_speed
;
10173 else if (IS_I945GM(dev
) || IS_845G(dev
))
10174 dev_priv
->display
.get_display_clock_speed
=
10175 i9xx_misc_get_display_clock_speed
;
10176 else if (IS_PINEVIEW(dev
))
10177 dev_priv
->display
.get_display_clock_speed
=
10178 pnv_get_display_clock_speed
;
10179 else if (IS_I915GM(dev
))
10180 dev_priv
->display
.get_display_clock_speed
=
10181 i915gm_get_display_clock_speed
;
10182 else if (IS_I865G(dev
))
10183 dev_priv
->display
.get_display_clock_speed
=
10184 i865_get_display_clock_speed
;
10185 else if (IS_I85X(dev
))
10186 dev_priv
->display
.get_display_clock_speed
=
10187 i855_get_display_clock_speed
;
10188 else /* 852, 830 */
10189 dev_priv
->display
.get_display_clock_speed
=
10190 i830_get_display_clock_speed
;
10192 if (HAS_PCH_SPLIT(dev
)) {
10193 if (IS_GEN5(dev
)) {
10194 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10195 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10196 } else if (IS_GEN6(dev
)) {
10197 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10198 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10199 } else if (IS_IVYBRIDGE(dev
)) {
10200 /* FIXME: detect B0+ stepping and use auto training */
10201 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10202 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10203 dev_priv
->display
.modeset_global_resources
=
10204 ivb_modeset_global_resources
;
10205 } else if (IS_HASWELL(dev
)) {
10206 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10207 dev_priv
->display
.write_eld
= haswell_write_eld
;
10208 dev_priv
->display
.modeset_global_resources
=
10209 haswell_modeset_global_resources
;
10211 } else if (IS_G4X(dev
)) {
10212 dev_priv
->display
.write_eld
= g4x_write_eld
;
10215 /* Default just returns -ENODEV to indicate unsupported */
10216 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10218 switch (INTEL_INFO(dev
)->gen
) {
10220 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10224 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10229 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10233 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10236 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10242 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10243 * resume, or other times. This quirk makes sure that's the case for
10244 * affected systems.
10246 static void quirk_pipea_force(struct drm_device
*dev
)
10248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10250 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10251 DRM_INFO("applying pipe a force quirk\n");
10255 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10257 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10260 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10261 DRM_INFO("applying lvds SSC disable quirk\n");
10265 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10268 static void quirk_invert_brightness(struct drm_device
*dev
)
10270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10271 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10272 DRM_INFO("applying inverted panel brightness quirk\n");
10276 * Some machines (Dell XPS13) suffer broken backlight controls if
10277 * BLM_PCH_PWM_ENABLE is set.
10279 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10282 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10283 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10286 struct intel_quirk
{
10288 int subsystem_vendor
;
10289 int subsystem_device
;
10290 void (*hook
)(struct drm_device
*dev
);
10293 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10294 struct intel_dmi_quirk
{
10295 void (*hook
)(struct drm_device
*dev
);
10296 const struct dmi_system_id (*dmi_id_list
)[];
10299 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10301 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10305 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10307 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10309 .callback
= intel_dmi_reverse_brightness
,
10310 .ident
= "NCR Corporation",
10311 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10312 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10315 { } /* terminating entry */
10317 .hook
= quirk_invert_brightness
,
10321 static struct intel_quirk intel_quirks
[] = {
10322 /* HP Mini needs pipe A force quirk (LP: #322104) */
10323 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10325 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10326 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10328 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10329 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10331 /* 830 needs to leave pipe A & dpll A up */
10332 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10334 /* Lenovo U160 cannot use SSC on LVDS */
10335 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10337 /* Sony Vaio Y cannot use SSC on LVDS */
10338 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10341 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10342 * seem to use inverted backlight PWM.
10344 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10346 /* Dell XPS13 HD Sandy Bridge */
10347 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10348 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10349 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10352 static void intel_init_quirks(struct drm_device
*dev
)
10354 struct pci_dev
*d
= dev
->pdev
;
10357 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10358 struct intel_quirk
*q
= &intel_quirks
[i
];
10360 if (d
->device
== q
->device
&&
10361 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10362 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10363 (d
->subsystem_device
== q
->subsystem_device
||
10364 q
->subsystem_device
== PCI_ANY_ID
))
10367 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10368 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10369 intel_dmi_quirks
[i
].hook(dev
);
10373 /* Disable the VGA plane that we never use */
10374 static void i915_disable_vga(struct drm_device
*dev
)
10376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10378 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10380 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10381 outb(SR01
, VGA_SR_INDEX
);
10382 sr1
= inb(VGA_SR_DATA
);
10383 outb(sr1
| 1<<5, VGA_SR_DATA
);
10384 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10387 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10388 POSTING_READ(vga_reg
);
10391 static void i915_enable_vga_mem(struct drm_device
*dev
)
10393 /* Enable VGA memory on Intel HD */
10394 if (HAS_PCH_SPLIT(dev
)) {
10395 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10396 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10397 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10398 VGA_RSRC_LEGACY_MEM
|
10399 VGA_RSRC_NORMAL_IO
|
10400 VGA_RSRC_NORMAL_MEM
);
10401 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10405 void i915_disable_vga_mem(struct drm_device
*dev
)
10407 /* Disable VGA memory on Intel HD */
10408 if (HAS_PCH_SPLIT(dev
)) {
10409 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10410 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10411 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10412 VGA_RSRC_NORMAL_IO
|
10413 VGA_RSRC_NORMAL_MEM
);
10414 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10418 void intel_modeset_init_hw(struct drm_device
*dev
)
10420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10422 intel_prepare_ddi(dev
);
10424 intel_init_clock_gating(dev
);
10426 /* Enable the CRI clock source so we can get at the display */
10427 if (IS_VALLEYVIEW(dev
))
10428 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
10429 DPLL_INTEGRATED_CRI_CLK_VLV
);
10431 intel_init_dpio(dev
);
10433 mutex_lock(&dev
->struct_mutex
);
10434 intel_enable_gt_powersave(dev
);
10435 mutex_unlock(&dev
->struct_mutex
);
10438 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10440 intel_suspend_hw(dev
);
10443 void intel_modeset_init(struct drm_device
*dev
)
10445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10448 drm_mode_config_init(dev
);
10450 dev
->mode_config
.min_width
= 0;
10451 dev
->mode_config
.min_height
= 0;
10453 dev
->mode_config
.preferred_depth
= 24;
10454 dev
->mode_config
.prefer_shadow
= 1;
10456 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10458 intel_init_quirks(dev
);
10460 intel_init_pm(dev
);
10462 if (INTEL_INFO(dev
)->num_pipes
== 0)
10465 intel_init_display(dev
);
10467 if (IS_GEN2(dev
)) {
10468 dev
->mode_config
.max_width
= 2048;
10469 dev
->mode_config
.max_height
= 2048;
10470 } else if (IS_GEN3(dev
)) {
10471 dev
->mode_config
.max_width
= 4096;
10472 dev
->mode_config
.max_height
= 4096;
10474 dev
->mode_config
.max_width
= 8192;
10475 dev
->mode_config
.max_height
= 8192;
10477 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10479 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10480 INTEL_INFO(dev
)->num_pipes
,
10481 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10484 intel_crtc_init(dev
, i
);
10485 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10486 ret
= intel_plane_init(dev
, i
, j
);
10488 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10489 pipe_name(i
), sprite_name(i
, j
), ret
);
10493 intel_cpu_pll_init(dev
);
10494 intel_shared_dpll_init(dev
);
10496 /* Just disable it once at startup */
10497 i915_disable_vga(dev
);
10498 intel_setup_outputs(dev
);
10500 /* Just in case the BIOS is doing something questionable. */
10501 intel_disable_fbc(dev
);
10505 intel_connector_break_all_links(struct intel_connector
*connector
)
10507 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10508 connector
->base
.encoder
= NULL
;
10509 connector
->encoder
->connectors_active
= false;
10510 connector
->encoder
->base
.crtc
= NULL
;
10513 static void intel_enable_pipe_a(struct drm_device
*dev
)
10515 struct intel_connector
*connector
;
10516 struct drm_connector
*crt
= NULL
;
10517 struct intel_load_detect_pipe load_detect_temp
;
10519 /* We can't just switch on the pipe A, we need to set things up with a
10520 * proper mode and output configuration. As a gross hack, enable pipe A
10521 * by enabling the load detect pipe once. */
10522 list_for_each_entry(connector
,
10523 &dev
->mode_config
.connector_list
,
10525 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10526 crt
= &connector
->base
;
10534 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10535 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10541 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10543 struct drm_device
*dev
= crtc
->base
.dev
;
10544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10547 if (INTEL_INFO(dev
)->num_pipes
== 1)
10550 reg
= DSPCNTR(!crtc
->plane
);
10551 val
= I915_READ(reg
);
10553 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10554 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10560 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10562 struct drm_device
*dev
= crtc
->base
.dev
;
10563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10566 /* Clear any frame start delays used for debugging left by the BIOS */
10567 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10568 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10570 /* We need to sanitize the plane -> pipe mapping first because this will
10571 * disable the crtc (and hence change the state) if it is wrong. Note
10572 * that gen4+ has a fixed plane -> pipe mapping. */
10573 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10574 struct intel_connector
*connector
;
10577 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10578 crtc
->base
.base
.id
);
10580 /* Pipe has the wrong plane attached and the plane is active.
10581 * Temporarily change the plane mapping and disable everything
10583 plane
= crtc
->plane
;
10584 crtc
->plane
= !plane
;
10585 dev_priv
->display
.crtc_disable(&crtc
->base
);
10586 crtc
->plane
= plane
;
10588 /* ... and break all links. */
10589 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10591 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10594 intel_connector_break_all_links(connector
);
10597 WARN_ON(crtc
->active
);
10598 crtc
->base
.enabled
= false;
10601 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10602 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10603 /* BIOS forgot to enable pipe A, this mostly happens after
10604 * resume. Force-enable the pipe to fix this, the update_dpms
10605 * call below we restore the pipe to the right state, but leave
10606 * the required bits on. */
10607 intel_enable_pipe_a(dev
);
10610 /* Adjust the state of the output pipe according to whether we
10611 * have active connectors/encoders. */
10612 intel_crtc_update_dpms(&crtc
->base
);
10614 if (crtc
->active
!= crtc
->base
.enabled
) {
10615 struct intel_encoder
*encoder
;
10617 /* This can happen either due to bugs in the get_hw_state
10618 * functions or because the pipe is force-enabled due to the
10620 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10621 crtc
->base
.base
.id
,
10622 crtc
->base
.enabled
? "enabled" : "disabled",
10623 crtc
->active
? "enabled" : "disabled");
10625 crtc
->base
.enabled
= crtc
->active
;
10627 /* Because we only establish the connector -> encoder ->
10628 * crtc links if something is active, this means the
10629 * crtc is now deactivated. Break the links. connector
10630 * -> encoder links are only establish when things are
10631 * actually up, hence no need to break them. */
10632 WARN_ON(crtc
->active
);
10634 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10635 WARN_ON(encoder
->connectors_active
);
10636 encoder
->base
.crtc
= NULL
;
10641 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10643 struct intel_connector
*connector
;
10644 struct drm_device
*dev
= encoder
->base
.dev
;
10646 /* We need to check both for a crtc link (meaning that the
10647 * encoder is active and trying to read from a pipe) and the
10648 * pipe itself being active. */
10649 bool has_active_crtc
= encoder
->base
.crtc
&&
10650 to_intel_crtc(encoder
->base
.crtc
)->active
;
10652 if (encoder
->connectors_active
&& !has_active_crtc
) {
10653 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10654 encoder
->base
.base
.id
,
10655 drm_get_encoder_name(&encoder
->base
));
10657 /* Connector is active, but has no active pipe. This is
10658 * fallout from our resume register restoring. Disable
10659 * the encoder manually again. */
10660 if (encoder
->base
.crtc
) {
10661 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10662 encoder
->base
.base
.id
,
10663 drm_get_encoder_name(&encoder
->base
));
10664 encoder
->disable(encoder
);
10667 /* Inconsistent output/port/pipe state happens presumably due to
10668 * a bug in one of the get_hw_state functions. Or someplace else
10669 * in our code, like the register restore mess on resume. Clamp
10670 * things to off as a safer default. */
10671 list_for_each_entry(connector
,
10672 &dev
->mode_config
.connector_list
,
10674 if (connector
->encoder
!= encoder
)
10677 intel_connector_break_all_links(connector
);
10680 /* Enabled encoders without active connectors will be fixed in
10681 * the crtc fixup. */
10684 void i915_redisable_vga(struct drm_device
*dev
)
10686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10687 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10689 /* This function can be called both from intel_modeset_setup_hw_state or
10690 * at a very early point in our resume sequence, where the power well
10691 * structures are not yet restored. Since this function is at a very
10692 * paranoid "someone might have enabled VGA while we were not looking"
10693 * level, just check if the power well is enabled instead of trying to
10694 * follow the "don't touch the power well if we don't need it" policy
10695 * the rest of the driver uses. */
10696 if (HAS_POWER_WELL(dev
) &&
10697 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10700 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
10701 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10702 i915_disable_vga(dev
);
10703 i915_disable_vga_mem(dev
);
10707 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10711 struct intel_crtc
*crtc
;
10712 struct intel_encoder
*encoder
;
10713 struct intel_connector
*connector
;
10716 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10718 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10720 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10723 crtc
->base
.enabled
= crtc
->active
;
10724 crtc
->primary_enabled
= crtc
->active
;
10726 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10727 crtc
->base
.base
.id
,
10728 crtc
->active
? "enabled" : "disabled");
10731 /* FIXME: Smash this into the new shared dpll infrastructure. */
10733 intel_ddi_setup_hw_pll_state(dev
);
10735 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10736 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10738 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10740 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10742 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10745 pll
->refcount
= pll
->active
;
10747 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10748 pll
->name
, pll
->refcount
, pll
->on
);
10751 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10755 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10756 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10757 encoder
->base
.crtc
= &crtc
->base
;
10758 if (encoder
->get_config
)
10759 encoder
->get_config(encoder
, &crtc
->config
);
10761 encoder
->base
.crtc
= NULL
;
10764 encoder
->connectors_active
= false;
10765 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10766 encoder
->base
.base
.id
,
10767 drm_get_encoder_name(&encoder
->base
),
10768 encoder
->base
.crtc
? "enabled" : "disabled",
10772 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10774 if (connector
->get_hw_state(connector
)) {
10775 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10776 connector
->encoder
->connectors_active
= true;
10777 connector
->base
.encoder
= &connector
->encoder
->base
;
10779 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10780 connector
->base
.encoder
= NULL
;
10782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10783 connector
->base
.base
.id
,
10784 drm_get_connector_name(&connector
->base
),
10785 connector
->base
.encoder
? "enabled" : "disabled");
10789 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10790 * and i915 state tracking structures. */
10791 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10792 bool force_restore
)
10794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10796 struct intel_crtc
*crtc
;
10797 struct intel_encoder
*encoder
;
10800 intel_modeset_readout_hw_state(dev
);
10803 * Now that we have the config, copy it to each CRTC struct
10804 * Note that this could go away if we move to using crtc_config
10805 * checking everywhere.
10807 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10809 if (crtc
->active
&& i915_fastboot
) {
10810 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10812 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10813 crtc
->base
.base
.id
);
10814 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10818 /* HW state is read out, now we need to sanitize this mess. */
10819 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10821 intel_sanitize_encoder(encoder
);
10824 for_each_pipe(pipe
) {
10825 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10826 intel_sanitize_crtc(crtc
);
10827 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10830 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10831 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10833 if (!pll
->on
|| pll
->active
)
10836 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10838 pll
->disable(dev_priv
, pll
);
10842 if (force_restore
) {
10843 i915_redisable_vga(dev
);
10846 * We need to use raw interfaces for restoring state to avoid
10847 * checking (bogus) intermediate states.
10849 for_each_pipe(pipe
) {
10850 struct drm_crtc
*crtc
=
10851 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10853 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10857 intel_modeset_update_staged_output_state(dev
);
10860 intel_modeset_check_state(dev
);
10862 drm_mode_config_reset(dev
);
10865 void intel_modeset_gem_init(struct drm_device
*dev
)
10867 intel_modeset_init_hw(dev
);
10869 intel_setup_overlay(dev
);
10871 intel_modeset_setup_hw_state(dev
, false);
10874 void intel_modeset_cleanup(struct drm_device
*dev
)
10876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10877 struct drm_crtc
*crtc
;
10878 struct drm_connector
*connector
;
10881 * Interrupts and polling as the first thing to avoid creating havoc.
10882 * Too much stuff here (turning of rps, connectors, ...) would
10883 * experience fancy races otherwise.
10885 drm_irq_uninstall(dev
);
10886 cancel_work_sync(&dev_priv
->hotplug_work
);
10888 * Due to the hpd irq storm handling the hotplug work can re-arm the
10889 * poll handlers. Hence disable polling after hpd handling is shut down.
10891 drm_kms_helper_poll_fini(dev
);
10893 mutex_lock(&dev
->struct_mutex
);
10895 intel_unregister_dsm_handler();
10897 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10898 /* Skip inactive CRTCs */
10902 intel_increase_pllclock(crtc
);
10905 intel_disable_fbc(dev
);
10907 i915_enable_vga_mem(dev
);
10909 intel_disable_gt_powersave(dev
);
10911 ironlake_teardown_rc6(dev
);
10913 mutex_unlock(&dev
->struct_mutex
);
10915 /* flush any delayed tasks or pending work */
10916 flush_scheduled_work();
10918 /* destroy backlight, if any, before the connectors */
10919 intel_panel_destroy_backlight(dev
);
10921 /* destroy the sysfs files before encoders/connectors */
10922 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
10923 drm_sysfs_connector_remove(connector
);
10925 drm_mode_config_cleanup(dev
);
10927 intel_cleanup_overlay(dev
);
10931 * Return which encoder is currently attached for connector.
10933 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10935 return &intel_attached_encoder(connector
)->base
;
10938 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10939 struct intel_encoder
*encoder
)
10941 connector
->encoder
= encoder
;
10942 drm_mode_connector_attach_encoder(&connector
->base
,
10947 * set vga decode state - true == enable VGA decode
10949 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10954 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10956 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10958 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10959 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10963 struct intel_display_error_state
{
10965 u32 power_well_driver
;
10967 int num_transcoders
;
10969 struct intel_cursor_error_state
{
10974 } cursor
[I915_MAX_PIPES
];
10976 struct intel_pipe_error_state
{
10978 } pipe
[I915_MAX_PIPES
];
10980 struct intel_plane_error_state
{
10988 } plane
[I915_MAX_PIPES
];
10990 struct intel_transcoder_error_state
{
10991 enum transcoder cpu_transcoder
;
11004 struct intel_display_error_state
*
11005 intel_display_capture_error_state(struct drm_device
*dev
)
11007 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
11008 struct intel_display_error_state
*error
;
11009 int transcoders
[] = {
11017 if (INTEL_INFO(dev
)->num_pipes
== 0)
11020 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
11024 if (HAS_POWER_WELL(dev
))
11025 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
11028 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
11029 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
11030 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
11031 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
11033 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
11034 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11035 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11038 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11039 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11040 if (INTEL_INFO(dev
)->gen
<= 3) {
11041 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11042 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11044 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11045 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11046 if (INTEL_INFO(dev
)->gen
>= 4) {
11047 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11048 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11051 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11054 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11055 if (HAS_DDI(dev_priv
->dev
))
11056 error
->num_transcoders
++; /* Account for eDP. */
11058 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11059 enum transcoder cpu_transcoder
= transcoders
[i
];
11061 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11063 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11064 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11065 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11066 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11067 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11068 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11069 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11072 /* In the code above we read the registers without checking if the power
11073 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11074 * prevent the next I915_WRITE from detecting it and printing an error
11076 intel_uncore_clear_errors(dev
);
11081 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11084 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11085 struct drm_device
*dev
,
11086 struct intel_display_error_state
*error
)
11093 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11094 if (HAS_POWER_WELL(dev
))
11095 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11096 error
->power_well_driver
);
11098 err_printf(m
, "Pipe [%d]:\n", i
);
11099 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11101 err_printf(m
, "Plane [%d]:\n", i
);
11102 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11103 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11104 if (INTEL_INFO(dev
)->gen
<= 3) {
11105 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11106 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11108 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11109 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11110 if (INTEL_INFO(dev
)->gen
>= 4) {
11111 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11112 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11115 err_printf(m
, "Cursor [%d]:\n", i
);
11116 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11117 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11118 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11121 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11122 err_printf(m
, " CPU transcoder: %c\n",
11123 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11124 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11125 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11126 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11127 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11128 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11129 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11130 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);