2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector
*connector
,
195 struct drm_display_mode
*mode
)
197 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
198 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
199 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
200 int target_clock
= mode
->clock
;
201 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
204 if (is_edp(intel_dp
) && fixed_mode
) {
205 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
208 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
211 target_clock
= fixed_mode
->clock
;
214 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
215 max_lanes
= intel_dp_max_lane_count(intel_dp
);
217 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
218 mode_rate
= intel_dp_link_required(target_clock
, 18);
220 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
221 return MODE_CLOCK_HIGH
;
223 if (mode
->clock
< 10000)
224 return MODE_CLOCK_LOW
;
226 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
227 return MODE_H_ILLEGAL
;
232 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
239 for (i
= 0; i
< src_bytes
; i
++)
240 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
255 struct intel_dp
*intel_dp
);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
258 struct intel_dp
*intel_dp
);
260 static void pps_lock(struct intel_dp
*intel_dp
)
262 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
263 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
264 struct drm_device
*dev
= encoder
->base
.dev
;
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 enum intel_display_power_domain power_domain
;
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
272 power_domain
= intel_display_port_aux_power_domain(encoder
);
273 intel_display_power_get(dev_priv
, power_domain
);
275 mutex_lock(&dev_priv
->pps_mutex
);
278 static void pps_unlock(struct intel_dp
*intel_dp
)
280 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
281 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
282 struct drm_device
*dev
= encoder
->base
.dev
;
283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 enum intel_display_power_domain power_domain
;
286 mutex_unlock(&dev_priv
->pps_mutex
);
288 power_domain
= intel_display_port_aux_power_domain(encoder
);
289 intel_display_power_put(dev_priv
, power_domain
);
293 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum pipe pipe
= intel_dp
->pps_pipe
;
299 bool pll_enabled
, release_cl_override
= false;
300 enum dpio_phy phy
= DPIO_PHY(pipe
);
301 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
304 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe
), port_name(intel_dig_port
->port
));
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
315 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
316 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
317 DP
|= DP_PORT_WIDTH(1);
318 DP
|= DP_LINK_TRAIN_PAT_1
;
320 if (IS_CHERRYVIEW(dev
))
321 DP
|= DP_PIPE_SELECT_CHV(pipe
);
322 else if (pipe
== PIPE_B
)
323 DP
|= DP_PIPEB_SELECT
;
325 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
332 release_cl_override
= IS_CHERRYVIEW(dev
) &&
333 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
335 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
336 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
349 I915_WRITE(intel_dp
->output_reg
, DP
);
350 POSTING_READ(intel_dp
->output_reg
);
352 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
353 POSTING_READ(intel_dp
->output_reg
);
355 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
356 POSTING_READ(intel_dp
->output_reg
);
359 vlv_force_pll_off(dev
, pipe
);
361 if (release_cl_override
)
362 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
367 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
369 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
370 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct intel_encoder
*encoder
;
373 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
376 lockdep_assert_held(&dev_priv
->pps_mutex
);
378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp
));
381 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
382 return intel_dp
->pps_pipe
;
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
388 for_each_intel_encoder(dev
, encoder
) {
389 struct intel_dp
*tmp
;
391 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
394 tmp
= enc_to_intel_dp(&encoder
->base
);
396 if (tmp
->pps_pipe
!= INVALID_PIPE
)
397 pipes
&= ~(1 << tmp
->pps_pipe
);
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
404 if (WARN_ON(pipes
== 0))
407 pipe
= ffs(pipes
) - 1;
409 vlv_steal_power_sequencer(dev
, pipe
);
410 intel_dp
->pps_pipe
= pipe
;
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp
->pps_pipe
),
414 port_name(intel_dig_port
->port
));
416 /* init power sequencer on this pipe and port */
417 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
418 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
424 vlv_power_sequencer_kick(intel_dp
);
426 return intel_dp
->pps_pipe
;
430 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
432 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
433 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
436 lockdep_assert_held(&dev_priv
->pps_mutex
);
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp
));
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
446 if (!intel_dp
->pps_reset
)
449 intel_dp
->pps_reset
= false;
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
455 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
460 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
463 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
475 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
482 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
484 vlv_pipe_check pipe_check
)
488 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
489 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
490 PANEL_PORT_SELECT_MASK
;
492 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
495 if (!pipe_check(dev_priv
, pipe
))
505 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
507 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
508 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
510 enum port port
= intel_dig_port
->port
;
512 lockdep_assert_held(&dev_priv
->pps_mutex
);
514 /* try to find a pipe with this port selected */
515 /* first pick one where the panel is on */
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
521 vlv_pipe_has_vdd_on
);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
524 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
537 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
538 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
541 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
543 struct drm_device
*dev
= dev_priv
->dev
;
544 struct intel_encoder
*encoder
;
546 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
560 for_each_intel_encoder(dev
, encoder
) {
561 struct intel_dp
*intel_dp
;
563 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
566 intel_dp
= enc_to_intel_dp(&encoder
->base
);
568 intel_dp
->pps_reset
= true;
570 intel_dp
->pps_pipe
= INVALID_PIPE
;
574 struct pps_registers
{
582 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
583 struct intel_dp
*intel_dp
,
584 struct pps_registers
*regs
)
586 memset(regs
, 0, sizeof(*regs
));
588 if (IS_BROXTON(dev_priv
)) {
589 int idx
= bxt_power_sequencer_idx(intel_dp
);
591 regs
->pp_ctrl
= BXT_PP_CONTROL(idx
);
592 regs
->pp_stat
= BXT_PP_STATUS(idx
);
593 regs
->pp_on
= BXT_PP_ON_DELAYS(idx
);
594 regs
->pp_off
= BXT_PP_OFF_DELAYS(idx
);
595 } else if (HAS_PCH_SPLIT(dev_priv
)) {
596 regs
->pp_ctrl
= PCH_PP_CONTROL
;
597 regs
->pp_stat
= PCH_PP_STATUS
;
598 regs
->pp_on
= PCH_PP_ON_DELAYS
;
599 regs
->pp_off
= PCH_PP_OFF_DELAYS
;
600 regs
->pp_div
= PCH_PP_DIVISOR
;
602 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
604 regs
->pp_ctrl
= VLV_PIPE_PP_CONTROL(pipe
);
605 regs
->pp_stat
= VLV_PIPE_PP_STATUS(pipe
);
606 regs
->pp_on
= VLV_PIPE_PP_ON_DELAYS(pipe
);
607 regs
->pp_off
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
608 regs
->pp_div
= VLV_PIPE_PP_DIVISOR(pipe
);
613 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
615 struct pps_registers regs
;
617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
624 _pp_stat_reg(struct intel_dp
*intel_dp
)
626 struct pps_registers regs
;
628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
639 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
641 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
649 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
650 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
651 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
654 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
655 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
656 pp_div
= I915_READ(pp_div_reg
);
657 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
661 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
662 msleep(intel_dp
->panel_power_cycle_delay
);
665 pps_unlock(intel_dp
);
670 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
672 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
675 lockdep_assert_held(&dev_priv
->pps_mutex
);
677 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
678 intel_dp
->pps_pipe
== INVALID_PIPE
)
681 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
684 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
686 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 lockdep_assert_held(&dev_priv
->pps_mutex
);
691 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
692 intel_dp
->pps_pipe
== INVALID_PIPE
)
695 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
699 intel_dp_check_edp(struct intel_dp
*intel_dp
)
701 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
704 if (!is_edp(intel_dp
))
707 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
710 I915_READ(_pp_stat_reg(intel_dp
)),
711 I915_READ(_pp_ctrl_reg(intel_dp
)));
716 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
718 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
719 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
721 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
725 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
727 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
728 msecs_to_jiffies_timeout(10));
730 done
= wait_for(C
, 10) == 0;
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
739 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
742 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
748 * The clock divider is based off the hrawclk, and would like to run at
749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
751 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
754 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
756 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
757 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
767 if (intel_dig_port
->port
== PORT_A
)
768 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
770 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
773 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
775 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
776 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
778 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
779 /* Workaround for non-ULT HSW */
787 return ilk_get_aux_clock_divider(intel_dp
, index
);
790 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
797 return index
? 0 : 1;
800 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
803 uint32_t aux_clock_divider
)
805 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
806 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
807 uint32_t precharge
, timeout
;
814 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
815 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
817 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
819 return DP_AUX_CH_CTL_SEND_BUSY
|
821 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
822 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
824 DP_AUX_CH_CTL_RECEIVE_ERROR
|
825 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
826 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
827 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
830 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
835 return DP_AUX_CH_CTL_SEND_BUSY
|
837 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
839 DP_AUX_CH_CTL_TIME_OUT_1600us
|
840 DP_AUX_CH_CTL_RECEIVE_ERROR
|
841 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
847 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
848 const uint8_t *send
, int send_bytes
,
849 uint8_t *recv
, int recv_size
)
851 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
852 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
854 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
855 uint32_t aux_clock_divider
;
856 int i
, ret
, recv_bytes
;
859 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
870 vdd
= edp_panel_vdd_on(intel_dp
);
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
876 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
878 intel_dp_check_edp(intel_dp
);
880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
882 status
= I915_READ_NOTRACE(ch_ctl
);
883 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
889 static u32 last_status
= -1;
890 const u32 status
= I915_READ(ch_ctl
);
892 if (status
!= last_status
) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
895 last_status
= status
;
902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
908 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
909 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i
= 0; i
< send_bytes
; i
+= 4)
918 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
919 intel_dp_pack_aux(send
+ i
,
922 /* Send the command and wait for it to complete */
923 I915_WRITE(ch_ctl
, send_ctl
);
925 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
927 /* Clear done status and any errors */
931 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
932 DP_AUX_CH_CTL_RECEIVE_ERROR
);
934 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
942 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
943 usleep_range(400, 500);
946 if (status
& DP_AUX_CH_CTL_DONE
)
951 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
961 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
969 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
975 /* Unload any bytes sent back from the other side */
976 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
984 if (recv_bytes
== 0 || recv_bytes
> 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
994 usleep_range(1000, 1500);
999 if (recv_bytes
> recv_size
)
1000 recv_bytes
= recv_size
;
1002 for (i
= 0; i
< recv_bytes
; i
+= 4)
1003 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1004 recv
+ i
, recv_bytes
- i
);
1008 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1011 edp_panel_vdd_off(intel_dp
, false);
1013 pps_unlock(intel_dp
);
1018 #define BARE_ADDRESS_SIZE 3
1019 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1021 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1023 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1024 uint8_t txbuf
[20], rxbuf
[20];
1025 size_t txsize
, rxsize
;
1028 txbuf
[0] = (msg
->request
<< 4) |
1029 ((msg
->address
>> 16) & 0xf);
1030 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1031 txbuf
[2] = msg
->address
& 0xff;
1032 txbuf
[3] = msg
->size
- 1;
1034 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1035 case DP_AUX_NATIVE_WRITE
:
1036 case DP_AUX_I2C_WRITE
:
1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1038 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1039 rxsize
= 2; /* 0 or 1 data bytes */
1041 if (WARN_ON(txsize
> 20))
1045 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1049 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1051 msg
->reply
= rxbuf
[0] >> 4;
1054 /* Number of bytes written in a short write. */
1055 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1057 /* Return payload size. */
1063 case DP_AUX_NATIVE_READ
:
1064 case DP_AUX_I2C_READ
:
1065 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1066 rxsize
= msg
->size
+ 1;
1068 if (WARN_ON(rxsize
> 20))
1071 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1073 msg
->reply
= rxbuf
[0] >> 4;
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1078 * Return payload size.
1081 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1093 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1100 return DP_AUX_CH_CTL(port
);
1103 return DP_AUX_CH_CTL(PORT_B
);
1107 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1108 enum port port
, int index
)
1114 return DP_AUX_CH_DATA(port
, index
);
1117 return DP_AUX_CH_DATA(PORT_B
, index
);
1121 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1126 return DP_AUX_CH_CTL(port
);
1130 return PCH_DP_AUX_CH_CTL(port
);
1133 return DP_AUX_CH_CTL(PORT_A
);
1137 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1138 enum port port
, int index
)
1142 return DP_AUX_CH_DATA(port
, index
);
1146 return PCH_DP_AUX_CH_DATA(port
, index
);
1149 return DP_AUX_CH_DATA(PORT_A
, index
);
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1157 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1159 const struct ddi_vbt_port_info
*info
=
1160 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1162 switch (info
->alternate_aux_channel
) {
1172 MISSING_CASE(info
->alternate_aux_channel
);
1177 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1181 port
= skl_porte_aux_port(dev_priv
);
1188 return DP_AUX_CH_CTL(port
);
1191 return DP_AUX_CH_CTL(PORT_A
);
1195 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1196 enum port port
, int index
)
1199 port
= skl_porte_aux_port(dev_priv
);
1206 return DP_AUX_CH_DATA(port
, index
);
1209 return DP_AUX_CH_DATA(PORT_A
, index
);
1213 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1216 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1217 return skl_aux_ctl_reg(dev_priv
, port
);
1218 else if (HAS_PCH_SPLIT(dev_priv
))
1219 return ilk_aux_ctl_reg(dev_priv
, port
);
1221 return g4x_aux_ctl_reg(dev_priv
, port
);
1224 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1225 enum port port
, int index
)
1227 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1228 return skl_aux_data_reg(dev_priv
, port
, index
);
1229 else if (HAS_PCH_SPLIT(dev_priv
))
1230 return ilk_aux_data_reg(dev_priv
, port
, index
);
1232 return g4x_aux_data_reg(dev_priv
, port
, index
);
1235 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1237 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1238 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1241 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1242 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1243 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1247 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1249 kfree(intel_dp
->aux
.name
);
1253 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1255 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1256 enum port port
= intel_dig_port
->port
;
1258 intel_aux_reg_init(intel_dp
);
1259 drm_dp_aux_init(&intel_dp
->aux
);
1261 /* Failure to allocate our preferred name is not critical */
1262 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1263 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1267 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1269 if (intel_dp
->num_sink_rates
) {
1270 *sink_rates
= intel_dp
->sink_rates
;
1271 return intel_dp
->num_sink_rates
;
1274 *sink_rates
= default_rates
;
1276 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1279 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1281 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1282 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1284 /* WaDisableHBR2:skl */
1285 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1288 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1289 (INTEL_INFO(dev
)->gen
>= 9))
1296 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1298 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1299 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1302 if (IS_BROXTON(dev
)) {
1303 *source_rates
= bxt_rates
;
1304 size
= ARRAY_SIZE(bxt_rates
);
1305 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1306 *source_rates
= skl_rates
;
1307 size
= ARRAY_SIZE(skl_rates
);
1309 *source_rates
= default_rates
;
1310 size
= ARRAY_SIZE(default_rates
);
1313 /* This depends on the fact that 5.4 is last value in the array */
1314 if (!intel_dp_source_supports_hbr2(intel_dp
))
1321 intel_dp_set_clock(struct intel_encoder
*encoder
,
1322 struct intel_crtc_state
*pipe_config
)
1324 struct drm_device
*dev
= encoder
->base
.dev
;
1325 const struct dp_link_dpll
*divisor
= NULL
;
1329 divisor
= gen4_dpll
;
1330 count
= ARRAY_SIZE(gen4_dpll
);
1331 } else if (HAS_PCH_SPLIT(dev
)) {
1333 count
= ARRAY_SIZE(pch_dpll
);
1334 } else if (IS_CHERRYVIEW(dev
)) {
1336 count
= ARRAY_SIZE(chv_dpll
);
1337 } else if (IS_VALLEYVIEW(dev
)) {
1339 count
= ARRAY_SIZE(vlv_dpll
);
1342 if (divisor
&& count
) {
1343 for (i
= 0; i
< count
; i
++) {
1344 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1345 pipe_config
->dpll
= divisor
[i
].dpll
;
1346 pipe_config
->clock_set
= true;
1353 static int intersect_rates(const int *source_rates
, int source_len
,
1354 const int *sink_rates
, int sink_len
,
1357 int i
= 0, j
= 0, k
= 0;
1359 while (i
< source_len
&& j
< sink_len
) {
1360 if (source_rates
[i
] == sink_rates
[j
]) {
1361 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1363 common_rates
[k
] = source_rates
[i
];
1367 } else if (source_rates
[i
] < sink_rates
[j
]) {
1376 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1379 const int *source_rates
, *sink_rates
;
1380 int source_len
, sink_len
;
1382 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1383 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1385 return intersect_rates(source_rates
, source_len
,
1386 sink_rates
, sink_len
,
1390 static void snprintf_int_array(char *str
, size_t len
,
1391 const int *array
, int nelem
)
1397 for (i
= 0; i
< nelem
; i
++) {
1398 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1406 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1408 const int *source_rates
, *sink_rates
;
1409 int source_len
, sink_len
, common_len
;
1410 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1411 char str
[128]; /* FIXME: too big for stack? */
1413 if ((drm_debug
& DRM_UT_KMS
) == 0)
1416 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1417 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1418 DRM_DEBUG_KMS("source rates: %s\n", str
);
1420 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1421 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1422 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1424 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1425 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1426 DRM_DEBUG_KMS("common rates: %s\n", str
);
1429 static int rate_to_index(int find
, const int *rates
)
1433 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1434 if (find
== rates
[i
])
1441 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1443 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1446 len
= intel_dp_common_rates(intel_dp
, rates
);
1447 if (WARN_ON(len
<= 0))
1450 return rates
[rate_to_index(0, rates
) - 1];
1453 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1455 return rate_to_index(rate
, intel_dp
->sink_rates
);
1458 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1459 uint8_t *link_bw
, uint8_t *rate_select
)
1461 if (intel_dp
->num_sink_rates
) {
1464 intel_dp_rate_select(intel_dp
, port_clock
);
1466 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1472 intel_dp_compute_config(struct intel_encoder
*encoder
,
1473 struct intel_crtc_state
*pipe_config
)
1475 struct drm_device
*dev
= encoder
->base
.dev
;
1476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1478 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1479 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1480 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1481 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1482 int lane_count
, clock
;
1483 int min_lane_count
= 1;
1484 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1485 /* Conveniently, the link BW constants become indices with a shift...*/
1489 int link_avail
, link_clock
;
1490 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1492 uint8_t link_bw
, rate_select
;
1494 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1496 /* No common link rates between source and sink */
1497 WARN_ON(common_len
<= 0);
1499 max_clock
= common_len
- 1;
1501 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1502 pipe_config
->has_pch_encoder
= true;
1504 pipe_config
->has_dp_encoder
= true;
1505 pipe_config
->has_drrs
= false;
1506 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1508 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1509 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1512 if (INTEL_INFO(dev
)->gen
>= 9) {
1514 ret
= skl_update_scaler_crtc(pipe_config
);
1519 if (HAS_GMCH_DISPLAY(dev
))
1520 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1521 intel_connector
->panel
.fitting_mode
);
1523 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1524 intel_connector
->panel
.fitting_mode
);
1527 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1530 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1531 "max bw %d pixel clock %iKHz\n",
1532 max_lane_count
, common_rates
[max_clock
],
1533 adjusted_mode
->crtc_clock
);
1535 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1536 * bpc in between. */
1537 bpp
= pipe_config
->pipe_bpp
;
1538 if (is_edp(intel_dp
)) {
1540 /* Get bpp from vbt only for panels that dont have bpp in edid */
1541 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1542 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1543 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1544 dev_priv
->vbt
.edp
.bpp
);
1545 bpp
= dev_priv
->vbt
.edp
.bpp
;
1549 * Use the maximum clock and number of lanes the eDP panel
1550 * advertizes being capable of. The panels are generally
1551 * designed to support only a single clock and lane
1552 * configuration, and typically these values correspond to the
1553 * native resolution of the panel.
1555 min_lane_count
= max_lane_count
;
1556 min_clock
= max_clock
;
1559 for (; bpp
>= 6*3; bpp
-= 2*3) {
1560 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1563 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1564 for (lane_count
= min_lane_count
;
1565 lane_count
<= max_lane_count
;
1568 link_clock
= common_rates
[clock
];
1569 link_avail
= intel_dp_max_data_rate(link_clock
,
1572 if (mode_rate
<= link_avail
) {
1582 if (intel_dp
->color_range_auto
) {
1585 * CEA-861-E - 5.1 Default Encoding Parameters
1586 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1588 pipe_config
->limited_color_range
=
1589 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1591 pipe_config
->limited_color_range
=
1592 intel_dp
->limited_color_range
;
1595 pipe_config
->lane_count
= lane_count
;
1597 pipe_config
->pipe_bpp
= bpp
;
1598 pipe_config
->port_clock
= common_rates
[clock
];
1600 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1601 &link_bw
, &rate_select
);
1603 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1604 link_bw
, rate_select
, pipe_config
->lane_count
,
1605 pipe_config
->port_clock
, bpp
);
1606 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1607 mode_rate
, link_avail
);
1609 intel_link_compute_m_n(bpp
, lane_count
,
1610 adjusted_mode
->crtc_clock
,
1611 pipe_config
->port_clock
,
1612 &pipe_config
->dp_m_n
);
1614 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1615 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1616 pipe_config
->has_drrs
= true;
1617 intel_link_compute_m_n(bpp
, lane_count
,
1618 intel_connector
->panel
.downclock_mode
->clock
,
1619 pipe_config
->port_clock
,
1620 &pipe_config
->dp_m2_n2
);
1624 * DPLL0 VCO may need to be adjusted to get the correct
1625 * clock for eDP. This will affect cdclk as well.
1627 if (is_edp(intel_dp
) &&
1628 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1631 switch (pipe_config
->port_clock
/ 2) {
1641 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1645 intel_dp_set_clock(encoder
, pipe_config
);
1650 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1651 const struct intel_crtc_state
*pipe_config
)
1653 intel_dp
->link_rate
= pipe_config
->port_clock
;
1654 intel_dp
->lane_count
= pipe_config
->lane_count
;
1657 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1659 struct drm_device
*dev
= encoder
->base
.dev
;
1660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1661 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1662 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1663 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1664 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1666 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1669 * There are four kinds of DP registers:
1676 * IBX PCH and CPU are the same for almost everything,
1677 * except that the CPU DP PLL is configured in this
1680 * CPT PCH is quite different, having many bits moved
1681 * to the TRANS_DP_CTL register instead. That
1682 * configuration happens (oddly) in ironlake_pch_enable
1685 /* Preserve the BIOS-computed detected bit. This is
1686 * supposed to be read-only.
1688 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1690 /* Handle DP bits in common between all three register formats */
1691 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1692 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1694 /* Split out the IBX/CPU vs CPT settings */
1696 if (IS_GEN7(dev
) && port
== PORT_A
) {
1697 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1698 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1699 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1700 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1701 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1703 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1704 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1706 intel_dp
->DP
|= crtc
->pipe
<< 29;
1707 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1710 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1712 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1713 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1714 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1716 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1717 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1719 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1720 !IS_CHERRYVIEW(dev
) && crtc
->config
->limited_color_range
)
1721 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1723 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1724 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1725 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1726 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1727 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1729 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1730 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1732 if (IS_CHERRYVIEW(dev
))
1733 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1734 else if (crtc
->pipe
== PIPE_B
)
1735 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1739 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1740 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1742 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1743 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1745 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1746 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1748 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1749 struct intel_dp
*intel_dp
);
1751 static void wait_panel_status(struct intel_dp
*intel_dp
,
1755 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1757 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1759 lockdep_assert_held(&dev_priv
->pps_mutex
);
1761 intel_pps_verify_state(dev_priv
, intel_dp
);
1763 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1764 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1766 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1768 I915_READ(pp_stat_reg
),
1769 I915_READ(pp_ctrl_reg
));
1771 if (intel_wait_for_register(dev_priv
,
1772 pp_stat_reg
, mask
, value
,
1774 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1775 I915_READ(pp_stat_reg
),
1776 I915_READ(pp_ctrl_reg
));
1778 DRM_DEBUG_KMS("Wait complete\n");
1781 static void wait_panel_on(struct intel_dp
*intel_dp
)
1783 DRM_DEBUG_KMS("Wait for panel power on\n");
1784 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1787 static void wait_panel_off(struct intel_dp
*intel_dp
)
1789 DRM_DEBUG_KMS("Wait for panel power off time\n");
1790 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1793 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1795 ktime_t panel_power_on_time
;
1796 s64 panel_power_off_duration
;
1798 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1800 /* take the difference of currrent time and panel power off time
1801 * and then make panel wait for t11_t12 if needed. */
1802 panel_power_on_time
= ktime_get_boottime();
1803 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1805 /* When we disable the VDD override bit last we have to do the manual
1807 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1808 wait_remaining_ms_from_jiffies(jiffies
,
1809 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1811 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1814 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1816 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1817 intel_dp
->backlight_on_delay
);
1820 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1822 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1823 intel_dp
->backlight_off_delay
);
1826 /* Read the current pp_control value, unlocking the register if it
1830 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1832 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 lockdep_assert_held(&dev_priv
->pps_mutex
);
1838 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1839 if (!IS_BROXTON(dev
)) {
1840 control
&= ~PANEL_UNLOCK_MASK
;
1841 control
|= PANEL_UNLOCK_REGS
;
1847 * Must be paired with edp_panel_vdd_off().
1848 * Must hold pps_mutex around the whole on/off sequence.
1849 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1851 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1853 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1854 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1855 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1857 enum intel_display_power_domain power_domain
;
1859 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1860 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1862 lockdep_assert_held(&dev_priv
->pps_mutex
);
1864 if (!is_edp(intel_dp
))
1867 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1868 intel_dp
->want_panel_vdd
= true;
1870 if (edp_have_panel_vdd(intel_dp
))
1871 return need_to_disable
;
1873 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1874 intel_display_power_get(dev_priv
, power_domain
);
1876 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1877 port_name(intel_dig_port
->port
));
1879 if (!edp_have_panel_power(intel_dp
))
1880 wait_panel_power_cycle(intel_dp
);
1882 pp
= ironlake_get_pp_control(intel_dp
);
1883 pp
|= EDP_FORCE_VDD
;
1885 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1886 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1888 I915_WRITE(pp_ctrl_reg
, pp
);
1889 POSTING_READ(pp_ctrl_reg
);
1890 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1891 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1893 * If the panel wasn't on, delay before accessing aux channel
1895 if (!edp_have_panel_power(intel_dp
)) {
1896 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1897 port_name(intel_dig_port
->port
));
1898 msleep(intel_dp
->panel_power_up_delay
);
1901 return need_to_disable
;
1905 * Must be paired with intel_edp_panel_vdd_off() or
1906 * intel_edp_panel_off().
1907 * Nested calls to these functions are not allowed since
1908 * we drop the lock. Caller must use some higher level
1909 * locking to prevent nested calls from other threads.
1911 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1915 if (!is_edp(intel_dp
))
1919 vdd
= edp_panel_vdd_on(intel_dp
);
1920 pps_unlock(intel_dp
);
1922 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1923 port_name(dp_to_dig_port(intel_dp
)->port
));
1926 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1928 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct intel_digital_port
*intel_dig_port
=
1931 dp_to_dig_port(intel_dp
);
1932 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1933 enum intel_display_power_domain power_domain
;
1935 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1937 lockdep_assert_held(&dev_priv
->pps_mutex
);
1939 WARN_ON(intel_dp
->want_panel_vdd
);
1941 if (!edp_have_panel_vdd(intel_dp
))
1944 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1945 port_name(intel_dig_port
->port
));
1947 pp
= ironlake_get_pp_control(intel_dp
);
1948 pp
&= ~EDP_FORCE_VDD
;
1950 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1951 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1953 I915_WRITE(pp_ctrl_reg
, pp
);
1954 POSTING_READ(pp_ctrl_reg
);
1956 /* Make sure sequencer is idle before allowing subsequent activity */
1957 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1958 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1960 if ((pp
& POWER_TARGET_ON
) == 0)
1961 intel_dp
->panel_power_off_time
= ktime_get_boottime();
1963 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1964 intel_display_power_put(dev_priv
, power_domain
);
1967 static void edp_panel_vdd_work(struct work_struct
*__work
)
1969 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1970 struct intel_dp
, panel_vdd_work
);
1973 if (!intel_dp
->want_panel_vdd
)
1974 edp_panel_vdd_off_sync(intel_dp
);
1975 pps_unlock(intel_dp
);
1978 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1980 unsigned long delay
;
1983 * Queue the timer to fire a long time from now (relative to the power
1984 * down delay) to keep the panel power up across a sequence of
1987 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1988 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1992 * Must be paired with edp_panel_vdd_on().
1993 * Must hold pps_mutex around the whole on/off sequence.
1994 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1996 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1998 struct drm_i915_private
*dev_priv
=
1999 intel_dp_to_dev(intel_dp
)->dev_private
;
2001 lockdep_assert_held(&dev_priv
->pps_mutex
);
2003 if (!is_edp(intel_dp
))
2006 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2007 port_name(dp_to_dig_port(intel_dp
)->port
));
2009 intel_dp
->want_panel_vdd
= false;
2012 edp_panel_vdd_off_sync(intel_dp
);
2014 edp_panel_vdd_schedule_off(intel_dp
);
2017 static void edp_panel_on(struct intel_dp
*intel_dp
)
2019 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2022 i915_reg_t pp_ctrl_reg
;
2024 lockdep_assert_held(&dev_priv
->pps_mutex
);
2026 if (!is_edp(intel_dp
))
2029 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2030 port_name(dp_to_dig_port(intel_dp
)->port
));
2032 if (WARN(edp_have_panel_power(intel_dp
),
2033 "eDP port %c panel power already on\n",
2034 port_name(dp_to_dig_port(intel_dp
)->port
)))
2037 wait_panel_power_cycle(intel_dp
);
2039 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2040 pp
= ironlake_get_pp_control(intel_dp
);
2042 /* ILK workaround: disable reset around power sequence */
2043 pp
&= ~PANEL_POWER_RESET
;
2044 I915_WRITE(pp_ctrl_reg
, pp
);
2045 POSTING_READ(pp_ctrl_reg
);
2048 pp
|= POWER_TARGET_ON
;
2050 pp
|= PANEL_POWER_RESET
;
2052 I915_WRITE(pp_ctrl_reg
, pp
);
2053 POSTING_READ(pp_ctrl_reg
);
2055 wait_panel_on(intel_dp
);
2056 intel_dp
->last_power_on
= jiffies
;
2059 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2060 I915_WRITE(pp_ctrl_reg
, pp
);
2061 POSTING_READ(pp_ctrl_reg
);
2065 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2067 if (!is_edp(intel_dp
))
2071 edp_panel_on(intel_dp
);
2072 pps_unlock(intel_dp
);
2076 static void edp_panel_off(struct intel_dp
*intel_dp
)
2078 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2079 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2080 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 enum intel_display_power_domain power_domain
;
2084 i915_reg_t pp_ctrl_reg
;
2086 lockdep_assert_held(&dev_priv
->pps_mutex
);
2088 if (!is_edp(intel_dp
))
2091 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2092 port_name(dp_to_dig_port(intel_dp
)->port
));
2094 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2095 port_name(dp_to_dig_port(intel_dp
)->port
));
2097 pp
= ironlake_get_pp_control(intel_dp
);
2098 /* We need to switch off panel power _and_ force vdd, for otherwise some
2099 * panels get very unhappy and cease to work. */
2100 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2103 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2105 intel_dp
->want_panel_vdd
= false;
2107 I915_WRITE(pp_ctrl_reg
, pp
);
2108 POSTING_READ(pp_ctrl_reg
);
2110 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2111 wait_panel_off(intel_dp
);
2113 /* We got a reference when we enabled the VDD. */
2114 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2115 intel_display_power_put(dev_priv
, power_domain
);
2118 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2120 if (!is_edp(intel_dp
))
2124 edp_panel_off(intel_dp
);
2125 pps_unlock(intel_dp
);
2128 /* Enable backlight in the panel power control. */
2129 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2131 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2132 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2135 i915_reg_t pp_ctrl_reg
;
2138 * If we enable the backlight right away following a panel power
2139 * on, we may see slight flicker as the panel syncs with the eDP
2140 * link. So delay a bit to make sure the image is solid before
2141 * allowing it to appear.
2143 wait_backlight_on(intel_dp
);
2147 pp
= ironlake_get_pp_control(intel_dp
);
2148 pp
|= EDP_BLC_ENABLE
;
2150 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2152 I915_WRITE(pp_ctrl_reg
, pp
);
2153 POSTING_READ(pp_ctrl_reg
);
2155 pps_unlock(intel_dp
);
2158 /* Enable backlight PWM and backlight PP control. */
2159 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2161 if (!is_edp(intel_dp
))
2164 DRM_DEBUG_KMS("\n");
2166 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2167 _intel_edp_backlight_on(intel_dp
);
2170 /* Disable backlight in the panel power control. */
2171 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2173 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2176 i915_reg_t pp_ctrl_reg
;
2178 if (!is_edp(intel_dp
))
2183 pp
= ironlake_get_pp_control(intel_dp
);
2184 pp
&= ~EDP_BLC_ENABLE
;
2186 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2188 I915_WRITE(pp_ctrl_reg
, pp
);
2189 POSTING_READ(pp_ctrl_reg
);
2191 pps_unlock(intel_dp
);
2193 intel_dp
->last_backlight_off
= jiffies
;
2194 edp_wait_backlight_off(intel_dp
);
2197 /* Disable backlight PP control and backlight PWM. */
2198 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2200 if (!is_edp(intel_dp
))
2203 DRM_DEBUG_KMS("\n");
2205 _intel_edp_backlight_off(intel_dp
);
2206 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2210 * Hook for controlling the panel power control backlight through the bl_power
2211 * sysfs attribute. Take care to handle multiple calls.
2213 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2216 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2220 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2221 pps_unlock(intel_dp
);
2223 if (is_enabled
== enable
)
2226 DRM_DEBUG_KMS("panel power control backlight %s\n",
2227 enable
? "enable" : "disable");
2230 _intel_edp_backlight_on(intel_dp
);
2232 _intel_edp_backlight_off(intel_dp
);
2235 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2237 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2238 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2239 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2241 I915_STATE_WARN(cur_state
!= state
,
2242 "DP port %c state assertion failure (expected %s, current %s)\n",
2243 port_name(dig_port
->port
),
2244 onoff(state
), onoff(cur_state
));
2246 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2248 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2250 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2252 I915_STATE_WARN(cur_state
!= state
,
2253 "eDP PLL state assertion failure (expected %s, current %s)\n",
2254 onoff(state
), onoff(cur_state
));
2256 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2257 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2259 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2261 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2262 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2263 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2265 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2266 assert_dp_port_disabled(intel_dp
);
2267 assert_edp_pll_disabled(dev_priv
);
2269 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2270 crtc
->config
->port_clock
);
2272 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2274 if (crtc
->config
->port_clock
== 162000)
2275 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2277 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2279 I915_WRITE(DP_A
, intel_dp
->DP
);
2284 * [DevILK] Work around required when enabling DP PLL
2285 * while a pipe is enabled going to FDI:
2286 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2287 * 2. Program DP PLL enable
2289 if (IS_GEN5(dev_priv
))
2290 intel_wait_for_vblank_if_active(dev_priv
->dev
, !crtc
->pipe
);
2292 intel_dp
->DP
|= DP_PLL_ENABLE
;
2294 I915_WRITE(DP_A
, intel_dp
->DP
);
2299 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2301 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2302 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2303 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2305 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2306 assert_dp_port_disabled(intel_dp
);
2307 assert_edp_pll_enabled(dev_priv
);
2309 DRM_DEBUG_KMS("disabling eDP PLL\n");
2311 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2313 I915_WRITE(DP_A
, intel_dp
->DP
);
2318 /* If the sink supports it, try to set the power state appropriately */
2319 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2323 /* Should have a valid DPCD by this point */
2324 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2327 if (mode
!= DRM_MODE_DPMS_ON
) {
2328 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2332 * When turning on, we need to retry for 1ms to give the sink
2335 for (i
= 0; i
< 3; i
++) {
2336 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2345 DRM_DEBUG_KMS("failed to %s sink power state\n",
2346 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2349 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2352 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2353 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2354 struct drm_device
*dev
= encoder
->base
.dev
;
2355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2356 enum intel_display_power_domain power_domain
;
2360 power_domain
= intel_display_port_power_domain(encoder
);
2361 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2366 tmp
= I915_READ(intel_dp
->output_reg
);
2368 if (!(tmp
& DP_PORT_EN
))
2371 if (IS_GEN7(dev
) && port
== PORT_A
) {
2372 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2373 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2376 for_each_pipe(dev_priv
, p
) {
2377 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2378 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2386 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2387 i915_mmio_reg_offset(intel_dp
->output_reg
));
2388 } else if (IS_CHERRYVIEW(dev
)) {
2389 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2391 *pipe
= PORT_TO_PIPE(tmp
);
2397 intel_display_power_put(dev_priv
, power_domain
);
2402 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2403 struct intel_crtc_state
*pipe_config
)
2405 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2407 struct drm_device
*dev
= encoder
->base
.dev
;
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2409 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2410 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2412 tmp
= I915_READ(intel_dp
->output_reg
);
2414 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2416 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2417 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2419 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2420 flags
|= DRM_MODE_FLAG_PHSYNC
;
2422 flags
|= DRM_MODE_FLAG_NHSYNC
;
2424 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2425 flags
|= DRM_MODE_FLAG_PVSYNC
;
2427 flags
|= DRM_MODE_FLAG_NVSYNC
;
2429 if (tmp
& DP_SYNC_HS_HIGH
)
2430 flags
|= DRM_MODE_FLAG_PHSYNC
;
2432 flags
|= DRM_MODE_FLAG_NHSYNC
;
2434 if (tmp
& DP_SYNC_VS_HIGH
)
2435 flags
|= DRM_MODE_FLAG_PVSYNC
;
2437 flags
|= DRM_MODE_FLAG_NVSYNC
;
2440 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2442 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2443 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2444 pipe_config
->limited_color_range
= true;
2446 pipe_config
->has_dp_encoder
= true;
2448 pipe_config
->lane_count
=
2449 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2451 intel_dp_get_m_n(crtc
, pipe_config
);
2453 if (port
== PORT_A
) {
2454 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2455 pipe_config
->port_clock
= 162000;
2457 pipe_config
->port_clock
= 270000;
2460 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2461 intel_dotclock_calculate(pipe_config
->port_clock
,
2462 &pipe_config
->dp_m_n
);
2464 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2465 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2467 * This is a big fat ugly hack.
2469 * Some machines in UEFI boot mode provide us a VBT that has 18
2470 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2471 * unknown we fail to light up. Yet the same BIOS boots up with
2472 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2473 * max, not what it tells us to use.
2475 * Note: This will still be broken if the eDP panel is not lit
2476 * up by the BIOS, and thus we can't get the mode at module
2479 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2480 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2481 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2485 static void intel_disable_dp(struct intel_encoder
*encoder
)
2487 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2488 struct drm_device
*dev
= encoder
->base
.dev
;
2489 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2491 if (crtc
->config
->has_audio
)
2492 intel_audio_codec_disable(encoder
);
2494 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2495 intel_psr_disable(intel_dp
);
2497 /* Make sure the panel is off before trying to change the mode. But also
2498 * ensure that we have vdd while we switch off the panel. */
2499 intel_edp_panel_vdd_on(intel_dp
);
2500 intel_edp_backlight_off(intel_dp
);
2501 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2502 intel_edp_panel_off(intel_dp
);
2504 /* disable the port before the pipe on g4x */
2505 if (INTEL_INFO(dev
)->gen
< 5)
2506 intel_dp_link_down(intel_dp
);
2509 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2511 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2512 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2514 intel_dp_link_down(intel_dp
);
2516 /* Only ilk+ has port A */
2518 ironlake_edp_pll_off(intel_dp
);
2521 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2523 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2525 intel_dp_link_down(intel_dp
);
2528 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2530 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2531 struct drm_device
*dev
= encoder
->base
.dev
;
2532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 intel_dp_link_down(intel_dp
);
2536 mutex_lock(&dev_priv
->sb_lock
);
2538 /* Assert data lane reset */
2539 chv_data_lane_soft_reset(encoder
, true);
2541 mutex_unlock(&dev_priv
->sb_lock
);
2545 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2547 uint8_t dp_train_pat
)
2549 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2550 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2552 enum port port
= intel_dig_port
->port
;
2555 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2557 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2558 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2560 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2562 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2563 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2564 case DP_TRAINING_PATTERN_DISABLE
:
2565 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2568 case DP_TRAINING_PATTERN_1
:
2569 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2571 case DP_TRAINING_PATTERN_2
:
2572 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2574 case DP_TRAINING_PATTERN_3
:
2575 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2578 I915_WRITE(DP_TP_CTL(port
), temp
);
2580 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2581 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2582 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2584 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2585 case DP_TRAINING_PATTERN_DISABLE
:
2586 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2588 case DP_TRAINING_PATTERN_1
:
2589 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2591 case DP_TRAINING_PATTERN_2
:
2592 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2594 case DP_TRAINING_PATTERN_3
:
2595 DRM_ERROR("DP training pattern 3 not supported\n");
2596 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2601 if (IS_CHERRYVIEW(dev
))
2602 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2604 *DP
&= ~DP_LINK_TRAIN_MASK
;
2606 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2607 case DP_TRAINING_PATTERN_DISABLE
:
2608 *DP
|= DP_LINK_TRAIN_OFF
;
2610 case DP_TRAINING_PATTERN_1
:
2611 *DP
|= DP_LINK_TRAIN_PAT_1
;
2613 case DP_TRAINING_PATTERN_2
:
2614 *DP
|= DP_LINK_TRAIN_PAT_2
;
2616 case DP_TRAINING_PATTERN_3
:
2617 if (IS_CHERRYVIEW(dev
)) {
2618 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2620 DRM_ERROR("DP training pattern 3 not supported\n");
2621 *DP
|= DP_LINK_TRAIN_PAT_2
;
2628 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2630 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2632 struct intel_crtc
*crtc
=
2633 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2635 /* enable with pattern 1 (as per spec) */
2636 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2637 DP_TRAINING_PATTERN_1
);
2639 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2640 POSTING_READ(intel_dp
->output_reg
);
2643 * Magic for VLV/CHV. We _must_ first set up the register
2644 * without actually enabling the port, and then do another
2645 * write to enable the port. Otherwise link training will
2646 * fail when the power sequencer is freshly used for this port.
2648 intel_dp
->DP
|= DP_PORT_EN
;
2649 if (crtc
->config
->has_audio
)
2650 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2652 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2653 POSTING_READ(intel_dp
->output_reg
);
2656 static void intel_enable_dp(struct intel_encoder
*encoder
)
2658 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2659 struct drm_device
*dev
= encoder
->base
.dev
;
2660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2661 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2662 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2663 enum pipe pipe
= crtc
->pipe
;
2665 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2670 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2671 vlv_init_panel_power_sequencer(intel_dp
);
2673 intel_dp_enable_port(intel_dp
);
2675 edp_panel_vdd_on(intel_dp
);
2676 edp_panel_on(intel_dp
);
2677 edp_panel_vdd_off(intel_dp
, true);
2679 pps_unlock(intel_dp
);
2681 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2682 unsigned int lane_mask
= 0x0;
2684 if (IS_CHERRYVIEW(dev
))
2685 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2687 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2691 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2692 intel_dp_start_link_train(intel_dp
);
2693 intel_dp_stop_link_train(intel_dp
);
2695 if (crtc
->config
->has_audio
) {
2696 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2698 intel_audio_codec_enable(encoder
);
2702 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2704 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2706 intel_enable_dp(encoder
);
2707 intel_edp_backlight_on(intel_dp
);
2710 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2712 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2714 intel_edp_backlight_on(intel_dp
);
2715 intel_psr_enable(intel_dp
);
2718 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2720 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2721 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2723 intel_dp_prepare(encoder
);
2725 /* Only ilk+ has port A */
2727 ironlake_edp_pll_on(intel_dp
);
2730 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2732 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2733 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2734 enum pipe pipe
= intel_dp
->pps_pipe
;
2735 i915_reg_t pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2737 edp_panel_vdd_off_sync(intel_dp
);
2740 * VLV seems to get confused when multiple power seqeuencers
2741 * have the same port selected (even if only one has power/vdd
2742 * enabled). The failure manifests as vlv_wait_port_ready() failing
2743 * CHV on the other hand doesn't seem to mind having the same port
2744 * selected in multiple power seqeuencers, but let's clear the
2745 * port select always when logically disconnecting a power sequencer
2748 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2749 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2750 I915_WRITE(pp_on_reg
, 0);
2751 POSTING_READ(pp_on_reg
);
2753 intel_dp
->pps_pipe
= INVALID_PIPE
;
2756 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 struct intel_encoder
*encoder
;
2762 lockdep_assert_held(&dev_priv
->pps_mutex
);
2764 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2767 for_each_intel_encoder(dev
, encoder
) {
2768 struct intel_dp
*intel_dp
;
2771 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2774 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2775 port
= dp_to_dig_port(intel_dp
)->port
;
2777 if (intel_dp
->pps_pipe
!= pipe
)
2780 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2781 pipe_name(pipe
), port_name(port
));
2783 WARN(encoder
->base
.crtc
,
2784 "stealing pipe %c power sequencer from active eDP port %c\n",
2785 pipe_name(pipe
), port_name(port
));
2787 /* make sure vdd is off before we steal it */
2788 vlv_detach_power_sequencer(intel_dp
);
2792 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2794 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2795 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2796 struct drm_device
*dev
= encoder
->base
.dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2800 lockdep_assert_held(&dev_priv
->pps_mutex
);
2802 if (!is_edp(intel_dp
))
2805 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2809 * If another power sequencer was being used on this
2810 * port previously make sure to turn off vdd there while
2811 * we still have control of it.
2813 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2814 vlv_detach_power_sequencer(intel_dp
);
2817 * We may be stealing the power
2818 * sequencer from another port.
2820 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2822 /* now it's all ours */
2823 intel_dp
->pps_pipe
= crtc
->pipe
;
2825 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2826 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2828 /* init power sequencer on this pipe and port */
2829 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2830 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2833 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2835 vlv_phy_pre_encoder_enable(encoder
);
2837 intel_enable_dp(encoder
);
2840 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2842 intel_dp_prepare(encoder
);
2844 vlv_phy_pre_pll_enable(encoder
);
2847 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2849 chv_phy_pre_encoder_enable(encoder
);
2851 intel_enable_dp(encoder
);
2853 /* Second common lane will stay alive on its own now */
2854 chv_phy_release_cl2_override(encoder
);
2857 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2859 intel_dp_prepare(encoder
);
2861 chv_phy_pre_pll_enable(encoder
);
2864 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
2866 chv_phy_post_pll_disable(encoder
);
2870 * Fetch AUX CH registers 0x202 - 0x207 which contain
2871 * link status information
2874 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2876 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2877 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2880 /* These are source-specific values. */
2882 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2884 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2888 if (IS_BROXTON(dev
))
2889 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2890 else if (INTEL_INFO(dev
)->gen
>= 9) {
2891 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2892 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2893 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2894 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2896 else if (IS_GEN7(dev
) && port
== PORT_A
)
2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2898 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2905 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2907 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2908 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2910 if (INTEL_INFO(dev
)->gen
>= 9) {
2911 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2921 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2923 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2924 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2933 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2935 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2936 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2947 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2948 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2950 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2953 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2955 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2958 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2972 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
2974 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
2975 unsigned long demph_reg_value
, preemph_reg_value
,
2976 uniqtranscale_reg_value
;
2977 uint8_t train_set
= intel_dp
->train_set
[0];
2979 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2980 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2981 preemph_reg_value
= 0x0004000;
2982 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2984 demph_reg_value
= 0x2B405555;
2985 uniqtranscale_reg_value
= 0x552AB83A;
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2988 demph_reg_value
= 0x2B404040;
2989 uniqtranscale_reg_value
= 0x5548B83A;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2992 demph_reg_value
= 0x2B245555;
2993 uniqtranscale_reg_value
= 0x5560B83A;
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2996 demph_reg_value
= 0x2B405555;
2997 uniqtranscale_reg_value
= 0x5598DA3A;
3003 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3004 preemph_reg_value
= 0x0002000;
3005 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3007 demph_reg_value
= 0x2B404040;
3008 uniqtranscale_reg_value
= 0x5552B83A;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3011 demph_reg_value
= 0x2B404848;
3012 uniqtranscale_reg_value
= 0x5580B83A;
3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3015 demph_reg_value
= 0x2B404040;
3016 uniqtranscale_reg_value
= 0x55ADDA3A;
3022 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3023 preemph_reg_value
= 0x0000000;
3024 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3026 demph_reg_value
= 0x2B305555;
3027 uniqtranscale_reg_value
= 0x5570B83A;
3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3030 demph_reg_value
= 0x2B2B4040;
3031 uniqtranscale_reg_value
= 0x55ADDA3A;
3037 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3038 preemph_reg_value
= 0x0006000;
3039 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3041 demph_reg_value
= 0x1B405555;
3042 uniqtranscale_reg_value
= 0x55ADDA3A;
3052 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3053 uniqtranscale_reg_value
, 0);
3058 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3060 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3061 u32 deemph_reg_value
, margin_reg_value
;
3062 bool uniq_trans_scale
= false;
3063 uint8_t train_set
= intel_dp
->train_set
[0];
3065 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3066 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3067 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3069 deemph_reg_value
= 128;
3070 margin_reg_value
= 52;
3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3073 deemph_reg_value
= 128;
3074 margin_reg_value
= 77;
3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3077 deemph_reg_value
= 128;
3078 margin_reg_value
= 102;
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3081 deemph_reg_value
= 128;
3082 margin_reg_value
= 154;
3083 uniq_trans_scale
= true;
3089 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3090 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3092 deemph_reg_value
= 85;
3093 margin_reg_value
= 78;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3096 deemph_reg_value
= 85;
3097 margin_reg_value
= 116;
3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3100 deemph_reg_value
= 85;
3101 margin_reg_value
= 154;
3107 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3108 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3110 deemph_reg_value
= 64;
3111 margin_reg_value
= 104;
3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3114 deemph_reg_value
= 64;
3115 margin_reg_value
= 154;
3121 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3122 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3124 deemph_reg_value
= 43;
3125 margin_reg_value
= 154;
3135 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3136 margin_reg_value
, uniq_trans_scale
);
3142 gen4_signal_levels(uint8_t train_set
)
3144 uint32_t signal_levels
= 0;
3146 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3147 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3149 signal_levels
|= DP_VOLTAGE_0_4
;
3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3152 signal_levels
|= DP_VOLTAGE_0_6
;
3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3155 signal_levels
|= DP_VOLTAGE_0_8
;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3158 signal_levels
|= DP_VOLTAGE_1_2
;
3161 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3162 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3164 signal_levels
|= DP_PRE_EMPHASIS_0
;
3166 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3167 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3169 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3170 signal_levels
|= DP_PRE_EMPHASIS_6
;
3172 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3173 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3176 return signal_levels
;
3179 /* Gen6's DP voltage swing and pre-emphasis control */
3181 gen6_edp_signal_levels(uint8_t train_set
)
3183 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3184 DP_TRAIN_PRE_EMPHASIS_MASK
);
3185 switch (signal_levels
) {
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3188 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3190 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3193 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3196 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3199 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3201 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3202 "0x%x\n", signal_levels
);
3203 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3207 /* Gen7's DP voltage swing and pre-emphasis control */
3209 gen7_edp_signal_levels(uint8_t train_set
)
3211 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3212 DP_TRAIN_PRE_EMPHASIS_MASK
);
3213 switch (signal_levels
) {
3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3215 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3217 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3219 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3222 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3224 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3227 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3229 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3232 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3233 "0x%x\n", signal_levels
);
3234 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3239 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3241 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3242 enum port port
= intel_dig_port
->port
;
3243 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3244 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3245 uint32_t signal_levels
, mask
= 0;
3246 uint8_t train_set
= intel_dp
->train_set
[0];
3249 signal_levels
= ddi_signal_levels(intel_dp
);
3251 if (IS_BROXTON(dev
))
3254 mask
= DDI_BUF_EMP_MASK
;
3255 } else if (IS_CHERRYVIEW(dev
)) {
3256 signal_levels
= chv_signal_levels(intel_dp
);
3257 } else if (IS_VALLEYVIEW(dev
)) {
3258 signal_levels
= vlv_signal_levels(intel_dp
);
3259 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3260 signal_levels
= gen7_edp_signal_levels(train_set
);
3261 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3262 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3263 signal_levels
= gen6_edp_signal_levels(train_set
);
3264 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3266 signal_levels
= gen4_signal_levels(train_set
);
3267 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3271 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3273 DRM_DEBUG_KMS("Using vswing level %d\n",
3274 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3275 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3276 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3277 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3279 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3281 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3282 POSTING_READ(intel_dp
->output_reg
);
3286 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3287 uint8_t dp_train_pat
)
3289 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3290 struct drm_i915_private
*dev_priv
=
3291 to_i915(intel_dig_port
->base
.base
.dev
);
3293 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3295 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3296 POSTING_READ(intel_dp
->output_reg
);
3299 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3301 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3302 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3304 enum port port
= intel_dig_port
->port
;
3310 val
= I915_READ(DP_TP_CTL(port
));
3311 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3312 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3313 I915_WRITE(DP_TP_CTL(port
), val
);
3316 * On PORT_A we can have only eDP in SST mode. There the only reason
3317 * we need to set idle transmission mode is to work around a HW issue
3318 * where we enable the pipe while not in idle link-training mode.
3319 * In this case there is requirement to wait for a minimum number of
3320 * idle patterns to be sent.
3325 if (intel_wait_for_register(dev_priv
,DP_TP_STATUS(port
),
3326 DP_TP_STATUS_IDLE_DONE
,
3327 DP_TP_STATUS_IDLE_DONE
,
3329 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3333 intel_dp_link_down(struct intel_dp
*intel_dp
)
3335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3336 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3337 enum port port
= intel_dig_port
->port
;
3338 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3340 uint32_t DP
= intel_dp
->DP
;
3342 if (WARN_ON(HAS_DDI(dev
)))
3345 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3348 DRM_DEBUG_KMS("\n");
3350 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3351 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3352 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3353 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3355 if (IS_CHERRYVIEW(dev
))
3356 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3358 DP
&= ~DP_LINK_TRAIN_MASK
;
3359 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3361 I915_WRITE(intel_dp
->output_reg
, DP
);
3362 POSTING_READ(intel_dp
->output_reg
);
3364 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3365 I915_WRITE(intel_dp
->output_reg
, DP
);
3366 POSTING_READ(intel_dp
->output_reg
);
3369 * HW workaround for IBX, we need to move the port
3370 * to transcoder A after disabling it to allow the
3371 * matching HDMI port to be enabled on transcoder A.
3373 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3375 * We get CPU/PCH FIFO underruns on the other pipe when
3376 * doing the workaround. Sweep them under the rug.
3378 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3379 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3381 /* always enable with pattern 1 (as per spec) */
3382 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3383 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3384 I915_WRITE(intel_dp
->output_reg
, DP
);
3385 POSTING_READ(intel_dp
->output_reg
);
3388 I915_WRITE(intel_dp
->output_reg
, DP
);
3389 POSTING_READ(intel_dp
->output_reg
);
3391 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
3392 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3393 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3396 msleep(intel_dp
->panel_power_down_delay
);
3402 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3404 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3405 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3408 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3409 sizeof(intel_dp
->dpcd
)) < 0)
3410 return false; /* aux transfer failed */
3412 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3414 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3415 return false; /* DPCD not present */
3417 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3418 &intel_dp
->sink_count
, 1) < 0)
3422 * Sink count can change between short pulse hpd hence
3423 * a member variable in intel_dp will track any changes
3424 * between short pulse interrupts.
3426 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3429 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3430 * a dongle is present but no display. Unless we require to know
3431 * if a dongle is present or not, we don't need to update
3432 * downstream port information. So, an early return here saves
3433 * time from performing other operations which are not required.
3435 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3438 /* Check if the panel supports PSR */
3439 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3440 if (is_edp(intel_dp
)) {
3441 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3443 sizeof(intel_dp
->psr_dpcd
));
3444 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3445 dev_priv
->psr
.sink_support
= true;
3446 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3449 if (INTEL_INFO(dev
)->gen
>= 9 &&
3450 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3451 uint8_t frame_sync_cap
;
3453 dev_priv
->psr
.sink_support
= true;
3454 drm_dp_dpcd_read(&intel_dp
->aux
,
3455 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3456 &frame_sync_cap
, 1);
3457 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3458 /* PSR2 needs frame sync as well */
3459 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3460 DRM_DEBUG_KMS("PSR2 %s on sink",
3461 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3464 /* Read the eDP Display control capabilities registers */
3465 memset(intel_dp
->edp_dpcd
, 0, sizeof(intel_dp
->edp_dpcd
));
3466 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3467 (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3468 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3469 sizeof(intel_dp
->edp_dpcd
)))
3470 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3471 intel_dp
->edp_dpcd
);
3474 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3475 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
3476 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
3478 /* Intermediate frequency support */
3479 if (is_edp(intel_dp
) && (intel_dp
->edp_dpcd
[0] >= 0x03)) { /* eDp v1.4 or higher */
3480 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3483 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3484 sink_rates
, sizeof(sink_rates
));
3486 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3487 int val
= le16_to_cpu(sink_rates
[i
]);
3492 /* Value read is in kHz while drm clock is saved in deca-kHz */
3493 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3495 intel_dp
->num_sink_rates
= i
;
3498 intel_dp_print_rates(intel_dp
);
3500 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3501 DP_DWN_STRM_PORT_PRESENT
))
3502 return true; /* native DP sink */
3504 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3505 return true; /* no per-port downstream info */
3507 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3508 intel_dp
->downstream_ports
,
3509 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3510 return false; /* downstream port status fetch failed */
3516 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3520 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3523 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3524 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3525 buf
[0], buf
[1], buf
[2]);
3527 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3528 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3529 buf
[0], buf
[1], buf
[2]);
3533 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3537 if (!i915
.enable_dp_mst
)
3540 if (!intel_dp
->can_mst
)
3543 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3546 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3547 if (buf
[0] & DP_MST_CAP
) {
3548 DRM_DEBUG_KMS("Sink is MST capable\n");
3549 intel_dp
->is_mst
= true;
3551 DRM_DEBUG_KMS("Sink is not MST capable\n");
3552 intel_dp
->is_mst
= false;
3556 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3557 return intel_dp
->is_mst
;
3560 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3562 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3563 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3564 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3570 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3571 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3576 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3577 buf
& ~DP_TEST_SINK_START
) < 0) {
3578 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3584 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3586 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3587 DP_TEST_SINK_MISC
, &buf
) < 0) {
3591 count
= buf
& DP_TEST_COUNT_MASK
;
3592 } while (--attempts
&& count
);
3594 if (attempts
== 0) {
3595 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3600 hsw_enable_ips(intel_crtc
);
3604 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3606 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3607 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3608 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3612 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3615 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3618 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3621 if (buf
& DP_TEST_SINK_START
) {
3622 ret
= intel_dp_sink_crc_stop(intel_dp
);
3627 hsw_disable_ips(intel_crtc
);
3629 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3630 buf
| DP_TEST_SINK_START
) < 0) {
3631 hsw_enable_ips(intel_crtc
);
3635 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3639 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3641 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3642 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3643 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3648 ret
= intel_dp_sink_crc_start(intel_dp
);
3653 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3655 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3656 DP_TEST_SINK_MISC
, &buf
) < 0) {
3660 count
= buf
& DP_TEST_COUNT_MASK
;
3662 } while (--attempts
&& count
== 0);
3664 if (attempts
== 0) {
3665 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3670 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3676 intel_dp_sink_crc_stop(intel_dp
);
3681 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3683 return drm_dp_dpcd_read(&intel_dp
->aux
,
3684 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3685 sink_irq_vector
, 1) == 1;
3689 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3693 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3695 sink_irq_vector
, 14);
3702 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3704 uint8_t test_result
= DP_TEST_ACK
;
3708 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3710 uint8_t test_result
= DP_TEST_NAK
;
3714 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3716 uint8_t test_result
= DP_TEST_NAK
;
3717 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3718 struct drm_connector
*connector
= &intel_connector
->base
;
3720 if (intel_connector
->detect_edid
== NULL
||
3721 connector
->edid_corrupt
||
3722 intel_dp
->aux
.i2c_defer_count
> 6) {
3723 /* Check EDID read for NACKs, DEFERs and corruption
3724 * (DP CTS 1.2 Core r1.1)
3725 * 4.2.2.4 : Failed EDID read, I2C_NAK
3726 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3727 * 4.2.2.6 : EDID corruption detected
3728 * Use failsafe mode for all cases
3730 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3731 intel_dp
->aux
.i2c_defer_count
> 0)
3732 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3733 intel_dp
->aux
.i2c_nack_count
,
3734 intel_dp
->aux
.i2c_defer_count
);
3735 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3737 struct edid
*block
= intel_connector
->detect_edid
;
3739 /* We have to write the checksum
3740 * of the last block read
3742 block
+= intel_connector
->detect_edid
->extensions
;
3744 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3745 DP_TEST_EDID_CHECKSUM
,
3748 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3750 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3751 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3754 /* Set test active flag here so userspace doesn't interrupt things */
3755 intel_dp
->compliance_test_active
= 1;
3760 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3762 uint8_t test_result
= DP_TEST_NAK
;
3766 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3768 uint8_t response
= DP_TEST_NAK
;
3772 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3774 DRM_DEBUG_KMS("Could not read test request from sink\n");
3779 case DP_TEST_LINK_TRAINING
:
3780 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3781 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3782 response
= intel_dp_autotest_link_training(intel_dp
);
3784 case DP_TEST_LINK_VIDEO_PATTERN
:
3785 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3786 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3787 response
= intel_dp_autotest_video_pattern(intel_dp
);
3789 case DP_TEST_LINK_EDID_READ
:
3790 DRM_DEBUG_KMS("EDID test requested\n");
3791 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3792 response
= intel_dp_autotest_edid(intel_dp
);
3794 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3795 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3796 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3797 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3800 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3805 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3809 DRM_DEBUG_KMS("Could not write test response to sink\n");
3813 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3817 if (intel_dp
->is_mst
) {
3822 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3826 /* check link status - esi[10] = 0x200c */
3827 if (intel_dp
->active_mst_links
&&
3828 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3829 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3830 intel_dp_start_link_train(intel_dp
);
3831 intel_dp_stop_link_train(intel_dp
);
3834 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3835 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3838 for (retry
= 0; retry
< 3; retry
++) {
3840 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3841 DP_SINK_COUNT_ESI
+1,
3848 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3850 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3858 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3859 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3860 intel_dp
->is_mst
= false;
3861 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3862 /* send a hotplug event */
3863 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3870 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3872 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3873 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3874 u8 link_status
[DP_LINK_STATUS_SIZE
];
3876 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3878 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3879 DRM_ERROR("Failed to get link status\n");
3883 if (!intel_encoder
->base
.crtc
)
3886 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3889 /* if link training is requested we should perform it always */
3890 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
3891 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
3892 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3893 intel_encoder
->base
.name
);
3894 intel_dp_start_link_train(intel_dp
);
3895 intel_dp_stop_link_train(intel_dp
);
3900 * According to DP spec
3903 * 2. Configure link according to Receiver Capabilities
3904 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3905 * 4. Check link status on receipt of hot-plug interrupt
3907 * intel_dp_short_pulse - handles short pulse interrupts
3908 * when full detection is not required.
3909 * Returns %true if short pulse is handled and full detection
3910 * is NOT required and %false otherwise.
3913 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
3915 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3917 u8 old_sink_count
= intel_dp
->sink_count
;
3921 * Clearing compliance test variables to allow capturing
3922 * of values for next automated test request.
3924 intel_dp
->compliance_test_active
= 0;
3925 intel_dp
->compliance_test_type
= 0;
3926 intel_dp
->compliance_test_data
= 0;
3929 * Now read the DPCD to see if it's actually running
3930 * If the current value of sink count doesn't match with
3931 * the value that was stored earlier or dpcd read failed
3932 * we need to do full detection
3934 ret
= intel_dp_get_dpcd(intel_dp
);
3936 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
3937 /* No need to proceed if we are going to do full detect */
3941 /* Try to read the source of the interrupt */
3942 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3943 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3944 /* Clear interrupt source */
3945 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3946 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3949 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3950 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3951 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3952 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3955 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3956 intel_dp_check_link_status(intel_dp
);
3957 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3962 /* XXX this is probably wrong for multiple downstream ports */
3963 static enum drm_connector_status
3964 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3966 uint8_t *dpcd
= intel_dp
->dpcd
;
3969 if (!intel_dp_get_dpcd(intel_dp
))
3970 return connector_status_disconnected
;
3972 if (is_edp(intel_dp
))
3973 return connector_status_connected
;
3975 /* if there's no downstream port, we're done */
3976 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3977 return connector_status_connected
;
3979 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3980 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3981 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3983 return intel_dp
->sink_count
?
3984 connector_status_connected
: connector_status_disconnected
;
3987 /* If no HPD, poke DDC gently */
3988 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3989 return connector_status_connected
;
3991 /* Well we tried, say unknown for unreliable port types */
3992 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3993 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3994 if (type
== DP_DS_PORT_TYPE_VGA
||
3995 type
== DP_DS_PORT_TYPE_NON_EDID
)
3996 return connector_status_unknown
;
3998 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3999 DP_DWN_STRM_PORT_TYPE_MASK
;
4000 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4001 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4002 return connector_status_unknown
;
4005 /* Anything else is out of spec, warn and ignore */
4006 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4007 return connector_status_disconnected
;
4010 static enum drm_connector_status
4011 edp_detect(struct intel_dp
*intel_dp
)
4013 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4014 enum drm_connector_status status
;
4016 status
= intel_panel_detect(dev
);
4017 if (status
== connector_status_unknown
)
4018 status
= connector_status_connected
;
4023 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4024 struct intel_digital_port
*port
)
4028 switch (port
->port
) {
4032 bit
= SDE_PORTB_HOTPLUG
;
4035 bit
= SDE_PORTC_HOTPLUG
;
4038 bit
= SDE_PORTD_HOTPLUG
;
4041 MISSING_CASE(port
->port
);
4045 return I915_READ(SDEISR
) & bit
;
4048 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4049 struct intel_digital_port
*port
)
4053 switch (port
->port
) {
4057 bit
= SDE_PORTB_HOTPLUG_CPT
;
4060 bit
= SDE_PORTC_HOTPLUG_CPT
;
4063 bit
= SDE_PORTD_HOTPLUG_CPT
;
4066 bit
= SDE_PORTE_HOTPLUG_SPT
;
4069 MISSING_CASE(port
->port
);
4073 return I915_READ(SDEISR
) & bit
;
4076 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4077 struct intel_digital_port
*port
)
4081 switch (port
->port
) {
4083 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4086 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4089 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4092 MISSING_CASE(port
->port
);
4096 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4099 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4100 struct intel_digital_port
*port
)
4104 switch (port
->port
) {
4106 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4109 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4112 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4115 MISSING_CASE(port
->port
);
4119 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4122 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4123 struct intel_digital_port
*intel_dig_port
)
4125 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4129 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4132 bit
= BXT_DE_PORT_HP_DDIA
;
4135 bit
= BXT_DE_PORT_HP_DDIB
;
4138 bit
= BXT_DE_PORT_HP_DDIC
;
4145 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4149 * intel_digital_port_connected - is the specified port connected?
4150 * @dev_priv: i915 private structure
4151 * @port: the port to test
4153 * Return %true if @port is connected, %false otherwise.
4155 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4156 struct intel_digital_port
*port
)
4158 if (HAS_PCH_IBX(dev_priv
))
4159 return ibx_digital_port_connected(dev_priv
, port
);
4160 else if (HAS_PCH_SPLIT(dev_priv
))
4161 return cpt_digital_port_connected(dev_priv
, port
);
4162 else if (IS_BROXTON(dev_priv
))
4163 return bxt_digital_port_connected(dev_priv
, port
);
4164 else if (IS_GM45(dev_priv
))
4165 return gm45_digital_port_connected(dev_priv
, port
);
4167 return g4x_digital_port_connected(dev_priv
, port
);
4170 static struct edid
*
4171 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4173 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4175 /* use cached edid if we have one */
4176 if (intel_connector
->edid
) {
4178 if (IS_ERR(intel_connector
->edid
))
4181 return drm_edid_duplicate(intel_connector
->edid
);
4183 return drm_get_edid(&intel_connector
->base
,
4184 &intel_dp
->aux
.ddc
);
4188 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4190 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4193 intel_dp_unset_edid(intel_dp
);
4194 edid
= intel_dp_get_edid(intel_dp
);
4195 intel_connector
->detect_edid
= edid
;
4197 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4198 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4200 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4204 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4206 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4208 kfree(intel_connector
->detect_edid
);
4209 intel_connector
->detect_edid
= NULL
;
4211 intel_dp
->has_audio
= false;
4215 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4217 struct drm_connector
*connector
= &intel_connector
->base
;
4218 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4219 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4220 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4221 struct drm_device
*dev
= connector
->dev
;
4222 enum drm_connector_status status
;
4223 enum intel_display_power_domain power_domain
;
4227 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4228 intel_display_power_get(to_i915(dev
), power_domain
);
4230 /* Can't disconnect eDP, but you can close the lid... */
4231 if (is_edp(intel_dp
))
4232 status
= edp_detect(intel_dp
);
4233 else if (intel_digital_port_connected(to_i915(dev
),
4234 dp_to_dig_port(intel_dp
)))
4235 status
= intel_dp_detect_dpcd(intel_dp
);
4237 status
= connector_status_disconnected
;
4239 if (status
!= connector_status_connected
) {
4240 intel_dp
->compliance_test_active
= 0;
4241 intel_dp
->compliance_test_type
= 0;
4242 intel_dp
->compliance_test_data
= 0;
4244 if (intel_dp
->is_mst
) {
4245 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4247 intel_dp
->mst_mgr
.mst_state
);
4248 intel_dp
->is_mst
= false;
4249 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4256 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4257 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4259 intel_dp_probe_oui(intel_dp
);
4261 ret
= intel_dp_probe_mst(intel_dp
);
4264 * If we are in MST mode then this connector
4265 * won't appear connected or have anything
4268 status
= connector_status_disconnected
;
4270 } else if (connector
->status
== connector_status_connected
) {
4272 * If display was connected already and is still connected
4273 * check links status, there has been known issues of
4274 * link loss triggerring long pulse!!!!
4276 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4277 intel_dp_check_link_status(intel_dp
);
4278 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4283 * Clearing NACK and defer counts to get their exact values
4284 * while reading EDID which are required by Compliance tests
4285 * 4.2.2.4 and 4.2.2.5
4287 intel_dp
->aux
.i2c_nack_count
= 0;
4288 intel_dp
->aux
.i2c_defer_count
= 0;
4290 intel_dp_set_edid(intel_dp
);
4292 status
= connector_status_connected
;
4293 intel_dp
->detect_done
= true;
4295 /* Try to read the source of the interrupt */
4296 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4297 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4298 /* Clear interrupt source */
4299 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4300 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4303 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4304 intel_dp_handle_test_request(intel_dp
);
4305 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4306 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4310 if ((status
!= connector_status_connected
) &&
4311 (intel_dp
->is_mst
== false))
4312 intel_dp_unset_edid(intel_dp
);
4314 intel_display_power_put(to_i915(dev
), power_domain
);
4318 static enum drm_connector_status
4319 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4321 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4322 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4323 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4324 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4327 connector
->base
.id
, connector
->name
);
4329 if (intel_dp
->is_mst
) {
4330 /* MST devices are disconnected from a monitor POV */
4331 intel_dp_unset_edid(intel_dp
);
4332 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4333 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4334 return connector_status_disconnected
;
4337 /* If full detect is not performed yet, do a full detect */
4338 if (!intel_dp
->detect_done
)
4339 intel_dp_long_pulse(intel_dp
->attached_connector
);
4341 intel_dp
->detect_done
= false;
4343 if (intel_connector
->detect_edid
)
4344 return connector_status_connected
;
4346 return connector_status_disconnected
;
4350 intel_dp_force(struct drm_connector
*connector
)
4352 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4353 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4354 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4355 enum intel_display_power_domain power_domain
;
4357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4358 connector
->base
.id
, connector
->name
);
4359 intel_dp_unset_edid(intel_dp
);
4361 if (connector
->status
!= connector_status_connected
)
4364 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4365 intel_display_power_get(dev_priv
, power_domain
);
4367 intel_dp_set_edid(intel_dp
);
4369 intel_display_power_put(dev_priv
, power_domain
);
4371 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4372 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4375 static int intel_dp_get_modes(struct drm_connector
*connector
)
4377 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4380 edid
= intel_connector
->detect_edid
;
4382 int ret
= intel_connector_update_modes(connector
, edid
);
4387 /* if eDP has no EDID, fall back to fixed mode */
4388 if (is_edp(intel_attached_dp(connector
)) &&
4389 intel_connector
->panel
.fixed_mode
) {
4390 struct drm_display_mode
*mode
;
4392 mode
= drm_mode_duplicate(connector
->dev
,
4393 intel_connector
->panel
.fixed_mode
);
4395 drm_mode_probed_add(connector
, mode
);
4404 intel_dp_detect_audio(struct drm_connector
*connector
)
4406 bool has_audio
= false;
4409 edid
= to_intel_connector(connector
)->detect_edid
;
4411 has_audio
= drm_detect_monitor_audio(edid
);
4417 intel_dp_set_property(struct drm_connector
*connector
,
4418 struct drm_property
*property
,
4421 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4422 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4423 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4424 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4427 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4431 if (property
== dev_priv
->force_audio_property
) {
4435 if (i
== intel_dp
->force_audio
)
4438 intel_dp
->force_audio
= i
;
4440 if (i
== HDMI_AUDIO_AUTO
)
4441 has_audio
= intel_dp_detect_audio(connector
);
4443 has_audio
= (i
== HDMI_AUDIO_ON
);
4445 if (has_audio
== intel_dp
->has_audio
)
4448 intel_dp
->has_audio
= has_audio
;
4452 if (property
== dev_priv
->broadcast_rgb_property
) {
4453 bool old_auto
= intel_dp
->color_range_auto
;
4454 bool old_range
= intel_dp
->limited_color_range
;
4457 case INTEL_BROADCAST_RGB_AUTO
:
4458 intel_dp
->color_range_auto
= true;
4460 case INTEL_BROADCAST_RGB_FULL
:
4461 intel_dp
->color_range_auto
= false;
4462 intel_dp
->limited_color_range
= false;
4464 case INTEL_BROADCAST_RGB_LIMITED
:
4465 intel_dp
->color_range_auto
= false;
4466 intel_dp
->limited_color_range
= true;
4472 if (old_auto
== intel_dp
->color_range_auto
&&
4473 old_range
== intel_dp
->limited_color_range
)
4479 if (is_edp(intel_dp
) &&
4480 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4481 if (val
== DRM_MODE_SCALE_NONE
) {
4482 DRM_DEBUG_KMS("no scaling not supported\n");
4485 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4486 val
== DRM_MODE_SCALE_CENTER
) {
4487 DRM_DEBUG_KMS("centering not supported\n");
4491 if (intel_connector
->panel
.fitting_mode
== val
) {
4492 /* the eDP scaling property is not changed */
4495 intel_connector
->panel
.fitting_mode
= val
;
4503 if (intel_encoder
->base
.crtc
)
4504 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4510 intel_dp_connector_register(struct drm_connector
*connector
)
4512 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4515 ret
= intel_connector_register(connector
);
4519 i915_debugfs_connector_add(connector
);
4521 DRM_DEBUG_KMS("registering %s bus for %s\n",
4522 intel_dp
->aux
.name
, connector
->kdev
->kobj
.name
);
4524 intel_dp
->aux
.dev
= connector
->kdev
;
4525 return drm_dp_aux_register(&intel_dp
->aux
);
4529 intel_dp_connector_unregister(struct drm_connector
*connector
)
4531 drm_dp_aux_unregister(&intel_attached_dp(connector
)->aux
);
4532 intel_connector_unregister(connector
);
4536 intel_dp_connector_destroy(struct drm_connector
*connector
)
4538 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4540 kfree(intel_connector
->detect_edid
);
4542 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4543 kfree(intel_connector
->edid
);
4545 /* Can't call is_edp() since the encoder may have been destroyed
4547 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4548 intel_panel_fini(&intel_connector
->panel
);
4550 drm_connector_cleanup(connector
);
4554 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4556 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4557 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4559 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4560 if (is_edp(intel_dp
)) {
4561 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4563 * vdd might still be enabled do to the delayed vdd off.
4564 * Make sure vdd is actually turned off here.
4567 edp_panel_vdd_off_sync(intel_dp
);
4568 pps_unlock(intel_dp
);
4570 if (intel_dp
->edp_notifier
.notifier_call
) {
4571 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4572 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4576 intel_dp_aux_fini(intel_dp
);
4578 drm_encoder_cleanup(encoder
);
4579 kfree(intel_dig_port
);
4582 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4584 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4586 if (!is_edp(intel_dp
))
4590 * vdd might still be enabled do to the delayed vdd off.
4591 * Make sure vdd is actually turned off here.
4593 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4595 edp_panel_vdd_off_sync(intel_dp
);
4596 pps_unlock(intel_dp
);
4599 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4601 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4602 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4604 enum intel_display_power_domain power_domain
;
4606 lockdep_assert_held(&dev_priv
->pps_mutex
);
4608 if (!edp_have_panel_vdd(intel_dp
))
4612 * The VDD bit needs a power domain reference, so if the bit is
4613 * already enabled when we boot or resume, grab this reference and
4614 * schedule a vdd off, so we don't hold on to the reference
4617 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4618 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4619 intel_display_power_get(dev_priv
, power_domain
);
4621 edp_panel_vdd_schedule_off(intel_dp
);
4624 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4626 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4627 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4629 if (!HAS_DDI(dev_priv
))
4630 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4632 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4638 * Read out the current power sequencer assignment,
4639 * in case the BIOS did something with it.
4641 if (IS_VALLEYVIEW(encoder
->dev
) || IS_CHERRYVIEW(encoder
->dev
))
4642 vlv_initial_power_sequencer_setup(intel_dp
);
4644 intel_edp_panel_vdd_sanitize(intel_dp
);
4646 pps_unlock(intel_dp
);
4649 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4650 .dpms
= drm_atomic_helper_connector_dpms
,
4651 .detect
= intel_dp_detect
,
4652 .force
= intel_dp_force
,
4653 .fill_modes
= drm_helper_probe_single_connector_modes
,
4654 .set_property
= intel_dp_set_property
,
4655 .atomic_get_property
= intel_connector_atomic_get_property
,
4656 .late_register
= intel_dp_connector_register
,
4657 .early_unregister
= intel_dp_connector_unregister
,
4658 .destroy
= intel_dp_connector_destroy
,
4659 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4660 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4663 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4664 .get_modes
= intel_dp_get_modes
,
4665 .mode_valid
= intel_dp_mode_valid
,
4668 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4669 .reset
= intel_dp_encoder_reset
,
4670 .destroy
= intel_dp_encoder_destroy
,
4674 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4676 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4677 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4678 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4680 enum intel_display_power_domain power_domain
;
4681 enum irqreturn ret
= IRQ_NONE
;
4683 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4684 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4685 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4687 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4689 * vdd off can generate a long pulse on eDP which
4690 * would require vdd on to handle it, and thus we
4691 * would end up in an endless cycle of
4692 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4694 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4695 port_name(intel_dig_port
->port
));
4699 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4700 port_name(intel_dig_port
->port
),
4701 long_hpd
? "long" : "short");
4703 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4704 intel_display_power_get(dev_priv
, power_domain
);
4707 intel_dp_long_pulse(intel_dp
->attached_connector
);
4708 if (intel_dp
->is_mst
)
4713 if (intel_dp
->is_mst
) {
4714 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4716 * If we were in MST mode, and device is not
4717 * there, get out of MST mode
4719 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4720 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4721 intel_dp
->is_mst
= false;
4722 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4728 if (!intel_dp
->is_mst
) {
4729 if (!intel_dp_short_pulse(intel_dp
)) {
4730 intel_dp_long_pulse(intel_dp
->attached_connector
);
4739 intel_display_power_put(dev_priv
, power_domain
);
4744 /* check the VBT to see whether the eDP is on another port */
4745 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4750 * eDP not supported on g4x. so bail out early just
4751 * for a bit extra safety in case the VBT is bonkers.
4753 if (INTEL_INFO(dev
)->gen
< 5)
4759 return intel_bios_is_port_edp(dev_priv
, port
);
4763 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4765 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4767 intel_attach_force_audio_property(connector
);
4768 intel_attach_broadcast_rgb_property(connector
);
4769 intel_dp
->color_range_auto
= true;
4771 if (is_edp(intel_dp
)) {
4772 drm_mode_create_scaling_mode_property(connector
->dev
);
4773 drm_object_attach_property(
4775 connector
->dev
->mode_config
.scaling_mode_property
,
4776 DRM_MODE_SCALE_ASPECT
);
4777 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4781 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4783 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4784 intel_dp
->last_power_on
= jiffies
;
4785 intel_dp
->last_backlight_off
= jiffies
;
4789 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4790 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4792 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4793 struct pps_registers regs
;
4795 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4797 /* Workaround: Need to write PP_CONTROL with the unlock key as
4798 * the very first thing. */
4799 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4801 pp_on
= I915_READ(regs
.pp_on
);
4802 pp_off
= I915_READ(regs
.pp_off
);
4803 if (!IS_BROXTON(dev_priv
)) {
4804 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4805 pp_div
= I915_READ(regs
.pp_div
);
4808 /* Pull timing values out of registers */
4809 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4810 PANEL_POWER_UP_DELAY_SHIFT
;
4812 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4813 PANEL_LIGHT_ON_DELAY_SHIFT
;
4815 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4816 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4818 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4819 PANEL_POWER_DOWN_DELAY_SHIFT
;
4821 if (IS_BROXTON(dev_priv
)) {
4822 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4823 BXT_POWER_CYCLE_DELAY_SHIFT
;
4825 seq
->t11_t12
= (tmp
- 1) * 1000;
4829 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4830 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4835 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4837 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4839 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4843 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4844 struct intel_dp
*intel_dp
)
4846 struct edp_power_seq hw
;
4847 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4849 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4851 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4852 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4853 DRM_ERROR("PPS state mismatch\n");
4854 intel_pps_dump_state("sw", sw
);
4855 intel_pps_dump_state("hw", &hw
);
4860 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4861 struct intel_dp
*intel_dp
)
4863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4864 struct edp_power_seq cur
, vbt
, spec
,
4865 *final
= &intel_dp
->pps_delays
;
4867 lockdep_assert_held(&dev_priv
->pps_mutex
);
4869 /* already initialized? */
4870 if (final
->t11_t12
!= 0)
4873 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
4875 intel_pps_dump_state("cur", &cur
);
4877 vbt
= dev_priv
->vbt
.edp
.pps
;
4879 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4880 * our hw here, which are all in 100usec. */
4881 spec
.t1_t3
= 210 * 10;
4882 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4883 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4884 spec
.t10
= 500 * 10;
4885 /* This one is special and actually in units of 100ms, but zero
4886 * based in the hw (so we need to add 100 ms). But the sw vbt
4887 * table multiplies it with 1000 to make it in units of 100usec,
4889 spec
.t11_t12
= (510 + 100) * 10;
4891 intel_pps_dump_state("vbt", &vbt
);
4893 /* Use the max of the register settings and vbt. If both are
4894 * unset, fall back to the spec limits. */
4895 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4897 max(cur.field, vbt.field))
4898 assign_final(t1_t3
);
4902 assign_final(t11_t12
);
4905 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4906 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4907 intel_dp
->backlight_on_delay
= get_delay(t8
);
4908 intel_dp
->backlight_off_delay
= get_delay(t9
);
4909 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4910 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4913 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4914 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4915 intel_dp
->panel_power_cycle_delay
);
4917 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4918 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4921 * We override the HW backlight delays to 1 because we do manual waits
4922 * on them. For T8, even BSpec recommends doing it. For T9, if we
4923 * don't do this, we'll end up waiting for the backlight off delay
4924 * twice: once when we do the manual sleep, and once when we disable
4925 * the panel and wait for the PP_STATUS bit to become zero.
4932 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4933 struct intel_dp
*intel_dp
)
4935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4937 int div
= dev_priv
->rawclk_freq
/ 1000;
4938 struct pps_registers regs
;
4939 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4940 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4942 lockdep_assert_held(&dev_priv
->pps_mutex
);
4944 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4946 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4947 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
4948 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4949 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4950 /* Compute the divisor for the pp clock, simply match the Bspec
4952 if (IS_BROXTON(dev
)) {
4953 pp_div
= I915_READ(regs
.pp_ctrl
);
4954 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
4955 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
4956 << BXT_POWER_CYCLE_DELAY_SHIFT
);
4958 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4959 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4960 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4963 /* Haswell doesn't have any port selection bits for the panel
4964 * power sequencer any more. */
4965 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
4966 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4967 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4969 port_sel
= PANEL_PORT_SELECT_DPA
;
4971 port_sel
= PANEL_PORT_SELECT_DPD
;
4976 I915_WRITE(regs
.pp_on
, pp_on
);
4977 I915_WRITE(regs
.pp_off
, pp_off
);
4978 if (IS_BROXTON(dev
))
4979 I915_WRITE(regs
.pp_ctrl
, pp_div
);
4981 I915_WRITE(regs
.pp_div
, pp_div
);
4983 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4984 I915_READ(regs
.pp_on
),
4985 I915_READ(regs
.pp_off
),
4987 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
4988 I915_READ(regs
.pp_div
));
4992 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4994 * @refresh_rate: RR to be programmed
4996 * This function gets called when refresh rate (RR) has to be changed from
4997 * one frequency to another. Switches can be between high and low RR
4998 * supported by the panel or to any other RR based on media playback (in
4999 * this case, RR value needs to be passed from user space).
5001 * The caller of this function needs to take a lock on dev_priv->drrs.
5003 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5006 struct intel_encoder
*encoder
;
5007 struct intel_digital_port
*dig_port
= NULL
;
5008 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5009 struct intel_crtc_state
*config
= NULL
;
5010 struct intel_crtc
*intel_crtc
= NULL
;
5011 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5013 if (refresh_rate
<= 0) {
5014 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5018 if (intel_dp
== NULL
) {
5019 DRM_DEBUG_KMS("DRRS not supported.\n");
5024 * FIXME: This needs proper synchronization with psr state for some
5025 * platforms that cannot have PSR and DRRS enabled at the same time.
5028 dig_port
= dp_to_dig_port(intel_dp
);
5029 encoder
= &dig_port
->base
;
5030 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5033 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5037 config
= intel_crtc
->config
;
5039 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5040 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5044 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5046 index
= DRRS_LOW_RR
;
5048 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5050 "DRRS requested for previously set RR...ignoring\n");
5054 if (!intel_crtc
->active
) {
5055 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5059 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5062 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5065 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5069 DRM_ERROR("Unsupported refreshrate type\n");
5071 } else if (INTEL_INFO(dev
)->gen
> 6) {
5072 i915_reg_t reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5075 val
= I915_READ(reg
);
5076 if (index
> DRRS_HIGH_RR
) {
5077 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5078 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5080 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5082 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5083 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5085 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5087 I915_WRITE(reg
, val
);
5090 dev_priv
->drrs
.refresh_rate_type
= index
;
5092 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5096 * intel_edp_drrs_enable - init drrs struct if supported
5097 * @intel_dp: DP struct
5099 * Initializes frontbuffer_bits and drrs.dp
5101 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5103 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5105 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5106 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5109 if (!intel_crtc
->config
->has_drrs
) {
5110 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5114 mutex_lock(&dev_priv
->drrs
.mutex
);
5115 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5116 DRM_ERROR("DRRS already enabled\n");
5120 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5122 dev_priv
->drrs
.dp
= intel_dp
;
5125 mutex_unlock(&dev_priv
->drrs
.mutex
);
5129 * intel_edp_drrs_disable - Disable DRRS
5130 * @intel_dp: DP struct
5133 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5135 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5137 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5138 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5139 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5141 if (!intel_crtc
->config
->has_drrs
)
5144 mutex_lock(&dev_priv
->drrs
.mutex
);
5145 if (!dev_priv
->drrs
.dp
) {
5146 mutex_unlock(&dev_priv
->drrs
.mutex
);
5150 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5151 intel_dp_set_drrs_state(dev_priv
->dev
,
5152 intel_dp
->attached_connector
->panel
.
5153 fixed_mode
->vrefresh
);
5155 dev_priv
->drrs
.dp
= NULL
;
5156 mutex_unlock(&dev_priv
->drrs
.mutex
);
5158 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5161 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5163 struct drm_i915_private
*dev_priv
=
5164 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5165 struct intel_dp
*intel_dp
;
5167 mutex_lock(&dev_priv
->drrs
.mutex
);
5169 intel_dp
= dev_priv
->drrs
.dp
;
5175 * The delayed work can race with an invalidate hence we need to
5179 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5182 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5183 intel_dp_set_drrs_state(dev_priv
->dev
,
5184 intel_dp
->attached_connector
->panel
.
5185 downclock_mode
->vrefresh
);
5188 mutex_unlock(&dev_priv
->drrs
.mutex
);
5192 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5194 * @frontbuffer_bits: frontbuffer plane tracking bits
5196 * This function gets called everytime rendering on the given planes start.
5197 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5199 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5201 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5202 unsigned frontbuffer_bits
)
5204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5205 struct drm_crtc
*crtc
;
5208 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5211 cancel_delayed_work(&dev_priv
->drrs
.work
);
5213 mutex_lock(&dev_priv
->drrs
.mutex
);
5214 if (!dev_priv
->drrs
.dp
) {
5215 mutex_unlock(&dev_priv
->drrs
.mutex
);
5219 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5220 pipe
= to_intel_crtc(crtc
)->pipe
;
5222 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5223 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5225 /* invalidate means busy screen hence upclock */
5226 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5227 intel_dp_set_drrs_state(dev_priv
->dev
,
5228 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5229 fixed_mode
->vrefresh
);
5231 mutex_unlock(&dev_priv
->drrs
.mutex
);
5235 * intel_edp_drrs_flush - Restart Idleness DRRS
5237 * @frontbuffer_bits: frontbuffer plane tracking bits
5239 * This function gets called every time rendering on the given planes has
5240 * completed or flip on a crtc is completed. So DRRS should be upclocked
5241 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5242 * if no other planes are dirty.
5244 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5246 void intel_edp_drrs_flush(struct drm_device
*dev
,
5247 unsigned frontbuffer_bits
)
5249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5250 struct drm_crtc
*crtc
;
5253 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5256 cancel_delayed_work(&dev_priv
->drrs
.work
);
5258 mutex_lock(&dev_priv
->drrs
.mutex
);
5259 if (!dev_priv
->drrs
.dp
) {
5260 mutex_unlock(&dev_priv
->drrs
.mutex
);
5264 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5265 pipe
= to_intel_crtc(crtc
)->pipe
;
5267 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5268 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5270 /* flush means busy screen hence upclock */
5271 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5272 intel_dp_set_drrs_state(dev_priv
->dev
,
5273 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5274 fixed_mode
->vrefresh
);
5277 * flush also means no more activity hence schedule downclock, if all
5278 * other fbs are quiescent too
5280 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5281 schedule_delayed_work(&dev_priv
->drrs
.work
,
5282 msecs_to_jiffies(1000));
5283 mutex_unlock(&dev_priv
->drrs
.mutex
);
5287 * DOC: Display Refresh Rate Switching (DRRS)
5289 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5290 * which enables swtching between low and high refresh rates,
5291 * dynamically, based on the usage scenario. This feature is applicable
5292 * for internal panels.
5294 * Indication that the panel supports DRRS is given by the panel EDID, which
5295 * would list multiple refresh rates for one resolution.
5297 * DRRS is of 2 types - static and seamless.
5298 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5299 * (may appear as a blink on screen) and is used in dock-undock scenario.
5300 * Seamless DRRS involves changing RR without any visual effect to the user
5301 * and can be used during normal system usage. This is done by programming
5302 * certain registers.
5304 * Support for static/seamless DRRS may be indicated in the VBT based on
5305 * inputs from the panel spec.
5307 * DRRS saves power by switching to low RR based on usage scenarios.
5309 * The implementation is based on frontbuffer tracking implementation. When
5310 * there is a disturbance on the screen triggered by user activity or a periodic
5311 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5312 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5315 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5316 * and intel_edp_drrs_flush() are called.
5318 * DRRS can be further extended to support other internal panels and also
5319 * the scenario of video playback wherein RR is set based on the rate
5320 * requested by userspace.
5324 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5325 * @intel_connector: eDP connector
5326 * @fixed_mode: preferred mode of panel
5328 * This function is called only once at driver load to initialize basic
5332 * Downclock mode if panel supports it, else return NULL.
5333 * DRRS support is determined by the presence of downclock mode (apart
5334 * from VBT setting).
5336 static struct drm_display_mode
*
5337 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5338 struct drm_display_mode
*fixed_mode
)
5340 struct drm_connector
*connector
= &intel_connector
->base
;
5341 struct drm_device
*dev
= connector
->dev
;
5342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 struct drm_display_mode
*downclock_mode
= NULL
;
5345 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5346 mutex_init(&dev_priv
->drrs
.mutex
);
5348 if (INTEL_INFO(dev
)->gen
<= 6) {
5349 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5353 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5354 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5358 downclock_mode
= intel_find_panel_downclock
5359 (dev
, fixed_mode
, connector
);
5361 if (!downclock_mode
) {
5362 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5366 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5368 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5369 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5370 return downclock_mode
;
5373 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5374 struct intel_connector
*intel_connector
)
5376 struct drm_connector
*connector
= &intel_connector
->base
;
5377 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5378 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5379 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5381 struct drm_display_mode
*fixed_mode
= NULL
;
5382 struct drm_display_mode
*downclock_mode
= NULL
;
5384 struct drm_display_mode
*scan
;
5386 enum pipe pipe
= INVALID_PIPE
;
5388 if (!is_edp(intel_dp
))
5392 * On IBX/CPT we may get here with LVDS already registered. Since the
5393 * driver uses the only internal power sequencer available for both
5394 * eDP and LVDS bail out early in this case to prevent interfering
5395 * with an already powered-on LVDS power sequencer.
5397 if (intel_get_lvds_encoder(dev
)) {
5398 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5399 DRM_INFO("LVDS was detected, not registering eDP\n");
5406 intel_dp_init_panel_power_timestamps(intel_dp
);
5408 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5409 vlv_initial_power_sequencer_setup(intel_dp
);
5411 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5412 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5415 intel_edp_panel_vdd_sanitize(intel_dp
);
5417 pps_unlock(intel_dp
);
5419 /* Cache DPCD and EDID for edp. */
5420 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5423 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5424 dev_priv
->no_aux_handshake
=
5425 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5426 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5428 /* if this fails, presume the device is a ghost */
5429 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5433 mutex_lock(&dev
->mode_config
.mutex
);
5434 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5436 if (drm_add_edid_modes(connector
, edid
)) {
5437 drm_mode_connector_update_edid_property(connector
,
5439 drm_edid_to_eld(connector
, edid
);
5442 edid
= ERR_PTR(-EINVAL
);
5445 edid
= ERR_PTR(-ENOENT
);
5447 intel_connector
->edid
= edid
;
5449 /* prefer fixed mode from EDID if available */
5450 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5451 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5452 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5453 downclock_mode
= intel_dp_drrs_init(
5454 intel_connector
, fixed_mode
);
5459 /* fallback to VBT if available for eDP */
5460 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5461 fixed_mode
= drm_mode_duplicate(dev
,
5462 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5464 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5465 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5466 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5469 mutex_unlock(&dev
->mode_config
.mutex
);
5471 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5472 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5473 register_reboot_notifier(&intel_dp
->edp_notifier
);
5476 * Figure out the current pipe for the initial backlight setup.
5477 * If the current pipe isn't valid, try the PPS pipe, and if that
5478 * fails just assume pipe A.
5480 if (IS_CHERRYVIEW(dev
))
5481 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5483 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5485 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5486 pipe
= intel_dp
->pps_pipe
;
5488 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5491 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5495 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5496 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5497 intel_panel_setup_backlight(connector
, pipe
);
5502 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5504 * vdd might still be enabled do to the delayed vdd off.
5505 * Make sure vdd is actually turned off here.
5508 edp_panel_vdd_off_sync(intel_dp
);
5509 pps_unlock(intel_dp
);
5515 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5516 struct intel_connector
*intel_connector
)
5518 struct drm_connector
*connector
= &intel_connector
->base
;
5519 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5520 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5521 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5523 enum port port
= intel_dig_port
->port
;
5526 if (WARN(intel_dig_port
->max_lanes
< 1,
5527 "Not enough lanes (%d) for DP on port %c\n",
5528 intel_dig_port
->max_lanes
, port_name(port
)))
5531 intel_dp
->pps_pipe
= INVALID_PIPE
;
5533 /* intel_dp vfuncs */
5534 if (INTEL_INFO(dev
)->gen
>= 9)
5535 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5536 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5537 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5538 else if (HAS_PCH_SPLIT(dev
))
5539 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5541 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5543 if (INTEL_INFO(dev
)->gen
>= 9)
5544 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5546 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5549 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5551 /* Preserve the current hw state. */
5552 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5553 intel_dp
->attached_connector
= intel_connector
;
5555 if (intel_dp_is_edp(dev
, port
))
5556 type
= DRM_MODE_CONNECTOR_eDP
;
5558 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5561 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5562 * for DP the encoder type can be set by the caller to
5563 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5565 if (type
== DRM_MODE_CONNECTOR_eDP
)
5566 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5568 /* eDP only on port B and/or C on vlv/chv */
5569 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5570 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5573 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5574 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5577 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5578 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5580 connector
->interlace_allowed
= true;
5581 connector
->doublescan_allowed
= 0;
5583 intel_dp_aux_init(intel_dp
, intel_connector
);
5585 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5586 edp_panel_vdd_work
);
5588 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5591 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5593 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5595 /* Set up the hotplug pin. */
5598 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5601 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5602 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5603 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5606 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5609 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5612 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5618 /* init MST on ports that can support it */
5619 if (HAS_DP_MST(dev
) &&
5620 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5621 intel_dp_mst_encoder_init(intel_dig_port
,
5622 intel_connector
->base
.base
.id
);
5624 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5625 intel_dp_aux_fini(intel_dp
);
5626 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5630 intel_dp_add_properties(intel_dp
, connector
);
5632 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5633 * 0xd. Failure to do so will result in spurious interrupts being
5634 * generated on the port when a cable is not attached.
5636 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5637 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5638 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5644 drm_connector_cleanup(connector
);
5649 bool intel_dp_init(struct drm_device
*dev
,
5650 i915_reg_t output_reg
,
5653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5654 struct intel_digital_port
*intel_dig_port
;
5655 struct intel_encoder
*intel_encoder
;
5656 struct drm_encoder
*encoder
;
5657 struct intel_connector
*intel_connector
;
5659 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5660 if (!intel_dig_port
)
5663 intel_connector
= intel_connector_alloc();
5664 if (!intel_connector
)
5665 goto err_connector_alloc
;
5667 intel_encoder
= &intel_dig_port
->base
;
5668 encoder
= &intel_encoder
->base
;
5670 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5671 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5672 goto err_encoder_init
;
5674 intel_encoder
->compute_config
= intel_dp_compute_config
;
5675 intel_encoder
->disable
= intel_disable_dp
;
5676 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5677 intel_encoder
->get_config
= intel_dp_get_config
;
5678 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5679 if (IS_CHERRYVIEW(dev
)) {
5680 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5681 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5682 intel_encoder
->enable
= vlv_enable_dp
;
5683 intel_encoder
->post_disable
= chv_post_disable_dp
;
5684 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5685 } else if (IS_VALLEYVIEW(dev
)) {
5686 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5687 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5688 intel_encoder
->enable
= vlv_enable_dp
;
5689 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5691 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5692 intel_encoder
->enable
= g4x_enable_dp
;
5693 if (INTEL_INFO(dev
)->gen
>= 5)
5694 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5697 intel_dig_port
->port
= port
;
5698 intel_dig_port
->dp
.output_reg
= output_reg
;
5699 intel_dig_port
->max_lanes
= 4;
5701 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5702 if (IS_CHERRYVIEW(dev
)) {
5704 intel_encoder
->crtc_mask
= 1 << 2;
5706 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5708 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5710 intel_encoder
->cloneable
= 0;
5712 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5713 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5715 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5716 goto err_init_connector
;
5721 drm_encoder_cleanup(encoder
);
5723 kfree(intel_connector
);
5724 err_connector_alloc
:
5725 kfree(intel_dig_port
);
5729 void intel_dp_mst_suspend(struct drm_device
*dev
)
5731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5735 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5736 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5737 if (!intel_dig_port
)
5740 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5741 if (!intel_dig_port
->dp
.can_mst
)
5743 if (intel_dig_port
->dp
.is_mst
)
5744 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5749 void intel_dp_mst_resume(struct drm_device
*dev
)
5751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5754 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5755 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5756 if (!intel_dig_port
)
5758 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5761 if (!intel_dig_port
->dp
.can_mst
)
5764 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5766 intel_dp_check_mst_status(&intel_dig_port
->dp
);