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drm/i915: dp: fix order of dp aux i2c device cleanup
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44 };
45
46 static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51 };
52
53 static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58 };
59
60 static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65 };
66
67 /**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74 static bool is_edp(struct intel_dp *intel_dp)
75 {
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 }
80
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82 {
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
86 }
87
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89 {
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 }
92
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static void edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
96
97 static int
98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
99 {
100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
113 break;
114 default:
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121 }
122
123 /*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
140 static int
141 intel_dp_link_required(int pixel_clock, int bpp)
142 {
143 return (pixel_clock * bpp + 9) / 10;
144 }
145
146 static int
147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148 {
149 return (max_link_clock * max_lanes * 8) / 10;
150 }
151
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155 {
156 struct intel_dp *intel_dp = intel_attached_dp(connector);
157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
161
162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
164 return MODE_PANEL;
165
166 if (mode->vdisplay > fixed_mode->vdisplay)
167 return MODE_PANEL;
168
169 target_clock = fixed_mode->clock;
170 }
171
172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
179 return MODE_CLOCK_HIGH;
180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
187 return MODE_OK;
188 }
189
190 static uint32_t
191 pack_aux(uint8_t *src, int src_bytes)
192 {
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201 }
202
203 static void
204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205 {
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211 }
212
213 /* hrawclock is 1/4 the FSB frequency */
214 static int
215 intel_hrawclk(struct drm_device *dev)
216 {
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245 }
246
247 static void
248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251 static void
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256 static enum pipe
257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258 {
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282 }
283
284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285 {
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292 }
293
294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295 {
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302 }
303
304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
305 {
306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 struct drm_i915_private *dev_priv = dev->dev_private;
308
309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
310 }
311
312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
313 {
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
318 }
319
320 static void
321 intel_dp_check_edp(struct intel_dp *intel_dp)
322 {
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (!is_edp(intel_dp))
327 return;
328
329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
334 }
335 }
336
337 static uint32_t
338 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339 {
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
344 uint32_t status;
345 bool done;
346
347 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
348 if (has_aux_irq)
349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
350 msecs_to_jiffies_timeout(10));
351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356 #undef C
357
358 return status;
359 }
360
361 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
362 {
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365
366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
369 */
370 return index ? 0 : intel_hrawclk(dev) / 2;
371 }
372
373 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374 {
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
384 else
385 return 225; /* eDP input clock at 450Mhz */
386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389 }
390
391 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392 {
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
408 } else {
409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
410 }
411 }
412
413 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414 {
415 return index ? 0 : 100;
416 }
417
418 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422 {
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
438 DP_AUX_CH_CTL_DONE |
439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
441 timeout |
442 DP_AUX_CH_CTL_RECEIVE_ERROR |
443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
446 }
447
448 static int
449 intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452 {
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
458 uint32_t aux_clock_divider;
459 int i, ret, recv_bytes;
460 uint32_t status;
461 int try, clock = 0;
462 bool has_aux_irq = true;
463
464 /* dp aux is extremely sensitive to irq latency, hence request the
465 * lowest possible wakeup latency and so prevent the cpu from going into
466 * deep sleep states.
467 */
468 pm_qos_update_request(&dev_priv->pm_qos, 0);
469
470 intel_dp_check_edp(intel_dp);
471
472 intel_aux_display_runtime_get(dev_priv);
473
474 /* Try to wait for any previous AUX channel activity */
475 for (try = 0; try < 3; try++) {
476 status = I915_READ_NOTRACE(ch_ctl);
477 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
478 break;
479 msleep(1);
480 }
481
482 if (try == 3) {
483 WARN(1, "dp_aux_ch not started status 0x%08x\n",
484 I915_READ(ch_ctl));
485 ret = -EBUSY;
486 goto out;
487 }
488
489 /* Only 5 data registers! */
490 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
491 ret = -E2BIG;
492 goto out;
493 }
494
495 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
496 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
497 has_aux_irq,
498 send_bytes,
499 aux_clock_divider);
500
501 /* Must try at least 3 times according to DP spec */
502 for (try = 0; try < 5; try++) {
503 /* Load the send data into the aux channel data registers */
504 for (i = 0; i < send_bytes; i += 4)
505 I915_WRITE(ch_data + i,
506 pack_aux(send + i, send_bytes - i));
507
508 /* Send the command and wait for it to complete */
509 I915_WRITE(ch_ctl, send_ctl);
510
511 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
512
513 /* Clear done status and any errors */
514 I915_WRITE(ch_ctl,
515 status |
516 DP_AUX_CH_CTL_DONE |
517 DP_AUX_CH_CTL_TIME_OUT_ERROR |
518 DP_AUX_CH_CTL_RECEIVE_ERROR);
519
520 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR))
522 continue;
523 if (status & DP_AUX_CH_CTL_DONE)
524 break;
525 }
526 if (status & DP_AUX_CH_CTL_DONE)
527 break;
528 }
529
530 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
532 ret = -EBUSY;
533 goto out;
534 }
535
536 /* Check for timeout or receive error.
537 * Timeouts occur when the sink is not connected
538 */
539 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
541 ret = -EIO;
542 goto out;
543 }
544
545 /* Timeouts occur when the device isn't connected, so they're
546 * "normal" -- don't fill the kernel log with these */
547 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
549 ret = -ETIMEDOUT;
550 goto out;
551 }
552
553 /* Unload any bytes sent back from the other side */
554 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
556 if (recv_bytes > recv_size)
557 recv_bytes = recv_size;
558
559 for (i = 0; i < recv_bytes; i += 4)
560 unpack_aux(I915_READ(ch_data + i),
561 recv + i, recv_bytes - i);
562
563 ret = recv_bytes;
564 out:
565 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
566 intel_aux_display_runtime_put(dev_priv);
567
568 return ret;
569 }
570
571 /* Write data to the aux channel in native mode */
572 static int
573 intel_dp_aux_native_write(struct intel_dp *intel_dp,
574 uint16_t address, uint8_t *send, int send_bytes)
575 {
576 int ret;
577 uint8_t msg[20];
578 int msg_bytes;
579 uint8_t ack;
580
581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
584 intel_dp_check_edp(intel_dp);
585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
586 msg[1] = address >> 8;
587 msg[2] = address & 0xff;
588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
591 for (;;) {
592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
593 if (ret < 0)
594 return ret;
595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
597 break;
598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
599 udelay(100);
600 else
601 return -EIO;
602 }
603 return send_bytes;
604 }
605
606 /* Write a single byte to the aux channel in native mode */
607 static int
608 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
609 uint16_t address, uint8_t byte)
610 {
611 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
612 }
613
614 /* read bytes from a native aux channel */
615 static int
616 intel_dp_aux_native_read(struct intel_dp *intel_dp,
617 uint16_t address, uint8_t *recv, int recv_bytes)
618 {
619 uint8_t msg[4];
620 int msg_bytes;
621 uint8_t reply[20];
622 int reply_bytes;
623 uint8_t ack;
624 int ret;
625
626 if (WARN_ON(recv_bytes > 19))
627 return -E2BIG;
628
629 intel_dp_check_edp(intel_dp);
630 msg[0] = DP_AUX_NATIVE_READ << 4;
631 msg[1] = address >> 8;
632 msg[2] = address & 0xff;
633 msg[3] = recv_bytes - 1;
634
635 msg_bytes = 4;
636 reply_bytes = recv_bytes + 1;
637
638 for (;;) {
639 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
640 reply, reply_bytes);
641 if (ret == 0)
642 return -EPROTO;
643 if (ret < 0)
644 return ret;
645 ack = reply[0] >> 4;
646 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
647 memcpy(recv, reply + 1, ret - 1);
648 return ret - 1;
649 }
650 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
651 udelay(100);
652 else
653 return -EIO;
654 }
655 }
656
657 static int
658 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
659 uint8_t write_byte, uint8_t *read_byte)
660 {
661 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
662 struct intel_dp *intel_dp = container_of(adapter,
663 struct intel_dp,
664 adapter);
665 uint16_t address = algo_data->address;
666 uint8_t msg[5];
667 uint8_t reply[2];
668 unsigned retry;
669 int msg_bytes;
670 int reply_bytes;
671 int ret;
672
673 edp_panel_vdd_on(intel_dp);
674 intel_dp_check_edp(intel_dp);
675 /* Set up the command byte */
676 if (mode & MODE_I2C_READ)
677 msg[0] = DP_AUX_I2C_READ << 4;
678 else
679 msg[0] = DP_AUX_I2C_WRITE << 4;
680
681 if (!(mode & MODE_I2C_STOP))
682 msg[0] |= DP_AUX_I2C_MOT << 4;
683
684 msg[1] = address >> 8;
685 msg[2] = address;
686
687 switch (mode) {
688 case MODE_I2C_WRITE:
689 msg[3] = 0;
690 msg[4] = write_byte;
691 msg_bytes = 5;
692 reply_bytes = 1;
693 break;
694 case MODE_I2C_READ:
695 msg[3] = 0;
696 msg_bytes = 4;
697 reply_bytes = 2;
698 break;
699 default:
700 msg_bytes = 3;
701 reply_bytes = 1;
702 break;
703 }
704
705 /*
706 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
707 * required to retry at least seven times upon receiving AUX_DEFER
708 * before giving up the AUX transaction.
709 */
710 for (retry = 0; retry < 7; retry++) {
711 ret = intel_dp_aux_ch(intel_dp,
712 msg, msg_bytes,
713 reply, reply_bytes);
714 if (ret < 0) {
715 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
716 goto out;
717 }
718
719 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
720 case DP_AUX_NATIVE_REPLY_ACK:
721 /* I2C-over-AUX Reply field is only valid
722 * when paired with AUX ACK.
723 */
724 break;
725 case DP_AUX_NATIVE_REPLY_NACK:
726 DRM_DEBUG_KMS("aux_ch native nack\n");
727 ret = -EREMOTEIO;
728 goto out;
729 case DP_AUX_NATIVE_REPLY_DEFER:
730 /*
731 * For now, just give more slack to branch devices. We
732 * could check the DPCD for I2C bit rate capabilities,
733 * and if available, adjust the interval. We could also
734 * be more careful with DP-to-Legacy adapters where a
735 * long legacy cable may force very low I2C bit rates.
736 */
737 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
738 DP_DWN_STRM_PORT_PRESENT)
739 usleep_range(500, 600);
740 else
741 usleep_range(300, 400);
742 continue;
743 default:
744 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
745 reply[0]);
746 ret = -EREMOTEIO;
747 goto out;
748 }
749
750 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
751 case DP_AUX_I2C_REPLY_ACK:
752 if (mode == MODE_I2C_READ) {
753 *read_byte = reply[1];
754 }
755 ret = reply_bytes - 1;
756 goto out;
757 case DP_AUX_I2C_REPLY_NACK:
758 DRM_DEBUG_KMS("aux_i2c nack\n");
759 ret = -EREMOTEIO;
760 goto out;
761 case DP_AUX_I2C_REPLY_DEFER:
762 DRM_DEBUG_KMS("aux_i2c defer\n");
763 udelay(100);
764 break;
765 default:
766 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
767 ret = -EREMOTEIO;
768 goto out;
769 }
770 }
771
772 DRM_ERROR("too many retries, giving up\n");
773 ret = -EREMOTEIO;
774
775 out:
776 edp_panel_vdd_off(intel_dp, false);
777 return ret;
778 }
779
780 static void
781 intel_dp_connector_unregister(struct intel_connector *intel_connector)
782 {
783 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
784
785 sysfs_remove_link(&intel_connector->base.kdev->kobj,
786 intel_dp->adapter.dev.kobj.name);
787 intel_connector_unregister(intel_connector);
788 }
789
790 static int
791 intel_dp_i2c_init(struct intel_dp *intel_dp,
792 struct intel_connector *intel_connector, const char *name)
793 {
794 int ret;
795
796 DRM_DEBUG_KMS("i2c_init %s\n", name);
797 intel_dp->algo.running = false;
798 intel_dp->algo.address = 0;
799 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
800
801 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
802 intel_dp->adapter.owner = THIS_MODULE;
803 intel_dp->adapter.class = I2C_CLASS_DDC;
804 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
805 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
806 intel_dp->adapter.algo_data = &intel_dp->algo;
807 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
808
809 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
810 if (ret < 0)
811 return ret;
812
813 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
814 &intel_dp->adapter.dev.kobj,
815 intel_dp->adapter.dev.kobj.name);
816
817 if (ret < 0)
818 i2c_del_adapter(&intel_dp->adapter);
819
820 return ret;
821 }
822
823 static void
824 intel_dp_set_clock(struct intel_encoder *encoder,
825 struct intel_crtc_config *pipe_config, int link_bw)
826 {
827 struct drm_device *dev = encoder->base.dev;
828 const struct dp_link_dpll *divisor = NULL;
829 int i, count = 0;
830
831 if (IS_G4X(dev)) {
832 divisor = gen4_dpll;
833 count = ARRAY_SIZE(gen4_dpll);
834 } else if (IS_HASWELL(dev)) {
835 /* Haswell has special-purpose DP DDI clocks. */
836 } else if (HAS_PCH_SPLIT(dev)) {
837 divisor = pch_dpll;
838 count = ARRAY_SIZE(pch_dpll);
839 } else if (IS_VALLEYVIEW(dev)) {
840 divisor = vlv_dpll;
841 count = ARRAY_SIZE(vlv_dpll);
842 }
843
844 if (divisor && count) {
845 for (i = 0; i < count; i++) {
846 if (link_bw == divisor[i].link_bw) {
847 pipe_config->dpll = divisor[i].dpll;
848 pipe_config->clock_set = true;
849 break;
850 }
851 }
852 }
853 }
854
855 bool
856 intel_dp_compute_config(struct intel_encoder *encoder,
857 struct intel_crtc_config *pipe_config)
858 {
859 struct drm_device *dev = encoder->base.dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
862 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
863 enum port port = dp_to_dig_port(intel_dp)->port;
864 struct intel_crtc *intel_crtc = encoder->new_crtc;
865 struct intel_connector *intel_connector = intel_dp->attached_connector;
866 int lane_count, clock;
867 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
868 /* Conveniently, the link BW constants become indices with a shift...*/
869 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
870 int bpp, mode_rate;
871 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
872 int link_avail, link_clock;
873
874 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
875 pipe_config->has_pch_encoder = true;
876
877 pipe_config->has_dp_encoder = true;
878
879 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
880 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
881 adjusted_mode);
882 if (!HAS_PCH_SPLIT(dev))
883 intel_gmch_panel_fitting(intel_crtc, pipe_config,
884 intel_connector->panel.fitting_mode);
885 else
886 intel_pch_panel_fitting(intel_crtc, pipe_config,
887 intel_connector->panel.fitting_mode);
888 }
889
890 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
891 return false;
892
893 DRM_DEBUG_KMS("DP link computation with max lane count %i "
894 "max bw %02x pixel clock %iKHz\n",
895 max_lane_count, bws[max_clock],
896 adjusted_mode->crtc_clock);
897
898 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
899 * bpc in between. */
900 bpp = pipe_config->pipe_bpp;
901 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
902 dev_priv->vbt.edp_bpp < bpp) {
903 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
904 dev_priv->vbt.edp_bpp);
905 bpp = dev_priv->vbt.edp_bpp;
906 }
907
908 for (; bpp >= 6*3; bpp -= 2*3) {
909 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
910 bpp);
911
912 for (clock = 0; clock <= max_clock; clock++) {
913 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
914 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
915 link_avail = intel_dp_max_data_rate(link_clock,
916 lane_count);
917
918 if (mode_rate <= link_avail) {
919 goto found;
920 }
921 }
922 }
923 }
924
925 return false;
926
927 found:
928 if (intel_dp->color_range_auto) {
929 /*
930 * See:
931 * CEA-861-E - 5.1 Default Encoding Parameters
932 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
933 */
934 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
935 intel_dp->color_range = DP_COLOR_RANGE_16_235;
936 else
937 intel_dp->color_range = 0;
938 }
939
940 if (intel_dp->color_range)
941 pipe_config->limited_color_range = true;
942
943 intel_dp->link_bw = bws[clock];
944 intel_dp->lane_count = lane_count;
945 pipe_config->pipe_bpp = bpp;
946 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
947
948 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
949 intel_dp->link_bw, intel_dp->lane_count,
950 pipe_config->port_clock, bpp);
951 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
952 mode_rate, link_avail);
953
954 intel_link_compute_m_n(bpp, lane_count,
955 adjusted_mode->crtc_clock,
956 pipe_config->port_clock,
957 &pipe_config->dp_m_n);
958
959 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
960
961 return true;
962 }
963
964 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
965 {
966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
967 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
968 struct drm_device *dev = crtc->base.dev;
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 u32 dpa_ctl;
971
972 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
973 dpa_ctl = I915_READ(DP_A);
974 dpa_ctl &= ~DP_PLL_FREQ_MASK;
975
976 if (crtc->config.port_clock == 162000) {
977 /* For a long time we've carried around a ILK-DevA w/a for the
978 * 160MHz clock. If we're really unlucky, it's still required.
979 */
980 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
981 dpa_ctl |= DP_PLL_FREQ_160MHZ;
982 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
983 } else {
984 dpa_ctl |= DP_PLL_FREQ_270MHZ;
985 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
986 }
987
988 I915_WRITE(DP_A, dpa_ctl);
989
990 POSTING_READ(DP_A);
991 udelay(500);
992 }
993
994 static void intel_dp_mode_set(struct intel_encoder *encoder)
995 {
996 struct drm_device *dev = encoder->base.dev;
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
999 enum port port = dp_to_dig_port(intel_dp)->port;
1000 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1001 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1002
1003 /*
1004 * There are four kinds of DP registers:
1005 *
1006 * IBX PCH
1007 * SNB CPU
1008 * IVB CPU
1009 * CPT PCH
1010 *
1011 * IBX PCH and CPU are the same for almost everything,
1012 * except that the CPU DP PLL is configured in this
1013 * register
1014 *
1015 * CPT PCH is quite different, having many bits moved
1016 * to the TRANS_DP_CTL register instead. That
1017 * configuration happens (oddly) in ironlake_pch_enable
1018 */
1019
1020 /* Preserve the BIOS-computed detected bit. This is
1021 * supposed to be read-only.
1022 */
1023 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1024
1025 /* Handle DP bits in common between all three register formats */
1026 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1027 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1028
1029 if (intel_dp->has_audio) {
1030 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1031 pipe_name(crtc->pipe));
1032 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1033 intel_write_eld(&encoder->base, adjusted_mode);
1034 }
1035
1036 /* Split out the IBX/CPU vs CPT settings */
1037
1038 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1039 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1040 intel_dp->DP |= DP_SYNC_HS_HIGH;
1041 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1042 intel_dp->DP |= DP_SYNC_VS_HIGH;
1043 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1044
1045 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1046 intel_dp->DP |= DP_ENHANCED_FRAMING;
1047
1048 intel_dp->DP |= crtc->pipe << 29;
1049 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1050 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1051 intel_dp->DP |= intel_dp->color_range;
1052
1053 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1054 intel_dp->DP |= DP_SYNC_HS_HIGH;
1055 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1056 intel_dp->DP |= DP_SYNC_VS_HIGH;
1057 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1058
1059 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1060 intel_dp->DP |= DP_ENHANCED_FRAMING;
1061
1062 if (crtc->pipe == 1)
1063 intel_dp->DP |= DP_PIPEB_SELECT;
1064 } else {
1065 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1066 }
1067
1068 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1069 ironlake_set_pll_cpu_edp(intel_dp);
1070 }
1071
1072 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1073 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1074
1075 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1076 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1077
1078 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1079 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1080
1081 static void wait_panel_status(struct intel_dp *intel_dp,
1082 u32 mask,
1083 u32 value)
1084 {
1085 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 u32 pp_stat_reg, pp_ctrl_reg;
1088
1089 pp_stat_reg = _pp_stat_reg(intel_dp);
1090 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1091
1092 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1093 mask, value,
1094 I915_READ(pp_stat_reg),
1095 I915_READ(pp_ctrl_reg));
1096
1097 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1098 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1099 I915_READ(pp_stat_reg),
1100 I915_READ(pp_ctrl_reg));
1101 }
1102
1103 DRM_DEBUG_KMS("Wait complete\n");
1104 }
1105
1106 static void wait_panel_on(struct intel_dp *intel_dp)
1107 {
1108 DRM_DEBUG_KMS("Wait for panel power on\n");
1109 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1110 }
1111
1112 static void wait_panel_off(struct intel_dp *intel_dp)
1113 {
1114 DRM_DEBUG_KMS("Wait for panel power off time\n");
1115 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1116 }
1117
1118 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1119 {
1120 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1121
1122 /* When we disable the VDD override bit last we have to do the manual
1123 * wait. */
1124 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1125 intel_dp->panel_power_cycle_delay);
1126
1127 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1128 }
1129
1130 static void wait_backlight_on(struct intel_dp *intel_dp)
1131 {
1132 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1133 intel_dp->backlight_on_delay);
1134 }
1135
1136 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1137 {
1138 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1139 intel_dp->backlight_off_delay);
1140 }
1141
1142 /* Read the current pp_control value, unlocking the register if it
1143 * is locked
1144 */
1145
1146 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1147 {
1148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 u32 control;
1151
1152 control = I915_READ(_pp_ctrl_reg(intel_dp));
1153 control &= ~PANEL_UNLOCK_MASK;
1154 control |= PANEL_UNLOCK_REGS;
1155 return control;
1156 }
1157
1158 static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1159 {
1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 pp;
1163 u32 pp_stat_reg, pp_ctrl_reg;
1164
1165 if (!is_edp(intel_dp))
1166 return;
1167
1168 WARN(intel_dp->want_panel_vdd,
1169 "eDP VDD already requested on\n");
1170
1171 intel_dp->want_panel_vdd = true;
1172
1173 if (edp_have_panel_vdd(intel_dp))
1174 return;
1175
1176 intel_runtime_pm_get(dev_priv);
1177
1178 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1179
1180 if (!edp_have_panel_power(intel_dp))
1181 wait_panel_power_cycle(intel_dp);
1182
1183 pp = ironlake_get_pp_control(intel_dp);
1184 pp |= EDP_FORCE_VDD;
1185
1186 pp_stat_reg = _pp_stat_reg(intel_dp);
1187 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
1191 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1192 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1193 /*
1194 * If the panel wasn't on, delay before accessing aux channel
1195 */
1196 if (!edp_have_panel_power(intel_dp)) {
1197 DRM_DEBUG_KMS("eDP was not running\n");
1198 msleep(intel_dp->panel_power_up_delay);
1199 }
1200 }
1201
1202 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1203 {
1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
1207 u32 pp_stat_reg, pp_ctrl_reg;
1208
1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1210
1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1212 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1213
1214 pp = ironlake_get_pp_control(intel_dp);
1215 pp &= ~EDP_FORCE_VDD;
1216
1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1218 pp_stat_reg = _pp_stat_reg(intel_dp);
1219
1220 I915_WRITE(pp_ctrl_reg, pp);
1221 POSTING_READ(pp_ctrl_reg);
1222
1223 /* Make sure sequencer is idle before allowing subsequent activity */
1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1226
1227 if ((pp & POWER_TARGET_ON) == 0)
1228 intel_dp->last_power_cycle = jiffies;
1229
1230 intel_runtime_pm_put(dev_priv);
1231 }
1232 }
1233
1234 static void edp_panel_vdd_work(struct work_struct *__work)
1235 {
1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1237 struct intel_dp, panel_vdd_work);
1238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1239
1240 mutex_lock(&dev->mode_config.mutex);
1241 edp_panel_vdd_off_sync(intel_dp);
1242 mutex_unlock(&dev->mode_config.mutex);
1243 }
1244
1245 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1246 {
1247 if (!is_edp(intel_dp))
1248 return;
1249
1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1251
1252 intel_dp->want_panel_vdd = false;
1253
1254 if (sync) {
1255 edp_panel_vdd_off_sync(intel_dp);
1256 } else {
1257 /*
1258 * Queue the timer to fire a long
1259 * time from now (relative to the power down delay)
1260 * to keep the panel power up across a sequence of operations
1261 */
1262 schedule_delayed_work(&intel_dp->panel_vdd_work,
1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1264 }
1265 }
1266
1267 void intel_edp_panel_on(struct intel_dp *intel_dp)
1268 {
1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 u32 pp;
1272 u32 pp_ctrl_reg;
1273
1274 if (!is_edp(intel_dp))
1275 return;
1276
1277 DRM_DEBUG_KMS("Turn eDP power on\n");
1278
1279 if (edp_have_panel_power(intel_dp)) {
1280 DRM_DEBUG_KMS("eDP power already on\n");
1281 return;
1282 }
1283
1284 wait_panel_power_cycle(intel_dp);
1285
1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1287 pp = ironlake_get_pp_control(intel_dp);
1288 if (IS_GEN5(dev)) {
1289 /* ILK workaround: disable reset around power sequence */
1290 pp &= ~PANEL_POWER_RESET;
1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
1293 }
1294
1295 pp |= POWER_TARGET_ON;
1296 if (!IS_GEN5(dev))
1297 pp |= PANEL_POWER_RESET;
1298
1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
1301
1302 wait_panel_on(intel_dp);
1303 intel_dp->last_power_on = jiffies;
1304
1305 if (IS_GEN5(dev)) {
1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
1309 }
1310 }
1311
1312 void intel_edp_panel_off(struct intel_dp *intel_dp)
1313 {
1314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 u32 pp;
1317 u32 pp_ctrl_reg;
1318
1319 if (!is_edp(intel_dp))
1320 return;
1321
1322 DRM_DEBUG_KMS("Turn eDP power off\n");
1323
1324 edp_wait_backlight_off(intel_dp);
1325
1326 pp = ironlake_get_pp_control(intel_dp);
1327 /* We need to switch off panel power _and_ force vdd, for otherwise some
1328 * panels get very unhappy and cease to work. */
1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1330
1331 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1332
1333 I915_WRITE(pp_ctrl_reg, pp);
1334 POSTING_READ(pp_ctrl_reg);
1335
1336 intel_dp->last_power_cycle = jiffies;
1337 wait_panel_off(intel_dp);
1338 }
1339
1340 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1341 {
1342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1343 struct drm_device *dev = intel_dig_port->base.base.dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 u32 pp;
1346 u32 pp_ctrl_reg;
1347
1348 if (!is_edp(intel_dp))
1349 return;
1350
1351 DRM_DEBUG_KMS("\n");
1352 /*
1353 * If we enable the backlight right away following a panel power
1354 * on, we may see slight flicker as the panel syncs with the eDP
1355 * link. So delay a bit to make sure the image is solid before
1356 * allowing it to appear.
1357 */
1358 wait_backlight_on(intel_dp);
1359 pp = ironlake_get_pp_control(intel_dp);
1360 pp |= EDP_BLC_ENABLE;
1361
1362 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1363
1364 I915_WRITE(pp_ctrl_reg, pp);
1365 POSTING_READ(pp_ctrl_reg);
1366
1367 intel_panel_enable_backlight(intel_dp->attached_connector);
1368 }
1369
1370 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1371 {
1372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 u32 pp;
1375 u32 pp_ctrl_reg;
1376
1377 if (!is_edp(intel_dp))
1378 return;
1379
1380 intel_panel_disable_backlight(intel_dp->attached_connector);
1381
1382 DRM_DEBUG_KMS("\n");
1383 pp = ironlake_get_pp_control(intel_dp);
1384 pp &= ~EDP_BLC_ENABLE;
1385
1386 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1387
1388 I915_WRITE(pp_ctrl_reg, pp);
1389 POSTING_READ(pp_ctrl_reg);
1390 intel_dp->last_backlight_off = jiffies;
1391 }
1392
1393 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1394 {
1395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1396 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1397 struct drm_device *dev = crtc->dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 u32 dpa_ctl;
1400
1401 assert_pipe_disabled(dev_priv,
1402 to_intel_crtc(crtc)->pipe);
1403
1404 DRM_DEBUG_KMS("\n");
1405 dpa_ctl = I915_READ(DP_A);
1406 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1407 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1408
1409 /* We don't adjust intel_dp->DP while tearing down the link, to
1410 * facilitate link retraining (e.g. after hotplug). Hence clear all
1411 * enable bits here to ensure that we don't enable too much. */
1412 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1413 intel_dp->DP |= DP_PLL_ENABLE;
1414 I915_WRITE(DP_A, intel_dp->DP);
1415 POSTING_READ(DP_A);
1416 udelay(200);
1417 }
1418
1419 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1420 {
1421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1422 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1423 struct drm_device *dev = crtc->dev;
1424 struct drm_i915_private *dev_priv = dev->dev_private;
1425 u32 dpa_ctl;
1426
1427 assert_pipe_disabled(dev_priv,
1428 to_intel_crtc(crtc)->pipe);
1429
1430 dpa_ctl = I915_READ(DP_A);
1431 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1432 "dp pll off, should be on\n");
1433 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1434
1435 /* We can't rely on the value tracked for the DP register in
1436 * intel_dp->DP because link_down must not change that (otherwise link
1437 * re-training will fail. */
1438 dpa_ctl &= ~DP_PLL_ENABLE;
1439 I915_WRITE(DP_A, dpa_ctl);
1440 POSTING_READ(DP_A);
1441 udelay(200);
1442 }
1443
1444 /* If the sink supports it, try to set the power state appropriately */
1445 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1446 {
1447 int ret, i;
1448
1449 /* Should have a valid DPCD by this point */
1450 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1451 return;
1452
1453 if (mode != DRM_MODE_DPMS_ON) {
1454 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1455 DP_SET_POWER_D3);
1456 if (ret != 1)
1457 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1458 } else {
1459 /*
1460 * When turning on, we need to retry for 1ms to give the sink
1461 * time to wake up.
1462 */
1463 for (i = 0; i < 3; i++) {
1464 ret = intel_dp_aux_native_write_1(intel_dp,
1465 DP_SET_POWER,
1466 DP_SET_POWER_D0);
1467 if (ret == 1)
1468 break;
1469 msleep(1);
1470 }
1471 }
1472 }
1473
1474 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1475 enum pipe *pipe)
1476 {
1477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1478 enum port port = dp_to_dig_port(intel_dp)->port;
1479 struct drm_device *dev = encoder->base.dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 tmp = I915_READ(intel_dp->output_reg);
1482
1483 if (!(tmp & DP_PORT_EN))
1484 return false;
1485
1486 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1487 *pipe = PORT_TO_PIPE_CPT(tmp);
1488 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1489 *pipe = PORT_TO_PIPE(tmp);
1490 } else {
1491 u32 trans_sel;
1492 u32 trans_dp;
1493 int i;
1494
1495 switch (intel_dp->output_reg) {
1496 case PCH_DP_B:
1497 trans_sel = TRANS_DP_PORT_SEL_B;
1498 break;
1499 case PCH_DP_C:
1500 trans_sel = TRANS_DP_PORT_SEL_C;
1501 break;
1502 case PCH_DP_D:
1503 trans_sel = TRANS_DP_PORT_SEL_D;
1504 break;
1505 default:
1506 return true;
1507 }
1508
1509 for_each_pipe(i) {
1510 trans_dp = I915_READ(TRANS_DP_CTL(i));
1511 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1512 *pipe = i;
1513 return true;
1514 }
1515 }
1516
1517 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1518 intel_dp->output_reg);
1519 }
1520
1521 return true;
1522 }
1523
1524 static void intel_dp_get_config(struct intel_encoder *encoder,
1525 struct intel_crtc_config *pipe_config)
1526 {
1527 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1528 u32 tmp, flags = 0;
1529 struct drm_device *dev = encoder->base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 enum port port = dp_to_dig_port(intel_dp)->port;
1532 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1533 int dotclock;
1534
1535 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1536 tmp = I915_READ(intel_dp->output_reg);
1537 if (tmp & DP_SYNC_HS_HIGH)
1538 flags |= DRM_MODE_FLAG_PHSYNC;
1539 else
1540 flags |= DRM_MODE_FLAG_NHSYNC;
1541
1542 if (tmp & DP_SYNC_VS_HIGH)
1543 flags |= DRM_MODE_FLAG_PVSYNC;
1544 else
1545 flags |= DRM_MODE_FLAG_NVSYNC;
1546 } else {
1547 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1548 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1549 flags |= DRM_MODE_FLAG_PHSYNC;
1550 else
1551 flags |= DRM_MODE_FLAG_NHSYNC;
1552
1553 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1554 flags |= DRM_MODE_FLAG_PVSYNC;
1555 else
1556 flags |= DRM_MODE_FLAG_NVSYNC;
1557 }
1558
1559 pipe_config->adjusted_mode.flags |= flags;
1560
1561 pipe_config->has_dp_encoder = true;
1562
1563 intel_dp_get_m_n(crtc, pipe_config);
1564
1565 if (port == PORT_A) {
1566 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1567 pipe_config->port_clock = 162000;
1568 else
1569 pipe_config->port_clock = 270000;
1570 }
1571
1572 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1573 &pipe_config->dp_m_n);
1574
1575 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1576 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1577
1578 pipe_config->adjusted_mode.crtc_clock = dotclock;
1579
1580 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1581 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1582 /*
1583 * This is a big fat ugly hack.
1584 *
1585 * Some machines in UEFI boot mode provide us a VBT that has 18
1586 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1587 * unknown we fail to light up. Yet the same BIOS boots up with
1588 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1589 * max, not what it tells us to use.
1590 *
1591 * Note: This will still be broken if the eDP panel is not lit
1592 * up by the BIOS, and thus we can't get the mode at module
1593 * load.
1594 */
1595 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1596 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1597 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1598 }
1599 }
1600
1601 static bool is_edp_psr(struct drm_device *dev)
1602 {
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605 return dev_priv->psr.sink_support;
1606 }
1607
1608 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1609 {
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611
1612 if (!HAS_PSR(dev))
1613 return false;
1614
1615 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1616 }
1617
1618 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1619 struct edp_vsc_psr *vsc_psr)
1620 {
1621 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1622 struct drm_device *dev = dig_port->base.base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1625 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1626 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1627 uint32_t *data = (uint32_t *) vsc_psr;
1628 unsigned int i;
1629
1630 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1631 the video DIP being updated before program video DIP data buffer
1632 registers for DIP being updated. */
1633 I915_WRITE(ctl_reg, 0);
1634 POSTING_READ(ctl_reg);
1635
1636 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1637 if (i < sizeof(struct edp_vsc_psr))
1638 I915_WRITE(data_reg + i, *data++);
1639 else
1640 I915_WRITE(data_reg + i, 0);
1641 }
1642
1643 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1644 POSTING_READ(ctl_reg);
1645 }
1646
1647 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1648 {
1649 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 struct edp_vsc_psr psr_vsc;
1652
1653 if (intel_dp->psr_setup_done)
1654 return;
1655
1656 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1657 memset(&psr_vsc, 0, sizeof(psr_vsc));
1658 psr_vsc.sdp_header.HB0 = 0;
1659 psr_vsc.sdp_header.HB1 = 0x7;
1660 psr_vsc.sdp_header.HB2 = 0x2;
1661 psr_vsc.sdp_header.HB3 = 0x8;
1662 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1663
1664 /* Avoid continuous PSR exit by masking memup and hpd */
1665 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1666 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1667
1668 intel_dp->psr_setup_done = true;
1669 }
1670
1671 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1672 {
1673 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 uint32_t aux_clock_divider;
1676 int precharge = 0x3;
1677 int msg_size = 5; /* Header(4) + Message(1) */
1678
1679 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1680
1681 /* Enable PSR in sink */
1682 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1683 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1684 DP_PSR_ENABLE &
1685 ~DP_PSR_MAIN_LINK_ACTIVE);
1686 else
1687 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1688 DP_PSR_ENABLE |
1689 DP_PSR_MAIN_LINK_ACTIVE);
1690
1691 /* Setup AUX registers */
1692 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1693 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1694 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1695 DP_AUX_CH_CTL_TIME_OUT_400us |
1696 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1697 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1698 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1699 }
1700
1701 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1702 {
1703 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 uint32_t max_sleep_time = 0x1f;
1706 uint32_t idle_frames = 1;
1707 uint32_t val = 0x0;
1708 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1709
1710 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1711 val |= EDP_PSR_LINK_STANDBY;
1712 val |= EDP_PSR_TP2_TP3_TIME_0us;
1713 val |= EDP_PSR_TP1_TIME_0us;
1714 val |= EDP_PSR_SKIP_AUX_EXIT;
1715 } else
1716 val |= EDP_PSR_LINK_DISABLE;
1717
1718 I915_WRITE(EDP_PSR_CTL(dev), val |
1719 IS_BROADWELL(dev) ? 0 : link_entry_time |
1720 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1721 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1722 EDP_PSR_ENABLE);
1723 }
1724
1725 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1726 {
1727 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1728 struct drm_device *dev = dig_port->base.base.dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 struct drm_crtc *crtc = dig_port->base.base.crtc;
1731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1732 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1733 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1734
1735 dev_priv->psr.source_ok = false;
1736
1737 if (!HAS_PSR(dev)) {
1738 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1739 return false;
1740 }
1741
1742 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1743 (dig_port->port != PORT_A)) {
1744 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1745 return false;
1746 }
1747
1748 if (!i915.enable_psr) {
1749 DRM_DEBUG_KMS("PSR disable by flag\n");
1750 return false;
1751 }
1752
1753 crtc = dig_port->base.base.crtc;
1754 if (crtc == NULL) {
1755 DRM_DEBUG_KMS("crtc not active for PSR\n");
1756 return false;
1757 }
1758
1759 intel_crtc = to_intel_crtc(crtc);
1760 if (!intel_crtc_active(crtc)) {
1761 DRM_DEBUG_KMS("crtc not active for PSR\n");
1762 return false;
1763 }
1764
1765 obj = to_intel_framebuffer(crtc->fb)->obj;
1766 if (obj->tiling_mode != I915_TILING_X ||
1767 obj->fence_reg == I915_FENCE_REG_NONE) {
1768 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1769 return false;
1770 }
1771
1772 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1773 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1774 return false;
1775 }
1776
1777 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1778 S3D_ENABLE) {
1779 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1780 return false;
1781 }
1782
1783 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1784 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1785 return false;
1786 }
1787
1788 dev_priv->psr.source_ok = true;
1789 return true;
1790 }
1791
1792 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1793 {
1794 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1795
1796 if (!intel_edp_psr_match_conditions(intel_dp) ||
1797 intel_edp_is_psr_enabled(dev))
1798 return;
1799
1800 /* Setup PSR once */
1801 intel_edp_psr_setup(intel_dp);
1802
1803 /* Enable PSR on the panel */
1804 intel_edp_psr_enable_sink(intel_dp);
1805
1806 /* Enable PSR on the host */
1807 intel_edp_psr_enable_source(intel_dp);
1808 }
1809
1810 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1811 {
1812 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1813
1814 if (intel_edp_psr_match_conditions(intel_dp) &&
1815 !intel_edp_is_psr_enabled(dev))
1816 intel_edp_psr_do_enable(intel_dp);
1817 }
1818
1819 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1820 {
1821 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823
1824 if (!intel_edp_is_psr_enabled(dev))
1825 return;
1826
1827 I915_WRITE(EDP_PSR_CTL(dev),
1828 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1829
1830 /* Wait till PSR is idle */
1831 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1832 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1833 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1834 }
1835
1836 void intel_edp_psr_update(struct drm_device *dev)
1837 {
1838 struct intel_encoder *encoder;
1839 struct intel_dp *intel_dp = NULL;
1840
1841 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1842 if (encoder->type == INTEL_OUTPUT_EDP) {
1843 intel_dp = enc_to_intel_dp(&encoder->base);
1844
1845 if (!is_edp_psr(dev))
1846 return;
1847
1848 if (!intel_edp_psr_match_conditions(intel_dp))
1849 intel_edp_psr_disable(intel_dp);
1850 else
1851 if (!intel_edp_is_psr_enabled(dev))
1852 intel_edp_psr_do_enable(intel_dp);
1853 }
1854 }
1855
1856 static void intel_disable_dp(struct intel_encoder *encoder)
1857 {
1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1859 enum port port = dp_to_dig_port(intel_dp)->port;
1860 struct drm_device *dev = encoder->base.dev;
1861
1862 /* Make sure the panel is off before trying to change the mode. But also
1863 * ensure that we have vdd while we switch off the panel. */
1864 intel_edp_backlight_off(intel_dp);
1865 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1866 intel_edp_panel_off(intel_dp);
1867
1868 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1869 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1870 intel_dp_link_down(intel_dp);
1871 }
1872
1873 static void intel_post_disable_dp(struct intel_encoder *encoder)
1874 {
1875 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1876 enum port port = dp_to_dig_port(intel_dp)->port;
1877 struct drm_device *dev = encoder->base.dev;
1878
1879 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1880 intel_dp_link_down(intel_dp);
1881 if (!IS_VALLEYVIEW(dev))
1882 ironlake_edp_pll_off(intel_dp);
1883 }
1884 }
1885
1886 static void intel_enable_dp(struct intel_encoder *encoder)
1887 {
1888 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1889 struct drm_device *dev = encoder->base.dev;
1890 struct drm_i915_private *dev_priv = dev->dev_private;
1891 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1892
1893 if (WARN_ON(dp_reg & DP_PORT_EN))
1894 return;
1895
1896 edp_panel_vdd_on(intel_dp);
1897 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1898 intel_dp_start_link_train(intel_dp);
1899 intel_edp_panel_on(intel_dp);
1900 edp_panel_vdd_off(intel_dp, true);
1901 intel_dp_complete_link_train(intel_dp);
1902 intel_dp_stop_link_train(intel_dp);
1903 }
1904
1905 static void g4x_enable_dp(struct intel_encoder *encoder)
1906 {
1907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1908
1909 intel_enable_dp(encoder);
1910 intel_edp_backlight_on(intel_dp);
1911 }
1912
1913 static void vlv_enable_dp(struct intel_encoder *encoder)
1914 {
1915 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1916
1917 intel_edp_backlight_on(intel_dp);
1918 }
1919
1920 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1921 {
1922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1923 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1924
1925 if (dport->port == PORT_A)
1926 ironlake_edp_pll_on(intel_dp);
1927 }
1928
1929 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1930 {
1931 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1932 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1933 struct drm_device *dev = encoder->base.dev;
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1936 enum dpio_channel port = vlv_dport_to_channel(dport);
1937 int pipe = intel_crtc->pipe;
1938 struct edp_power_seq power_seq;
1939 u32 val;
1940
1941 mutex_lock(&dev_priv->dpio_lock);
1942
1943 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1944 val = 0;
1945 if (pipe)
1946 val |= (1<<21);
1947 else
1948 val &= ~(1<<21);
1949 val |= 0x001000c4;
1950 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1951 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1952 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1953
1954 mutex_unlock(&dev_priv->dpio_lock);
1955
1956 /* init power sequencer on this pipe and port */
1957 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1958 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1959 &power_seq);
1960
1961 intel_enable_dp(encoder);
1962
1963 vlv_wait_port_ready(dev_priv, dport);
1964 }
1965
1966 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1967 {
1968 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1969 struct drm_device *dev = encoder->base.dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct intel_crtc *intel_crtc =
1972 to_intel_crtc(encoder->base.crtc);
1973 enum dpio_channel port = vlv_dport_to_channel(dport);
1974 int pipe = intel_crtc->pipe;
1975
1976 /* Program Tx lane resets to default */
1977 mutex_lock(&dev_priv->dpio_lock);
1978 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1979 DPIO_PCS_TX_LANE2_RESET |
1980 DPIO_PCS_TX_LANE1_RESET);
1981 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1982 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1983 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1984 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1985 DPIO_PCS_CLK_SOFT_RESET);
1986
1987 /* Fix up inter-pair skew failure */
1988 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1989 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1990 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1991 mutex_unlock(&dev_priv->dpio_lock);
1992 }
1993
1994 /*
1995 * Native read with retry for link status and receiver capability reads for
1996 * cases where the sink may still be asleep.
1997 */
1998 static bool
1999 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2000 uint8_t *recv, int recv_bytes)
2001 {
2002 int ret, i;
2003
2004 /*
2005 * Sinks are *supposed* to come up within 1ms from an off state,
2006 * but we're also supposed to retry 3 times per the spec.
2007 */
2008 for (i = 0; i < 3; i++) {
2009 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2010 recv_bytes);
2011 if (ret == recv_bytes)
2012 return true;
2013 msleep(1);
2014 }
2015
2016 return false;
2017 }
2018
2019 /*
2020 * Fetch AUX CH registers 0x202 - 0x207 which contain
2021 * link status information
2022 */
2023 static bool
2024 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2025 {
2026 return intel_dp_aux_native_read_retry(intel_dp,
2027 DP_LANE0_1_STATUS,
2028 link_status,
2029 DP_LINK_STATUS_SIZE);
2030 }
2031
2032 /*
2033 * These are source-specific values; current Intel hardware supports
2034 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2035 */
2036
2037 static uint8_t
2038 intel_dp_voltage_max(struct intel_dp *intel_dp)
2039 {
2040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2041 enum port port = dp_to_dig_port(intel_dp)->port;
2042
2043 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2044 return DP_TRAIN_VOLTAGE_SWING_1200;
2045 else if (IS_GEN7(dev) && port == PORT_A)
2046 return DP_TRAIN_VOLTAGE_SWING_800;
2047 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2048 return DP_TRAIN_VOLTAGE_SWING_1200;
2049 else
2050 return DP_TRAIN_VOLTAGE_SWING_800;
2051 }
2052
2053 static uint8_t
2054 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2055 {
2056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2057 enum port port = dp_to_dig_port(intel_dp)->port;
2058
2059 if (IS_BROADWELL(dev)) {
2060 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2061 case DP_TRAIN_VOLTAGE_SWING_400:
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 return DP_TRAIN_PRE_EMPHASIS_6;
2064 case DP_TRAIN_VOLTAGE_SWING_800:
2065 return DP_TRAIN_PRE_EMPHASIS_3_5;
2066 case DP_TRAIN_VOLTAGE_SWING_1200:
2067 default:
2068 return DP_TRAIN_PRE_EMPHASIS_0;
2069 }
2070 } else if (IS_HASWELL(dev)) {
2071 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2072 case DP_TRAIN_VOLTAGE_SWING_400:
2073 return DP_TRAIN_PRE_EMPHASIS_9_5;
2074 case DP_TRAIN_VOLTAGE_SWING_600:
2075 return DP_TRAIN_PRE_EMPHASIS_6;
2076 case DP_TRAIN_VOLTAGE_SWING_800:
2077 return DP_TRAIN_PRE_EMPHASIS_3_5;
2078 case DP_TRAIN_VOLTAGE_SWING_1200:
2079 default:
2080 return DP_TRAIN_PRE_EMPHASIS_0;
2081 }
2082 } else if (IS_VALLEYVIEW(dev)) {
2083 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2084 case DP_TRAIN_VOLTAGE_SWING_400:
2085 return DP_TRAIN_PRE_EMPHASIS_9_5;
2086 case DP_TRAIN_VOLTAGE_SWING_600:
2087 return DP_TRAIN_PRE_EMPHASIS_6;
2088 case DP_TRAIN_VOLTAGE_SWING_800:
2089 return DP_TRAIN_PRE_EMPHASIS_3_5;
2090 case DP_TRAIN_VOLTAGE_SWING_1200:
2091 default:
2092 return DP_TRAIN_PRE_EMPHASIS_0;
2093 }
2094 } else if (IS_GEN7(dev) && port == PORT_A) {
2095 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2096 case DP_TRAIN_VOLTAGE_SWING_400:
2097 return DP_TRAIN_PRE_EMPHASIS_6;
2098 case DP_TRAIN_VOLTAGE_SWING_600:
2099 case DP_TRAIN_VOLTAGE_SWING_800:
2100 return DP_TRAIN_PRE_EMPHASIS_3_5;
2101 default:
2102 return DP_TRAIN_PRE_EMPHASIS_0;
2103 }
2104 } else {
2105 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106 case DP_TRAIN_VOLTAGE_SWING_400:
2107 return DP_TRAIN_PRE_EMPHASIS_6;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 return DP_TRAIN_PRE_EMPHASIS_6;
2110 case DP_TRAIN_VOLTAGE_SWING_800:
2111 return DP_TRAIN_PRE_EMPHASIS_3_5;
2112 case DP_TRAIN_VOLTAGE_SWING_1200:
2113 default:
2114 return DP_TRAIN_PRE_EMPHASIS_0;
2115 }
2116 }
2117 }
2118
2119 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2120 {
2121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2124 struct intel_crtc *intel_crtc =
2125 to_intel_crtc(dport->base.base.crtc);
2126 unsigned long demph_reg_value, preemph_reg_value,
2127 uniqtranscale_reg_value;
2128 uint8_t train_set = intel_dp->train_set[0];
2129 enum dpio_channel port = vlv_dport_to_channel(dport);
2130 int pipe = intel_crtc->pipe;
2131
2132 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2133 case DP_TRAIN_PRE_EMPHASIS_0:
2134 preemph_reg_value = 0x0004000;
2135 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2136 case DP_TRAIN_VOLTAGE_SWING_400:
2137 demph_reg_value = 0x2B405555;
2138 uniqtranscale_reg_value = 0x552AB83A;
2139 break;
2140 case DP_TRAIN_VOLTAGE_SWING_600:
2141 demph_reg_value = 0x2B404040;
2142 uniqtranscale_reg_value = 0x5548B83A;
2143 break;
2144 case DP_TRAIN_VOLTAGE_SWING_800:
2145 demph_reg_value = 0x2B245555;
2146 uniqtranscale_reg_value = 0x5560B83A;
2147 break;
2148 case DP_TRAIN_VOLTAGE_SWING_1200:
2149 demph_reg_value = 0x2B405555;
2150 uniqtranscale_reg_value = 0x5598DA3A;
2151 break;
2152 default:
2153 return 0;
2154 }
2155 break;
2156 case DP_TRAIN_PRE_EMPHASIS_3_5:
2157 preemph_reg_value = 0x0002000;
2158 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2159 case DP_TRAIN_VOLTAGE_SWING_400:
2160 demph_reg_value = 0x2B404040;
2161 uniqtranscale_reg_value = 0x5552B83A;
2162 break;
2163 case DP_TRAIN_VOLTAGE_SWING_600:
2164 demph_reg_value = 0x2B404848;
2165 uniqtranscale_reg_value = 0x5580B83A;
2166 break;
2167 case DP_TRAIN_VOLTAGE_SWING_800:
2168 demph_reg_value = 0x2B404040;
2169 uniqtranscale_reg_value = 0x55ADDA3A;
2170 break;
2171 default:
2172 return 0;
2173 }
2174 break;
2175 case DP_TRAIN_PRE_EMPHASIS_6:
2176 preemph_reg_value = 0x0000000;
2177 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2178 case DP_TRAIN_VOLTAGE_SWING_400:
2179 demph_reg_value = 0x2B305555;
2180 uniqtranscale_reg_value = 0x5570B83A;
2181 break;
2182 case DP_TRAIN_VOLTAGE_SWING_600:
2183 demph_reg_value = 0x2B2B4040;
2184 uniqtranscale_reg_value = 0x55ADDA3A;
2185 break;
2186 default:
2187 return 0;
2188 }
2189 break;
2190 case DP_TRAIN_PRE_EMPHASIS_9_5:
2191 preemph_reg_value = 0x0006000;
2192 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2193 case DP_TRAIN_VOLTAGE_SWING_400:
2194 demph_reg_value = 0x1B405555;
2195 uniqtranscale_reg_value = 0x55ADDA3A;
2196 break;
2197 default:
2198 return 0;
2199 }
2200 break;
2201 default:
2202 return 0;
2203 }
2204
2205 mutex_lock(&dev_priv->dpio_lock);
2206 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2207 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2208 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2209 uniqtranscale_reg_value);
2210 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2211 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2212 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2213 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2214 mutex_unlock(&dev_priv->dpio_lock);
2215
2216 return 0;
2217 }
2218
2219 static void
2220 intel_get_adjust_train(struct intel_dp *intel_dp,
2221 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2222 {
2223 uint8_t v = 0;
2224 uint8_t p = 0;
2225 int lane;
2226 uint8_t voltage_max;
2227 uint8_t preemph_max;
2228
2229 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2230 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2231 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2232
2233 if (this_v > v)
2234 v = this_v;
2235 if (this_p > p)
2236 p = this_p;
2237 }
2238
2239 voltage_max = intel_dp_voltage_max(intel_dp);
2240 if (v >= voltage_max)
2241 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2242
2243 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2244 if (p >= preemph_max)
2245 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2246
2247 for (lane = 0; lane < 4; lane++)
2248 intel_dp->train_set[lane] = v | p;
2249 }
2250
2251 static uint32_t
2252 intel_gen4_signal_levels(uint8_t train_set)
2253 {
2254 uint32_t signal_levels = 0;
2255
2256 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2257 case DP_TRAIN_VOLTAGE_SWING_400:
2258 default:
2259 signal_levels |= DP_VOLTAGE_0_4;
2260 break;
2261 case DP_TRAIN_VOLTAGE_SWING_600:
2262 signal_levels |= DP_VOLTAGE_0_6;
2263 break;
2264 case DP_TRAIN_VOLTAGE_SWING_800:
2265 signal_levels |= DP_VOLTAGE_0_8;
2266 break;
2267 case DP_TRAIN_VOLTAGE_SWING_1200:
2268 signal_levels |= DP_VOLTAGE_1_2;
2269 break;
2270 }
2271 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2272 case DP_TRAIN_PRE_EMPHASIS_0:
2273 default:
2274 signal_levels |= DP_PRE_EMPHASIS_0;
2275 break;
2276 case DP_TRAIN_PRE_EMPHASIS_3_5:
2277 signal_levels |= DP_PRE_EMPHASIS_3_5;
2278 break;
2279 case DP_TRAIN_PRE_EMPHASIS_6:
2280 signal_levels |= DP_PRE_EMPHASIS_6;
2281 break;
2282 case DP_TRAIN_PRE_EMPHASIS_9_5:
2283 signal_levels |= DP_PRE_EMPHASIS_9_5;
2284 break;
2285 }
2286 return signal_levels;
2287 }
2288
2289 /* Gen6's DP voltage swing and pre-emphasis control */
2290 static uint32_t
2291 intel_gen6_edp_signal_levels(uint8_t train_set)
2292 {
2293 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2294 DP_TRAIN_PRE_EMPHASIS_MASK);
2295 switch (signal_levels) {
2296 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2297 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2298 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2300 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2301 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2302 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2303 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2304 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2305 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2306 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2307 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2308 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2309 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2310 default:
2311 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2312 "0x%x\n", signal_levels);
2313 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2314 }
2315 }
2316
2317 /* Gen7's DP voltage swing and pre-emphasis control */
2318 static uint32_t
2319 intel_gen7_edp_signal_levels(uint8_t train_set)
2320 {
2321 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2322 DP_TRAIN_PRE_EMPHASIS_MASK);
2323 switch (signal_levels) {
2324 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2325 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2326 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2327 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2328 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2329 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2330
2331 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2332 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2333 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2334 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2335
2336 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2337 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2338 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2339 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2340
2341 default:
2342 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2343 "0x%x\n", signal_levels);
2344 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2345 }
2346 }
2347
2348 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2349 static uint32_t
2350 intel_hsw_signal_levels(uint8_t train_set)
2351 {
2352 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2353 DP_TRAIN_PRE_EMPHASIS_MASK);
2354 switch (signal_levels) {
2355 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2356 return DDI_BUF_EMP_400MV_0DB_HSW;
2357 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2358 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2359 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2360 return DDI_BUF_EMP_400MV_6DB_HSW;
2361 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2362 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2363
2364 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2365 return DDI_BUF_EMP_600MV_0DB_HSW;
2366 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2367 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2368 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2369 return DDI_BUF_EMP_600MV_6DB_HSW;
2370
2371 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2372 return DDI_BUF_EMP_800MV_0DB_HSW;
2373 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2374 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2375 default:
2376 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2377 "0x%x\n", signal_levels);
2378 return DDI_BUF_EMP_400MV_0DB_HSW;
2379 }
2380 }
2381
2382 static uint32_t
2383 intel_bdw_signal_levels(uint8_t train_set)
2384 {
2385 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2386 DP_TRAIN_PRE_EMPHASIS_MASK);
2387 switch (signal_levels) {
2388 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2389 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2390 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2391 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2392 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2393 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2394
2395 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2396 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2397 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2398 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2399 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2400 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2401
2402 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2403 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2404 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2405 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2406
2407 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2408 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2409
2410 default:
2411 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2412 "0x%x\n", signal_levels);
2413 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2414 }
2415 }
2416
2417 /* Properly updates "DP" with the correct signal levels. */
2418 static void
2419 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2420 {
2421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2422 enum port port = intel_dig_port->port;
2423 struct drm_device *dev = intel_dig_port->base.base.dev;
2424 uint32_t signal_levels, mask;
2425 uint8_t train_set = intel_dp->train_set[0];
2426
2427 if (IS_BROADWELL(dev)) {
2428 signal_levels = intel_bdw_signal_levels(train_set);
2429 mask = DDI_BUF_EMP_MASK;
2430 } else if (IS_HASWELL(dev)) {
2431 signal_levels = intel_hsw_signal_levels(train_set);
2432 mask = DDI_BUF_EMP_MASK;
2433 } else if (IS_VALLEYVIEW(dev)) {
2434 signal_levels = intel_vlv_signal_levels(intel_dp);
2435 mask = 0;
2436 } else if (IS_GEN7(dev) && port == PORT_A) {
2437 signal_levels = intel_gen7_edp_signal_levels(train_set);
2438 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2439 } else if (IS_GEN6(dev) && port == PORT_A) {
2440 signal_levels = intel_gen6_edp_signal_levels(train_set);
2441 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2442 } else {
2443 signal_levels = intel_gen4_signal_levels(train_set);
2444 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2445 }
2446
2447 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2448
2449 *DP = (*DP & ~mask) | signal_levels;
2450 }
2451
2452 static bool
2453 intel_dp_set_link_train(struct intel_dp *intel_dp,
2454 uint32_t *DP,
2455 uint8_t dp_train_pat)
2456 {
2457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2458 struct drm_device *dev = intel_dig_port->base.base.dev;
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 enum port port = intel_dig_port->port;
2461 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2462 int ret, len;
2463
2464 if (HAS_DDI(dev)) {
2465 uint32_t temp = I915_READ(DP_TP_CTL(port));
2466
2467 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2468 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2469 else
2470 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2471
2472 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2473 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2474 case DP_TRAINING_PATTERN_DISABLE:
2475 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2476
2477 break;
2478 case DP_TRAINING_PATTERN_1:
2479 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2480 break;
2481 case DP_TRAINING_PATTERN_2:
2482 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2483 break;
2484 case DP_TRAINING_PATTERN_3:
2485 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2486 break;
2487 }
2488 I915_WRITE(DP_TP_CTL(port), temp);
2489
2490 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2491 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2492
2493 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2494 case DP_TRAINING_PATTERN_DISABLE:
2495 *DP |= DP_LINK_TRAIN_OFF_CPT;
2496 break;
2497 case DP_TRAINING_PATTERN_1:
2498 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2499 break;
2500 case DP_TRAINING_PATTERN_2:
2501 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2502 break;
2503 case DP_TRAINING_PATTERN_3:
2504 DRM_ERROR("DP training pattern 3 not supported\n");
2505 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2506 break;
2507 }
2508
2509 } else {
2510 *DP &= ~DP_LINK_TRAIN_MASK;
2511
2512 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2513 case DP_TRAINING_PATTERN_DISABLE:
2514 *DP |= DP_LINK_TRAIN_OFF;
2515 break;
2516 case DP_TRAINING_PATTERN_1:
2517 *DP |= DP_LINK_TRAIN_PAT_1;
2518 break;
2519 case DP_TRAINING_PATTERN_2:
2520 *DP |= DP_LINK_TRAIN_PAT_2;
2521 break;
2522 case DP_TRAINING_PATTERN_3:
2523 DRM_ERROR("DP training pattern 3 not supported\n");
2524 *DP |= DP_LINK_TRAIN_PAT_2;
2525 break;
2526 }
2527 }
2528
2529 I915_WRITE(intel_dp->output_reg, *DP);
2530 POSTING_READ(intel_dp->output_reg);
2531
2532 buf[0] = dp_train_pat;
2533 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2534 DP_TRAINING_PATTERN_DISABLE) {
2535 /* don't write DP_TRAINING_LANEx_SET on disable */
2536 len = 1;
2537 } else {
2538 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2539 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2540 len = intel_dp->lane_count + 1;
2541 }
2542
2543 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2544 buf, len);
2545
2546 return ret == len;
2547 }
2548
2549 static bool
2550 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2551 uint8_t dp_train_pat)
2552 {
2553 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2554 intel_dp_set_signal_levels(intel_dp, DP);
2555 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2556 }
2557
2558 static bool
2559 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2560 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2561 {
2562 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2563 struct drm_device *dev = intel_dig_port->base.base.dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 int ret;
2566
2567 intel_get_adjust_train(intel_dp, link_status);
2568 intel_dp_set_signal_levels(intel_dp, DP);
2569
2570 I915_WRITE(intel_dp->output_reg, *DP);
2571 POSTING_READ(intel_dp->output_reg);
2572
2573 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2574 intel_dp->train_set,
2575 intel_dp->lane_count);
2576
2577 return ret == intel_dp->lane_count;
2578 }
2579
2580 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2581 {
2582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2583 struct drm_device *dev = intel_dig_port->base.base.dev;
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2585 enum port port = intel_dig_port->port;
2586 uint32_t val;
2587
2588 if (!HAS_DDI(dev))
2589 return;
2590
2591 val = I915_READ(DP_TP_CTL(port));
2592 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2593 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2594 I915_WRITE(DP_TP_CTL(port), val);
2595
2596 /*
2597 * On PORT_A we can have only eDP in SST mode. There the only reason
2598 * we need to set idle transmission mode is to work around a HW issue
2599 * where we enable the pipe while not in idle link-training mode.
2600 * In this case there is requirement to wait for a minimum number of
2601 * idle patterns to be sent.
2602 */
2603 if (port == PORT_A)
2604 return;
2605
2606 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2607 1))
2608 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2609 }
2610
2611 /* Enable corresponding port and start training pattern 1 */
2612 void
2613 intel_dp_start_link_train(struct intel_dp *intel_dp)
2614 {
2615 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2616 struct drm_device *dev = encoder->dev;
2617 int i;
2618 uint8_t voltage;
2619 int voltage_tries, loop_tries;
2620 uint32_t DP = intel_dp->DP;
2621 uint8_t link_config[2];
2622
2623 if (HAS_DDI(dev))
2624 intel_ddi_prepare_link_retrain(encoder);
2625
2626 /* Write the link configuration data */
2627 link_config[0] = intel_dp->link_bw;
2628 link_config[1] = intel_dp->lane_count;
2629 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2630 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2631 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2632
2633 link_config[0] = 0;
2634 link_config[1] = DP_SET_ANSI_8B10B;
2635 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2636
2637 DP |= DP_PORT_EN;
2638
2639 /* clock recovery */
2640 if (!intel_dp_reset_link_train(intel_dp, &DP,
2641 DP_TRAINING_PATTERN_1 |
2642 DP_LINK_SCRAMBLING_DISABLE)) {
2643 DRM_ERROR("failed to enable link training\n");
2644 return;
2645 }
2646
2647 voltage = 0xff;
2648 voltage_tries = 0;
2649 loop_tries = 0;
2650 for (;;) {
2651 uint8_t link_status[DP_LINK_STATUS_SIZE];
2652
2653 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2654 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2655 DRM_ERROR("failed to get link status\n");
2656 break;
2657 }
2658
2659 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2660 DRM_DEBUG_KMS("clock recovery OK\n");
2661 break;
2662 }
2663
2664 /* Check to see if we've tried the max voltage */
2665 for (i = 0; i < intel_dp->lane_count; i++)
2666 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2667 break;
2668 if (i == intel_dp->lane_count) {
2669 ++loop_tries;
2670 if (loop_tries == 5) {
2671 DRM_ERROR("too many full retries, give up\n");
2672 break;
2673 }
2674 intel_dp_reset_link_train(intel_dp, &DP,
2675 DP_TRAINING_PATTERN_1 |
2676 DP_LINK_SCRAMBLING_DISABLE);
2677 voltage_tries = 0;
2678 continue;
2679 }
2680
2681 /* Check to see if we've tried the same voltage 5 times */
2682 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2683 ++voltage_tries;
2684 if (voltage_tries == 5) {
2685 DRM_ERROR("too many voltage retries, give up\n");
2686 break;
2687 }
2688 } else
2689 voltage_tries = 0;
2690 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2691
2692 /* Update training set as requested by target */
2693 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2694 DRM_ERROR("failed to update link training\n");
2695 break;
2696 }
2697 }
2698
2699 intel_dp->DP = DP;
2700 }
2701
2702 void
2703 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2704 {
2705 bool channel_eq = false;
2706 int tries, cr_tries;
2707 uint32_t DP = intel_dp->DP;
2708 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2709
2710 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2711 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2712 training_pattern = DP_TRAINING_PATTERN_3;
2713
2714 /* channel equalization */
2715 if (!intel_dp_set_link_train(intel_dp, &DP,
2716 training_pattern |
2717 DP_LINK_SCRAMBLING_DISABLE)) {
2718 DRM_ERROR("failed to start channel equalization\n");
2719 return;
2720 }
2721
2722 tries = 0;
2723 cr_tries = 0;
2724 channel_eq = false;
2725 for (;;) {
2726 uint8_t link_status[DP_LINK_STATUS_SIZE];
2727
2728 if (cr_tries > 5) {
2729 DRM_ERROR("failed to train DP, aborting\n");
2730 break;
2731 }
2732
2733 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2734 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2735 DRM_ERROR("failed to get link status\n");
2736 break;
2737 }
2738
2739 /* Make sure clock is still ok */
2740 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2741 intel_dp_start_link_train(intel_dp);
2742 intel_dp_set_link_train(intel_dp, &DP,
2743 training_pattern |
2744 DP_LINK_SCRAMBLING_DISABLE);
2745 cr_tries++;
2746 continue;
2747 }
2748
2749 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2750 channel_eq = true;
2751 break;
2752 }
2753
2754 /* Try 5 times, then try clock recovery if that fails */
2755 if (tries > 5) {
2756 intel_dp_link_down(intel_dp);
2757 intel_dp_start_link_train(intel_dp);
2758 intel_dp_set_link_train(intel_dp, &DP,
2759 training_pattern |
2760 DP_LINK_SCRAMBLING_DISABLE);
2761 tries = 0;
2762 cr_tries++;
2763 continue;
2764 }
2765
2766 /* Update training set as requested by target */
2767 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2768 DRM_ERROR("failed to update link training\n");
2769 break;
2770 }
2771 ++tries;
2772 }
2773
2774 intel_dp_set_idle_link_train(intel_dp);
2775
2776 intel_dp->DP = DP;
2777
2778 if (channel_eq)
2779 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2780
2781 }
2782
2783 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2784 {
2785 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2786 DP_TRAINING_PATTERN_DISABLE);
2787 }
2788
2789 static void
2790 intel_dp_link_down(struct intel_dp *intel_dp)
2791 {
2792 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2793 enum port port = intel_dig_port->port;
2794 struct drm_device *dev = intel_dig_port->base.base.dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_crtc *intel_crtc =
2797 to_intel_crtc(intel_dig_port->base.base.crtc);
2798 uint32_t DP = intel_dp->DP;
2799
2800 /*
2801 * DDI code has a strict mode set sequence and we should try to respect
2802 * it, otherwise we might hang the machine in many different ways. So we
2803 * really should be disabling the port only on a complete crtc_disable
2804 * sequence. This function is just called under two conditions on DDI
2805 * code:
2806 * - Link train failed while doing crtc_enable, and on this case we
2807 * really should respect the mode set sequence and wait for a
2808 * crtc_disable.
2809 * - Someone turned the monitor off and intel_dp_check_link_status
2810 * called us. We don't need to disable the whole port on this case, so
2811 * when someone turns the monitor on again,
2812 * intel_ddi_prepare_link_retrain will take care of redoing the link
2813 * train.
2814 */
2815 if (HAS_DDI(dev))
2816 return;
2817
2818 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2819 return;
2820
2821 DRM_DEBUG_KMS("\n");
2822
2823 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2824 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2825 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2826 } else {
2827 DP &= ~DP_LINK_TRAIN_MASK;
2828 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2829 }
2830 POSTING_READ(intel_dp->output_reg);
2831
2832 /* We don't really know why we're doing this */
2833 intel_wait_for_vblank(dev, intel_crtc->pipe);
2834
2835 if (HAS_PCH_IBX(dev) &&
2836 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2837 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2838
2839 /* Hardware workaround: leaving our transcoder select
2840 * set to transcoder B while it's off will prevent the
2841 * corresponding HDMI output on transcoder A.
2842 *
2843 * Combine this with another hardware workaround:
2844 * transcoder select bit can only be cleared while the
2845 * port is enabled.
2846 */
2847 DP &= ~DP_PIPEB_SELECT;
2848 I915_WRITE(intel_dp->output_reg, DP);
2849
2850 /* Changes to enable or select take place the vblank
2851 * after being written.
2852 */
2853 if (WARN_ON(crtc == NULL)) {
2854 /* We should never try to disable a port without a crtc
2855 * attached. For paranoia keep the code around for a
2856 * bit. */
2857 POSTING_READ(intel_dp->output_reg);
2858 msleep(50);
2859 } else
2860 intel_wait_for_vblank(dev, intel_crtc->pipe);
2861 }
2862
2863 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2864 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2865 POSTING_READ(intel_dp->output_reg);
2866 msleep(intel_dp->panel_power_down_delay);
2867 }
2868
2869 static bool
2870 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2871 {
2872 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2873 struct drm_device *dev = dig_port->base.base.dev;
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875
2876 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2877
2878 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2879 sizeof(intel_dp->dpcd)) == 0)
2880 return false; /* aux transfer failed */
2881
2882 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2883 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2884 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2885
2886 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2887 return false; /* DPCD not present */
2888
2889 /* Check if the panel supports PSR */
2890 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2891 if (is_edp(intel_dp)) {
2892 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2893 intel_dp->psr_dpcd,
2894 sizeof(intel_dp->psr_dpcd));
2895 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2896 dev_priv->psr.sink_support = true;
2897 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2898 }
2899 }
2900
2901 /* Training Pattern 3 support */
2902 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2903 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2904 intel_dp->use_tps3 = true;
2905 DRM_DEBUG_KMS("Displayport TPS3 supported");
2906 } else
2907 intel_dp->use_tps3 = false;
2908
2909 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2910 DP_DWN_STRM_PORT_PRESENT))
2911 return true; /* native DP sink */
2912
2913 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2914 return true; /* no per-port downstream info */
2915
2916 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2917 intel_dp->downstream_ports,
2918 DP_MAX_DOWNSTREAM_PORTS) == 0)
2919 return false; /* downstream port status fetch failed */
2920
2921 return true;
2922 }
2923
2924 static void
2925 intel_dp_probe_oui(struct intel_dp *intel_dp)
2926 {
2927 u8 buf[3];
2928
2929 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2930 return;
2931
2932 edp_panel_vdd_on(intel_dp);
2933
2934 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2935 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2936 buf[0], buf[1], buf[2]);
2937
2938 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2939 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2940 buf[0], buf[1], buf[2]);
2941
2942 edp_panel_vdd_off(intel_dp, false);
2943 }
2944
2945 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2946 {
2947 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2948 struct drm_device *dev = intel_dig_port->base.base.dev;
2949 struct intel_crtc *intel_crtc =
2950 to_intel_crtc(intel_dig_port->base.base.crtc);
2951 u8 buf[1];
2952
2953 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2954 return -EAGAIN;
2955
2956 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2957 return -ENOTTY;
2958
2959 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2960 DP_TEST_SINK_START))
2961 return -EAGAIN;
2962
2963 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2964 intel_wait_for_vblank(dev, intel_crtc->pipe);
2965 intel_wait_for_vblank(dev, intel_crtc->pipe);
2966
2967 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2968 return -EAGAIN;
2969
2970 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2971 return 0;
2972 }
2973
2974 static bool
2975 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2976 {
2977 int ret;
2978
2979 ret = intel_dp_aux_native_read_retry(intel_dp,
2980 DP_DEVICE_SERVICE_IRQ_VECTOR,
2981 sink_irq_vector, 1);
2982 if (!ret)
2983 return false;
2984
2985 return true;
2986 }
2987
2988 static void
2989 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2990 {
2991 /* NAK by default */
2992 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2993 }
2994
2995 /*
2996 * According to DP spec
2997 * 5.1.2:
2998 * 1. Read DPCD
2999 * 2. Configure link according to Receiver Capabilities
3000 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3001 * 4. Check link status on receipt of hot-plug interrupt
3002 */
3003
3004 void
3005 intel_dp_check_link_status(struct intel_dp *intel_dp)
3006 {
3007 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3008 u8 sink_irq_vector;
3009 u8 link_status[DP_LINK_STATUS_SIZE];
3010
3011 if (!intel_encoder->connectors_active)
3012 return;
3013
3014 if (WARN_ON(!intel_encoder->base.crtc))
3015 return;
3016
3017 /* Try to read receiver status if the link appears to be up */
3018 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3019 return;
3020 }
3021
3022 /* Now read the DPCD to see if it's actually running */
3023 if (!intel_dp_get_dpcd(intel_dp)) {
3024 return;
3025 }
3026
3027 /* Try to read the source of the interrupt */
3028 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3029 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3030 /* Clear interrupt source */
3031 intel_dp_aux_native_write_1(intel_dp,
3032 DP_DEVICE_SERVICE_IRQ_VECTOR,
3033 sink_irq_vector);
3034
3035 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3036 intel_dp_handle_test_request(intel_dp);
3037 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3038 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3039 }
3040
3041 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3042 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3043 drm_get_encoder_name(&intel_encoder->base));
3044 intel_dp_start_link_train(intel_dp);
3045 intel_dp_complete_link_train(intel_dp);
3046 intel_dp_stop_link_train(intel_dp);
3047 }
3048 }
3049
3050 /* XXX this is probably wrong for multiple downstream ports */
3051 static enum drm_connector_status
3052 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3053 {
3054 uint8_t *dpcd = intel_dp->dpcd;
3055 uint8_t type;
3056
3057 if (!intel_dp_get_dpcd(intel_dp))
3058 return connector_status_disconnected;
3059
3060 /* if there's no downstream port, we're done */
3061 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3062 return connector_status_connected;
3063
3064 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3065 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3066 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3067 uint8_t reg;
3068 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
3069 &reg, 1))
3070 return connector_status_unknown;
3071 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3072 : connector_status_disconnected;
3073 }
3074
3075 /* If no HPD, poke DDC gently */
3076 if (drm_probe_ddc(&intel_dp->adapter))
3077 return connector_status_connected;
3078
3079 /* Well we tried, say unknown for unreliable port types */
3080 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3081 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3082 if (type == DP_DS_PORT_TYPE_VGA ||
3083 type == DP_DS_PORT_TYPE_NON_EDID)
3084 return connector_status_unknown;
3085 } else {
3086 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3087 DP_DWN_STRM_PORT_TYPE_MASK;
3088 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3089 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3090 return connector_status_unknown;
3091 }
3092
3093 /* Anything else is out of spec, warn and ignore */
3094 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3095 return connector_status_disconnected;
3096 }
3097
3098 static enum drm_connector_status
3099 ironlake_dp_detect(struct intel_dp *intel_dp)
3100 {
3101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3104 enum drm_connector_status status;
3105
3106 /* Can't disconnect eDP, but you can close the lid... */
3107 if (is_edp(intel_dp)) {
3108 status = intel_panel_detect(dev);
3109 if (status == connector_status_unknown)
3110 status = connector_status_connected;
3111 return status;
3112 }
3113
3114 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3115 return connector_status_disconnected;
3116
3117 return intel_dp_detect_dpcd(intel_dp);
3118 }
3119
3120 static enum drm_connector_status
3121 g4x_dp_detect(struct intel_dp *intel_dp)
3122 {
3123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3126 uint32_t bit;
3127
3128 /* Can't disconnect eDP, but you can close the lid... */
3129 if (is_edp(intel_dp)) {
3130 enum drm_connector_status status;
3131
3132 status = intel_panel_detect(dev);
3133 if (status == connector_status_unknown)
3134 status = connector_status_connected;
3135 return status;
3136 }
3137
3138 if (IS_VALLEYVIEW(dev)) {
3139 switch (intel_dig_port->port) {
3140 case PORT_B:
3141 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3142 break;
3143 case PORT_C:
3144 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3145 break;
3146 case PORT_D:
3147 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3148 break;
3149 default:
3150 return connector_status_unknown;
3151 }
3152 } else {
3153 switch (intel_dig_port->port) {
3154 case PORT_B:
3155 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3156 break;
3157 case PORT_C:
3158 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3159 break;
3160 case PORT_D:
3161 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3162 break;
3163 default:
3164 return connector_status_unknown;
3165 }
3166 }
3167
3168 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3169 return connector_status_disconnected;
3170
3171 return intel_dp_detect_dpcd(intel_dp);
3172 }
3173
3174 static struct edid *
3175 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3176 {
3177 struct intel_connector *intel_connector = to_intel_connector(connector);
3178
3179 /* use cached edid if we have one */
3180 if (intel_connector->edid) {
3181 /* invalid edid */
3182 if (IS_ERR(intel_connector->edid))
3183 return NULL;
3184
3185 return drm_edid_duplicate(intel_connector->edid);
3186 }
3187
3188 return drm_get_edid(connector, adapter);
3189 }
3190
3191 static int
3192 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3193 {
3194 struct intel_connector *intel_connector = to_intel_connector(connector);
3195
3196 /* use cached edid if we have one */
3197 if (intel_connector->edid) {
3198 /* invalid edid */
3199 if (IS_ERR(intel_connector->edid))
3200 return 0;
3201
3202 return intel_connector_update_modes(connector,
3203 intel_connector->edid);
3204 }
3205
3206 return intel_ddc_get_modes(connector, adapter);
3207 }
3208
3209 static enum drm_connector_status
3210 intel_dp_detect(struct drm_connector *connector, bool force)
3211 {
3212 struct intel_dp *intel_dp = intel_attached_dp(connector);
3213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3214 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3215 struct drm_device *dev = connector->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 enum drm_connector_status status;
3218 struct edid *edid = NULL;
3219
3220 intel_runtime_pm_get(dev_priv);
3221
3222 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3223 connector->base.id, drm_get_connector_name(connector));
3224
3225 intel_dp->has_audio = false;
3226
3227 if (HAS_PCH_SPLIT(dev))
3228 status = ironlake_dp_detect(intel_dp);
3229 else
3230 status = g4x_dp_detect(intel_dp);
3231
3232 if (status != connector_status_connected)
3233 goto out;
3234
3235 intel_dp_probe_oui(intel_dp);
3236
3237 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3238 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3239 } else {
3240 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3241 if (edid) {
3242 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3243 kfree(edid);
3244 }
3245 }
3246
3247 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3248 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3249 status = connector_status_connected;
3250
3251 out:
3252 intel_runtime_pm_put(dev_priv);
3253 return status;
3254 }
3255
3256 static int intel_dp_get_modes(struct drm_connector *connector)
3257 {
3258 struct intel_dp *intel_dp = intel_attached_dp(connector);
3259 struct intel_connector *intel_connector = to_intel_connector(connector);
3260 struct drm_device *dev = connector->dev;
3261 int ret;
3262
3263 /* We should parse the EDID data and find out if it has an audio sink
3264 */
3265
3266 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3267 if (ret)
3268 return ret;
3269
3270 /* if eDP has no EDID, fall back to fixed mode */
3271 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3272 struct drm_display_mode *mode;
3273 mode = drm_mode_duplicate(dev,
3274 intel_connector->panel.fixed_mode);
3275 if (mode) {
3276 drm_mode_probed_add(connector, mode);
3277 return 1;
3278 }
3279 }
3280 return 0;
3281 }
3282
3283 static bool
3284 intel_dp_detect_audio(struct drm_connector *connector)
3285 {
3286 struct intel_dp *intel_dp = intel_attached_dp(connector);
3287 struct edid *edid;
3288 bool has_audio = false;
3289
3290 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3291 if (edid) {
3292 has_audio = drm_detect_monitor_audio(edid);
3293 kfree(edid);
3294 }
3295
3296 return has_audio;
3297 }
3298
3299 static int
3300 intel_dp_set_property(struct drm_connector *connector,
3301 struct drm_property *property,
3302 uint64_t val)
3303 {
3304 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3305 struct intel_connector *intel_connector = to_intel_connector(connector);
3306 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3307 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3308 int ret;
3309
3310 ret = drm_object_property_set_value(&connector->base, property, val);
3311 if (ret)
3312 return ret;
3313
3314 if (property == dev_priv->force_audio_property) {
3315 int i = val;
3316 bool has_audio;
3317
3318 if (i == intel_dp->force_audio)
3319 return 0;
3320
3321 intel_dp->force_audio = i;
3322
3323 if (i == HDMI_AUDIO_AUTO)
3324 has_audio = intel_dp_detect_audio(connector);
3325 else
3326 has_audio = (i == HDMI_AUDIO_ON);
3327
3328 if (has_audio == intel_dp->has_audio)
3329 return 0;
3330
3331 intel_dp->has_audio = has_audio;
3332 goto done;
3333 }
3334
3335 if (property == dev_priv->broadcast_rgb_property) {
3336 bool old_auto = intel_dp->color_range_auto;
3337 uint32_t old_range = intel_dp->color_range;
3338
3339 switch (val) {
3340 case INTEL_BROADCAST_RGB_AUTO:
3341 intel_dp->color_range_auto = true;
3342 break;
3343 case INTEL_BROADCAST_RGB_FULL:
3344 intel_dp->color_range_auto = false;
3345 intel_dp->color_range = 0;
3346 break;
3347 case INTEL_BROADCAST_RGB_LIMITED:
3348 intel_dp->color_range_auto = false;
3349 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3350 break;
3351 default:
3352 return -EINVAL;
3353 }
3354
3355 if (old_auto == intel_dp->color_range_auto &&
3356 old_range == intel_dp->color_range)
3357 return 0;
3358
3359 goto done;
3360 }
3361
3362 if (is_edp(intel_dp) &&
3363 property == connector->dev->mode_config.scaling_mode_property) {
3364 if (val == DRM_MODE_SCALE_NONE) {
3365 DRM_DEBUG_KMS("no scaling not supported\n");
3366 return -EINVAL;
3367 }
3368
3369 if (intel_connector->panel.fitting_mode == val) {
3370 /* the eDP scaling property is not changed */
3371 return 0;
3372 }
3373 intel_connector->panel.fitting_mode = val;
3374
3375 goto done;
3376 }
3377
3378 return -EINVAL;
3379
3380 done:
3381 if (intel_encoder->base.crtc)
3382 intel_crtc_restore_mode(intel_encoder->base.crtc);
3383
3384 return 0;
3385 }
3386
3387 static void
3388 intel_dp_connector_destroy(struct drm_connector *connector)
3389 {
3390 struct intel_connector *intel_connector = to_intel_connector(connector);
3391
3392 if (!IS_ERR_OR_NULL(intel_connector->edid))
3393 kfree(intel_connector->edid);
3394
3395 /* Can't call is_edp() since the encoder may have been destroyed
3396 * already. */
3397 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3398 intel_panel_fini(&intel_connector->panel);
3399
3400 drm_connector_cleanup(connector);
3401 kfree(connector);
3402 }
3403
3404 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3405 {
3406 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3407 struct intel_dp *intel_dp = &intel_dig_port->dp;
3408 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3409
3410 i2c_del_adapter(&intel_dp->adapter);
3411 drm_encoder_cleanup(encoder);
3412 if (is_edp(intel_dp)) {
3413 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3414 mutex_lock(&dev->mode_config.mutex);
3415 edp_panel_vdd_off_sync(intel_dp);
3416 mutex_unlock(&dev->mode_config.mutex);
3417 }
3418 kfree(intel_dig_port);
3419 }
3420
3421 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3422 .dpms = intel_connector_dpms,
3423 .detect = intel_dp_detect,
3424 .fill_modes = drm_helper_probe_single_connector_modes,
3425 .set_property = intel_dp_set_property,
3426 .destroy = intel_dp_connector_destroy,
3427 };
3428
3429 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3430 .get_modes = intel_dp_get_modes,
3431 .mode_valid = intel_dp_mode_valid,
3432 .best_encoder = intel_best_encoder,
3433 };
3434
3435 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3436 .destroy = intel_dp_encoder_destroy,
3437 };
3438
3439 static void
3440 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3441 {
3442 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3443
3444 intel_dp_check_link_status(intel_dp);
3445 }
3446
3447 /* Return which DP Port should be selected for Transcoder DP control */
3448 int
3449 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3450 {
3451 struct drm_device *dev = crtc->dev;
3452 struct intel_encoder *intel_encoder;
3453 struct intel_dp *intel_dp;
3454
3455 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3456 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3457
3458 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3459 intel_encoder->type == INTEL_OUTPUT_EDP)
3460 return intel_dp->output_reg;
3461 }
3462
3463 return -1;
3464 }
3465
3466 /* check the VBT to see whether the eDP is on DP-D port */
3467 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3468 {
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 union child_device_config *p_child;
3471 int i;
3472 static const short port_mapping[] = {
3473 [PORT_B] = PORT_IDPB,
3474 [PORT_C] = PORT_IDPC,
3475 [PORT_D] = PORT_IDPD,
3476 };
3477
3478 if (port == PORT_A)
3479 return true;
3480
3481 if (!dev_priv->vbt.child_dev_num)
3482 return false;
3483
3484 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3485 p_child = dev_priv->vbt.child_dev + i;
3486
3487 if (p_child->common.dvo_port == port_mapping[port] &&
3488 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3489 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3490 return true;
3491 }
3492 return false;
3493 }
3494
3495 static void
3496 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3497 {
3498 struct intel_connector *intel_connector = to_intel_connector(connector);
3499
3500 intel_attach_force_audio_property(connector);
3501 intel_attach_broadcast_rgb_property(connector);
3502 intel_dp->color_range_auto = true;
3503
3504 if (is_edp(intel_dp)) {
3505 drm_mode_create_scaling_mode_property(connector->dev);
3506 drm_object_attach_property(
3507 &connector->base,
3508 connector->dev->mode_config.scaling_mode_property,
3509 DRM_MODE_SCALE_ASPECT);
3510 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3511 }
3512 }
3513
3514 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3515 {
3516 intel_dp->last_power_cycle = jiffies;
3517 intel_dp->last_power_on = jiffies;
3518 intel_dp->last_backlight_off = jiffies;
3519 }
3520
3521 static void
3522 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3523 struct intel_dp *intel_dp,
3524 struct edp_power_seq *out)
3525 {
3526 struct drm_i915_private *dev_priv = dev->dev_private;
3527 struct edp_power_seq cur, vbt, spec, final;
3528 u32 pp_on, pp_off, pp_div, pp;
3529 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3530
3531 if (HAS_PCH_SPLIT(dev)) {
3532 pp_ctrl_reg = PCH_PP_CONTROL;
3533 pp_on_reg = PCH_PP_ON_DELAYS;
3534 pp_off_reg = PCH_PP_OFF_DELAYS;
3535 pp_div_reg = PCH_PP_DIVISOR;
3536 } else {
3537 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3538
3539 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3540 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3541 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3542 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3543 }
3544
3545 /* Workaround: Need to write PP_CONTROL with the unlock key as
3546 * the very first thing. */
3547 pp = ironlake_get_pp_control(intel_dp);
3548 I915_WRITE(pp_ctrl_reg, pp);
3549
3550 pp_on = I915_READ(pp_on_reg);
3551 pp_off = I915_READ(pp_off_reg);
3552 pp_div = I915_READ(pp_div_reg);
3553
3554 /* Pull timing values out of registers */
3555 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3556 PANEL_POWER_UP_DELAY_SHIFT;
3557
3558 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3559 PANEL_LIGHT_ON_DELAY_SHIFT;
3560
3561 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3562 PANEL_LIGHT_OFF_DELAY_SHIFT;
3563
3564 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3565 PANEL_POWER_DOWN_DELAY_SHIFT;
3566
3567 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3568 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3569
3570 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3571 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3572
3573 vbt = dev_priv->vbt.edp_pps;
3574
3575 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3576 * our hw here, which are all in 100usec. */
3577 spec.t1_t3 = 210 * 10;
3578 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3579 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3580 spec.t10 = 500 * 10;
3581 /* This one is special and actually in units of 100ms, but zero
3582 * based in the hw (so we need to add 100 ms). But the sw vbt
3583 * table multiplies it with 1000 to make it in units of 100usec,
3584 * too. */
3585 spec.t11_t12 = (510 + 100) * 10;
3586
3587 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3588 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3589
3590 /* Use the max of the register settings and vbt. If both are
3591 * unset, fall back to the spec limits. */
3592 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3593 spec.field : \
3594 max(cur.field, vbt.field))
3595 assign_final(t1_t3);
3596 assign_final(t8);
3597 assign_final(t9);
3598 assign_final(t10);
3599 assign_final(t11_t12);
3600 #undef assign_final
3601
3602 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3603 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3604 intel_dp->backlight_on_delay = get_delay(t8);
3605 intel_dp->backlight_off_delay = get_delay(t9);
3606 intel_dp->panel_power_down_delay = get_delay(t10);
3607 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3608 #undef get_delay
3609
3610 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3611 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3612 intel_dp->panel_power_cycle_delay);
3613
3614 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3615 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3616
3617 if (out)
3618 *out = final;
3619 }
3620
3621 static void
3622 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3623 struct intel_dp *intel_dp,
3624 struct edp_power_seq *seq)
3625 {
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 u32 pp_on, pp_off, pp_div, port_sel = 0;
3628 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3629 int pp_on_reg, pp_off_reg, pp_div_reg;
3630
3631 if (HAS_PCH_SPLIT(dev)) {
3632 pp_on_reg = PCH_PP_ON_DELAYS;
3633 pp_off_reg = PCH_PP_OFF_DELAYS;
3634 pp_div_reg = PCH_PP_DIVISOR;
3635 } else {
3636 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3637
3638 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3639 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3640 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3641 }
3642
3643 /*
3644 * And finally store the new values in the power sequencer. The
3645 * backlight delays are set to 1 because we do manual waits on them. For
3646 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3647 * we'll end up waiting for the backlight off delay twice: once when we
3648 * do the manual sleep, and once when we disable the panel and wait for
3649 * the PP_STATUS bit to become zero.
3650 */
3651 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3652 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3653 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3654 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3655 /* Compute the divisor for the pp clock, simply match the Bspec
3656 * formula. */
3657 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3658 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3659 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3660
3661 /* Haswell doesn't have any port selection bits for the panel
3662 * power sequencer any more. */
3663 if (IS_VALLEYVIEW(dev)) {
3664 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3665 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3666 else
3667 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3668 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3669 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3670 port_sel = PANEL_PORT_SELECT_DPA;
3671 else
3672 port_sel = PANEL_PORT_SELECT_DPD;
3673 }
3674
3675 pp_on |= port_sel;
3676
3677 I915_WRITE(pp_on_reg, pp_on);
3678 I915_WRITE(pp_off_reg, pp_off);
3679 I915_WRITE(pp_div_reg, pp_div);
3680
3681 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3682 I915_READ(pp_on_reg),
3683 I915_READ(pp_off_reg),
3684 I915_READ(pp_div_reg));
3685 }
3686
3687 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3688 struct intel_connector *intel_connector,
3689 struct edp_power_seq *power_seq)
3690 {
3691 struct drm_connector *connector = &intel_connector->base;
3692 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3693 struct drm_device *dev = intel_dig_port->base.base.dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct drm_display_mode *fixed_mode = NULL;
3696 bool has_dpcd;
3697 struct drm_display_mode *scan;
3698 struct edid *edid;
3699
3700 if (!is_edp(intel_dp))
3701 return true;
3702
3703 /* Cache DPCD and EDID for edp. */
3704 edp_panel_vdd_on(intel_dp);
3705 has_dpcd = intel_dp_get_dpcd(intel_dp);
3706 edp_panel_vdd_off(intel_dp, false);
3707
3708 if (has_dpcd) {
3709 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3710 dev_priv->no_aux_handshake =
3711 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3712 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3713 } else {
3714 /* if this fails, presume the device is a ghost */
3715 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3716 return false;
3717 }
3718
3719 /* We now know it's not a ghost, init power sequence regs. */
3720 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3721
3722 edid = drm_get_edid(connector, &intel_dp->adapter);
3723 if (edid) {
3724 if (drm_add_edid_modes(connector, edid)) {
3725 drm_mode_connector_update_edid_property(connector,
3726 edid);
3727 drm_edid_to_eld(connector, edid);
3728 } else {
3729 kfree(edid);
3730 edid = ERR_PTR(-EINVAL);
3731 }
3732 } else {
3733 edid = ERR_PTR(-ENOENT);
3734 }
3735 intel_connector->edid = edid;
3736
3737 /* prefer fixed mode from EDID if available */
3738 list_for_each_entry(scan, &connector->probed_modes, head) {
3739 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3740 fixed_mode = drm_mode_duplicate(dev, scan);
3741 break;
3742 }
3743 }
3744
3745 /* fallback to VBT if available for eDP */
3746 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3747 fixed_mode = drm_mode_duplicate(dev,
3748 dev_priv->vbt.lfp_lvds_vbt_mode);
3749 if (fixed_mode)
3750 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3751 }
3752
3753 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3754 intel_panel_setup_backlight(connector);
3755
3756 return true;
3757 }
3758
3759 bool
3760 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3761 struct intel_connector *intel_connector)
3762 {
3763 struct drm_connector *connector = &intel_connector->base;
3764 struct intel_dp *intel_dp = &intel_dig_port->dp;
3765 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3766 struct drm_device *dev = intel_encoder->base.dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 enum port port = intel_dig_port->port;
3769 struct edp_power_seq power_seq = { 0 };
3770 const char *name = NULL;
3771 int type, error;
3772
3773 /* intel_dp vfuncs */
3774 if (IS_VALLEYVIEW(dev))
3775 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3776 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3777 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3778 else if (HAS_PCH_SPLIT(dev))
3779 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3780 else
3781 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3782
3783 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3784
3785 /* Preserve the current hw state. */
3786 intel_dp->DP = I915_READ(intel_dp->output_reg);
3787 intel_dp->attached_connector = intel_connector;
3788
3789 if (intel_dp_is_edp(dev, port))
3790 type = DRM_MODE_CONNECTOR_eDP;
3791 else
3792 type = DRM_MODE_CONNECTOR_DisplayPort;
3793
3794 /*
3795 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3796 * for DP the encoder type can be set by the caller to
3797 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3798 */
3799 if (type == DRM_MODE_CONNECTOR_eDP)
3800 intel_encoder->type = INTEL_OUTPUT_EDP;
3801
3802 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3803 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3804 port_name(port));
3805
3806 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3807 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3808
3809 connector->interlace_allowed = true;
3810 connector->doublescan_allowed = 0;
3811
3812 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3813 edp_panel_vdd_work);
3814
3815 intel_connector_attach_encoder(intel_connector, intel_encoder);
3816 drm_sysfs_connector_add(connector);
3817
3818 if (HAS_DDI(dev))
3819 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3820 else
3821 intel_connector->get_hw_state = intel_connector_get_hw_state;
3822 intel_connector->unregister = intel_dp_connector_unregister;
3823
3824 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3825 if (HAS_DDI(dev)) {
3826 switch (intel_dig_port->port) {
3827 case PORT_A:
3828 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3829 break;
3830 case PORT_B:
3831 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3832 break;
3833 case PORT_C:
3834 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3835 break;
3836 case PORT_D:
3837 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3838 break;
3839 default:
3840 BUG();
3841 }
3842 }
3843
3844 /* Set up the DDC bus. */
3845 switch (port) {
3846 case PORT_A:
3847 intel_encoder->hpd_pin = HPD_PORT_A;
3848 name = "DPDDC-A";
3849 break;
3850 case PORT_B:
3851 intel_encoder->hpd_pin = HPD_PORT_B;
3852 name = "DPDDC-B";
3853 break;
3854 case PORT_C:
3855 intel_encoder->hpd_pin = HPD_PORT_C;
3856 name = "DPDDC-C";
3857 break;
3858 case PORT_D:
3859 intel_encoder->hpd_pin = HPD_PORT_D;
3860 name = "DPDDC-D";
3861 break;
3862 default:
3863 BUG();
3864 }
3865
3866 if (is_edp(intel_dp)) {
3867 intel_dp_init_panel_power_timestamps(intel_dp);
3868 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3869 }
3870
3871 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3872 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3873 error, port_name(port));
3874
3875 intel_dp->psr_setup_done = false;
3876
3877 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3878 i2c_del_adapter(&intel_dp->adapter);
3879 if (is_edp(intel_dp)) {
3880 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3881 mutex_lock(&dev->mode_config.mutex);
3882 edp_panel_vdd_off_sync(intel_dp);
3883 mutex_unlock(&dev->mode_config.mutex);
3884 }
3885 drm_sysfs_connector_remove(connector);
3886 drm_connector_cleanup(connector);
3887 return false;
3888 }
3889
3890 intel_dp_add_properties(intel_dp, connector);
3891
3892 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3893 * 0xd. Failure to do so will result in spurious interrupts being
3894 * generated on the port when a cable is not attached.
3895 */
3896 if (IS_G4X(dev) && !IS_GM45(dev)) {
3897 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3898 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3899 }
3900
3901 return true;
3902 }
3903
3904 void
3905 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3906 {
3907 struct intel_digital_port *intel_dig_port;
3908 struct intel_encoder *intel_encoder;
3909 struct drm_encoder *encoder;
3910 struct intel_connector *intel_connector;
3911
3912 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3913 if (!intel_dig_port)
3914 return;
3915
3916 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3917 if (!intel_connector) {
3918 kfree(intel_dig_port);
3919 return;
3920 }
3921
3922 intel_encoder = &intel_dig_port->base;
3923 encoder = &intel_encoder->base;
3924
3925 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3926 DRM_MODE_ENCODER_TMDS);
3927
3928 intel_encoder->compute_config = intel_dp_compute_config;
3929 intel_encoder->mode_set = intel_dp_mode_set;
3930 intel_encoder->disable = intel_disable_dp;
3931 intel_encoder->post_disable = intel_post_disable_dp;
3932 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3933 intel_encoder->get_config = intel_dp_get_config;
3934 if (IS_VALLEYVIEW(dev)) {
3935 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3936 intel_encoder->pre_enable = vlv_pre_enable_dp;
3937 intel_encoder->enable = vlv_enable_dp;
3938 } else {
3939 intel_encoder->pre_enable = g4x_pre_enable_dp;
3940 intel_encoder->enable = g4x_enable_dp;
3941 }
3942
3943 intel_dig_port->port = port;
3944 intel_dig_port->dp.output_reg = output_reg;
3945
3946 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3947 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3948 intel_encoder->cloneable = false;
3949 intel_encoder->hot_plug = intel_dp_hot_plug;
3950
3951 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3952 drm_encoder_cleanup(encoder);
3953 kfree(intel_dig_port);
3954 kfree(intel_connector);
3955 }
3956 }
Linux kernel - Deliverables
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