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drm/i915: stop using is_pch_edp() in is_cpu_edp()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 /**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63 static bool is_pch_edp(struct intel_dp *intel_dp)
64 {
65 return intel_dp->is_pch_edp;
66 }
67
68 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
69 {
70 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
71
72 return intel_dig_port->base.base.dev;
73 }
74
75 /**
76 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
77 * @intel_dp: DP struct
78 *
79 * Returns true if the given DP struct corresponds to a CPU eDP port.
80 */
81 static bool is_cpu_edp(struct intel_dp *intel_dp)
82 {
83 struct drm_device *dev = intel_dp_to_dev(intel_dp);
84 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 enum port port = intel_dig_port->port;
86
87 return is_edp(intel_dp) &&
88 (port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev)));
89 }
90
91 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
92 {
93 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
94 }
95
96 /**
97 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
98 * @encoder: DRM encoder
99 *
100 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
101 * by intel_display.c.
102 */
103 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
104 {
105 struct intel_dp *intel_dp;
106
107 if (!encoder)
108 return false;
109
110 intel_dp = enc_to_intel_dp(encoder);
111
112 return is_pch_edp(intel_dp);
113 }
114
115 static void intel_dp_link_down(struct intel_dp *intel_dp);
116
117 static int
118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
119 {
120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
121
122 switch (max_link_bw) {
123 case DP_LINK_BW_1_62:
124 case DP_LINK_BW_2_7:
125 break;
126 default:
127 max_link_bw = DP_LINK_BW_1_62;
128 break;
129 }
130 return max_link_bw;
131 }
132
133 /*
134 * The units on the numbers in the next two are... bizarre. Examples will
135 * make it clearer; this one parallels an example in the eDP spec.
136 *
137 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
138 *
139 * 270000 * 1 * 8 / 10 == 216000
140 *
141 * The actual data capacity of that configuration is 2.16Gbit/s, so the
142 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
143 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
144 * 119000. At 18bpp that's 2142000 kilobits per second.
145 *
146 * Thus the strange-looking division by 10 in intel_dp_link_required, to
147 * get the result in decakilobits instead of kilobits.
148 */
149
150 static int
151 intel_dp_link_required(int pixel_clock, int bpp)
152 {
153 return (pixel_clock * bpp + 9) / 10;
154 }
155
156 static int
157 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
158 {
159 return (max_link_clock * max_lanes * 8) / 10;
160 }
161
162 static int
163 intel_dp_mode_valid(struct drm_connector *connector,
164 struct drm_display_mode *mode)
165 {
166 struct intel_dp *intel_dp = intel_attached_dp(connector);
167 struct intel_connector *intel_connector = to_intel_connector(connector);
168 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
169 int target_clock = mode->clock;
170 int max_rate, mode_rate, max_lanes, max_link_clock;
171
172 if (is_edp(intel_dp) && fixed_mode) {
173 if (mode->hdisplay > fixed_mode->hdisplay)
174 return MODE_PANEL;
175
176 if (mode->vdisplay > fixed_mode->vdisplay)
177 return MODE_PANEL;
178
179 target_clock = fixed_mode->clock;
180 }
181
182 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
183 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
184
185 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
186 mode_rate = intel_dp_link_required(target_clock, 18);
187
188 if (mode_rate > max_rate)
189 return MODE_CLOCK_HIGH;
190
191 if (mode->clock < 10000)
192 return MODE_CLOCK_LOW;
193
194 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
195 return MODE_H_ILLEGAL;
196
197 return MODE_OK;
198 }
199
200 static uint32_t
201 pack_aux(uint8_t *src, int src_bytes)
202 {
203 int i;
204 uint32_t v = 0;
205
206 if (src_bytes > 4)
207 src_bytes = 4;
208 for (i = 0; i < src_bytes; i++)
209 v |= ((uint32_t) src[i]) << ((3-i) * 8);
210 return v;
211 }
212
213 static void
214 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
215 {
216 int i;
217 if (dst_bytes > 4)
218 dst_bytes = 4;
219 for (i = 0; i < dst_bytes; i++)
220 dst[i] = src >> ((3-i) * 8);
221 }
222
223 /* hrawclock is 1/4 the FSB frequency */
224 static int
225 intel_hrawclk(struct drm_device *dev)
226 {
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 uint32_t clkcfg;
229
230 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
231 if (IS_VALLEYVIEW(dev))
232 return 200;
233
234 clkcfg = I915_READ(CLKCFG);
235 switch (clkcfg & CLKCFG_FSB_MASK) {
236 case CLKCFG_FSB_400:
237 return 100;
238 case CLKCFG_FSB_533:
239 return 133;
240 case CLKCFG_FSB_667:
241 return 166;
242 case CLKCFG_FSB_800:
243 return 200;
244 case CLKCFG_FSB_1067:
245 return 266;
246 case CLKCFG_FSB_1333:
247 return 333;
248 /* these two are just a guess; one of them might be right */
249 case CLKCFG_FSB_1600:
250 case CLKCFG_FSB_1600_ALT:
251 return 400;
252 default:
253 return 133;
254 }
255 }
256
257 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
258 {
259 struct drm_device *dev = intel_dp_to_dev(intel_dp);
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 u32 pp_stat_reg;
262
263 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
264 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
265 }
266
267 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
268 {
269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 u32 pp_ctrl_reg;
272
273 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
274 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
275 }
276
277 static void
278 intel_dp_check_edp(struct intel_dp *intel_dp)
279 {
280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 u32 pp_stat_reg, pp_ctrl_reg;
283
284 if (!is_edp(intel_dp))
285 return;
286
287 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
288 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
289
290 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
291 WARN(1, "eDP powered off while attempting aux channel communication.\n");
292 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
293 I915_READ(pp_stat_reg),
294 I915_READ(pp_ctrl_reg));
295 }
296 }
297
298 static uint32_t
299 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
300 {
301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
302 struct drm_device *dev = intel_dig_port->base.base.dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
305 uint32_t status;
306 bool done;
307
308 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
309 if (has_aux_irq)
310 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
311 msecs_to_jiffies(10));
312 else
313 done = wait_for_atomic(C, 10) == 0;
314 if (!done)
315 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
316 has_aux_irq);
317 #undef C
318
319 return status;
320 }
321
322 static int
323 intel_dp_aux_ch(struct intel_dp *intel_dp,
324 uint8_t *send, int send_bytes,
325 uint8_t *recv, int recv_size)
326 {
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
331 uint32_t ch_data = ch_ctl + 4;
332 int i, ret, recv_bytes;
333 uint32_t status;
334 uint32_t aux_clock_divider;
335 int try, precharge;
336 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
337
338 /* dp aux is extremely sensitive to irq latency, hence request the
339 * lowest possible wakeup latency and so prevent the cpu from going into
340 * deep sleep states.
341 */
342 pm_qos_update_request(&dev_priv->pm_qos, 0);
343
344 intel_dp_check_edp(intel_dp);
345 /* The clock divider is based off the hrawclk,
346 * and would like to run at 2MHz. So, take the
347 * hrawclk value and divide by 2 and use that
348 *
349 * Note that PCH attached eDP panels should use a 125MHz input
350 * clock divider.
351 */
352 if (is_cpu_edp(intel_dp)) {
353 if (HAS_DDI(dev))
354 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
355 else if (IS_VALLEYVIEW(dev))
356 aux_clock_divider = 100;
357 else if (IS_GEN6(dev) || IS_GEN7(dev))
358 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
359 else
360 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
361 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
362 /* Workaround for non-ULT HSW */
363 aux_clock_divider = 74;
364 } else if (HAS_PCH_SPLIT(dev)) {
365 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
366 } else {
367 aux_clock_divider = intel_hrawclk(dev) / 2;
368 }
369
370 if (IS_GEN6(dev))
371 precharge = 3;
372 else
373 precharge = 5;
374
375 /* Try to wait for any previous AUX channel activity */
376 for (try = 0; try < 3; try++) {
377 status = I915_READ_NOTRACE(ch_ctl);
378 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
379 break;
380 msleep(1);
381 }
382
383 if (try == 3) {
384 WARN(1, "dp_aux_ch not started status 0x%08x\n",
385 I915_READ(ch_ctl));
386 ret = -EBUSY;
387 goto out;
388 }
389
390 /* Must try at least 3 times according to DP spec */
391 for (try = 0; try < 5; try++) {
392 /* Load the send data into the aux channel data registers */
393 for (i = 0; i < send_bytes; i += 4)
394 I915_WRITE(ch_data + i,
395 pack_aux(send + i, send_bytes - i));
396
397 /* Send the command and wait for it to complete */
398 I915_WRITE(ch_ctl,
399 DP_AUX_CH_CTL_SEND_BUSY |
400 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
401 DP_AUX_CH_CTL_TIME_OUT_400us |
402 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
403 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
404 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
405 DP_AUX_CH_CTL_DONE |
406 DP_AUX_CH_CTL_TIME_OUT_ERROR |
407 DP_AUX_CH_CTL_RECEIVE_ERROR);
408
409 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
410
411 /* Clear done status and any errors */
412 I915_WRITE(ch_ctl,
413 status |
414 DP_AUX_CH_CTL_DONE |
415 DP_AUX_CH_CTL_TIME_OUT_ERROR |
416 DP_AUX_CH_CTL_RECEIVE_ERROR);
417
418 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR))
420 continue;
421 if (status & DP_AUX_CH_CTL_DONE)
422 break;
423 }
424
425 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
426 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
427 ret = -EBUSY;
428 goto out;
429 }
430
431 /* Check for timeout or receive error.
432 * Timeouts occur when the sink is not connected
433 */
434 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
435 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
436 ret = -EIO;
437 goto out;
438 }
439
440 /* Timeouts occur when the device isn't connected, so they're
441 * "normal" -- don't fill the kernel log with these */
442 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
443 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
444 ret = -ETIMEDOUT;
445 goto out;
446 }
447
448 /* Unload any bytes sent back from the other side */
449 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
450 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
451 if (recv_bytes > recv_size)
452 recv_bytes = recv_size;
453
454 for (i = 0; i < recv_bytes; i += 4)
455 unpack_aux(I915_READ(ch_data + i),
456 recv + i, recv_bytes - i);
457
458 ret = recv_bytes;
459 out:
460 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
461
462 return ret;
463 }
464
465 /* Write data to the aux channel in native mode */
466 static int
467 intel_dp_aux_native_write(struct intel_dp *intel_dp,
468 uint16_t address, uint8_t *send, int send_bytes)
469 {
470 int ret;
471 uint8_t msg[20];
472 int msg_bytes;
473 uint8_t ack;
474
475 intel_dp_check_edp(intel_dp);
476 if (send_bytes > 16)
477 return -1;
478 msg[0] = AUX_NATIVE_WRITE << 4;
479 msg[1] = address >> 8;
480 msg[2] = address & 0xff;
481 msg[3] = send_bytes - 1;
482 memcpy(&msg[4], send, send_bytes);
483 msg_bytes = send_bytes + 4;
484 for (;;) {
485 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
486 if (ret < 0)
487 return ret;
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
489 break;
490 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
491 udelay(100);
492 else
493 return -EIO;
494 }
495 return send_bytes;
496 }
497
498 /* Write a single byte to the aux channel in native mode */
499 static int
500 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
501 uint16_t address, uint8_t byte)
502 {
503 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
504 }
505
506 /* read bytes from a native aux channel */
507 static int
508 intel_dp_aux_native_read(struct intel_dp *intel_dp,
509 uint16_t address, uint8_t *recv, int recv_bytes)
510 {
511 uint8_t msg[4];
512 int msg_bytes;
513 uint8_t reply[20];
514 int reply_bytes;
515 uint8_t ack;
516 int ret;
517
518 intel_dp_check_edp(intel_dp);
519 msg[0] = AUX_NATIVE_READ << 4;
520 msg[1] = address >> 8;
521 msg[2] = address & 0xff;
522 msg[3] = recv_bytes - 1;
523
524 msg_bytes = 4;
525 reply_bytes = recv_bytes + 1;
526
527 for (;;) {
528 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
529 reply, reply_bytes);
530 if (ret == 0)
531 return -EPROTO;
532 if (ret < 0)
533 return ret;
534 ack = reply[0];
535 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
536 memcpy(recv, reply + 1, ret - 1);
537 return ret - 1;
538 }
539 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
540 udelay(100);
541 else
542 return -EIO;
543 }
544 }
545
546 static int
547 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
548 uint8_t write_byte, uint8_t *read_byte)
549 {
550 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
551 struct intel_dp *intel_dp = container_of(adapter,
552 struct intel_dp,
553 adapter);
554 uint16_t address = algo_data->address;
555 uint8_t msg[5];
556 uint8_t reply[2];
557 unsigned retry;
558 int msg_bytes;
559 int reply_bytes;
560 int ret;
561
562 intel_dp_check_edp(intel_dp);
563 /* Set up the command byte */
564 if (mode & MODE_I2C_READ)
565 msg[0] = AUX_I2C_READ << 4;
566 else
567 msg[0] = AUX_I2C_WRITE << 4;
568
569 if (!(mode & MODE_I2C_STOP))
570 msg[0] |= AUX_I2C_MOT << 4;
571
572 msg[1] = address >> 8;
573 msg[2] = address;
574
575 switch (mode) {
576 case MODE_I2C_WRITE:
577 msg[3] = 0;
578 msg[4] = write_byte;
579 msg_bytes = 5;
580 reply_bytes = 1;
581 break;
582 case MODE_I2C_READ:
583 msg[3] = 0;
584 msg_bytes = 4;
585 reply_bytes = 2;
586 break;
587 default:
588 msg_bytes = 3;
589 reply_bytes = 1;
590 break;
591 }
592
593 for (retry = 0; retry < 5; retry++) {
594 ret = intel_dp_aux_ch(intel_dp,
595 msg, msg_bytes,
596 reply, reply_bytes);
597 if (ret < 0) {
598 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
599 return ret;
600 }
601
602 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
603 case AUX_NATIVE_REPLY_ACK:
604 /* I2C-over-AUX Reply field is only valid
605 * when paired with AUX ACK.
606 */
607 break;
608 case AUX_NATIVE_REPLY_NACK:
609 DRM_DEBUG_KMS("aux_ch native nack\n");
610 return -EREMOTEIO;
611 case AUX_NATIVE_REPLY_DEFER:
612 udelay(100);
613 continue;
614 default:
615 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
616 reply[0]);
617 return -EREMOTEIO;
618 }
619
620 switch (reply[0] & AUX_I2C_REPLY_MASK) {
621 case AUX_I2C_REPLY_ACK:
622 if (mode == MODE_I2C_READ) {
623 *read_byte = reply[1];
624 }
625 return reply_bytes - 1;
626 case AUX_I2C_REPLY_NACK:
627 DRM_DEBUG_KMS("aux_i2c nack\n");
628 return -EREMOTEIO;
629 case AUX_I2C_REPLY_DEFER:
630 DRM_DEBUG_KMS("aux_i2c defer\n");
631 udelay(100);
632 break;
633 default:
634 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
635 return -EREMOTEIO;
636 }
637 }
638
639 DRM_ERROR("too many retries, giving up\n");
640 return -EREMOTEIO;
641 }
642
643 static int
644 intel_dp_i2c_init(struct intel_dp *intel_dp,
645 struct intel_connector *intel_connector, const char *name)
646 {
647 int ret;
648
649 DRM_DEBUG_KMS("i2c_init %s\n", name);
650 intel_dp->algo.running = false;
651 intel_dp->algo.address = 0;
652 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
653
654 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
655 intel_dp->adapter.owner = THIS_MODULE;
656 intel_dp->adapter.class = I2C_CLASS_DDC;
657 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
658 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
659 intel_dp->adapter.algo_data = &intel_dp->algo;
660 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
661
662 ironlake_edp_panel_vdd_on(intel_dp);
663 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
664 ironlake_edp_panel_vdd_off(intel_dp, false);
665 return ret;
666 }
667
668 static void
669 intel_dp_set_clock(struct intel_encoder *encoder,
670 struct intel_crtc_config *pipe_config, int link_bw)
671 {
672 struct drm_device *dev = encoder->base.dev;
673
674 if (IS_G4X(dev)) {
675 if (link_bw == DP_LINK_BW_1_62) {
676 pipe_config->dpll.p1 = 2;
677 pipe_config->dpll.p2 = 10;
678 pipe_config->dpll.n = 2;
679 pipe_config->dpll.m1 = 23;
680 pipe_config->dpll.m2 = 8;
681 } else {
682 pipe_config->dpll.p1 = 1;
683 pipe_config->dpll.p2 = 10;
684 pipe_config->dpll.n = 1;
685 pipe_config->dpll.m1 = 14;
686 pipe_config->dpll.m2 = 2;
687 }
688 pipe_config->clock_set = true;
689 } else if (IS_HASWELL(dev)) {
690 /* Haswell has special-purpose DP DDI clocks. */
691 } else if (HAS_PCH_SPLIT(dev)) {
692 if (link_bw == DP_LINK_BW_1_62) {
693 pipe_config->dpll.n = 1;
694 pipe_config->dpll.p1 = 2;
695 pipe_config->dpll.p2 = 10;
696 pipe_config->dpll.m1 = 12;
697 pipe_config->dpll.m2 = 9;
698 } else {
699 pipe_config->dpll.n = 2;
700 pipe_config->dpll.p1 = 1;
701 pipe_config->dpll.p2 = 10;
702 pipe_config->dpll.m1 = 14;
703 pipe_config->dpll.m2 = 8;
704 }
705 pipe_config->clock_set = true;
706 } else if (IS_VALLEYVIEW(dev)) {
707 /* FIXME: Need to figure out optimized DP clocks for vlv. */
708 }
709 }
710
711 bool
712 intel_dp_compute_config(struct intel_encoder *encoder,
713 struct intel_crtc_config *pipe_config)
714 {
715 struct drm_device *dev = encoder->base.dev;
716 struct drm_i915_private *dev_priv = dev->dev_private;
717 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
718 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
719 struct intel_crtc *intel_crtc = encoder->new_crtc;
720 struct intel_connector *intel_connector = intel_dp->attached_connector;
721 int lane_count, clock;
722 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
723 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
724 int bpp, mode_rate;
725 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
726 int target_clock, link_avail, link_clock;
727
728 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
729 pipe_config->has_pch_encoder = true;
730
731 pipe_config->has_dp_encoder = true;
732
733 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
734 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
735 adjusted_mode);
736 if (!HAS_PCH_SPLIT(dev))
737 intel_gmch_panel_fitting(intel_crtc, pipe_config,
738 intel_connector->panel.fitting_mode);
739 else
740 intel_pch_panel_fitting(intel_crtc, pipe_config,
741 intel_connector->panel.fitting_mode);
742 }
743 /* We need to take the panel's fixed mode into account. */
744 target_clock = adjusted_mode->clock;
745
746 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
747 return false;
748
749 DRM_DEBUG_KMS("DP link computation with max lane count %i "
750 "max bw %02x pixel clock %iKHz\n",
751 max_lane_count, bws[max_clock], adjusted_mode->clock);
752
753 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
754 * bpc in between. */
755 bpp = pipe_config->pipe_bpp;
756
757 /*
758 * eDP panels are really fickle, try to enfore the bpp the firmware
759 * recomments. This means we'll up-dither 16bpp framebuffers on
760 * high-depth panels.
761 */
762 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
763 DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
764 dev_priv->edp.bpp);
765 bpp = dev_priv->edp.bpp;
766 }
767
768 for (; bpp >= 6*3; bpp -= 2*3) {
769 mode_rate = intel_dp_link_required(target_clock, bpp);
770
771 for (clock = 0; clock <= max_clock; clock++) {
772 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
773 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
774 link_avail = intel_dp_max_data_rate(link_clock,
775 lane_count);
776
777 if (mode_rate <= link_avail) {
778 goto found;
779 }
780 }
781 }
782 }
783
784 return false;
785
786 found:
787 if (intel_dp->color_range_auto) {
788 /*
789 * See:
790 * CEA-861-E - 5.1 Default Encoding Parameters
791 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
792 */
793 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
794 intel_dp->color_range = DP_COLOR_RANGE_16_235;
795 else
796 intel_dp->color_range = 0;
797 }
798
799 if (intel_dp->color_range)
800 pipe_config->limited_color_range = true;
801
802 intel_dp->link_bw = bws[clock];
803 intel_dp->lane_count = lane_count;
804 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
805 pipe_config->pixel_target_clock = target_clock;
806
807 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
808 intel_dp->link_bw, intel_dp->lane_count,
809 adjusted_mode->clock, bpp);
810 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
811 mode_rate, link_avail);
812
813 intel_link_compute_m_n(bpp, lane_count,
814 target_clock, adjusted_mode->clock,
815 &pipe_config->dp_m_n);
816
817 pipe_config->pipe_bpp = bpp;
818
819 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
820
821 return true;
822 }
823
824 void intel_dp_init_link_config(struct intel_dp *intel_dp)
825 {
826 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
827 intel_dp->link_configuration[0] = intel_dp->link_bw;
828 intel_dp->link_configuration[1] = intel_dp->lane_count;
829 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
830 /*
831 * Check for DPCD version > 1.1 and enhanced framing support
832 */
833 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
834 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
835 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
836 }
837 }
838
839 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
840 {
841 struct drm_device *dev = crtc->dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 u32 dpa_ctl;
844
845 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
846 dpa_ctl = I915_READ(DP_A);
847 dpa_ctl &= ~DP_PLL_FREQ_MASK;
848
849 if (clock < 200000) {
850 /* For a long time we've carried around a ILK-DevA w/a for the
851 * 160MHz clock. If we're really unlucky, it's still required.
852 */
853 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
854 dpa_ctl |= DP_PLL_FREQ_160MHZ;
855 } else {
856 dpa_ctl |= DP_PLL_FREQ_270MHZ;
857 }
858
859 I915_WRITE(DP_A, dpa_ctl);
860
861 POSTING_READ(DP_A);
862 udelay(500);
863 }
864
865 static void
866 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
867 struct drm_display_mode *adjusted_mode)
868 {
869 struct drm_device *dev = encoder->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
872 struct drm_crtc *crtc = encoder->crtc;
873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
874
875 /*
876 * There are four kinds of DP registers:
877 *
878 * IBX PCH
879 * SNB CPU
880 * IVB CPU
881 * CPT PCH
882 *
883 * IBX PCH and CPU are the same for almost everything,
884 * except that the CPU DP PLL is configured in this
885 * register
886 *
887 * CPT PCH is quite different, having many bits moved
888 * to the TRANS_DP_CTL register instead. That
889 * configuration happens (oddly) in ironlake_pch_enable
890 */
891
892 /* Preserve the BIOS-computed detected bit. This is
893 * supposed to be read-only.
894 */
895 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
896
897 /* Handle DP bits in common between all three register formats */
898 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
899 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
900
901 if (intel_dp->has_audio) {
902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
903 pipe_name(intel_crtc->pipe));
904 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
905 intel_write_eld(encoder, adjusted_mode);
906 }
907
908 intel_dp_init_link_config(intel_dp);
909
910 /* Split out the IBX/CPU vs CPT settings */
911
912 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
914 intel_dp->DP |= DP_SYNC_HS_HIGH;
915 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
916 intel_dp->DP |= DP_SYNC_VS_HIGH;
917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
918
919 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
920 intel_dp->DP |= DP_ENHANCED_FRAMING;
921
922 intel_dp->DP |= intel_crtc->pipe << 29;
923
924 /* don't miss out required setting for eDP */
925 if (adjusted_mode->clock < 200000)
926 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
927 else
928 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
929 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
930 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
931 intel_dp->DP |= intel_dp->color_range;
932
933 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
934 intel_dp->DP |= DP_SYNC_HS_HIGH;
935 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
936 intel_dp->DP |= DP_SYNC_VS_HIGH;
937 intel_dp->DP |= DP_LINK_TRAIN_OFF;
938
939 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
940 intel_dp->DP |= DP_ENHANCED_FRAMING;
941
942 if (intel_crtc->pipe == 1)
943 intel_dp->DP |= DP_PIPEB_SELECT;
944
945 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
946 /* don't miss out required setting for eDP */
947 if (adjusted_mode->clock < 200000)
948 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
949 else
950 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
951 }
952 } else {
953 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
954 }
955
956 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
957 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
958 }
959
960 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
961 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
962
963 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
964 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965
966 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
967 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
968
969 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
970 u32 mask,
971 u32 value)
972 {
973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 u32 pp_stat_reg, pp_ctrl_reg;
976
977 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
978 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
979
980 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
981 mask, value,
982 I915_READ(pp_stat_reg),
983 I915_READ(pp_ctrl_reg));
984
985 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
986 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
987 I915_READ(pp_stat_reg),
988 I915_READ(pp_ctrl_reg));
989 }
990 }
991
992 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
993 {
994 DRM_DEBUG_KMS("Wait for panel power on\n");
995 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
996 }
997
998 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
999 {
1000 DRM_DEBUG_KMS("Wait for panel power off time\n");
1001 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1002 }
1003
1004 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1005 {
1006 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1007 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1008 }
1009
1010
1011 /* Read the current pp_control value, unlocking the register if it
1012 * is locked
1013 */
1014
1015 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1016 {
1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 control;
1020 u32 pp_ctrl_reg;
1021
1022 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1023 control = I915_READ(pp_ctrl_reg);
1024
1025 control &= ~PANEL_UNLOCK_MASK;
1026 control |= PANEL_UNLOCK_REGS;
1027 return control;
1028 }
1029
1030 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1031 {
1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 pp;
1035 u32 pp_stat_reg, pp_ctrl_reg;
1036
1037 if (!is_edp(intel_dp))
1038 return;
1039 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1040
1041 WARN(intel_dp->want_panel_vdd,
1042 "eDP VDD already requested on\n");
1043
1044 intel_dp->want_panel_vdd = true;
1045
1046 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1047 DRM_DEBUG_KMS("eDP VDD already on\n");
1048 return;
1049 }
1050
1051 if (!ironlake_edp_have_panel_power(intel_dp))
1052 ironlake_wait_panel_power_cycle(intel_dp);
1053
1054 pp = ironlake_get_pp_control(intel_dp);
1055 pp |= EDP_FORCE_VDD;
1056
1057 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1058 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1059
1060 I915_WRITE(pp_ctrl_reg, pp);
1061 POSTING_READ(pp_ctrl_reg);
1062 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1063 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1064 /*
1065 * If the panel wasn't on, delay before accessing aux channel
1066 */
1067 if (!ironlake_edp_have_panel_power(intel_dp)) {
1068 DRM_DEBUG_KMS("eDP was not running\n");
1069 msleep(intel_dp->panel_power_up_delay);
1070 }
1071 }
1072
1073 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1074 {
1075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 u32 pp;
1078 u32 pp_stat_reg, pp_ctrl_reg;
1079
1080 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1081
1082 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1083 pp = ironlake_get_pp_control(intel_dp);
1084 pp &= ~EDP_FORCE_VDD;
1085
1086 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1087 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1088
1089 I915_WRITE(pp_ctrl_reg, pp);
1090 POSTING_READ(pp_ctrl_reg);
1091
1092 /* Make sure sequencer is idle before allowing subsequent activity */
1093 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1094 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1095 msleep(intel_dp->panel_power_down_delay);
1096 }
1097 }
1098
1099 static void ironlake_panel_vdd_work(struct work_struct *__work)
1100 {
1101 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1102 struct intel_dp, panel_vdd_work);
1103 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1104
1105 mutex_lock(&dev->mode_config.mutex);
1106 ironlake_panel_vdd_off_sync(intel_dp);
1107 mutex_unlock(&dev->mode_config.mutex);
1108 }
1109
1110 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1111 {
1112 if (!is_edp(intel_dp))
1113 return;
1114
1115 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1116 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1117
1118 intel_dp->want_panel_vdd = false;
1119
1120 if (sync) {
1121 ironlake_panel_vdd_off_sync(intel_dp);
1122 } else {
1123 /*
1124 * Queue the timer to fire a long
1125 * time from now (relative to the power down delay)
1126 * to keep the panel power up across a sequence of operations
1127 */
1128 schedule_delayed_work(&intel_dp->panel_vdd_work,
1129 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1130 }
1131 }
1132
1133 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1134 {
1135 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 u32 pp;
1138 u32 pp_ctrl_reg;
1139
1140 if (!is_edp(intel_dp))
1141 return;
1142
1143 DRM_DEBUG_KMS("Turn eDP power on\n");
1144
1145 if (ironlake_edp_have_panel_power(intel_dp)) {
1146 DRM_DEBUG_KMS("eDP power already on\n");
1147 return;
1148 }
1149
1150 ironlake_wait_panel_power_cycle(intel_dp);
1151
1152 pp = ironlake_get_pp_control(intel_dp);
1153 if (IS_GEN5(dev)) {
1154 /* ILK workaround: disable reset around power sequence */
1155 pp &= ~PANEL_POWER_RESET;
1156 I915_WRITE(PCH_PP_CONTROL, pp);
1157 POSTING_READ(PCH_PP_CONTROL);
1158 }
1159
1160 pp |= POWER_TARGET_ON;
1161 if (!IS_GEN5(dev))
1162 pp |= PANEL_POWER_RESET;
1163
1164 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1165
1166 I915_WRITE(pp_ctrl_reg, pp);
1167 POSTING_READ(pp_ctrl_reg);
1168
1169 ironlake_wait_panel_on(intel_dp);
1170
1171 if (IS_GEN5(dev)) {
1172 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1173 I915_WRITE(PCH_PP_CONTROL, pp);
1174 POSTING_READ(PCH_PP_CONTROL);
1175 }
1176 }
1177
1178 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1179 {
1180 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 u32 pp;
1183 u32 pp_ctrl_reg;
1184
1185 if (!is_edp(intel_dp))
1186 return;
1187
1188 DRM_DEBUG_KMS("Turn eDP power off\n");
1189
1190 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1191
1192 pp = ironlake_get_pp_control(intel_dp);
1193 /* We need to switch off panel power _and_ force vdd, for otherwise some
1194 * panels get very unhappy and cease to work. */
1195 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1196
1197 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1198
1199 I915_WRITE(pp_ctrl_reg, pp);
1200 POSTING_READ(pp_ctrl_reg);
1201
1202 intel_dp->want_panel_vdd = false;
1203
1204 ironlake_wait_panel_off(intel_dp);
1205 }
1206
1207 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1208 {
1209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1210 struct drm_device *dev = intel_dig_port->base.base.dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1213 u32 pp;
1214 u32 pp_ctrl_reg;
1215
1216 if (!is_edp(intel_dp))
1217 return;
1218
1219 DRM_DEBUG_KMS("\n");
1220 /*
1221 * If we enable the backlight right away following a panel power
1222 * on, we may see slight flicker as the panel syncs with the eDP
1223 * link. So delay a bit to make sure the image is solid before
1224 * allowing it to appear.
1225 */
1226 msleep(intel_dp->backlight_on_delay);
1227 pp = ironlake_get_pp_control(intel_dp);
1228 pp |= EDP_BLC_ENABLE;
1229
1230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1231
1232 I915_WRITE(pp_ctrl_reg, pp);
1233 POSTING_READ(pp_ctrl_reg);
1234
1235 intel_panel_enable_backlight(dev, pipe);
1236 }
1237
1238 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1239 {
1240 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 u32 pp;
1243 u32 pp_ctrl_reg;
1244
1245 if (!is_edp(intel_dp))
1246 return;
1247
1248 intel_panel_disable_backlight(dev);
1249
1250 DRM_DEBUG_KMS("\n");
1251 pp = ironlake_get_pp_control(intel_dp);
1252 pp &= ~EDP_BLC_ENABLE;
1253
1254 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1255
1256 I915_WRITE(pp_ctrl_reg, pp);
1257 POSTING_READ(pp_ctrl_reg);
1258 msleep(intel_dp->backlight_off_delay);
1259 }
1260
1261 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1262 {
1263 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1264 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1265 struct drm_device *dev = crtc->dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 u32 dpa_ctl;
1268
1269 assert_pipe_disabled(dev_priv,
1270 to_intel_crtc(crtc)->pipe);
1271
1272 DRM_DEBUG_KMS("\n");
1273 dpa_ctl = I915_READ(DP_A);
1274 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1275 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1276
1277 /* We don't adjust intel_dp->DP while tearing down the link, to
1278 * facilitate link retraining (e.g. after hotplug). Hence clear all
1279 * enable bits here to ensure that we don't enable too much. */
1280 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1281 intel_dp->DP |= DP_PLL_ENABLE;
1282 I915_WRITE(DP_A, intel_dp->DP);
1283 POSTING_READ(DP_A);
1284 udelay(200);
1285 }
1286
1287 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1288 {
1289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1290 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1291 struct drm_device *dev = crtc->dev;
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293 u32 dpa_ctl;
1294
1295 assert_pipe_disabled(dev_priv,
1296 to_intel_crtc(crtc)->pipe);
1297
1298 dpa_ctl = I915_READ(DP_A);
1299 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1300 "dp pll off, should be on\n");
1301 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1302
1303 /* We can't rely on the value tracked for the DP register in
1304 * intel_dp->DP because link_down must not change that (otherwise link
1305 * re-training will fail. */
1306 dpa_ctl &= ~DP_PLL_ENABLE;
1307 I915_WRITE(DP_A, dpa_ctl);
1308 POSTING_READ(DP_A);
1309 udelay(200);
1310 }
1311
1312 /* If the sink supports it, try to set the power state appropriately */
1313 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1314 {
1315 int ret, i;
1316
1317 /* Should have a valid DPCD by this point */
1318 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1319 return;
1320
1321 if (mode != DRM_MODE_DPMS_ON) {
1322 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1323 DP_SET_POWER_D3);
1324 if (ret != 1)
1325 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1326 } else {
1327 /*
1328 * When turning on, we need to retry for 1ms to give the sink
1329 * time to wake up.
1330 */
1331 for (i = 0; i < 3; i++) {
1332 ret = intel_dp_aux_native_write_1(intel_dp,
1333 DP_SET_POWER,
1334 DP_SET_POWER_D0);
1335 if (ret == 1)
1336 break;
1337 msleep(1);
1338 }
1339 }
1340 }
1341
1342 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1343 enum pipe *pipe)
1344 {
1345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1346 struct drm_device *dev = encoder->base.dev;
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 u32 tmp = I915_READ(intel_dp->output_reg);
1349
1350 if (!(tmp & DP_PORT_EN))
1351 return false;
1352
1353 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1354 *pipe = PORT_TO_PIPE_CPT(tmp);
1355 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1356 *pipe = PORT_TO_PIPE(tmp);
1357 } else {
1358 u32 trans_sel;
1359 u32 trans_dp;
1360 int i;
1361
1362 switch (intel_dp->output_reg) {
1363 case PCH_DP_B:
1364 trans_sel = TRANS_DP_PORT_SEL_B;
1365 break;
1366 case PCH_DP_C:
1367 trans_sel = TRANS_DP_PORT_SEL_C;
1368 break;
1369 case PCH_DP_D:
1370 trans_sel = TRANS_DP_PORT_SEL_D;
1371 break;
1372 default:
1373 return true;
1374 }
1375
1376 for_each_pipe(i) {
1377 trans_dp = I915_READ(TRANS_DP_CTL(i));
1378 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1379 *pipe = i;
1380 return true;
1381 }
1382 }
1383
1384 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1385 intel_dp->output_reg);
1386 }
1387
1388 return true;
1389 }
1390
1391 static void intel_disable_dp(struct intel_encoder *encoder)
1392 {
1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1394
1395 /* Make sure the panel is off before trying to change the mode. But also
1396 * ensure that we have vdd while we switch off the panel. */
1397 ironlake_edp_panel_vdd_on(intel_dp);
1398 ironlake_edp_backlight_off(intel_dp);
1399 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1400 ironlake_edp_panel_off(intel_dp);
1401
1402 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1403 if (!is_cpu_edp(intel_dp))
1404 intel_dp_link_down(intel_dp);
1405 }
1406
1407 static void intel_post_disable_dp(struct intel_encoder *encoder)
1408 {
1409 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1410 struct drm_device *dev = encoder->base.dev;
1411
1412 if (is_cpu_edp(intel_dp)) {
1413 intel_dp_link_down(intel_dp);
1414 if (!IS_VALLEYVIEW(dev))
1415 ironlake_edp_pll_off(intel_dp);
1416 }
1417 }
1418
1419 static void intel_enable_dp(struct intel_encoder *encoder)
1420 {
1421 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1422 struct drm_device *dev = encoder->base.dev;
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1425
1426 if (WARN_ON(dp_reg & DP_PORT_EN))
1427 return;
1428
1429 ironlake_edp_panel_vdd_on(intel_dp);
1430 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1431 intel_dp_start_link_train(intel_dp);
1432 ironlake_edp_panel_on(intel_dp);
1433 ironlake_edp_panel_vdd_off(intel_dp, true);
1434 intel_dp_complete_link_train(intel_dp);
1435 ironlake_edp_backlight_on(intel_dp);
1436
1437 if (IS_VALLEYVIEW(dev)) {
1438 struct intel_digital_port *dport =
1439 enc_to_dig_port(&encoder->base);
1440 int channel = vlv_dport_to_channel(dport);
1441
1442 vlv_wait_port_ready(dev_priv, channel);
1443 }
1444 }
1445
1446 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1447 {
1448 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1449 struct drm_device *dev = encoder->base.dev;
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451
1452 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1453 ironlake_edp_pll_on(intel_dp);
1454
1455 if (IS_VALLEYVIEW(dev)) {
1456 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1457 struct intel_crtc *intel_crtc =
1458 to_intel_crtc(encoder->base.crtc);
1459 int port = vlv_dport_to_channel(dport);
1460 int pipe = intel_crtc->pipe;
1461 u32 val;
1462
1463 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1464
1465 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1466 val = 0;
1467 if (pipe)
1468 val |= (1<<21);
1469 else
1470 val &= ~(1<<21);
1471 val |= 0x001000c4;
1472 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1473
1474 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1475 0x00760018);
1476 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1477 0x00400888);
1478 }
1479 }
1480
1481 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1482 {
1483 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1484 struct drm_device *dev = encoder->base.dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 int port = vlv_dport_to_channel(dport);
1487
1488 if (!IS_VALLEYVIEW(dev))
1489 return;
1490
1491 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1492
1493 /* Program Tx lane resets to default */
1494 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1495 DPIO_PCS_TX_LANE2_RESET |
1496 DPIO_PCS_TX_LANE1_RESET);
1497 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1498 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1499 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1500 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1501 DPIO_PCS_CLK_SOFT_RESET);
1502
1503 /* Fix up inter-pair skew failure */
1504 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1505 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1506 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1507 }
1508
1509 /*
1510 * Native read with retry for link status and receiver capability reads for
1511 * cases where the sink may still be asleep.
1512 */
1513 static bool
1514 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1515 uint8_t *recv, int recv_bytes)
1516 {
1517 int ret, i;
1518
1519 /*
1520 * Sinks are *supposed* to come up within 1ms from an off state,
1521 * but we're also supposed to retry 3 times per the spec.
1522 */
1523 for (i = 0; i < 3; i++) {
1524 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1525 recv_bytes);
1526 if (ret == recv_bytes)
1527 return true;
1528 msleep(1);
1529 }
1530
1531 return false;
1532 }
1533
1534 /*
1535 * Fetch AUX CH registers 0x202 - 0x207 which contain
1536 * link status information
1537 */
1538 static bool
1539 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1540 {
1541 return intel_dp_aux_native_read_retry(intel_dp,
1542 DP_LANE0_1_STATUS,
1543 link_status,
1544 DP_LINK_STATUS_SIZE);
1545 }
1546
1547 #if 0
1548 static char *voltage_names[] = {
1549 "0.4V", "0.6V", "0.8V", "1.2V"
1550 };
1551 static char *pre_emph_names[] = {
1552 "0dB", "3.5dB", "6dB", "9.5dB"
1553 };
1554 static char *link_train_names[] = {
1555 "pattern 1", "pattern 2", "idle", "off"
1556 };
1557 #endif
1558
1559 /*
1560 * These are source-specific values; current Intel hardware supports
1561 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1562 */
1563
1564 static uint8_t
1565 intel_dp_voltage_max(struct intel_dp *intel_dp)
1566 {
1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568
1569 if (IS_VALLEYVIEW(dev))
1570 return DP_TRAIN_VOLTAGE_SWING_1200;
1571 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1572 return DP_TRAIN_VOLTAGE_SWING_800;
1573 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1574 return DP_TRAIN_VOLTAGE_SWING_1200;
1575 else
1576 return DP_TRAIN_VOLTAGE_SWING_800;
1577 }
1578
1579 static uint8_t
1580 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1581 {
1582 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1583
1584 if (HAS_DDI(dev)) {
1585 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1586 case DP_TRAIN_VOLTAGE_SWING_400:
1587 return DP_TRAIN_PRE_EMPHASIS_9_5;
1588 case DP_TRAIN_VOLTAGE_SWING_600:
1589 return DP_TRAIN_PRE_EMPHASIS_6;
1590 case DP_TRAIN_VOLTAGE_SWING_800:
1591 return DP_TRAIN_PRE_EMPHASIS_3_5;
1592 case DP_TRAIN_VOLTAGE_SWING_1200:
1593 default:
1594 return DP_TRAIN_PRE_EMPHASIS_0;
1595 }
1596 } else if (IS_VALLEYVIEW(dev)) {
1597 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1598 case DP_TRAIN_VOLTAGE_SWING_400:
1599 return DP_TRAIN_PRE_EMPHASIS_9_5;
1600 case DP_TRAIN_VOLTAGE_SWING_600:
1601 return DP_TRAIN_PRE_EMPHASIS_6;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 return DP_TRAIN_PRE_EMPHASIS_3_5;
1604 case DP_TRAIN_VOLTAGE_SWING_1200:
1605 default:
1606 return DP_TRAIN_PRE_EMPHASIS_0;
1607 }
1608 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1609 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1610 case DP_TRAIN_VOLTAGE_SWING_400:
1611 return DP_TRAIN_PRE_EMPHASIS_6;
1612 case DP_TRAIN_VOLTAGE_SWING_600:
1613 case DP_TRAIN_VOLTAGE_SWING_800:
1614 return DP_TRAIN_PRE_EMPHASIS_3_5;
1615 default:
1616 return DP_TRAIN_PRE_EMPHASIS_0;
1617 }
1618 } else {
1619 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1620 case DP_TRAIN_VOLTAGE_SWING_400:
1621 return DP_TRAIN_PRE_EMPHASIS_6;
1622 case DP_TRAIN_VOLTAGE_SWING_600:
1623 return DP_TRAIN_PRE_EMPHASIS_6;
1624 case DP_TRAIN_VOLTAGE_SWING_800:
1625 return DP_TRAIN_PRE_EMPHASIS_3_5;
1626 case DP_TRAIN_VOLTAGE_SWING_1200:
1627 default:
1628 return DP_TRAIN_PRE_EMPHASIS_0;
1629 }
1630 }
1631 }
1632
1633 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1634 {
1635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1638 unsigned long demph_reg_value, preemph_reg_value,
1639 uniqtranscale_reg_value;
1640 uint8_t train_set = intel_dp->train_set[0];
1641 int port = vlv_dport_to_channel(dport);
1642
1643 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1644
1645 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1646 case DP_TRAIN_PRE_EMPHASIS_0:
1647 preemph_reg_value = 0x0004000;
1648 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1649 case DP_TRAIN_VOLTAGE_SWING_400:
1650 demph_reg_value = 0x2B405555;
1651 uniqtranscale_reg_value = 0x552AB83A;
1652 break;
1653 case DP_TRAIN_VOLTAGE_SWING_600:
1654 demph_reg_value = 0x2B404040;
1655 uniqtranscale_reg_value = 0x5548B83A;
1656 break;
1657 case DP_TRAIN_VOLTAGE_SWING_800:
1658 demph_reg_value = 0x2B245555;
1659 uniqtranscale_reg_value = 0x5560B83A;
1660 break;
1661 case DP_TRAIN_VOLTAGE_SWING_1200:
1662 demph_reg_value = 0x2B405555;
1663 uniqtranscale_reg_value = 0x5598DA3A;
1664 break;
1665 default:
1666 return 0;
1667 }
1668 break;
1669 case DP_TRAIN_PRE_EMPHASIS_3_5:
1670 preemph_reg_value = 0x0002000;
1671 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1672 case DP_TRAIN_VOLTAGE_SWING_400:
1673 demph_reg_value = 0x2B404040;
1674 uniqtranscale_reg_value = 0x5552B83A;
1675 break;
1676 case DP_TRAIN_VOLTAGE_SWING_600:
1677 demph_reg_value = 0x2B404848;
1678 uniqtranscale_reg_value = 0x5580B83A;
1679 break;
1680 case DP_TRAIN_VOLTAGE_SWING_800:
1681 demph_reg_value = 0x2B404040;
1682 uniqtranscale_reg_value = 0x55ADDA3A;
1683 break;
1684 default:
1685 return 0;
1686 }
1687 break;
1688 case DP_TRAIN_PRE_EMPHASIS_6:
1689 preemph_reg_value = 0x0000000;
1690 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1691 case DP_TRAIN_VOLTAGE_SWING_400:
1692 demph_reg_value = 0x2B305555;
1693 uniqtranscale_reg_value = 0x5570B83A;
1694 break;
1695 case DP_TRAIN_VOLTAGE_SWING_600:
1696 demph_reg_value = 0x2B2B4040;
1697 uniqtranscale_reg_value = 0x55ADDA3A;
1698 break;
1699 default:
1700 return 0;
1701 }
1702 break;
1703 case DP_TRAIN_PRE_EMPHASIS_9_5:
1704 preemph_reg_value = 0x0006000;
1705 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1706 case DP_TRAIN_VOLTAGE_SWING_400:
1707 demph_reg_value = 0x1B405555;
1708 uniqtranscale_reg_value = 0x55ADDA3A;
1709 break;
1710 default:
1711 return 0;
1712 }
1713 break;
1714 default:
1715 return 0;
1716 }
1717
1718 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1719 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1720 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1721 uniqtranscale_reg_value);
1722 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1723 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1724 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1725 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1726
1727 return 0;
1728 }
1729
1730 static void
1731 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1732 {
1733 uint8_t v = 0;
1734 uint8_t p = 0;
1735 int lane;
1736 uint8_t voltage_max;
1737 uint8_t preemph_max;
1738
1739 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1740 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1741 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1742
1743 if (this_v > v)
1744 v = this_v;
1745 if (this_p > p)
1746 p = this_p;
1747 }
1748
1749 voltage_max = intel_dp_voltage_max(intel_dp);
1750 if (v >= voltage_max)
1751 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1752
1753 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1754 if (p >= preemph_max)
1755 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1756
1757 for (lane = 0; lane < 4; lane++)
1758 intel_dp->train_set[lane] = v | p;
1759 }
1760
1761 static uint32_t
1762 intel_gen4_signal_levels(uint8_t train_set)
1763 {
1764 uint32_t signal_levels = 0;
1765
1766 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1767 case DP_TRAIN_VOLTAGE_SWING_400:
1768 default:
1769 signal_levels |= DP_VOLTAGE_0_4;
1770 break;
1771 case DP_TRAIN_VOLTAGE_SWING_600:
1772 signal_levels |= DP_VOLTAGE_0_6;
1773 break;
1774 case DP_TRAIN_VOLTAGE_SWING_800:
1775 signal_levels |= DP_VOLTAGE_0_8;
1776 break;
1777 case DP_TRAIN_VOLTAGE_SWING_1200:
1778 signal_levels |= DP_VOLTAGE_1_2;
1779 break;
1780 }
1781 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1782 case DP_TRAIN_PRE_EMPHASIS_0:
1783 default:
1784 signal_levels |= DP_PRE_EMPHASIS_0;
1785 break;
1786 case DP_TRAIN_PRE_EMPHASIS_3_5:
1787 signal_levels |= DP_PRE_EMPHASIS_3_5;
1788 break;
1789 case DP_TRAIN_PRE_EMPHASIS_6:
1790 signal_levels |= DP_PRE_EMPHASIS_6;
1791 break;
1792 case DP_TRAIN_PRE_EMPHASIS_9_5:
1793 signal_levels |= DP_PRE_EMPHASIS_9_5;
1794 break;
1795 }
1796 return signal_levels;
1797 }
1798
1799 /* Gen6's DP voltage swing and pre-emphasis control */
1800 static uint32_t
1801 intel_gen6_edp_signal_levels(uint8_t train_set)
1802 {
1803 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1804 DP_TRAIN_PRE_EMPHASIS_MASK);
1805 switch (signal_levels) {
1806 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1807 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1808 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1809 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1810 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1811 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1812 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1813 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1814 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1815 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1816 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1817 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1818 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1819 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1820 default:
1821 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1822 "0x%x\n", signal_levels);
1823 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1824 }
1825 }
1826
1827 /* Gen7's DP voltage swing and pre-emphasis control */
1828 static uint32_t
1829 intel_gen7_edp_signal_levels(uint8_t train_set)
1830 {
1831 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1832 DP_TRAIN_PRE_EMPHASIS_MASK);
1833 switch (signal_levels) {
1834 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1835 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1836 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1837 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1838 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1839 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1840
1841 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1842 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1843 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1844 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1845
1846 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1847 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1848 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1849 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1850
1851 default:
1852 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1853 "0x%x\n", signal_levels);
1854 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1855 }
1856 }
1857
1858 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1859 static uint32_t
1860 intel_hsw_signal_levels(uint8_t train_set)
1861 {
1862 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1863 DP_TRAIN_PRE_EMPHASIS_MASK);
1864 switch (signal_levels) {
1865 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1866 return DDI_BUF_EMP_400MV_0DB_HSW;
1867 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1868 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1869 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1870 return DDI_BUF_EMP_400MV_6DB_HSW;
1871 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1872 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1873
1874 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1875 return DDI_BUF_EMP_600MV_0DB_HSW;
1876 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1877 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1878 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1879 return DDI_BUF_EMP_600MV_6DB_HSW;
1880
1881 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1882 return DDI_BUF_EMP_800MV_0DB_HSW;
1883 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1884 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1885 default:
1886 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1887 "0x%x\n", signal_levels);
1888 return DDI_BUF_EMP_400MV_0DB_HSW;
1889 }
1890 }
1891
1892 /* Properly updates "DP" with the correct signal levels. */
1893 static void
1894 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1895 {
1896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1897 struct drm_device *dev = intel_dig_port->base.base.dev;
1898 uint32_t signal_levels, mask;
1899 uint8_t train_set = intel_dp->train_set[0];
1900
1901 if (HAS_DDI(dev)) {
1902 signal_levels = intel_hsw_signal_levels(train_set);
1903 mask = DDI_BUF_EMP_MASK;
1904 } else if (IS_VALLEYVIEW(dev)) {
1905 signal_levels = intel_vlv_signal_levels(intel_dp);
1906 mask = 0;
1907 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1908 signal_levels = intel_gen7_edp_signal_levels(train_set);
1909 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1910 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1911 signal_levels = intel_gen6_edp_signal_levels(train_set);
1912 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1913 } else {
1914 signal_levels = intel_gen4_signal_levels(train_set);
1915 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1916 }
1917
1918 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1919
1920 *DP = (*DP & ~mask) | signal_levels;
1921 }
1922
1923 static bool
1924 intel_dp_set_link_train(struct intel_dp *intel_dp,
1925 uint32_t dp_reg_value,
1926 uint8_t dp_train_pat)
1927 {
1928 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1929 struct drm_device *dev = intel_dig_port->base.base.dev;
1930 struct drm_i915_private *dev_priv = dev->dev_private;
1931 enum port port = intel_dig_port->port;
1932 int ret;
1933 uint32_t temp;
1934
1935 if (HAS_DDI(dev)) {
1936 temp = I915_READ(DP_TP_CTL(port));
1937
1938 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1939 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1940 else
1941 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1942
1943 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1944 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1945 case DP_TRAINING_PATTERN_DISABLE:
1946
1947 if (port != PORT_A) {
1948 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1949 I915_WRITE(DP_TP_CTL(port), temp);
1950
1951 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1952 DP_TP_STATUS_IDLE_DONE), 1))
1953 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1954
1955 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1956 }
1957
1958 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1959
1960 break;
1961 case DP_TRAINING_PATTERN_1:
1962 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1963 break;
1964 case DP_TRAINING_PATTERN_2:
1965 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1966 break;
1967 case DP_TRAINING_PATTERN_3:
1968 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1969 break;
1970 }
1971 I915_WRITE(DP_TP_CTL(port), temp);
1972
1973 } else if (HAS_PCH_CPT(dev) &&
1974 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1975 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1976
1977 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1978 case DP_TRAINING_PATTERN_DISABLE:
1979 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1980 break;
1981 case DP_TRAINING_PATTERN_1:
1982 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1983 break;
1984 case DP_TRAINING_PATTERN_2:
1985 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1986 break;
1987 case DP_TRAINING_PATTERN_3:
1988 DRM_ERROR("DP training pattern 3 not supported\n");
1989 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1990 break;
1991 }
1992
1993 } else {
1994 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1995
1996 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1997 case DP_TRAINING_PATTERN_DISABLE:
1998 dp_reg_value |= DP_LINK_TRAIN_OFF;
1999 break;
2000 case DP_TRAINING_PATTERN_1:
2001 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2002 break;
2003 case DP_TRAINING_PATTERN_2:
2004 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2005 break;
2006 case DP_TRAINING_PATTERN_3:
2007 DRM_ERROR("DP training pattern 3 not supported\n");
2008 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2009 break;
2010 }
2011 }
2012
2013 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2014 POSTING_READ(intel_dp->output_reg);
2015
2016 intel_dp_aux_native_write_1(intel_dp,
2017 DP_TRAINING_PATTERN_SET,
2018 dp_train_pat);
2019
2020 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2021 DP_TRAINING_PATTERN_DISABLE) {
2022 ret = intel_dp_aux_native_write(intel_dp,
2023 DP_TRAINING_LANE0_SET,
2024 intel_dp->train_set,
2025 intel_dp->lane_count);
2026 if (ret != intel_dp->lane_count)
2027 return false;
2028 }
2029
2030 return true;
2031 }
2032
2033 /* Enable corresponding port and start training pattern 1 */
2034 void
2035 intel_dp_start_link_train(struct intel_dp *intel_dp)
2036 {
2037 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2038 struct drm_device *dev = encoder->dev;
2039 int i;
2040 uint8_t voltage;
2041 bool clock_recovery = false;
2042 int voltage_tries, loop_tries;
2043 uint32_t DP = intel_dp->DP;
2044
2045 if (HAS_DDI(dev))
2046 intel_ddi_prepare_link_retrain(encoder);
2047
2048 /* Write the link configuration data */
2049 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2050 intel_dp->link_configuration,
2051 DP_LINK_CONFIGURATION_SIZE);
2052
2053 DP |= DP_PORT_EN;
2054
2055 memset(intel_dp->train_set, 0, 4);
2056 voltage = 0xff;
2057 voltage_tries = 0;
2058 loop_tries = 0;
2059 clock_recovery = false;
2060 for (;;) {
2061 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2062 uint8_t link_status[DP_LINK_STATUS_SIZE];
2063
2064 intel_dp_set_signal_levels(intel_dp, &DP);
2065
2066 /* Set training pattern 1 */
2067 if (!intel_dp_set_link_train(intel_dp, DP,
2068 DP_TRAINING_PATTERN_1 |
2069 DP_LINK_SCRAMBLING_DISABLE))
2070 break;
2071
2072 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2073 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2074 DRM_ERROR("failed to get link status\n");
2075 break;
2076 }
2077
2078 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2079 DRM_DEBUG_KMS("clock recovery OK\n");
2080 clock_recovery = true;
2081 break;
2082 }
2083
2084 /* Check to see if we've tried the max voltage */
2085 for (i = 0; i < intel_dp->lane_count; i++)
2086 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2087 break;
2088 if (i == intel_dp->lane_count) {
2089 ++loop_tries;
2090 if (loop_tries == 5) {
2091 DRM_DEBUG_KMS("too many full retries, give up\n");
2092 break;
2093 }
2094 memset(intel_dp->train_set, 0, 4);
2095 voltage_tries = 0;
2096 continue;
2097 }
2098
2099 /* Check to see if we've tried the same voltage 5 times */
2100 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2101 ++voltage_tries;
2102 if (voltage_tries == 5) {
2103 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2104 break;
2105 }
2106 } else
2107 voltage_tries = 0;
2108 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2109
2110 /* Compute new intel_dp->train_set as requested by target */
2111 intel_get_adjust_train(intel_dp, link_status);
2112 }
2113
2114 intel_dp->DP = DP;
2115 }
2116
2117 void
2118 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2119 {
2120 bool channel_eq = false;
2121 int tries, cr_tries;
2122 uint32_t DP = intel_dp->DP;
2123
2124 /* channel equalization */
2125 tries = 0;
2126 cr_tries = 0;
2127 channel_eq = false;
2128 for (;;) {
2129 uint8_t link_status[DP_LINK_STATUS_SIZE];
2130
2131 if (cr_tries > 5) {
2132 DRM_ERROR("failed to train DP, aborting\n");
2133 intel_dp_link_down(intel_dp);
2134 break;
2135 }
2136
2137 intel_dp_set_signal_levels(intel_dp, &DP);
2138
2139 /* channel eq pattern */
2140 if (!intel_dp_set_link_train(intel_dp, DP,
2141 DP_TRAINING_PATTERN_2 |
2142 DP_LINK_SCRAMBLING_DISABLE))
2143 break;
2144
2145 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2146 if (!intel_dp_get_link_status(intel_dp, link_status))
2147 break;
2148
2149 /* Make sure clock is still ok */
2150 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2151 intel_dp_start_link_train(intel_dp);
2152 cr_tries++;
2153 continue;
2154 }
2155
2156 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2157 channel_eq = true;
2158 break;
2159 }
2160
2161 /* Try 5 times, then try clock recovery if that fails */
2162 if (tries > 5) {
2163 intel_dp_link_down(intel_dp);
2164 intel_dp_start_link_train(intel_dp);
2165 tries = 0;
2166 cr_tries++;
2167 continue;
2168 }
2169
2170 /* Compute new intel_dp->train_set as requested by target */
2171 intel_get_adjust_train(intel_dp, link_status);
2172 ++tries;
2173 }
2174
2175 if (channel_eq)
2176 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2177
2178 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2179 }
2180
2181 static void
2182 intel_dp_link_down(struct intel_dp *intel_dp)
2183 {
2184 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2185 struct drm_device *dev = intel_dig_port->base.base.dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct intel_crtc *intel_crtc =
2188 to_intel_crtc(intel_dig_port->base.base.crtc);
2189 uint32_t DP = intel_dp->DP;
2190
2191 /*
2192 * DDI code has a strict mode set sequence and we should try to respect
2193 * it, otherwise we might hang the machine in many different ways. So we
2194 * really should be disabling the port only on a complete crtc_disable
2195 * sequence. This function is just called under two conditions on DDI
2196 * code:
2197 * - Link train failed while doing crtc_enable, and on this case we
2198 * really should respect the mode set sequence and wait for a
2199 * crtc_disable.
2200 * - Someone turned the monitor off and intel_dp_check_link_status
2201 * called us. We don't need to disable the whole port on this case, so
2202 * when someone turns the monitor on again,
2203 * intel_ddi_prepare_link_retrain will take care of redoing the link
2204 * train.
2205 */
2206 if (HAS_DDI(dev))
2207 return;
2208
2209 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2210 return;
2211
2212 DRM_DEBUG_KMS("\n");
2213
2214 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2215 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2216 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2217 } else {
2218 DP &= ~DP_LINK_TRAIN_MASK;
2219 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2220 }
2221 POSTING_READ(intel_dp->output_reg);
2222
2223 /* We don't really know why we're doing this */
2224 intel_wait_for_vblank(dev, intel_crtc->pipe);
2225
2226 if (HAS_PCH_IBX(dev) &&
2227 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2228 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2229
2230 /* Hardware workaround: leaving our transcoder select
2231 * set to transcoder B while it's off will prevent the
2232 * corresponding HDMI output on transcoder A.
2233 *
2234 * Combine this with another hardware workaround:
2235 * transcoder select bit can only be cleared while the
2236 * port is enabled.
2237 */
2238 DP &= ~DP_PIPEB_SELECT;
2239 I915_WRITE(intel_dp->output_reg, DP);
2240
2241 /* Changes to enable or select take place the vblank
2242 * after being written.
2243 */
2244 if (WARN_ON(crtc == NULL)) {
2245 /* We should never try to disable a port without a crtc
2246 * attached. For paranoia keep the code around for a
2247 * bit. */
2248 POSTING_READ(intel_dp->output_reg);
2249 msleep(50);
2250 } else
2251 intel_wait_for_vblank(dev, intel_crtc->pipe);
2252 }
2253
2254 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2255 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2256 POSTING_READ(intel_dp->output_reg);
2257 msleep(intel_dp->panel_power_down_delay);
2258 }
2259
2260 static bool
2261 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2262 {
2263 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2264
2265 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2266 sizeof(intel_dp->dpcd)) == 0)
2267 return false; /* aux transfer failed */
2268
2269 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2270 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2271 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2272
2273 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2274 return false; /* DPCD not present */
2275
2276 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2277 DP_DWN_STRM_PORT_PRESENT))
2278 return true; /* native DP sink */
2279
2280 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2281 return true; /* no per-port downstream info */
2282
2283 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2284 intel_dp->downstream_ports,
2285 DP_MAX_DOWNSTREAM_PORTS) == 0)
2286 return false; /* downstream port status fetch failed */
2287
2288 return true;
2289 }
2290
2291 static void
2292 intel_dp_probe_oui(struct intel_dp *intel_dp)
2293 {
2294 u8 buf[3];
2295
2296 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2297 return;
2298
2299 ironlake_edp_panel_vdd_on(intel_dp);
2300
2301 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2302 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2303 buf[0], buf[1], buf[2]);
2304
2305 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2306 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2307 buf[0], buf[1], buf[2]);
2308
2309 ironlake_edp_panel_vdd_off(intel_dp, false);
2310 }
2311
2312 static bool
2313 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2314 {
2315 int ret;
2316
2317 ret = intel_dp_aux_native_read_retry(intel_dp,
2318 DP_DEVICE_SERVICE_IRQ_VECTOR,
2319 sink_irq_vector, 1);
2320 if (!ret)
2321 return false;
2322
2323 return true;
2324 }
2325
2326 static void
2327 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2328 {
2329 /* NAK by default */
2330 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2331 }
2332
2333 /*
2334 * According to DP spec
2335 * 5.1.2:
2336 * 1. Read DPCD
2337 * 2. Configure link according to Receiver Capabilities
2338 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2339 * 4. Check link status on receipt of hot-plug interrupt
2340 */
2341
2342 void
2343 intel_dp_check_link_status(struct intel_dp *intel_dp)
2344 {
2345 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2346 u8 sink_irq_vector;
2347 u8 link_status[DP_LINK_STATUS_SIZE];
2348
2349 if (!intel_encoder->connectors_active)
2350 return;
2351
2352 if (WARN_ON(!intel_encoder->base.crtc))
2353 return;
2354
2355 /* Try to read receiver status if the link appears to be up */
2356 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2357 intel_dp_link_down(intel_dp);
2358 return;
2359 }
2360
2361 /* Now read the DPCD to see if it's actually running */
2362 if (!intel_dp_get_dpcd(intel_dp)) {
2363 intel_dp_link_down(intel_dp);
2364 return;
2365 }
2366
2367 /* Try to read the source of the interrupt */
2368 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2369 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2370 /* Clear interrupt source */
2371 intel_dp_aux_native_write_1(intel_dp,
2372 DP_DEVICE_SERVICE_IRQ_VECTOR,
2373 sink_irq_vector);
2374
2375 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2376 intel_dp_handle_test_request(intel_dp);
2377 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2378 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2379 }
2380
2381 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2382 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2383 drm_get_encoder_name(&intel_encoder->base));
2384 intel_dp_start_link_train(intel_dp);
2385 intel_dp_complete_link_train(intel_dp);
2386 }
2387 }
2388
2389 /* XXX this is probably wrong for multiple downstream ports */
2390 static enum drm_connector_status
2391 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2392 {
2393 uint8_t *dpcd = intel_dp->dpcd;
2394 bool hpd;
2395 uint8_t type;
2396
2397 if (!intel_dp_get_dpcd(intel_dp))
2398 return connector_status_disconnected;
2399
2400 /* if there's no downstream port, we're done */
2401 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2402 return connector_status_connected;
2403
2404 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2405 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2406 if (hpd) {
2407 uint8_t reg;
2408 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2409 &reg, 1))
2410 return connector_status_unknown;
2411 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2412 : connector_status_disconnected;
2413 }
2414
2415 /* If no HPD, poke DDC gently */
2416 if (drm_probe_ddc(&intel_dp->adapter))
2417 return connector_status_connected;
2418
2419 /* Well we tried, say unknown for unreliable port types */
2420 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2421 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2422 return connector_status_unknown;
2423
2424 /* Anything else is out of spec, warn and ignore */
2425 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2426 return connector_status_disconnected;
2427 }
2428
2429 static enum drm_connector_status
2430 ironlake_dp_detect(struct intel_dp *intel_dp)
2431 {
2432 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2435 enum drm_connector_status status;
2436
2437 /* Can't disconnect eDP, but you can close the lid... */
2438 if (is_edp(intel_dp)) {
2439 status = intel_panel_detect(dev);
2440 if (status == connector_status_unknown)
2441 status = connector_status_connected;
2442 return status;
2443 }
2444
2445 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2446 return connector_status_disconnected;
2447
2448 return intel_dp_detect_dpcd(intel_dp);
2449 }
2450
2451 static enum drm_connector_status
2452 g4x_dp_detect(struct intel_dp *intel_dp)
2453 {
2454 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2457 uint32_t bit;
2458
2459 /* Can't disconnect eDP, but you can close the lid... */
2460 if (is_edp(intel_dp)) {
2461 enum drm_connector_status status;
2462
2463 status = intel_panel_detect(dev);
2464 if (status == connector_status_unknown)
2465 status = connector_status_connected;
2466 return status;
2467 }
2468
2469 switch (intel_dig_port->port) {
2470 case PORT_B:
2471 bit = PORTB_HOTPLUG_LIVE_STATUS;
2472 break;
2473 case PORT_C:
2474 bit = PORTC_HOTPLUG_LIVE_STATUS;
2475 break;
2476 case PORT_D:
2477 bit = PORTD_HOTPLUG_LIVE_STATUS;
2478 break;
2479 default:
2480 return connector_status_unknown;
2481 }
2482
2483 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2484 return connector_status_disconnected;
2485
2486 return intel_dp_detect_dpcd(intel_dp);
2487 }
2488
2489 static struct edid *
2490 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2491 {
2492 struct intel_connector *intel_connector = to_intel_connector(connector);
2493
2494 /* use cached edid if we have one */
2495 if (intel_connector->edid) {
2496 struct edid *edid;
2497 int size;
2498
2499 /* invalid edid */
2500 if (IS_ERR(intel_connector->edid))
2501 return NULL;
2502
2503 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2504 edid = kmalloc(size, GFP_KERNEL);
2505 if (!edid)
2506 return NULL;
2507
2508 memcpy(edid, intel_connector->edid, size);
2509 return edid;
2510 }
2511
2512 return drm_get_edid(connector, adapter);
2513 }
2514
2515 static int
2516 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2517 {
2518 struct intel_connector *intel_connector = to_intel_connector(connector);
2519
2520 /* use cached edid if we have one */
2521 if (intel_connector->edid) {
2522 /* invalid edid */
2523 if (IS_ERR(intel_connector->edid))
2524 return 0;
2525
2526 return intel_connector_update_modes(connector,
2527 intel_connector->edid);
2528 }
2529
2530 return intel_ddc_get_modes(connector, adapter);
2531 }
2532
2533 static enum drm_connector_status
2534 intel_dp_detect(struct drm_connector *connector, bool force)
2535 {
2536 struct intel_dp *intel_dp = intel_attached_dp(connector);
2537 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2538 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2539 struct drm_device *dev = connector->dev;
2540 enum drm_connector_status status;
2541 struct edid *edid = NULL;
2542
2543 intel_dp->has_audio = false;
2544
2545 if (HAS_PCH_SPLIT(dev))
2546 status = ironlake_dp_detect(intel_dp);
2547 else
2548 status = g4x_dp_detect(intel_dp);
2549
2550 if (status != connector_status_connected)
2551 return status;
2552
2553 intel_dp_probe_oui(intel_dp);
2554
2555 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2556 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2557 } else {
2558 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2559 if (edid) {
2560 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2561 kfree(edid);
2562 }
2563 }
2564
2565 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2566 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2567 return connector_status_connected;
2568 }
2569
2570 static int intel_dp_get_modes(struct drm_connector *connector)
2571 {
2572 struct intel_dp *intel_dp = intel_attached_dp(connector);
2573 struct intel_connector *intel_connector = to_intel_connector(connector);
2574 struct drm_device *dev = connector->dev;
2575 int ret;
2576
2577 /* We should parse the EDID data and find out if it has an audio sink
2578 */
2579
2580 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2581 if (ret)
2582 return ret;
2583
2584 /* if eDP has no EDID, fall back to fixed mode */
2585 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2586 struct drm_display_mode *mode;
2587 mode = drm_mode_duplicate(dev,
2588 intel_connector->panel.fixed_mode);
2589 if (mode) {
2590 drm_mode_probed_add(connector, mode);
2591 return 1;
2592 }
2593 }
2594 return 0;
2595 }
2596
2597 static bool
2598 intel_dp_detect_audio(struct drm_connector *connector)
2599 {
2600 struct intel_dp *intel_dp = intel_attached_dp(connector);
2601 struct edid *edid;
2602 bool has_audio = false;
2603
2604 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2605 if (edid) {
2606 has_audio = drm_detect_monitor_audio(edid);
2607 kfree(edid);
2608 }
2609
2610 return has_audio;
2611 }
2612
2613 static int
2614 intel_dp_set_property(struct drm_connector *connector,
2615 struct drm_property *property,
2616 uint64_t val)
2617 {
2618 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2619 struct intel_connector *intel_connector = to_intel_connector(connector);
2620 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2621 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2622 int ret;
2623
2624 ret = drm_object_property_set_value(&connector->base, property, val);
2625 if (ret)
2626 return ret;
2627
2628 if (property == dev_priv->force_audio_property) {
2629 int i = val;
2630 bool has_audio;
2631
2632 if (i == intel_dp->force_audio)
2633 return 0;
2634
2635 intel_dp->force_audio = i;
2636
2637 if (i == HDMI_AUDIO_AUTO)
2638 has_audio = intel_dp_detect_audio(connector);
2639 else
2640 has_audio = (i == HDMI_AUDIO_ON);
2641
2642 if (has_audio == intel_dp->has_audio)
2643 return 0;
2644
2645 intel_dp->has_audio = has_audio;
2646 goto done;
2647 }
2648
2649 if (property == dev_priv->broadcast_rgb_property) {
2650 switch (val) {
2651 case INTEL_BROADCAST_RGB_AUTO:
2652 intel_dp->color_range_auto = true;
2653 break;
2654 case INTEL_BROADCAST_RGB_FULL:
2655 intel_dp->color_range_auto = false;
2656 intel_dp->color_range = 0;
2657 break;
2658 case INTEL_BROADCAST_RGB_LIMITED:
2659 intel_dp->color_range_auto = false;
2660 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2661 break;
2662 default:
2663 return -EINVAL;
2664 }
2665 goto done;
2666 }
2667
2668 if (is_edp(intel_dp) &&
2669 property == connector->dev->mode_config.scaling_mode_property) {
2670 if (val == DRM_MODE_SCALE_NONE) {
2671 DRM_DEBUG_KMS("no scaling not supported\n");
2672 return -EINVAL;
2673 }
2674
2675 if (intel_connector->panel.fitting_mode == val) {
2676 /* the eDP scaling property is not changed */
2677 return 0;
2678 }
2679 intel_connector->panel.fitting_mode = val;
2680
2681 goto done;
2682 }
2683
2684 return -EINVAL;
2685
2686 done:
2687 if (intel_encoder->base.crtc)
2688 intel_crtc_restore_mode(intel_encoder->base.crtc);
2689
2690 return 0;
2691 }
2692
2693 static void
2694 intel_dp_destroy(struct drm_connector *connector)
2695 {
2696 struct intel_dp *intel_dp = intel_attached_dp(connector);
2697 struct intel_connector *intel_connector = to_intel_connector(connector);
2698
2699 if (!IS_ERR_OR_NULL(intel_connector->edid))
2700 kfree(intel_connector->edid);
2701
2702 if (is_edp(intel_dp))
2703 intel_panel_fini(&intel_connector->panel);
2704
2705 drm_sysfs_connector_remove(connector);
2706 drm_connector_cleanup(connector);
2707 kfree(connector);
2708 }
2709
2710 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2711 {
2712 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2713 struct intel_dp *intel_dp = &intel_dig_port->dp;
2714
2715 i2c_del_adapter(&intel_dp->adapter);
2716 drm_encoder_cleanup(encoder);
2717 if (is_edp(intel_dp)) {
2718 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2719 ironlake_panel_vdd_off_sync(intel_dp);
2720 }
2721 kfree(intel_dig_port);
2722 }
2723
2724 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2725 .mode_set = intel_dp_mode_set,
2726 };
2727
2728 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2729 .dpms = intel_connector_dpms,
2730 .detect = intel_dp_detect,
2731 .fill_modes = drm_helper_probe_single_connector_modes,
2732 .set_property = intel_dp_set_property,
2733 .destroy = intel_dp_destroy,
2734 };
2735
2736 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2737 .get_modes = intel_dp_get_modes,
2738 .mode_valid = intel_dp_mode_valid,
2739 .best_encoder = intel_best_encoder,
2740 };
2741
2742 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2743 .destroy = intel_dp_encoder_destroy,
2744 };
2745
2746 static void
2747 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2748 {
2749 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2750
2751 intel_dp_check_link_status(intel_dp);
2752 }
2753
2754 /* Return which DP Port should be selected for Transcoder DP control */
2755 int
2756 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2757 {
2758 struct drm_device *dev = crtc->dev;
2759 struct intel_encoder *intel_encoder;
2760 struct intel_dp *intel_dp;
2761
2762 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2763 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2764
2765 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2766 intel_encoder->type == INTEL_OUTPUT_EDP)
2767 return intel_dp->output_reg;
2768 }
2769
2770 return -1;
2771 }
2772
2773 /* check the VBT to see whether the eDP is on DP-D port */
2774 bool intel_dpd_is_edp(struct drm_device *dev)
2775 {
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct child_device_config *p_child;
2778 int i;
2779
2780 if (!dev_priv->child_dev_num)
2781 return false;
2782
2783 for (i = 0; i < dev_priv->child_dev_num; i++) {
2784 p_child = dev_priv->child_dev + i;
2785
2786 if (p_child->dvo_port == PORT_IDPD &&
2787 p_child->device_type == DEVICE_TYPE_eDP)
2788 return true;
2789 }
2790 return false;
2791 }
2792
2793 static void
2794 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2795 {
2796 struct intel_connector *intel_connector = to_intel_connector(connector);
2797
2798 intel_attach_force_audio_property(connector);
2799 intel_attach_broadcast_rgb_property(connector);
2800 intel_dp->color_range_auto = true;
2801
2802 if (is_edp(intel_dp)) {
2803 drm_mode_create_scaling_mode_property(connector->dev);
2804 drm_object_attach_property(
2805 &connector->base,
2806 connector->dev->mode_config.scaling_mode_property,
2807 DRM_MODE_SCALE_ASPECT);
2808 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2809 }
2810 }
2811
2812 static void
2813 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2814 struct intel_dp *intel_dp,
2815 struct edp_power_seq *out)
2816 {
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct edp_power_seq cur, vbt, spec, final;
2819 u32 pp_on, pp_off, pp_div, pp;
2820 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2821
2822 if (HAS_PCH_SPLIT(dev)) {
2823 pp_control_reg = PCH_PP_CONTROL;
2824 pp_on_reg = PCH_PP_ON_DELAYS;
2825 pp_off_reg = PCH_PP_OFF_DELAYS;
2826 pp_div_reg = PCH_PP_DIVISOR;
2827 } else {
2828 pp_control_reg = PIPEA_PP_CONTROL;
2829 pp_on_reg = PIPEA_PP_ON_DELAYS;
2830 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2831 pp_div_reg = PIPEA_PP_DIVISOR;
2832 }
2833
2834 /* Workaround: Need to write PP_CONTROL with the unlock key as
2835 * the very first thing. */
2836 pp = ironlake_get_pp_control(intel_dp);
2837 I915_WRITE(pp_control_reg, pp);
2838
2839 pp_on = I915_READ(pp_on_reg);
2840 pp_off = I915_READ(pp_off_reg);
2841 pp_div = I915_READ(pp_div_reg);
2842
2843 /* Pull timing values out of registers */
2844 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2845 PANEL_POWER_UP_DELAY_SHIFT;
2846
2847 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2848 PANEL_LIGHT_ON_DELAY_SHIFT;
2849
2850 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2851 PANEL_LIGHT_OFF_DELAY_SHIFT;
2852
2853 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2854 PANEL_POWER_DOWN_DELAY_SHIFT;
2855
2856 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2857 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2858
2859 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2860 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2861
2862 vbt = dev_priv->edp.pps;
2863
2864 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2865 * our hw here, which are all in 100usec. */
2866 spec.t1_t3 = 210 * 10;
2867 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2868 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2869 spec.t10 = 500 * 10;
2870 /* This one is special and actually in units of 100ms, but zero
2871 * based in the hw (so we need to add 100 ms). But the sw vbt
2872 * table multiplies it with 1000 to make it in units of 100usec,
2873 * too. */
2874 spec.t11_t12 = (510 + 100) * 10;
2875
2876 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2877 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2878
2879 /* Use the max of the register settings and vbt. If both are
2880 * unset, fall back to the spec limits. */
2881 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2882 spec.field : \
2883 max(cur.field, vbt.field))
2884 assign_final(t1_t3);
2885 assign_final(t8);
2886 assign_final(t9);
2887 assign_final(t10);
2888 assign_final(t11_t12);
2889 #undef assign_final
2890
2891 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2892 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2893 intel_dp->backlight_on_delay = get_delay(t8);
2894 intel_dp->backlight_off_delay = get_delay(t9);
2895 intel_dp->panel_power_down_delay = get_delay(t10);
2896 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2897 #undef get_delay
2898
2899 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2900 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2901 intel_dp->panel_power_cycle_delay);
2902
2903 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2904 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2905
2906 if (out)
2907 *out = final;
2908 }
2909
2910 static void
2911 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2912 struct intel_dp *intel_dp,
2913 struct edp_power_seq *seq)
2914 {
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 u32 pp_on, pp_off, pp_div, port_sel = 0;
2917 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2918 int pp_on_reg, pp_off_reg, pp_div_reg;
2919
2920 if (HAS_PCH_SPLIT(dev)) {
2921 pp_on_reg = PCH_PP_ON_DELAYS;
2922 pp_off_reg = PCH_PP_OFF_DELAYS;
2923 pp_div_reg = PCH_PP_DIVISOR;
2924 } else {
2925 pp_on_reg = PIPEA_PP_ON_DELAYS;
2926 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2927 pp_div_reg = PIPEA_PP_DIVISOR;
2928 }
2929
2930 if (IS_VALLEYVIEW(dev))
2931 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2932
2933 /* And finally store the new values in the power sequencer. */
2934 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2935 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2936 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2937 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2938 /* Compute the divisor for the pp clock, simply match the Bspec
2939 * formula. */
2940 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2941 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2942 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2943
2944 /* Haswell doesn't have any port selection bits for the panel
2945 * power sequencer any more. */
2946 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2947 if (is_cpu_edp(intel_dp))
2948 port_sel = PANEL_POWER_PORT_DP_A;
2949 else
2950 port_sel = PANEL_POWER_PORT_DP_D;
2951 }
2952
2953 pp_on |= port_sel;
2954
2955 I915_WRITE(pp_on_reg, pp_on);
2956 I915_WRITE(pp_off_reg, pp_off);
2957 I915_WRITE(pp_div_reg, pp_div);
2958
2959 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2960 I915_READ(pp_on_reg),
2961 I915_READ(pp_off_reg),
2962 I915_READ(pp_div_reg));
2963 }
2964
2965 void
2966 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2967 struct intel_connector *intel_connector)
2968 {
2969 struct drm_connector *connector = &intel_connector->base;
2970 struct intel_dp *intel_dp = &intel_dig_port->dp;
2971 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2972 struct drm_device *dev = intel_encoder->base.dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974 struct drm_display_mode *fixed_mode = NULL;
2975 struct edp_power_seq power_seq = { 0 };
2976 enum port port = intel_dig_port->port;
2977 const char *name = NULL;
2978 int type;
2979
2980 /* Preserve the current hw state. */
2981 intel_dp->DP = I915_READ(intel_dp->output_reg);
2982 intel_dp->attached_connector = intel_connector;
2983
2984 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2985 if (intel_dpd_is_edp(dev))
2986 intel_dp->is_pch_edp = true;
2987
2988 type = DRM_MODE_CONNECTOR_DisplayPort;
2989 /*
2990 * FIXME : We need to initialize built-in panels before external panels.
2991 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2992 */
2993 switch (port) {
2994 case PORT_A:
2995 type = DRM_MODE_CONNECTOR_eDP;
2996 break;
2997 case PORT_C:
2998 if (IS_VALLEYVIEW(dev))
2999 type = DRM_MODE_CONNECTOR_eDP;
3000 break;
3001 case PORT_D:
3002 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3003 type = DRM_MODE_CONNECTOR_eDP;
3004 break;
3005 default: /* silence GCC warning */
3006 break;
3007 }
3008
3009 /*
3010 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3011 * for DP the encoder type can be set by the caller to
3012 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3013 */
3014 if (type == DRM_MODE_CONNECTOR_eDP)
3015 intel_encoder->type = INTEL_OUTPUT_EDP;
3016
3017 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3018 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3019
3020 connector->interlace_allowed = true;
3021 connector->doublescan_allowed = 0;
3022
3023 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3024 ironlake_panel_vdd_work);
3025
3026 intel_connector_attach_encoder(intel_connector, intel_encoder);
3027 drm_sysfs_connector_add(connector);
3028
3029 if (HAS_DDI(dev))
3030 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3031 else
3032 intel_connector->get_hw_state = intel_connector_get_hw_state;
3033
3034 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3035 if (HAS_DDI(dev)) {
3036 switch (intel_dig_port->port) {
3037 case PORT_A:
3038 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3039 break;
3040 case PORT_B:
3041 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3042 break;
3043 case PORT_C:
3044 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3045 break;
3046 case PORT_D:
3047 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3048 break;
3049 default:
3050 BUG();
3051 }
3052 }
3053
3054 /* Set up the DDC bus. */
3055 switch (port) {
3056 case PORT_A:
3057 intel_encoder->hpd_pin = HPD_PORT_A;
3058 name = "DPDDC-A";
3059 break;
3060 case PORT_B:
3061 intel_encoder->hpd_pin = HPD_PORT_B;
3062 name = "DPDDC-B";
3063 break;
3064 case PORT_C:
3065 intel_encoder->hpd_pin = HPD_PORT_C;
3066 name = "DPDDC-C";
3067 break;
3068 case PORT_D:
3069 intel_encoder->hpd_pin = HPD_PORT_D;
3070 name = "DPDDC-D";
3071 break;
3072 default:
3073 BUG();
3074 }
3075
3076 if (is_edp(intel_dp))
3077 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3078
3079 intel_dp_i2c_init(intel_dp, intel_connector, name);
3080
3081 /* Cache DPCD and EDID for edp. */
3082 if (is_edp(intel_dp)) {
3083 bool ret;
3084 struct drm_display_mode *scan;
3085 struct edid *edid;
3086
3087 ironlake_edp_panel_vdd_on(intel_dp);
3088 ret = intel_dp_get_dpcd(intel_dp);
3089 ironlake_edp_panel_vdd_off(intel_dp, false);
3090
3091 if (ret) {
3092 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3093 dev_priv->no_aux_handshake =
3094 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3095 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3096 } else {
3097 /* if this fails, presume the device is a ghost */
3098 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3099 intel_dp_encoder_destroy(&intel_encoder->base);
3100 intel_dp_destroy(connector);
3101 return;
3102 }
3103
3104 /* We now know it's not a ghost, init power sequence regs. */
3105 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3106 &power_seq);
3107
3108 ironlake_edp_panel_vdd_on(intel_dp);
3109 edid = drm_get_edid(connector, &intel_dp->adapter);
3110 if (edid) {
3111 if (drm_add_edid_modes(connector, edid)) {
3112 drm_mode_connector_update_edid_property(connector, edid);
3113 drm_edid_to_eld(connector, edid);
3114 } else {
3115 kfree(edid);
3116 edid = ERR_PTR(-EINVAL);
3117 }
3118 } else {
3119 edid = ERR_PTR(-ENOENT);
3120 }
3121 intel_connector->edid = edid;
3122
3123 /* prefer fixed mode from EDID if available */
3124 list_for_each_entry(scan, &connector->probed_modes, head) {
3125 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3126 fixed_mode = drm_mode_duplicate(dev, scan);
3127 break;
3128 }
3129 }
3130
3131 /* fallback to VBT if available for eDP */
3132 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3133 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3134 if (fixed_mode)
3135 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3136 }
3137
3138 ironlake_edp_panel_vdd_off(intel_dp, false);
3139 }
3140
3141 if (is_edp(intel_dp)) {
3142 intel_panel_init(&intel_connector->panel, fixed_mode);
3143 intel_panel_setup_backlight(connector);
3144 }
3145
3146 intel_dp_add_properties(intel_dp, connector);
3147
3148 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3149 * 0xd. Failure to do so will result in spurious interrupts being
3150 * generated on the port when a cable is not attached.
3151 */
3152 if (IS_G4X(dev) && !IS_GM45(dev)) {
3153 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3154 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3155 }
3156 }
3157
3158 void
3159 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3160 {
3161 struct intel_digital_port *intel_dig_port;
3162 struct intel_encoder *intel_encoder;
3163 struct drm_encoder *encoder;
3164 struct intel_connector *intel_connector;
3165
3166 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3167 if (!intel_dig_port)
3168 return;
3169
3170 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3171 if (!intel_connector) {
3172 kfree(intel_dig_port);
3173 return;
3174 }
3175
3176 intel_encoder = &intel_dig_port->base;
3177 encoder = &intel_encoder->base;
3178
3179 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3180 DRM_MODE_ENCODER_TMDS);
3181 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3182
3183 intel_encoder->compute_config = intel_dp_compute_config;
3184 intel_encoder->enable = intel_enable_dp;
3185 intel_encoder->pre_enable = intel_pre_enable_dp;
3186 intel_encoder->disable = intel_disable_dp;
3187 intel_encoder->post_disable = intel_post_disable_dp;
3188 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3189 if (IS_VALLEYVIEW(dev))
3190 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3191
3192 intel_dig_port->port = port;
3193 intel_dig_port->dp.output_reg = output_reg;
3194
3195 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3196 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3197 intel_encoder->cloneable = false;
3198 intel_encoder->hot_plug = intel_dp_hot_plug;
3199
3200 intel_dp_init_connector(intel_dig_port, intel_connector);
3201 }
Linux kernel - Deliverables
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