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drm/i915: wait_event_timeout's timeout is in jiffies
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 /**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63 static bool is_pch_edp(struct intel_dp *intel_dp)
64 {
65 return intel_dp->is_pch_edp;
66 }
67
68 /**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
75 {
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 }
78
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80 {
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
84 }
85
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87 {
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
89 }
90
91 /**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99 {
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108 }
109
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
111
112 void
113 intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
115 {
116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
117
118 *lane_num = intel_dp->lane_count;
119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
120 }
121
122 int
123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125 {
126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
127 struct intel_connector *intel_connector = intel_dp->attached_connector;
128
129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
131 else
132 return mode->clock;
133 }
134
135 static int
136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 {
138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149 }
150
151 /*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
168 static int
169 intel_dp_link_required(int pixel_clock, int bpp)
170 {
171 return (pixel_clock * bpp + 9) / 10;
172 }
173
174 static int
175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 {
177 return (max_link_clock * max_lanes * 8) / 10;
178 }
179
180 static bool
181 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
183 bool adjust_mode)
184 {
185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
198 if (adjust_mode)
199 mode->private_flags
200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206 }
207
208 static int
209 intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211 {
212 struct intel_dp *intel_dp = intel_attached_dp(connector);
213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
215
216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
218 return MODE_PANEL;
219
220 if (mode->vdisplay > fixed_mode->vdisplay)
221 return MODE_PANEL;
222 }
223
224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
225 return MODE_CLOCK_HIGH;
226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
233 return MODE_OK;
234 }
235
236 static uint32_t
237 pack_aux(uint8_t *src, int src_bytes)
238 {
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247 }
248
249 static void
250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251 {
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257 }
258
259 /* hrawclock is 1/4 the FSB frequency */
260 static int
261 intel_hrawclk(struct drm_device *dev)
262 {
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291 }
292
293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294 {
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299 }
300
301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302 {
303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307 }
308
309 static void
310 intel_dp_check_edp(struct intel_dp *intel_dp)
311 {
312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
313 struct drm_i915_private *dev_priv = dev->dev_private;
314
315 if (!is_edp(intel_dp))
316 return;
317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS),
321 I915_READ(PCH_PP_CONTROL));
322 }
323 }
324
325 static uint32_t
326 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327 {
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
354 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
357 msecs_to_jiffies(10));
358 else
359 done = wait_for_atomic(C, 10) == 0;
360 if (!done)
361 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 has_aux_irq);
363 #undef C
364
365 return status;
366 }
367
368 static int
369 intel_dp_aux_ch(struct intel_dp *intel_dp,
370 uint8_t *send, int send_bytes,
371 uint8_t *recv, int recv_size)
372 {
373 uint32_t output_reg = intel_dp->output_reg;
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
375 struct drm_device *dev = intel_dig_port->base.base.dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 uint32_t ch_ctl = output_reg + 0x10;
378 uint32_t ch_data = ch_ctl + 4;
379 int i, ret, recv_bytes;
380 uint32_t status;
381 uint32_t aux_clock_divider;
382 int try, precharge;
383 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
384
385 /* dp aux is extremely sensitive to irq latency, hence request the
386 * lowest possible wakeup latency and so prevent the cpu from going into
387 * deep sleep states.
388 */
389 pm_qos_update_request(&dev_priv->pm_qos, 0);
390
391 if (IS_HASWELL(dev)) {
392 switch (intel_dig_port->port) {
393 case PORT_A:
394 ch_ctl = DPA_AUX_CH_CTL;
395 ch_data = DPA_AUX_CH_DATA1;
396 break;
397 case PORT_B:
398 ch_ctl = PCH_DPB_AUX_CH_CTL;
399 ch_data = PCH_DPB_AUX_CH_DATA1;
400 break;
401 case PORT_C:
402 ch_ctl = PCH_DPC_AUX_CH_CTL;
403 ch_data = PCH_DPC_AUX_CH_DATA1;
404 break;
405 case PORT_D:
406 ch_ctl = PCH_DPD_AUX_CH_CTL;
407 ch_data = PCH_DPD_AUX_CH_DATA1;
408 break;
409 default:
410 BUG();
411 }
412 }
413
414 intel_dp_check_edp(intel_dp);
415 /* The clock divider is based off the hrawclk,
416 * and would like to run at 2MHz. So, take the
417 * hrawclk value and divide by 2 and use that
418 *
419 * Note that PCH attached eDP panels should use a 125MHz input
420 * clock divider.
421 */
422 if (is_cpu_edp(intel_dp)) {
423 if (HAS_DDI(dev))
424 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
425 else if (IS_VALLEYVIEW(dev))
426 aux_clock_divider = 100;
427 else if (IS_GEN6(dev) || IS_GEN7(dev))
428 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
429 else
430 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
431 } else if (HAS_PCH_SPLIT(dev))
432 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
433 else
434 aux_clock_divider = intel_hrawclk(dev) / 2;
435
436 if (IS_GEN6(dev))
437 precharge = 3;
438 else
439 precharge = 5;
440
441 /* Try to wait for any previous AUX channel activity */
442 for (try = 0; try < 3; try++) {
443 status = I915_READ_NOTRACE(ch_ctl);
444 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
445 break;
446 msleep(1);
447 }
448
449 if (try == 3) {
450 WARN(1, "dp_aux_ch not started status 0x%08x\n",
451 I915_READ(ch_ctl));
452 ret = -EBUSY;
453 goto out;
454 }
455
456 /* Must try at least 3 times according to DP spec */
457 for (try = 0; try < 5; try++) {
458 /* Load the send data into the aux channel data registers */
459 for (i = 0; i < send_bytes; i += 4)
460 I915_WRITE(ch_data + i,
461 pack_aux(send + i, send_bytes - i));
462
463 /* Send the command and wait for it to complete */
464 I915_WRITE(ch_ctl,
465 DP_AUX_CH_CTL_SEND_BUSY |
466 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
467 DP_AUX_CH_CTL_TIME_OUT_400us |
468 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
469 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
470 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
471 DP_AUX_CH_CTL_DONE |
472 DP_AUX_CH_CTL_TIME_OUT_ERROR |
473 DP_AUX_CH_CTL_RECEIVE_ERROR);
474
475 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
476
477 /* Clear done status and any errors */
478 I915_WRITE(ch_ctl,
479 status |
480 DP_AUX_CH_CTL_DONE |
481 DP_AUX_CH_CTL_TIME_OUT_ERROR |
482 DP_AUX_CH_CTL_RECEIVE_ERROR);
483
484 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
485 DP_AUX_CH_CTL_RECEIVE_ERROR))
486 continue;
487 if (status & DP_AUX_CH_CTL_DONE)
488 break;
489 }
490
491 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
492 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
493 ret = -EBUSY;
494 goto out;
495 }
496
497 /* Check for timeout or receive error.
498 * Timeouts occur when the sink is not connected
499 */
500 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
501 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
502 ret = -EIO;
503 goto out;
504 }
505
506 /* Timeouts occur when the device isn't connected, so they're
507 * "normal" -- don't fill the kernel log with these */
508 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
509 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
510 ret = -ETIMEDOUT;
511 goto out;
512 }
513
514 /* Unload any bytes sent back from the other side */
515 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
516 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
517 if (recv_bytes > recv_size)
518 recv_bytes = recv_size;
519
520 for (i = 0; i < recv_bytes; i += 4)
521 unpack_aux(I915_READ(ch_data + i),
522 recv + i, recv_bytes - i);
523
524 ret = recv_bytes;
525 out:
526 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
527
528 return ret;
529 }
530
531 /* Write data to the aux channel in native mode */
532 static int
533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *send, int send_bytes)
535 {
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
541 intel_dp_check_edp(intel_dp);
542 if (send_bytes > 16)
543 return -1;
544 msg[0] = AUX_NATIVE_WRITE << 4;
545 msg[1] = address >> 8;
546 msg[2] = address & 0xff;
547 msg[3] = send_bytes - 1;
548 memcpy(&msg[4], send, send_bytes);
549 msg_bytes = send_bytes + 4;
550 for (;;) {
551 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
552 if (ret < 0)
553 return ret;
554 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
555 break;
556 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
557 udelay(100);
558 else
559 return -EIO;
560 }
561 return send_bytes;
562 }
563
564 /* Write a single byte to the aux channel in native mode */
565 static int
566 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
567 uint16_t address, uint8_t byte)
568 {
569 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
570 }
571
572 /* read bytes from a native aux channel */
573 static int
574 intel_dp_aux_native_read(struct intel_dp *intel_dp,
575 uint16_t address, uint8_t *recv, int recv_bytes)
576 {
577 uint8_t msg[4];
578 int msg_bytes;
579 uint8_t reply[20];
580 int reply_bytes;
581 uint8_t ack;
582 int ret;
583
584 intel_dp_check_edp(intel_dp);
585 msg[0] = AUX_NATIVE_READ << 4;
586 msg[1] = address >> 8;
587 msg[2] = address & 0xff;
588 msg[3] = recv_bytes - 1;
589
590 msg_bytes = 4;
591 reply_bytes = recv_bytes + 1;
592
593 for (;;) {
594 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
595 reply, reply_bytes);
596 if (ret == 0)
597 return -EPROTO;
598 if (ret < 0)
599 return ret;
600 ack = reply[0];
601 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
602 memcpy(recv, reply + 1, ret - 1);
603 return ret - 1;
604 }
605 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
606 udelay(100);
607 else
608 return -EIO;
609 }
610 }
611
612 static int
613 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
614 uint8_t write_byte, uint8_t *read_byte)
615 {
616 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
617 struct intel_dp *intel_dp = container_of(adapter,
618 struct intel_dp,
619 adapter);
620 uint16_t address = algo_data->address;
621 uint8_t msg[5];
622 uint8_t reply[2];
623 unsigned retry;
624 int msg_bytes;
625 int reply_bytes;
626 int ret;
627
628 intel_dp_check_edp(intel_dp);
629 /* Set up the command byte */
630 if (mode & MODE_I2C_READ)
631 msg[0] = AUX_I2C_READ << 4;
632 else
633 msg[0] = AUX_I2C_WRITE << 4;
634
635 if (!(mode & MODE_I2C_STOP))
636 msg[0] |= AUX_I2C_MOT << 4;
637
638 msg[1] = address >> 8;
639 msg[2] = address;
640
641 switch (mode) {
642 case MODE_I2C_WRITE:
643 msg[3] = 0;
644 msg[4] = write_byte;
645 msg_bytes = 5;
646 reply_bytes = 1;
647 break;
648 case MODE_I2C_READ:
649 msg[3] = 0;
650 msg_bytes = 4;
651 reply_bytes = 2;
652 break;
653 default:
654 msg_bytes = 3;
655 reply_bytes = 1;
656 break;
657 }
658
659 for (retry = 0; retry < 5; retry++) {
660 ret = intel_dp_aux_ch(intel_dp,
661 msg, msg_bytes,
662 reply, reply_bytes);
663 if (ret < 0) {
664 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
665 return ret;
666 }
667
668 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
669 case AUX_NATIVE_REPLY_ACK:
670 /* I2C-over-AUX Reply field is only valid
671 * when paired with AUX ACK.
672 */
673 break;
674 case AUX_NATIVE_REPLY_NACK:
675 DRM_DEBUG_KMS("aux_ch native nack\n");
676 return -EREMOTEIO;
677 case AUX_NATIVE_REPLY_DEFER:
678 udelay(100);
679 continue;
680 default:
681 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
682 reply[0]);
683 return -EREMOTEIO;
684 }
685
686 switch (reply[0] & AUX_I2C_REPLY_MASK) {
687 case AUX_I2C_REPLY_ACK:
688 if (mode == MODE_I2C_READ) {
689 *read_byte = reply[1];
690 }
691 return reply_bytes - 1;
692 case AUX_I2C_REPLY_NACK:
693 DRM_DEBUG_KMS("aux_i2c nack\n");
694 return -EREMOTEIO;
695 case AUX_I2C_REPLY_DEFER:
696 DRM_DEBUG_KMS("aux_i2c defer\n");
697 udelay(100);
698 break;
699 default:
700 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
701 return -EREMOTEIO;
702 }
703 }
704
705 DRM_ERROR("too many retries, giving up\n");
706 return -EREMOTEIO;
707 }
708
709 static int
710 intel_dp_i2c_init(struct intel_dp *intel_dp,
711 struct intel_connector *intel_connector, const char *name)
712 {
713 int ret;
714
715 DRM_DEBUG_KMS("i2c_init %s\n", name);
716 intel_dp->algo.running = false;
717 intel_dp->algo.address = 0;
718 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
719
720 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
721 intel_dp->adapter.owner = THIS_MODULE;
722 intel_dp->adapter.class = I2C_CLASS_DDC;
723 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
724 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
725 intel_dp->adapter.algo_data = &intel_dp->algo;
726 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
727
728 ironlake_edp_panel_vdd_on(intel_dp);
729 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
730 ironlake_edp_panel_vdd_off(intel_dp, false);
731 return ret;
732 }
733
734 bool
735 intel_dp_mode_fixup(struct drm_encoder *encoder,
736 const struct drm_display_mode *mode,
737 struct drm_display_mode *adjusted_mode)
738 {
739 struct drm_device *dev = encoder->dev;
740 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
741 struct intel_connector *intel_connector = intel_dp->attached_connector;
742 int lane_count, clock;
743 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
744 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
745 int bpp, mode_rate;
746 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
747
748 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
749 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
750 adjusted_mode);
751 intel_pch_panel_fitting(dev,
752 intel_connector->panel.fitting_mode,
753 mode, adjusted_mode);
754 }
755
756 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
757 return false;
758
759 DRM_DEBUG_KMS("DP link computation with max lane count %i "
760 "max bw %02x pixel clock %iKHz\n",
761 max_lane_count, bws[max_clock], adjusted_mode->clock);
762
763 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
764 return false;
765
766 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
767
768 if (intel_dp->color_range_auto) {
769 /*
770 * See:
771 * CEA-861-E - 5.1 Default Encoding Parameters
772 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
773 */
774 if (bpp != 18 && drm_mode_cea_vic(adjusted_mode) > 1)
775 intel_dp->color_range = DP_COLOR_RANGE_16_235;
776 else
777 intel_dp->color_range = 0;
778 }
779
780 if (intel_dp->color_range)
781 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
782
783 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
784
785 for (clock = 0; clock <= max_clock; clock++) {
786 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
787 int link_bw_clock =
788 drm_dp_bw_code_to_link_rate(bws[clock]);
789 int link_avail = intel_dp_max_data_rate(link_bw_clock,
790 lane_count);
791
792 if (mode_rate <= link_avail) {
793 intel_dp->link_bw = bws[clock];
794 intel_dp->lane_count = lane_count;
795 adjusted_mode->clock = link_bw_clock;
796 DRM_DEBUG_KMS("DP link bw %02x lane "
797 "count %d clock %d bpp %d\n",
798 intel_dp->link_bw, intel_dp->lane_count,
799 adjusted_mode->clock, bpp);
800 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
801 mode_rate, link_avail);
802 return true;
803 }
804 }
805 }
806
807 return false;
808 }
809
810 void
811 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813 {
814 struct drm_device *dev = crtc->dev;
815 struct intel_encoder *intel_encoder;
816 struct intel_dp *intel_dp;
817 struct drm_i915_private *dev_priv = dev->dev_private;
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
819 int lane_count = 4;
820 struct intel_link_m_n m_n;
821 int pipe = intel_crtc->pipe;
822 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
823
824 /*
825 * Find the lane count in the intel_encoder private
826 */
827 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
828 intel_dp = enc_to_intel_dp(&intel_encoder->base);
829
830 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
831 intel_encoder->type == INTEL_OUTPUT_EDP)
832 {
833 lane_count = intel_dp->lane_count;
834 break;
835 }
836 }
837
838 /*
839 * Compute the GMCH and Link ratios. The '3' here is
840 * the number of bytes_per_pixel post-LUT, which we always
841 * set up for 8-bits of R/G/B, or 3 bytes total.
842 */
843 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
844 mode->clock, adjusted_mode->clock, &m_n);
845
846 if (IS_HASWELL(dev)) {
847 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
848 TU_SIZE(m_n.tu) | m_n.gmch_m);
849 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
850 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
851 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
852 } else if (HAS_PCH_SPLIT(dev)) {
853 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
854 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
855 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
856 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
857 } else if (IS_VALLEYVIEW(dev)) {
858 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
859 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
860 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
861 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
862 } else {
863 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
864 TU_SIZE(m_n.tu) | m_n.gmch_m);
865 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
866 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
867 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
868 }
869 }
870
871 void intel_dp_init_link_config(struct intel_dp *intel_dp)
872 {
873 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
874 intel_dp->link_configuration[0] = intel_dp->link_bw;
875 intel_dp->link_configuration[1] = intel_dp->lane_count;
876 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
877 /*
878 * Check for DPCD version > 1.1 and enhanced framing support
879 */
880 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
881 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
882 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
883 }
884 }
885
886 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
887 {
888 struct drm_device *dev = crtc->dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
890 u32 dpa_ctl;
891
892 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
893 dpa_ctl = I915_READ(DP_A);
894 dpa_ctl &= ~DP_PLL_FREQ_MASK;
895
896 if (clock < 200000) {
897 /* For a long time we've carried around a ILK-DevA w/a for the
898 * 160MHz clock. If we're really unlucky, it's still required.
899 */
900 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
901 dpa_ctl |= DP_PLL_FREQ_160MHZ;
902 } else {
903 dpa_ctl |= DP_PLL_FREQ_270MHZ;
904 }
905
906 I915_WRITE(DP_A, dpa_ctl);
907
908 POSTING_READ(DP_A);
909 udelay(500);
910 }
911
912 static void
913 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
914 struct drm_display_mode *adjusted_mode)
915 {
916 struct drm_device *dev = encoder->dev;
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
919 struct drm_crtc *crtc = encoder->crtc;
920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
921
922 /*
923 * There are four kinds of DP registers:
924 *
925 * IBX PCH
926 * SNB CPU
927 * IVB CPU
928 * CPT PCH
929 *
930 * IBX PCH and CPU are the same for almost everything,
931 * except that the CPU DP PLL is configured in this
932 * register
933 *
934 * CPT PCH is quite different, having many bits moved
935 * to the TRANS_DP_CTL register instead. That
936 * configuration happens (oddly) in ironlake_pch_enable
937 */
938
939 /* Preserve the BIOS-computed detected bit. This is
940 * supposed to be read-only.
941 */
942 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
943
944 /* Handle DP bits in common between all three register formats */
945 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
946
947 switch (intel_dp->lane_count) {
948 case 1:
949 intel_dp->DP |= DP_PORT_WIDTH_1;
950 break;
951 case 2:
952 intel_dp->DP |= DP_PORT_WIDTH_2;
953 break;
954 case 4:
955 intel_dp->DP |= DP_PORT_WIDTH_4;
956 break;
957 }
958 if (intel_dp->has_audio) {
959 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
960 pipe_name(intel_crtc->pipe));
961 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
962 intel_write_eld(encoder, adjusted_mode);
963 }
964
965 intel_dp_init_link_config(intel_dp);
966
967 /* Split out the IBX/CPU vs CPT settings */
968
969 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
970 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
971 intel_dp->DP |= DP_SYNC_HS_HIGH;
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
973 intel_dp->DP |= DP_SYNC_VS_HIGH;
974 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
975
976 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
977 intel_dp->DP |= DP_ENHANCED_FRAMING;
978
979 intel_dp->DP |= intel_crtc->pipe << 29;
980
981 /* don't miss out required setting for eDP */
982 if (adjusted_mode->clock < 200000)
983 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
984 else
985 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
986 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
987 if (!HAS_PCH_SPLIT(dev))
988 intel_dp->DP |= intel_dp->color_range;
989
990 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
991 intel_dp->DP |= DP_SYNC_HS_HIGH;
992 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
993 intel_dp->DP |= DP_SYNC_VS_HIGH;
994 intel_dp->DP |= DP_LINK_TRAIN_OFF;
995
996 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
997 intel_dp->DP |= DP_ENHANCED_FRAMING;
998
999 if (intel_crtc->pipe == 1)
1000 intel_dp->DP |= DP_PIPEB_SELECT;
1001
1002 if (is_cpu_edp(intel_dp)) {
1003 /* don't miss out required setting for eDP */
1004 if (adjusted_mode->clock < 200000)
1005 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1006 else
1007 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1008 }
1009 } else {
1010 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1011 }
1012
1013 if (is_cpu_edp(intel_dp))
1014 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
1015 }
1016
1017 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1018 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1019
1020 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1021 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1022
1023 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1024 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1025
1026 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1027 u32 mask,
1028 u32 value)
1029 {
1030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032
1033 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1034 mask, value,
1035 I915_READ(PCH_PP_STATUS),
1036 I915_READ(PCH_PP_CONTROL));
1037
1038 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1039 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1040 I915_READ(PCH_PP_STATUS),
1041 I915_READ(PCH_PP_CONTROL));
1042 }
1043 }
1044
1045 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046 {
1047 DRM_DEBUG_KMS("Wait for panel power on\n");
1048 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1049 }
1050
1051 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052 {
1053 DRM_DEBUG_KMS("Wait for panel power off time\n");
1054 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055 }
1056
1057 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058 {
1059 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1060 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 }
1062
1063
1064 /* Read the current pp_control value, unlocking the register if it
1065 * is locked
1066 */
1067
1068 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1069 {
1070 u32 control = I915_READ(PCH_PP_CONTROL);
1071
1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1074 return control;
1075 }
1076
1077 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1078 {
1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 u32 pp;
1082
1083 if (!is_edp(intel_dp))
1084 return;
1085 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1086
1087 WARN(intel_dp->want_panel_vdd,
1088 "eDP VDD already requested on\n");
1089
1090 intel_dp->want_panel_vdd = true;
1091
1092 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP VDD already on\n");
1094 return;
1095 }
1096
1097 if (!ironlake_edp_have_panel_power(intel_dp))
1098 ironlake_wait_panel_power_cycle(intel_dp);
1099
1100 pp = ironlake_get_pp_control(dev_priv);
1101 pp |= EDP_FORCE_VDD;
1102 I915_WRITE(PCH_PP_CONTROL, pp);
1103 POSTING_READ(PCH_PP_CONTROL);
1104 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1105 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1106
1107 /*
1108 * If the panel wasn't on, delay before accessing aux channel
1109 */
1110 if (!ironlake_edp_have_panel_power(intel_dp)) {
1111 DRM_DEBUG_KMS("eDP was not running\n");
1112 msleep(intel_dp->panel_power_up_delay);
1113 }
1114 }
1115
1116 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1117 {
1118 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 u32 pp;
1121
1122 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1123
1124 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1125 pp = ironlake_get_pp_control(dev_priv);
1126 pp &= ~EDP_FORCE_VDD;
1127 I915_WRITE(PCH_PP_CONTROL, pp);
1128 POSTING_READ(PCH_PP_CONTROL);
1129
1130 /* Make sure sequencer is idle before allowing subsequent activity */
1131 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1132 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1133
1134 msleep(intel_dp->panel_power_down_delay);
1135 }
1136 }
1137
1138 static void ironlake_panel_vdd_work(struct work_struct *__work)
1139 {
1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1141 struct intel_dp, panel_vdd_work);
1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1143
1144 mutex_lock(&dev->mode_config.mutex);
1145 ironlake_panel_vdd_off_sync(intel_dp);
1146 mutex_unlock(&dev->mode_config.mutex);
1147 }
1148
1149 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1150 {
1151 if (!is_edp(intel_dp))
1152 return;
1153
1154 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1155 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1156
1157 intel_dp->want_panel_vdd = false;
1158
1159 if (sync) {
1160 ironlake_panel_vdd_off_sync(intel_dp);
1161 } else {
1162 /*
1163 * Queue the timer to fire a long
1164 * time from now (relative to the power down delay)
1165 * to keep the panel power up across a sequence of operations
1166 */
1167 schedule_delayed_work(&intel_dp->panel_vdd_work,
1168 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1169 }
1170 }
1171
1172 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1173 {
1174 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 u32 pp;
1177
1178 if (!is_edp(intel_dp))
1179 return;
1180
1181 DRM_DEBUG_KMS("Turn eDP power on\n");
1182
1183 if (ironlake_edp_have_panel_power(intel_dp)) {
1184 DRM_DEBUG_KMS("eDP power already on\n");
1185 return;
1186 }
1187
1188 ironlake_wait_panel_power_cycle(intel_dp);
1189
1190 pp = ironlake_get_pp_control(dev_priv);
1191 if (IS_GEN5(dev)) {
1192 /* ILK workaround: disable reset around power sequence */
1193 pp &= ~PANEL_POWER_RESET;
1194 I915_WRITE(PCH_PP_CONTROL, pp);
1195 POSTING_READ(PCH_PP_CONTROL);
1196 }
1197
1198 pp |= POWER_TARGET_ON;
1199 if (!IS_GEN5(dev))
1200 pp |= PANEL_POWER_RESET;
1201
1202 I915_WRITE(PCH_PP_CONTROL, pp);
1203 POSTING_READ(PCH_PP_CONTROL);
1204
1205 ironlake_wait_panel_on(intel_dp);
1206
1207 if (IS_GEN5(dev)) {
1208 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1209 I915_WRITE(PCH_PP_CONTROL, pp);
1210 POSTING_READ(PCH_PP_CONTROL);
1211 }
1212 }
1213
1214 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1215 {
1216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 u32 pp;
1219
1220 if (!is_edp(intel_dp))
1221 return;
1222
1223 DRM_DEBUG_KMS("Turn eDP power off\n");
1224
1225 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1226
1227 pp = ironlake_get_pp_control(dev_priv);
1228 /* We need to switch off panel power _and_ force vdd, for otherwise some
1229 * panels get very unhappy and cease to work. */
1230 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1231 I915_WRITE(PCH_PP_CONTROL, pp);
1232 POSTING_READ(PCH_PP_CONTROL);
1233
1234 intel_dp->want_panel_vdd = false;
1235
1236 ironlake_wait_panel_off(intel_dp);
1237 }
1238
1239 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1240 {
1241 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242 struct drm_device *dev = intel_dig_port->base.base.dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1245 u32 pp;
1246
1247 if (!is_edp(intel_dp))
1248 return;
1249
1250 DRM_DEBUG_KMS("\n");
1251 /*
1252 * If we enable the backlight right away following a panel power
1253 * on, we may see slight flicker as the panel syncs with the eDP
1254 * link. So delay a bit to make sure the image is solid before
1255 * allowing it to appear.
1256 */
1257 msleep(intel_dp->backlight_on_delay);
1258 pp = ironlake_get_pp_control(dev_priv);
1259 pp |= EDP_BLC_ENABLE;
1260 I915_WRITE(PCH_PP_CONTROL, pp);
1261 POSTING_READ(PCH_PP_CONTROL);
1262
1263 intel_panel_enable_backlight(dev, pipe);
1264 }
1265
1266 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1267 {
1268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 u32 pp;
1271
1272 if (!is_edp(intel_dp))
1273 return;
1274
1275 intel_panel_disable_backlight(dev);
1276
1277 DRM_DEBUG_KMS("\n");
1278 pp = ironlake_get_pp_control(dev_priv);
1279 pp &= ~EDP_BLC_ENABLE;
1280 I915_WRITE(PCH_PP_CONTROL, pp);
1281 POSTING_READ(PCH_PP_CONTROL);
1282 msleep(intel_dp->backlight_off_delay);
1283 }
1284
1285 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1286 {
1287 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1288 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1289 struct drm_device *dev = crtc->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 u32 dpa_ctl;
1292
1293 assert_pipe_disabled(dev_priv,
1294 to_intel_crtc(crtc)->pipe);
1295
1296 DRM_DEBUG_KMS("\n");
1297 dpa_ctl = I915_READ(DP_A);
1298 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1299 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1300
1301 /* We don't adjust intel_dp->DP while tearing down the link, to
1302 * facilitate link retraining (e.g. after hotplug). Hence clear all
1303 * enable bits here to ensure that we don't enable too much. */
1304 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1305 intel_dp->DP |= DP_PLL_ENABLE;
1306 I915_WRITE(DP_A, intel_dp->DP);
1307 POSTING_READ(DP_A);
1308 udelay(200);
1309 }
1310
1311 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1312 {
1313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1314 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1315 struct drm_device *dev = crtc->dev;
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 u32 dpa_ctl;
1318
1319 assert_pipe_disabled(dev_priv,
1320 to_intel_crtc(crtc)->pipe);
1321
1322 dpa_ctl = I915_READ(DP_A);
1323 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1324 "dp pll off, should be on\n");
1325 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1326
1327 /* We can't rely on the value tracked for the DP register in
1328 * intel_dp->DP because link_down must not change that (otherwise link
1329 * re-training will fail. */
1330 dpa_ctl &= ~DP_PLL_ENABLE;
1331 I915_WRITE(DP_A, dpa_ctl);
1332 POSTING_READ(DP_A);
1333 udelay(200);
1334 }
1335
1336 /* If the sink supports it, try to set the power state appropriately */
1337 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1338 {
1339 int ret, i;
1340
1341 /* Should have a valid DPCD by this point */
1342 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1343 return;
1344
1345 if (mode != DRM_MODE_DPMS_ON) {
1346 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1347 DP_SET_POWER_D3);
1348 if (ret != 1)
1349 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1350 } else {
1351 /*
1352 * When turning on, we need to retry for 1ms to give the sink
1353 * time to wake up.
1354 */
1355 for (i = 0; i < 3; i++) {
1356 ret = intel_dp_aux_native_write_1(intel_dp,
1357 DP_SET_POWER,
1358 DP_SET_POWER_D0);
1359 if (ret == 1)
1360 break;
1361 msleep(1);
1362 }
1363 }
1364 }
1365
1366 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1367 enum pipe *pipe)
1368 {
1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370 struct drm_device *dev = encoder->base.dev;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 u32 tmp = I915_READ(intel_dp->output_reg);
1373
1374 if (!(tmp & DP_PORT_EN))
1375 return false;
1376
1377 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1378 *pipe = PORT_TO_PIPE_CPT(tmp);
1379 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1380 *pipe = PORT_TO_PIPE(tmp);
1381 } else {
1382 u32 trans_sel;
1383 u32 trans_dp;
1384 int i;
1385
1386 switch (intel_dp->output_reg) {
1387 case PCH_DP_B:
1388 trans_sel = TRANS_DP_PORT_SEL_B;
1389 break;
1390 case PCH_DP_C:
1391 trans_sel = TRANS_DP_PORT_SEL_C;
1392 break;
1393 case PCH_DP_D:
1394 trans_sel = TRANS_DP_PORT_SEL_D;
1395 break;
1396 default:
1397 return true;
1398 }
1399
1400 for_each_pipe(i) {
1401 trans_dp = I915_READ(TRANS_DP_CTL(i));
1402 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1403 *pipe = i;
1404 return true;
1405 }
1406 }
1407
1408 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1409 intel_dp->output_reg);
1410 }
1411
1412 return true;
1413 }
1414
1415 static void intel_disable_dp(struct intel_encoder *encoder)
1416 {
1417 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1418
1419 /* Make sure the panel is off before trying to change the mode. But also
1420 * ensure that we have vdd while we switch off the panel. */
1421 ironlake_edp_panel_vdd_on(intel_dp);
1422 ironlake_edp_backlight_off(intel_dp);
1423 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1424 ironlake_edp_panel_off(intel_dp);
1425
1426 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1427 if (!is_cpu_edp(intel_dp))
1428 intel_dp_link_down(intel_dp);
1429 }
1430
1431 static void intel_post_disable_dp(struct intel_encoder *encoder)
1432 {
1433 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1434
1435 if (is_cpu_edp(intel_dp)) {
1436 intel_dp_link_down(intel_dp);
1437 ironlake_edp_pll_off(intel_dp);
1438 }
1439 }
1440
1441 static void intel_enable_dp(struct intel_encoder *encoder)
1442 {
1443 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1447
1448 if (WARN_ON(dp_reg & DP_PORT_EN))
1449 return;
1450
1451 ironlake_edp_panel_vdd_on(intel_dp);
1452 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1453 intel_dp_start_link_train(intel_dp);
1454 ironlake_edp_panel_on(intel_dp);
1455 ironlake_edp_panel_vdd_off(intel_dp, true);
1456 intel_dp_complete_link_train(intel_dp);
1457 ironlake_edp_backlight_on(intel_dp);
1458 }
1459
1460 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1461 {
1462 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1463
1464 if (is_cpu_edp(intel_dp))
1465 ironlake_edp_pll_on(intel_dp);
1466 }
1467
1468 /*
1469 * Native read with retry for link status and receiver capability reads for
1470 * cases where the sink may still be asleep.
1471 */
1472 static bool
1473 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1474 uint8_t *recv, int recv_bytes)
1475 {
1476 int ret, i;
1477
1478 /*
1479 * Sinks are *supposed* to come up within 1ms from an off state,
1480 * but we're also supposed to retry 3 times per the spec.
1481 */
1482 for (i = 0; i < 3; i++) {
1483 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1484 recv_bytes);
1485 if (ret == recv_bytes)
1486 return true;
1487 msleep(1);
1488 }
1489
1490 return false;
1491 }
1492
1493 /*
1494 * Fetch AUX CH registers 0x202 - 0x207 which contain
1495 * link status information
1496 */
1497 static bool
1498 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1499 {
1500 return intel_dp_aux_native_read_retry(intel_dp,
1501 DP_LANE0_1_STATUS,
1502 link_status,
1503 DP_LINK_STATUS_SIZE);
1504 }
1505
1506 #if 0
1507 static char *voltage_names[] = {
1508 "0.4V", "0.6V", "0.8V", "1.2V"
1509 };
1510 static char *pre_emph_names[] = {
1511 "0dB", "3.5dB", "6dB", "9.5dB"
1512 };
1513 static char *link_train_names[] = {
1514 "pattern 1", "pattern 2", "idle", "off"
1515 };
1516 #endif
1517
1518 /*
1519 * These are source-specific values; current Intel hardware supports
1520 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1521 */
1522
1523 static uint8_t
1524 intel_dp_voltage_max(struct intel_dp *intel_dp)
1525 {
1526 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1527
1528 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1529 return DP_TRAIN_VOLTAGE_SWING_800;
1530 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1531 return DP_TRAIN_VOLTAGE_SWING_1200;
1532 else
1533 return DP_TRAIN_VOLTAGE_SWING_800;
1534 }
1535
1536 static uint8_t
1537 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1538 {
1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1540
1541 if (IS_HASWELL(dev)) {
1542 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1543 case DP_TRAIN_VOLTAGE_SWING_400:
1544 return DP_TRAIN_PRE_EMPHASIS_9_5;
1545 case DP_TRAIN_VOLTAGE_SWING_600:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_800:
1548 return DP_TRAIN_PRE_EMPHASIS_3_5;
1549 case DP_TRAIN_VOLTAGE_SWING_1200:
1550 default:
1551 return DP_TRAIN_PRE_EMPHASIS_0;
1552 }
1553 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1554 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1555 case DP_TRAIN_VOLTAGE_SWING_400:
1556 return DP_TRAIN_PRE_EMPHASIS_6;
1557 case DP_TRAIN_VOLTAGE_SWING_600:
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 return DP_TRAIN_PRE_EMPHASIS_3_5;
1560 default:
1561 return DP_TRAIN_PRE_EMPHASIS_0;
1562 }
1563 } else {
1564 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1565 case DP_TRAIN_VOLTAGE_SWING_400:
1566 return DP_TRAIN_PRE_EMPHASIS_6;
1567 case DP_TRAIN_VOLTAGE_SWING_600:
1568 return DP_TRAIN_PRE_EMPHASIS_6;
1569 case DP_TRAIN_VOLTAGE_SWING_800:
1570 return DP_TRAIN_PRE_EMPHASIS_3_5;
1571 case DP_TRAIN_VOLTAGE_SWING_1200:
1572 default:
1573 return DP_TRAIN_PRE_EMPHASIS_0;
1574 }
1575 }
1576 }
1577
1578 static void
1579 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1580 {
1581 uint8_t v = 0;
1582 uint8_t p = 0;
1583 int lane;
1584 uint8_t voltage_max;
1585 uint8_t preemph_max;
1586
1587 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1588 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1589 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1590
1591 if (this_v > v)
1592 v = this_v;
1593 if (this_p > p)
1594 p = this_p;
1595 }
1596
1597 voltage_max = intel_dp_voltage_max(intel_dp);
1598 if (v >= voltage_max)
1599 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1600
1601 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1602 if (p >= preemph_max)
1603 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1604
1605 for (lane = 0; lane < 4; lane++)
1606 intel_dp->train_set[lane] = v | p;
1607 }
1608
1609 static uint32_t
1610 intel_gen4_signal_levels(uint8_t train_set)
1611 {
1612 uint32_t signal_levels = 0;
1613
1614 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1615 case DP_TRAIN_VOLTAGE_SWING_400:
1616 default:
1617 signal_levels |= DP_VOLTAGE_0_4;
1618 break;
1619 case DP_TRAIN_VOLTAGE_SWING_600:
1620 signal_levels |= DP_VOLTAGE_0_6;
1621 break;
1622 case DP_TRAIN_VOLTAGE_SWING_800:
1623 signal_levels |= DP_VOLTAGE_0_8;
1624 break;
1625 case DP_TRAIN_VOLTAGE_SWING_1200:
1626 signal_levels |= DP_VOLTAGE_1_2;
1627 break;
1628 }
1629 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1630 case DP_TRAIN_PRE_EMPHASIS_0:
1631 default:
1632 signal_levels |= DP_PRE_EMPHASIS_0;
1633 break;
1634 case DP_TRAIN_PRE_EMPHASIS_3_5:
1635 signal_levels |= DP_PRE_EMPHASIS_3_5;
1636 break;
1637 case DP_TRAIN_PRE_EMPHASIS_6:
1638 signal_levels |= DP_PRE_EMPHASIS_6;
1639 break;
1640 case DP_TRAIN_PRE_EMPHASIS_9_5:
1641 signal_levels |= DP_PRE_EMPHASIS_9_5;
1642 break;
1643 }
1644 return signal_levels;
1645 }
1646
1647 /* Gen6's DP voltage swing and pre-emphasis control */
1648 static uint32_t
1649 intel_gen6_edp_signal_levels(uint8_t train_set)
1650 {
1651 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1652 DP_TRAIN_PRE_EMPHASIS_MASK);
1653 switch (signal_levels) {
1654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1656 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1657 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1659 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1661 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1662 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1664 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1665 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1666 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1667 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1668 default:
1669 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1670 "0x%x\n", signal_levels);
1671 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1672 }
1673 }
1674
1675 /* Gen7's DP voltage swing and pre-emphasis control */
1676 static uint32_t
1677 intel_gen7_edp_signal_levels(uint8_t train_set)
1678 {
1679 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1680 DP_TRAIN_PRE_EMPHASIS_MASK);
1681 switch (signal_levels) {
1682 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1683 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1684 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1685 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1686 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1687 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1688
1689 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1690 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1691 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1692 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1693
1694 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1695 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1696 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1697 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1698
1699 default:
1700 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1701 "0x%x\n", signal_levels);
1702 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1703 }
1704 }
1705
1706 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1707 static uint32_t
1708 intel_hsw_signal_levels(uint8_t train_set)
1709 {
1710 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1711 DP_TRAIN_PRE_EMPHASIS_MASK);
1712 switch (signal_levels) {
1713 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1714 return DDI_BUF_EMP_400MV_0DB_HSW;
1715 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1716 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1717 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1718 return DDI_BUF_EMP_400MV_6DB_HSW;
1719 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1720 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1721
1722 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1723 return DDI_BUF_EMP_600MV_0DB_HSW;
1724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1725 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1726 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1727 return DDI_BUF_EMP_600MV_6DB_HSW;
1728
1729 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1730 return DDI_BUF_EMP_800MV_0DB_HSW;
1731 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1732 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1733 default:
1734 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1735 "0x%x\n", signal_levels);
1736 return DDI_BUF_EMP_400MV_0DB_HSW;
1737 }
1738 }
1739
1740 /* Properly updates "DP" with the correct signal levels. */
1741 static void
1742 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1743 {
1744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1745 struct drm_device *dev = intel_dig_port->base.base.dev;
1746 uint32_t signal_levels, mask;
1747 uint8_t train_set = intel_dp->train_set[0];
1748
1749 if (IS_HASWELL(dev)) {
1750 signal_levels = intel_hsw_signal_levels(train_set);
1751 mask = DDI_BUF_EMP_MASK;
1752 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1753 signal_levels = intel_gen7_edp_signal_levels(train_set);
1754 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1755 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1756 signal_levels = intel_gen6_edp_signal_levels(train_set);
1757 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1758 } else {
1759 signal_levels = intel_gen4_signal_levels(train_set);
1760 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1761 }
1762
1763 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1764
1765 *DP = (*DP & ~mask) | signal_levels;
1766 }
1767
1768 static bool
1769 intel_dp_set_link_train(struct intel_dp *intel_dp,
1770 uint32_t dp_reg_value,
1771 uint8_t dp_train_pat)
1772 {
1773 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1774 struct drm_device *dev = intel_dig_port->base.base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 enum port port = intel_dig_port->port;
1777 int ret;
1778 uint32_t temp;
1779
1780 if (IS_HASWELL(dev)) {
1781 temp = I915_READ(DP_TP_CTL(port));
1782
1783 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1784 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1785 else
1786 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1787
1788 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1789 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790 case DP_TRAINING_PATTERN_DISABLE:
1791
1792 if (port != PORT_A) {
1793 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1794 I915_WRITE(DP_TP_CTL(port), temp);
1795
1796 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1797 DP_TP_STATUS_IDLE_DONE), 1))
1798 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1799
1800 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1801 }
1802
1803 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1804
1805 break;
1806 case DP_TRAINING_PATTERN_1:
1807 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1808 break;
1809 case DP_TRAINING_PATTERN_2:
1810 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1811 break;
1812 case DP_TRAINING_PATTERN_3:
1813 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1814 break;
1815 }
1816 I915_WRITE(DP_TP_CTL(port), temp);
1817
1818 } else if (HAS_PCH_CPT(dev) &&
1819 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1820 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1821
1822 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1823 case DP_TRAINING_PATTERN_DISABLE:
1824 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1825 break;
1826 case DP_TRAINING_PATTERN_1:
1827 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1828 break;
1829 case DP_TRAINING_PATTERN_2:
1830 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1831 break;
1832 case DP_TRAINING_PATTERN_3:
1833 DRM_ERROR("DP training pattern 3 not supported\n");
1834 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1835 break;
1836 }
1837
1838 } else {
1839 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1840
1841 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1842 case DP_TRAINING_PATTERN_DISABLE:
1843 dp_reg_value |= DP_LINK_TRAIN_OFF;
1844 break;
1845 case DP_TRAINING_PATTERN_1:
1846 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1847 break;
1848 case DP_TRAINING_PATTERN_2:
1849 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1850 break;
1851 case DP_TRAINING_PATTERN_3:
1852 DRM_ERROR("DP training pattern 3 not supported\n");
1853 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1854 break;
1855 }
1856 }
1857
1858 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1859 POSTING_READ(intel_dp->output_reg);
1860
1861 intel_dp_aux_native_write_1(intel_dp,
1862 DP_TRAINING_PATTERN_SET,
1863 dp_train_pat);
1864
1865 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1866 DP_TRAINING_PATTERN_DISABLE) {
1867 ret = intel_dp_aux_native_write(intel_dp,
1868 DP_TRAINING_LANE0_SET,
1869 intel_dp->train_set,
1870 intel_dp->lane_count);
1871 if (ret != intel_dp->lane_count)
1872 return false;
1873 }
1874
1875 return true;
1876 }
1877
1878 /* Enable corresponding port and start training pattern 1 */
1879 void
1880 intel_dp_start_link_train(struct intel_dp *intel_dp)
1881 {
1882 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1883 struct drm_device *dev = encoder->dev;
1884 int i;
1885 uint8_t voltage;
1886 bool clock_recovery = false;
1887 int voltage_tries, loop_tries;
1888 uint32_t DP = intel_dp->DP;
1889
1890 if (HAS_DDI(dev))
1891 intel_ddi_prepare_link_retrain(encoder);
1892
1893 /* Write the link configuration data */
1894 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1895 intel_dp->link_configuration,
1896 DP_LINK_CONFIGURATION_SIZE);
1897
1898 DP |= DP_PORT_EN;
1899
1900 memset(intel_dp->train_set, 0, 4);
1901 voltage = 0xff;
1902 voltage_tries = 0;
1903 loop_tries = 0;
1904 clock_recovery = false;
1905 for (;;) {
1906 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1907 uint8_t link_status[DP_LINK_STATUS_SIZE];
1908
1909 intel_dp_set_signal_levels(intel_dp, &DP);
1910
1911 /* Set training pattern 1 */
1912 if (!intel_dp_set_link_train(intel_dp, DP,
1913 DP_TRAINING_PATTERN_1 |
1914 DP_LINK_SCRAMBLING_DISABLE))
1915 break;
1916
1917 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1918 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1919 DRM_ERROR("failed to get link status\n");
1920 break;
1921 }
1922
1923 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1924 DRM_DEBUG_KMS("clock recovery OK\n");
1925 clock_recovery = true;
1926 break;
1927 }
1928
1929 /* Check to see if we've tried the max voltage */
1930 for (i = 0; i < intel_dp->lane_count; i++)
1931 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1932 break;
1933 if (i == intel_dp->lane_count && voltage_tries == 5) {
1934 ++loop_tries;
1935 if (loop_tries == 5) {
1936 DRM_DEBUG_KMS("too many full retries, give up\n");
1937 break;
1938 }
1939 memset(intel_dp->train_set, 0, 4);
1940 voltage_tries = 0;
1941 continue;
1942 }
1943
1944 /* Check to see if we've tried the same voltage 5 times */
1945 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1946 ++voltage_tries;
1947 if (voltage_tries == 5) {
1948 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1949 break;
1950 }
1951 } else
1952 voltage_tries = 0;
1953 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1954
1955 /* Compute new intel_dp->train_set as requested by target */
1956 intel_get_adjust_train(intel_dp, link_status);
1957 }
1958
1959 intel_dp->DP = DP;
1960 }
1961
1962 void
1963 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1964 {
1965 bool channel_eq = false;
1966 int tries, cr_tries;
1967 uint32_t DP = intel_dp->DP;
1968
1969 /* channel equalization */
1970 tries = 0;
1971 cr_tries = 0;
1972 channel_eq = false;
1973 for (;;) {
1974 uint8_t link_status[DP_LINK_STATUS_SIZE];
1975
1976 if (cr_tries > 5) {
1977 DRM_ERROR("failed to train DP, aborting\n");
1978 intel_dp_link_down(intel_dp);
1979 break;
1980 }
1981
1982 intel_dp_set_signal_levels(intel_dp, &DP);
1983
1984 /* channel eq pattern */
1985 if (!intel_dp_set_link_train(intel_dp, DP,
1986 DP_TRAINING_PATTERN_2 |
1987 DP_LINK_SCRAMBLING_DISABLE))
1988 break;
1989
1990 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1991 if (!intel_dp_get_link_status(intel_dp, link_status))
1992 break;
1993
1994 /* Make sure clock is still ok */
1995 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1996 intel_dp_start_link_train(intel_dp);
1997 cr_tries++;
1998 continue;
1999 }
2000
2001 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2002 channel_eq = true;
2003 break;
2004 }
2005
2006 /* Try 5 times, then try clock recovery if that fails */
2007 if (tries > 5) {
2008 intel_dp_link_down(intel_dp);
2009 intel_dp_start_link_train(intel_dp);
2010 tries = 0;
2011 cr_tries++;
2012 continue;
2013 }
2014
2015 /* Compute new intel_dp->train_set as requested by target */
2016 intel_get_adjust_train(intel_dp, link_status);
2017 ++tries;
2018 }
2019
2020 if (channel_eq)
2021 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2022
2023 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2024 }
2025
2026 static void
2027 intel_dp_link_down(struct intel_dp *intel_dp)
2028 {
2029 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2030 struct drm_device *dev = intel_dig_port->base.base.dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct intel_crtc *intel_crtc =
2033 to_intel_crtc(intel_dig_port->base.base.crtc);
2034 uint32_t DP = intel_dp->DP;
2035
2036 /*
2037 * DDI code has a strict mode set sequence and we should try to respect
2038 * it, otherwise we might hang the machine in many different ways. So we
2039 * really should be disabling the port only on a complete crtc_disable
2040 * sequence. This function is just called under two conditions on DDI
2041 * code:
2042 * - Link train failed while doing crtc_enable, and on this case we
2043 * really should respect the mode set sequence and wait for a
2044 * crtc_disable.
2045 * - Someone turned the monitor off and intel_dp_check_link_status
2046 * called us. We don't need to disable the whole port on this case, so
2047 * when someone turns the monitor on again,
2048 * intel_ddi_prepare_link_retrain will take care of redoing the link
2049 * train.
2050 */
2051 if (HAS_DDI(dev))
2052 return;
2053
2054 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2055 return;
2056
2057 DRM_DEBUG_KMS("\n");
2058
2059 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2060 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2061 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2062 } else {
2063 DP &= ~DP_LINK_TRAIN_MASK;
2064 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2065 }
2066 POSTING_READ(intel_dp->output_reg);
2067
2068 /* We don't really know why we're doing this */
2069 intel_wait_for_vblank(dev, intel_crtc->pipe);
2070
2071 if (HAS_PCH_IBX(dev) &&
2072 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2073 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2074
2075 /* Hardware workaround: leaving our transcoder select
2076 * set to transcoder B while it's off will prevent the
2077 * corresponding HDMI output on transcoder A.
2078 *
2079 * Combine this with another hardware workaround:
2080 * transcoder select bit can only be cleared while the
2081 * port is enabled.
2082 */
2083 DP &= ~DP_PIPEB_SELECT;
2084 I915_WRITE(intel_dp->output_reg, DP);
2085
2086 /* Changes to enable or select take place the vblank
2087 * after being written.
2088 */
2089 if (WARN_ON(crtc == NULL)) {
2090 /* We should never try to disable a port without a crtc
2091 * attached. For paranoia keep the code around for a
2092 * bit. */
2093 POSTING_READ(intel_dp->output_reg);
2094 msleep(50);
2095 } else
2096 intel_wait_for_vblank(dev, intel_crtc->pipe);
2097 }
2098
2099 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2100 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2101 POSTING_READ(intel_dp->output_reg);
2102 msleep(intel_dp->panel_power_down_delay);
2103 }
2104
2105 static bool
2106 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2107 {
2108 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2109
2110 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2111 sizeof(intel_dp->dpcd)) == 0)
2112 return false; /* aux transfer failed */
2113
2114 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2115 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2116 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2117
2118 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2119 return false; /* DPCD not present */
2120
2121 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2122 DP_DWN_STRM_PORT_PRESENT))
2123 return true; /* native DP sink */
2124
2125 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2126 return true; /* no per-port downstream info */
2127
2128 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2129 intel_dp->downstream_ports,
2130 DP_MAX_DOWNSTREAM_PORTS) == 0)
2131 return false; /* downstream port status fetch failed */
2132
2133 return true;
2134 }
2135
2136 static void
2137 intel_dp_probe_oui(struct intel_dp *intel_dp)
2138 {
2139 u8 buf[3];
2140
2141 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2142 return;
2143
2144 ironlake_edp_panel_vdd_on(intel_dp);
2145
2146 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2147 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2148 buf[0], buf[1], buf[2]);
2149
2150 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2151 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2152 buf[0], buf[1], buf[2]);
2153
2154 ironlake_edp_panel_vdd_off(intel_dp, false);
2155 }
2156
2157 static bool
2158 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2159 {
2160 int ret;
2161
2162 ret = intel_dp_aux_native_read_retry(intel_dp,
2163 DP_DEVICE_SERVICE_IRQ_VECTOR,
2164 sink_irq_vector, 1);
2165 if (!ret)
2166 return false;
2167
2168 return true;
2169 }
2170
2171 static void
2172 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2173 {
2174 /* NAK by default */
2175 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2176 }
2177
2178 /*
2179 * According to DP spec
2180 * 5.1.2:
2181 * 1. Read DPCD
2182 * 2. Configure link according to Receiver Capabilities
2183 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2184 * 4. Check link status on receipt of hot-plug interrupt
2185 */
2186
2187 void
2188 intel_dp_check_link_status(struct intel_dp *intel_dp)
2189 {
2190 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2191 u8 sink_irq_vector;
2192 u8 link_status[DP_LINK_STATUS_SIZE];
2193
2194 if (!intel_encoder->connectors_active)
2195 return;
2196
2197 if (WARN_ON(!intel_encoder->base.crtc))
2198 return;
2199
2200 /* Try to read receiver status if the link appears to be up */
2201 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2202 intel_dp_link_down(intel_dp);
2203 return;
2204 }
2205
2206 /* Now read the DPCD to see if it's actually running */
2207 if (!intel_dp_get_dpcd(intel_dp)) {
2208 intel_dp_link_down(intel_dp);
2209 return;
2210 }
2211
2212 /* Try to read the source of the interrupt */
2213 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2214 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2215 /* Clear interrupt source */
2216 intel_dp_aux_native_write_1(intel_dp,
2217 DP_DEVICE_SERVICE_IRQ_VECTOR,
2218 sink_irq_vector);
2219
2220 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2221 intel_dp_handle_test_request(intel_dp);
2222 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2223 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2224 }
2225
2226 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2227 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2228 drm_get_encoder_name(&intel_encoder->base));
2229 intel_dp_start_link_train(intel_dp);
2230 intel_dp_complete_link_train(intel_dp);
2231 }
2232 }
2233
2234 /* XXX this is probably wrong for multiple downstream ports */
2235 static enum drm_connector_status
2236 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2237 {
2238 uint8_t *dpcd = intel_dp->dpcd;
2239 bool hpd;
2240 uint8_t type;
2241
2242 if (!intel_dp_get_dpcd(intel_dp))
2243 return connector_status_disconnected;
2244
2245 /* if there's no downstream port, we're done */
2246 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2247 return connector_status_connected;
2248
2249 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2250 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2251 if (hpd) {
2252 uint8_t reg;
2253 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2254 &reg, 1))
2255 return connector_status_unknown;
2256 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2257 : connector_status_disconnected;
2258 }
2259
2260 /* If no HPD, poke DDC gently */
2261 if (drm_probe_ddc(&intel_dp->adapter))
2262 return connector_status_connected;
2263
2264 /* Well we tried, say unknown for unreliable port types */
2265 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2266 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2267 return connector_status_unknown;
2268
2269 /* Anything else is out of spec, warn and ignore */
2270 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2271 return connector_status_disconnected;
2272 }
2273
2274 static enum drm_connector_status
2275 ironlake_dp_detect(struct intel_dp *intel_dp)
2276 {
2277 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2280 enum drm_connector_status status;
2281
2282 /* Can't disconnect eDP, but you can close the lid... */
2283 if (is_edp(intel_dp)) {
2284 status = intel_panel_detect(dev);
2285 if (status == connector_status_unknown)
2286 status = connector_status_connected;
2287 return status;
2288 }
2289
2290 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2291 return connector_status_disconnected;
2292
2293 return intel_dp_detect_dpcd(intel_dp);
2294 }
2295
2296 static enum drm_connector_status
2297 g4x_dp_detect(struct intel_dp *intel_dp)
2298 {
2299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2302 uint32_t bit;
2303
2304 switch (intel_dig_port->port) {
2305 case PORT_B:
2306 bit = PORTB_HOTPLUG_LIVE_STATUS;
2307 break;
2308 case PORT_C:
2309 bit = PORTC_HOTPLUG_LIVE_STATUS;
2310 break;
2311 case PORT_D:
2312 bit = PORTD_HOTPLUG_LIVE_STATUS;
2313 break;
2314 default:
2315 return connector_status_unknown;
2316 }
2317
2318 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2319 return connector_status_disconnected;
2320
2321 return intel_dp_detect_dpcd(intel_dp);
2322 }
2323
2324 static struct edid *
2325 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2326 {
2327 struct intel_connector *intel_connector = to_intel_connector(connector);
2328
2329 /* use cached edid if we have one */
2330 if (intel_connector->edid) {
2331 struct edid *edid;
2332 int size;
2333
2334 /* invalid edid */
2335 if (IS_ERR(intel_connector->edid))
2336 return NULL;
2337
2338 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2339 edid = kmalloc(size, GFP_KERNEL);
2340 if (!edid)
2341 return NULL;
2342
2343 memcpy(edid, intel_connector->edid, size);
2344 return edid;
2345 }
2346
2347 return drm_get_edid(connector, adapter);
2348 }
2349
2350 static int
2351 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2352 {
2353 struct intel_connector *intel_connector = to_intel_connector(connector);
2354
2355 /* use cached edid if we have one */
2356 if (intel_connector->edid) {
2357 /* invalid edid */
2358 if (IS_ERR(intel_connector->edid))
2359 return 0;
2360
2361 return intel_connector_update_modes(connector,
2362 intel_connector->edid);
2363 }
2364
2365 return intel_ddc_get_modes(connector, adapter);
2366 }
2367
2368 static enum drm_connector_status
2369 intel_dp_detect(struct drm_connector *connector, bool force)
2370 {
2371 struct intel_dp *intel_dp = intel_attached_dp(connector);
2372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2373 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2374 struct drm_device *dev = connector->dev;
2375 enum drm_connector_status status;
2376 struct edid *edid = NULL;
2377
2378 intel_dp->has_audio = false;
2379
2380 if (HAS_PCH_SPLIT(dev))
2381 status = ironlake_dp_detect(intel_dp);
2382 else
2383 status = g4x_dp_detect(intel_dp);
2384
2385 if (status != connector_status_connected)
2386 return status;
2387
2388 intel_dp_probe_oui(intel_dp);
2389
2390 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2391 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2392 } else {
2393 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2394 if (edid) {
2395 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2396 kfree(edid);
2397 }
2398 }
2399
2400 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2401 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2402 return connector_status_connected;
2403 }
2404
2405 static int intel_dp_get_modes(struct drm_connector *connector)
2406 {
2407 struct intel_dp *intel_dp = intel_attached_dp(connector);
2408 struct intel_connector *intel_connector = to_intel_connector(connector);
2409 struct drm_device *dev = connector->dev;
2410 int ret;
2411
2412 /* We should parse the EDID data and find out if it has an audio sink
2413 */
2414
2415 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2416 if (ret)
2417 return ret;
2418
2419 /* if eDP has no EDID, fall back to fixed mode */
2420 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2421 struct drm_display_mode *mode;
2422 mode = drm_mode_duplicate(dev,
2423 intel_connector->panel.fixed_mode);
2424 if (mode) {
2425 drm_mode_probed_add(connector, mode);
2426 return 1;
2427 }
2428 }
2429 return 0;
2430 }
2431
2432 static bool
2433 intel_dp_detect_audio(struct drm_connector *connector)
2434 {
2435 struct intel_dp *intel_dp = intel_attached_dp(connector);
2436 struct edid *edid;
2437 bool has_audio = false;
2438
2439 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2440 if (edid) {
2441 has_audio = drm_detect_monitor_audio(edid);
2442 kfree(edid);
2443 }
2444
2445 return has_audio;
2446 }
2447
2448 static int
2449 intel_dp_set_property(struct drm_connector *connector,
2450 struct drm_property *property,
2451 uint64_t val)
2452 {
2453 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2454 struct intel_connector *intel_connector = to_intel_connector(connector);
2455 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2456 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2457 int ret;
2458
2459 ret = drm_object_property_set_value(&connector->base, property, val);
2460 if (ret)
2461 return ret;
2462
2463 if (property == dev_priv->force_audio_property) {
2464 int i = val;
2465 bool has_audio;
2466
2467 if (i == intel_dp->force_audio)
2468 return 0;
2469
2470 intel_dp->force_audio = i;
2471
2472 if (i == HDMI_AUDIO_AUTO)
2473 has_audio = intel_dp_detect_audio(connector);
2474 else
2475 has_audio = (i == HDMI_AUDIO_ON);
2476
2477 if (has_audio == intel_dp->has_audio)
2478 return 0;
2479
2480 intel_dp->has_audio = has_audio;
2481 goto done;
2482 }
2483
2484 if (property == dev_priv->broadcast_rgb_property) {
2485 switch (val) {
2486 case INTEL_BROADCAST_RGB_AUTO:
2487 intel_dp->color_range_auto = true;
2488 break;
2489 case INTEL_BROADCAST_RGB_FULL:
2490 intel_dp->color_range_auto = false;
2491 intel_dp->color_range = 0;
2492 break;
2493 case INTEL_BROADCAST_RGB_LIMITED:
2494 intel_dp->color_range_auto = false;
2495 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2496 break;
2497 default:
2498 return -EINVAL;
2499 }
2500 goto done;
2501 }
2502
2503 if (is_edp(intel_dp) &&
2504 property == connector->dev->mode_config.scaling_mode_property) {
2505 if (val == DRM_MODE_SCALE_NONE) {
2506 DRM_DEBUG_KMS("no scaling not supported\n");
2507 return -EINVAL;
2508 }
2509
2510 if (intel_connector->panel.fitting_mode == val) {
2511 /* the eDP scaling property is not changed */
2512 return 0;
2513 }
2514 intel_connector->panel.fitting_mode = val;
2515
2516 goto done;
2517 }
2518
2519 return -EINVAL;
2520
2521 done:
2522 if (intel_encoder->base.crtc)
2523 intel_crtc_restore_mode(intel_encoder->base.crtc);
2524
2525 return 0;
2526 }
2527
2528 static void
2529 intel_dp_destroy(struct drm_connector *connector)
2530 {
2531 struct drm_device *dev = connector->dev;
2532 struct intel_dp *intel_dp = intel_attached_dp(connector);
2533 struct intel_connector *intel_connector = to_intel_connector(connector);
2534
2535 if (!IS_ERR_OR_NULL(intel_connector->edid))
2536 kfree(intel_connector->edid);
2537
2538 if (is_edp(intel_dp)) {
2539 intel_panel_destroy_backlight(dev);
2540 intel_panel_fini(&intel_connector->panel);
2541 }
2542
2543 drm_sysfs_connector_remove(connector);
2544 drm_connector_cleanup(connector);
2545 kfree(connector);
2546 }
2547
2548 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2549 {
2550 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2551 struct intel_dp *intel_dp = &intel_dig_port->dp;
2552
2553 i2c_del_adapter(&intel_dp->adapter);
2554 drm_encoder_cleanup(encoder);
2555 if (is_edp(intel_dp)) {
2556 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2557 ironlake_panel_vdd_off_sync(intel_dp);
2558 }
2559 kfree(intel_dig_port);
2560 }
2561
2562 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2563 .mode_fixup = intel_dp_mode_fixup,
2564 .mode_set = intel_dp_mode_set,
2565 .disable = intel_encoder_noop,
2566 };
2567
2568 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2569 .dpms = intel_connector_dpms,
2570 .detect = intel_dp_detect,
2571 .fill_modes = drm_helper_probe_single_connector_modes,
2572 .set_property = intel_dp_set_property,
2573 .destroy = intel_dp_destroy,
2574 };
2575
2576 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2577 .get_modes = intel_dp_get_modes,
2578 .mode_valid = intel_dp_mode_valid,
2579 .best_encoder = intel_best_encoder,
2580 };
2581
2582 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2583 .destroy = intel_dp_encoder_destroy,
2584 };
2585
2586 static void
2587 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2588 {
2589 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2590
2591 intel_dp_check_link_status(intel_dp);
2592 }
2593
2594 /* Return which DP Port should be selected for Transcoder DP control */
2595 int
2596 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2597 {
2598 struct drm_device *dev = crtc->dev;
2599 struct intel_encoder *intel_encoder;
2600 struct intel_dp *intel_dp;
2601
2602 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2603 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2604
2605 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2606 intel_encoder->type == INTEL_OUTPUT_EDP)
2607 return intel_dp->output_reg;
2608 }
2609
2610 return -1;
2611 }
2612
2613 /* check the VBT to see whether the eDP is on DP-D port */
2614 bool intel_dpd_is_edp(struct drm_device *dev)
2615 {
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 struct child_device_config *p_child;
2618 int i;
2619
2620 if (!dev_priv->child_dev_num)
2621 return false;
2622
2623 for (i = 0; i < dev_priv->child_dev_num; i++) {
2624 p_child = dev_priv->child_dev + i;
2625
2626 if (p_child->dvo_port == PORT_IDPD &&
2627 p_child->device_type == DEVICE_TYPE_eDP)
2628 return true;
2629 }
2630 return false;
2631 }
2632
2633 static void
2634 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2635 {
2636 struct intel_connector *intel_connector = to_intel_connector(connector);
2637
2638 intel_attach_force_audio_property(connector);
2639 intel_attach_broadcast_rgb_property(connector);
2640 intel_dp->color_range_auto = true;
2641
2642 if (is_edp(intel_dp)) {
2643 drm_mode_create_scaling_mode_property(connector->dev);
2644 drm_object_attach_property(
2645 &connector->base,
2646 connector->dev->mode_config.scaling_mode_property,
2647 DRM_MODE_SCALE_ASPECT);
2648 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2649 }
2650 }
2651
2652 static void
2653 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2654 struct intel_dp *intel_dp,
2655 struct edp_power_seq *out)
2656 {
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct edp_power_seq cur, vbt, spec, final;
2659 u32 pp_on, pp_off, pp_div, pp;
2660
2661 /* Workaround: Need to write PP_CONTROL with the unlock key as
2662 * the very first thing. */
2663 pp = ironlake_get_pp_control(dev_priv);
2664 I915_WRITE(PCH_PP_CONTROL, pp);
2665
2666 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2667 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2668 pp_div = I915_READ(PCH_PP_DIVISOR);
2669
2670 /* Pull timing values out of registers */
2671 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2672 PANEL_POWER_UP_DELAY_SHIFT;
2673
2674 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2675 PANEL_LIGHT_ON_DELAY_SHIFT;
2676
2677 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2678 PANEL_LIGHT_OFF_DELAY_SHIFT;
2679
2680 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2681 PANEL_POWER_DOWN_DELAY_SHIFT;
2682
2683 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2684 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2685
2686 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2687 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2688
2689 vbt = dev_priv->edp.pps;
2690
2691 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2692 * our hw here, which are all in 100usec. */
2693 spec.t1_t3 = 210 * 10;
2694 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2695 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2696 spec.t10 = 500 * 10;
2697 /* This one is special and actually in units of 100ms, but zero
2698 * based in the hw (so we need to add 100 ms). But the sw vbt
2699 * table multiplies it with 1000 to make it in units of 100usec,
2700 * too. */
2701 spec.t11_t12 = (510 + 100) * 10;
2702
2703 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2704 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2705
2706 /* Use the max of the register settings and vbt. If both are
2707 * unset, fall back to the spec limits. */
2708 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2709 spec.field : \
2710 max(cur.field, vbt.field))
2711 assign_final(t1_t3);
2712 assign_final(t8);
2713 assign_final(t9);
2714 assign_final(t10);
2715 assign_final(t11_t12);
2716 #undef assign_final
2717
2718 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2719 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2720 intel_dp->backlight_on_delay = get_delay(t8);
2721 intel_dp->backlight_off_delay = get_delay(t9);
2722 intel_dp->panel_power_down_delay = get_delay(t10);
2723 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2724 #undef get_delay
2725
2726 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2727 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2728 intel_dp->panel_power_cycle_delay);
2729
2730 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2731 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2732
2733 if (out)
2734 *out = final;
2735 }
2736
2737 static void
2738 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2739 struct intel_dp *intel_dp,
2740 struct edp_power_seq *seq)
2741 {
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 pp_on, pp_off, pp_div;
2744
2745 /* And finally store the new values in the power sequencer. */
2746 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2747 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2748 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2749 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2750 /* Compute the divisor for the pp clock, simply match the Bspec
2751 * formula. */
2752 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2753 << PP_REFERENCE_DIVIDER_SHIFT;
2754 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2755 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2756
2757 /* Haswell doesn't have any port selection bits for the panel
2758 * power sequencer any more. */
2759 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2760 if (is_cpu_edp(intel_dp))
2761 pp_on |= PANEL_POWER_PORT_DP_A;
2762 else
2763 pp_on |= PANEL_POWER_PORT_DP_D;
2764 }
2765
2766 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2767 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2768 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2769
2770 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2771 I915_READ(PCH_PP_ON_DELAYS),
2772 I915_READ(PCH_PP_OFF_DELAYS),
2773 I915_READ(PCH_PP_DIVISOR));
2774 }
2775
2776 void
2777 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2778 struct intel_connector *intel_connector)
2779 {
2780 struct drm_connector *connector = &intel_connector->base;
2781 struct intel_dp *intel_dp = &intel_dig_port->dp;
2782 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2783 struct drm_device *dev = intel_encoder->base.dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct drm_display_mode *fixed_mode = NULL;
2786 struct edp_power_seq power_seq = { 0 };
2787 enum port port = intel_dig_port->port;
2788 const char *name = NULL;
2789 int type;
2790
2791 /* Preserve the current hw state. */
2792 intel_dp->DP = I915_READ(intel_dp->output_reg);
2793 intel_dp->attached_connector = intel_connector;
2794
2795 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2796 if (intel_dpd_is_edp(dev))
2797 intel_dp->is_pch_edp = true;
2798
2799 /*
2800 * FIXME : We need to initialize built-in panels before external panels.
2801 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2802 */
2803 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2804 type = DRM_MODE_CONNECTOR_eDP;
2805 intel_encoder->type = INTEL_OUTPUT_EDP;
2806 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2807 type = DRM_MODE_CONNECTOR_eDP;
2808 intel_encoder->type = INTEL_OUTPUT_EDP;
2809 } else {
2810 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2811 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2812 * rewrite it.
2813 */
2814 type = DRM_MODE_CONNECTOR_DisplayPort;
2815 }
2816
2817 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2818 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2819
2820 connector->polled = DRM_CONNECTOR_POLL_HPD;
2821 connector->interlace_allowed = true;
2822 connector->doublescan_allowed = 0;
2823
2824 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2825 ironlake_panel_vdd_work);
2826
2827 intel_connector_attach_encoder(intel_connector, intel_encoder);
2828 drm_sysfs_connector_add(connector);
2829
2830 if (HAS_DDI(dev))
2831 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2832 else
2833 intel_connector->get_hw_state = intel_connector_get_hw_state;
2834
2835
2836 /* Set up the DDC bus. */
2837 switch (port) {
2838 case PORT_A:
2839 name = "DPDDC-A";
2840 break;
2841 case PORT_B:
2842 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
2843 name = "DPDDC-B";
2844 break;
2845 case PORT_C:
2846 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
2847 name = "DPDDC-C";
2848 break;
2849 case PORT_D:
2850 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
2851 name = "DPDDC-D";
2852 break;
2853 default:
2854 WARN(1, "Invalid port %c\n", port_name(port));
2855 break;
2856 }
2857
2858 if (is_edp(intel_dp))
2859 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2860
2861 intel_dp_i2c_init(intel_dp, intel_connector, name);
2862
2863 /* Cache DPCD and EDID for edp. */
2864 if (is_edp(intel_dp)) {
2865 bool ret;
2866 struct drm_display_mode *scan;
2867 struct edid *edid;
2868
2869 ironlake_edp_panel_vdd_on(intel_dp);
2870 ret = intel_dp_get_dpcd(intel_dp);
2871 ironlake_edp_panel_vdd_off(intel_dp, false);
2872
2873 if (ret) {
2874 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2875 dev_priv->no_aux_handshake =
2876 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2877 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2878 } else {
2879 /* if this fails, presume the device is a ghost */
2880 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2881 intel_dp_encoder_destroy(&intel_encoder->base);
2882 intel_dp_destroy(connector);
2883 return;
2884 }
2885
2886 /* We now know it's not a ghost, init power sequence regs. */
2887 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2888 &power_seq);
2889
2890 ironlake_edp_panel_vdd_on(intel_dp);
2891 edid = drm_get_edid(connector, &intel_dp->adapter);
2892 if (edid) {
2893 if (drm_add_edid_modes(connector, edid)) {
2894 drm_mode_connector_update_edid_property(connector, edid);
2895 drm_edid_to_eld(connector, edid);
2896 } else {
2897 kfree(edid);
2898 edid = ERR_PTR(-EINVAL);
2899 }
2900 } else {
2901 edid = ERR_PTR(-ENOENT);
2902 }
2903 intel_connector->edid = edid;
2904
2905 /* prefer fixed mode from EDID if available */
2906 list_for_each_entry(scan, &connector->probed_modes, head) {
2907 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2908 fixed_mode = drm_mode_duplicate(dev, scan);
2909 break;
2910 }
2911 }
2912
2913 /* fallback to VBT if available for eDP */
2914 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2915 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2916 if (fixed_mode)
2917 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2918 }
2919
2920 ironlake_edp_panel_vdd_off(intel_dp, false);
2921 }
2922
2923 if (is_edp(intel_dp)) {
2924 intel_panel_init(&intel_connector->panel, fixed_mode);
2925 intel_panel_setup_backlight(connector);
2926 }
2927
2928 intel_dp_add_properties(intel_dp, connector);
2929
2930 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2931 * 0xd. Failure to do so will result in spurious interrupts being
2932 * generated on the port when a cable is not attached.
2933 */
2934 if (IS_G4X(dev) && !IS_GM45(dev)) {
2935 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2936 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2937 }
2938 }
2939
2940 void
2941 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2942 {
2943 struct intel_digital_port *intel_dig_port;
2944 struct intel_encoder *intel_encoder;
2945 struct drm_encoder *encoder;
2946 struct intel_connector *intel_connector;
2947
2948 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2949 if (!intel_dig_port)
2950 return;
2951
2952 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2953 if (!intel_connector) {
2954 kfree(intel_dig_port);
2955 return;
2956 }
2957
2958 intel_encoder = &intel_dig_port->base;
2959 encoder = &intel_encoder->base;
2960
2961 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2962 DRM_MODE_ENCODER_TMDS);
2963 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2964
2965 intel_encoder->enable = intel_enable_dp;
2966 intel_encoder->pre_enable = intel_pre_enable_dp;
2967 intel_encoder->disable = intel_disable_dp;
2968 intel_encoder->post_disable = intel_post_disable_dp;
2969 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2970
2971 intel_dig_port->port = port;
2972 intel_dig_port->dp.output_reg = output_reg;
2973
2974 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2975 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2976 intel_encoder->cloneable = false;
2977 intel_encoder->hot_plug = intel_dp_hot_plug;
2978
2979 intel_dp_init_connector(intel_dig_port, intel_connector);
2980 }
Linux kernel - Deliverables
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