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drm/i915: Clarify error returns from display port aux channel I/O
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc.h"
32 #include "drm_crtc_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "intel_dp.h"
37
38 #define DP_LINK_STATUS_SIZE 6
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 #define DP_LINK_CONFIGURATION_SIZE 9
42
43 struct intel_dp_priv {
44 uint32_t output_reg;
45 uint32_t DP;
46 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
47 uint32_t save_DP;
48 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
49 bool has_audio;
50 int dpms_mode;
51 uint8_t link_bw;
52 uint8_t lane_count;
53 uint8_t dpcd[4];
54 struct intel_output *intel_output;
55 struct i2c_adapter adapter;
56 struct i2c_algo_dp_aux_data algo;
57 };
58
59 static void
60 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
61 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
62
63 static void
64 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
65
66 static int
67 intel_dp_max_lane_count(struct intel_output *intel_output)
68 {
69 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
70 int max_lane_count = 4;
71
72 if (dp_priv->dpcd[0] >= 0x11) {
73 max_lane_count = dp_priv->dpcd[2] & 0x1f;
74 switch (max_lane_count) {
75 case 1: case 2: case 4:
76 break;
77 default:
78 max_lane_count = 4;
79 }
80 }
81 return max_lane_count;
82 }
83
84 static int
85 intel_dp_max_link_bw(struct intel_output *intel_output)
86 {
87 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
88 int max_link_bw = dp_priv->dpcd[1];
89
90 switch (max_link_bw) {
91 case DP_LINK_BW_1_62:
92 case DP_LINK_BW_2_7:
93 break;
94 default:
95 max_link_bw = DP_LINK_BW_1_62;
96 break;
97 }
98 return max_link_bw;
99 }
100
101 static int
102 intel_dp_link_clock(uint8_t link_bw)
103 {
104 if (link_bw == DP_LINK_BW_2_7)
105 return 270000;
106 else
107 return 162000;
108 }
109
110 /* I think this is a fiction */
111 static int
112 intel_dp_link_required(int pixel_clock)
113 {
114 return pixel_clock * 3;
115 }
116
117 static int
118 intel_dp_mode_valid(struct drm_connector *connector,
119 struct drm_display_mode *mode)
120 {
121 struct intel_output *intel_output = to_intel_output(connector);
122 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
123 int max_lanes = intel_dp_max_lane_count(intel_output);
124
125 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes)
126 return MODE_CLOCK_HIGH;
127
128 if (mode->clock < 10000)
129 return MODE_CLOCK_LOW;
130
131 return MODE_OK;
132 }
133
134 static uint32_t
135 pack_aux(uint8_t *src, int src_bytes)
136 {
137 int i;
138 uint32_t v = 0;
139
140 if (src_bytes > 4)
141 src_bytes = 4;
142 for (i = 0; i < src_bytes; i++)
143 v |= ((uint32_t) src[i]) << ((3-i) * 8);
144 return v;
145 }
146
147 static void
148 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
149 {
150 int i;
151 if (dst_bytes > 4)
152 dst_bytes = 4;
153 for (i = 0; i < dst_bytes; i++)
154 dst[i] = src >> ((3-i) * 8);
155 }
156
157 static int
158 intel_dp_aux_ch(struct intel_output *intel_output,
159 uint8_t *send, int send_bytes,
160 uint8_t *recv, int recv_size)
161 {
162 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
163 uint32_t output_reg = dp_priv->output_reg;
164 struct drm_device *dev = intel_output->base.dev;
165 struct drm_i915_private *dev_priv = dev->dev_private;
166 uint32_t ch_ctl = output_reg + 0x10;
167 uint32_t ch_data = ch_ctl + 4;
168 int i;
169 int recv_bytes;
170 uint32_t ctl;
171 uint32_t status;
172
173 /* Load the send data into the aux channel data registers */
174 for (i = 0; i < send_bytes; i += 4) {
175 uint32_t d = pack_aux(send + i, send_bytes - i);;
176
177 I915_WRITE(ch_data + i, d);
178 }
179
180 /* The clock divider is based off the hrawclk,
181 * and would like to run at 2MHz. The 133 below assumes
182 * a 266MHz hrawclk; need to figure out how we're supposed
183 * to know what hrawclk is...
184 */
185 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
186 DP_AUX_CH_CTL_TIME_OUT_1600us |
187 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
188 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
189 (133 << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
190 DP_AUX_CH_CTL_TIME_OUT_ERROR |
191 DP_AUX_CH_CTL_RECEIVE_ERROR);
192
193 /* Send the command and wait for it to complete */
194 I915_WRITE(ch_ctl, ctl);
195 (void) I915_READ(ch_ctl);
196 for (;;) {
197 udelay(100);
198 status = I915_READ(ch_ctl);
199 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
200 break;
201 }
202
203 /* Clear done status and any errors */
204 I915_WRITE(ch_ctl, (ctl |
205 DP_AUX_CH_CTL_DONE |
206 DP_AUX_CH_CTL_TIME_OUT_ERROR |
207 DP_AUX_CH_CTL_RECEIVE_ERROR));
208 (void) I915_READ(ch_ctl);
209
210 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
211 printk(KERN_ERR "dp_aux_ch not done status 0x%08x\n", status);
212 return -EBUSY;
213 }
214
215 /* Check for timeout or receive error.
216 * Timeouts occur when the sink is not connected
217 */
218 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
219 printk(KERN_ERR "dp_aux_ch receive error status 0x%08x\n", status);
220 return -EIO;
221 }
222 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
223 printk(KERN_ERR "dp_aux_ch timeout status 0x%08x\n", status);
224 return -ETIMEDOUT;
225 }
226
227 /* Unload any bytes sent back from the other side */
228 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
229 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
230
231 if (recv_bytes > recv_size)
232 recv_bytes = recv_size;
233
234 for (i = 0; i < recv_bytes; i += 4) {
235 uint32_t d = I915_READ(ch_data + i);
236
237 unpack_aux(d, recv + i, recv_bytes - i);
238 }
239
240 return recv_bytes;
241 }
242
243 /* Write data to the aux channel in native mode */
244 static int
245 intel_dp_aux_native_write(struct intel_output *intel_output,
246 uint16_t address, uint8_t *send, int send_bytes)
247 {
248 int ret;
249 uint8_t msg[20];
250 int msg_bytes;
251 uint8_t ack;
252
253 if (send_bytes > 16)
254 return -1;
255 msg[0] = AUX_NATIVE_WRITE << 4;
256 msg[1] = address >> 8;
257 msg[2] = address;
258 msg[3] = send_bytes - 1;
259 memcpy(&msg[4], send, send_bytes);
260 msg_bytes = send_bytes + 4;
261 for (;;) {
262 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
263 if (ret < 0)
264 return ret;
265 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
266 break;
267 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
268 udelay(100);
269 else
270 return -EIO;
271 }
272 return send_bytes;
273 }
274
275 /* Write a single byte to the aux channel in native mode */
276 static int
277 intel_dp_aux_native_write_1(struct intel_output *intel_output,
278 uint16_t address, uint8_t byte)
279 {
280 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
281 }
282
283 /* read bytes from a native aux channel */
284 static int
285 intel_dp_aux_native_read(struct intel_output *intel_output,
286 uint16_t address, uint8_t *recv, int recv_bytes)
287 {
288 uint8_t msg[4];
289 int msg_bytes;
290 uint8_t reply[20];
291 int reply_bytes;
292 uint8_t ack;
293 int ret;
294
295 msg[0] = AUX_NATIVE_READ << 4;
296 msg[1] = address >> 8;
297 msg[2] = address & 0xff;
298 msg[3] = recv_bytes - 1;
299
300 msg_bytes = 4;
301 reply_bytes = recv_bytes + 1;
302
303 for (;;) {
304 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
305 reply, reply_bytes);
306 if (ret == 0)
307 return -EPROTO;
308 if (ret < 0)
309 return ret;
310 ack = reply[0];
311 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
312 memcpy(recv, reply + 1, ret - 1);
313 return ret - 1;
314 }
315 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
316 udelay(100);
317 else
318 return -EIO;
319 }
320 }
321
322 static int
323 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter,
324 uint8_t *send, int send_bytes,
325 uint8_t *recv, int recv_bytes)
326 {
327 struct intel_dp_priv *dp_priv = container_of(adapter,
328 struct intel_dp_priv,
329 adapter);
330 struct intel_output *intel_output = dp_priv->intel_output;
331
332 return intel_dp_aux_ch(intel_output,
333 send, send_bytes, recv, recv_bytes);
334 }
335
336 static int
337 intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
338 {
339 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
340
341 DRM_ERROR("i2c_init %s\n", name);
342 dp_priv->algo.running = false;
343 dp_priv->algo.address = 0;
344 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
345
346 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
347 dp_priv->adapter.owner = THIS_MODULE;
348 dp_priv->adapter.class = I2C_CLASS_DDC;
349 strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1);
350 dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0';
351 dp_priv->adapter.algo_data = &dp_priv->algo;
352 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
353
354 return i2c_dp_aux_add_bus(&dp_priv->adapter);
355 }
356
357 static bool
358 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
359 struct drm_display_mode *adjusted_mode)
360 {
361 struct intel_output *intel_output = enc_to_intel_output(encoder);
362 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
363 int lane_count, clock;
364 int max_lane_count = intel_dp_max_lane_count(intel_output);
365 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
366 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
367
368 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
369 for (clock = 0; clock <= max_clock; clock++) {
370 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
371
372 if (intel_dp_link_required(mode->clock) <= link_avail) {
373 dp_priv->link_bw = bws[clock];
374 dp_priv->lane_count = lane_count;
375 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
376 printk(KERN_ERR "link bw %02x lane count %d clock %d\n",
377 dp_priv->link_bw, dp_priv->lane_count,
378 adjusted_mode->clock);
379 return true;
380 }
381 }
382 }
383 return false;
384 }
385
386 struct intel_dp_m_n {
387 uint32_t tu;
388 uint32_t gmch_m;
389 uint32_t gmch_n;
390 uint32_t link_m;
391 uint32_t link_n;
392 };
393
394 static void
395 intel_reduce_ratio(uint32_t *num, uint32_t *den)
396 {
397 while (*num > 0xffffff || *den > 0xffffff) {
398 *num >>= 1;
399 *den >>= 1;
400 }
401 }
402
403 static void
404 intel_dp_compute_m_n(int bytes_per_pixel,
405 int nlanes,
406 int pixel_clock,
407 int link_clock,
408 struct intel_dp_m_n *m_n)
409 {
410 m_n->tu = 64;
411 m_n->gmch_m = pixel_clock * bytes_per_pixel;
412 m_n->gmch_n = link_clock * nlanes;
413 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
414 m_n->link_m = pixel_clock;
415 m_n->link_n = link_clock;
416 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
417 }
418
419 void
420 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
421 struct drm_display_mode *adjusted_mode)
422 {
423 struct drm_device *dev = crtc->dev;
424 struct drm_mode_config *mode_config = &dev->mode_config;
425 struct drm_connector *connector;
426 struct drm_i915_private *dev_priv = dev->dev_private;
427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
428 int lane_count = 4;
429 struct intel_dp_m_n m_n;
430
431 /*
432 * Find the lane count in the intel_output private
433 */
434 list_for_each_entry(connector, &mode_config->connector_list, head) {
435 struct intel_output *intel_output = to_intel_output(connector);
436 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
437
438 if (!connector->encoder || connector->encoder->crtc != crtc)
439 continue;
440
441 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
442 lane_count = dp_priv->lane_count;
443 break;
444 }
445 }
446
447 /*
448 * Compute the GMCH and Link ratios. The '3' here is
449 * the number of bytes_per_pixel post-LUT, which we always
450 * set up for 8-bits of R/G/B, or 3 bytes total.
451 */
452 intel_dp_compute_m_n(3, lane_count,
453 mode->clock, adjusted_mode->clock, &m_n);
454
455 if (intel_crtc->pipe == 0) {
456 I915_WRITE(PIPEA_GMCH_DATA_M,
457 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
458 m_n.gmch_m);
459 I915_WRITE(PIPEA_GMCH_DATA_N,
460 m_n.gmch_n);
461 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
462 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
463 } else {
464 I915_WRITE(PIPEB_GMCH_DATA_M,
465 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
466 m_n.gmch_m);
467 I915_WRITE(PIPEB_GMCH_DATA_N,
468 m_n.gmch_n);
469 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
470 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
471 }
472 }
473
474 static void
475 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
476 struct drm_display_mode *adjusted_mode)
477 {
478 struct intel_output *intel_output = enc_to_intel_output(encoder);
479 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
480 struct drm_crtc *crtc = intel_output->enc.crtc;
481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
482
483 dp_priv->DP = (DP_LINK_TRAIN_OFF |
484 DP_VOLTAGE_0_4 |
485 DP_PRE_EMPHASIS_0 |
486 DP_SYNC_VS_HIGH |
487 DP_SYNC_HS_HIGH);
488
489 switch (dp_priv->lane_count) {
490 case 1:
491 dp_priv->DP |= DP_PORT_WIDTH_1;
492 break;
493 case 2:
494 dp_priv->DP |= DP_PORT_WIDTH_2;
495 break;
496 case 4:
497 dp_priv->DP |= DP_PORT_WIDTH_4;
498 break;
499 }
500 if (dp_priv->has_audio)
501 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
502
503 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
504 dp_priv->link_configuration[0] = dp_priv->link_bw;
505 dp_priv->link_configuration[1] = dp_priv->lane_count;
506
507 /*
508 * Check for DPCD version > 1.1,
509 * enable enahanced frame stuff in that case
510 */
511 if (dp_priv->dpcd[0] >= 0x11) {
512 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
513 dp_priv->DP |= DP_ENHANCED_FRAMING;
514 }
515
516 if (intel_crtc->pipe == 1)
517 dp_priv->DP |= DP_PIPEB_SELECT;
518 }
519
520
521 static void
522 intel_dp_dpms(struct drm_encoder *encoder, int mode)
523 {
524 struct intel_output *intel_output = enc_to_intel_output(encoder);
525 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
526 struct drm_device *dev = intel_output->base.dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
529
530 if (mode != DRM_MODE_DPMS_ON) {
531 if (dp_reg & DP_PORT_EN)
532 intel_dp_link_down(intel_output, dp_priv->DP);
533 } else {
534 if (!(dp_reg & DP_PORT_EN))
535 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
536 }
537 dp_priv->dpms_mode = mode;
538 }
539
540 /*
541 * Fetch AUX CH registers 0x202 - 0x207 which contain
542 * link status information
543 */
544 static bool
545 intel_dp_get_link_status(struct intel_output *intel_output,
546 uint8_t link_status[DP_LINK_STATUS_SIZE])
547 {
548 int ret;
549
550 ret = intel_dp_aux_native_read(intel_output,
551 DP_LANE0_1_STATUS,
552 link_status, DP_LINK_STATUS_SIZE);
553 if (ret != DP_LINK_STATUS_SIZE)
554 return false;
555 return true;
556 }
557
558 static uint8_t
559 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
560 int r)
561 {
562 return link_status[r - DP_LANE0_1_STATUS];
563 }
564
565 static void
566 intel_dp_save(struct drm_connector *connector)
567 {
568 struct intel_output *intel_output = to_intel_output(connector);
569 struct drm_device *dev = intel_output->base.dev;
570 struct drm_i915_private *dev_priv = dev->dev_private;
571 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
572
573 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
574 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
575 dp_priv->save_link_configuration,
576 sizeof (dp_priv->save_link_configuration));
577 }
578
579 static uint8_t
580 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
581 int lane)
582 {
583 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
584 int s = ((lane & 1) ?
585 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
586 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
587 uint8_t l = intel_dp_link_status(link_status, i);
588
589 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
590 }
591
592 static uint8_t
593 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
594 int lane)
595 {
596 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
597 int s = ((lane & 1) ?
598 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
599 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
600 uint8_t l = intel_dp_link_status(link_status, i);
601
602 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
603 }
604
605
606 #if 0
607 static char *voltage_names[] = {
608 "0.4V", "0.6V", "0.8V", "1.2V"
609 };
610 static char *pre_emph_names[] = {
611 "0dB", "3.5dB", "6dB", "9.5dB"
612 };
613 static char *link_train_names[] = {
614 "pattern 1", "pattern 2", "idle", "off"
615 };
616 #endif
617
618 /*
619 * These are source-specific values; current Intel hardware supports
620 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
621 */
622 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
623
624 static uint8_t
625 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
626 {
627 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
628 case DP_TRAIN_VOLTAGE_SWING_400:
629 return DP_TRAIN_PRE_EMPHASIS_6;
630 case DP_TRAIN_VOLTAGE_SWING_600:
631 return DP_TRAIN_PRE_EMPHASIS_6;
632 case DP_TRAIN_VOLTAGE_SWING_800:
633 return DP_TRAIN_PRE_EMPHASIS_3_5;
634 case DP_TRAIN_VOLTAGE_SWING_1200:
635 default:
636 return DP_TRAIN_PRE_EMPHASIS_0;
637 }
638 }
639
640 static void
641 intel_get_adjust_train(struct intel_output *intel_output,
642 uint8_t link_status[DP_LINK_STATUS_SIZE],
643 int lane_count,
644 uint8_t train_set[4])
645 {
646 uint8_t v = 0;
647 uint8_t p = 0;
648 int lane;
649
650 for (lane = 0; lane < lane_count; lane++) {
651 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
652 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
653
654 if (this_v > v)
655 v = this_v;
656 if (this_p > p)
657 p = this_p;
658 }
659
660 if (v >= I830_DP_VOLTAGE_MAX)
661 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
662
663 if (p >= intel_dp_pre_emphasis_max(v))
664 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
665
666 for (lane = 0; lane < 4; lane++)
667 train_set[lane] = v | p;
668 }
669
670 static uint32_t
671 intel_dp_signal_levels(uint8_t train_set, int lane_count)
672 {
673 uint32_t signal_levels = 0;
674
675 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
676 case DP_TRAIN_VOLTAGE_SWING_400:
677 default:
678 signal_levels |= DP_VOLTAGE_0_4;
679 break;
680 case DP_TRAIN_VOLTAGE_SWING_600:
681 signal_levels |= DP_VOLTAGE_0_6;
682 break;
683 case DP_TRAIN_VOLTAGE_SWING_800:
684 signal_levels |= DP_VOLTAGE_0_8;
685 break;
686 case DP_TRAIN_VOLTAGE_SWING_1200:
687 signal_levels |= DP_VOLTAGE_1_2;
688 break;
689 }
690 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
691 case DP_TRAIN_PRE_EMPHASIS_0:
692 default:
693 signal_levels |= DP_PRE_EMPHASIS_0;
694 break;
695 case DP_TRAIN_PRE_EMPHASIS_3_5:
696 signal_levels |= DP_PRE_EMPHASIS_3_5;
697 break;
698 case DP_TRAIN_PRE_EMPHASIS_6:
699 signal_levels |= DP_PRE_EMPHASIS_6;
700 break;
701 case DP_TRAIN_PRE_EMPHASIS_9_5:
702 signal_levels |= DP_PRE_EMPHASIS_9_5;
703 break;
704 }
705 return signal_levels;
706 }
707
708 static uint8_t
709 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
710 int lane)
711 {
712 int i = DP_LANE0_1_STATUS + (lane >> 1);
713 int s = (lane & 1) * 4;
714 uint8_t l = intel_dp_link_status(link_status, i);
715
716 return (l >> s) & 0xf;
717 }
718
719 /* Check for clock recovery is done on all channels */
720 static bool
721 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
722 {
723 int lane;
724 uint8_t lane_status;
725
726 for (lane = 0; lane < lane_count; lane++) {
727 lane_status = intel_get_lane_status(link_status, lane);
728 if ((lane_status & DP_LANE_CR_DONE) == 0)
729 return false;
730 }
731 return true;
732 }
733
734 /* Check to see if channel eq is done on all channels */
735 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
736 DP_LANE_CHANNEL_EQ_DONE|\
737 DP_LANE_SYMBOL_LOCKED)
738 static bool
739 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
740 {
741 uint8_t lane_align;
742 uint8_t lane_status;
743 int lane;
744
745 lane_align = intel_dp_link_status(link_status,
746 DP_LANE_ALIGN_STATUS_UPDATED);
747 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
748 return false;
749 for (lane = 0; lane < lane_count; lane++) {
750 lane_status = intel_get_lane_status(link_status, lane);
751 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
752 return false;
753 }
754 return true;
755 }
756
757 static bool
758 intel_dp_set_link_train(struct intel_output *intel_output,
759 uint32_t dp_reg_value,
760 uint8_t dp_train_pat,
761 uint8_t train_set[4],
762 bool first)
763 {
764 struct drm_device *dev = intel_output->base.dev;
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
767 int ret;
768
769 I915_WRITE(dp_priv->output_reg, dp_reg_value);
770 POSTING_READ(dp_priv->output_reg);
771 if (first)
772 intel_wait_for_vblank(dev);
773
774 intel_dp_aux_native_write_1(intel_output,
775 DP_TRAINING_PATTERN_SET,
776 dp_train_pat);
777
778 ret = intel_dp_aux_native_write(intel_output,
779 DP_TRAINING_LANE0_SET, train_set, 4);
780 if (ret != 4)
781 return false;
782
783 return true;
784 }
785
786 static void
787 intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
788 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
789 {
790 struct drm_device *dev = intel_output->base.dev;
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
793 uint8_t train_set[4];
794 uint8_t link_status[DP_LINK_STATUS_SIZE];
795 int i;
796 uint8_t voltage;
797 bool clock_recovery = false;
798 bool channel_eq = false;
799 bool first = true;
800 int tries;
801
802 /* Write the link configuration data */
803 intel_dp_aux_native_write(intel_output, 0x100,
804 link_configuration, DP_LINK_CONFIGURATION_SIZE);
805
806 DP |= DP_PORT_EN;
807 DP &= ~DP_LINK_TRAIN_MASK;
808 memset(train_set, 0, 4);
809 voltage = 0xff;
810 tries = 0;
811 clock_recovery = false;
812 for (;;) {
813 /* Use train_set[0] to set the voltage and pre emphasis values */
814 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
815 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
816
817 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
818 DP_TRAINING_PATTERN_1, train_set, first))
819 break;
820 first = false;
821 /* Set training pattern 1 */
822
823 udelay(100);
824 if (!intel_dp_get_link_status(intel_output, link_status))
825 break;
826
827 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
828 clock_recovery = true;
829 break;
830 }
831
832 /* Check to see if we've tried the max voltage */
833 for (i = 0; i < dp_priv->lane_count; i++)
834 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
835 break;
836 if (i == dp_priv->lane_count)
837 break;
838
839 /* Check to see if we've tried the same voltage 5 times */
840 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
841 ++tries;
842 if (tries == 5)
843 break;
844 } else
845 tries = 0;
846 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
847
848 /* Compute new train_set as requested by target */
849 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
850 }
851
852 /* channel equalization */
853 tries = 0;
854 channel_eq = false;
855 for (;;) {
856 /* Use train_set[0] to set the voltage and pre emphasis values */
857 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
858 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
859
860 /* channel eq pattern */
861 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
862 DP_TRAINING_PATTERN_2, train_set,
863 false))
864 break;
865
866 udelay(400);
867 if (!intel_dp_get_link_status(intel_output, link_status))
868 break;
869
870 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
871 channel_eq = true;
872 break;
873 }
874
875 /* Try 5 times */
876 if (tries > 5)
877 break;
878
879 /* Compute new train_set as requested by target */
880 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
881 ++tries;
882 }
883
884 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
885 POSTING_READ(dp_priv->output_reg);
886 intel_dp_aux_native_write_1(intel_output,
887 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
888 }
889
890 static void
891 intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
892 {
893 struct drm_device *dev = intel_output->base.dev;
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
896
897 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
898 POSTING_READ(dp_priv->output_reg);
899 }
900
901 static void
902 intel_dp_restore(struct drm_connector *connector)
903 {
904 struct intel_output *intel_output = to_intel_output(connector);
905 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
906
907 if (dp_priv->save_DP & DP_PORT_EN)
908 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
909 else
910 intel_dp_link_down(intel_output, dp_priv->save_DP);
911 }
912
913 /*
914 * According to DP spec
915 * 5.1.2:
916 * 1. Read DPCD
917 * 2. Configure link according to Receiver Capabilities
918 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
919 * 4. Check link status on receipt of hot-plug interrupt
920 */
921
922 static void
923 intel_dp_check_link_status(struct intel_output *intel_output)
924 {
925 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
926 uint8_t link_status[DP_LINK_STATUS_SIZE];
927
928 if (!intel_output->enc.crtc)
929 return;
930
931 if (!intel_dp_get_link_status(intel_output, link_status)) {
932 intel_dp_link_down(intel_output, dp_priv->DP);
933 return;
934 }
935
936 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
937 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
938 }
939
940 /**
941 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
942 *
943 * \return true if DP port is connected.
944 * \return false if DP port is disconnected.
945 */
946 static enum drm_connector_status
947 intel_dp_detect(struct drm_connector *connector)
948 {
949 struct intel_output *intel_output = to_intel_output(connector);
950 struct drm_device *dev = intel_output->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
953 uint32_t temp, bit;
954 enum drm_connector_status status;
955
956 dp_priv->has_audio = false;
957
958 temp = I915_READ(PORT_HOTPLUG_EN);
959
960 I915_WRITE(PORT_HOTPLUG_EN,
961 temp |
962 DPB_HOTPLUG_INT_EN |
963 DPC_HOTPLUG_INT_EN |
964 DPD_HOTPLUG_INT_EN);
965
966 POSTING_READ(PORT_HOTPLUG_EN);
967
968 switch (dp_priv->output_reg) {
969 case DP_B:
970 bit = DPB_HOTPLUG_INT_STATUS;
971 break;
972 case DP_C:
973 bit = DPC_HOTPLUG_INT_STATUS;
974 break;
975 case DP_D:
976 bit = DPD_HOTPLUG_INT_STATUS;
977 break;
978 default:
979 return connector_status_unknown;
980 }
981
982 temp = I915_READ(PORT_HOTPLUG_STAT);
983
984 if ((temp & bit) == 0)
985 return connector_status_disconnected;
986
987 status = connector_status_disconnected;
988 if (intel_dp_aux_native_read(intel_output,
989 0x000, dp_priv->dpcd,
990 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
991 {
992 if (dp_priv->dpcd[0] != 0)
993 status = connector_status_connected;
994 }
995 return status;
996 }
997
998 static int intel_dp_get_modes(struct drm_connector *connector)
999 {
1000 struct intel_output *intel_output = to_intel_output(connector);
1001
1002 /* We should parse the EDID data and find out if it has an audio sink
1003 */
1004
1005 return intel_ddc_get_modes(intel_output);
1006 }
1007
1008 static void
1009 intel_dp_destroy (struct drm_connector *connector)
1010 {
1011 struct intel_output *intel_output = to_intel_output(connector);
1012
1013 if (intel_output->i2c_bus)
1014 intel_i2c_destroy(intel_output->i2c_bus);
1015 drm_sysfs_connector_remove(connector);
1016 drm_connector_cleanup(connector);
1017 kfree(intel_output);
1018 }
1019
1020 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1021 .dpms = intel_dp_dpms,
1022 .mode_fixup = intel_dp_mode_fixup,
1023 .prepare = intel_encoder_prepare,
1024 .mode_set = intel_dp_mode_set,
1025 .commit = intel_encoder_commit,
1026 };
1027
1028 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1029 .dpms = drm_helper_connector_dpms,
1030 .save = intel_dp_save,
1031 .restore = intel_dp_restore,
1032 .detect = intel_dp_detect,
1033 .fill_modes = drm_helper_probe_single_connector_modes,
1034 .destroy = intel_dp_destroy,
1035 };
1036
1037 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1038 .get_modes = intel_dp_get_modes,
1039 .mode_valid = intel_dp_mode_valid,
1040 .best_encoder = intel_best_encoder,
1041 };
1042
1043 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1044 {
1045 drm_encoder_cleanup(encoder);
1046 }
1047
1048 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1049 .destroy = intel_dp_enc_destroy,
1050 };
1051
1052 void
1053 intel_dp_hot_plug(struct intel_output *intel_output)
1054 {
1055 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1056
1057 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1058 intel_dp_check_link_status(intel_output);
1059 }
1060
1061 void
1062 intel_dp_init(struct drm_device *dev, int output_reg)
1063 {
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct drm_connector *connector;
1066 struct intel_output *intel_output;
1067 struct intel_dp_priv *dp_priv;
1068
1069 intel_output = kcalloc(sizeof(struct intel_output) +
1070 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1071 if (!intel_output)
1072 return;
1073
1074 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1075
1076 connector = &intel_output->base;
1077 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1078 DRM_MODE_CONNECTOR_DisplayPort);
1079 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1080
1081 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1082
1083 connector->interlace_allowed = true;
1084 connector->doublescan_allowed = 0;
1085
1086 dp_priv->intel_output = intel_output;
1087 dp_priv->output_reg = output_reg;
1088 dp_priv->has_audio = false;
1089 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1090 intel_output->dev_priv = dp_priv;
1091
1092 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1093 DRM_MODE_ENCODER_TMDS);
1094 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1095
1096 drm_mode_connector_attach_encoder(&intel_output->base,
1097 &intel_output->enc);
1098 drm_sysfs_connector_add(connector);
1099
1100 /* Set up the DDC bus. */
1101 intel_dp_i2c_init(intel_output,
1102 (output_reg == DP_B) ? "DPDDC-B" :
1103 (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D");
1104 intel_output->ddc_bus = &dp_priv->adapter;
1105 intel_output->hot_plug = intel_dp_hot_plug;
1106
1107 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1108 * 0xd. Failure to do so will result in spurious interrupts being
1109 * generated on the port when a cable is not attached.
1110 */
1111 if (IS_G4X(dev) && !IS_GM45(dev)) {
1112 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1113 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1114 }
1115 }
Linux kernel - Deliverables
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