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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
41 /**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48 static bool is_edp(struct intel_dp *intel_dp)
49 {
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 }
54
55 /**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63 static bool is_pch_edp(struct intel_dp *intel_dp)
64 {
65 return intel_dp->is_pch_edp;
66 }
67
68 /**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
75 {
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77 }
78
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80 {
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
84 }
85
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87 {
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
89 }
90
91 /**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99 {
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108 }
109
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
111
112 void
113 intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
115 {
116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
117
118 *lane_num = intel_dp->lane_count;
119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
120 }
121
122 int
123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125 {
126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
127 struct intel_connector *intel_connector = intel_dp->attached_connector;
128
129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
131 else
132 return mode->clock;
133 }
134
135 static int
136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 {
138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149 }
150
151 /*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
168 static int
169 intel_dp_link_required(int pixel_clock, int bpp)
170 {
171 return (pixel_clock * bpp + 9) / 10;
172 }
173
174 static int
175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 {
177 return (max_link_clock * max_lanes * 8) / 10;
178 }
179
180 static int
181 intel_dp_mode_valid(struct drm_connector *connector,
182 struct drm_display_mode *mode)
183 {
184 struct intel_dp *intel_dp = intel_attached_dp(connector);
185 struct intel_connector *intel_connector = to_intel_connector(connector);
186 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
187 int target_clock = mode->clock;
188 int max_rate, mode_rate, max_lanes, max_link_clock;
189
190 if (is_edp(intel_dp) && fixed_mode) {
191 if (mode->hdisplay > fixed_mode->hdisplay)
192 return MODE_PANEL;
193
194 if (mode->vdisplay > fixed_mode->vdisplay)
195 return MODE_PANEL;
196
197 target_clock = fixed_mode->clock;
198 }
199
200 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
201 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
202
203 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
204 mode_rate = intel_dp_link_required(target_clock, 18);
205
206 if (mode_rate > max_rate)
207 return MODE_CLOCK_HIGH;
208
209 if (mode->clock < 10000)
210 return MODE_CLOCK_LOW;
211
212 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
213 return MODE_H_ILLEGAL;
214
215 return MODE_OK;
216 }
217
218 static uint32_t
219 pack_aux(uint8_t *src, int src_bytes)
220 {
221 int i;
222 uint32_t v = 0;
223
224 if (src_bytes > 4)
225 src_bytes = 4;
226 for (i = 0; i < src_bytes; i++)
227 v |= ((uint32_t) src[i]) << ((3-i) * 8);
228 return v;
229 }
230
231 static void
232 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
233 {
234 int i;
235 if (dst_bytes > 4)
236 dst_bytes = 4;
237 for (i = 0; i < dst_bytes; i++)
238 dst[i] = src >> ((3-i) * 8);
239 }
240
241 /* hrawclock is 1/4 the FSB frequency */
242 static int
243 intel_hrawclk(struct drm_device *dev)
244 {
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 uint32_t clkcfg;
247
248 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
249 if (IS_VALLEYVIEW(dev))
250 return 200;
251
252 clkcfg = I915_READ(CLKCFG);
253 switch (clkcfg & CLKCFG_FSB_MASK) {
254 case CLKCFG_FSB_400:
255 return 100;
256 case CLKCFG_FSB_533:
257 return 133;
258 case CLKCFG_FSB_667:
259 return 166;
260 case CLKCFG_FSB_800:
261 return 200;
262 case CLKCFG_FSB_1067:
263 return 266;
264 case CLKCFG_FSB_1333:
265 return 333;
266 /* these two are just a guess; one of them might be right */
267 case CLKCFG_FSB_1600:
268 case CLKCFG_FSB_1600_ALT:
269 return 400;
270 default:
271 return 133;
272 }
273 }
274
275 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
276 {
277 struct drm_device *dev = intel_dp_to_dev(intel_dp);
278 struct drm_i915_private *dev_priv = dev->dev_private;
279 u32 pp_stat_reg;
280
281 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
282 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
283 }
284
285 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
286 {
287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 u32 pp_ctrl_reg;
290
291 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
292 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
293 }
294
295 static void
296 intel_dp_check_edp(struct intel_dp *intel_dp)
297 {
298 struct drm_device *dev = intel_dp_to_dev(intel_dp);
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 u32 pp_stat_reg, pp_ctrl_reg;
301
302 if (!is_edp(intel_dp))
303 return;
304
305 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
306 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
307
308 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
309 WARN(1, "eDP powered off while attempting aux channel communication.\n");
310 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
311 I915_READ(pp_stat_reg),
312 I915_READ(pp_ctrl_reg));
313 }
314 }
315
316 static uint32_t
317 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
318 {
319 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
320 struct drm_device *dev = intel_dig_port->base.base.dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
323 uint32_t status;
324 bool done;
325
326 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
327 if (has_aux_irq)
328 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
329 msecs_to_jiffies(10));
330 else
331 done = wait_for_atomic(C, 10) == 0;
332 if (!done)
333 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
334 has_aux_irq);
335 #undef C
336
337 return status;
338 }
339
340 static int
341 intel_dp_aux_ch(struct intel_dp *intel_dp,
342 uint8_t *send, int send_bytes,
343 uint8_t *recv, int recv_size)
344 {
345 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
346 struct drm_device *dev = intel_dig_port->base.base.dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
349 uint32_t ch_data = ch_ctl + 4;
350 int i, ret, recv_bytes;
351 uint32_t status;
352 uint32_t aux_clock_divider;
353 int try, precharge;
354 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
355
356 /* dp aux is extremely sensitive to irq latency, hence request the
357 * lowest possible wakeup latency and so prevent the cpu from going into
358 * deep sleep states.
359 */
360 pm_qos_update_request(&dev_priv->pm_qos, 0);
361
362 intel_dp_check_edp(intel_dp);
363 /* The clock divider is based off the hrawclk,
364 * and would like to run at 2MHz. So, take the
365 * hrawclk value and divide by 2 and use that
366 *
367 * Note that PCH attached eDP panels should use a 125MHz input
368 * clock divider.
369 */
370 if (is_cpu_edp(intel_dp)) {
371 if (HAS_DDI(dev))
372 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
373 else if (IS_VALLEYVIEW(dev))
374 aux_clock_divider = 100;
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
376 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
377 else
378 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
379 } else if (HAS_PCH_SPLIT(dev))
380 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
381 else
382 aux_clock_divider = intel_hrawclk(dev) / 2;
383
384 if (IS_GEN6(dev))
385 precharge = 3;
386 else
387 precharge = 5;
388
389 /* Try to wait for any previous AUX channel activity */
390 for (try = 0; try < 3; try++) {
391 status = I915_READ_NOTRACE(ch_ctl);
392 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
393 break;
394 msleep(1);
395 }
396
397 if (try == 3) {
398 WARN(1, "dp_aux_ch not started status 0x%08x\n",
399 I915_READ(ch_ctl));
400 ret = -EBUSY;
401 goto out;
402 }
403
404 /* Must try at least 3 times according to DP spec */
405 for (try = 0; try < 5; try++) {
406 /* Load the send data into the aux channel data registers */
407 for (i = 0; i < send_bytes; i += 4)
408 I915_WRITE(ch_data + i,
409 pack_aux(send + i, send_bytes - i));
410
411 /* Send the command and wait for it to complete */
412 I915_WRITE(ch_ctl,
413 DP_AUX_CH_CTL_SEND_BUSY |
414 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
422
423 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
424
425 /* Clear done status and any errors */
426 I915_WRITE(ch_ctl,
427 status |
428 DP_AUX_CH_CTL_DONE |
429 DP_AUX_CH_CTL_TIME_OUT_ERROR |
430 DP_AUX_CH_CTL_RECEIVE_ERROR);
431
432 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
433 DP_AUX_CH_CTL_RECEIVE_ERROR))
434 continue;
435 if (status & DP_AUX_CH_CTL_DONE)
436 break;
437 }
438
439 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
440 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
441 ret = -EBUSY;
442 goto out;
443 }
444
445 /* Check for timeout or receive error.
446 * Timeouts occur when the sink is not connected
447 */
448 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
449 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
450 ret = -EIO;
451 goto out;
452 }
453
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
458 ret = -ETIMEDOUT;
459 goto out;
460 }
461
462 /* Unload any bytes sent back from the other side */
463 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
464 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
465 if (recv_bytes > recv_size)
466 recv_bytes = recv_size;
467
468 for (i = 0; i < recv_bytes; i += 4)
469 unpack_aux(I915_READ(ch_data + i),
470 recv + i, recv_bytes - i);
471
472 ret = recv_bytes;
473 out:
474 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
475
476 return ret;
477 }
478
479 /* Write data to the aux channel in native mode */
480 static int
481 intel_dp_aux_native_write(struct intel_dp *intel_dp,
482 uint16_t address, uint8_t *send, int send_bytes)
483 {
484 int ret;
485 uint8_t msg[20];
486 int msg_bytes;
487 uint8_t ack;
488
489 intel_dp_check_edp(intel_dp);
490 if (send_bytes > 16)
491 return -1;
492 msg[0] = AUX_NATIVE_WRITE << 4;
493 msg[1] = address >> 8;
494 msg[2] = address & 0xff;
495 msg[3] = send_bytes - 1;
496 memcpy(&msg[4], send, send_bytes);
497 msg_bytes = send_bytes + 4;
498 for (;;) {
499 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
500 if (ret < 0)
501 return ret;
502 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
503 break;
504 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
505 udelay(100);
506 else
507 return -EIO;
508 }
509 return send_bytes;
510 }
511
512 /* Write a single byte to the aux channel in native mode */
513 static int
514 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
515 uint16_t address, uint8_t byte)
516 {
517 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
518 }
519
520 /* read bytes from a native aux channel */
521 static int
522 intel_dp_aux_native_read(struct intel_dp *intel_dp,
523 uint16_t address, uint8_t *recv, int recv_bytes)
524 {
525 uint8_t msg[4];
526 int msg_bytes;
527 uint8_t reply[20];
528 int reply_bytes;
529 uint8_t ack;
530 int ret;
531
532 intel_dp_check_edp(intel_dp);
533 msg[0] = AUX_NATIVE_READ << 4;
534 msg[1] = address >> 8;
535 msg[2] = address & 0xff;
536 msg[3] = recv_bytes - 1;
537
538 msg_bytes = 4;
539 reply_bytes = recv_bytes + 1;
540
541 for (;;) {
542 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
543 reply, reply_bytes);
544 if (ret == 0)
545 return -EPROTO;
546 if (ret < 0)
547 return ret;
548 ack = reply[0];
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
550 memcpy(recv, reply + 1, ret - 1);
551 return ret - 1;
552 }
553 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
554 udelay(100);
555 else
556 return -EIO;
557 }
558 }
559
560 static int
561 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
562 uint8_t write_byte, uint8_t *read_byte)
563 {
564 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
565 struct intel_dp *intel_dp = container_of(adapter,
566 struct intel_dp,
567 adapter);
568 uint16_t address = algo_data->address;
569 uint8_t msg[5];
570 uint8_t reply[2];
571 unsigned retry;
572 int msg_bytes;
573 int reply_bytes;
574 int ret;
575
576 intel_dp_check_edp(intel_dp);
577 /* Set up the command byte */
578 if (mode & MODE_I2C_READ)
579 msg[0] = AUX_I2C_READ << 4;
580 else
581 msg[0] = AUX_I2C_WRITE << 4;
582
583 if (!(mode & MODE_I2C_STOP))
584 msg[0] |= AUX_I2C_MOT << 4;
585
586 msg[1] = address >> 8;
587 msg[2] = address;
588
589 switch (mode) {
590 case MODE_I2C_WRITE:
591 msg[3] = 0;
592 msg[4] = write_byte;
593 msg_bytes = 5;
594 reply_bytes = 1;
595 break;
596 case MODE_I2C_READ:
597 msg[3] = 0;
598 msg_bytes = 4;
599 reply_bytes = 2;
600 break;
601 default:
602 msg_bytes = 3;
603 reply_bytes = 1;
604 break;
605 }
606
607 for (retry = 0; retry < 5; retry++) {
608 ret = intel_dp_aux_ch(intel_dp,
609 msg, msg_bytes,
610 reply, reply_bytes);
611 if (ret < 0) {
612 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
613 return ret;
614 }
615
616 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
617 case AUX_NATIVE_REPLY_ACK:
618 /* I2C-over-AUX Reply field is only valid
619 * when paired with AUX ACK.
620 */
621 break;
622 case AUX_NATIVE_REPLY_NACK:
623 DRM_DEBUG_KMS("aux_ch native nack\n");
624 return -EREMOTEIO;
625 case AUX_NATIVE_REPLY_DEFER:
626 udelay(100);
627 continue;
628 default:
629 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
630 reply[0]);
631 return -EREMOTEIO;
632 }
633
634 switch (reply[0] & AUX_I2C_REPLY_MASK) {
635 case AUX_I2C_REPLY_ACK:
636 if (mode == MODE_I2C_READ) {
637 *read_byte = reply[1];
638 }
639 return reply_bytes - 1;
640 case AUX_I2C_REPLY_NACK:
641 DRM_DEBUG_KMS("aux_i2c nack\n");
642 return -EREMOTEIO;
643 case AUX_I2C_REPLY_DEFER:
644 DRM_DEBUG_KMS("aux_i2c defer\n");
645 udelay(100);
646 break;
647 default:
648 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
649 return -EREMOTEIO;
650 }
651 }
652
653 DRM_ERROR("too many retries, giving up\n");
654 return -EREMOTEIO;
655 }
656
657 static int
658 intel_dp_i2c_init(struct intel_dp *intel_dp,
659 struct intel_connector *intel_connector, const char *name)
660 {
661 int ret;
662
663 DRM_DEBUG_KMS("i2c_init %s\n", name);
664 intel_dp->algo.running = false;
665 intel_dp->algo.address = 0;
666 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
667
668 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
669 intel_dp->adapter.owner = THIS_MODULE;
670 intel_dp->adapter.class = I2C_CLASS_DDC;
671 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
672 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
673 intel_dp->adapter.algo_data = &intel_dp->algo;
674 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
675
676 ironlake_edp_panel_vdd_on(intel_dp);
677 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
678 ironlake_edp_panel_vdd_off(intel_dp, false);
679 return ret;
680 }
681
682 bool
683 intel_dp_compute_config(struct intel_encoder *encoder,
684 struct intel_crtc_config *pipe_config)
685 {
686 struct drm_device *dev = encoder->base.dev;
687 struct drm_i915_private *dev_priv = dev->dev_private;
688 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
689 struct drm_display_mode *mode = &pipe_config->requested_mode;
690 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
691 struct intel_connector *intel_connector = intel_dp->attached_connector;
692 int lane_count, clock;
693 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
694 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
695 int bpp, mode_rate;
696 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
697 int target_clock, link_avail, link_clock;
698
699 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
700 pipe_config->has_pch_encoder = true;
701
702 pipe_config->has_dp_encoder = true;
703
704 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
705 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
706 adjusted_mode);
707 intel_pch_panel_fitting(dev,
708 intel_connector->panel.fitting_mode,
709 mode, adjusted_mode);
710 }
711 /* We need to take the panel's fixed mode into account. */
712 target_clock = adjusted_mode->clock;
713
714 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
715 return false;
716
717 DRM_DEBUG_KMS("DP link computation with max lane count %i "
718 "max bw %02x pixel clock %iKHz\n",
719 max_lane_count, bws[max_clock], adjusted_mode->clock);
720
721 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
722 * bpc in between. */
723 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
724 if (is_edp(intel_dp) && dev_priv->edp.bpp)
725 bpp = min_t(int, bpp, dev_priv->edp.bpp);
726
727 for (; bpp >= 6*3; bpp -= 2*3) {
728 mode_rate = intel_dp_link_required(target_clock, bpp);
729
730 for (clock = 0; clock <= max_clock; clock++) {
731 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
732 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
733 link_avail = intel_dp_max_data_rate(link_clock,
734 lane_count);
735
736 if (mode_rate <= link_avail) {
737 goto found;
738 }
739 }
740 }
741 }
742
743 return false;
744
745 found:
746 if (intel_dp->color_range_auto) {
747 /*
748 * See:
749 * CEA-861-E - 5.1 Default Encoding Parameters
750 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
751 */
752 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
753 intel_dp->color_range = DP_COLOR_RANGE_16_235;
754 else
755 intel_dp->color_range = 0;
756 }
757
758 if (intel_dp->color_range)
759 pipe_config->limited_color_range = true;
760
761 intel_dp->link_bw = bws[clock];
762 intel_dp->lane_count = lane_count;
763 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
764 pipe_config->pipe_bpp = bpp;
765 pipe_config->pixel_target_clock = target_clock;
766
767 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
768 intel_dp->link_bw, intel_dp->lane_count,
769 adjusted_mode->clock, bpp);
770 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
771 mode_rate, link_avail);
772
773 intel_link_compute_m_n(bpp, lane_count,
774 target_clock, adjusted_mode->clock,
775 &pipe_config->dp_m_n);
776
777 return true;
778 }
779
780 void intel_dp_init_link_config(struct intel_dp *intel_dp)
781 {
782 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
783 intel_dp->link_configuration[0] = intel_dp->link_bw;
784 intel_dp->link_configuration[1] = intel_dp->lane_count;
785 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
786 /*
787 * Check for DPCD version > 1.1 and enhanced framing support
788 */
789 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
790 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
791 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
792 }
793 }
794
795 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
796 {
797 struct drm_device *dev = crtc->dev;
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 u32 dpa_ctl;
800
801 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
802 dpa_ctl = I915_READ(DP_A);
803 dpa_ctl &= ~DP_PLL_FREQ_MASK;
804
805 if (clock < 200000) {
806 /* For a long time we've carried around a ILK-DevA w/a for the
807 * 160MHz clock. If we're really unlucky, it's still required.
808 */
809 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
810 dpa_ctl |= DP_PLL_FREQ_160MHZ;
811 } else {
812 dpa_ctl |= DP_PLL_FREQ_270MHZ;
813 }
814
815 I915_WRITE(DP_A, dpa_ctl);
816
817 POSTING_READ(DP_A);
818 udelay(500);
819 }
820
821 static void
822 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
823 struct drm_display_mode *adjusted_mode)
824 {
825 struct drm_device *dev = encoder->dev;
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
828 struct drm_crtc *crtc = encoder->crtc;
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /*
832 * There are four kinds of DP registers:
833 *
834 * IBX PCH
835 * SNB CPU
836 * IVB CPU
837 * CPT PCH
838 *
839 * IBX PCH and CPU are the same for almost everything,
840 * except that the CPU DP PLL is configured in this
841 * register
842 *
843 * CPT PCH is quite different, having many bits moved
844 * to the TRANS_DP_CTL register instead. That
845 * configuration happens (oddly) in ironlake_pch_enable
846 */
847
848 /* Preserve the BIOS-computed detected bit. This is
849 * supposed to be read-only.
850 */
851 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
852
853 /* Handle DP bits in common between all three register formats */
854 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
855
856 switch (intel_dp->lane_count) {
857 case 1:
858 intel_dp->DP |= DP_PORT_WIDTH_1;
859 break;
860 case 2:
861 intel_dp->DP |= DP_PORT_WIDTH_2;
862 break;
863 case 4:
864 intel_dp->DP |= DP_PORT_WIDTH_4;
865 break;
866 }
867 if (intel_dp->has_audio) {
868 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
869 pipe_name(intel_crtc->pipe));
870 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
871 intel_write_eld(encoder, adjusted_mode);
872 }
873
874 intel_dp_init_link_config(intel_dp);
875
876 /* Split out the IBX/CPU vs CPT settings */
877
878 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
879 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
880 intel_dp->DP |= DP_SYNC_HS_HIGH;
881 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
882 intel_dp->DP |= DP_SYNC_VS_HIGH;
883 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
884
885 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
886 intel_dp->DP |= DP_ENHANCED_FRAMING;
887
888 intel_dp->DP |= intel_crtc->pipe << 29;
889
890 /* don't miss out required setting for eDP */
891 if (adjusted_mode->clock < 200000)
892 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893 else
894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
895 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
896 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
897 intel_dp->DP |= intel_dp->color_range;
898
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
900 intel_dp->DP |= DP_SYNC_HS_HIGH;
901 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
902 intel_dp->DP |= DP_SYNC_VS_HIGH;
903 intel_dp->DP |= DP_LINK_TRAIN_OFF;
904
905 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
906 intel_dp->DP |= DP_ENHANCED_FRAMING;
907
908 if (intel_crtc->pipe == 1)
909 intel_dp->DP |= DP_PIPEB_SELECT;
910
911 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
912 /* don't miss out required setting for eDP */
913 if (adjusted_mode->clock < 200000)
914 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915 else
916 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
917 }
918 } else {
919 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
920 }
921
922 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
923 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
924 }
925
926 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
927 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
928
929 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
930 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
931
932 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
933 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
934
935 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
936 u32 mask,
937 u32 value)
938 {
939 struct drm_device *dev = intel_dp_to_dev(intel_dp);
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 pp_stat_reg, pp_ctrl_reg;
942
943 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
944 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
945
946 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
947 mask, value,
948 I915_READ(pp_stat_reg),
949 I915_READ(pp_ctrl_reg));
950
951 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
952 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
953 I915_READ(pp_stat_reg),
954 I915_READ(pp_ctrl_reg));
955 }
956 }
957
958 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
959 {
960 DRM_DEBUG_KMS("Wait for panel power on\n");
961 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
962 }
963
964 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
965 {
966 DRM_DEBUG_KMS("Wait for panel power off time\n");
967 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
968 }
969
970 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
971 {
972 DRM_DEBUG_KMS("Wait for panel power cycle\n");
973 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
974 }
975
976
977 /* Read the current pp_control value, unlocking the register if it
978 * is locked
979 */
980
981 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
982 {
983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 control;
986 u32 pp_ctrl_reg;
987
988 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
989 control = I915_READ(pp_ctrl_reg);
990
991 control &= ~PANEL_UNLOCK_MASK;
992 control |= PANEL_UNLOCK_REGS;
993 return control;
994 }
995
996 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
997 {
998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 u32 pp;
1001 u32 pp_stat_reg, pp_ctrl_reg;
1002
1003 if (!is_edp(intel_dp))
1004 return;
1005 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1006
1007 WARN(intel_dp->want_panel_vdd,
1008 "eDP VDD already requested on\n");
1009
1010 intel_dp->want_panel_vdd = true;
1011
1012 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1013 DRM_DEBUG_KMS("eDP VDD already on\n");
1014 return;
1015 }
1016
1017 if (!ironlake_edp_have_panel_power(intel_dp))
1018 ironlake_wait_panel_power_cycle(intel_dp);
1019
1020 pp = ironlake_get_pp_control(intel_dp);
1021 pp |= EDP_FORCE_VDD;
1022
1023 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1024 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1025
1026 I915_WRITE(pp_ctrl_reg, pp);
1027 POSTING_READ(pp_ctrl_reg);
1028 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1029 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1030 /*
1031 * If the panel wasn't on, delay before accessing aux channel
1032 */
1033 if (!ironlake_edp_have_panel_power(intel_dp)) {
1034 DRM_DEBUG_KMS("eDP was not running\n");
1035 msleep(intel_dp->panel_power_up_delay);
1036 }
1037 }
1038
1039 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1040 {
1041 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1042 struct drm_i915_private *dev_priv = dev->dev_private;
1043 u32 pp;
1044 u32 pp_stat_reg, pp_ctrl_reg;
1045
1046 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1047
1048 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1049 pp = ironlake_get_pp_control(intel_dp);
1050 pp &= ~EDP_FORCE_VDD;
1051
1052 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1053 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1054
1055 I915_WRITE(pp_ctrl_reg, pp);
1056 POSTING_READ(pp_ctrl_reg);
1057
1058 /* Make sure sequencer is idle before allowing subsequent activity */
1059 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1060 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1061 msleep(intel_dp->panel_power_down_delay);
1062 }
1063 }
1064
1065 static void ironlake_panel_vdd_work(struct work_struct *__work)
1066 {
1067 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1068 struct intel_dp, panel_vdd_work);
1069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1070
1071 mutex_lock(&dev->mode_config.mutex);
1072 ironlake_panel_vdd_off_sync(intel_dp);
1073 mutex_unlock(&dev->mode_config.mutex);
1074 }
1075
1076 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1077 {
1078 if (!is_edp(intel_dp))
1079 return;
1080
1081 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1082 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1083
1084 intel_dp->want_panel_vdd = false;
1085
1086 if (sync) {
1087 ironlake_panel_vdd_off_sync(intel_dp);
1088 } else {
1089 /*
1090 * Queue the timer to fire a long
1091 * time from now (relative to the power down delay)
1092 * to keep the panel power up across a sequence of operations
1093 */
1094 schedule_delayed_work(&intel_dp->panel_vdd_work,
1095 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1096 }
1097 }
1098
1099 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1100 {
1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 u32 pp;
1104 u32 pp_ctrl_reg;
1105
1106 if (!is_edp(intel_dp))
1107 return;
1108
1109 DRM_DEBUG_KMS("Turn eDP power on\n");
1110
1111 if (ironlake_edp_have_panel_power(intel_dp)) {
1112 DRM_DEBUG_KMS("eDP power already on\n");
1113 return;
1114 }
1115
1116 ironlake_wait_panel_power_cycle(intel_dp);
1117
1118 pp = ironlake_get_pp_control(intel_dp);
1119 if (IS_GEN5(dev)) {
1120 /* ILK workaround: disable reset around power sequence */
1121 pp &= ~PANEL_POWER_RESET;
1122 I915_WRITE(PCH_PP_CONTROL, pp);
1123 POSTING_READ(PCH_PP_CONTROL);
1124 }
1125
1126 pp |= POWER_TARGET_ON;
1127 if (!IS_GEN5(dev))
1128 pp |= PANEL_POWER_RESET;
1129
1130 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1131
1132 I915_WRITE(pp_ctrl_reg, pp);
1133 POSTING_READ(pp_ctrl_reg);
1134
1135 ironlake_wait_panel_on(intel_dp);
1136
1137 if (IS_GEN5(dev)) {
1138 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
1141 }
1142 }
1143
1144 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1145 {
1146 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148 u32 pp;
1149 u32 pp_ctrl_reg;
1150
1151 if (!is_edp(intel_dp))
1152 return;
1153
1154 DRM_DEBUG_KMS("Turn eDP power off\n");
1155
1156 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1157
1158 pp = ironlake_get_pp_control(intel_dp);
1159 /* We need to switch off panel power _and_ force vdd, for otherwise some
1160 * panels get very unhappy and cease to work. */
1161 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1162
1163 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1164
1165 I915_WRITE(pp_ctrl_reg, pp);
1166 POSTING_READ(pp_ctrl_reg);
1167
1168 intel_dp->want_panel_vdd = false;
1169
1170 ironlake_wait_panel_off(intel_dp);
1171 }
1172
1173 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1174 {
1175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1176 struct drm_device *dev = intel_dig_port->base.base.dev;
1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1179 u32 pp;
1180 u32 pp_ctrl_reg;
1181
1182 if (!is_edp(intel_dp))
1183 return;
1184
1185 DRM_DEBUG_KMS("\n");
1186 /*
1187 * If we enable the backlight right away following a panel power
1188 * on, we may see slight flicker as the panel syncs with the eDP
1189 * link. So delay a bit to make sure the image is solid before
1190 * allowing it to appear.
1191 */
1192 msleep(intel_dp->backlight_on_delay);
1193 pp = ironlake_get_pp_control(intel_dp);
1194 pp |= EDP_BLC_ENABLE;
1195
1196 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1197
1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
1200
1201 intel_panel_enable_backlight(dev, pipe);
1202 }
1203
1204 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1205 {
1206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 u32 pp;
1209 u32 pp_ctrl_reg;
1210
1211 if (!is_edp(intel_dp))
1212 return;
1213
1214 intel_panel_disable_backlight(dev);
1215
1216 DRM_DEBUG_KMS("\n");
1217 pp = ironlake_get_pp_control(intel_dp);
1218 pp &= ~EDP_BLC_ENABLE;
1219
1220 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1221
1222 I915_WRITE(pp_ctrl_reg, pp);
1223 POSTING_READ(pp_ctrl_reg);
1224 msleep(intel_dp->backlight_off_delay);
1225 }
1226
1227 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1228 {
1229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1230 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1231 struct drm_device *dev = crtc->dev;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 u32 dpa_ctl;
1234
1235 assert_pipe_disabled(dev_priv,
1236 to_intel_crtc(crtc)->pipe);
1237
1238 DRM_DEBUG_KMS("\n");
1239 dpa_ctl = I915_READ(DP_A);
1240 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1241 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1242
1243 /* We don't adjust intel_dp->DP while tearing down the link, to
1244 * facilitate link retraining (e.g. after hotplug). Hence clear all
1245 * enable bits here to ensure that we don't enable too much. */
1246 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1247 intel_dp->DP |= DP_PLL_ENABLE;
1248 I915_WRITE(DP_A, intel_dp->DP);
1249 POSTING_READ(DP_A);
1250 udelay(200);
1251 }
1252
1253 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1254 {
1255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1257 struct drm_device *dev = crtc->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 u32 dpa_ctl;
1260
1261 assert_pipe_disabled(dev_priv,
1262 to_intel_crtc(crtc)->pipe);
1263
1264 dpa_ctl = I915_READ(DP_A);
1265 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1266 "dp pll off, should be on\n");
1267 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1268
1269 /* We can't rely on the value tracked for the DP register in
1270 * intel_dp->DP because link_down must not change that (otherwise link
1271 * re-training will fail. */
1272 dpa_ctl &= ~DP_PLL_ENABLE;
1273 I915_WRITE(DP_A, dpa_ctl);
1274 POSTING_READ(DP_A);
1275 udelay(200);
1276 }
1277
1278 /* If the sink supports it, try to set the power state appropriately */
1279 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1280 {
1281 int ret, i;
1282
1283 /* Should have a valid DPCD by this point */
1284 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1285 return;
1286
1287 if (mode != DRM_MODE_DPMS_ON) {
1288 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1289 DP_SET_POWER_D3);
1290 if (ret != 1)
1291 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1292 } else {
1293 /*
1294 * When turning on, we need to retry for 1ms to give the sink
1295 * time to wake up.
1296 */
1297 for (i = 0; i < 3; i++) {
1298 ret = intel_dp_aux_native_write_1(intel_dp,
1299 DP_SET_POWER,
1300 DP_SET_POWER_D0);
1301 if (ret == 1)
1302 break;
1303 msleep(1);
1304 }
1305 }
1306 }
1307
1308 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1309 enum pipe *pipe)
1310 {
1311 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1312 struct drm_device *dev = encoder->base.dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 u32 tmp = I915_READ(intel_dp->output_reg);
1315
1316 if (!(tmp & DP_PORT_EN))
1317 return false;
1318
1319 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1320 *pipe = PORT_TO_PIPE_CPT(tmp);
1321 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1322 *pipe = PORT_TO_PIPE(tmp);
1323 } else {
1324 u32 trans_sel;
1325 u32 trans_dp;
1326 int i;
1327
1328 switch (intel_dp->output_reg) {
1329 case PCH_DP_B:
1330 trans_sel = TRANS_DP_PORT_SEL_B;
1331 break;
1332 case PCH_DP_C:
1333 trans_sel = TRANS_DP_PORT_SEL_C;
1334 break;
1335 case PCH_DP_D:
1336 trans_sel = TRANS_DP_PORT_SEL_D;
1337 break;
1338 default:
1339 return true;
1340 }
1341
1342 for_each_pipe(i) {
1343 trans_dp = I915_READ(TRANS_DP_CTL(i));
1344 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1345 *pipe = i;
1346 return true;
1347 }
1348 }
1349
1350 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1351 intel_dp->output_reg);
1352 }
1353
1354 return false;
1355 }
1356
1357 static void intel_disable_dp(struct intel_encoder *encoder)
1358 {
1359 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1360
1361 /* Make sure the panel is off before trying to change the mode. But also
1362 * ensure that we have vdd while we switch off the panel. */
1363 ironlake_edp_panel_vdd_on(intel_dp);
1364 ironlake_edp_backlight_off(intel_dp);
1365 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1366 ironlake_edp_panel_off(intel_dp);
1367
1368 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1369 if (!is_cpu_edp(intel_dp))
1370 intel_dp_link_down(intel_dp);
1371 }
1372
1373 static void intel_post_disable_dp(struct intel_encoder *encoder)
1374 {
1375 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1376 struct drm_device *dev = encoder->base.dev;
1377
1378 if (is_cpu_edp(intel_dp)) {
1379 intel_dp_link_down(intel_dp);
1380 if (!IS_VALLEYVIEW(dev))
1381 ironlake_edp_pll_off(intel_dp);
1382 }
1383 }
1384
1385 static void intel_enable_dp(struct intel_encoder *encoder)
1386 {
1387 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1388 struct drm_device *dev = encoder->base.dev;
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1391
1392 if (WARN_ON(dp_reg & DP_PORT_EN))
1393 return;
1394
1395 ironlake_edp_panel_vdd_on(intel_dp);
1396 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1397 intel_dp_start_link_train(intel_dp);
1398 ironlake_edp_panel_on(intel_dp);
1399 ironlake_edp_panel_vdd_off(intel_dp, true);
1400 intel_dp_complete_link_train(intel_dp);
1401 ironlake_edp_backlight_on(intel_dp);
1402 }
1403
1404 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1405 {
1406 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1407 struct drm_device *dev = encoder->base.dev;
1408
1409 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1410 ironlake_edp_pll_on(intel_dp);
1411 }
1412
1413 /*
1414 * Native read with retry for link status and receiver capability reads for
1415 * cases where the sink may still be asleep.
1416 */
1417 static bool
1418 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1419 uint8_t *recv, int recv_bytes)
1420 {
1421 int ret, i;
1422
1423 /*
1424 * Sinks are *supposed* to come up within 1ms from an off state,
1425 * but we're also supposed to retry 3 times per the spec.
1426 */
1427 for (i = 0; i < 3; i++) {
1428 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1429 recv_bytes);
1430 if (ret == recv_bytes)
1431 return true;
1432 msleep(1);
1433 }
1434
1435 return false;
1436 }
1437
1438 /*
1439 * Fetch AUX CH registers 0x202 - 0x207 which contain
1440 * link status information
1441 */
1442 static bool
1443 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1444 {
1445 return intel_dp_aux_native_read_retry(intel_dp,
1446 DP_LANE0_1_STATUS,
1447 link_status,
1448 DP_LINK_STATUS_SIZE);
1449 }
1450
1451 #if 0
1452 static char *voltage_names[] = {
1453 "0.4V", "0.6V", "0.8V", "1.2V"
1454 };
1455 static char *pre_emph_names[] = {
1456 "0dB", "3.5dB", "6dB", "9.5dB"
1457 };
1458 static char *link_train_names[] = {
1459 "pattern 1", "pattern 2", "idle", "off"
1460 };
1461 #endif
1462
1463 /*
1464 * These are source-specific values; current Intel hardware supports
1465 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1466 */
1467
1468 static uint8_t
1469 intel_dp_voltage_max(struct intel_dp *intel_dp)
1470 {
1471 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1472
1473 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1474 return DP_TRAIN_VOLTAGE_SWING_800;
1475 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1476 return DP_TRAIN_VOLTAGE_SWING_1200;
1477 else
1478 return DP_TRAIN_VOLTAGE_SWING_800;
1479 }
1480
1481 static uint8_t
1482 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1483 {
1484 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1485
1486 if (HAS_DDI(dev)) {
1487 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1488 case DP_TRAIN_VOLTAGE_SWING_400:
1489 return DP_TRAIN_PRE_EMPHASIS_9_5;
1490 case DP_TRAIN_VOLTAGE_SWING_600:
1491 return DP_TRAIN_PRE_EMPHASIS_6;
1492 case DP_TRAIN_VOLTAGE_SWING_800:
1493 return DP_TRAIN_PRE_EMPHASIS_3_5;
1494 case DP_TRAIN_VOLTAGE_SWING_1200:
1495 default:
1496 return DP_TRAIN_PRE_EMPHASIS_0;
1497 }
1498 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1499 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1500 case DP_TRAIN_VOLTAGE_SWING_400:
1501 return DP_TRAIN_PRE_EMPHASIS_6;
1502 case DP_TRAIN_VOLTAGE_SWING_600:
1503 case DP_TRAIN_VOLTAGE_SWING_800:
1504 return DP_TRAIN_PRE_EMPHASIS_3_5;
1505 default:
1506 return DP_TRAIN_PRE_EMPHASIS_0;
1507 }
1508 } else {
1509 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1510 case DP_TRAIN_VOLTAGE_SWING_400:
1511 return DP_TRAIN_PRE_EMPHASIS_6;
1512 case DP_TRAIN_VOLTAGE_SWING_600:
1513 return DP_TRAIN_PRE_EMPHASIS_6;
1514 case DP_TRAIN_VOLTAGE_SWING_800:
1515 return DP_TRAIN_PRE_EMPHASIS_3_5;
1516 case DP_TRAIN_VOLTAGE_SWING_1200:
1517 default:
1518 return DP_TRAIN_PRE_EMPHASIS_0;
1519 }
1520 }
1521 }
1522
1523 static void
1524 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1525 {
1526 uint8_t v = 0;
1527 uint8_t p = 0;
1528 int lane;
1529 uint8_t voltage_max;
1530 uint8_t preemph_max;
1531
1532 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1533 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1534 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1535
1536 if (this_v > v)
1537 v = this_v;
1538 if (this_p > p)
1539 p = this_p;
1540 }
1541
1542 voltage_max = intel_dp_voltage_max(intel_dp);
1543 if (v >= voltage_max)
1544 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1545
1546 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1547 if (p >= preemph_max)
1548 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1549
1550 for (lane = 0; lane < 4; lane++)
1551 intel_dp->train_set[lane] = v | p;
1552 }
1553
1554 static uint32_t
1555 intel_gen4_signal_levels(uint8_t train_set)
1556 {
1557 uint32_t signal_levels = 0;
1558
1559 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1560 case DP_TRAIN_VOLTAGE_SWING_400:
1561 default:
1562 signal_levels |= DP_VOLTAGE_0_4;
1563 break;
1564 case DP_TRAIN_VOLTAGE_SWING_600:
1565 signal_levels |= DP_VOLTAGE_0_6;
1566 break;
1567 case DP_TRAIN_VOLTAGE_SWING_800:
1568 signal_levels |= DP_VOLTAGE_0_8;
1569 break;
1570 case DP_TRAIN_VOLTAGE_SWING_1200:
1571 signal_levels |= DP_VOLTAGE_1_2;
1572 break;
1573 }
1574 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1575 case DP_TRAIN_PRE_EMPHASIS_0:
1576 default:
1577 signal_levels |= DP_PRE_EMPHASIS_0;
1578 break;
1579 case DP_TRAIN_PRE_EMPHASIS_3_5:
1580 signal_levels |= DP_PRE_EMPHASIS_3_5;
1581 break;
1582 case DP_TRAIN_PRE_EMPHASIS_6:
1583 signal_levels |= DP_PRE_EMPHASIS_6;
1584 break;
1585 case DP_TRAIN_PRE_EMPHASIS_9_5:
1586 signal_levels |= DP_PRE_EMPHASIS_9_5;
1587 break;
1588 }
1589 return signal_levels;
1590 }
1591
1592 /* Gen6's DP voltage swing and pre-emphasis control */
1593 static uint32_t
1594 intel_gen6_edp_signal_levels(uint8_t train_set)
1595 {
1596 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1597 DP_TRAIN_PRE_EMPHASIS_MASK);
1598 switch (signal_levels) {
1599 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1600 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1601 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1602 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1603 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1604 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1605 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1606 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1607 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1608 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1609 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1610 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1611 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1612 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1613 default:
1614 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1615 "0x%x\n", signal_levels);
1616 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1617 }
1618 }
1619
1620 /* Gen7's DP voltage swing and pre-emphasis control */
1621 static uint32_t
1622 intel_gen7_edp_signal_levels(uint8_t train_set)
1623 {
1624 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1625 DP_TRAIN_PRE_EMPHASIS_MASK);
1626 switch (signal_levels) {
1627 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1628 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1629 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1630 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1631 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1632 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1633
1634 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1635 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1636 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1637 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1638
1639 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1640 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1641 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1642 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1643
1644 default:
1645 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1646 "0x%x\n", signal_levels);
1647 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1648 }
1649 }
1650
1651 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1652 static uint32_t
1653 intel_hsw_signal_levels(uint8_t train_set)
1654 {
1655 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1656 DP_TRAIN_PRE_EMPHASIS_MASK);
1657 switch (signal_levels) {
1658 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1659 return DDI_BUF_EMP_400MV_0DB_HSW;
1660 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1662 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1663 return DDI_BUF_EMP_400MV_6DB_HSW;
1664 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1665 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1666
1667 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1668 return DDI_BUF_EMP_600MV_0DB_HSW;
1669 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1670 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1671 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1672 return DDI_BUF_EMP_600MV_6DB_HSW;
1673
1674 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return DDI_BUF_EMP_800MV_0DB_HSW;
1676 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1678 default:
1679 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1680 "0x%x\n", signal_levels);
1681 return DDI_BUF_EMP_400MV_0DB_HSW;
1682 }
1683 }
1684
1685 /* Properly updates "DP" with the correct signal levels. */
1686 static void
1687 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1688 {
1689 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1690 struct drm_device *dev = intel_dig_port->base.base.dev;
1691 uint32_t signal_levels, mask;
1692 uint8_t train_set = intel_dp->train_set[0];
1693
1694 if (HAS_DDI(dev)) {
1695 signal_levels = intel_hsw_signal_levels(train_set);
1696 mask = DDI_BUF_EMP_MASK;
1697 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1698 signal_levels = intel_gen7_edp_signal_levels(train_set);
1699 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1700 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1701 signal_levels = intel_gen6_edp_signal_levels(train_set);
1702 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1703 } else {
1704 signal_levels = intel_gen4_signal_levels(train_set);
1705 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1706 }
1707
1708 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1709
1710 *DP = (*DP & ~mask) | signal_levels;
1711 }
1712
1713 static bool
1714 intel_dp_set_link_train(struct intel_dp *intel_dp,
1715 uint32_t dp_reg_value,
1716 uint8_t dp_train_pat)
1717 {
1718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1719 struct drm_device *dev = intel_dig_port->base.base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 enum port port = intel_dig_port->port;
1722 int ret;
1723 uint32_t temp;
1724
1725 if (HAS_DDI(dev)) {
1726 temp = I915_READ(DP_TP_CTL(port));
1727
1728 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1729 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1730 else
1731 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1732
1733 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1734 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1735 case DP_TRAINING_PATTERN_DISABLE:
1736
1737 if (port != PORT_A) {
1738 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1739 I915_WRITE(DP_TP_CTL(port), temp);
1740
1741 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1742 DP_TP_STATUS_IDLE_DONE), 1))
1743 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1744
1745 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1746 }
1747
1748 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1749
1750 break;
1751 case DP_TRAINING_PATTERN_1:
1752 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1753 break;
1754 case DP_TRAINING_PATTERN_2:
1755 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1756 break;
1757 case DP_TRAINING_PATTERN_3:
1758 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1759 break;
1760 }
1761 I915_WRITE(DP_TP_CTL(port), temp);
1762
1763 } else if (HAS_PCH_CPT(dev) &&
1764 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1765 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1766
1767 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1768 case DP_TRAINING_PATTERN_DISABLE:
1769 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1770 break;
1771 case DP_TRAINING_PATTERN_1:
1772 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1773 break;
1774 case DP_TRAINING_PATTERN_2:
1775 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1776 break;
1777 case DP_TRAINING_PATTERN_3:
1778 DRM_ERROR("DP training pattern 3 not supported\n");
1779 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1780 break;
1781 }
1782
1783 } else {
1784 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1785
1786 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1787 case DP_TRAINING_PATTERN_DISABLE:
1788 dp_reg_value |= DP_LINK_TRAIN_OFF;
1789 break;
1790 case DP_TRAINING_PATTERN_1:
1791 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1792 break;
1793 case DP_TRAINING_PATTERN_2:
1794 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1795 break;
1796 case DP_TRAINING_PATTERN_3:
1797 DRM_ERROR("DP training pattern 3 not supported\n");
1798 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1799 break;
1800 }
1801 }
1802
1803 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1804 POSTING_READ(intel_dp->output_reg);
1805
1806 intel_dp_aux_native_write_1(intel_dp,
1807 DP_TRAINING_PATTERN_SET,
1808 dp_train_pat);
1809
1810 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1811 DP_TRAINING_PATTERN_DISABLE) {
1812 ret = intel_dp_aux_native_write(intel_dp,
1813 DP_TRAINING_LANE0_SET,
1814 intel_dp->train_set,
1815 intel_dp->lane_count);
1816 if (ret != intel_dp->lane_count)
1817 return false;
1818 }
1819
1820 return true;
1821 }
1822
1823 /* Enable corresponding port and start training pattern 1 */
1824 void
1825 intel_dp_start_link_train(struct intel_dp *intel_dp)
1826 {
1827 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1828 struct drm_device *dev = encoder->dev;
1829 int i;
1830 uint8_t voltage;
1831 bool clock_recovery = false;
1832 int voltage_tries, loop_tries;
1833 uint32_t DP = intel_dp->DP;
1834
1835 if (HAS_DDI(dev))
1836 intel_ddi_prepare_link_retrain(encoder);
1837
1838 /* Write the link configuration data */
1839 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1840 intel_dp->link_configuration,
1841 DP_LINK_CONFIGURATION_SIZE);
1842
1843 DP |= DP_PORT_EN;
1844
1845 memset(intel_dp->train_set, 0, 4);
1846 voltage = 0xff;
1847 voltage_tries = 0;
1848 loop_tries = 0;
1849 clock_recovery = false;
1850 for (;;) {
1851 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1852 uint8_t link_status[DP_LINK_STATUS_SIZE];
1853
1854 intel_dp_set_signal_levels(intel_dp, &DP);
1855
1856 /* Set training pattern 1 */
1857 if (!intel_dp_set_link_train(intel_dp, DP,
1858 DP_TRAINING_PATTERN_1 |
1859 DP_LINK_SCRAMBLING_DISABLE))
1860 break;
1861
1862 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1863 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1864 DRM_ERROR("failed to get link status\n");
1865 break;
1866 }
1867
1868 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1869 DRM_DEBUG_KMS("clock recovery OK\n");
1870 clock_recovery = true;
1871 break;
1872 }
1873
1874 /* Check to see if we've tried the max voltage */
1875 for (i = 0; i < intel_dp->lane_count; i++)
1876 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1877 break;
1878 if (i == intel_dp->lane_count) {
1879 ++loop_tries;
1880 if (loop_tries == 5) {
1881 DRM_DEBUG_KMS("too many full retries, give up\n");
1882 break;
1883 }
1884 memset(intel_dp->train_set, 0, 4);
1885 voltage_tries = 0;
1886 continue;
1887 }
1888
1889 /* Check to see if we've tried the same voltage 5 times */
1890 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1891 ++voltage_tries;
1892 if (voltage_tries == 5) {
1893 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1894 break;
1895 }
1896 } else
1897 voltage_tries = 0;
1898 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1899
1900 /* Compute new intel_dp->train_set as requested by target */
1901 intel_get_adjust_train(intel_dp, link_status);
1902 }
1903
1904 intel_dp->DP = DP;
1905 }
1906
1907 void
1908 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1909 {
1910 bool channel_eq = false;
1911 int tries, cr_tries;
1912 uint32_t DP = intel_dp->DP;
1913
1914 /* channel equalization */
1915 tries = 0;
1916 cr_tries = 0;
1917 channel_eq = false;
1918 for (;;) {
1919 uint8_t link_status[DP_LINK_STATUS_SIZE];
1920
1921 if (cr_tries > 5) {
1922 DRM_ERROR("failed to train DP, aborting\n");
1923 intel_dp_link_down(intel_dp);
1924 break;
1925 }
1926
1927 intel_dp_set_signal_levels(intel_dp, &DP);
1928
1929 /* channel eq pattern */
1930 if (!intel_dp_set_link_train(intel_dp, DP,
1931 DP_TRAINING_PATTERN_2 |
1932 DP_LINK_SCRAMBLING_DISABLE))
1933 break;
1934
1935 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1936 if (!intel_dp_get_link_status(intel_dp, link_status))
1937 break;
1938
1939 /* Make sure clock is still ok */
1940 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1941 intel_dp_start_link_train(intel_dp);
1942 cr_tries++;
1943 continue;
1944 }
1945
1946 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1947 channel_eq = true;
1948 break;
1949 }
1950
1951 /* Try 5 times, then try clock recovery if that fails */
1952 if (tries > 5) {
1953 intel_dp_link_down(intel_dp);
1954 intel_dp_start_link_train(intel_dp);
1955 tries = 0;
1956 cr_tries++;
1957 continue;
1958 }
1959
1960 /* Compute new intel_dp->train_set as requested by target */
1961 intel_get_adjust_train(intel_dp, link_status);
1962 ++tries;
1963 }
1964
1965 if (channel_eq)
1966 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1967
1968 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1969 }
1970
1971 static void
1972 intel_dp_link_down(struct intel_dp *intel_dp)
1973 {
1974 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1975 struct drm_device *dev = intel_dig_port->base.base.dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct intel_crtc *intel_crtc =
1978 to_intel_crtc(intel_dig_port->base.base.crtc);
1979 uint32_t DP = intel_dp->DP;
1980
1981 /*
1982 * DDI code has a strict mode set sequence and we should try to respect
1983 * it, otherwise we might hang the machine in many different ways. So we
1984 * really should be disabling the port only on a complete crtc_disable
1985 * sequence. This function is just called under two conditions on DDI
1986 * code:
1987 * - Link train failed while doing crtc_enable, and on this case we
1988 * really should respect the mode set sequence and wait for a
1989 * crtc_disable.
1990 * - Someone turned the monitor off and intel_dp_check_link_status
1991 * called us. We don't need to disable the whole port on this case, so
1992 * when someone turns the monitor on again,
1993 * intel_ddi_prepare_link_retrain will take care of redoing the link
1994 * train.
1995 */
1996 if (HAS_DDI(dev))
1997 return;
1998
1999 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2000 return;
2001
2002 DRM_DEBUG_KMS("\n");
2003
2004 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2005 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2006 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2007 } else {
2008 DP &= ~DP_LINK_TRAIN_MASK;
2009 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2010 }
2011 POSTING_READ(intel_dp->output_reg);
2012
2013 /* We don't really know why we're doing this */
2014 intel_wait_for_vblank(dev, intel_crtc->pipe);
2015
2016 if (HAS_PCH_IBX(dev) &&
2017 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2018 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2019
2020 /* Hardware workaround: leaving our transcoder select
2021 * set to transcoder B while it's off will prevent the
2022 * corresponding HDMI output on transcoder A.
2023 *
2024 * Combine this with another hardware workaround:
2025 * transcoder select bit can only be cleared while the
2026 * port is enabled.
2027 */
2028 DP &= ~DP_PIPEB_SELECT;
2029 I915_WRITE(intel_dp->output_reg, DP);
2030
2031 /* Changes to enable or select take place the vblank
2032 * after being written.
2033 */
2034 if (WARN_ON(crtc == NULL)) {
2035 /* We should never try to disable a port without a crtc
2036 * attached. For paranoia keep the code around for a
2037 * bit. */
2038 POSTING_READ(intel_dp->output_reg);
2039 msleep(50);
2040 } else
2041 intel_wait_for_vblank(dev, intel_crtc->pipe);
2042 }
2043
2044 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2045 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2046 POSTING_READ(intel_dp->output_reg);
2047 msleep(intel_dp->panel_power_down_delay);
2048 }
2049
2050 static bool
2051 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2052 {
2053 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2054
2055 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2056 sizeof(intel_dp->dpcd)) == 0)
2057 return false; /* aux transfer failed */
2058
2059 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2060 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2061 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2062
2063 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2064 return false; /* DPCD not present */
2065
2066 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2067 DP_DWN_STRM_PORT_PRESENT))
2068 return true; /* native DP sink */
2069
2070 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2071 return true; /* no per-port downstream info */
2072
2073 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2074 intel_dp->downstream_ports,
2075 DP_MAX_DOWNSTREAM_PORTS) == 0)
2076 return false; /* downstream port status fetch failed */
2077
2078 return true;
2079 }
2080
2081 static void
2082 intel_dp_probe_oui(struct intel_dp *intel_dp)
2083 {
2084 u8 buf[3];
2085
2086 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2087 return;
2088
2089 ironlake_edp_panel_vdd_on(intel_dp);
2090
2091 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2092 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2093 buf[0], buf[1], buf[2]);
2094
2095 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2096 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2097 buf[0], buf[1], buf[2]);
2098
2099 ironlake_edp_panel_vdd_off(intel_dp, false);
2100 }
2101
2102 static bool
2103 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2104 {
2105 int ret;
2106
2107 ret = intel_dp_aux_native_read_retry(intel_dp,
2108 DP_DEVICE_SERVICE_IRQ_VECTOR,
2109 sink_irq_vector, 1);
2110 if (!ret)
2111 return false;
2112
2113 return true;
2114 }
2115
2116 static void
2117 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2118 {
2119 /* NAK by default */
2120 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2121 }
2122
2123 /*
2124 * According to DP spec
2125 * 5.1.2:
2126 * 1. Read DPCD
2127 * 2. Configure link according to Receiver Capabilities
2128 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2129 * 4. Check link status on receipt of hot-plug interrupt
2130 */
2131
2132 void
2133 intel_dp_check_link_status(struct intel_dp *intel_dp)
2134 {
2135 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2136 u8 sink_irq_vector;
2137 u8 link_status[DP_LINK_STATUS_SIZE];
2138
2139 if (!intel_encoder->connectors_active)
2140 return;
2141
2142 if (WARN_ON(!intel_encoder->base.crtc))
2143 return;
2144
2145 /* Try to read receiver status if the link appears to be up */
2146 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2147 intel_dp_link_down(intel_dp);
2148 return;
2149 }
2150
2151 /* Now read the DPCD to see if it's actually running */
2152 if (!intel_dp_get_dpcd(intel_dp)) {
2153 intel_dp_link_down(intel_dp);
2154 return;
2155 }
2156
2157 /* Try to read the source of the interrupt */
2158 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2159 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2160 /* Clear interrupt source */
2161 intel_dp_aux_native_write_1(intel_dp,
2162 DP_DEVICE_SERVICE_IRQ_VECTOR,
2163 sink_irq_vector);
2164
2165 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2166 intel_dp_handle_test_request(intel_dp);
2167 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2168 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2169 }
2170
2171 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2172 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2173 drm_get_encoder_name(&intel_encoder->base));
2174 intel_dp_start_link_train(intel_dp);
2175 intel_dp_complete_link_train(intel_dp);
2176 }
2177 }
2178
2179 /* XXX this is probably wrong for multiple downstream ports */
2180 static enum drm_connector_status
2181 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2182 {
2183 uint8_t *dpcd = intel_dp->dpcd;
2184 bool hpd;
2185 uint8_t type;
2186
2187 if (!intel_dp_get_dpcd(intel_dp))
2188 return connector_status_disconnected;
2189
2190 /* if there's no downstream port, we're done */
2191 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2192 return connector_status_connected;
2193
2194 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2195 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2196 if (hpd) {
2197 uint8_t reg;
2198 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2199 &reg, 1))
2200 return connector_status_unknown;
2201 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2202 : connector_status_disconnected;
2203 }
2204
2205 /* If no HPD, poke DDC gently */
2206 if (drm_probe_ddc(&intel_dp->adapter))
2207 return connector_status_connected;
2208
2209 /* Well we tried, say unknown for unreliable port types */
2210 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2211 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2212 return connector_status_unknown;
2213
2214 /* Anything else is out of spec, warn and ignore */
2215 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2216 return connector_status_disconnected;
2217 }
2218
2219 static enum drm_connector_status
2220 ironlake_dp_detect(struct intel_dp *intel_dp)
2221 {
2222 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2225 enum drm_connector_status status;
2226
2227 /* Can't disconnect eDP, but you can close the lid... */
2228 if (is_edp(intel_dp)) {
2229 status = intel_panel_detect(dev);
2230 if (status == connector_status_unknown)
2231 status = connector_status_connected;
2232 return status;
2233 }
2234
2235 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2236 return connector_status_disconnected;
2237
2238 return intel_dp_detect_dpcd(intel_dp);
2239 }
2240
2241 static enum drm_connector_status
2242 g4x_dp_detect(struct intel_dp *intel_dp)
2243 {
2244 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2247 uint32_t bit;
2248
2249 /* Can't disconnect eDP, but you can close the lid... */
2250 if (is_edp(intel_dp)) {
2251 enum drm_connector_status status;
2252
2253 status = intel_panel_detect(dev);
2254 if (status == connector_status_unknown)
2255 status = connector_status_connected;
2256 return status;
2257 }
2258
2259 switch (intel_dig_port->port) {
2260 case PORT_B:
2261 bit = PORTB_HOTPLUG_LIVE_STATUS;
2262 break;
2263 case PORT_C:
2264 bit = PORTC_HOTPLUG_LIVE_STATUS;
2265 break;
2266 case PORT_D:
2267 bit = PORTD_HOTPLUG_LIVE_STATUS;
2268 break;
2269 default:
2270 return connector_status_unknown;
2271 }
2272
2273 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2274 return connector_status_disconnected;
2275
2276 return intel_dp_detect_dpcd(intel_dp);
2277 }
2278
2279 static struct edid *
2280 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2281 {
2282 struct intel_connector *intel_connector = to_intel_connector(connector);
2283
2284 /* use cached edid if we have one */
2285 if (intel_connector->edid) {
2286 struct edid *edid;
2287 int size;
2288
2289 /* invalid edid */
2290 if (IS_ERR(intel_connector->edid))
2291 return NULL;
2292
2293 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2294 edid = kmalloc(size, GFP_KERNEL);
2295 if (!edid)
2296 return NULL;
2297
2298 memcpy(edid, intel_connector->edid, size);
2299 return edid;
2300 }
2301
2302 return drm_get_edid(connector, adapter);
2303 }
2304
2305 static int
2306 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2307 {
2308 struct intel_connector *intel_connector = to_intel_connector(connector);
2309
2310 /* use cached edid if we have one */
2311 if (intel_connector->edid) {
2312 /* invalid edid */
2313 if (IS_ERR(intel_connector->edid))
2314 return 0;
2315
2316 return intel_connector_update_modes(connector,
2317 intel_connector->edid);
2318 }
2319
2320 return intel_ddc_get_modes(connector, adapter);
2321 }
2322
2323 static enum drm_connector_status
2324 intel_dp_detect(struct drm_connector *connector, bool force)
2325 {
2326 struct intel_dp *intel_dp = intel_attached_dp(connector);
2327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2328 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2329 struct drm_device *dev = connector->dev;
2330 enum drm_connector_status status;
2331 struct edid *edid = NULL;
2332
2333 intel_dp->has_audio = false;
2334
2335 if (HAS_PCH_SPLIT(dev))
2336 status = ironlake_dp_detect(intel_dp);
2337 else
2338 status = g4x_dp_detect(intel_dp);
2339
2340 if (status != connector_status_connected)
2341 return status;
2342
2343 intel_dp_probe_oui(intel_dp);
2344
2345 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2346 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2347 } else {
2348 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2349 if (edid) {
2350 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2351 kfree(edid);
2352 }
2353 }
2354
2355 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2356 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2357 return connector_status_connected;
2358 }
2359
2360 static int intel_dp_get_modes(struct drm_connector *connector)
2361 {
2362 struct intel_dp *intel_dp = intel_attached_dp(connector);
2363 struct intel_connector *intel_connector = to_intel_connector(connector);
2364 struct drm_device *dev = connector->dev;
2365 int ret;
2366
2367 /* We should parse the EDID data and find out if it has an audio sink
2368 */
2369
2370 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2371 if (ret)
2372 return ret;
2373
2374 /* if eDP has no EDID, fall back to fixed mode */
2375 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2376 struct drm_display_mode *mode;
2377 mode = drm_mode_duplicate(dev,
2378 intel_connector->panel.fixed_mode);
2379 if (mode) {
2380 drm_mode_probed_add(connector, mode);
2381 return 1;
2382 }
2383 }
2384 return 0;
2385 }
2386
2387 static bool
2388 intel_dp_detect_audio(struct drm_connector *connector)
2389 {
2390 struct intel_dp *intel_dp = intel_attached_dp(connector);
2391 struct edid *edid;
2392 bool has_audio = false;
2393
2394 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2395 if (edid) {
2396 has_audio = drm_detect_monitor_audio(edid);
2397 kfree(edid);
2398 }
2399
2400 return has_audio;
2401 }
2402
2403 static int
2404 intel_dp_set_property(struct drm_connector *connector,
2405 struct drm_property *property,
2406 uint64_t val)
2407 {
2408 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2409 struct intel_connector *intel_connector = to_intel_connector(connector);
2410 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2411 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2412 int ret;
2413
2414 ret = drm_object_property_set_value(&connector->base, property, val);
2415 if (ret)
2416 return ret;
2417
2418 if (property == dev_priv->force_audio_property) {
2419 int i = val;
2420 bool has_audio;
2421
2422 if (i == intel_dp->force_audio)
2423 return 0;
2424
2425 intel_dp->force_audio = i;
2426
2427 if (i == HDMI_AUDIO_AUTO)
2428 has_audio = intel_dp_detect_audio(connector);
2429 else
2430 has_audio = (i == HDMI_AUDIO_ON);
2431
2432 if (has_audio == intel_dp->has_audio)
2433 return 0;
2434
2435 intel_dp->has_audio = has_audio;
2436 goto done;
2437 }
2438
2439 if (property == dev_priv->broadcast_rgb_property) {
2440 switch (val) {
2441 case INTEL_BROADCAST_RGB_AUTO:
2442 intel_dp->color_range_auto = true;
2443 break;
2444 case INTEL_BROADCAST_RGB_FULL:
2445 intel_dp->color_range_auto = false;
2446 intel_dp->color_range = 0;
2447 break;
2448 case INTEL_BROADCAST_RGB_LIMITED:
2449 intel_dp->color_range_auto = false;
2450 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2451 break;
2452 default:
2453 return -EINVAL;
2454 }
2455 goto done;
2456 }
2457
2458 if (is_edp(intel_dp) &&
2459 property == connector->dev->mode_config.scaling_mode_property) {
2460 if (val == DRM_MODE_SCALE_NONE) {
2461 DRM_DEBUG_KMS("no scaling not supported\n");
2462 return -EINVAL;
2463 }
2464
2465 if (intel_connector->panel.fitting_mode == val) {
2466 /* the eDP scaling property is not changed */
2467 return 0;
2468 }
2469 intel_connector->panel.fitting_mode = val;
2470
2471 goto done;
2472 }
2473
2474 return -EINVAL;
2475
2476 done:
2477 if (intel_encoder->base.crtc)
2478 intel_crtc_restore_mode(intel_encoder->base.crtc);
2479
2480 return 0;
2481 }
2482
2483 static void
2484 intel_dp_destroy(struct drm_connector *connector)
2485 {
2486 struct drm_device *dev = connector->dev;
2487 struct intel_dp *intel_dp = intel_attached_dp(connector);
2488 struct intel_connector *intel_connector = to_intel_connector(connector);
2489
2490 if (!IS_ERR_OR_NULL(intel_connector->edid))
2491 kfree(intel_connector->edid);
2492
2493 if (is_edp(intel_dp)) {
2494 intel_panel_destroy_backlight(dev);
2495 intel_panel_fini(&intel_connector->panel);
2496 }
2497
2498 drm_sysfs_connector_remove(connector);
2499 drm_connector_cleanup(connector);
2500 kfree(connector);
2501 }
2502
2503 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2504 {
2505 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2506 struct intel_dp *intel_dp = &intel_dig_port->dp;
2507
2508 i2c_del_adapter(&intel_dp->adapter);
2509 drm_encoder_cleanup(encoder);
2510 if (is_edp(intel_dp)) {
2511 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2512 ironlake_panel_vdd_off_sync(intel_dp);
2513 }
2514 kfree(intel_dig_port);
2515 }
2516
2517 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2518 .mode_set = intel_dp_mode_set,
2519 };
2520
2521 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2522 .dpms = intel_connector_dpms,
2523 .detect = intel_dp_detect,
2524 .fill_modes = drm_helper_probe_single_connector_modes,
2525 .set_property = intel_dp_set_property,
2526 .destroy = intel_dp_destroy,
2527 };
2528
2529 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2530 .get_modes = intel_dp_get_modes,
2531 .mode_valid = intel_dp_mode_valid,
2532 .best_encoder = intel_best_encoder,
2533 };
2534
2535 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2536 .destroy = intel_dp_encoder_destroy,
2537 };
2538
2539 static void
2540 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2541 {
2542 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2543
2544 intel_dp_check_link_status(intel_dp);
2545 }
2546
2547 /* Return which DP Port should be selected for Transcoder DP control */
2548 int
2549 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2550 {
2551 struct drm_device *dev = crtc->dev;
2552 struct intel_encoder *intel_encoder;
2553 struct intel_dp *intel_dp;
2554
2555 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2556 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2557
2558 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2559 intel_encoder->type == INTEL_OUTPUT_EDP)
2560 return intel_dp->output_reg;
2561 }
2562
2563 return -1;
2564 }
2565
2566 /* check the VBT to see whether the eDP is on DP-D port */
2567 bool intel_dpd_is_edp(struct drm_device *dev)
2568 {
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct child_device_config *p_child;
2571 int i;
2572
2573 if (!dev_priv->child_dev_num)
2574 return false;
2575
2576 for (i = 0; i < dev_priv->child_dev_num; i++) {
2577 p_child = dev_priv->child_dev + i;
2578
2579 if (p_child->dvo_port == PORT_IDPD &&
2580 p_child->device_type == DEVICE_TYPE_eDP)
2581 return true;
2582 }
2583 return false;
2584 }
2585
2586 static void
2587 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2588 {
2589 struct intel_connector *intel_connector = to_intel_connector(connector);
2590
2591 intel_attach_force_audio_property(connector);
2592 intel_attach_broadcast_rgb_property(connector);
2593 intel_dp->color_range_auto = true;
2594
2595 if (is_edp(intel_dp)) {
2596 drm_mode_create_scaling_mode_property(connector->dev);
2597 drm_object_attach_property(
2598 &connector->base,
2599 connector->dev->mode_config.scaling_mode_property,
2600 DRM_MODE_SCALE_ASPECT);
2601 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2602 }
2603 }
2604
2605 static void
2606 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2607 struct intel_dp *intel_dp,
2608 struct edp_power_seq *out)
2609 {
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 struct edp_power_seq cur, vbt, spec, final;
2612 u32 pp_on, pp_off, pp_div, pp;
2613 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2614
2615 if (HAS_PCH_SPLIT(dev)) {
2616 pp_control_reg = PCH_PP_CONTROL;
2617 pp_on_reg = PCH_PP_ON_DELAYS;
2618 pp_off_reg = PCH_PP_OFF_DELAYS;
2619 pp_div_reg = PCH_PP_DIVISOR;
2620 } else {
2621 pp_control_reg = PIPEA_PP_CONTROL;
2622 pp_on_reg = PIPEA_PP_ON_DELAYS;
2623 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2624 pp_div_reg = PIPEA_PP_DIVISOR;
2625 }
2626
2627 /* Workaround: Need to write PP_CONTROL with the unlock key as
2628 * the very first thing. */
2629 pp = ironlake_get_pp_control(intel_dp);
2630 I915_WRITE(pp_control_reg, pp);
2631
2632 pp_on = I915_READ(pp_on_reg);
2633 pp_off = I915_READ(pp_off_reg);
2634 pp_div = I915_READ(pp_div_reg);
2635
2636 /* Pull timing values out of registers */
2637 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2638 PANEL_POWER_UP_DELAY_SHIFT;
2639
2640 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2641 PANEL_LIGHT_ON_DELAY_SHIFT;
2642
2643 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2644 PANEL_LIGHT_OFF_DELAY_SHIFT;
2645
2646 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2647 PANEL_POWER_DOWN_DELAY_SHIFT;
2648
2649 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2650 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2651
2652 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2653 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2654
2655 vbt = dev_priv->edp.pps;
2656
2657 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2658 * our hw here, which are all in 100usec. */
2659 spec.t1_t3 = 210 * 10;
2660 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2661 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2662 spec.t10 = 500 * 10;
2663 /* This one is special and actually in units of 100ms, but zero
2664 * based in the hw (so we need to add 100 ms). But the sw vbt
2665 * table multiplies it with 1000 to make it in units of 100usec,
2666 * too. */
2667 spec.t11_t12 = (510 + 100) * 10;
2668
2669 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2670 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2671
2672 /* Use the max of the register settings and vbt. If both are
2673 * unset, fall back to the spec limits. */
2674 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2675 spec.field : \
2676 max(cur.field, vbt.field))
2677 assign_final(t1_t3);
2678 assign_final(t8);
2679 assign_final(t9);
2680 assign_final(t10);
2681 assign_final(t11_t12);
2682 #undef assign_final
2683
2684 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2685 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2686 intel_dp->backlight_on_delay = get_delay(t8);
2687 intel_dp->backlight_off_delay = get_delay(t9);
2688 intel_dp->panel_power_down_delay = get_delay(t10);
2689 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2690 #undef get_delay
2691
2692 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2693 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2694 intel_dp->panel_power_cycle_delay);
2695
2696 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2697 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2698
2699 if (out)
2700 *out = final;
2701 }
2702
2703 static void
2704 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2705 struct intel_dp *intel_dp,
2706 struct edp_power_seq *seq)
2707 {
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709 u32 pp_on, pp_off, pp_div, port_sel = 0;
2710 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2711 int pp_on_reg, pp_off_reg, pp_div_reg;
2712
2713 if (HAS_PCH_SPLIT(dev)) {
2714 pp_on_reg = PCH_PP_ON_DELAYS;
2715 pp_off_reg = PCH_PP_OFF_DELAYS;
2716 pp_div_reg = PCH_PP_DIVISOR;
2717 } else {
2718 pp_on_reg = PIPEA_PP_ON_DELAYS;
2719 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2720 pp_div_reg = PIPEA_PP_DIVISOR;
2721 }
2722
2723 if (IS_VALLEYVIEW(dev))
2724 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2725
2726 /* And finally store the new values in the power sequencer. */
2727 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2728 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2729 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2730 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2731 /* Compute the divisor for the pp clock, simply match the Bspec
2732 * formula. */
2733 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2734 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2735 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2736
2737 /* Haswell doesn't have any port selection bits for the panel
2738 * power sequencer any more. */
2739 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2740 if (is_cpu_edp(intel_dp))
2741 port_sel = PANEL_POWER_PORT_DP_A;
2742 else
2743 port_sel = PANEL_POWER_PORT_DP_D;
2744 }
2745
2746 pp_on |= port_sel;
2747
2748 I915_WRITE(pp_on_reg, pp_on);
2749 I915_WRITE(pp_off_reg, pp_off);
2750 I915_WRITE(pp_div_reg, pp_div);
2751
2752 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2753 I915_READ(pp_on_reg),
2754 I915_READ(pp_off_reg),
2755 I915_READ(pp_div_reg));
2756 }
2757
2758 void
2759 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2760 struct intel_connector *intel_connector)
2761 {
2762 struct drm_connector *connector = &intel_connector->base;
2763 struct intel_dp *intel_dp = &intel_dig_port->dp;
2764 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2765 struct drm_device *dev = intel_encoder->base.dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct drm_display_mode *fixed_mode = NULL;
2768 struct edp_power_seq power_seq = { 0 };
2769 enum port port = intel_dig_port->port;
2770 const char *name = NULL;
2771 int type;
2772
2773 /* Preserve the current hw state. */
2774 intel_dp->DP = I915_READ(intel_dp->output_reg);
2775 intel_dp->attached_connector = intel_connector;
2776
2777 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2778 if (intel_dpd_is_edp(dev))
2779 intel_dp->is_pch_edp = true;
2780
2781 /*
2782 * FIXME : We need to initialize built-in panels before external panels.
2783 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2784 */
2785 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2786 type = DRM_MODE_CONNECTOR_eDP;
2787 intel_encoder->type = INTEL_OUTPUT_EDP;
2788 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2789 type = DRM_MODE_CONNECTOR_eDP;
2790 intel_encoder->type = INTEL_OUTPUT_EDP;
2791 } else {
2792 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2793 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2794 * rewrite it.
2795 */
2796 type = DRM_MODE_CONNECTOR_DisplayPort;
2797 }
2798
2799 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2800 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2801
2802 connector->polled = DRM_CONNECTOR_POLL_HPD;
2803 connector->interlace_allowed = true;
2804 connector->doublescan_allowed = 0;
2805
2806 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2807 ironlake_panel_vdd_work);
2808
2809 intel_connector_attach_encoder(intel_connector, intel_encoder);
2810 drm_sysfs_connector_add(connector);
2811
2812 if (HAS_DDI(dev))
2813 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2814 else
2815 intel_connector->get_hw_state = intel_connector_get_hw_state;
2816
2817 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2818 if (HAS_DDI(dev)) {
2819 switch (intel_dig_port->port) {
2820 case PORT_A:
2821 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2822 break;
2823 case PORT_B:
2824 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2825 break;
2826 case PORT_C:
2827 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2828 break;
2829 case PORT_D:
2830 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2831 break;
2832 default:
2833 BUG();
2834 }
2835 }
2836
2837 /* Set up the DDC bus. */
2838 switch (port) {
2839 case PORT_A:
2840 intel_encoder->hpd_pin = HPD_PORT_A;
2841 name = "DPDDC-A";
2842 break;
2843 case PORT_B:
2844 intel_encoder->hpd_pin = HPD_PORT_B;
2845 name = "DPDDC-B";
2846 break;
2847 case PORT_C:
2848 intel_encoder->hpd_pin = HPD_PORT_C;
2849 name = "DPDDC-C";
2850 break;
2851 case PORT_D:
2852 intel_encoder->hpd_pin = HPD_PORT_D;
2853 name = "DPDDC-D";
2854 break;
2855 default:
2856 BUG();
2857 }
2858
2859 if (is_edp(intel_dp))
2860 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2861
2862 intel_dp_i2c_init(intel_dp, intel_connector, name);
2863
2864 /* Cache DPCD and EDID for edp. */
2865 if (is_edp(intel_dp)) {
2866 bool ret;
2867 struct drm_display_mode *scan;
2868 struct edid *edid;
2869
2870 ironlake_edp_panel_vdd_on(intel_dp);
2871 ret = intel_dp_get_dpcd(intel_dp);
2872 ironlake_edp_panel_vdd_off(intel_dp, false);
2873
2874 if (ret) {
2875 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2876 dev_priv->no_aux_handshake =
2877 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2878 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2879 } else {
2880 /* if this fails, presume the device is a ghost */
2881 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2882 intel_dp_encoder_destroy(&intel_encoder->base);
2883 intel_dp_destroy(connector);
2884 return;
2885 }
2886
2887 /* We now know it's not a ghost, init power sequence regs. */
2888 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2889 &power_seq);
2890
2891 ironlake_edp_panel_vdd_on(intel_dp);
2892 edid = drm_get_edid(connector, &intel_dp->adapter);
2893 if (edid) {
2894 if (drm_add_edid_modes(connector, edid)) {
2895 drm_mode_connector_update_edid_property(connector, edid);
2896 drm_edid_to_eld(connector, edid);
2897 } else {
2898 kfree(edid);
2899 edid = ERR_PTR(-EINVAL);
2900 }
2901 } else {
2902 edid = ERR_PTR(-ENOENT);
2903 }
2904 intel_connector->edid = edid;
2905
2906 /* prefer fixed mode from EDID if available */
2907 list_for_each_entry(scan, &connector->probed_modes, head) {
2908 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2909 fixed_mode = drm_mode_duplicate(dev, scan);
2910 break;
2911 }
2912 }
2913
2914 /* fallback to VBT if available for eDP */
2915 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2916 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2917 if (fixed_mode)
2918 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2919 }
2920
2921 ironlake_edp_panel_vdd_off(intel_dp, false);
2922 }
2923
2924 if (is_edp(intel_dp)) {
2925 intel_panel_init(&intel_connector->panel, fixed_mode);
2926 intel_panel_setup_backlight(connector);
2927 }
2928
2929 intel_dp_add_properties(intel_dp, connector);
2930
2931 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2932 * 0xd. Failure to do so will result in spurious interrupts being
2933 * generated on the port when a cable is not attached.
2934 */
2935 if (IS_G4X(dev) && !IS_GM45(dev)) {
2936 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2937 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2938 }
2939 }
2940
2941 void
2942 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2943 {
2944 struct intel_digital_port *intel_dig_port;
2945 struct intel_encoder *intel_encoder;
2946 struct drm_encoder *encoder;
2947 struct intel_connector *intel_connector;
2948
2949 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2950 if (!intel_dig_port)
2951 return;
2952
2953 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2954 if (!intel_connector) {
2955 kfree(intel_dig_port);
2956 return;
2957 }
2958
2959 intel_encoder = &intel_dig_port->base;
2960 encoder = &intel_encoder->base;
2961
2962 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2963 DRM_MODE_ENCODER_TMDS);
2964 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2965
2966 intel_encoder->compute_config = intel_dp_compute_config;
2967 intel_encoder->enable = intel_enable_dp;
2968 intel_encoder->pre_enable = intel_pre_enable_dp;
2969 intel_encoder->disable = intel_disable_dp;
2970 intel_encoder->post_disable = intel_post_disable_dp;
2971 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2972
2973 intel_dig_port->port = port;
2974 intel_dig_port->dp.output_reg = output_reg;
2975
2976 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2977 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2978 intel_encoder->cloneable = false;
2979 intel_encoder->hot_plug = intel_dp_hot_plug;
2980
2981 intel_dp_init_connector(intel_dig_port, intel_connector);
2982 }
Linux kernel - Deliverables
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