2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
116 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
117 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
121 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
123 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
124 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
126 switch (max_link_bw
) {
127 case DP_LINK_BW_1_62
:
130 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
131 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
132 INTEL_INFO(dev
)->gen
>= 8) &&
133 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
134 max_link_bw
= DP_LINK_BW_5_4
;
136 max_link_bw
= DP_LINK_BW_2_7
;
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw
= DP_LINK_BW_1_62
;
147 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
149 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
150 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
151 u8 source_max
, sink_max
;
154 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
155 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
158 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
160 return min(source_max
, sink_max
);
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 * 270000 * 1 * 8 / 10 == 216000
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
181 intel_dp_link_required(int pixel_clock
, int bpp
)
183 return (pixel_clock
* bpp
+ 9) / 10;
187 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
189 return (max_link_clock
* max_lanes
* 8) / 10;
192 static enum drm_mode_status
193 intel_dp_mode_valid(struct drm_connector
*connector
,
194 struct drm_display_mode
*mode
)
196 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
197 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
198 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
199 int target_clock
= mode
->clock
;
200 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 if (is_edp(intel_dp
) && fixed_mode
) {
203 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
206 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
209 target_clock
= fixed_mode
->clock
;
212 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
213 max_lanes
= intel_dp_max_lane_count(intel_dp
);
215 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
216 mode_rate
= intel_dp_link_required(target_clock
, 18);
218 if (mode_rate
> max_rate
)
219 return MODE_CLOCK_HIGH
;
221 if (mode
->clock
< 10000)
222 return MODE_CLOCK_LOW
;
224 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
225 return MODE_H_ILLEGAL
;
230 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
237 for (i
= 0; i
< src_bytes
; i
++)
238 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
242 void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
247 for (i
= 0; i
< dst_bytes
; i
++)
248 dst
[i
] = src
>> ((3-i
) * 8);
251 /* hrawclock is 1/4 the FSB frequency */
253 intel_hrawclk(struct drm_device
*dev
)
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev
))
262 clkcfg
= I915_READ(CLKCFG
);
263 switch (clkcfg
& CLKCFG_FSB_MASK
) {
272 case CLKCFG_FSB_1067
:
274 case CLKCFG_FSB_1333
:
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600
:
278 case CLKCFG_FSB_1600_ALT
:
286 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
287 struct intel_dp
*intel_dp
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
);
292 static void pps_lock(struct intel_dp
*intel_dp
)
294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
295 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
296 struct drm_device
*dev
= encoder
->base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum intel_display_power_domain power_domain
;
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
304 power_domain
= intel_display_port_power_domain(encoder
);
305 intel_display_power_get(dev_priv
, power_domain
);
307 mutex_lock(&dev_priv
->pps_mutex
);
310 static void pps_unlock(struct intel_dp
*intel_dp
)
312 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
313 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
314 struct drm_device
*dev
= encoder
->base
.dev
;
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 enum intel_display_power_domain power_domain
;
318 mutex_unlock(&dev_priv
->pps_mutex
);
320 power_domain
= intel_display_port_power_domain(encoder
);
321 intel_display_power_put(dev_priv
, power_domain
);
325 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 enum pipe pipe
= intel_dp
->pps_pipe
;
334 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe
), port_name(intel_dig_port
->port
));
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
345 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
346 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
347 DP
|= DP_PORT_WIDTH(1);
348 DP
|= DP_LINK_TRAIN_PAT_1
;
350 if (IS_CHERRYVIEW(dev
))
351 DP
|= DP_PIPE_SELECT_CHV(pipe
);
352 else if (pipe
== PIPE_B
)
353 DP
|= DP_PIPEB_SELECT
;
355 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
362 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
371 I915_WRITE(intel_dp
->output_reg
, DP
);
372 POSTING_READ(intel_dp
->output_reg
);
374 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
375 POSTING_READ(intel_dp
->output_reg
);
377 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
378 POSTING_READ(intel_dp
->output_reg
);
381 vlv_force_pll_off(dev
, pipe
);
385 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
388 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
390 struct intel_encoder
*encoder
;
391 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
394 lockdep_assert_held(&dev_priv
->pps_mutex
);
396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp
));
399 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
400 return intel_dp
->pps_pipe
;
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
406 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
408 struct intel_dp
*tmp
;
410 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
413 tmp
= enc_to_intel_dp(&encoder
->base
);
415 if (tmp
->pps_pipe
!= INVALID_PIPE
)
416 pipes
&= ~(1 << tmp
->pps_pipe
);
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
423 if (WARN_ON(pipes
== 0))
426 pipe
= ffs(pipes
) - 1;
428 vlv_steal_power_sequencer(dev
, pipe
);
429 intel_dp
->pps_pipe
= pipe
;
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp
->pps_pipe
),
433 port_name(intel_dig_port
->port
));
435 /* init power sequencer on this pipe and port */
436 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
437 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
443 vlv_power_sequencer_kick(intel_dp
);
445 return intel_dp
->pps_pipe
;
448 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
451 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
457 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
463 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
470 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
472 vlv_pipe_check pipe_check
)
476 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
477 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
478 PANEL_PORT_SELECT_MASK
;
480 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
483 if (!pipe_check(dev_priv
, pipe
))
493 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
495 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
496 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 enum port port
= intel_dig_port
->port
;
500 lockdep_assert_held(&dev_priv
->pps_mutex
);
502 /* try to find a pipe with this port selected */
503 /* first pick one where the panel is on */
504 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
508 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
509 vlv_pipe_has_vdd_on
);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
525 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
526 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
529 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
531 struct drm_device
*dev
= dev_priv
->dev
;
532 struct intel_encoder
*encoder
;
534 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
547 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
548 struct intel_dp
*intel_dp
;
550 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
553 intel_dp
= enc_to_intel_dp(&encoder
->base
);
554 intel_dp
->pps_pipe
= INVALID_PIPE
;
558 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
562 if (HAS_PCH_SPLIT(dev
))
563 return PCH_PP_CONTROL
;
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
568 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
570 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
572 if (HAS_PCH_SPLIT(dev
))
573 return PCH_PP_STATUS
;
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
578 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
583 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
585 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
588 u32 pp_ctrl_reg
, pp_div_reg
;
590 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
595 if (IS_VALLEYVIEW(dev
)) {
596 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
598 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
599 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
600 pp_div
= I915_READ(pp_div_reg
);
601 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
605 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
606 msleep(intel_dp
->panel_power_cycle_delay
);
609 pps_unlock(intel_dp
);
614 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
616 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
619 lockdep_assert_held(&dev_priv
->pps_mutex
);
621 if (IS_VALLEYVIEW(dev
) &&
622 intel_dp
->pps_pipe
== INVALID_PIPE
)
625 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
628 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
630 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 lockdep_assert_held(&dev_priv
->pps_mutex
);
635 if (IS_VALLEYVIEW(dev
) &&
636 intel_dp
->pps_pipe
== INVALID_PIPE
)
639 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
643 intel_dp_check_edp(struct intel_dp
*intel_dp
)
645 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
648 if (!is_edp(intel_dp
))
651 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
654 I915_READ(_pp_stat_reg(intel_dp
)),
655 I915_READ(_pp_ctrl_reg(intel_dp
)));
660 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
662 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
663 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
665 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
669 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
671 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
672 msecs_to_jiffies_timeout(10));
674 done
= wait_for_atomic(C
, 10) == 0;
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
683 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
685 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
686 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
692 return index
? 0 : intel_hrawclk(dev
) / 2;
695 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
703 if (intel_dig_port
->port
== PORT_A
) {
704 if (IS_GEN6(dev
) || IS_GEN7(dev
))
705 return 200; /* SNB & IVB eDP input clock at 400Mhz */
707 return 225; /* eDP input clock at 450Mhz */
709 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
713 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
715 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
716 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
719 if (intel_dig_port
->port
== PORT_A
) {
722 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
723 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
724 /* Workaround for non-ULT HSW */
731 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
735 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
737 return index
? 0 : 100;
740 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
743 * SKL doesn't need us to program the AUX clock divider (Hardware will
744 * derive the clock from CDCLK automatically). We still implement the
745 * get_aux_clock_divider vfunc to plug-in into the existing code.
747 return index
? 0 : 1;
750 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
753 uint32_t aux_clock_divider
)
755 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
756 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
757 uint32_t precharge
, timeout
;
764 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
765 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
767 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
769 return DP_AUX_CH_CTL_SEND_BUSY
|
771 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
772 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
774 DP_AUX_CH_CTL_RECEIVE_ERROR
|
775 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
776 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
777 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
780 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
785 return DP_AUX_CH_CTL_SEND_BUSY
|
787 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
788 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
789 DP_AUX_CH_CTL_TIME_OUT_1600us
|
790 DP_AUX_CH_CTL_RECEIVE_ERROR
|
791 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
792 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
796 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
797 const uint8_t *send
, int send_bytes
,
798 uint8_t *recv
, int recv_size
)
800 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
801 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
803 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
804 uint32_t ch_data
= ch_ctl
+ 4;
805 uint32_t aux_clock_divider
;
806 int i
, ret
, recv_bytes
;
809 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
815 * We will be called with VDD already enabled for dpcd/edid/oui reads.
816 * In such cases we want to leave VDD enabled and it's up to upper layers
817 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
820 vdd
= edp_panel_vdd_on(intel_dp
);
822 /* dp aux is extremely sensitive to irq latency, hence request the
823 * lowest possible wakeup latency and so prevent the cpu from going into
826 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
828 intel_dp_check_edp(intel_dp
);
830 intel_aux_display_runtime_get(dev_priv
);
832 /* Try to wait for any previous AUX channel activity */
833 for (try = 0; try < 3; try++) {
834 status
= I915_READ_NOTRACE(ch_ctl
);
835 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
841 WARN(1, "dp_aux_ch not started status 0x%08x\n",
847 /* Only 5 data registers! */
848 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
853 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
854 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
859 /* Must try at least 3 times according to DP spec */
860 for (try = 0; try < 5; try++) {
861 /* Load the send data into the aux channel data registers */
862 for (i
= 0; i
< send_bytes
; i
+= 4)
863 I915_WRITE(ch_data
+ i
,
864 intel_dp_pack_aux(send
+ i
,
867 /* Send the command and wait for it to complete */
868 I915_WRITE(ch_ctl
, send_ctl
);
870 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
872 /* Clear done status and any errors */
876 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
877 DP_AUX_CH_CTL_RECEIVE_ERROR
);
879 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
880 DP_AUX_CH_CTL_RECEIVE_ERROR
))
882 if (status
& DP_AUX_CH_CTL_DONE
)
885 if (status
& DP_AUX_CH_CTL_DONE
)
889 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
895 /* Check for timeout or receive error.
896 * Timeouts occur when the sink is not connected
898 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
899 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
904 /* Timeouts occur when the device isn't connected, so they're
905 * "normal" -- don't fill the kernel log with these */
906 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
907 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
912 /* Unload any bytes sent back from the other side */
913 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
914 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
915 if (recv_bytes
> recv_size
)
916 recv_bytes
= recv_size
;
918 for (i
= 0; i
< recv_bytes
; i
+= 4)
919 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
920 recv
+ i
, recv_bytes
- i
);
924 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
925 intel_aux_display_runtime_put(dev_priv
);
928 edp_panel_vdd_off(intel_dp
, false);
930 pps_unlock(intel_dp
);
935 #define BARE_ADDRESS_SIZE 3
936 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
938 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
940 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
941 uint8_t txbuf
[20], rxbuf
[20];
942 size_t txsize
, rxsize
;
945 txbuf
[0] = msg
->request
<< 4;
946 txbuf
[1] = msg
->address
>> 8;
947 txbuf
[2] = msg
->address
& 0xff;
948 txbuf
[3] = msg
->size
- 1;
950 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
951 case DP_AUX_NATIVE_WRITE
:
952 case DP_AUX_I2C_WRITE
:
953 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
956 if (WARN_ON(txsize
> 20))
959 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
961 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
963 msg
->reply
= rxbuf
[0] >> 4;
965 /* Return payload size. */
970 case DP_AUX_NATIVE_READ
:
971 case DP_AUX_I2C_READ
:
972 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
973 rxsize
= msg
->size
+ 1;
975 if (WARN_ON(rxsize
> 20))
978 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
980 msg
->reply
= rxbuf
[0] >> 4;
982 * Assume happy day, and copy the data. The caller is
983 * expected to check msg->reply before touching it.
985 * Return payload size.
988 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1001 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1003 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1004 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1005 enum port port
= intel_dig_port
->port
;
1006 const char *name
= NULL
;
1011 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1015 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1019 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1023 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1031 * The AUX_CTL register is usually DP_CTL + 0x10.
1033 * On Haswell and Broadwell though:
1034 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1040 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1042 intel_dp
->aux
.name
= name
;
1043 intel_dp
->aux
.dev
= dev
->dev
;
1044 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1046 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1047 connector
->base
.kdev
->kobj
.name
);
1049 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1051 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1056 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1057 &intel_dp
->aux
.ddc
.dev
.kobj
,
1058 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1060 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1061 drm_dp_aux_unregister(&intel_dp
->aux
);
1066 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1068 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1070 if (!intel_connector
->mst_port
)
1071 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1072 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1073 intel_connector_unregister(intel_connector
);
1077 skl_edp_set_pll_config(struct intel_crtc_config
*pipe_config
, int link_bw
)
1081 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1082 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1083 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1085 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1087 case DP_LINK_BW_1_62
:
1088 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
,
1091 case DP_LINK_BW_2_7
:
1092 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
,
1095 case DP_LINK_BW_5_4
:
1096 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
,
1100 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1104 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
1107 case DP_LINK_BW_1_62
:
1108 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1110 case DP_LINK_BW_2_7
:
1111 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1113 case DP_LINK_BW_5_4
:
1114 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1120 intel_dp_set_clock(struct intel_encoder
*encoder
,
1121 struct intel_crtc_config
*pipe_config
, int link_bw
)
1123 struct drm_device
*dev
= encoder
->base
.dev
;
1124 const struct dp_link_dpll
*divisor
= NULL
;
1128 divisor
= gen4_dpll
;
1129 count
= ARRAY_SIZE(gen4_dpll
);
1130 } else if (HAS_PCH_SPLIT(dev
)) {
1132 count
= ARRAY_SIZE(pch_dpll
);
1133 } else if (IS_CHERRYVIEW(dev
)) {
1135 count
= ARRAY_SIZE(chv_dpll
);
1136 } else if (IS_VALLEYVIEW(dev
)) {
1138 count
= ARRAY_SIZE(vlv_dpll
);
1141 if (divisor
&& count
) {
1142 for (i
= 0; i
< count
; i
++) {
1143 if (link_bw
== divisor
[i
].link_bw
) {
1144 pipe_config
->dpll
= divisor
[i
].dpll
;
1145 pipe_config
->clock_set
= true;
1153 intel_dp_compute_config(struct intel_encoder
*encoder
,
1154 struct intel_crtc_config
*pipe_config
)
1156 struct drm_device
*dev
= encoder
->base
.dev
;
1157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1158 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1159 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1160 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1161 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1162 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1163 int lane_count
, clock
;
1164 int min_lane_count
= 1;
1165 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1166 /* Conveniently, the link BW constants become indices with a shift...*/
1168 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1170 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1171 int link_avail
, link_clock
;
1173 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1174 pipe_config
->has_pch_encoder
= true;
1176 pipe_config
->has_dp_encoder
= true;
1177 pipe_config
->has_drrs
= false;
1178 pipe_config
->has_audio
= intel_dp
->has_audio
;
1180 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1181 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1183 if (!HAS_PCH_SPLIT(dev
))
1184 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1185 intel_connector
->panel
.fitting_mode
);
1187 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1188 intel_connector
->panel
.fitting_mode
);
1191 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1194 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195 "max bw %02x pixel clock %iKHz\n",
1196 max_lane_count
, bws
[max_clock
],
1197 adjusted_mode
->crtc_clock
);
1199 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200 * bpc in between. */
1201 bpp
= pipe_config
->pipe_bpp
;
1202 if (is_edp(intel_dp
)) {
1203 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1204 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205 dev_priv
->vbt
.edp_bpp
);
1206 bpp
= dev_priv
->vbt
.edp_bpp
;
1210 * Use the maximum clock and number of lanes the eDP panel
1211 * advertizes being capable of. The panels are generally
1212 * designed to support only a single clock and lane
1213 * configuration, and typically these values correspond to the
1214 * native resolution of the panel.
1216 min_lane_count
= max_lane_count
;
1217 min_clock
= max_clock
;
1220 for (; bpp
>= 6*3; bpp
-= 2*3) {
1221 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1224 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1225 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1226 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1227 link_avail
= intel_dp_max_data_rate(link_clock
,
1230 if (mode_rate
<= link_avail
) {
1240 if (intel_dp
->color_range_auto
) {
1243 * CEA-861-E - 5.1 Default Encoding Parameters
1244 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1246 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1247 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1249 intel_dp
->color_range
= 0;
1252 if (intel_dp
->color_range
)
1253 pipe_config
->limited_color_range
= true;
1255 intel_dp
->link_bw
= bws
[clock
];
1256 intel_dp
->lane_count
= lane_count
;
1257 pipe_config
->pipe_bpp
= bpp
;
1258 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1260 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261 intel_dp
->link_bw
, intel_dp
->lane_count
,
1262 pipe_config
->port_clock
, bpp
);
1263 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264 mode_rate
, link_avail
);
1266 intel_link_compute_m_n(bpp
, lane_count
,
1267 adjusted_mode
->crtc_clock
,
1268 pipe_config
->port_clock
,
1269 &pipe_config
->dp_m_n
);
1271 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1272 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1273 pipe_config
->has_drrs
= true;
1274 intel_link_compute_m_n(bpp
, lane_count
,
1275 intel_connector
->panel
.downclock_mode
->clock
,
1276 pipe_config
->port_clock
,
1277 &pipe_config
->dp_m2_n2
);
1280 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1281 skl_edp_set_pll_config(pipe_config
, intel_dp
->link_bw
);
1282 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1283 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1285 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1290 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1292 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1293 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1294 struct drm_device
*dev
= crtc
->base
.dev
;
1295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1299 dpa_ctl
= I915_READ(DP_A
);
1300 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1302 if (crtc
->config
.port_clock
== 162000) {
1303 /* For a long time we've carried around a ILK-DevA w/a for the
1304 * 160MHz clock. If we're really unlucky, it's still required.
1306 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1307 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1308 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1310 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1311 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1314 I915_WRITE(DP_A
, dpa_ctl
);
1320 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1322 struct drm_device
*dev
= encoder
->base
.dev
;
1323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1325 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1326 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1327 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1330 * There are four kinds of DP registers:
1337 * IBX PCH and CPU are the same for almost everything,
1338 * except that the CPU DP PLL is configured in this
1341 * CPT PCH is quite different, having many bits moved
1342 * to the TRANS_DP_CTL register instead. That
1343 * configuration happens (oddly) in ironlake_pch_enable
1346 /* Preserve the BIOS-computed detected bit. This is
1347 * supposed to be read-only.
1349 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1351 /* Handle DP bits in common between all three register formats */
1352 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1353 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1355 if (crtc
->config
.has_audio
)
1356 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1358 /* Split out the IBX/CPU vs CPT settings */
1360 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1361 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1362 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1363 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1364 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1365 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1367 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1368 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1370 intel_dp
->DP
|= crtc
->pipe
<< 29;
1371 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1372 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1373 intel_dp
->DP
|= intel_dp
->color_range
;
1375 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1376 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1377 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1378 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1379 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1381 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1382 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1384 if (!IS_CHERRYVIEW(dev
)) {
1385 if (crtc
->pipe
== 1)
1386 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1388 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1391 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1395 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1396 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1398 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1399 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1401 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1402 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1404 static void wait_panel_status(struct intel_dp
*intel_dp
,
1408 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1410 u32 pp_stat_reg
, pp_ctrl_reg
;
1412 lockdep_assert_held(&dev_priv
->pps_mutex
);
1414 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1415 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1417 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1419 I915_READ(pp_stat_reg
),
1420 I915_READ(pp_ctrl_reg
));
1422 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1423 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1424 I915_READ(pp_stat_reg
),
1425 I915_READ(pp_ctrl_reg
));
1428 DRM_DEBUG_KMS("Wait complete\n");
1431 static void wait_panel_on(struct intel_dp
*intel_dp
)
1433 DRM_DEBUG_KMS("Wait for panel power on\n");
1434 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1437 static void wait_panel_off(struct intel_dp
*intel_dp
)
1439 DRM_DEBUG_KMS("Wait for panel power off time\n");
1440 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1443 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1445 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1447 /* When we disable the VDD override bit last we have to do the manual
1449 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1450 intel_dp
->panel_power_cycle_delay
);
1452 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1455 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1457 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1458 intel_dp
->backlight_on_delay
);
1461 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1463 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1464 intel_dp
->backlight_off_delay
);
1467 /* Read the current pp_control value, unlocking the register if it
1471 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1473 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1477 lockdep_assert_held(&dev_priv
->pps_mutex
);
1479 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1480 control
&= ~PANEL_UNLOCK_MASK
;
1481 control
|= PANEL_UNLOCK_REGS
;
1486 * Must be paired with edp_panel_vdd_off().
1487 * Must hold pps_mutex around the whole on/off sequence.
1488 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1490 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1492 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1493 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1494 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1496 enum intel_display_power_domain power_domain
;
1498 u32 pp_stat_reg
, pp_ctrl_reg
;
1499 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1501 lockdep_assert_held(&dev_priv
->pps_mutex
);
1503 if (!is_edp(intel_dp
))
1506 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1507 intel_dp
->want_panel_vdd
= true;
1509 if (edp_have_panel_vdd(intel_dp
))
1510 return need_to_disable
;
1512 power_domain
= intel_display_port_power_domain(intel_encoder
);
1513 intel_display_power_get(dev_priv
, power_domain
);
1515 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1516 port_name(intel_dig_port
->port
));
1518 if (!edp_have_panel_power(intel_dp
))
1519 wait_panel_power_cycle(intel_dp
);
1521 pp
= ironlake_get_pp_control(intel_dp
);
1522 pp
|= EDP_FORCE_VDD
;
1524 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1525 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1527 I915_WRITE(pp_ctrl_reg
, pp
);
1528 POSTING_READ(pp_ctrl_reg
);
1529 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1530 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1532 * If the panel wasn't on, delay before accessing aux channel
1534 if (!edp_have_panel_power(intel_dp
)) {
1535 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1536 port_name(intel_dig_port
->port
));
1537 msleep(intel_dp
->panel_power_up_delay
);
1540 return need_to_disable
;
1544 * Must be paired with intel_edp_panel_vdd_off() or
1545 * intel_edp_panel_off().
1546 * Nested calls to these functions are not allowed since
1547 * we drop the lock. Caller must use some higher level
1548 * locking to prevent nested calls from other threads.
1550 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1554 if (!is_edp(intel_dp
))
1558 vdd
= edp_panel_vdd_on(intel_dp
);
1559 pps_unlock(intel_dp
);
1561 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1562 port_name(dp_to_dig_port(intel_dp
)->port
));
1565 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1567 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 struct intel_digital_port
*intel_dig_port
=
1570 dp_to_dig_port(intel_dp
);
1571 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1572 enum intel_display_power_domain power_domain
;
1574 u32 pp_stat_reg
, pp_ctrl_reg
;
1576 lockdep_assert_held(&dev_priv
->pps_mutex
);
1578 WARN_ON(intel_dp
->want_panel_vdd
);
1580 if (!edp_have_panel_vdd(intel_dp
))
1583 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1584 port_name(intel_dig_port
->port
));
1586 pp
= ironlake_get_pp_control(intel_dp
);
1587 pp
&= ~EDP_FORCE_VDD
;
1589 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1590 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1592 I915_WRITE(pp_ctrl_reg
, pp
);
1593 POSTING_READ(pp_ctrl_reg
);
1595 /* Make sure sequencer is idle before allowing subsequent activity */
1596 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1597 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1599 if ((pp
& POWER_TARGET_ON
) == 0)
1600 intel_dp
->last_power_cycle
= jiffies
;
1602 power_domain
= intel_display_port_power_domain(intel_encoder
);
1603 intel_display_power_put(dev_priv
, power_domain
);
1606 static void edp_panel_vdd_work(struct work_struct
*__work
)
1608 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1609 struct intel_dp
, panel_vdd_work
);
1612 if (!intel_dp
->want_panel_vdd
)
1613 edp_panel_vdd_off_sync(intel_dp
);
1614 pps_unlock(intel_dp
);
1617 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1619 unsigned long delay
;
1622 * Queue the timer to fire a long time from now (relative to the power
1623 * down delay) to keep the panel power up across a sequence of
1626 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1627 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1631 * Must be paired with edp_panel_vdd_on().
1632 * Must hold pps_mutex around the whole on/off sequence.
1633 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1635 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1637 struct drm_i915_private
*dev_priv
=
1638 intel_dp_to_dev(intel_dp
)->dev_private
;
1640 lockdep_assert_held(&dev_priv
->pps_mutex
);
1642 if (!is_edp(intel_dp
))
1645 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1646 port_name(dp_to_dig_port(intel_dp
)->port
));
1648 intel_dp
->want_panel_vdd
= false;
1651 edp_panel_vdd_off_sync(intel_dp
);
1653 edp_panel_vdd_schedule_off(intel_dp
);
1656 static void edp_panel_on(struct intel_dp
*intel_dp
)
1658 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1659 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1663 lockdep_assert_held(&dev_priv
->pps_mutex
);
1665 if (!is_edp(intel_dp
))
1668 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1669 port_name(dp_to_dig_port(intel_dp
)->port
));
1671 if (WARN(edp_have_panel_power(intel_dp
),
1672 "eDP port %c panel power already on\n",
1673 port_name(dp_to_dig_port(intel_dp
)->port
)))
1676 wait_panel_power_cycle(intel_dp
);
1678 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1679 pp
= ironlake_get_pp_control(intel_dp
);
1681 /* ILK workaround: disable reset around power sequence */
1682 pp
&= ~PANEL_POWER_RESET
;
1683 I915_WRITE(pp_ctrl_reg
, pp
);
1684 POSTING_READ(pp_ctrl_reg
);
1687 pp
|= POWER_TARGET_ON
;
1689 pp
|= PANEL_POWER_RESET
;
1691 I915_WRITE(pp_ctrl_reg
, pp
);
1692 POSTING_READ(pp_ctrl_reg
);
1694 wait_panel_on(intel_dp
);
1695 intel_dp
->last_power_on
= jiffies
;
1698 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1699 I915_WRITE(pp_ctrl_reg
, pp
);
1700 POSTING_READ(pp_ctrl_reg
);
1704 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1706 if (!is_edp(intel_dp
))
1710 edp_panel_on(intel_dp
);
1711 pps_unlock(intel_dp
);
1715 static void edp_panel_off(struct intel_dp
*intel_dp
)
1717 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1718 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1719 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1721 enum intel_display_power_domain power_domain
;
1725 lockdep_assert_held(&dev_priv
->pps_mutex
);
1727 if (!is_edp(intel_dp
))
1730 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1731 port_name(dp_to_dig_port(intel_dp
)->port
));
1733 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1734 port_name(dp_to_dig_port(intel_dp
)->port
));
1736 pp
= ironlake_get_pp_control(intel_dp
);
1737 /* We need to switch off panel power _and_ force vdd, for otherwise some
1738 * panels get very unhappy and cease to work. */
1739 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1742 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1744 intel_dp
->want_panel_vdd
= false;
1746 I915_WRITE(pp_ctrl_reg
, pp
);
1747 POSTING_READ(pp_ctrl_reg
);
1749 intel_dp
->last_power_cycle
= jiffies
;
1750 wait_panel_off(intel_dp
);
1752 /* We got a reference when we enabled the VDD. */
1753 power_domain
= intel_display_port_power_domain(intel_encoder
);
1754 intel_display_power_put(dev_priv
, power_domain
);
1757 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1759 if (!is_edp(intel_dp
))
1763 edp_panel_off(intel_dp
);
1764 pps_unlock(intel_dp
);
1767 /* Enable backlight in the panel power control. */
1768 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1770 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1771 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 * If we enable the backlight right away following a panel power
1778 * on, we may see slight flicker as the panel syncs with the eDP
1779 * link. So delay a bit to make sure the image is solid before
1780 * allowing it to appear.
1782 wait_backlight_on(intel_dp
);
1786 pp
= ironlake_get_pp_control(intel_dp
);
1787 pp
|= EDP_BLC_ENABLE
;
1789 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1791 I915_WRITE(pp_ctrl_reg
, pp
);
1792 POSTING_READ(pp_ctrl_reg
);
1794 pps_unlock(intel_dp
);
1797 /* Enable backlight PWM and backlight PP control. */
1798 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1800 if (!is_edp(intel_dp
))
1803 DRM_DEBUG_KMS("\n");
1805 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1806 _intel_edp_backlight_on(intel_dp
);
1809 /* Disable backlight in the panel power control. */
1810 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1812 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1817 if (!is_edp(intel_dp
))
1822 pp
= ironlake_get_pp_control(intel_dp
);
1823 pp
&= ~EDP_BLC_ENABLE
;
1825 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1827 I915_WRITE(pp_ctrl_reg
, pp
);
1828 POSTING_READ(pp_ctrl_reg
);
1830 pps_unlock(intel_dp
);
1832 intel_dp
->last_backlight_off
= jiffies
;
1833 edp_wait_backlight_off(intel_dp
);
1836 /* Disable backlight PP control and backlight PWM. */
1837 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1839 if (!is_edp(intel_dp
))
1842 DRM_DEBUG_KMS("\n");
1844 _intel_edp_backlight_off(intel_dp
);
1845 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1849 * Hook for controlling the panel power control backlight through the bl_power
1850 * sysfs attribute. Take care to handle multiple calls.
1852 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1855 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1859 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1860 pps_unlock(intel_dp
);
1862 if (is_enabled
== enable
)
1865 DRM_DEBUG_KMS("panel power control backlight %s\n",
1866 enable
? "enable" : "disable");
1869 _intel_edp_backlight_on(intel_dp
);
1871 _intel_edp_backlight_off(intel_dp
);
1874 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1876 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1877 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1878 struct drm_device
*dev
= crtc
->dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1882 assert_pipe_disabled(dev_priv
,
1883 to_intel_crtc(crtc
)->pipe
);
1885 DRM_DEBUG_KMS("\n");
1886 dpa_ctl
= I915_READ(DP_A
);
1887 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1888 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1890 /* We don't adjust intel_dp->DP while tearing down the link, to
1891 * facilitate link retraining (e.g. after hotplug). Hence clear all
1892 * enable bits here to ensure that we don't enable too much. */
1893 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1894 intel_dp
->DP
|= DP_PLL_ENABLE
;
1895 I915_WRITE(DP_A
, intel_dp
->DP
);
1900 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1902 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1903 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1904 struct drm_device
*dev
= crtc
->dev
;
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1908 assert_pipe_disabled(dev_priv
,
1909 to_intel_crtc(crtc
)->pipe
);
1911 dpa_ctl
= I915_READ(DP_A
);
1912 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1913 "dp pll off, should be on\n");
1914 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1916 /* We can't rely on the value tracked for the DP register in
1917 * intel_dp->DP because link_down must not change that (otherwise link
1918 * re-training will fail. */
1919 dpa_ctl
&= ~DP_PLL_ENABLE
;
1920 I915_WRITE(DP_A
, dpa_ctl
);
1925 /* If the sink supports it, try to set the power state appropriately */
1926 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1930 /* Should have a valid DPCD by this point */
1931 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1934 if (mode
!= DRM_MODE_DPMS_ON
) {
1935 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1939 * When turning on, we need to retry for 1ms to give the sink
1942 for (i
= 0; i
< 3; i
++) {
1943 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1952 DRM_DEBUG_KMS("failed to %s sink power state\n",
1953 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1956 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1959 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1960 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1961 struct drm_device
*dev
= encoder
->base
.dev
;
1962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1963 enum intel_display_power_domain power_domain
;
1966 power_domain
= intel_display_port_power_domain(encoder
);
1967 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
1970 tmp
= I915_READ(intel_dp
->output_reg
);
1972 if (!(tmp
& DP_PORT_EN
))
1975 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1976 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1977 } else if (IS_CHERRYVIEW(dev
)) {
1978 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1979 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1980 *pipe
= PORT_TO_PIPE(tmp
);
1986 switch (intel_dp
->output_reg
) {
1988 trans_sel
= TRANS_DP_PORT_SEL_B
;
1991 trans_sel
= TRANS_DP_PORT_SEL_C
;
1994 trans_sel
= TRANS_DP_PORT_SEL_D
;
2000 for_each_pipe(dev_priv
, i
) {
2001 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
2002 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
2008 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2009 intel_dp
->output_reg
);
2015 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2016 struct intel_crtc_config
*pipe_config
)
2018 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2020 struct drm_device
*dev
= encoder
->base
.dev
;
2021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2023 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2026 tmp
= I915_READ(intel_dp
->output_reg
);
2027 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
2028 pipe_config
->has_audio
= true;
2030 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2031 if (tmp
& DP_SYNC_HS_HIGH
)
2032 flags
|= DRM_MODE_FLAG_PHSYNC
;
2034 flags
|= DRM_MODE_FLAG_NHSYNC
;
2036 if (tmp
& DP_SYNC_VS_HIGH
)
2037 flags
|= DRM_MODE_FLAG_PVSYNC
;
2039 flags
|= DRM_MODE_FLAG_NVSYNC
;
2041 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2042 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2043 flags
|= DRM_MODE_FLAG_PHSYNC
;
2045 flags
|= DRM_MODE_FLAG_NHSYNC
;
2047 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2048 flags
|= DRM_MODE_FLAG_PVSYNC
;
2050 flags
|= DRM_MODE_FLAG_NVSYNC
;
2053 pipe_config
->adjusted_mode
.flags
|= flags
;
2055 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2056 tmp
& DP_COLOR_RANGE_16_235
)
2057 pipe_config
->limited_color_range
= true;
2059 pipe_config
->has_dp_encoder
= true;
2061 intel_dp_get_m_n(crtc
, pipe_config
);
2063 if (port
== PORT_A
) {
2064 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2065 pipe_config
->port_clock
= 162000;
2067 pipe_config
->port_clock
= 270000;
2070 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2071 &pipe_config
->dp_m_n
);
2073 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2074 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2076 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
2078 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2079 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2081 * This is a big fat ugly hack.
2083 * Some machines in UEFI boot mode provide us a VBT that has 18
2084 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2085 * unknown we fail to light up. Yet the same BIOS boots up with
2086 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2087 * max, not what it tells us to use.
2089 * Note: This will still be broken if the eDP panel is not lit
2090 * up by the BIOS, and thus we can't get the mode at module
2093 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2094 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2095 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2099 static void intel_disable_dp(struct intel_encoder
*encoder
)
2101 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2102 struct drm_device
*dev
= encoder
->base
.dev
;
2103 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2105 if (crtc
->config
.has_audio
)
2106 intel_audio_codec_disable(encoder
);
2108 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2109 intel_psr_disable(intel_dp
);
2111 /* Make sure the panel is off before trying to change the mode. But also
2112 * ensure that we have vdd while we switch off the panel. */
2113 intel_edp_panel_vdd_on(intel_dp
);
2114 intel_edp_backlight_off(intel_dp
);
2115 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2116 intel_edp_panel_off(intel_dp
);
2118 /* disable the port before the pipe on g4x */
2119 if (INTEL_INFO(dev
)->gen
< 5)
2120 intel_dp_link_down(intel_dp
);
2123 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2125 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2126 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2128 intel_dp_link_down(intel_dp
);
2130 ironlake_edp_pll_off(intel_dp
);
2133 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2135 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2137 intel_dp_link_down(intel_dp
);
2140 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2142 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2143 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2144 struct drm_device
*dev
= encoder
->base
.dev
;
2145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 struct intel_crtc
*intel_crtc
=
2147 to_intel_crtc(encoder
->base
.crtc
);
2148 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2149 enum pipe pipe
= intel_crtc
->pipe
;
2152 intel_dp_link_down(intel_dp
);
2154 mutex_lock(&dev_priv
->dpio_lock
);
2156 /* Propagate soft reset to data lane reset */
2157 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2158 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2159 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2161 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2162 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2163 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2165 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2166 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2167 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2169 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2170 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2171 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2173 mutex_unlock(&dev_priv
->dpio_lock
);
2177 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2179 uint8_t dp_train_pat
)
2181 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2182 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2184 enum port port
= intel_dig_port
->port
;
2187 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2189 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2190 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2192 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2194 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2195 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2196 case DP_TRAINING_PATTERN_DISABLE
:
2197 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2200 case DP_TRAINING_PATTERN_1
:
2201 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2203 case DP_TRAINING_PATTERN_2
:
2204 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2206 case DP_TRAINING_PATTERN_3
:
2207 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2210 I915_WRITE(DP_TP_CTL(port
), temp
);
2212 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2213 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2215 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2216 case DP_TRAINING_PATTERN_DISABLE
:
2217 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2219 case DP_TRAINING_PATTERN_1
:
2220 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2222 case DP_TRAINING_PATTERN_2
:
2223 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2225 case DP_TRAINING_PATTERN_3
:
2226 DRM_ERROR("DP training pattern 3 not supported\n");
2227 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2232 if (IS_CHERRYVIEW(dev
))
2233 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2235 *DP
&= ~DP_LINK_TRAIN_MASK
;
2237 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2238 case DP_TRAINING_PATTERN_DISABLE
:
2239 *DP
|= DP_LINK_TRAIN_OFF
;
2241 case DP_TRAINING_PATTERN_1
:
2242 *DP
|= DP_LINK_TRAIN_PAT_1
;
2244 case DP_TRAINING_PATTERN_2
:
2245 *DP
|= DP_LINK_TRAIN_PAT_2
;
2247 case DP_TRAINING_PATTERN_3
:
2248 if (IS_CHERRYVIEW(dev
)) {
2249 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2251 DRM_ERROR("DP training pattern 3 not supported\n");
2252 *DP
|= DP_LINK_TRAIN_PAT_2
;
2259 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2261 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2264 /* enable with pattern 1 (as per spec) */
2265 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2266 DP_TRAINING_PATTERN_1
);
2268 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2269 POSTING_READ(intel_dp
->output_reg
);
2272 * Magic for VLV/CHV. We _must_ first set up the register
2273 * without actually enabling the port, and then do another
2274 * write to enable the port. Otherwise link training will
2275 * fail when the power sequencer is freshly used for this port.
2277 intel_dp
->DP
|= DP_PORT_EN
;
2279 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2280 POSTING_READ(intel_dp
->output_reg
);
2283 static void intel_enable_dp(struct intel_encoder
*encoder
)
2285 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2286 struct drm_device
*dev
= encoder
->base
.dev
;
2287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2288 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2289 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2291 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2296 if (IS_VALLEYVIEW(dev
))
2297 vlv_init_panel_power_sequencer(intel_dp
);
2299 intel_dp_enable_port(intel_dp
);
2301 edp_panel_vdd_on(intel_dp
);
2302 edp_panel_on(intel_dp
);
2303 edp_panel_vdd_off(intel_dp
, true);
2305 pps_unlock(intel_dp
);
2307 if (IS_VALLEYVIEW(dev
))
2308 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2310 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2311 intel_dp_start_link_train(intel_dp
);
2312 intel_dp_complete_link_train(intel_dp
);
2313 intel_dp_stop_link_train(intel_dp
);
2315 if (crtc
->config
.has_audio
) {
2316 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2317 pipe_name(crtc
->pipe
));
2318 intel_audio_codec_enable(encoder
);
2322 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2324 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2326 intel_enable_dp(encoder
);
2327 intel_edp_backlight_on(intel_dp
);
2330 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2332 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2334 intel_edp_backlight_on(intel_dp
);
2335 intel_psr_enable(intel_dp
);
2338 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2340 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2341 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2343 intel_dp_prepare(encoder
);
2345 /* Only ilk+ has port A */
2346 if (dport
->port
== PORT_A
) {
2347 ironlake_set_pll_cpu_edp(intel_dp
);
2348 ironlake_edp_pll_on(intel_dp
);
2352 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2354 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2355 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2356 enum pipe pipe
= intel_dp
->pps_pipe
;
2357 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2359 edp_panel_vdd_off_sync(intel_dp
);
2362 * VLV seems to get confused when multiple power seqeuencers
2363 * have the same port selected (even if only one has power/vdd
2364 * enabled). The failure manifests as vlv_wait_port_ready() failing
2365 * CHV on the other hand doesn't seem to mind having the same port
2366 * selected in multiple power seqeuencers, but let's clear the
2367 * port select always when logically disconnecting a power sequencer
2370 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2371 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2372 I915_WRITE(pp_on_reg
, 0);
2373 POSTING_READ(pp_on_reg
);
2375 intel_dp
->pps_pipe
= INVALID_PIPE
;
2378 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2382 struct intel_encoder
*encoder
;
2384 lockdep_assert_held(&dev_priv
->pps_mutex
);
2386 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2389 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2391 struct intel_dp
*intel_dp
;
2394 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2397 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2398 port
= dp_to_dig_port(intel_dp
)->port
;
2400 if (intel_dp
->pps_pipe
!= pipe
)
2403 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2404 pipe_name(pipe
), port_name(port
));
2406 WARN(encoder
->connectors_active
,
2407 "stealing pipe %c power sequencer from active eDP port %c\n",
2408 pipe_name(pipe
), port_name(port
));
2410 /* make sure vdd is off before we steal it */
2411 vlv_detach_power_sequencer(intel_dp
);
2415 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2417 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2418 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2419 struct drm_device
*dev
= encoder
->base
.dev
;
2420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2421 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2423 lockdep_assert_held(&dev_priv
->pps_mutex
);
2425 if (!is_edp(intel_dp
))
2428 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2432 * If another power sequencer was being used on this
2433 * port previously make sure to turn off vdd there while
2434 * we still have control of it.
2436 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2437 vlv_detach_power_sequencer(intel_dp
);
2440 * We may be stealing the power
2441 * sequencer from another port.
2443 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2445 /* now it's all ours */
2446 intel_dp
->pps_pipe
= crtc
->pipe
;
2448 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2449 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2451 /* init power sequencer on this pipe and port */
2452 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2453 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2456 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2458 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2459 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2460 struct drm_device
*dev
= encoder
->base
.dev
;
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2463 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2464 int pipe
= intel_crtc
->pipe
;
2467 mutex_lock(&dev_priv
->dpio_lock
);
2469 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2476 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2477 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2478 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2480 mutex_unlock(&dev_priv
->dpio_lock
);
2482 intel_enable_dp(encoder
);
2485 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2487 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2488 struct drm_device
*dev
= encoder
->base
.dev
;
2489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2490 struct intel_crtc
*intel_crtc
=
2491 to_intel_crtc(encoder
->base
.crtc
);
2492 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2493 int pipe
= intel_crtc
->pipe
;
2495 intel_dp_prepare(encoder
);
2497 /* Program Tx lane resets to default */
2498 mutex_lock(&dev_priv
->dpio_lock
);
2499 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2500 DPIO_PCS_TX_LANE2_RESET
|
2501 DPIO_PCS_TX_LANE1_RESET
);
2502 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2503 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2504 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2505 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2506 DPIO_PCS_CLK_SOFT_RESET
);
2508 /* Fix up inter-pair skew failure */
2509 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2510 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2511 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2512 mutex_unlock(&dev_priv
->dpio_lock
);
2515 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2517 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2518 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2519 struct drm_device
*dev
= encoder
->base
.dev
;
2520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 struct intel_crtc
*intel_crtc
=
2522 to_intel_crtc(encoder
->base
.crtc
);
2523 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2524 int pipe
= intel_crtc
->pipe
;
2528 mutex_lock(&dev_priv
->dpio_lock
);
2530 /* allow hardware to manage TX FIFO reset source */
2531 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2532 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2533 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2535 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2536 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2537 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2539 /* Deassert soft data lane reset*/
2540 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2541 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2542 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2544 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2545 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2546 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2548 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2549 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2550 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2552 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2553 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2554 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2556 /* Program Tx lane latency optimal setting*/
2557 for (i
= 0; i
< 4; i
++) {
2558 /* Set the latency optimal bit */
2559 data
= (i
== 1) ? 0x0 : 0x6;
2560 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2561 data
<< DPIO_FRC_LATENCY_SHFIT
);
2563 /* Set the upar bit */
2564 data
= (i
== 1) ? 0x0 : 0x1;
2565 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2566 data
<< DPIO_UPAR_SHIFT
);
2569 /* Data lane stagger programming */
2570 /* FIXME: Fix up value only after power analysis */
2572 mutex_unlock(&dev_priv
->dpio_lock
);
2574 intel_enable_dp(encoder
);
2577 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2579 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2580 struct drm_device
*dev
= encoder
->base
.dev
;
2581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2582 struct intel_crtc
*intel_crtc
=
2583 to_intel_crtc(encoder
->base
.crtc
);
2584 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2585 enum pipe pipe
= intel_crtc
->pipe
;
2588 intel_dp_prepare(encoder
);
2590 mutex_lock(&dev_priv
->dpio_lock
);
2592 /* program left/right clock distribution */
2593 if (pipe
!= PIPE_B
) {
2594 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2595 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2597 val
|= CHV_BUFLEFTENA1_FORCE
;
2599 val
|= CHV_BUFRIGHTENA1_FORCE
;
2600 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2602 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2603 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2605 val
|= CHV_BUFLEFTENA2_FORCE
;
2607 val
|= CHV_BUFRIGHTENA2_FORCE
;
2608 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2611 /* program clock channel usage */
2612 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2613 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2615 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2617 val
|= CHV_PCS_USEDCLKCHANNEL
;
2618 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2620 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2621 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2623 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2625 val
|= CHV_PCS_USEDCLKCHANNEL
;
2626 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2629 * This a a bit weird since generally CL
2630 * matches the pipe, but here we need to
2631 * pick the CL based on the port.
2633 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2635 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2637 val
|= CHV_CMN_USEDCLKCHANNEL
;
2638 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2640 mutex_unlock(&dev_priv
->dpio_lock
);
2644 * Native read with retry for link status and receiver capability reads for
2645 * cases where the sink may still be asleep.
2647 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2648 * supposed to retry 3 times per the spec.
2651 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2652 void *buffer
, size_t size
)
2658 * Sometime we just get the same incorrect byte repeated
2659 * over the entire buffer. Doing just one throw away read
2660 * initially seems to "solve" it.
2662 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2664 for (i
= 0; i
< 3; i
++) {
2665 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2675 * Fetch AUX CH registers 0x202 - 0x207 which contain
2676 * link status information
2679 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2681 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2684 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2687 /* These are source-specific values. */
2689 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2691 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2692 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2694 if (INTEL_INFO(dev
)->gen
>= 9)
2695 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2696 else if (IS_VALLEYVIEW(dev
))
2697 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2698 else if (IS_GEN7(dev
) && port
== PORT_A
)
2699 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2700 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2701 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2703 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2707 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2709 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2710 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2712 if (INTEL_INFO(dev
)->gen
>= 9) {
2713 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2714 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2715 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2716 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2717 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2718 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2719 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2721 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2723 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2724 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2726 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2727 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2728 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2730 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2731 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2733 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2735 } else if (IS_VALLEYVIEW(dev
)) {
2736 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2737 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2738 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2740 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2741 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2742 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2743 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2745 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2747 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2748 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2749 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2750 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2751 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2752 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2753 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2755 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2758 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2759 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2760 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2761 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2762 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2763 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2764 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2765 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2767 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2772 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2774 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2776 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2777 struct intel_crtc
*intel_crtc
=
2778 to_intel_crtc(dport
->base
.base
.crtc
);
2779 unsigned long demph_reg_value
, preemph_reg_value
,
2780 uniqtranscale_reg_value
;
2781 uint8_t train_set
= intel_dp
->train_set
[0];
2782 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2783 int pipe
= intel_crtc
->pipe
;
2785 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2786 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2787 preemph_reg_value
= 0x0004000;
2788 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2789 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2790 demph_reg_value
= 0x2B405555;
2791 uniqtranscale_reg_value
= 0x552AB83A;
2793 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2794 demph_reg_value
= 0x2B404040;
2795 uniqtranscale_reg_value
= 0x5548B83A;
2797 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2798 demph_reg_value
= 0x2B245555;
2799 uniqtranscale_reg_value
= 0x5560B83A;
2801 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2802 demph_reg_value
= 0x2B405555;
2803 uniqtranscale_reg_value
= 0x5598DA3A;
2809 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2810 preemph_reg_value
= 0x0002000;
2811 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2812 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2813 demph_reg_value
= 0x2B404040;
2814 uniqtranscale_reg_value
= 0x5552B83A;
2816 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2817 demph_reg_value
= 0x2B404848;
2818 uniqtranscale_reg_value
= 0x5580B83A;
2820 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2821 demph_reg_value
= 0x2B404040;
2822 uniqtranscale_reg_value
= 0x55ADDA3A;
2828 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2829 preemph_reg_value
= 0x0000000;
2830 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2831 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2832 demph_reg_value
= 0x2B305555;
2833 uniqtranscale_reg_value
= 0x5570B83A;
2835 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2836 demph_reg_value
= 0x2B2B4040;
2837 uniqtranscale_reg_value
= 0x55ADDA3A;
2843 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2844 preemph_reg_value
= 0x0006000;
2845 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2847 demph_reg_value
= 0x1B405555;
2848 uniqtranscale_reg_value
= 0x55ADDA3A;
2858 mutex_lock(&dev_priv
->dpio_lock
);
2859 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2860 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2861 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2862 uniqtranscale_reg_value
);
2863 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
2864 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
2865 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
2866 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
2867 mutex_unlock(&dev_priv
->dpio_lock
);
2872 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
2874 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2876 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2877 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
2878 u32 deemph_reg_value
, margin_reg_value
, val
;
2879 uint8_t train_set
= intel_dp
->train_set
[0];
2880 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2881 enum pipe pipe
= intel_crtc
->pipe
;
2884 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2885 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2886 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2888 deemph_reg_value
= 128;
2889 margin_reg_value
= 52;
2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2892 deemph_reg_value
= 128;
2893 margin_reg_value
= 77;
2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2896 deemph_reg_value
= 128;
2897 margin_reg_value
= 102;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2900 deemph_reg_value
= 128;
2901 margin_reg_value
= 154;
2902 /* FIXME extra to set for 1200 */
2908 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2909 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2911 deemph_reg_value
= 85;
2912 margin_reg_value
= 78;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2915 deemph_reg_value
= 85;
2916 margin_reg_value
= 116;
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2919 deemph_reg_value
= 85;
2920 margin_reg_value
= 154;
2926 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2927 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2929 deemph_reg_value
= 64;
2930 margin_reg_value
= 104;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2933 deemph_reg_value
= 64;
2934 margin_reg_value
= 154;
2940 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2941 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2943 deemph_reg_value
= 43;
2944 margin_reg_value
= 154;
2954 mutex_lock(&dev_priv
->dpio_lock
);
2956 /* Clear calc init */
2957 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
2958 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2959 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
2960 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
2961 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
2963 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
2964 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
2965 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
2966 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
2967 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
2969 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
2970 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
2971 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
2972 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
2974 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
2975 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
2976 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
2977 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
2979 /* Program swing deemph */
2980 for (i
= 0; i
< 4; i
++) {
2981 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
2982 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
2983 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
2984 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
2987 /* Program swing margin */
2988 for (i
= 0; i
< 4; i
++) {
2989 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
2990 val
&= ~DPIO_SWING_MARGIN000_MASK
;
2991 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
2992 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
2995 /* Disable unique transition scale */
2996 for (i
= 0; i
< 4; i
++) {
2997 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
2998 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
2999 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3002 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3003 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3004 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3005 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3008 * The document said it needs to set bit 27 for ch0 and bit 26
3009 * for ch1. Might be a typo in the doc.
3010 * For now, for this unique transition scale selection, set bit
3011 * 27 for ch0 and ch1.
3013 for (i
= 0; i
< 4; i
++) {
3014 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3015 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3016 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3019 for (i
= 0; i
< 4; i
++) {
3020 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3021 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3022 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3023 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3027 /* Start swing calculation */
3028 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3029 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3030 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3032 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3033 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3034 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3037 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3038 val
|= DPIO_LRC_BYPASS
;
3039 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3041 mutex_unlock(&dev_priv
->dpio_lock
);
3047 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3048 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3053 uint8_t voltage_max
;
3054 uint8_t preemph_max
;
3056 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3057 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3058 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3066 voltage_max
= intel_dp_voltage_max(intel_dp
);
3067 if (v
>= voltage_max
)
3068 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3070 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3071 if (p
>= preemph_max
)
3072 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3074 for (lane
= 0; lane
< 4; lane
++)
3075 intel_dp
->train_set
[lane
] = v
| p
;
3079 intel_gen4_signal_levels(uint8_t train_set
)
3081 uint32_t signal_levels
= 0;
3083 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3086 signal_levels
|= DP_VOLTAGE_0_4
;
3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3089 signal_levels
|= DP_VOLTAGE_0_6
;
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3092 signal_levels
|= DP_VOLTAGE_0_8
;
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3095 signal_levels
|= DP_VOLTAGE_1_2
;
3098 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3099 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3101 signal_levels
|= DP_PRE_EMPHASIS_0
;
3103 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3104 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3106 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3107 signal_levels
|= DP_PRE_EMPHASIS_6
;
3109 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3110 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3113 return signal_levels
;
3116 /* Gen6's DP voltage swing and pre-emphasis control */
3118 intel_gen6_edp_signal_levels(uint8_t train_set
)
3120 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3121 DP_TRAIN_PRE_EMPHASIS_MASK
);
3122 switch (signal_levels
) {
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3125 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3127 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3130 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3133 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3136 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3138 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3139 "0x%x\n", signal_levels
);
3140 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3144 /* Gen7's DP voltage swing and pre-emphasis control */
3146 intel_gen7_edp_signal_levels(uint8_t train_set
)
3148 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3149 DP_TRAIN_PRE_EMPHASIS_MASK
);
3150 switch (signal_levels
) {
3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3152 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3154 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3156 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3159 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3161 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3164 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3166 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3169 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3170 "0x%x\n", signal_levels
);
3171 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3175 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3177 intel_hsw_signal_levels(uint8_t train_set
)
3179 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3180 DP_TRAIN_PRE_EMPHASIS_MASK
);
3181 switch (signal_levels
) {
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3183 return DDI_BUF_TRANS_SELECT(0);
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3185 return DDI_BUF_TRANS_SELECT(1);
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3187 return DDI_BUF_TRANS_SELECT(2);
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3189 return DDI_BUF_TRANS_SELECT(3);
3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3192 return DDI_BUF_TRANS_SELECT(4);
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3194 return DDI_BUF_TRANS_SELECT(5);
3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3196 return DDI_BUF_TRANS_SELECT(6);
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3199 return DDI_BUF_TRANS_SELECT(7);
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3201 return DDI_BUF_TRANS_SELECT(8);
3203 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3204 "0x%x\n", signal_levels
);
3205 return DDI_BUF_TRANS_SELECT(0);
3209 /* Properly updates "DP" with the correct signal levels. */
3211 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3213 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3214 enum port port
= intel_dig_port
->port
;
3215 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3216 uint32_t signal_levels
, mask
;
3217 uint8_t train_set
= intel_dp
->train_set
[0];
3219 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
3220 signal_levels
= intel_hsw_signal_levels(train_set
);
3221 mask
= DDI_BUF_EMP_MASK
;
3222 } else if (IS_CHERRYVIEW(dev
)) {
3223 signal_levels
= intel_chv_signal_levels(intel_dp
);
3225 } else if (IS_VALLEYVIEW(dev
)) {
3226 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3228 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3229 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3230 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3231 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3232 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3233 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3235 signal_levels
= intel_gen4_signal_levels(train_set
);
3236 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3239 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3241 *DP
= (*DP
& ~mask
) | signal_levels
;
3245 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3247 uint8_t dp_train_pat
)
3249 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3250 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3252 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3255 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3257 I915_WRITE(intel_dp
->output_reg
, *DP
);
3258 POSTING_READ(intel_dp
->output_reg
);
3260 buf
[0] = dp_train_pat
;
3261 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3262 DP_TRAINING_PATTERN_DISABLE
) {
3263 /* don't write DP_TRAINING_LANEx_SET on disable */
3266 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3267 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3268 len
= intel_dp
->lane_count
+ 1;
3271 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3278 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3279 uint8_t dp_train_pat
)
3281 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3282 intel_dp_set_signal_levels(intel_dp
, DP
);
3283 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3287 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3288 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3290 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3291 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3295 intel_get_adjust_train(intel_dp
, link_status
);
3296 intel_dp_set_signal_levels(intel_dp
, DP
);
3298 I915_WRITE(intel_dp
->output_reg
, *DP
);
3299 POSTING_READ(intel_dp
->output_reg
);
3301 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3302 intel_dp
->train_set
, intel_dp
->lane_count
);
3304 return ret
== intel_dp
->lane_count
;
3307 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3309 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3310 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3312 enum port port
= intel_dig_port
->port
;
3318 val
= I915_READ(DP_TP_CTL(port
));
3319 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3320 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3321 I915_WRITE(DP_TP_CTL(port
), val
);
3324 * On PORT_A we can have only eDP in SST mode. There the only reason
3325 * we need to set idle transmission mode is to work around a HW issue
3326 * where we enable the pipe while not in idle link-training mode.
3327 * In this case there is requirement to wait for a minimum number of
3328 * idle patterns to be sent.
3333 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3335 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3338 /* Enable corresponding port and start training pattern 1 */
3340 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3342 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3343 struct drm_device
*dev
= encoder
->dev
;
3346 int voltage_tries
, loop_tries
;
3347 uint32_t DP
= intel_dp
->DP
;
3348 uint8_t link_config
[2];
3351 intel_ddi_prepare_link_retrain(encoder
);
3353 /* Write the link configuration data */
3354 link_config
[0] = intel_dp
->link_bw
;
3355 link_config
[1] = intel_dp
->lane_count
;
3356 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3357 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3358 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3361 link_config
[1] = DP_SET_ANSI_8B10B
;
3362 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3366 /* clock recovery */
3367 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3368 DP_TRAINING_PATTERN_1
|
3369 DP_LINK_SCRAMBLING_DISABLE
)) {
3370 DRM_ERROR("failed to enable link training\n");
3378 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3380 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3381 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3382 DRM_ERROR("failed to get link status\n");
3386 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3387 DRM_DEBUG_KMS("clock recovery OK\n");
3391 /* Check to see if we've tried the max voltage */
3392 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3393 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3395 if (i
== intel_dp
->lane_count
) {
3397 if (loop_tries
== 5) {
3398 DRM_ERROR("too many full retries, give up\n");
3401 intel_dp_reset_link_train(intel_dp
, &DP
,
3402 DP_TRAINING_PATTERN_1
|
3403 DP_LINK_SCRAMBLING_DISABLE
);
3408 /* Check to see if we've tried the same voltage 5 times */
3409 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3411 if (voltage_tries
== 5) {
3412 DRM_ERROR("too many voltage retries, give up\n");
3417 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3419 /* Update training set as requested by target */
3420 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3421 DRM_ERROR("failed to update link training\n");
3430 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3432 bool channel_eq
= false;
3433 int tries
, cr_tries
;
3434 uint32_t DP
= intel_dp
->DP
;
3435 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3437 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3438 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3439 training_pattern
= DP_TRAINING_PATTERN_3
;
3441 /* channel equalization */
3442 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3444 DP_LINK_SCRAMBLING_DISABLE
)) {
3445 DRM_ERROR("failed to start channel equalization\n");
3453 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3456 DRM_ERROR("failed to train DP, aborting\n");
3460 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3461 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3462 DRM_ERROR("failed to get link status\n");
3466 /* Make sure clock is still ok */
3467 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3468 intel_dp_start_link_train(intel_dp
);
3469 intel_dp_set_link_train(intel_dp
, &DP
,
3471 DP_LINK_SCRAMBLING_DISABLE
);
3476 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3481 /* Try 5 times, then try clock recovery if that fails */
3483 intel_dp_start_link_train(intel_dp
);
3484 intel_dp_set_link_train(intel_dp
, &DP
,
3486 DP_LINK_SCRAMBLING_DISABLE
);
3492 /* Update training set as requested by target */
3493 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3494 DRM_ERROR("failed to update link training\n");
3500 intel_dp_set_idle_link_train(intel_dp
);
3505 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3509 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3511 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3512 DP_TRAINING_PATTERN_DISABLE
);
3516 intel_dp_link_down(struct intel_dp
*intel_dp
)
3518 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3519 enum port port
= intel_dig_port
->port
;
3520 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3522 struct intel_crtc
*intel_crtc
=
3523 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3524 uint32_t DP
= intel_dp
->DP
;
3526 if (WARN_ON(HAS_DDI(dev
)))
3529 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3532 DRM_DEBUG_KMS("\n");
3534 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3535 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3536 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3538 if (IS_CHERRYVIEW(dev
))
3539 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3541 DP
&= ~DP_LINK_TRAIN_MASK
;
3542 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3544 POSTING_READ(intel_dp
->output_reg
);
3546 if (HAS_PCH_IBX(dev
) &&
3547 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3548 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3550 /* Hardware workaround: leaving our transcoder select
3551 * set to transcoder B while it's off will prevent the
3552 * corresponding HDMI output on transcoder A.
3554 * Combine this with another hardware workaround:
3555 * transcoder select bit can only be cleared while the
3558 DP
&= ~DP_PIPEB_SELECT
;
3559 I915_WRITE(intel_dp
->output_reg
, DP
);
3561 /* Changes to enable or select take place the vblank
3562 * after being written.
3564 if (WARN_ON(crtc
== NULL
)) {
3565 /* We should never try to disable a port without a crtc
3566 * attached. For paranoia keep the code around for a
3568 POSTING_READ(intel_dp
->output_reg
);
3571 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3574 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3575 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3576 POSTING_READ(intel_dp
->output_reg
);
3577 msleep(intel_dp
->panel_power_down_delay
);
3581 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3583 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3584 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3587 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3588 sizeof(intel_dp
->dpcd
)) < 0)
3589 return false; /* aux transfer failed */
3591 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3593 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3594 return false; /* DPCD not present */
3596 /* Check if the panel supports PSR */
3597 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3598 if (is_edp(intel_dp
)) {
3599 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3601 sizeof(intel_dp
->psr_dpcd
));
3602 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3603 dev_priv
->psr
.sink_support
= true;
3604 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3608 /* Training Pattern 3 support, both source and sink */
3609 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3610 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3611 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3612 intel_dp
->use_tps3
= true;
3613 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3615 intel_dp
->use_tps3
= false;
3617 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3618 DP_DWN_STRM_PORT_PRESENT
))
3619 return true; /* native DP sink */
3621 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3622 return true; /* no per-port downstream info */
3624 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3625 intel_dp
->downstream_ports
,
3626 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3627 return false; /* downstream port status fetch failed */
3633 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3637 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3640 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3641 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3642 buf
[0], buf
[1], buf
[2]);
3644 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3645 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3646 buf
[0], buf
[1], buf
[2]);
3650 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3654 if (!intel_dp
->can_mst
)
3657 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3660 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3661 if (buf
[0] & DP_MST_CAP
) {
3662 DRM_DEBUG_KMS("Sink is MST capable\n");
3663 intel_dp
->is_mst
= true;
3665 DRM_DEBUG_KMS("Sink is not MST capable\n");
3666 intel_dp
->is_mst
= false;
3670 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3671 return intel_dp
->is_mst
;
3674 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3676 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3677 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3678 struct intel_crtc
*intel_crtc
=
3679 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3684 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3687 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3690 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3693 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3694 buf
| DP_TEST_SINK_START
) < 0)
3697 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3699 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
3702 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3703 DP_TEST_SINK_MISC
, &buf
) < 0)
3705 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3706 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
3708 if (attempts
== 0) {
3709 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3713 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3716 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3718 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3719 buf
& ~DP_TEST_SINK_START
) < 0)
3726 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3728 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3729 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3730 sink_irq_vector
, 1) == 1;
3734 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3738 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3740 sink_irq_vector
, 14);
3748 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3750 /* NAK by default */
3751 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3755 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3759 if (intel_dp
->is_mst
) {
3764 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3768 /* check link status - esi[10] = 0x200c */
3769 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3770 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3771 intel_dp_start_link_train(intel_dp
);
3772 intel_dp_complete_link_train(intel_dp
);
3773 intel_dp_stop_link_train(intel_dp
);
3776 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3777 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3780 for (retry
= 0; retry
< 3; retry
++) {
3782 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3783 DP_SINK_COUNT_ESI
+1,
3790 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3792 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3800 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3801 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3802 intel_dp
->is_mst
= false;
3803 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3804 /* send a hotplug event */
3805 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3812 * According to DP spec
3815 * 2. Configure link according to Receiver Capabilities
3816 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3817 * 4. Check link status on receipt of hot-plug interrupt
3820 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3822 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3823 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3825 u8 link_status
[DP_LINK_STATUS_SIZE
];
3827 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3829 if (!intel_encoder
->connectors_active
)
3832 if (WARN_ON(!intel_encoder
->base
.crtc
))
3835 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3838 /* Try to read receiver status if the link appears to be up */
3839 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3843 /* Now read the DPCD to see if it's actually running */
3844 if (!intel_dp_get_dpcd(intel_dp
)) {
3848 /* Try to read the source of the interrupt */
3849 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3850 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3851 /* Clear interrupt source */
3852 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3853 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3856 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3857 intel_dp_handle_test_request(intel_dp
);
3858 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3859 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3862 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3863 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3864 intel_encoder
->base
.name
);
3865 intel_dp_start_link_train(intel_dp
);
3866 intel_dp_complete_link_train(intel_dp
);
3867 intel_dp_stop_link_train(intel_dp
);
3871 /* XXX this is probably wrong for multiple downstream ports */
3872 static enum drm_connector_status
3873 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3875 uint8_t *dpcd
= intel_dp
->dpcd
;
3878 if (!intel_dp_get_dpcd(intel_dp
))
3879 return connector_status_disconnected
;
3881 /* if there's no downstream port, we're done */
3882 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3883 return connector_status_connected
;
3885 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3886 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3887 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3890 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3892 return connector_status_unknown
;
3894 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
3895 : connector_status_disconnected
;
3898 /* If no HPD, poke DDC gently */
3899 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
3900 return connector_status_connected
;
3902 /* Well we tried, say unknown for unreliable port types */
3903 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
3904 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
3905 if (type
== DP_DS_PORT_TYPE_VGA
||
3906 type
== DP_DS_PORT_TYPE_NON_EDID
)
3907 return connector_status_unknown
;
3909 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3910 DP_DWN_STRM_PORT_TYPE_MASK
;
3911 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
3912 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
3913 return connector_status_unknown
;
3916 /* Anything else is out of spec, warn and ignore */
3917 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3918 return connector_status_disconnected
;
3921 static enum drm_connector_status
3922 edp_detect(struct intel_dp
*intel_dp
)
3924 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3925 enum drm_connector_status status
;
3927 status
= intel_panel_detect(dev
);
3928 if (status
== connector_status_unknown
)
3929 status
= connector_status_connected
;
3934 static enum drm_connector_status
3935 ironlake_dp_detect(struct intel_dp
*intel_dp
)
3937 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3939 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3941 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
3942 return connector_status_disconnected
;
3944 return intel_dp_detect_dpcd(intel_dp
);
3947 static int g4x_digital_port_connected(struct drm_device
*dev
,
3948 struct intel_digital_port
*intel_dig_port
)
3950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3953 if (IS_VALLEYVIEW(dev
)) {
3954 switch (intel_dig_port
->port
) {
3956 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
3959 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
3962 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
3968 switch (intel_dig_port
->port
) {
3970 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
3973 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
3976 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
3983 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
3988 static enum drm_connector_status
3989 g4x_dp_detect(struct intel_dp
*intel_dp
)
3991 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3992 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3995 /* Can't disconnect eDP, but you can close the lid... */
3996 if (is_edp(intel_dp
)) {
3997 enum drm_connector_status status
;
3999 status
= intel_panel_detect(dev
);
4000 if (status
== connector_status_unknown
)
4001 status
= connector_status_connected
;
4005 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4007 return connector_status_unknown
;
4009 return connector_status_disconnected
;
4011 return intel_dp_detect_dpcd(intel_dp
);
4014 static struct edid
*
4015 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4017 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4019 /* use cached edid if we have one */
4020 if (intel_connector
->edid
) {
4022 if (IS_ERR(intel_connector
->edid
))
4025 return drm_edid_duplicate(intel_connector
->edid
);
4027 return drm_get_edid(&intel_connector
->base
,
4028 &intel_dp
->aux
.ddc
);
4032 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4034 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4037 edid
= intel_dp_get_edid(intel_dp
);
4038 intel_connector
->detect_edid
= edid
;
4040 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4041 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4043 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4047 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4049 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4051 kfree(intel_connector
->detect_edid
);
4052 intel_connector
->detect_edid
= NULL
;
4054 intel_dp
->has_audio
= false;
4057 static enum intel_display_power_domain
4058 intel_dp_power_get(struct intel_dp
*dp
)
4060 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4061 enum intel_display_power_domain power_domain
;
4063 power_domain
= intel_display_port_power_domain(encoder
);
4064 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4066 return power_domain
;
4070 intel_dp_power_put(struct intel_dp
*dp
,
4071 enum intel_display_power_domain power_domain
)
4073 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4074 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4077 static enum drm_connector_status
4078 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4080 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4081 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4082 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4083 struct drm_device
*dev
= connector
->dev
;
4084 enum drm_connector_status status
;
4085 enum intel_display_power_domain power_domain
;
4088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4089 connector
->base
.id
, connector
->name
);
4090 intel_dp_unset_edid(intel_dp
);
4092 if (intel_dp
->is_mst
) {
4093 /* MST devices are disconnected from a monitor POV */
4094 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4095 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4096 return connector_status_disconnected
;
4099 power_domain
= intel_dp_power_get(intel_dp
);
4101 /* Can't disconnect eDP, but you can close the lid... */
4102 if (is_edp(intel_dp
))
4103 status
= edp_detect(intel_dp
);
4104 else if (HAS_PCH_SPLIT(dev
))
4105 status
= ironlake_dp_detect(intel_dp
);
4107 status
= g4x_dp_detect(intel_dp
);
4108 if (status
!= connector_status_connected
)
4111 intel_dp_probe_oui(intel_dp
);
4113 ret
= intel_dp_probe_mst(intel_dp
);
4115 /* if we are in MST mode then this connector
4116 won't appear connected or have anything with EDID on it */
4117 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4118 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4119 status
= connector_status_disconnected
;
4123 intel_dp_set_edid(intel_dp
);
4125 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4126 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4127 status
= connector_status_connected
;
4130 intel_dp_power_put(intel_dp
, power_domain
);
4135 intel_dp_force(struct drm_connector
*connector
)
4137 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4138 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4139 enum intel_display_power_domain power_domain
;
4141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4142 connector
->base
.id
, connector
->name
);
4143 intel_dp_unset_edid(intel_dp
);
4145 if (connector
->status
!= connector_status_connected
)
4148 power_domain
= intel_dp_power_get(intel_dp
);
4150 intel_dp_set_edid(intel_dp
);
4152 intel_dp_power_put(intel_dp
, power_domain
);
4154 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4155 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4158 static int intel_dp_get_modes(struct drm_connector
*connector
)
4160 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4163 edid
= intel_connector
->detect_edid
;
4165 int ret
= intel_connector_update_modes(connector
, edid
);
4170 /* if eDP has no EDID, fall back to fixed mode */
4171 if (is_edp(intel_attached_dp(connector
)) &&
4172 intel_connector
->panel
.fixed_mode
) {
4173 struct drm_display_mode
*mode
;
4175 mode
= drm_mode_duplicate(connector
->dev
,
4176 intel_connector
->panel
.fixed_mode
);
4178 drm_mode_probed_add(connector
, mode
);
4187 intel_dp_detect_audio(struct drm_connector
*connector
)
4189 bool has_audio
= false;
4192 edid
= to_intel_connector(connector
)->detect_edid
;
4194 has_audio
= drm_detect_monitor_audio(edid
);
4200 intel_dp_set_property(struct drm_connector
*connector
,
4201 struct drm_property
*property
,
4204 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4206 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4207 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4210 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4214 if (property
== dev_priv
->force_audio_property
) {
4218 if (i
== intel_dp
->force_audio
)
4221 intel_dp
->force_audio
= i
;
4223 if (i
== HDMI_AUDIO_AUTO
)
4224 has_audio
= intel_dp_detect_audio(connector
);
4226 has_audio
= (i
== HDMI_AUDIO_ON
);
4228 if (has_audio
== intel_dp
->has_audio
)
4231 intel_dp
->has_audio
= has_audio
;
4235 if (property
== dev_priv
->broadcast_rgb_property
) {
4236 bool old_auto
= intel_dp
->color_range_auto
;
4237 uint32_t old_range
= intel_dp
->color_range
;
4240 case INTEL_BROADCAST_RGB_AUTO
:
4241 intel_dp
->color_range_auto
= true;
4243 case INTEL_BROADCAST_RGB_FULL
:
4244 intel_dp
->color_range_auto
= false;
4245 intel_dp
->color_range
= 0;
4247 case INTEL_BROADCAST_RGB_LIMITED
:
4248 intel_dp
->color_range_auto
= false;
4249 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4255 if (old_auto
== intel_dp
->color_range_auto
&&
4256 old_range
== intel_dp
->color_range
)
4262 if (is_edp(intel_dp
) &&
4263 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4264 if (val
== DRM_MODE_SCALE_NONE
) {
4265 DRM_DEBUG_KMS("no scaling not supported\n");
4269 if (intel_connector
->panel
.fitting_mode
== val
) {
4270 /* the eDP scaling property is not changed */
4273 intel_connector
->panel
.fitting_mode
= val
;
4281 if (intel_encoder
->base
.crtc
)
4282 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4288 intel_dp_connector_destroy(struct drm_connector
*connector
)
4290 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4292 kfree(intel_connector
->detect_edid
);
4294 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4295 kfree(intel_connector
->edid
);
4297 /* Can't call is_edp() since the encoder may have been destroyed
4299 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4300 intel_panel_fini(&intel_connector
->panel
);
4302 drm_connector_cleanup(connector
);
4306 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4308 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4309 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4311 drm_dp_aux_unregister(&intel_dp
->aux
);
4312 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4313 if (is_edp(intel_dp
)) {
4314 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4316 * vdd might still be enabled do to the delayed vdd off.
4317 * Make sure vdd is actually turned off here.
4320 edp_panel_vdd_off_sync(intel_dp
);
4321 pps_unlock(intel_dp
);
4323 if (intel_dp
->edp_notifier
.notifier_call
) {
4324 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4325 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4328 drm_encoder_cleanup(encoder
);
4329 kfree(intel_dig_port
);
4332 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4334 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4336 if (!is_edp(intel_dp
))
4340 * vdd might still be enabled do to the delayed vdd off.
4341 * Make sure vdd is actually turned off here.
4343 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4345 edp_panel_vdd_off_sync(intel_dp
);
4346 pps_unlock(intel_dp
);
4349 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4351 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4352 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4354 enum intel_display_power_domain power_domain
;
4356 lockdep_assert_held(&dev_priv
->pps_mutex
);
4358 if (!edp_have_panel_vdd(intel_dp
))
4362 * The VDD bit needs a power domain reference, so if the bit is
4363 * already enabled when we boot or resume, grab this reference and
4364 * schedule a vdd off, so we don't hold on to the reference
4367 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4368 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4369 intel_display_power_get(dev_priv
, power_domain
);
4371 edp_panel_vdd_schedule_off(intel_dp
);
4374 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4376 struct intel_dp
*intel_dp
;
4378 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4381 intel_dp
= enc_to_intel_dp(encoder
);
4386 * Read out the current power sequencer assignment,
4387 * in case the BIOS did something with it.
4389 if (IS_VALLEYVIEW(encoder
->dev
))
4390 vlv_initial_power_sequencer_setup(intel_dp
);
4392 intel_edp_panel_vdd_sanitize(intel_dp
);
4394 pps_unlock(intel_dp
);
4397 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4398 .dpms
= intel_connector_dpms
,
4399 .detect
= intel_dp_detect
,
4400 .force
= intel_dp_force
,
4401 .fill_modes
= drm_helper_probe_single_connector_modes
,
4402 .set_property
= intel_dp_set_property
,
4403 .destroy
= intel_dp_connector_destroy
,
4406 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4407 .get_modes
= intel_dp_get_modes
,
4408 .mode_valid
= intel_dp_mode_valid
,
4409 .best_encoder
= intel_best_encoder
,
4412 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4413 .reset
= intel_dp_encoder_reset
,
4414 .destroy
= intel_dp_encoder_destroy
,
4418 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4424 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4426 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4427 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4428 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4430 enum intel_display_power_domain power_domain
;
4433 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4434 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4436 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4438 * vdd off can generate a long pulse on eDP which
4439 * would require vdd on to handle it, and thus we
4440 * would end up in an endless cycle of
4441 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4443 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4444 port_name(intel_dig_port
->port
));
4448 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4449 port_name(intel_dig_port
->port
),
4450 long_hpd
? "long" : "short");
4452 power_domain
= intel_display_port_power_domain(intel_encoder
);
4453 intel_display_power_get(dev_priv
, power_domain
);
4457 if (HAS_PCH_SPLIT(dev
)) {
4458 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4461 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4465 if (!intel_dp_get_dpcd(intel_dp
)) {
4469 intel_dp_probe_oui(intel_dp
);
4471 if (!intel_dp_probe_mst(intel_dp
))
4475 if (intel_dp
->is_mst
) {
4476 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4480 if (!intel_dp
->is_mst
) {
4482 * we'll check the link status via the normal hot plug path later -
4483 * but for short hpds we should check it now
4485 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4486 intel_dp_check_link_status(intel_dp
);
4487 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4493 /* if we were in MST mode, and device is not there get out of MST mode */
4494 if (intel_dp
->is_mst
) {
4495 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4496 intel_dp
->is_mst
= false;
4497 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4500 intel_display_power_put(dev_priv
, power_domain
);
4505 /* Return which DP Port should be selected for Transcoder DP control */
4507 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4509 struct drm_device
*dev
= crtc
->dev
;
4510 struct intel_encoder
*intel_encoder
;
4511 struct intel_dp
*intel_dp
;
4513 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4514 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4516 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4517 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4518 return intel_dp
->output_reg
;
4524 /* check the VBT to see whether the eDP is on DP-D port */
4525 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4528 union child_device_config
*p_child
;
4530 static const short port_mapping
[] = {
4531 [PORT_B
] = PORT_IDPB
,
4532 [PORT_C
] = PORT_IDPC
,
4533 [PORT_D
] = PORT_IDPD
,
4539 if (!dev_priv
->vbt
.child_dev_num
)
4542 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4543 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4545 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4546 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4547 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4554 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4556 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4558 intel_attach_force_audio_property(connector
);
4559 intel_attach_broadcast_rgb_property(connector
);
4560 intel_dp
->color_range_auto
= true;
4562 if (is_edp(intel_dp
)) {
4563 drm_mode_create_scaling_mode_property(connector
->dev
);
4564 drm_object_attach_property(
4566 connector
->dev
->mode_config
.scaling_mode_property
,
4567 DRM_MODE_SCALE_ASPECT
);
4568 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4572 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4574 intel_dp
->last_power_cycle
= jiffies
;
4575 intel_dp
->last_power_on
= jiffies
;
4576 intel_dp
->last_backlight_off
= jiffies
;
4580 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4581 struct intel_dp
*intel_dp
)
4583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4584 struct edp_power_seq cur
, vbt
, spec
,
4585 *final
= &intel_dp
->pps_delays
;
4586 u32 pp_on
, pp_off
, pp_div
, pp
;
4587 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4589 lockdep_assert_held(&dev_priv
->pps_mutex
);
4591 /* already initialized? */
4592 if (final
->t11_t12
!= 0)
4595 if (HAS_PCH_SPLIT(dev
)) {
4596 pp_ctrl_reg
= PCH_PP_CONTROL
;
4597 pp_on_reg
= PCH_PP_ON_DELAYS
;
4598 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4599 pp_div_reg
= PCH_PP_DIVISOR
;
4601 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4603 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4604 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4605 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4606 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4609 /* Workaround: Need to write PP_CONTROL with the unlock key as
4610 * the very first thing. */
4611 pp
= ironlake_get_pp_control(intel_dp
);
4612 I915_WRITE(pp_ctrl_reg
, pp
);
4614 pp_on
= I915_READ(pp_on_reg
);
4615 pp_off
= I915_READ(pp_off_reg
);
4616 pp_div
= I915_READ(pp_div_reg
);
4618 /* Pull timing values out of registers */
4619 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4620 PANEL_POWER_UP_DELAY_SHIFT
;
4622 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4623 PANEL_LIGHT_ON_DELAY_SHIFT
;
4625 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4626 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4628 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4629 PANEL_POWER_DOWN_DELAY_SHIFT
;
4631 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4632 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4634 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4635 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4637 vbt
= dev_priv
->vbt
.edp_pps
;
4639 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4640 * our hw here, which are all in 100usec. */
4641 spec
.t1_t3
= 210 * 10;
4642 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4643 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4644 spec
.t10
= 500 * 10;
4645 /* This one is special and actually in units of 100ms, but zero
4646 * based in the hw (so we need to add 100 ms). But the sw vbt
4647 * table multiplies it with 1000 to make it in units of 100usec,
4649 spec
.t11_t12
= (510 + 100) * 10;
4651 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4652 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4654 /* Use the max of the register settings and vbt. If both are
4655 * unset, fall back to the spec limits. */
4656 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4658 max(cur.field, vbt.field))
4659 assign_final(t1_t3
);
4663 assign_final(t11_t12
);
4666 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4667 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4668 intel_dp
->backlight_on_delay
= get_delay(t8
);
4669 intel_dp
->backlight_off_delay
= get_delay(t9
);
4670 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4671 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4674 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4675 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4676 intel_dp
->panel_power_cycle_delay
);
4678 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4679 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4683 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4684 struct intel_dp
*intel_dp
)
4686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4687 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4688 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4689 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4690 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4691 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4693 lockdep_assert_held(&dev_priv
->pps_mutex
);
4695 if (HAS_PCH_SPLIT(dev
)) {
4696 pp_on_reg
= PCH_PP_ON_DELAYS
;
4697 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4698 pp_div_reg
= PCH_PP_DIVISOR
;
4700 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4702 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4703 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4704 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4708 * And finally store the new values in the power sequencer. The
4709 * backlight delays are set to 1 because we do manual waits on them. For
4710 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4711 * we'll end up waiting for the backlight off delay twice: once when we
4712 * do the manual sleep, and once when we disable the panel and wait for
4713 * the PP_STATUS bit to become zero.
4715 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4716 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4717 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4718 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4719 /* Compute the divisor for the pp clock, simply match the Bspec
4721 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4722 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4723 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4725 /* Haswell doesn't have any port selection bits for the panel
4726 * power sequencer any more. */
4727 if (IS_VALLEYVIEW(dev
)) {
4728 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4729 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4731 port_sel
= PANEL_PORT_SELECT_DPA
;
4733 port_sel
= PANEL_PORT_SELECT_DPD
;
4738 I915_WRITE(pp_on_reg
, pp_on
);
4739 I915_WRITE(pp_off_reg
, pp_off
);
4740 I915_WRITE(pp_div_reg
, pp_div
);
4742 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4743 I915_READ(pp_on_reg
),
4744 I915_READ(pp_off_reg
),
4745 I915_READ(pp_div_reg
));
4748 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4751 struct intel_encoder
*encoder
;
4752 struct intel_dp
*intel_dp
= NULL
;
4753 struct intel_crtc_config
*config
= NULL
;
4754 struct intel_crtc
*intel_crtc
= NULL
;
4755 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4757 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4759 if (refresh_rate
<= 0) {
4760 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4764 if (intel_connector
== NULL
) {
4765 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4770 * FIXME: This needs proper synchronization with psr state for some
4771 * platforms that cannot have PSR and DRRS enabled at the same time.
4774 encoder
= intel_attached_encoder(&intel_connector
->base
);
4775 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4776 intel_crtc
= encoder
->new_crtc
;
4779 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4783 config
= &intel_crtc
->config
;
4785 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4786 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4790 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4791 index
= DRRS_LOW_RR
;
4793 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4795 "DRRS requested for previously set RR...ignoring\n");
4799 if (!intel_crtc
->active
) {
4800 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4804 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4805 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4806 val
= I915_READ(reg
);
4807 if (index
> DRRS_HIGH_RR
) {
4808 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4809 intel_dp_set_m_n(intel_crtc
);
4811 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4813 I915_WRITE(reg
, val
);
4817 * mutex taken to ensure that there is no race between differnt
4818 * drrs calls trying to update refresh rate. This scenario may occur
4819 * in future when idleness detection based DRRS in kernel and
4820 * possible calls from user space to set differnt RR are made.
4823 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4825 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4827 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4829 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4832 static struct drm_display_mode
*
4833 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4834 struct intel_connector
*intel_connector
,
4835 struct drm_display_mode
*fixed_mode
)
4837 struct drm_connector
*connector
= &intel_connector
->base
;
4838 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4839 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4841 struct drm_display_mode
*downclock_mode
= NULL
;
4843 if (INTEL_INFO(dev
)->gen
<= 6) {
4844 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4848 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4849 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4853 downclock_mode
= intel_find_panel_downclock
4854 (dev
, fixed_mode
, connector
);
4856 if (!downclock_mode
) {
4857 DRM_DEBUG_KMS("DRRS not supported\n");
4861 dev_priv
->drrs
.connector
= intel_connector
;
4863 mutex_init(&intel_dp
->drrs_state
.mutex
);
4865 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4867 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4868 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4869 return downclock_mode
;
4872 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4873 struct intel_connector
*intel_connector
)
4875 struct drm_connector
*connector
= &intel_connector
->base
;
4876 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4877 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4878 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4880 struct drm_display_mode
*fixed_mode
= NULL
;
4881 struct drm_display_mode
*downclock_mode
= NULL
;
4883 struct drm_display_mode
*scan
;
4885 enum pipe pipe
= INVALID_PIPE
;
4887 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4889 if (!is_edp(intel_dp
))
4893 intel_edp_panel_vdd_sanitize(intel_dp
);
4894 pps_unlock(intel_dp
);
4896 /* Cache DPCD and EDID for edp. */
4897 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4900 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4901 dev_priv
->no_aux_handshake
=
4902 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4903 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4905 /* if this fails, presume the device is a ghost */
4906 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4910 /* We now know it's not a ghost, init power sequence regs. */
4912 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
4913 pps_unlock(intel_dp
);
4915 mutex_lock(&dev
->mode_config
.mutex
);
4916 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
4918 if (drm_add_edid_modes(connector
, edid
)) {
4919 drm_mode_connector_update_edid_property(connector
,
4921 drm_edid_to_eld(connector
, edid
);
4924 edid
= ERR_PTR(-EINVAL
);
4927 edid
= ERR_PTR(-ENOENT
);
4929 intel_connector
->edid
= edid
;
4931 /* prefer fixed mode from EDID if available */
4932 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
4933 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
4934 fixed_mode
= drm_mode_duplicate(dev
, scan
);
4935 downclock_mode
= intel_dp_drrs_init(
4937 intel_connector
, fixed_mode
);
4942 /* fallback to VBT if available for eDP */
4943 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
4944 fixed_mode
= drm_mode_duplicate(dev
,
4945 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
4947 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4949 mutex_unlock(&dev
->mode_config
.mutex
);
4951 if (IS_VALLEYVIEW(dev
)) {
4952 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
4953 register_reboot_notifier(&intel_dp
->edp_notifier
);
4956 * Figure out the current pipe for the initial backlight setup.
4957 * If the current pipe isn't valid, try the PPS pipe, and if that
4958 * fails just assume pipe A.
4960 if (IS_CHERRYVIEW(dev
))
4961 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
4963 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
4965 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
4966 pipe
= intel_dp
->pps_pipe
;
4968 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
4971 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4975 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
4976 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
4977 intel_panel_setup_backlight(connector
, pipe
);
4983 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
4984 struct intel_connector
*intel_connector
)
4986 struct drm_connector
*connector
= &intel_connector
->base
;
4987 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4988 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4989 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 enum port port
= intel_dig_port
->port
;
4994 intel_dp
->pps_pipe
= INVALID_PIPE
;
4996 /* intel_dp vfuncs */
4997 if (INTEL_INFO(dev
)->gen
>= 9)
4998 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
4999 else if (IS_VALLEYVIEW(dev
))
5000 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5001 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5002 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5003 else if (HAS_PCH_SPLIT(dev
))
5004 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5006 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5008 if (INTEL_INFO(dev
)->gen
>= 9)
5009 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5011 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5013 /* Preserve the current hw state. */
5014 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5015 intel_dp
->attached_connector
= intel_connector
;
5017 if (intel_dp_is_edp(dev
, port
))
5018 type
= DRM_MODE_CONNECTOR_eDP
;
5020 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5023 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5024 * for DP the encoder type can be set by the caller to
5025 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5027 if (type
== DRM_MODE_CONNECTOR_eDP
)
5028 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5030 /* eDP only on port B and/or C on vlv/chv */
5031 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5032 port
!= PORT_B
&& port
!= PORT_C
))
5035 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5036 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5039 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5040 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5042 connector
->interlace_allowed
= true;
5043 connector
->doublescan_allowed
= 0;
5045 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5046 edp_panel_vdd_work
);
5048 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5049 drm_connector_register(connector
);
5052 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5054 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5055 intel_connector
->unregister
= intel_dp_connector_unregister
;
5057 /* Set up the hotplug pin. */
5060 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5063 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5066 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5069 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5075 if (is_edp(intel_dp
)) {
5077 intel_dp_init_panel_power_timestamps(intel_dp
);
5078 if (IS_VALLEYVIEW(dev
))
5079 vlv_initial_power_sequencer_setup(intel_dp
);
5081 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5082 pps_unlock(intel_dp
);
5085 intel_dp_aux_init(intel_dp
, intel_connector
);
5087 /* init MST on ports that can support it */
5088 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
5089 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5090 intel_dp_mst_encoder_init(intel_dig_port
,
5091 intel_connector
->base
.base
.id
);
5095 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5096 drm_dp_aux_unregister(&intel_dp
->aux
);
5097 if (is_edp(intel_dp
)) {
5098 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5100 * vdd might still be enabled do to the delayed vdd off.
5101 * Make sure vdd is actually turned off here.
5104 edp_panel_vdd_off_sync(intel_dp
);
5105 pps_unlock(intel_dp
);
5107 drm_connector_unregister(connector
);
5108 drm_connector_cleanup(connector
);
5112 intel_dp_add_properties(intel_dp
, connector
);
5114 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5115 * 0xd. Failure to do so will result in spurious interrupts being
5116 * generated on the port when a cable is not attached.
5118 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5119 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5120 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5127 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5130 struct intel_digital_port
*intel_dig_port
;
5131 struct intel_encoder
*intel_encoder
;
5132 struct drm_encoder
*encoder
;
5133 struct intel_connector
*intel_connector
;
5135 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5136 if (!intel_dig_port
)
5139 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5140 if (!intel_connector
) {
5141 kfree(intel_dig_port
);
5145 intel_encoder
= &intel_dig_port
->base
;
5146 encoder
= &intel_encoder
->base
;
5148 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5149 DRM_MODE_ENCODER_TMDS
);
5151 intel_encoder
->compute_config
= intel_dp_compute_config
;
5152 intel_encoder
->disable
= intel_disable_dp
;
5153 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5154 intel_encoder
->get_config
= intel_dp_get_config
;
5155 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5156 if (IS_CHERRYVIEW(dev
)) {
5157 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5158 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5159 intel_encoder
->enable
= vlv_enable_dp
;
5160 intel_encoder
->post_disable
= chv_post_disable_dp
;
5161 } else if (IS_VALLEYVIEW(dev
)) {
5162 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5163 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5164 intel_encoder
->enable
= vlv_enable_dp
;
5165 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5167 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5168 intel_encoder
->enable
= g4x_enable_dp
;
5169 if (INTEL_INFO(dev
)->gen
>= 5)
5170 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5173 intel_dig_port
->port
= port
;
5174 intel_dig_port
->dp
.output_reg
= output_reg
;
5176 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5177 if (IS_CHERRYVIEW(dev
)) {
5179 intel_encoder
->crtc_mask
= 1 << 2;
5181 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5183 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5185 intel_encoder
->cloneable
= 0;
5186 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5188 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5189 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5191 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5192 drm_encoder_cleanup(encoder
);
5193 kfree(intel_dig_port
);
5194 kfree(intel_connector
);
5198 void intel_dp_mst_suspend(struct drm_device
*dev
)
5200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5204 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5205 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5206 if (!intel_dig_port
)
5209 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5210 if (!intel_dig_port
->dp
.can_mst
)
5212 if (intel_dig_port
->dp
.is_mst
)
5213 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5218 void intel_dp_mst_resume(struct drm_device
*dev
)
5220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5223 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5224 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5225 if (!intel_dig_port
)
5227 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5230 if (!intel_dig_port
->dp
.can_mst
)
5233 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5235 intel_dp_check_mst_status(&intel_dig_port
->dp
);