2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates
[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp
*intel_dp
)
109 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
111 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
114 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
116 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
118 return intel_dig_port
->base
.base
.dev
;
121 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
123 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
126 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
127 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
128 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
129 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
130 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
132 static void intel_dp_unset_edid(struct intel_dp
*intel_dp
);
135 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
137 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
139 switch (max_link_bw
) {
140 case DP_LINK_BW_1_62
:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw
= DP_LINK_BW_1_62
;
153 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
155 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
156 u8 source_max
, sink_max
;
158 source_max
= intel_dig_port
->max_lanes
;
159 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
161 return min(source_max
, sink_max
);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock
, int bpp
)
184 return (pixel_clock
* bpp
+ 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
190 return (max_link_clock
* max_lanes
* 8) / 10;
193 static enum drm_mode_status
194 intel_dp_mode_valid(struct drm_connector
*connector
,
195 struct drm_display_mode
*mode
)
197 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
198 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
199 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
200 int target_clock
= mode
->clock
;
201 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
204 if (is_edp(intel_dp
) && fixed_mode
) {
205 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
208 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
211 target_clock
= fixed_mode
->clock
;
214 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
215 max_lanes
= intel_dp_max_lane_count(intel_dp
);
217 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
218 mode_rate
= intel_dp_link_required(target_clock
, 18);
220 if (mode_rate
> max_rate
|| target_clock
> max_dotclk
)
221 return MODE_CLOCK_HIGH
;
223 if (mode
->clock
< 10000)
224 return MODE_CLOCK_LOW
;
226 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
227 return MODE_H_ILLEGAL
;
232 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
239 for (i
= 0; i
< src_bytes
; i
++)
240 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
244 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
249 for (i
= 0; i
< dst_bytes
; i
++)
250 dst
[i
] = src
>> ((3-i
) * 8);
254 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
255 struct intel_dp
*intel_dp
);
257 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
258 struct intel_dp
*intel_dp
);
260 static void pps_lock(struct intel_dp
*intel_dp
)
262 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
263 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
264 struct drm_device
*dev
= encoder
->base
.dev
;
265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 enum intel_display_power_domain power_domain
;
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
272 power_domain
= intel_display_port_aux_power_domain(encoder
);
273 intel_display_power_get(dev_priv
, power_domain
);
275 mutex_lock(&dev_priv
->pps_mutex
);
278 static void pps_unlock(struct intel_dp
*intel_dp
)
280 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
281 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
282 struct drm_device
*dev
= encoder
->base
.dev
;
283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 enum intel_display_power_domain power_domain
;
286 mutex_unlock(&dev_priv
->pps_mutex
);
288 power_domain
= intel_display_port_aux_power_domain(encoder
);
289 intel_display_power_put(dev_priv
, power_domain
);
293 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum pipe pipe
= intel_dp
->pps_pipe
;
299 bool pll_enabled
, release_cl_override
= false;
300 enum dpio_phy phy
= DPIO_PHY(pipe
);
301 enum dpio_channel ch
= vlv_pipe_to_channel(pipe
);
304 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe
), port_name(intel_dig_port
->port
));
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
315 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
316 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
317 DP
|= DP_PORT_WIDTH(1);
318 DP
|= DP_LINK_TRAIN_PAT_1
;
320 if (IS_CHERRYVIEW(dev
))
321 DP
|= DP_PIPE_SELECT_CHV(pipe
);
322 else if (pipe
== PIPE_B
)
323 DP
|= DP_PIPEB_SELECT
;
325 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
332 release_cl_override
= IS_CHERRYVIEW(dev
) &&
333 !chv_phy_powergate_ch(dev_priv
, phy
, ch
, true);
335 if (vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
336 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
349 I915_WRITE(intel_dp
->output_reg
, DP
);
350 POSTING_READ(intel_dp
->output_reg
);
352 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
353 POSTING_READ(intel_dp
->output_reg
);
355 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
356 POSTING_READ(intel_dp
->output_reg
);
359 vlv_force_pll_off(dev
, pipe
);
361 if (release_cl_override
)
362 chv_phy_powergate_ch(dev_priv
, phy
, ch
, false);
367 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
369 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
370 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
372 struct intel_encoder
*encoder
;
373 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
376 lockdep_assert_held(&dev_priv
->pps_mutex
);
378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp
));
381 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
382 return intel_dp
->pps_pipe
;
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
388 for_each_intel_encoder(dev
, encoder
) {
389 struct intel_dp
*tmp
;
391 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
394 tmp
= enc_to_intel_dp(&encoder
->base
);
396 if (tmp
->pps_pipe
!= INVALID_PIPE
)
397 pipes
&= ~(1 << tmp
->pps_pipe
);
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
404 if (WARN_ON(pipes
== 0))
407 pipe
= ffs(pipes
) - 1;
409 vlv_steal_power_sequencer(dev
, pipe
);
410 intel_dp
->pps_pipe
= pipe
;
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp
->pps_pipe
),
414 port_name(intel_dig_port
->port
));
416 /* init power sequencer on this pipe and port */
417 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
418 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
424 vlv_power_sequencer_kick(intel_dp
);
426 return intel_dp
->pps_pipe
;
430 bxt_power_sequencer_idx(struct intel_dp
*intel_dp
)
432 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
433 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
436 lockdep_assert_held(&dev_priv
->pps_mutex
);
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp
));
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
446 if (!intel_dp
->pps_reset
)
449 intel_dp
->pps_reset
= false;
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
455 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
460 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
463 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
469 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
475 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
482 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
484 vlv_pipe_check pipe_check
)
488 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
489 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
490 PANEL_PORT_SELECT_MASK
;
492 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
495 if (!pipe_check(dev_priv
, pipe
))
505 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
507 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
508 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
510 enum port port
= intel_dig_port
->port
;
512 lockdep_assert_held(&dev_priv
->pps_mutex
);
514 /* try to find a pipe with this port selected */
515 /* first pick one where the panel is on */
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
521 vlv_pipe_has_vdd_on
);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
524 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
537 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
538 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
541 void intel_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
543 struct drm_device
*dev
= dev_priv
->dev
;
544 struct intel_encoder
*encoder
;
546 if (WARN_ON(!IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
560 for_each_intel_encoder(dev
, encoder
) {
561 struct intel_dp
*intel_dp
;
563 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
566 intel_dp
= enc_to_intel_dp(&encoder
->base
);
568 intel_dp
->pps_reset
= true;
570 intel_dp
->pps_pipe
= INVALID_PIPE
;
574 struct pps_registers
{
582 static void intel_pps_get_registers(struct drm_i915_private
*dev_priv
,
583 struct intel_dp
*intel_dp
,
584 struct pps_registers
*regs
)
586 memset(regs
, 0, sizeof(*regs
));
588 if (IS_BROXTON(dev_priv
)) {
589 int idx
= bxt_power_sequencer_idx(intel_dp
);
591 regs
->pp_ctrl
= BXT_PP_CONTROL(idx
);
592 regs
->pp_stat
= BXT_PP_STATUS(idx
);
593 regs
->pp_on
= BXT_PP_ON_DELAYS(idx
);
594 regs
->pp_off
= BXT_PP_OFF_DELAYS(idx
);
595 } else if (HAS_PCH_SPLIT(dev_priv
)) {
596 regs
->pp_ctrl
= PCH_PP_CONTROL
;
597 regs
->pp_stat
= PCH_PP_STATUS
;
598 regs
->pp_on
= PCH_PP_ON_DELAYS
;
599 regs
->pp_off
= PCH_PP_OFF_DELAYS
;
600 regs
->pp_div
= PCH_PP_DIVISOR
;
602 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
604 regs
->pp_ctrl
= VLV_PIPE_PP_CONTROL(pipe
);
605 regs
->pp_stat
= VLV_PIPE_PP_STATUS(pipe
);
606 regs
->pp_on
= VLV_PIPE_PP_ON_DELAYS(pipe
);
607 regs
->pp_off
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
608 regs
->pp_div
= VLV_PIPE_PP_DIVISOR(pipe
);
613 _pp_ctrl_reg(struct intel_dp
*intel_dp
)
615 struct pps_registers regs
;
617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
624 _pp_stat_reg(struct intel_dp
*intel_dp
)
626 struct pps_registers regs
;
628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp
)), intel_dp
,
634 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
639 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
641 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
649 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
650 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
651 i915_reg_t pp_ctrl_reg
, pp_div_reg
;
654 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
655 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
656 pp_div
= I915_READ(pp_div_reg
);
657 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
661 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
662 msleep(intel_dp
->panel_power_cycle_delay
);
665 pps_unlock(intel_dp
);
670 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
672 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
675 lockdep_assert_held(&dev_priv
->pps_mutex
);
677 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
678 intel_dp
->pps_pipe
== INVALID_PIPE
)
681 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
684 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
686 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
689 lockdep_assert_held(&dev_priv
->pps_mutex
);
691 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
692 intel_dp
->pps_pipe
== INVALID_PIPE
)
695 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
699 intel_dp_check_edp(struct intel_dp
*intel_dp
)
701 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
704 if (!is_edp(intel_dp
))
707 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
710 I915_READ(_pp_stat_reg(intel_dp
)),
711 I915_READ(_pp_ctrl_reg(intel_dp
)));
716 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
718 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
719 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
721 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
725 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
727 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
728 msecs_to_jiffies_timeout(10));
730 done
= wait_for_atomic(C
, 10) == 0;
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
739 static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
741 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
742 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
748 * The clock divider is based off the hrawclk, and would like to run at
749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
751 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
754 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
756 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
757 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
767 if (intel_dig_port
->port
== PORT_A
)
768 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
770 return DIV_ROUND_CLOSEST(dev_priv
->rawclk_freq
, 2000);
773 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
775 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
776 struct drm_i915_private
*dev_priv
= to_i915(intel_dig_port
->base
.base
.dev
);
778 if (intel_dig_port
->port
!= PORT_A
&& HAS_PCH_LPT_H(dev_priv
)) {
779 /* Workaround for non-ULT HSW */
787 return ilk_get_aux_clock_divider(intel_dp
, index
);
790 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
797 return index
? 0 : 1;
800 static uint32_t g4x_get_aux_send_ctl(struct intel_dp
*intel_dp
,
803 uint32_t aux_clock_divider
)
805 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
806 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
807 uint32_t precharge
, timeout
;
814 if (IS_BROADWELL(dev
) && intel_dig_port
->port
== PORT_A
)
815 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
817 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
819 return DP_AUX_CH_CTL_SEND_BUSY
|
821 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
822 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
824 DP_AUX_CH_CTL_RECEIVE_ERROR
|
825 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
826 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
827 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
830 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
835 return DP_AUX_CH_CTL_SEND_BUSY
|
837 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
839 DP_AUX_CH_CTL_TIME_OUT_1600us
|
840 DP_AUX_CH_CTL_RECEIVE_ERROR
|
841 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
847 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
848 const uint8_t *send
, int send_bytes
,
849 uint8_t *recv
, int recv_size
)
851 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
852 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
854 i915_reg_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
855 uint32_t aux_clock_divider
;
856 int i
, ret
, recv_bytes
;
859 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
870 vdd
= edp_panel_vdd_on(intel_dp
);
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
876 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
878 intel_dp_check_edp(intel_dp
);
880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
882 status
= I915_READ_NOTRACE(ch_ctl
);
883 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
889 static u32 last_status
= -1;
890 const u32 status
= I915_READ(ch_ctl
);
892 if (status
!= last_status
) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
895 last_status
= status
;
902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
908 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
909 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i
= 0; i
< send_bytes
; i
+= 4)
918 I915_WRITE(intel_dp
->aux_ch_data_reg
[i
>> 2],
919 intel_dp_pack_aux(send
+ i
,
922 /* Send the command and wait for it to complete */
923 I915_WRITE(ch_ctl
, send_ctl
);
925 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
927 /* Clear done status and any errors */
931 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
932 DP_AUX_CH_CTL_RECEIVE_ERROR
);
934 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
942 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
943 usleep_range(400, 500);
946 if (status
& DP_AUX_CH_CTL_DONE
)
951 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
961 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
969 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
975 /* Unload any bytes sent back from the other side */
976 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
984 if (recv_bytes
== 0 || recv_bytes
> 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
994 usleep_range(1000, 1500);
999 if (recv_bytes
> recv_size
)
1000 recv_bytes
= recv_size
;
1002 for (i
= 0; i
< recv_bytes
; i
+= 4)
1003 intel_dp_unpack_aux(I915_READ(intel_dp
->aux_ch_data_reg
[i
>> 2]),
1004 recv
+ i
, recv_bytes
- i
);
1008 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
1011 edp_panel_vdd_off(intel_dp
, false);
1013 pps_unlock(intel_dp
);
1018 #define BARE_ADDRESS_SIZE 3
1019 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1021 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
1023 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
1024 uint8_t txbuf
[20], rxbuf
[20];
1025 size_t txsize
, rxsize
;
1028 txbuf
[0] = (msg
->request
<< 4) |
1029 ((msg
->address
>> 16) & 0xf);
1030 txbuf
[1] = (msg
->address
>> 8) & 0xff;
1031 txbuf
[2] = msg
->address
& 0xff;
1032 txbuf
[3] = msg
->size
- 1;
1034 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
1035 case DP_AUX_NATIVE_WRITE
:
1036 case DP_AUX_I2C_WRITE
:
1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
1038 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
1039 rxsize
= 2; /* 0 or 1 data bytes */
1041 if (WARN_ON(txsize
> 20))
1045 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
1049 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1051 msg
->reply
= rxbuf
[0] >> 4;
1054 /* Number of bytes written in a short write. */
1055 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
1057 /* Return payload size. */
1063 case DP_AUX_NATIVE_READ
:
1064 case DP_AUX_I2C_READ
:
1065 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1066 rxsize
= msg
->size
+ 1;
1068 if (WARN_ON(rxsize
> 20))
1071 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1073 msg
->reply
= rxbuf
[0] >> 4;
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1078 * Return payload size.
1081 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1093 static i915_reg_t
g4x_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1100 return DP_AUX_CH_CTL(port
);
1103 return DP_AUX_CH_CTL(PORT_B
);
1107 static i915_reg_t
g4x_aux_data_reg(struct drm_i915_private
*dev_priv
,
1108 enum port port
, int index
)
1114 return DP_AUX_CH_DATA(port
, index
);
1117 return DP_AUX_CH_DATA(PORT_B
, index
);
1121 static i915_reg_t
ilk_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1126 return DP_AUX_CH_CTL(port
);
1130 return PCH_DP_AUX_CH_CTL(port
);
1133 return DP_AUX_CH_CTL(PORT_A
);
1137 static i915_reg_t
ilk_aux_data_reg(struct drm_i915_private
*dev_priv
,
1138 enum port port
, int index
)
1142 return DP_AUX_CH_DATA(port
, index
);
1146 return PCH_DP_AUX_CH_DATA(port
, index
);
1149 return DP_AUX_CH_DATA(PORT_A
, index
);
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1157 static enum port
skl_porte_aux_port(struct drm_i915_private
*dev_priv
)
1159 const struct ddi_vbt_port_info
*info
=
1160 &dev_priv
->vbt
.ddi_port_info
[PORT_E
];
1162 switch (info
->alternate_aux_channel
) {
1172 MISSING_CASE(info
->alternate_aux_channel
);
1177 static i915_reg_t
skl_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1181 port
= skl_porte_aux_port(dev_priv
);
1188 return DP_AUX_CH_CTL(port
);
1191 return DP_AUX_CH_CTL(PORT_A
);
1195 static i915_reg_t
skl_aux_data_reg(struct drm_i915_private
*dev_priv
,
1196 enum port port
, int index
)
1199 port
= skl_porte_aux_port(dev_priv
);
1206 return DP_AUX_CH_DATA(port
, index
);
1209 return DP_AUX_CH_DATA(PORT_A
, index
);
1213 static i915_reg_t
intel_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
1216 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1217 return skl_aux_ctl_reg(dev_priv
, port
);
1218 else if (HAS_PCH_SPLIT(dev_priv
))
1219 return ilk_aux_ctl_reg(dev_priv
, port
);
1221 return g4x_aux_ctl_reg(dev_priv
, port
);
1224 static i915_reg_t
intel_aux_data_reg(struct drm_i915_private
*dev_priv
,
1225 enum port port
, int index
)
1227 if (INTEL_INFO(dev_priv
)->gen
>= 9)
1228 return skl_aux_data_reg(dev_priv
, port
, index
);
1229 else if (HAS_PCH_SPLIT(dev_priv
))
1230 return ilk_aux_data_reg(dev_priv
, port
, index
);
1232 return g4x_aux_data_reg(dev_priv
, port
, index
);
1235 static void intel_aux_reg_init(struct intel_dp
*intel_dp
)
1237 struct drm_i915_private
*dev_priv
= to_i915(intel_dp_to_dev(intel_dp
));
1238 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1241 intel_dp
->aux_ch_ctl_reg
= intel_aux_ctl_reg(dev_priv
, port
);
1242 for (i
= 0; i
< ARRAY_SIZE(intel_dp
->aux_ch_data_reg
); i
++)
1243 intel_dp
->aux_ch_data_reg
[i
] = intel_aux_data_reg(dev_priv
, port
, i
);
1247 intel_dp_aux_fini(struct intel_dp
*intel_dp
)
1249 drm_dp_aux_unregister(&intel_dp
->aux
);
1250 kfree(intel_dp
->aux
.name
);
1254 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1256 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1257 enum port port
= intel_dig_port
->port
;
1260 intel_aux_reg_init(intel_dp
);
1262 intel_dp
->aux
.name
= kasprintf(GFP_KERNEL
, "DPDDC-%c", port_name(port
));
1263 if (!intel_dp
->aux
.name
)
1266 intel_dp
->aux
.dev
= connector
->base
.kdev
;
1267 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1269 DRM_DEBUG_KMS("registering %s bus for %s\n",
1271 connector
->base
.kdev
->kobj
.name
);
1273 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1275 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1276 intel_dp
->aux
.name
, ret
);
1277 kfree(intel_dp
->aux
.name
);
1285 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1287 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1289 intel_dp_aux_fini(intel_dp
);
1290 intel_connector_unregister(intel_connector
);
1294 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1296 if (intel_dp
->num_sink_rates
) {
1297 *sink_rates
= intel_dp
->sink_rates
;
1298 return intel_dp
->num_sink_rates
;
1301 *sink_rates
= default_rates
;
1303 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1306 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
)
1308 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1309 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1311 /* WaDisableHBR2:skl */
1312 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
))
1315 if ((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) || IS_BROADWELL(dev
) ||
1316 (INTEL_INFO(dev
)->gen
>= 9))
1323 intel_dp_source_rates(struct intel_dp
*intel_dp
, const int **source_rates
)
1325 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1326 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1329 if (IS_BROXTON(dev
)) {
1330 *source_rates
= bxt_rates
;
1331 size
= ARRAY_SIZE(bxt_rates
);
1332 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1333 *source_rates
= skl_rates
;
1334 size
= ARRAY_SIZE(skl_rates
);
1336 *source_rates
= default_rates
;
1337 size
= ARRAY_SIZE(default_rates
);
1340 /* This depends on the fact that 5.4 is last value in the array */
1341 if (!intel_dp_source_supports_hbr2(intel_dp
))
1348 intel_dp_set_clock(struct intel_encoder
*encoder
,
1349 struct intel_crtc_state
*pipe_config
)
1351 struct drm_device
*dev
= encoder
->base
.dev
;
1352 const struct dp_link_dpll
*divisor
= NULL
;
1356 divisor
= gen4_dpll
;
1357 count
= ARRAY_SIZE(gen4_dpll
);
1358 } else if (HAS_PCH_SPLIT(dev
)) {
1360 count
= ARRAY_SIZE(pch_dpll
);
1361 } else if (IS_CHERRYVIEW(dev
)) {
1363 count
= ARRAY_SIZE(chv_dpll
);
1364 } else if (IS_VALLEYVIEW(dev
)) {
1366 count
= ARRAY_SIZE(vlv_dpll
);
1369 if (divisor
&& count
) {
1370 for (i
= 0; i
< count
; i
++) {
1371 if (pipe_config
->port_clock
== divisor
[i
].clock
) {
1372 pipe_config
->dpll
= divisor
[i
].dpll
;
1373 pipe_config
->clock_set
= true;
1380 static int intersect_rates(const int *source_rates
, int source_len
,
1381 const int *sink_rates
, int sink_len
,
1384 int i
= 0, j
= 0, k
= 0;
1386 while (i
< source_len
&& j
< sink_len
) {
1387 if (source_rates
[i
] == sink_rates
[j
]) {
1388 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1390 common_rates
[k
] = source_rates
[i
];
1394 } else if (source_rates
[i
] < sink_rates
[j
]) {
1403 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1406 const int *source_rates
, *sink_rates
;
1407 int source_len
, sink_len
;
1409 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1410 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1412 return intersect_rates(source_rates
, source_len
,
1413 sink_rates
, sink_len
,
1417 static void snprintf_int_array(char *str
, size_t len
,
1418 const int *array
, int nelem
)
1424 for (i
= 0; i
< nelem
; i
++) {
1425 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1433 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1435 const int *source_rates
, *sink_rates
;
1436 int source_len
, sink_len
, common_len
;
1437 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1438 char str
[128]; /* FIXME: too big for stack? */
1440 if ((drm_debug
& DRM_UT_KMS
) == 0)
1443 source_len
= intel_dp_source_rates(intel_dp
, &source_rates
);
1444 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1445 DRM_DEBUG_KMS("source rates: %s\n", str
);
1447 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1448 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1449 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1451 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1452 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1453 DRM_DEBUG_KMS("common rates: %s\n", str
);
1456 static int rate_to_index(int find
, const int *rates
)
1460 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1461 if (find
== rates
[i
])
1468 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1470 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1473 len
= intel_dp_common_rates(intel_dp
, rates
);
1474 if (WARN_ON(len
<= 0))
1477 return rates
[rate_to_index(0, rates
) - 1];
1480 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1482 return rate_to_index(rate
, intel_dp
->sink_rates
);
1485 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1486 uint8_t *link_bw
, uint8_t *rate_select
)
1488 if (intel_dp
->num_sink_rates
) {
1491 intel_dp_rate_select(intel_dp
, port_clock
);
1493 *link_bw
= drm_dp_link_rate_to_bw_code(port_clock
);
1499 intel_dp_compute_config(struct intel_encoder
*encoder
,
1500 struct intel_crtc_state
*pipe_config
)
1502 struct drm_device
*dev
= encoder
->base
.dev
;
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1504 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1505 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1506 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1507 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1508 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1509 int lane_count
, clock
;
1510 int min_lane_count
= 1;
1511 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1512 /* Conveniently, the link BW constants become indices with a shift...*/
1516 int link_avail
, link_clock
;
1517 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1519 uint8_t link_bw
, rate_select
;
1521 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1523 /* No common link rates between source and sink */
1524 WARN_ON(common_len
<= 0);
1526 max_clock
= common_len
- 1;
1528 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1529 pipe_config
->has_pch_encoder
= true;
1531 pipe_config
->has_dp_encoder
= true;
1532 pipe_config
->has_drrs
= false;
1533 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1535 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1536 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1539 if (INTEL_INFO(dev
)->gen
>= 9) {
1541 ret
= skl_update_scaler_crtc(pipe_config
);
1546 if (HAS_GMCH_DISPLAY(dev
))
1547 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1548 intel_connector
->panel
.fitting_mode
);
1550 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1551 intel_connector
->panel
.fitting_mode
);
1554 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1557 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1558 "max bw %d pixel clock %iKHz\n",
1559 max_lane_count
, common_rates
[max_clock
],
1560 adjusted_mode
->crtc_clock
);
1562 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1563 * bpc in between. */
1564 bpp
= pipe_config
->pipe_bpp
;
1565 if (is_edp(intel_dp
)) {
1567 /* Get bpp from vbt only for panels that dont have bpp in edid */
1568 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1569 (dev_priv
->vbt
.edp
.bpp
&& dev_priv
->vbt
.edp
.bpp
< bpp
)) {
1570 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1571 dev_priv
->vbt
.edp
.bpp
);
1572 bpp
= dev_priv
->vbt
.edp
.bpp
;
1576 * Use the maximum clock and number of lanes the eDP panel
1577 * advertizes being capable of. The panels are generally
1578 * designed to support only a single clock and lane
1579 * configuration, and typically these values correspond to the
1580 * native resolution of the panel.
1582 min_lane_count
= max_lane_count
;
1583 min_clock
= max_clock
;
1586 for (; bpp
>= 6*3; bpp
-= 2*3) {
1587 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1590 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1591 for (lane_count
= min_lane_count
;
1592 lane_count
<= max_lane_count
;
1595 link_clock
= common_rates
[clock
];
1596 link_avail
= intel_dp_max_data_rate(link_clock
,
1599 if (mode_rate
<= link_avail
) {
1609 if (intel_dp
->color_range_auto
) {
1612 * CEA-861-E - 5.1 Default Encoding Parameters
1613 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1615 pipe_config
->limited_color_range
=
1616 bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1;
1618 pipe_config
->limited_color_range
=
1619 intel_dp
->limited_color_range
;
1622 pipe_config
->lane_count
= lane_count
;
1624 pipe_config
->pipe_bpp
= bpp
;
1625 pipe_config
->port_clock
= common_rates
[clock
];
1627 intel_dp_compute_rate(intel_dp
, pipe_config
->port_clock
,
1628 &link_bw
, &rate_select
);
1630 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1631 link_bw
, rate_select
, pipe_config
->lane_count
,
1632 pipe_config
->port_clock
, bpp
);
1633 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1634 mode_rate
, link_avail
);
1636 intel_link_compute_m_n(bpp
, lane_count
,
1637 adjusted_mode
->crtc_clock
,
1638 pipe_config
->port_clock
,
1639 &pipe_config
->dp_m_n
);
1641 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1642 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1643 pipe_config
->has_drrs
= true;
1644 intel_link_compute_m_n(bpp
, lane_count
,
1645 intel_connector
->panel
.downclock_mode
->clock
,
1646 pipe_config
->port_clock
,
1647 &pipe_config
->dp_m2_n2
);
1651 * DPLL0 VCO may need to be adjusted to get the correct
1652 * clock for eDP. This will affect cdclk as well.
1654 if (is_edp(intel_dp
) &&
1655 (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))) {
1658 switch (pipe_config
->port_clock
/ 2) {
1668 to_intel_atomic_state(pipe_config
->base
.state
)->cdclk_pll_vco
= vco
;
1672 intel_dp_set_clock(encoder
, pipe_config
);
1677 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1678 const struct intel_crtc_state
*pipe_config
)
1680 intel_dp
->link_rate
= pipe_config
->port_clock
;
1681 intel_dp
->lane_count
= pipe_config
->lane_count
;
1684 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1686 struct drm_device
*dev
= encoder
->base
.dev
;
1687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1688 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1689 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1690 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1691 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1693 intel_dp_set_link_params(intel_dp
, crtc
->config
);
1696 * There are four kinds of DP registers:
1703 * IBX PCH and CPU are the same for almost everything,
1704 * except that the CPU DP PLL is configured in this
1707 * CPT PCH is quite different, having many bits moved
1708 * to the TRANS_DP_CTL register instead. That
1709 * configuration happens (oddly) in ironlake_pch_enable
1712 /* Preserve the BIOS-computed detected bit. This is
1713 * supposed to be read-only.
1715 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1717 /* Handle DP bits in common between all three register formats */
1718 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1719 intel_dp
->DP
|= DP_PORT_WIDTH(crtc
->config
->lane_count
);
1721 /* Split out the IBX/CPU vs CPT settings */
1723 if (IS_GEN7(dev
) && port
== PORT_A
) {
1724 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1725 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1726 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1727 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1728 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1730 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1731 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1733 intel_dp
->DP
|= crtc
->pipe
<< 29;
1734 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1737 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1739 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1740 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1741 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1743 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1744 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1746 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
1747 !IS_CHERRYVIEW(dev
) && crtc
->config
->limited_color_range
)
1748 intel_dp
->DP
|= DP_COLOR_RANGE_16_235
;
1750 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1751 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1752 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1753 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1754 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1756 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1757 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1759 if (IS_CHERRYVIEW(dev
))
1760 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1761 else if (crtc
->pipe
== PIPE_B
)
1762 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1766 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1767 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1769 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1770 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1772 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1773 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1775 static void intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
1776 struct intel_dp
*intel_dp
);
1778 static void wait_panel_status(struct intel_dp
*intel_dp
,
1782 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1784 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1786 lockdep_assert_held(&dev_priv
->pps_mutex
);
1788 intel_pps_verify_state(dev_priv
, intel_dp
);
1790 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1791 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1793 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1795 I915_READ(pp_stat_reg
),
1796 I915_READ(pp_ctrl_reg
));
1798 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
,
1799 5 * USEC_PER_SEC
, 10 * USEC_PER_MSEC
))
1800 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1801 I915_READ(pp_stat_reg
),
1802 I915_READ(pp_ctrl_reg
));
1804 DRM_DEBUG_KMS("Wait complete\n");
1807 static void wait_panel_on(struct intel_dp
*intel_dp
)
1809 DRM_DEBUG_KMS("Wait for panel power on\n");
1810 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1813 static void wait_panel_off(struct intel_dp
*intel_dp
)
1815 DRM_DEBUG_KMS("Wait for panel power off time\n");
1816 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1819 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1821 ktime_t panel_power_on_time
;
1822 s64 panel_power_off_duration
;
1824 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1826 /* take the difference of currrent time and panel power off time
1827 * and then make panel wait for t11_t12 if needed. */
1828 panel_power_on_time
= ktime_get_boottime();
1829 panel_power_off_duration
= ktime_ms_delta(panel_power_on_time
, intel_dp
->panel_power_off_time
);
1831 /* When we disable the VDD override bit last we have to do the manual
1833 if (panel_power_off_duration
< (s64
)intel_dp
->panel_power_cycle_delay
)
1834 wait_remaining_ms_from_jiffies(jiffies
,
1835 intel_dp
->panel_power_cycle_delay
- panel_power_off_duration
);
1837 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1840 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1842 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1843 intel_dp
->backlight_on_delay
);
1846 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1848 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1849 intel_dp
->backlight_off_delay
);
1852 /* Read the current pp_control value, unlocking the register if it
1856 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1858 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1862 lockdep_assert_held(&dev_priv
->pps_mutex
);
1864 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1865 if (!IS_BROXTON(dev
)) {
1866 control
&= ~PANEL_UNLOCK_MASK
;
1867 control
|= PANEL_UNLOCK_REGS
;
1873 * Must be paired with edp_panel_vdd_off().
1874 * Must hold pps_mutex around the whole on/off sequence.
1875 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1877 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1879 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1880 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1881 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1883 enum intel_display_power_domain power_domain
;
1885 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1886 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1888 lockdep_assert_held(&dev_priv
->pps_mutex
);
1890 if (!is_edp(intel_dp
))
1893 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1894 intel_dp
->want_panel_vdd
= true;
1896 if (edp_have_panel_vdd(intel_dp
))
1897 return need_to_disable
;
1899 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1900 intel_display_power_get(dev_priv
, power_domain
);
1902 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1903 port_name(intel_dig_port
->port
));
1905 if (!edp_have_panel_power(intel_dp
))
1906 wait_panel_power_cycle(intel_dp
);
1908 pp
= ironlake_get_pp_control(intel_dp
);
1909 pp
|= EDP_FORCE_VDD
;
1911 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1912 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1914 I915_WRITE(pp_ctrl_reg
, pp
);
1915 POSTING_READ(pp_ctrl_reg
);
1916 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1917 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1919 * If the panel wasn't on, delay before accessing aux channel
1921 if (!edp_have_panel_power(intel_dp
)) {
1922 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1923 port_name(intel_dig_port
->port
));
1924 msleep(intel_dp
->panel_power_up_delay
);
1927 return need_to_disable
;
1931 * Must be paired with intel_edp_panel_vdd_off() or
1932 * intel_edp_panel_off().
1933 * Nested calls to these functions are not allowed since
1934 * we drop the lock. Caller must use some higher level
1935 * locking to prevent nested calls from other threads.
1937 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1941 if (!is_edp(intel_dp
))
1945 vdd
= edp_panel_vdd_on(intel_dp
);
1946 pps_unlock(intel_dp
);
1948 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1949 port_name(dp_to_dig_port(intel_dp
)->port
));
1952 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1954 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1956 struct intel_digital_port
*intel_dig_port
=
1957 dp_to_dig_port(intel_dp
);
1958 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1959 enum intel_display_power_domain power_domain
;
1961 i915_reg_t pp_stat_reg
, pp_ctrl_reg
;
1963 lockdep_assert_held(&dev_priv
->pps_mutex
);
1965 WARN_ON(intel_dp
->want_panel_vdd
);
1967 if (!edp_have_panel_vdd(intel_dp
))
1970 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1971 port_name(intel_dig_port
->port
));
1973 pp
= ironlake_get_pp_control(intel_dp
);
1974 pp
&= ~EDP_FORCE_VDD
;
1976 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1977 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1979 I915_WRITE(pp_ctrl_reg
, pp
);
1980 POSTING_READ(pp_ctrl_reg
);
1982 /* Make sure sequencer is idle before allowing subsequent activity */
1983 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1984 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1986 if ((pp
& POWER_TARGET_ON
) == 0)
1987 intel_dp
->panel_power_off_time
= ktime_get_boottime();
1989 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
1990 intel_display_power_put(dev_priv
, power_domain
);
1993 static void edp_panel_vdd_work(struct work_struct
*__work
)
1995 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1996 struct intel_dp
, panel_vdd_work
);
1999 if (!intel_dp
->want_panel_vdd
)
2000 edp_panel_vdd_off_sync(intel_dp
);
2001 pps_unlock(intel_dp
);
2004 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
2006 unsigned long delay
;
2009 * Queue the timer to fire a long time from now (relative to the power
2010 * down delay) to keep the panel power up across a sequence of
2013 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
2014 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
2018 * Must be paired with edp_panel_vdd_on().
2019 * Must hold pps_mutex around the whole on/off sequence.
2020 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2022 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
2024 struct drm_i915_private
*dev_priv
=
2025 intel_dp_to_dev(intel_dp
)->dev_private
;
2027 lockdep_assert_held(&dev_priv
->pps_mutex
);
2029 if (!is_edp(intel_dp
))
2032 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
2033 port_name(dp_to_dig_port(intel_dp
)->port
));
2035 intel_dp
->want_panel_vdd
= false;
2038 edp_panel_vdd_off_sync(intel_dp
);
2040 edp_panel_vdd_schedule_off(intel_dp
);
2043 static void edp_panel_on(struct intel_dp
*intel_dp
)
2045 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2046 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2048 i915_reg_t pp_ctrl_reg
;
2050 lockdep_assert_held(&dev_priv
->pps_mutex
);
2052 if (!is_edp(intel_dp
))
2055 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2056 port_name(dp_to_dig_port(intel_dp
)->port
));
2058 if (WARN(edp_have_panel_power(intel_dp
),
2059 "eDP port %c panel power already on\n",
2060 port_name(dp_to_dig_port(intel_dp
)->port
)))
2063 wait_panel_power_cycle(intel_dp
);
2065 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2066 pp
= ironlake_get_pp_control(intel_dp
);
2068 /* ILK workaround: disable reset around power sequence */
2069 pp
&= ~PANEL_POWER_RESET
;
2070 I915_WRITE(pp_ctrl_reg
, pp
);
2071 POSTING_READ(pp_ctrl_reg
);
2074 pp
|= POWER_TARGET_ON
;
2076 pp
|= PANEL_POWER_RESET
;
2078 I915_WRITE(pp_ctrl_reg
, pp
);
2079 POSTING_READ(pp_ctrl_reg
);
2081 wait_panel_on(intel_dp
);
2082 intel_dp
->last_power_on
= jiffies
;
2085 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
2086 I915_WRITE(pp_ctrl_reg
, pp
);
2087 POSTING_READ(pp_ctrl_reg
);
2091 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
2093 if (!is_edp(intel_dp
))
2097 edp_panel_on(intel_dp
);
2098 pps_unlock(intel_dp
);
2102 static void edp_panel_off(struct intel_dp
*intel_dp
)
2104 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2105 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
2106 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2108 enum intel_display_power_domain power_domain
;
2110 i915_reg_t pp_ctrl_reg
;
2112 lockdep_assert_held(&dev_priv
->pps_mutex
);
2114 if (!is_edp(intel_dp
))
2117 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2118 port_name(dp_to_dig_port(intel_dp
)->port
));
2120 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2121 port_name(dp_to_dig_port(intel_dp
)->port
));
2123 pp
= ironlake_get_pp_control(intel_dp
);
2124 /* We need to switch off panel power _and_ force vdd, for otherwise some
2125 * panels get very unhappy and cease to work. */
2126 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2129 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2131 intel_dp
->want_panel_vdd
= false;
2133 I915_WRITE(pp_ctrl_reg
, pp
);
2134 POSTING_READ(pp_ctrl_reg
);
2136 intel_dp
->panel_power_off_time
= ktime_get_boottime();
2137 wait_panel_off(intel_dp
);
2139 /* We got a reference when we enabled the VDD. */
2140 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
2141 intel_display_power_put(dev_priv
, power_domain
);
2144 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2146 if (!is_edp(intel_dp
))
2150 edp_panel_off(intel_dp
);
2151 pps_unlock(intel_dp
);
2154 /* Enable backlight in the panel power control. */
2155 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2161 i915_reg_t pp_ctrl_reg
;
2164 * If we enable the backlight right away following a panel power
2165 * on, we may see slight flicker as the panel syncs with the eDP
2166 * link. So delay a bit to make sure the image is solid before
2167 * allowing it to appear.
2169 wait_backlight_on(intel_dp
);
2173 pp
= ironlake_get_pp_control(intel_dp
);
2174 pp
|= EDP_BLC_ENABLE
;
2176 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2178 I915_WRITE(pp_ctrl_reg
, pp
);
2179 POSTING_READ(pp_ctrl_reg
);
2181 pps_unlock(intel_dp
);
2184 /* Enable backlight PWM and backlight PP control. */
2185 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2187 if (!is_edp(intel_dp
))
2190 DRM_DEBUG_KMS("\n");
2192 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2193 _intel_edp_backlight_on(intel_dp
);
2196 /* Disable backlight in the panel power control. */
2197 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2199 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2202 i915_reg_t pp_ctrl_reg
;
2204 if (!is_edp(intel_dp
))
2209 pp
= ironlake_get_pp_control(intel_dp
);
2210 pp
&= ~EDP_BLC_ENABLE
;
2212 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2214 I915_WRITE(pp_ctrl_reg
, pp
);
2215 POSTING_READ(pp_ctrl_reg
);
2217 pps_unlock(intel_dp
);
2219 intel_dp
->last_backlight_off
= jiffies
;
2220 edp_wait_backlight_off(intel_dp
);
2223 /* Disable backlight PP control and backlight PWM. */
2224 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2226 if (!is_edp(intel_dp
))
2229 DRM_DEBUG_KMS("\n");
2231 _intel_edp_backlight_off(intel_dp
);
2232 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2236 * Hook for controlling the panel power control backlight through the bl_power
2237 * sysfs attribute. Take care to handle multiple calls.
2239 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2242 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2246 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2247 pps_unlock(intel_dp
);
2249 if (is_enabled
== enable
)
2252 DRM_DEBUG_KMS("panel power control backlight %s\n",
2253 enable
? "enable" : "disable");
2256 _intel_edp_backlight_on(intel_dp
);
2258 _intel_edp_backlight_off(intel_dp
);
2261 static void assert_dp_port(struct intel_dp
*intel_dp
, bool state
)
2263 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2264 struct drm_i915_private
*dev_priv
= to_i915(dig_port
->base
.base
.dev
);
2265 bool cur_state
= I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
;
2267 I915_STATE_WARN(cur_state
!= state
,
2268 "DP port %c state assertion failure (expected %s, current %s)\n",
2269 port_name(dig_port
->port
),
2270 onoff(state
), onoff(cur_state
));
2272 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2274 static void assert_edp_pll(struct drm_i915_private
*dev_priv
, bool state
)
2276 bool cur_state
= I915_READ(DP_A
) & DP_PLL_ENABLE
;
2278 I915_STATE_WARN(cur_state
!= state
,
2279 "eDP PLL state assertion failure (expected %s, current %s)\n",
2280 onoff(state
), onoff(cur_state
));
2282 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2283 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2285 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2287 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2288 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2289 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2291 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2292 assert_dp_port_disabled(intel_dp
);
2293 assert_edp_pll_disabled(dev_priv
);
2295 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2296 crtc
->config
->port_clock
);
2298 intel_dp
->DP
&= ~DP_PLL_FREQ_MASK
;
2300 if (crtc
->config
->port_clock
== 162000)
2301 intel_dp
->DP
|= DP_PLL_FREQ_162MHZ
;
2303 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
2305 I915_WRITE(DP_A
, intel_dp
->DP
);
2310 * [DevILK] Work around required when enabling DP PLL
2311 * while a pipe is enabled going to FDI:
2312 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2313 * 2. Program DP PLL enable
2315 if (IS_GEN5(dev_priv
))
2316 intel_wait_for_vblank_if_active(dev_priv
->dev
, !crtc
->pipe
);
2318 intel_dp
->DP
|= DP_PLL_ENABLE
;
2320 I915_WRITE(DP_A
, intel_dp
->DP
);
2325 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2328 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
2329 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2331 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
2332 assert_dp_port_disabled(intel_dp
);
2333 assert_edp_pll_enabled(dev_priv
);
2335 DRM_DEBUG_KMS("disabling eDP PLL\n");
2337 intel_dp
->DP
&= ~DP_PLL_ENABLE
;
2339 I915_WRITE(DP_A
, intel_dp
->DP
);
2344 /* If the sink supports it, try to set the power state appropriately */
2345 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2349 /* Should have a valid DPCD by this point */
2350 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2353 if (mode
!= DRM_MODE_DPMS_ON
) {
2354 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2358 * When turning on, we need to retry for 1ms to give the sink
2361 for (i
= 0; i
< 3; i
++) {
2362 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2371 DRM_DEBUG_KMS("failed to %s sink power state\n",
2372 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2375 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2378 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2379 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2380 struct drm_device
*dev
= encoder
->base
.dev
;
2381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2382 enum intel_display_power_domain power_domain
;
2386 power_domain
= intel_display_port_power_domain(encoder
);
2387 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2392 tmp
= I915_READ(intel_dp
->output_reg
);
2394 if (!(tmp
& DP_PORT_EN
))
2397 if (IS_GEN7(dev
) && port
== PORT_A
) {
2398 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2399 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2402 for_each_pipe(dev_priv
, p
) {
2403 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2404 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2412 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2413 i915_mmio_reg_offset(intel_dp
->output_reg
));
2414 } else if (IS_CHERRYVIEW(dev
)) {
2415 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2417 *pipe
= PORT_TO_PIPE(tmp
);
2423 intel_display_power_put(dev_priv
, power_domain
);
2428 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2429 struct intel_crtc_state
*pipe_config
)
2431 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2433 struct drm_device
*dev
= encoder
->base
.dev
;
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2436 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2438 tmp
= I915_READ(intel_dp
->output_reg
);
2440 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2442 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2443 u32 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2445 if (trans_dp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2446 flags
|= DRM_MODE_FLAG_PHSYNC
;
2448 flags
|= DRM_MODE_FLAG_NHSYNC
;
2450 if (trans_dp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2451 flags
|= DRM_MODE_FLAG_PVSYNC
;
2453 flags
|= DRM_MODE_FLAG_NVSYNC
;
2455 if (tmp
& DP_SYNC_HS_HIGH
)
2456 flags
|= DRM_MODE_FLAG_PHSYNC
;
2458 flags
|= DRM_MODE_FLAG_NHSYNC
;
2460 if (tmp
& DP_SYNC_VS_HIGH
)
2461 flags
|= DRM_MODE_FLAG_PVSYNC
;
2463 flags
|= DRM_MODE_FLAG_NVSYNC
;
2466 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2468 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2469 !IS_CHERRYVIEW(dev
) && tmp
& DP_COLOR_RANGE_16_235
)
2470 pipe_config
->limited_color_range
= true;
2472 pipe_config
->has_dp_encoder
= true;
2474 pipe_config
->lane_count
=
2475 ((tmp
& DP_PORT_WIDTH_MASK
) >> DP_PORT_WIDTH_SHIFT
) + 1;
2477 intel_dp_get_m_n(crtc
, pipe_config
);
2479 if (port
== PORT_A
) {
2480 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_162MHZ
)
2481 pipe_config
->port_clock
= 162000;
2483 pipe_config
->port_clock
= 270000;
2486 pipe_config
->base
.adjusted_mode
.crtc_clock
=
2487 intel_dotclock_calculate(pipe_config
->port_clock
,
2488 &pipe_config
->dp_m_n
);
2490 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp
.bpp
&&
2491 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp
.bpp
) {
2493 * This is a big fat ugly hack.
2495 * Some machines in UEFI boot mode provide us a VBT that has 18
2496 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2497 * unknown we fail to light up. Yet the same BIOS boots up with
2498 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2499 * max, not what it tells us to use.
2501 * Note: This will still be broken if the eDP panel is not lit
2502 * up by the BIOS, and thus we can't get the mode at module
2505 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2506 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp
.bpp
);
2507 dev_priv
->vbt
.edp
.bpp
= pipe_config
->pipe_bpp
;
2511 static void intel_disable_dp(struct intel_encoder
*encoder
)
2513 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2514 struct drm_device
*dev
= encoder
->base
.dev
;
2515 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2517 if (crtc
->config
->has_audio
)
2518 intel_audio_codec_disable(encoder
);
2520 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2521 intel_psr_disable(intel_dp
);
2523 /* Make sure the panel is off before trying to change the mode. But also
2524 * ensure that we have vdd while we switch off the panel. */
2525 intel_edp_panel_vdd_on(intel_dp
);
2526 intel_edp_backlight_off(intel_dp
);
2527 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2528 intel_edp_panel_off(intel_dp
);
2530 /* disable the port before the pipe on g4x */
2531 if (INTEL_INFO(dev
)->gen
< 5)
2532 intel_dp_link_down(intel_dp
);
2535 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2537 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2538 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2540 intel_dp_link_down(intel_dp
);
2542 /* Only ilk+ has port A */
2544 ironlake_edp_pll_off(intel_dp
);
2547 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2549 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2551 intel_dp_link_down(intel_dp
);
2554 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2556 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2557 struct drm_device
*dev
= encoder
->base
.dev
;
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2560 intel_dp_link_down(intel_dp
);
2562 mutex_lock(&dev_priv
->sb_lock
);
2564 /* Assert data lane reset */
2565 chv_data_lane_soft_reset(encoder
, true);
2567 mutex_unlock(&dev_priv
->sb_lock
);
2571 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2573 uint8_t dp_train_pat
)
2575 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2576 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2578 enum port port
= intel_dig_port
->port
;
2581 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2583 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2584 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2586 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2588 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2589 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2590 case DP_TRAINING_PATTERN_DISABLE
:
2591 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2594 case DP_TRAINING_PATTERN_1
:
2595 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2597 case DP_TRAINING_PATTERN_2
:
2598 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2600 case DP_TRAINING_PATTERN_3
:
2601 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2604 I915_WRITE(DP_TP_CTL(port
), temp
);
2606 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2607 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2608 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2610 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2611 case DP_TRAINING_PATTERN_DISABLE
:
2612 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2614 case DP_TRAINING_PATTERN_1
:
2615 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2617 case DP_TRAINING_PATTERN_2
:
2618 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2620 case DP_TRAINING_PATTERN_3
:
2621 DRM_ERROR("DP training pattern 3 not supported\n");
2622 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2627 if (IS_CHERRYVIEW(dev
))
2628 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2630 *DP
&= ~DP_LINK_TRAIN_MASK
;
2632 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2633 case DP_TRAINING_PATTERN_DISABLE
:
2634 *DP
|= DP_LINK_TRAIN_OFF
;
2636 case DP_TRAINING_PATTERN_1
:
2637 *DP
|= DP_LINK_TRAIN_PAT_1
;
2639 case DP_TRAINING_PATTERN_2
:
2640 *DP
|= DP_LINK_TRAIN_PAT_2
;
2642 case DP_TRAINING_PATTERN_3
:
2643 if (IS_CHERRYVIEW(dev
)) {
2644 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2646 DRM_ERROR("DP training pattern 3 not supported\n");
2647 *DP
|= DP_LINK_TRAIN_PAT_2
;
2654 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2656 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2658 struct intel_crtc
*crtc
=
2659 to_intel_crtc(dp_to_dig_port(intel_dp
)->base
.base
.crtc
);
2661 /* enable with pattern 1 (as per spec) */
2662 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2663 DP_TRAINING_PATTERN_1
);
2665 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2666 POSTING_READ(intel_dp
->output_reg
);
2669 * Magic for VLV/CHV. We _must_ first set up the register
2670 * without actually enabling the port, and then do another
2671 * write to enable the port. Otherwise link training will
2672 * fail when the power sequencer is freshly used for this port.
2674 intel_dp
->DP
|= DP_PORT_EN
;
2675 if (crtc
->config
->has_audio
)
2676 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
2678 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2679 POSTING_READ(intel_dp
->output_reg
);
2682 static void intel_enable_dp(struct intel_encoder
*encoder
)
2684 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2685 struct drm_device
*dev
= encoder
->base
.dev
;
2686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2687 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2688 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2689 enum pipe pipe
= crtc
->pipe
;
2691 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2696 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2697 vlv_init_panel_power_sequencer(intel_dp
);
2699 intel_dp_enable_port(intel_dp
);
2701 edp_panel_vdd_on(intel_dp
);
2702 edp_panel_on(intel_dp
);
2703 edp_panel_vdd_off(intel_dp
, true);
2705 pps_unlock(intel_dp
);
2707 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2708 unsigned int lane_mask
= 0x0;
2710 if (IS_CHERRYVIEW(dev
))
2711 lane_mask
= intel_dp_unused_lane_mask(crtc
->config
->lane_count
);
2713 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2717 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2718 intel_dp_start_link_train(intel_dp
);
2719 intel_dp_stop_link_train(intel_dp
);
2721 if (crtc
->config
->has_audio
) {
2722 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2724 intel_audio_codec_enable(encoder
);
2728 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2730 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2732 intel_enable_dp(encoder
);
2733 intel_edp_backlight_on(intel_dp
);
2736 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2738 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2740 intel_edp_backlight_on(intel_dp
);
2741 intel_psr_enable(intel_dp
);
2744 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2746 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2747 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2749 intel_dp_prepare(encoder
);
2751 /* Only ilk+ has port A */
2753 ironlake_edp_pll_on(intel_dp
);
2756 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2758 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2759 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2760 enum pipe pipe
= intel_dp
->pps_pipe
;
2761 i915_reg_t pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2763 edp_panel_vdd_off_sync(intel_dp
);
2766 * VLV seems to get confused when multiple power seqeuencers
2767 * have the same port selected (even if only one has power/vdd
2768 * enabled). The failure manifests as vlv_wait_port_ready() failing
2769 * CHV on the other hand doesn't seem to mind having the same port
2770 * selected in multiple power seqeuencers, but let's clear the
2771 * port select always when logically disconnecting a power sequencer
2774 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2775 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2776 I915_WRITE(pp_on_reg
, 0);
2777 POSTING_READ(pp_on_reg
);
2779 intel_dp
->pps_pipe
= INVALID_PIPE
;
2782 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2786 struct intel_encoder
*encoder
;
2788 lockdep_assert_held(&dev_priv
->pps_mutex
);
2790 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2793 for_each_intel_encoder(dev
, encoder
) {
2794 struct intel_dp
*intel_dp
;
2797 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2800 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2801 port
= dp_to_dig_port(intel_dp
)->port
;
2803 if (intel_dp
->pps_pipe
!= pipe
)
2806 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2807 pipe_name(pipe
), port_name(port
));
2809 WARN(encoder
->base
.crtc
,
2810 "stealing pipe %c power sequencer from active eDP port %c\n",
2811 pipe_name(pipe
), port_name(port
));
2813 /* make sure vdd is off before we steal it */
2814 vlv_detach_power_sequencer(intel_dp
);
2818 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2820 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2821 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2822 struct drm_device
*dev
= encoder
->base
.dev
;
2823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2824 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2826 lockdep_assert_held(&dev_priv
->pps_mutex
);
2828 if (!is_edp(intel_dp
))
2831 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2835 * If another power sequencer was being used on this
2836 * port previously make sure to turn off vdd there while
2837 * we still have control of it.
2839 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2840 vlv_detach_power_sequencer(intel_dp
);
2843 * We may be stealing the power
2844 * sequencer from another port.
2846 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2848 /* now it's all ours */
2849 intel_dp
->pps_pipe
= crtc
->pipe
;
2851 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2852 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2854 /* init power sequencer on this pipe and port */
2855 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2856 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2859 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2861 vlv_phy_pre_encoder_enable(encoder
);
2863 intel_enable_dp(encoder
);
2866 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2868 intel_dp_prepare(encoder
);
2870 vlv_phy_pre_pll_enable(encoder
);
2873 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2875 chv_phy_pre_encoder_enable(encoder
);
2877 intel_enable_dp(encoder
);
2879 /* Second common lane will stay alive on its own now */
2880 chv_phy_release_cl2_override(encoder
);
2883 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2885 intel_dp_prepare(encoder
);
2887 chv_phy_pre_pll_enable(encoder
);
2890 static void chv_dp_post_pll_disable(struct intel_encoder
*encoder
)
2892 chv_phy_post_pll_disable(encoder
);
2896 * Fetch AUX CH registers 0x202 - 0x207 which contain
2897 * link status information
2900 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2902 return drm_dp_dpcd_read(&intel_dp
->aux
, DP_LANE0_1_STATUS
, link_status
,
2903 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2906 /* These are source-specific values. */
2908 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2910 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2912 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2914 if (IS_BROXTON(dev
))
2915 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2916 else if (INTEL_INFO(dev
)->gen
>= 9) {
2917 if (dev_priv
->vbt
.edp
.low_vswing
&& port
== PORT_A
)
2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2919 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2920 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
2921 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2922 else if (IS_GEN7(dev
) && port
== PORT_A
)
2923 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2924 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2925 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2927 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2931 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2933 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2934 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2936 if (INTEL_INFO(dev
)->gen
>= 9) {
2937 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2947 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2949 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2950 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2952 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2961 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
2962 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2968 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2973 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2974 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2979 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2981 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2984 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2986 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2987 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2988 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2990 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2993 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2998 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3000 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3001 unsigned long demph_reg_value
, preemph_reg_value
,
3002 uniqtranscale_reg_value
;
3003 uint8_t train_set
= intel_dp
->train_set
[0];
3005 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3006 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3007 preemph_reg_value
= 0x0004000;
3008 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3010 demph_reg_value
= 0x2B405555;
3011 uniqtranscale_reg_value
= 0x552AB83A;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3014 demph_reg_value
= 0x2B404040;
3015 uniqtranscale_reg_value
= 0x5548B83A;
3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3018 demph_reg_value
= 0x2B245555;
3019 uniqtranscale_reg_value
= 0x5560B83A;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3022 demph_reg_value
= 0x2B405555;
3023 uniqtranscale_reg_value
= 0x5598DA3A;
3029 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3030 preemph_reg_value
= 0x0002000;
3031 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3033 demph_reg_value
= 0x2B404040;
3034 uniqtranscale_reg_value
= 0x5552B83A;
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3037 demph_reg_value
= 0x2B404848;
3038 uniqtranscale_reg_value
= 0x5580B83A;
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3041 demph_reg_value
= 0x2B404040;
3042 uniqtranscale_reg_value
= 0x55ADDA3A;
3048 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3049 preemph_reg_value
= 0x0000000;
3050 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3052 demph_reg_value
= 0x2B305555;
3053 uniqtranscale_reg_value
= 0x5570B83A;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3056 demph_reg_value
= 0x2B2B4040;
3057 uniqtranscale_reg_value
= 0x55ADDA3A;
3063 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3064 preemph_reg_value
= 0x0006000;
3065 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3067 demph_reg_value
= 0x1B405555;
3068 uniqtranscale_reg_value
= 0x55ADDA3A;
3078 vlv_set_phy_signal_level(encoder
, demph_reg_value
, preemph_reg_value
,
3079 uniqtranscale_reg_value
, 0);
3084 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3086 struct intel_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
;
3087 u32 deemph_reg_value
, margin_reg_value
;
3088 bool uniq_trans_scale
= false;
3089 uint8_t train_set
= intel_dp
->train_set
[0];
3091 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3092 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3093 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3095 deemph_reg_value
= 128;
3096 margin_reg_value
= 52;
3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3099 deemph_reg_value
= 128;
3100 margin_reg_value
= 77;
3102 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3103 deemph_reg_value
= 128;
3104 margin_reg_value
= 102;
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3107 deemph_reg_value
= 128;
3108 margin_reg_value
= 154;
3109 uniq_trans_scale
= true;
3115 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3116 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3117 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3118 deemph_reg_value
= 85;
3119 margin_reg_value
= 78;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3122 deemph_reg_value
= 85;
3123 margin_reg_value
= 116;
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3126 deemph_reg_value
= 85;
3127 margin_reg_value
= 154;
3133 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3134 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3136 deemph_reg_value
= 64;
3137 margin_reg_value
= 104;
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3140 deemph_reg_value
= 64;
3141 margin_reg_value
= 154;
3147 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3148 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3150 deemph_reg_value
= 43;
3151 margin_reg_value
= 154;
3161 chv_set_phy_signal_level(encoder
, deemph_reg_value
,
3162 margin_reg_value
, uniq_trans_scale
);
3168 gen4_signal_levels(uint8_t train_set
)
3170 uint32_t signal_levels
= 0;
3172 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3175 signal_levels
|= DP_VOLTAGE_0_4
;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3178 signal_levels
|= DP_VOLTAGE_0_6
;
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3181 signal_levels
|= DP_VOLTAGE_0_8
;
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3184 signal_levels
|= DP_VOLTAGE_1_2
;
3187 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3188 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3190 signal_levels
|= DP_PRE_EMPHASIS_0
;
3192 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3193 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3195 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3196 signal_levels
|= DP_PRE_EMPHASIS_6
;
3198 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3199 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3202 return signal_levels
;
3205 /* Gen6's DP voltage swing and pre-emphasis control */
3207 gen6_edp_signal_levels(uint8_t train_set
)
3209 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3210 DP_TRAIN_PRE_EMPHASIS_MASK
);
3211 switch (signal_levels
) {
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3214 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3216 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3219 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3222 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3225 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3227 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3228 "0x%x\n", signal_levels
);
3229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3233 /* Gen7's DP voltage swing and pre-emphasis control */
3235 gen7_edp_signal_levels(uint8_t train_set
)
3237 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3238 DP_TRAIN_PRE_EMPHASIS_MASK
);
3239 switch (signal_levels
) {
3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3241 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3243 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3245 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3248 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3250 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3253 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3255 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3258 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3259 "0x%x\n", signal_levels
);
3260 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3265 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
)
3267 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3268 enum port port
= intel_dig_port
->port
;
3269 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3270 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3271 uint32_t signal_levels
, mask
= 0;
3272 uint8_t train_set
= intel_dp
->train_set
[0];
3275 signal_levels
= ddi_signal_levels(intel_dp
);
3277 if (IS_BROXTON(dev
))
3280 mask
= DDI_BUF_EMP_MASK
;
3281 } else if (IS_CHERRYVIEW(dev
)) {
3282 signal_levels
= chv_signal_levels(intel_dp
);
3283 } else if (IS_VALLEYVIEW(dev
)) {
3284 signal_levels
= vlv_signal_levels(intel_dp
);
3285 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3286 signal_levels
= gen7_edp_signal_levels(train_set
);
3287 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3288 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3289 signal_levels
= gen6_edp_signal_levels(train_set
);
3290 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3292 signal_levels
= gen4_signal_levels(train_set
);
3293 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3297 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3299 DRM_DEBUG_KMS("Using vswing level %d\n",
3300 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3301 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3302 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3303 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3305 intel_dp
->DP
= (intel_dp
->DP
& ~mask
) | signal_levels
;
3307 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3308 POSTING_READ(intel_dp
->output_reg
);
3312 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
3313 uint8_t dp_train_pat
)
3315 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3316 struct drm_i915_private
*dev_priv
=
3317 to_i915(intel_dig_port
->base
.base
.dev
);
3319 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
, dp_train_pat
);
3321 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
3322 POSTING_READ(intel_dp
->output_reg
);
3325 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 enum port port
= intel_dig_port
->port
;
3336 val
= I915_READ(DP_TP_CTL(port
));
3337 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3338 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3339 I915_WRITE(DP_TP_CTL(port
), val
);
3342 * On PORT_A we can have only eDP in SST mode. There the only reason
3343 * we need to set idle transmission mode is to work around a HW issue
3344 * where we enable the pipe while not in idle link-training mode.
3345 * In this case there is requirement to wait for a minimum number of
3346 * idle patterns to be sent.
3351 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3353 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3357 intel_dp_link_down(struct intel_dp
*intel_dp
)
3359 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3360 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3361 enum port port
= intel_dig_port
->port
;
3362 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 uint32_t DP
= intel_dp
->DP
;
3366 if (WARN_ON(HAS_DDI(dev
)))
3369 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3372 DRM_DEBUG_KMS("\n");
3374 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3375 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3376 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3377 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3379 if (IS_CHERRYVIEW(dev
))
3380 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3382 DP
&= ~DP_LINK_TRAIN_MASK
;
3383 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3385 I915_WRITE(intel_dp
->output_reg
, DP
);
3386 POSTING_READ(intel_dp
->output_reg
);
3388 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3389 I915_WRITE(intel_dp
->output_reg
, DP
);
3390 POSTING_READ(intel_dp
->output_reg
);
3393 * HW workaround for IBX, we need to move the port
3394 * to transcoder A after disabling it to allow the
3395 * matching HDMI port to be enabled on transcoder A.
3397 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3399 * We get CPU/PCH FIFO underruns on the other pipe when
3400 * doing the workaround. Sweep them under the rug.
3402 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3403 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
3405 /* always enable with pattern 1 (as per spec) */
3406 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3407 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3408 I915_WRITE(intel_dp
->output_reg
, DP
);
3409 POSTING_READ(intel_dp
->output_reg
);
3412 I915_WRITE(intel_dp
->output_reg
, DP
);
3413 POSTING_READ(intel_dp
->output_reg
);
3415 intel_wait_for_vblank_if_active(dev_priv
->dev
, PIPE_A
);
3416 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3417 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
3420 msleep(intel_dp
->panel_power_down_delay
);
3426 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3428 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3429 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3432 if (drm_dp_dpcd_read(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3433 sizeof(intel_dp
->dpcd
)) < 0)
3434 return false; /* aux transfer failed */
3436 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3438 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3439 return false; /* DPCD not present */
3441 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_COUNT
,
3442 &intel_dp
->sink_count
, 1) < 0)
3446 * Sink count can change between short pulse hpd hence
3447 * a member variable in intel_dp will track any changes
3448 * between short pulse interrupts.
3450 intel_dp
->sink_count
= DP_GET_SINK_COUNT(intel_dp
->sink_count
);
3453 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3454 * a dongle is present but no display. Unless we require to know
3455 * if a dongle is present or not, we don't need to update
3456 * downstream port information. So, an early return here saves
3457 * time from performing other operations which are not required.
3459 if (!is_edp(intel_dp
) && !intel_dp
->sink_count
)
3462 /* Check if the panel supports PSR */
3463 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3464 if (is_edp(intel_dp
)) {
3465 drm_dp_dpcd_read(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3467 sizeof(intel_dp
->psr_dpcd
));
3468 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3469 dev_priv
->psr
.sink_support
= true;
3470 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3473 if (INTEL_INFO(dev
)->gen
>= 9 &&
3474 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3475 uint8_t frame_sync_cap
;
3477 dev_priv
->psr
.sink_support
= true;
3478 drm_dp_dpcd_read(&intel_dp
->aux
,
3479 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3480 &frame_sync_cap
, 1);
3481 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3482 /* PSR2 needs frame sync as well */
3483 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3484 DRM_DEBUG_KMS("PSR2 %s on sink",
3485 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3488 /* Read the eDP Display control capabilities registers */
3489 memset(intel_dp
->edp_dpcd
, 0, sizeof(intel_dp
->edp_dpcd
));
3490 if ((intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3491 (drm_dp_dpcd_read(&intel_dp
->aux
, DP_EDP_DPCD_REV
,
3492 intel_dp
->edp_dpcd
, sizeof(intel_dp
->edp_dpcd
)) ==
3493 sizeof(intel_dp
->edp_dpcd
)))
3494 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp
->edp_dpcd
),
3495 intel_dp
->edp_dpcd
);
3498 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3499 yesno(intel_dp_source_supports_hbr2(intel_dp
)),
3500 yesno(drm_dp_tps3_supported(intel_dp
->dpcd
)));
3502 /* Intermediate frequency support */
3503 if (is_edp(intel_dp
) && (intel_dp
->edp_dpcd
[0] >= 0x03)) { /* eDp v1.4 or higher */
3504 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3507 drm_dp_dpcd_read(&intel_dp
->aux
, DP_SUPPORTED_LINK_RATES
,
3508 sink_rates
, sizeof(sink_rates
));
3510 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3511 int val
= le16_to_cpu(sink_rates
[i
]);
3516 /* Value read is in kHz while drm clock is saved in deca-kHz */
3517 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3519 intel_dp
->num_sink_rates
= i
;
3522 intel_dp_print_rates(intel_dp
);
3524 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3525 DP_DWN_STRM_PORT_PRESENT
))
3526 return true; /* native DP sink */
3528 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3529 return true; /* no per-port downstream info */
3531 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3532 intel_dp
->downstream_ports
,
3533 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3534 return false; /* downstream port status fetch failed */
3540 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3544 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3547 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3548 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3549 buf
[0], buf
[1], buf
[2]);
3551 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3552 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3553 buf
[0], buf
[1], buf
[2]);
3557 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3561 if (!i915
.enable_dp_mst
)
3564 if (!intel_dp
->can_mst
)
3567 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3570 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3571 if (buf
[0] & DP_MST_CAP
) {
3572 DRM_DEBUG_KMS("Sink is MST capable\n");
3573 intel_dp
->is_mst
= true;
3575 DRM_DEBUG_KMS("Sink is not MST capable\n");
3576 intel_dp
->is_mst
= false;
3580 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3581 return intel_dp
->is_mst
;
3584 static int intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
3586 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3587 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3588 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3594 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
3595 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3600 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3601 buf
& ~DP_TEST_SINK_START
) < 0) {
3602 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3608 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3610 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3611 DP_TEST_SINK_MISC
, &buf
) < 0) {
3615 count
= buf
& DP_TEST_COUNT_MASK
;
3616 } while (--attempts
&& count
);
3618 if (attempts
== 0) {
3619 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3624 hsw_enable_ips(intel_crtc
);
3628 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
3630 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3631 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3632 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3636 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3639 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3642 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3645 if (buf
& DP_TEST_SINK_START
) {
3646 ret
= intel_dp_sink_crc_stop(intel_dp
);
3651 hsw_disable_ips(intel_crtc
);
3653 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3654 buf
| DP_TEST_SINK_START
) < 0) {
3655 hsw_enable_ips(intel_crtc
);
3659 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3663 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3665 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3666 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3667 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
3672 ret
= intel_dp_sink_crc_start(intel_dp
);
3677 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3679 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
3680 DP_TEST_SINK_MISC
, &buf
) < 0) {
3684 count
= buf
& DP_TEST_COUNT_MASK
;
3686 } while (--attempts
&& count
== 0);
3688 if (attempts
== 0) {
3689 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3694 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0) {
3700 intel_dp_sink_crc_stop(intel_dp
);
3705 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3707 return drm_dp_dpcd_read(&intel_dp
->aux
,
3708 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3709 sink_irq_vector
, 1) == 1;
3713 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3717 ret
= drm_dp_dpcd_read(&intel_dp
->aux
,
3719 sink_irq_vector
, 14);
3726 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
3728 uint8_t test_result
= DP_TEST_ACK
;
3732 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
3734 uint8_t test_result
= DP_TEST_NAK
;
3738 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
3740 uint8_t test_result
= DP_TEST_NAK
;
3741 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
3742 struct drm_connector
*connector
= &intel_connector
->base
;
3744 if (intel_connector
->detect_edid
== NULL
||
3745 connector
->edid_corrupt
||
3746 intel_dp
->aux
.i2c_defer_count
> 6) {
3747 /* Check EDID read for NACKs, DEFERs and corruption
3748 * (DP CTS 1.2 Core r1.1)
3749 * 4.2.2.4 : Failed EDID read, I2C_NAK
3750 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3751 * 4.2.2.6 : EDID corruption detected
3752 * Use failsafe mode for all cases
3754 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
3755 intel_dp
->aux
.i2c_defer_count
> 0)
3756 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3757 intel_dp
->aux
.i2c_nack_count
,
3758 intel_dp
->aux
.i2c_defer_count
);
3759 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
3761 struct edid
*block
= intel_connector
->detect_edid
;
3763 /* We have to write the checksum
3764 * of the last block read
3766 block
+= intel_connector
->detect_edid
->extensions
;
3768 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
3769 DP_TEST_EDID_CHECKSUM
,
3772 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3774 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
3775 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
3778 /* Set test active flag here so userspace doesn't interrupt things */
3779 intel_dp
->compliance_test_active
= 1;
3784 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
3786 uint8_t test_result
= DP_TEST_NAK
;
3790 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3792 uint8_t response
= DP_TEST_NAK
;
3796 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
3798 DRM_DEBUG_KMS("Could not read test request from sink\n");
3803 case DP_TEST_LINK_TRAINING
:
3804 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3805 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
3806 response
= intel_dp_autotest_link_training(intel_dp
);
3808 case DP_TEST_LINK_VIDEO_PATTERN
:
3809 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3810 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
3811 response
= intel_dp_autotest_video_pattern(intel_dp
);
3813 case DP_TEST_LINK_EDID_READ
:
3814 DRM_DEBUG_KMS("EDID test requested\n");
3815 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
3816 response
= intel_dp_autotest_edid(intel_dp
);
3818 case DP_TEST_LINK_PHY_TEST_PATTERN
:
3819 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3820 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
3821 response
= intel_dp_autotest_phy_pattern(intel_dp
);
3824 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
3829 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
3833 DRM_DEBUG_KMS("Could not write test response to sink\n");
3837 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3841 if (intel_dp
->is_mst
) {
3846 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3850 /* check link status - esi[10] = 0x200c */
3851 if (intel_dp
->active_mst_links
&&
3852 !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3853 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3854 intel_dp_start_link_train(intel_dp
);
3855 intel_dp_stop_link_train(intel_dp
);
3858 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
3859 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3862 for (retry
= 0; retry
< 3; retry
++) {
3864 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3865 DP_SINK_COUNT_ESI
+1,
3872 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3874 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
3882 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3883 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3884 intel_dp
->is_mst
= false;
3885 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3886 /* send a hotplug event */
3887 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3894 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3896 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3897 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3898 u8 link_status
[DP_LINK_STATUS_SIZE
];
3900 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3902 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3903 DRM_ERROR("Failed to get link status\n");
3907 if (!intel_encoder
->base
.crtc
)
3910 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3913 /* if link training is requested we should perform it always */
3914 if ((intel_dp
->compliance_test_type
== DP_TEST_LINK_TRAINING
) ||
3915 (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
))) {
3916 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3917 intel_encoder
->base
.name
);
3918 intel_dp_start_link_train(intel_dp
);
3919 intel_dp_stop_link_train(intel_dp
);
3924 * According to DP spec
3927 * 2. Configure link according to Receiver Capabilities
3928 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3929 * 4. Check link status on receipt of hot-plug interrupt
3931 * intel_dp_short_pulse - handles short pulse interrupts
3932 * when full detection is not required.
3933 * Returns %true if short pulse is handled and full detection
3934 * is NOT required and %false otherwise.
3937 intel_dp_short_pulse(struct intel_dp
*intel_dp
)
3939 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3941 u8 old_sink_count
= intel_dp
->sink_count
;
3945 * Clearing compliance test variables to allow capturing
3946 * of values for next automated test request.
3948 intel_dp
->compliance_test_active
= 0;
3949 intel_dp
->compliance_test_type
= 0;
3950 intel_dp
->compliance_test_data
= 0;
3953 * Now read the DPCD to see if it's actually running
3954 * If the current value of sink count doesn't match with
3955 * the value that was stored earlier or dpcd read failed
3956 * we need to do full detection
3958 ret
= intel_dp_get_dpcd(intel_dp
);
3960 if ((old_sink_count
!= intel_dp
->sink_count
) || !ret
) {
3961 /* No need to proceed if we are going to do full detect */
3965 /* Try to read the source of the interrupt */
3966 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3967 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3968 /* Clear interrupt source */
3969 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3970 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3973 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3974 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3975 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3976 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3979 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
3980 intel_dp_check_link_status(intel_dp
);
3981 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
3986 /* XXX this is probably wrong for multiple downstream ports */
3987 static enum drm_connector_status
3988 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3990 uint8_t *dpcd
= intel_dp
->dpcd
;
3993 if (!intel_dp_get_dpcd(intel_dp
))
3994 return connector_status_disconnected
;
3996 if (is_edp(intel_dp
))
3997 return connector_status_connected
;
3999 /* if there's no downstream port, we're done */
4000 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4001 return connector_status_connected
;
4003 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4004 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4005 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4007 return intel_dp
->sink_count
?
4008 connector_status_connected
: connector_status_disconnected
;
4011 /* If no HPD, poke DDC gently */
4012 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4013 return connector_status_connected
;
4015 /* Well we tried, say unknown for unreliable port types */
4016 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4017 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4018 if (type
== DP_DS_PORT_TYPE_VGA
||
4019 type
== DP_DS_PORT_TYPE_NON_EDID
)
4020 return connector_status_unknown
;
4022 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4023 DP_DWN_STRM_PORT_TYPE_MASK
;
4024 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4025 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4026 return connector_status_unknown
;
4029 /* Anything else is out of spec, warn and ignore */
4030 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4031 return connector_status_disconnected
;
4034 static enum drm_connector_status
4035 edp_detect(struct intel_dp
*intel_dp
)
4037 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4038 enum drm_connector_status status
;
4040 status
= intel_panel_detect(dev
);
4041 if (status
== connector_status_unknown
)
4042 status
= connector_status_connected
;
4047 static bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
4048 struct intel_digital_port
*port
)
4052 switch (port
->port
) {
4056 bit
= SDE_PORTB_HOTPLUG
;
4059 bit
= SDE_PORTC_HOTPLUG
;
4062 bit
= SDE_PORTD_HOTPLUG
;
4065 MISSING_CASE(port
->port
);
4069 return I915_READ(SDEISR
) & bit
;
4072 static bool cpt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4073 struct intel_digital_port
*port
)
4077 switch (port
->port
) {
4081 bit
= SDE_PORTB_HOTPLUG_CPT
;
4084 bit
= SDE_PORTC_HOTPLUG_CPT
;
4087 bit
= SDE_PORTD_HOTPLUG_CPT
;
4090 bit
= SDE_PORTE_HOTPLUG_SPT
;
4093 MISSING_CASE(port
->port
);
4097 return I915_READ(SDEISR
) & bit
;
4100 static bool g4x_digital_port_connected(struct drm_i915_private
*dev_priv
,
4101 struct intel_digital_port
*port
)
4105 switch (port
->port
) {
4107 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4110 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4113 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4116 MISSING_CASE(port
->port
);
4120 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4123 static bool gm45_digital_port_connected(struct drm_i915_private
*dev_priv
,
4124 struct intel_digital_port
*port
)
4128 switch (port
->port
) {
4130 bit
= PORTB_HOTPLUG_LIVE_STATUS_GM45
;
4133 bit
= PORTC_HOTPLUG_LIVE_STATUS_GM45
;
4136 bit
= PORTD_HOTPLUG_LIVE_STATUS_GM45
;
4139 MISSING_CASE(port
->port
);
4143 return I915_READ(PORT_HOTPLUG_STAT
) & bit
;
4146 static bool bxt_digital_port_connected(struct drm_i915_private
*dev_priv
,
4147 struct intel_digital_port
*intel_dig_port
)
4149 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4153 intel_hpd_pin_to_port(intel_encoder
->hpd_pin
, &port
);
4156 bit
= BXT_DE_PORT_HP_DDIA
;
4159 bit
= BXT_DE_PORT_HP_DDIB
;
4162 bit
= BXT_DE_PORT_HP_DDIC
;
4169 return I915_READ(GEN8_DE_PORT_ISR
) & bit
;
4173 * intel_digital_port_connected - is the specified port connected?
4174 * @dev_priv: i915 private structure
4175 * @port: the port to test
4177 * Return %true if @port is connected, %false otherwise.
4179 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
4180 struct intel_digital_port
*port
)
4182 if (HAS_PCH_IBX(dev_priv
))
4183 return ibx_digital_port_connected(dev_priv
, port
);
4184 else if (HAS_PCH_SPLIT(dev_priv
))
4185 return cpt_digital_port_connected(dev_priv
, port
);
4186 else if (IS_BROXTON(dev_priv
))
4187 return bxt_digital_port_connected(dev_priv
, port
);
4188 else if (IS_GM45(dev_priv
))
4189 return gm45_digital_port_connected(dev_priv
, port
);
4191 return g4x_digital_port_connected(dev_priv
, port
);
4194 static struct edid
*
4195 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4197 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4199 /* use cached edid if we have one */
4200 if (intel_connector
->edid
) {
4202 if (IS_ERR(intel_connector
->edid
))
4205 return drm_edid_duplicate(intel_connector
->edid
);
4207 return drm_get_edid(&intel_connector
->base
,
4208 &intel_dp
->aux
.ddc
);
4212 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4214 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4217 intel_dp_unset_edid(intel_dp
);
4218 edid
= intel_dp_get_edid(intel_dp
);
4219 intel_connector
->detect_edid
= edid
;
4221 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4222 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4224 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4228 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4230 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4232 kfree(intel_connector
->detect_edid
);
4233 intel_connector
->detect_edid
= NULL
;
4235 intel_dp
->has_audio
= false;
4239 intel_dp_long_pulse(struct intel_connector
*intel_connector
)
4241 struct drm_connector
*connector
= &intel_connector
->base
;
4242 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4243 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4244 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4245 struct drm_device
*dev
= connector
->dev
;
4246 enum drm_connector_status status
;
4247 enum intel_display_power_domain power_domain
;
4251 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4252 intel_display_power_get(to_i915(dev
), power_domain
);
4254 /* Can't disconnect eDP, but you can close the lid... */
4255 if (is_edp(intel_dp
))
4256 status
= edp_detect(intel_dp
);
4257 else if (intel_digital_port_connected(to_i915(dev
),
4258 dp_to_dig_port(intel_dp
)))
4259 status
= intel_dp_detect_dpcd(intel_dp
);
4261 status
= connector_status_disconnected
;
4263 if (status
!= connector_status_connected
) {
4264 intel_dp
->compliance_test_active
= 0;
4265 intel_dp
->compliance_test_type
= 0;
4266 intel_dp
->compliance_test_data
= 0;
4268 if (intel_dp
->is_mst
) {
4269 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4271 intel_dp
->mst_mgr
.mst_state
);
4272 intel_dp
->is_mst
= false;
4273 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4280 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4281 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4283 intel_dp_probe_oui(intel_dp
);
4285 ret
= intel_dp_probe_mst(intel_dp
);
4288 * If we are in MST mode then this connector
4289 * won't appear connected or have anything
4292 status
= connector_status_disconnected
;
4294 } else if (connector
->status
== connector_status_connected
) {
4296 * If display was connected already and is still connected
4297 * check links status, there has been known issues of
4298 * link loss triggerring long pulse!!!!
4300 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4301 intel_dp_check_link_status(intel_dp
);
4302 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4307 * Clearing NACK and defer counts to get their exact values
4308 * while reading EDID which are required by Compliance tests
4309 * 4.2.2.4 and 4.2.2.5
4311 intel_dp
->aux
.i2c_nack_count
= 0;
4312 intel_dp
->aux
.i2c_defer_count
= 0;
4314 intel_dp_set_edid(intel_dp
);
4316 status
= connector_status_connected
;
4317 intel_dp
->detect_done
= true;
4319 /* Try to read the source of the interrupt */
4320 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4321 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4322 /* Clear interrupt source */
4323 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4324 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4327 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4328 intel_dp_handle_test_request(intel_dp
);
4329 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4330 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4334 if ((status
!= connector_status_connected
) &&
4335 (intel_dp
->is_mst
== false))
4336 intel_dp_unset_edid(intel_dp
);
4338 intel_display_power_put(to_i915(dev
), power_domain
);
4342 static enum drm_connector_status
4343 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4345 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4346 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4347 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4348 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4350 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4351 connector
->base
.id
, connector
->name
);
4353 if (intel_dp
->is_mst
) {
4354 /* MST devices are disconnected from a monitor POV */
4355 intel_dp_unset_edid(intel_dp
);
4356 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4357 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4358 return connector_status_disconnected
;
4361 /* If full detect is not performed yet, do a full detect */
4362 if (!intel_dp
->detect_done
)
4363 intel_dp_long_pulse(intel_dp
->attached_connector
);
4365 intel_dp
->detect_done
= false;
4367 if (intel_connector
->detect_edid
)
4368 return connector_status_connected
;
4370 return connector_status_disconnected
;
4374 intel_dp_force(struct drm_connector
*connector
)
4376 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4377 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4378 struct drm_i915_private
*dev_priv
= to_i915(intel_encoder
->base
.dev
);
4379 enum intel_display_power_domain power_domain
;
4381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4382 connector
->base
.id
, connector
->name
);
4383 intel_dp_unset_edid(intel_dp
);
4385 if (connector
->status
!= connector_status_connected
)
4388 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4389 intel_display_power_get(dev_priv
, power_domain
);
4391 intel_dp_set_edid(intel_dp
);
4393 intel_display_power_put(dev_priv
, power_domain
);
4395 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4396 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4399 static int intel_dp_get_modes(struct drm_connector
*connector
)
4401 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4404 edid
= intel_connector
->detect_edid
;
4406 int ret
= intel_connector_update_modes(connector
, edid
);
4411 /* if eDP has no EDID, fall back to fixed mode */
4412 if (is_edp(intel_attached_dp(connector
)) &&
4413 intel_connector
->panel
.fixed_mode
) {
4414 struct drm_display_mode
*mode
;
4416 mode
= drm_mode_duplicate(connector
->dev
,
4417 intel_connector
->panel
.fixed_mode
);
4419 drm_mode_probed_add(connector
, mode
);
4428 intel_dp_detect_audio(struct drm_connector
*connector
)
4430 bool has_audio
= false;
4433 edid
= to_intel_connector(connector
)->detect_edid
;
4435 has_audio
= drm_detect_monitor_audio(edid
);
4441 intel_dp_set_property(struct drm_connector
*connector
,
4442 struct drm_property
*property
,
4445 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4446 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4447 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4448 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4451 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4455 if (property
== dev_priv
->force_audio_property
) {
4459 if (i
== intel_dp
->force_audio
)
4462 intel_dp
->force_audio
= i
;
4464 if (i
== HDMI_AUDIO_AUTO
)
4465 has_audio
= intel_dp_detect_audio(connector
);
4467 has_audio
= (i
== HDMI_AUDIO_ON
);
4469 if (has_audio
== intel_dp
->has_audio
)
4472 intel_dp
->has_audio
= has_audio
;
4476 if (property
== dev_priv
->broadcast_rgb_property
) {
4477 bool old_auto
= intel_dp
->color_range_auto
;
4478 bool old_range
= intel_dp
->limited_color_range
;
4481 case INTEL_BROADCAST_RGB_AUTO
:
4482 intel_dp
->color_range_auto
= true;
4484 case INTEL_BROADCAST_RGB_FULL
:
4485 intel_dp
->color_range_auto
= false;
4486 intel_dp
->limited_color_range
= false;
4488 case INTEL_BROADCAST_RGB_LIMITED
:
4489 intel_dp
->color_range_auto
= false;
4490 intel_dp
->limited_color_range
= true;
4496 if (old_auto
== intel_dp
->color_range_auto
&&
4497 old_range
== intel_dp
->limited_color_range
)
4503 if (is_edp(intel_dp
) &&
4504 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4505 if (val
== DRM_MODE_SCALE_NONE
) {
4506 DRM_DEBUG_KMS("no scaling not supported\n");
4509 if (HAS_GMCH_DISPLAY(dev_priv
) &&
4510 val
== DRM_MODE_SCALE_CENTER
) {
4511 DRM_DEBUG_KMS("centering not supported\n");
4515 if (intel_connector
->panel
.fitting_mode
== val
) {
4516 /* the eDP scaling property is not changed */
4519 intel_connector
->panel
.fitting_mode
= val
;
4527 if (intel_encoder
->base
.crtc
)
4528 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4534 intel_dp_connector_destroy(struct drm_connector
*connector
)
4536 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4538 kfree(intel_connector
->detect_edid
);
4540 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4541 kfree(intel_connector
->edid
);
4543 /* Can't call is_edp() since the encoder may have been destroyed
4545 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4546 intel_panel_fini(&intel_connector
->panel
);
4548 drm_connector_cleanup(connector
);
4552 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4554 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4555 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4557 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4558 if (is_edp(intel_dp
)) {
4559 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4561 * vdd might still be enabled do to the delayed vdd off.
4562 * Make sure vdd is actually turned off here.
4565 edp_panel_vdd_off_sync(intel_dp
);
4566 pps_unlock(intel_dp
);
4568 if (intel_dp
->edp_notifier
.notifier_call
) {
4569 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4570 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4573 drm_encoder_cleanup(encoder
);
4574 kfree(intel_dig_port
);
4577 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4579 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4581 if (!is_edp(intel_dp
))
4585 * vdd might still be enabled do to the delayed vdd off.
4586 * Make sure vdd is actually turned off here.
4588 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4590 edp_panel_vdd_off_sync(intel_dp
);
4591 pps_unlock(intel_dp
);
4594 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4596 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4597 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4599 enum intel_display_power_domain power_domain
;
4601 lockdep_assert_held(&dev_priv
->pps_mutex
);
4603 if (!edp_have_panel_vdd(intel_dp
))
4607 * The VDD bit needs a power domain reference, so if the bit is
4608 * already enabled when we boot or resume, grab this reference and
4609 * schedule a vdd off, so we don't hold on to the reference
4612 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4613 power_domain
= intel_display_port_aux_power_domain(&intel_dig_port
->base
);
4614 intel_display_power_get(dev_priv
, power_domain
);
4616 edp_panel_vdd_schedule_off(intel_dp
);
4619 void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4621 struct drm_i915_private
*dev_priv
= to_i915(encoder
->dev
);
4622 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
4624 if (!HAS_DDI(dev_priv
))
4625 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
4627 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4633 * Read out the current power sequencer assignment,
4634 * in case the BIOS did something with it.
4636 if (IS_VALLEYVIEW(encoder
->dev
) || IS_CHERRYVIEW(encoder
->dev
))
4637 vlv_initial_power_sequencer_setup(intel_dp
);
4639 intel_edp_panel_vdd_sanitize(intel_dp
);
4641 pps_unlock(intel_dp
);
4644 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4645 .dpms
= drm_atomic_helper_connector_dpms
,
4646 .detect
= intel_dp_detect
,
4647 .force
= intel_dp_force
,
4648 .fill_modes
= drm_helper_probe_single_connector_modes
,
4649 .set_property
= intel_dp_set_property
,
4650 .atomic_get_property
= intel_connector_atomic_get_property
,
4651 .destroy
= intel_dp_connector_destroy
,
4652 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4653 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4656 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4657 .get_modes
= intel_dp_get_modes
,
4658 .mode_valid
= intel_dp_mode_valid
,
4661 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4662 .reset
= intel_dp_encoder_reset
,
4663 .destroy
= intel_dp_encoder_destroy
,
4667 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4669 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4670 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4671 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4673 enum intel_display_power_domain power_domain
;
4674 enum irqreturn ret
= IRQ_NONE
;
4676 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
&&
4677 intel_dig_port
->base
.type
!= INTEL_OUTPUT_HDMI
)
4678 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4680 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4682 * vdd off can generate a long pulse on eDP which
4683 * would require vdd on to handle it, and thus we
4684 * would end up in an endless cycle of
4685 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4687 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4688 port_name(intel_dig_port
->port
));
4692 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4693 port_name(intel_dig_port
->port
),
4694 long_hpd
? "long" : "short");
4696 power_domain
= intel_display_port_aux_power_domain(intel_encoder
);
4697 intel_display_power_get(dev_priv
, power_domain
);
4700 intel_dp_long_pulse(intel_dp
->attached_connector
);
4701 if (intel_dp
->is_mst
)
4706 if (intel_dp
->is_mst
) {
4707 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
) {
4709 * If we were in MST mode, and device is not
4710 * there, get out of MST mode
4712 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4713 intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4714 intel_dp
->is_mst
= false;
4715 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
,
4721 if (!intel_dp
->is_mst
) {
4722 if (!intel_dp_short_pulse(intel_dp
)) {
4723 intel_dp_long_pulse(intel_dp
->attached_connector
);
4732 intel_display_power_put(dev_priv
, power_domain
);
4737 /* check the VBT to see whether the eDP is on another port */
4738 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 * eDP not supported on g4x. so bail out early just
4744 * for a bit extra safety in case the VBT is bonkers.
4746 if (INTEL_INFO(dev
)->gen
< 5)
4752 return intel_bios_is_port_edp(dev_priv
, port
);
4756 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4758 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4760 intel_attach_force_audio_property(connector
);
4761 intel_attach_broadcast_rgb_property(connector
);
4762 intel_dp
->color_range_auto
= true;
4764 if (is_edp(intel_dp
)) {
4765 drm_mode_create_scaling_mode_property(connector
->dev
);
4766 drm_object_attach_property(
4768 connector
->dev
->mode_config
.scaling_mode_property
,
4769 DRM_MODE_SCALE_ASPECT
);
4770 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4774 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4776 intel_dp
->panel_power_off_time
= ktime_get_boottime();
4777 intel_dp
->last_power_on
= jiffies
;
4778 intel_dp
->last_backlight_off
= jiffies
;
4782 intel_pps_readout_hw_state(struct drm_i915_private
*dev_priv
,
4783 struct intel_dp
*intel_dp
, struct edp_power_seq
*seq
)
4785 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
4786 struct pps_registers regs
;
4788 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4790 /* Workaround: Need to write PP_CONTROL with the unlock key as
4791 * the very first thing. */
4792 pp_ctl
= ironlake_get_pp_control(intel_dp
);
4794 pp_on
= I915_READ(regs
.pp_on
);
4795 pp_off
= I915_READ(regs
.pp_off
);
4796 if (!IS_BROXTON(dev_priv
)) {
4797 I915_WRITE(regs
.pp_ctrl
, pp_ctl
);
4798 pp_div
= I915_READ(regs
.pp_div
);
4801 /* Pull timing values out of registers */
4802 seq
->t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4803 PANEL_POWER_UP_DELAY_SHIFT
;
4805 seq
->t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4806 PANEL_LIGHT_ON_DELAY_SHIFT
;
4808 seq
->t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4809 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4811 seq
->t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4812 PANEL_POWER_DOWN_DELAY_SHIFT
;
4814 if (IS_BROXTON(dev_priv
)) {
4815 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
4816 BXT_POWER_CYCLE_DELAY_SHIFT
;
4818 seq
->t11_t12
= (tmp
- 1) * 1000;
4822 seq
->t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4823 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4828 intel_pps_dump_state(const char *state_name
, const struct edp_power_seq
*seq
)
4830 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4832 seq
->t1_t3
, seq
->t8
, seq
->t9
, seq
->t10
, seq
->t11_t12
);
4836 intel_pps_verify_state(struct drm_i915_private
*dev_priv
,
4837 struct intel_dp
*intel_dp
)
4839 struct edp_power_seq hw
;
4840 struct edp_power_seq
*sw
= &intel_dp
->pps_delays
;
4842 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &hw
);
4844 if (hw
.t1_t3
!= sw
->t1_t3
|| hw
.t8
!= sw
->t8
|| hw
.t9
!= sw
->t9
||
4845 hw
.t10
!= sw
->t10
|| hw
.t11_t12
!= sw
->t11_t12
) {
4846 DRM_ERROR("PPS state mismatch\n");
4847 intel_pps_dump_state("sw", sw
);
4848 intel_pps_dump_state("hw", &hw
);
4853 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4854 struct intel_dp
*intel_dp
)
4856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4857 struct edp_power_seq cur
, vbt
, spec
,
4858 *final
= &intel_dp
->pps_delays
;
4860 lockdep_assert_held(&dev_priv
->pps_mutex
);
4862 /* already initialized? */
4863 if (final
->t11_t12
!= 0)
4866 intel_pps_readout_hw_state(dev_priv
, intel_dp
, &cur
);
4868 intel_pps_dump_state("cur", &cur
);
4870 vbt
= dev_priv
->vbt
.edp
.pps
;
4872 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4873 * our hw here, which are all in 100usec. */
4874 spec
.t1_t3
= 210 * 10;
4875 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4876 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4877 spec
.t10
= 500 * 10;
4878 /* This one is special and actually in units of 100ms, but zero
4879 * based in the hw (so we need to add 100 ms). But the sw vbt
4880 * table multiplies it with 1000 to make it in units of 100usec,
4882 spec
.t11_t12
= (510 + 100) * 10;
4884 intel_pps_dump_state("vbt", &vbt
);
4886 /* Use the max of the register settings and vbt. If both are
4887 * unset, fall back to the spec limits. */
4888 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
4890 max(cur.field, vbt.field))
4891 assign_final(t1_t3
);
4895 assign_final(t11_t12
);
4898 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
4899 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4900 intel_dp
->backlight_on_delay
= get_delay(t8
);
4901 intel_dp
->backlight_off_delay
= get_delay(t9
);
4902 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4903 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4906 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4907 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4908 intel_dp
->panel_power_cycle_delay
);
4910 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4911 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4914 * We override the HW backlight delays to 1 because we do manual waits
4915 * on them. For T8, even BSpec recommends doing it. For T9, if we
4916 * don't do this, we'll end up waiting for the backlight off delay
4917 * twice: once when we do the manual sleep, and once when we disable
4918 * the panel and wait for the PP_STATUS bit to become zero.
4925 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4926 struct intel_dp
*intel_dp
)
4928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4929 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4930 int div
= dev_priv
->rawclk_freq
/ 1000;
4931 struct pps_registers regs
;
4932 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4933 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
4935 lockdep_assert_held(&dev_priv
->pps_mutex
);
4937 intel_pps_get_registers(dev_priv
, intel_dp
, ®s
);
4939 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4940 (seq
->t8
<< PANEL_LIGHT_ON_DELAY_SHIFT
);
4941 pp_off
= (seq
->t9
<< PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4942 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4943 /* Compute the divisor for the pp clock, simply match the Bspec
4945 if (IS_BROXTON(dev
)) {
4946 pp_div
= I915_READ(regs
.pp_ctrl
);
4947 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
4948 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
4949 << BXT_POWER_CYCLE_DELAY_SHIFT
);
4951 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4952 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4953 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4956 /* Haswell doesn't have any port selection bits for the panel
4957 * power sequencer any more. */
4958 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
4959 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4960 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4962 port_sel
= PANEL_PORT_SELECT_DPA
;
4964 port_sel
= PANEL_PORT_SELECT_DPD
;
4969 I915_WRITE(regs
.pp_on
, pp_on
);
4970 I915_WRITE(regs
.pp_off
, pp_off
);
4971 if (IS_BROXTON(dev
))
4972 I915_WRITE(regs
.pp_ctrl
, pp_div
);
4974 I915_WRITE(regs
.pp_div
, pp_div
);
4976 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4977 I915_READ(regs
.pp_on
),
4978 I915_READ(regs
.pp_off
),
4980 (I915_READ(regs
.pp_ctrl
) & BXT_POWER_CYCLE_DELAY_MASK
) :
4981 I915_READ(regs
.pp_div
));
4985 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4987 * @refresh_rate: RR to be programmed
4989 * This function gets called when refresh rate (RR) has to be changed from
4990 * one frequency to another. Switches can be between high and low RR
4991 * supported by the panel or to any other RR based on media playback (in
4992 * this case, RR value needs to be passed from user space).
4994 * The caller of this function needs to take a lock on dev_priv->drrs.
4996 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 struct intel_encoder
*encoder
;
5000 struct intel_digital_port
*dig_port
= NULL
;
5001 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5002 struct intel_crtc_state
*config
= NULL
;
5003 struct intel_crtc
*intel_crtc
= NULL
;
5004 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5006 if (refresh_rate
<= 0) {
5007 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5011 if (intel_dp
== NULL
) {
5012 DRM_DEBUG_KMS("DRRS not supported.\n");
5017 * FIXME: This needs proper synchronization with psr state for some
5018 * platforms that cannot have PSR and DRRS enabled at the same time.
5021 dig_port
= dp_to_dig_port(intel_dp
);
5022 encoder
= &dig_port
->base
;
5023 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5026 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5030 config
= intel_crtc
->config
;
5032 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5033 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5037 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5039 index
= DRRS_LOW_RR
;
5041 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5043 "DRRS requested for previously set RR...ignoring\n");
5047 if (!intel_crtc
->active
) {
5048 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5052 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5055 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5058 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5062 DRM_ERROR("Unsupported refreshrate type\n");
5064 } else if (INTEL_INFO(dev
)->gen
> 6) {
5065 i915_reg_t reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5068 val
= I915_READ(reg
);
5069 if (index
> DRRS_HIGH_RR
) {
5070 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5071 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5073 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5075 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
5076 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5078 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5080 I915_WRITE(reg
, val
);
5083 dev_priv
->drrs
.refresh_rate_type
= index
;
5085 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5089 * intel_edp_drrs_enable - init drrs struct if supported
5090 * @intel_dp: DP struct
5092 * Initializes frontbuffer_bits and drrs.dp
5094 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5096 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5098 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5099 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5102 if (!intel_crtc
->config
->has_drrs
) {
5103 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5107 mutex_lock(&dev_priv
->drrs
.mutex
);
5108 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5109 DRM_ERROR("DRRS already enabled\n");
5113 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5115 dev_priv
->drrs
.dp
= intel_dp
;
5118 mutex_unlock(&dev_priv
->drrs
.mutex
);
5122 * intel_edp_drrs_disable - Disable DRRS
5123 * @intel_dp: DP struct
5126 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5128 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5130 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5131 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5134 if (!intel_crtc
->config
->has_drrs
)
5137 mutex_lock(&dev_priv
->drrs
.mutex
);
5138 if (!dev_priv
->drrs
.dp
) {
5139 mutex_unlock(&dev_priv
->drrs
.mutex
);
5143 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5144 intel_dp_set_drrs_state(dev_priv
->dev
,
5145 intel_dp
->attached_connector
->panel
.
5146 fixed_mode
->vrefresh
);
5148 dev_priv
->drrs
.dp
= NULL
;
5149 mutex_unlock(&dev_priv
->drrs
.mutex
);
5151 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5154 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5156 struct drm_i915_private
*dev_priv
=
5157 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5158 struct intel_dp
*intel_dp
;
5160 mutex_lock(&dev_priv
->drrs
.mutex
);
5162 intel_dp
= dev_priv
->drrs
.dp
;
5168 * The delayed work can race with an invalidate hence we need to
5172 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5175 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5176 intel_dp_set_drrs_state(dev_priv
->dev
,
5177 intel_dp
->attached_connector
->panel
.
5178 downclock_mode
->vrefresh
);
5181 mutex_unlock(&dev_priv
->drrs
.mutex
);
5185 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5187 * @frontbuffer_bits: frontbuffer plane tracking bits
5189 * This function gets called everytime rendering on the given planes start.
5190 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5192 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5194 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5195 unsigned frontbuffer_bits
)
5197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5198 struct drm_crtc
*crtc
;
5201 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5204 cancel_delayed_work(&dev_priv
->drrs
.work
);
5206 mutex_lock(&dev_priv
->drrs
.mutex
);
5207 if (!dev_priv
->drrs
.dp
) {
5208 mutex_unlock(&dev_priv
->drrs
.mutex
);
5212 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5213 pipe
= to_intel_crtc(crtc
)->pipe
;
5215 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5216 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5218 /* invalidate means busy screen hence upclock */
5219 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5220 intel_dp_set_drrs_state(dev_priv
->dev
,
5221 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5222 fixed_mode
->vrefresh
);
5224 mutex_unlock(&dev_priv
->drrs
.mutex
);
5228 * intel_edp_drrs_flush - Restart Idleness DRRS
5230 * @frontbuffer_bits: frontbuffer plane tracking bits
5232 * This function gets called every time rendering on the given planes has
5233 * completed or flip on a crtc is completed. So DRRS should be upclocked
5234 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5235 * if no other planes are dirty.
5237 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5239 void intel_edp_drrs_flush(struct drm_device
*dev
,
5240 unsigned frontbuffer_bits
)
5242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5243 struct drm_crtc
*crtc
;
5246 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5249 cancel_delayed_work(&dev_priv
->drrs
.work
);
5251 mutex_lock(&dev_priv
->drrs
.mutex
);
5252 if (!dev_priv
->drrs
.dp
) {
5253 mutex_unlock(&dev_priv
->drrs
.mutex
);
5257 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5258 pipe
= to_intel_crtc(crtc
)->pipe
;
5260 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5261 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5263 /* flush means busy screen hence upclock */
5264 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5265 intel_dp_set_drrs_state(dev_priv
->dev
,
5266 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5267 fixed_mode
->vrefresh
);
5270 * flush also means no more activity hence schedule downclock, if all
5271 * other fbs are quiescent too
5273 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5274 schedule_delayed_work(&dev_priv
->drrs
.work
,
5275 msecs_to_jiffies(1000));
5276 mutex_unlock(&dev_priv
->drrs
.mutex
);
5280 * DOC: Display Refresh Rate Switching (DRRS)
5282 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5283 * which enables swtching between low and high refresh rates,
5284 * dynamically, based on the usage scenario. This feature is applicable
5285 * for internal panels.
5287 * Indication that the panel supports DRRS is given by the panel EDID, which
5288 * would list multiple refresh rates for one resolution.
5290 * DRRS is of 2 types - static and seamless.
5291 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5292 * (may appear as a blink on screen) and is used in dock-undock scenario.
5293 * Seamless DRRS involves changing RR without any visual effect to the user
5294 * and can be used during normal system usage. This is done by programming
5295 * certain registers.
5297 * Support for static/seamless DRRS may be indicated in the VBT based on
5298 * inputs from the panel spec.
5300 * DRRS saves power by switching to low RR based on usage scenarios.
5302 * The implementation is based on frontbuffer tracking implementation. When
5303 * there is a disturbance on the screen triggered by user activity or a periodic
5304 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5305 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5308 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5309 * and intel_edp_drrs_flush() are called.
5311 * DRRS can be further extended to support other internal panels and also
5312 * the scenario of video playback wherein RR is set based on the rate
5313 * requested by userspace.
5317 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5318 * @intel_connector: eDP connector
5319 * @fixed_mode: preferred mode of panel
5321 * This function is called only once at driver load to initialize basic
5325 * Downclock mode if panel supports it, else return NULL.
5326 * DRRS support is determined by the presence of downclock mode (apart
5327 * from VBT setting).
5329 static struct drm_display_mode
*
5330 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5331 struct drm_display_mode
*fixed_mode
)
5333 struct drm_connector
*connector
= &intel_connector
->base
;
5334 struct drm_device
*dev
= connector
->dev
;
5335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5336 struct drm_display_mode
*downclock_mode
= NULL
;
5338 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5339 mutex_init(&dev_priv
->drrs
.mutex
);
5341 if (INTEL_INFO(dev
)->gen
<= 6) {
5342 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5346 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5347 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5351 downclock_mode
= intel_find_panel_downclock
5352 (dev
, fixed_mode
, connector
);
5354 if (!downclock_mode
) {
5355 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5359 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5361 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5362 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5363 return downclock_mode
;
5366 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5367 struct intel_connector
*intel_connector
)
5369 struct drm_connector
*connector
= &intel_connector
->base
;
5370 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5371 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5372 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5374 struct drm_display_mode
*fixed_mode
= NULL
;
5375 struct drm_display_mode
*downclock_mode
= NULL
;
5377 struct drm_display_mode
*scan
;
5379 enum pipe pipe
= INVALID_PIPE
;
5381 if (!is_edp(intel_dp
))
5385 * On IBX/CPT we may get here with LVDS already registered. Since the
5386 * driver uses the only internal power sequencer available for both
5387 * eDP and LVDS bail out early in this case to prevent interfering
5388 * with an already powered-on LVDS power sequencer.
5390 if (intel_get_lvds_encoder(dev
)) {
5391 WARN_ON(!(HAS_PCH_IBX(dev_priv
) || HAS_PCH_CPT(dev_priv
)));
5392 DRM_INFO("LVDS was detected, not registering eDP\n");
5399 intel_dp_init_panel_power_timestamps(intel_dp
);
5401 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5402 vlv_initial_power_sequencer_setup(intel_dp
);
5404 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5405 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5408 intel_edp_panel_vdd_sanitize(intel_dp
);
5410 pps_unlock(intel_dp
);
5412 /* Cache DPCD and EDID for edp. */
5413 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5416 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5417 dev_priv
->no_aux_handshake
=
5418 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5419 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5421 /* if this fails, presume the device is a ghost */
5422 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5426 mutex_lock(&dev
->mode_config
.mutex
);
5427 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5429 if (drm_add_edid_modes(connector
, edid
)) {
5430 drm_mode_connector_update_edid_property(connector
,
5432 drm_edid_to_eld(connector
, edid
);
5435 edid
= ERR_PTR(-EINVAL
);
5438 edid
= ERR_PTR(-ENOENT
);
5440 intel_connector
->edid
= edid
;
5442 /* prefer fixed mode from EDID if available */
5443 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5444 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5445 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5446 downclock_mode
= intel_dp_drrs_init(
5447 intel_connector
, fixed_mode
);
5452 /* fallback to VBT if available for eDP */
5453 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5454 fixed_mode
= drm_mode_duplicate(dev
,
5455 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5457 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5458 connector
->display_info
.width_mm
= fixed_mode
->width_mm
;
5459 connector
->display_info
.height_mm
= fixed_mode
->height_mm
;
5462 mutex_unlock(&dev
->mode_config
.mutex
);
5464 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
5465 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5466 register_reboot_notifier(&intel_dp
->edp_notifier
);
5469 * Figure out the current pipe for the initial backlight setup.
5470 * If the current pipe isn't valid, try the PPS pipe, and if that
5471 * fails just assume pipe A.
5473 if (IS_CHERRYVIEW(dev
))
5474 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5476 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5478 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5479 pipe
= intel_dp
->pps_pipe
;
5481 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5484 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5488 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5489 intel_connector
->panel
.backlight
.power
= intel_edp_backlight_power
;
5490 intel_panel_setup_backlight(connector
, pipe
);
5495 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5497 * vdd might still be enabled do to the delayed vdd off.
5498 * Make sure vdd is actually turned off here.
5501 edp_panel_vdd_off_sync(intel_dp
);
5502 pps_unlock(intel_dp
);
5508 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5509 struct intel_connector
*intel_connector
)
5511 struct drm_connector
*connector
= &intel_connector
->base
;
5512 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5513 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5514 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 enum port port
= intel_dig_port
->port
;
5519 if (WARN(intel_dig_port
->max_lanes
< 1,
5520 "Not enough lanes (%d) for DP on port %c\n",
5521 intel_dig_port
->max_lanes
, port_name(port
)))
5524 intel_dp
->pps_pipe
= INVALID_PIPE
;
5526 /* intel_dp vfuncs */
5527 if (INTEL_INFO(dev
)->gen
>= 9)
5528 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5529 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5530 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5531 else if (HAS_PCH_SPLIT(dev
))
5532 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5534 intel_dp
->get_aux_clock_divider
= g4x_get_aux_clock_divider
;
5536 if (INTEL_INFO(dev
)->gen
>= 9)
5537 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5539 intel_dp
->get_aux_send_ctl
= g4x_get_aux_send_ctl
;
5542 intel_dp
->prepare_link_retrain
= intel_ddi_prepare_link_retrain
;
5544 /* Preserve the current hw state. */
5545 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5546 intel_dp
->attached_connector
= intel_connector
;
5548 if (intel_dp_is_edp(dev
, port
))
5549 type
= DRM_MODE_CONNECTOR_eDP
;
5551 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5554 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5555 * for DP the encoder type can be set by the caller to
5556 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5558 if (type
== DRM_MODE_CONNECTOR_eDP
)
5559 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5561 /* eDP only on port B and/or C on vlv/chv */
5562 if (WARN_ON((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
5563 is_edp(intel_dp
) && port
!= PORT_B
&& port
!= PORT_C
))
5566 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5567 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5570 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5571 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5573 connector
->interlace_allowed
= true;
5574 connector
->doublescan_allowed
= 0;
5576 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5577 edp_panel_vdd_work
);
5579 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5580 drm_connector_register(connector
);
5583 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5585 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5586 intel_connector
->unregister
= intel_dp_connector_unregister
;
5588 /* Set up the hotplug pin. */
5591 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5594 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5595 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
5596 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5599 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5602 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5605 intel_encoder
->hpd_pin
= HPD_PORT_E
;
5611 ret
= intel_dp_aux_init(intel_dp
, intel_connector
);
5615 /* init MST on ports that can support it */
5616 if (HAS_DP_MST(dev
) &&
5617 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5618 intel_dp_mst_encoder_init(intel_dig_port
,
5619 intel_connector
->base
.base
.id
);
5621 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5622 intel_dp_aux_fini(intel_dp
);
5623 intel_dp_mst_encoder_cleanup(intel_dig_port
);
5627 intel_dp_add_properties(intel_dp
, connector
);
5629 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5630 * 0xd. Failure to do so will result in spurious interrupts being
5631 * generated on the port when a cable is not attached.
5633 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5634 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5635 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5638 i915_debugfs_connector_add(connector
);
5643 drm_connector_unregister(connector
);
5644 drm_connector_cleanup(connector
);
5649 bool intel_dp_init(struct drm_device
*dev
,
5650 i915_reg_t output_reg
,
5653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5654 struct intel_digital_port
*intel_dig_port
;
5655 struct intel_encoder
*intel_encoder
;
5656 struct drm_encoder
*encoder
;
5657 struct intel_connector
*intel_connector
;
5659 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5660 if (!intel_dig_port
)
5663 intel_connector
= intel_connector_alloc();
5664 if (!intel_connector
)
5665 goto err_connector_alloc
;
5667 intel_encoder
= &intel_dig_port
->base
;
5668 encoder
= &intel_encoder
->base
;
5670 if (drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5671 DRM_MODE_ENCODER_TMDS
, "DP %c", port_name(port
)))
5672 goto err_encoder_init
;
5674 intel_encoder
->compute_config
= intel_dp_compute_config
;
5675 intel_encoder
->disable
= intel_disable_dp
;
5676 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5677 intel_encoder
->get_config
= intel_dp_get_config
;
5678 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5679 if (IS_CHERRYVIEW(dev
)) {
5680 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5681 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5682 intel_encoder
->enable
= vlv_enable_dp
;
5683 intel_encoder
->post_disable
= chv_post_disable_dp
;
5684 intel_encoder
->post_pll_disable
= chv_dp_post_pll_disable
;
5685 } else if (IS_VALLEYVIEW(dev
)) {
5686 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5687 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5688 intel_encoder
->enable
= vlv_enable_dp
;
5689 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5691 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5692 intel_encoder
->enable
= g4x_enable_dp
;
5693 if (INTEL_INFO(dev
)->gen
>= 5)
5694 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5697 intel_dig_port
->port
= port
;
5698 intel_dig_port
->dp
.output_reg
= output_reg
;
5699 intel_dig_port
->max_lanes
= 4;
5701 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5702 if (IS_CHERRYVIEW(dev
)) {
5704 intel_encoder
->crtc_mask
= 1 << 2;
5706 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5708 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5710 intel_encoder
->cloneable
= 0;
5712 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5713 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5715 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
))
5716 goto err_init_connector
;
5721 drm_encoder_cleanup(encoder
);
5723 kfree(intel_connector
);
5724 err_connector_alloc
:
5725 kfree(intel_dig_port
);
5729 void intel_dp_mst_suspend(struct drm_device
*dev
)
5731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5735 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5736 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5737 if (!intel_dig_port
)
5740 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5741 if (!intel_dig_port
->dp
.can_mst
)
5743 if (intel_dig_port
->dp
.is_mst
)
5744 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5749 void intel_dp_mst_resume(struct drm_device
*dev
)
5751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5754 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5755 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5756 if (!intel_dig_port
)
5758 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5761 if (!intel_dig_port
->dp
.can_mst
)
5764 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5766 intel_dp_check_mst_status(&intel_dig_port
->dp
);