2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
59 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
62 static const struct dp_link_dpll pch_dpll
[] = {
64 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
66 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
69 static const struct dp_link_dpll vlv_dpll
[] = {
71 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
73 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll
[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
88 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
89 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
90 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
91 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
94 static const int bxt_rates
[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates
[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
101 static const int default_rates
[] = { 162000, 270000, 540000 };
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
110 static bool is_edp(struct intel_dp
*intel_dp
)
112 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
114 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
117 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
119 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
121 return intel_dig_port
->base
.base
.dev
;
124 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
126 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
129 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
130 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
131 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
132 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
133 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
137 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
139 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
141 switch (max_link_bw
) {
142 case DP_LINK_BW_1_62
:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw
= DP_LINK_BW_1_62
;
155 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
157 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
158 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
159 u8 source_max
, sink_max
;
162 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
163 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
166 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
168 return min(source_max
, sink_max
);
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 * 270000 * 1 * 8 / 10 == 216000
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
189 intel_dp_link_required(int pixel_clock
, int bpp
)
191 return (pixel_clock
* bpp
+ 9) / 10;
195 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
197 return (max_link_clock
* max_lanes
* 8) / 10;
200 static enum drm_mode_status
201 intel_dp_mode_valid(struct drm_connector
*connector
,
202 struct drm_display_mode
*mode
)
204 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
205 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
206 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
207 int target_clock
= mode
->clock
;
208 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
210 if (is_edp(intel_dp
) && fixed_mode
) {
211 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
214 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
217 target_clock
= fixed_mode
->clock
;
220 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
221 max_lanes
= intel_dp_max_lane_count(intel_dp
);
223 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
224 mode_rate
= intel_dp_link_required(target_clock
, 18);
226 if (mode_rate
> max_rate
)
227 return MODE_CLOCK_HIGH
;
229 if (mode
->clock
< 10000)
230 return MODE_CLOCK_LOW
;
232 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
233 return MODE_H_ILLEGAL
;
238 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
245 for (i
= 0; i
< src_bytes
; i
++)
246 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
250 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
255 for (i
= 0; i
< dst_bytes
; i
++)
256 dst
[i
] = src
>> ((3-i
) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device
*dev
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev
))
270 clkcfg
= I915_READ(CLKCFG
);
271 switch (clkcfg
& CLKCFG_FSB_MASK
) {
280 case CLKCFG_FSB_1067
:
282 case CLKCFG_FSB_1333
:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600
:
286 case CLKCFG_FSB_1600_ALT
:
294 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
295 struct intel_dp
*intel_dp
);
297 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
298 struct intel_dp
*intel_dp
);
300 static void pps_lock(struct intel_dp
*intel_dp
)
302 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
303 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
304 struct drm_device
*dev
= encoder
->base
.dev
;
305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
306 enum intel_display_power_domain power_domain
;
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
312 power_domain
= intel_display_port_power_domain(encoder
);
313 intel_display_power_get(dev_priv
, power_domain
);
315 mutex_lock(&dev_priv
->pps_mutex
);
318 static void pps_unlock(struct intel_dp
*intel_dp
)
320 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
321 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 enum intel_display_power_domain power_domain
;
326 mutex_unlock(&dev_priv
->pps_mutex
);
328 power_domain
= intel_display_port_power_domain(encoder
);
329 intel_display_power_put(dev_priv
, power_domain
);
333 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
336 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 enum pipe pipe
= intel_dp
->pps_pipe
;
342 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe
), port_name(intel_dig_port
->port
));
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
353 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
354 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
355 DP
|= DP_PORT_WIDTH(1);
356 DP
|= DP_LINK_TRAIN_PAT_1
;
358 if (IS_CHERRYVIEW(dev
))
359 DP
|= DP_PIPE_SELECT_CHV(pipe
);
360 else if (pipe
== PIPE_B
)
361 DP
|= DP_PIPEB_SELECT
;
363 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
370 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
371 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
379 I915_WRITE(intel_dp
->output_reg
, DP
);
380 POSTING_READ(intel_dp
->output_reg
);
382 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
383 POSTING_READ(intel_dp
->output_reg
);
385 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
386 POSTING_READ(intel_dp
->output_reg
);
389 vlv_force_pll_off(dev
, pipe
);
393 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
395 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
396 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 struct intel_encoder
*encoder
;
399 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
402 lockdep_assert_held(&dev_priv
->pps_mutex
);
404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp
));
407 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
408 return intel_dp
->pps_pipe
;
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
414 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
416 struct intel_dp
*tmp
;
418 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
421 tmp
= enc_to_intel_dp(&encoder
->base
);
423 if (tmp
->pps_pipe
!= INVALID_PIPE
)
424 pipes
&= ~(1 << tmp
->pps_pipe
);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes
== 0))
434 pipe
= ffs(pipes
) - 1;
436 vlv_steal_power_sequencer(dev
, pipe
);
437 intel_dp
->pps_pipe
= pipe
;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp
->pps_pipe
),
441 port_name(intel_dig_port
->port
));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
445 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp
);
453 return intel_dp
->pps_pipe
;
456 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
459 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
465 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
471 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
478 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
480 vlv_pipe_check pipe_check
)
484 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
485 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
486 PANEL_PORT_SELECT_MASK
;
488 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
491 if (!pipe_check(dev_priv
, pipe
))
501 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
503 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
504 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 enum port port
= intel_dig_port
->port
;
508 lockdep_assert_held(&dev_priv
->pps_mutex
);
510 /* try to find a pipe with this port selected */
511 /* first pick one where the panel is on */
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
516 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
517 vlv_pipe_has_vdd_on
);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
520 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
533 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
534 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
537 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
539 struct drm_device
*dev
= dev_priv
->dev
;
540 struct intel_encoder
*encoder
;
542 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
555 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
556 struct intel_dp
*intel_dp
;
558 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
561 intel_dp
= enc_to_intel_dp(&encoder
->base
);
562 intel_dp
->pps_pipe
= INVALID_PIPE
;
566 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
568 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev
))
573 return PCH_PP_CONTROL
;
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
578 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
580 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev
))
585 return PCH_PP_STATUS
;
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
590 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
595 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
597 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 u32 pp_ctrl_reg
, pp_div_reg
;
602 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
607 if (IS_VALLEYVIEW(dev
)) {
608 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
610 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
611 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
612 pp_div
= I915_READ(pp_div_reg
);
613 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
617 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
618 msleep(intel_dp
->panel_power_cycle_delay
);
621 pps_unlock(intel_dp
);
626 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
628 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
631 lockdep_assert_held(&dev_priv
->pps_mutex
);
633 if (IS_VALLEYVIEW(dev
) &&
634 intel_dp
->pps_pipe
== INVALID_PIPE
)
637 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
640 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
642 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 lockdep_assert_held(&dev_priv
->pps_mutex
);
647 if (IS_VALLEYVIEW(dev
) &&
648 intel_dp
->pps_pipe
== INVALID_PIPE
)
651 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
655 intel_dp_check_edp(struct intel_dp
*intel_dp
)
657 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
660 if (!is_edp(intel_dp
))
663 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
666 I915_READ(_pp_stat_reg(intel_dp
)),
667 I915_READ(_pp_ctrl_reg(intel_dp
)));
672 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
674 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
675 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
677 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
681 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
683 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
684 msecs_to_jiffies_timeout(10));
686 done
= wait_for_atomic(C
, 10) == 0;
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
695 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
704 return index
? 0 : intel_hrawclk(dev
) / 2;
707 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
709 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
710 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
716 if (intel_dig_port
->port
== PORT_A
) {
717 return DIV_ROUND_UP(dev_priv
->cdclk_freq
, 2000);
720 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
724 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
726 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
727 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
730 if (intel_dig_port
->port
== PORT_A
) {
733 return DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 2000);
734 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
735 /* Workaround for non-ULT HSW */
742 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
746 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
748 return index
? 0 : 100;
751 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
758 return index
? 0 : 1;
761 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
764 uint32_t aux_clock_divider
)
766 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
767 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
768 uint32_t precharge
, timeout
;
775 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
776 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
778 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
780 return DP_AUX_CH_CTL_SEND_BUSY
|
782 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
783 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
785 DP_AUX_CH_CTL_RECEIVE_ERROR
|
786 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
787 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
788 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
791 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
796 return DP_AUX_CH_CTL_SEND_BUSY
|
798 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
800 DP_AUX_CH_CTL_TIME_OUT_1600us
|
801 DP_AUX_CH_CTL_RECEIVE_ERROR
|
802 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
807 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
808 const uint8_t *send
, int send_bytes
,
809 uint8_t *recv
, int recv_size
)
811 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
812 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
814 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
815 uint32_t ch_data
= ch_ctl
+ 4;
816 uint32_t aux_clock_divider
;
817 int i
, ret
, recv_bytes
;
820 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
831 vdd
= edp_panel_vdd_on(intel_dp
);
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
837 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
839 intel_dp_check_edp(intel_dp
);
841 intel_aux_display_runtime_get(dev_priv
);
843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
845 status
= I915_READ_NOTRACE(ch_ctl
);
846 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
852 static u32 last_status
= -1;
853 const u32 status
= I915_READ(ch_ctl
);
855 if (status
!= last_status
) {
856 WARN(1, "dp_aux_ch not started status 0x%08x\n",
858 last_status
= status
;
865 /* Only 5 data registers! */
866 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
871 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
872 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
877 /* Must try at least 3 times according to DP spec */
878 for (try = 0; try < 5; try++) {
879 /* Load the send data into the aux channel data registers */
880 for (i
= 0; i
< send_bytes
; i
+= 4)
881 I915_WRITE(ch_data
+ i
,
882 intel_dp_pack_aux(send
+ i
,
885 /* Send the command and wait for it to complete */
886 I915_WRITE(ch_ctl
, send_ctl
);
888 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
890 /* Clear done status and any errors */
894 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
895 DP_AUX_CH_CTL_RECEIVE_ERROR
);
897 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
900 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
901 * 400us delay required for errors and timeouts
902 * Timeout errors from the HW already meet this
903 * requirement so skip to next iteration
905 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
906 usleep_range(400, 500);
909 if (status
& DP_AUX_CH_CTL_DONE
)
914 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
915 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
921 /* Check for timeout or receive error.
922 * Timeouts occur when the sink is not connected
924 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
925 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
930 /* Timeouts occur when the device isn't connected, so they're
931 * "normal" -- don't fill the kernel log with these */
932 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
933 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
938 /* Unload any bytes sent back from the other side */
939 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
940 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
941 if (recv_bytes
> recv_size
)
942 recv_bytes
= recv_size
;
944 for (i
= 0; i
< recv_bytes
; i
+= 4)
945 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
946 recv
+ i
, recv_bytes
- i
);
950 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
951 intel_aux_display_runtime_put(dev_priv
);
954 edp_panel_vdd_off(intel_dp
, false);
956 pps_unlock(intel_dp
);
961 #define BARE_ADDRESS_SIZE 3
962 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
964 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
966 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
967 uint8_t txbuf
[20], rxbuf
[20];
968 size_t txsize
, rxsize
;
971 txbuf
[0] = (msg
->request
<< 4) |
972 ((msg
->address
>> 16) & 0xf);
973 txbuf
[1] = (msg
->address
>> 8) & 0xff;
974 txbuf
[2] = msg
->address
& 0xff;
975 txbuf
[3] = msg
->size
- 1;
977 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
978 case DP_AUX_NATIVE_WRITE
:
979 case DP_AUX_I2C_WRITE
:
980 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
981 rxsize
= 2; /* 0 or 1 data bytes */
983 if (WARN_ON(txsize
> 20))
986 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
988 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
990 msg
->reply
= rxbuf
[0] >> 4;
993 /* Number of bytes written in a short write. */
994 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
996 /* Return payload size. */
1002 case DP_AUX_NATIVE_READ
:
1003 case DP_AUX_I2C_READ
:
1004 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
1005 rxsize
= msg
->size
+ 1;
1007 if (WARN_ON(rxsize
> 20))
1010 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
1012 msg
->reply
= rxbuf
[0] >> 4;
1014 * Assume happy day, and copy the data. The caller is
1015 * expected to check msg->reply before touching it.
1017 * Return payload size.
1020 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1033 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1035 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1037 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1038 enum port port
= intel_dig_port
->port
;
1039 struct ddi_vbt_port_info
*info
= &dev_priv
->vbt
.ddi_port_info
[port
];
1040 const char *name
= NULL
;
1041 uint32_t porte_aux_ctl_reg
= DPA_AUX_CH_CTL
;
1044 /* On SKL we don't have Aux for port E so we rely on VBT to set
1045 * a proper alternate aux channel.
1047 if (IS_SKYLAKE(dev
) && port
== PORT_E
) {
1048 switch (info
->alternate_aux_channel
) {
1050 porte_aux_ctl_reg
= DPB_AUX_CH_CTL
;
1053 porte_aux_ctl_reg
= DPC_AUX_CH_CTL
;
1056 porte_aux_ctl_reg
= DPD_AUX_CH_CTL
;
1060 porte_aux_ctl_reg
= DPA_AUX_CH_CTL
;
1066 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1070 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1074 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1078 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1082 intel_dp
->aux_ch_ctl_reg
= porte_aux_ctl_reg
;
1090 * The AUX_CTL register is usually DP_CTL + 0x10.
1092 * On Haswell and Broadwell though:
1093 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1094 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1096 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1098 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
) && port
!= PORT_E
)
1099 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1101 intel_dp
->aux
.name
= name
;
1102 intel_dp
->aux
.dev
= dev
->dev
;
1103 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1105 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1106 connector
->base
.kdev
->kobj
.name
);
1108 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1110 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1115 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1116 &intel_dp
->aux
.ddc
.dev
.kobj
,
1117 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1119 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1120 drm_dp_aux_unregister(&intel_dp
->aux
);
1125 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1127 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1129 if (!intel_connector
->mst_port
)
1130 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1131 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1132 intel_connector_unregister(intel_connector
);
1136 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1140 memset(&pipe_config
->dpll_hw_state
, 0,
1141 sizeof(pipe_config
->dpll_hw_state
));
1143 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1144 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1145 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1147 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1148 switch (link_clock
/ 2) {
1150 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
1154 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350
,
1158 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700
,
1162 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620
,
1165 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1166 results in CDCLK change. Need to handle the change of CDCLK by
1167 disabling pipes and re-enabling them */
1169 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
1173 ctrl1
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160
,
1178 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1182 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1184 memset(&pipe_config
->dpll_hw_state
, 0,
1185 sizeof(pipe_config
->dpll_hw_state
));
1188 case DP_LINK_BW_1_62
:
1189 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1191 case DP_LINK_BW_2_7
:
1192 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1194 case DP_LINK_BW_5_4
:
1195 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1201 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1203 if (intel_dp
->num_sink_rates
) {
1204 *sink_rates
= intel_dp
->sink_rates
;
1205 return intel_dp
->num_sink_rates
;
1208 *sink_rates
= default_rates
;
1210 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1214 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1216 if (IS_BROXTON(dev
)) {
1217 *source_rates
= bxt_rates
;
1218 return ARRAY_SIZE(bxt_rates
);
1219 } else if (IS_SKYLAKE(dev
)) {
1220 *source_rates
= skl_rates
;
1221 return ARRAY_SIZE(skl_rates
);
1222 } else if (IS_CHERRYVIEW(dev
)) {
1223 *source_rates
= chv_rates
;
1224 return ARRAY_SIZE(chv_rates
);
1227 *source_rates
= default_rates
;
1229 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1230 /* WaDisableHBR2:skl */
1231 return (DP_LINK_BW_2_7
>> 3) + 1;
1232 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1233 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1234 return (DP_LINK_BW_5_4
>> 3) + 1;
1236 return (DP_LINK_BW_2_7
>> 3) + 1;
1240 intel_dp_set_clock(struct intel_encoder
*encoder
,
1241 struct intel_crtc_state
*pipe_config
, int link_bw
)
1243 struct drm_device
*dev
= encoder
->base
.dev
;
1244 const struct dp_link_dpll
*divisor
= NULL
;
1248 divisor
= gen4_dpll
;
1249 count
= ARRAY_SIZE(gen4_dpll
);
1250 } else if (HAS_PCH_SPLIT(dev
)) {
1252 count
= ARRAY_SIZE(pch_dpll
);
1253 } else if (IS_CHERRYVIEW(dev
)) {
1255 count
= ARRAY_SIZE(chv_dpll
);
1256 } else if (IS_VALLEYVIEW(dev
)) {
1258 count
= ARRAY_SIZE(vlv_dpll
);
1261 if (divisor
&& count
) {
1262 for (i
= 0; i
< count
; i
++) {
1263 if (link_bw
== divisor
[i
].link_bw
) {
1264 pipe_config
->dpll
= divisor
[i
].dpll
;
1265 pipe_config
->clock_set
= true;
1272 static int intersect_rates(const int *source_rates
, int source_len
,
1273 const int *sink_rates
, int sink_len
,
1276 int i
= 0, j
= 0, k
= 0;
1278 while (i
< source_len
&& j
< sink_len
) {
1279 if (source_rates
[i
] == sink_rates
[j
]) {
1280 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1282 common_rates
[k
] = source_rates
[i
];
1286 } else if (source_rates
[i
] < sink_rates
[j
]) {
1295 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1298 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1299 const int *source_rates
, *sink_rates
;
1300 int source_len
, sink_len
;
1302 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1303 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1305 return intersect_rates(source_rates
, source_len
,
1306 sink_rates
, sink_len
,
1310 static void snprintf_int_array(char *str
, size_t len
,
1311 const int *array
, int nelem
)
1317 for (i
= 0; i
< nelem
; i
++) {
1318 int r
= snprintf(str
, len
, "%s%d", i
? ", " : "", array
[i
]);
1326 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1328 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1329 const int *source_rates
, *sink_rates
;
1330 int source_len
, sink_len
, common_len
;
1331 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1332 char str
[128]; /* FIXME: too big for stack? */
1334 if ((drm_debug
& DRM_UT_KMS
) == 0)
1337 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1338 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1339 DRM_DEBUG_KMS("source rates: %s\n", str
);
1341 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1342 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1343 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1345 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1346 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1347 DRM_DEBUG_KMS("common rates: %s\n", str
);
1350 static int rate_to_index(int find
, const int *rates
)
1354 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1355 if (find
== rates
[i
])
1362 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1364 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1367 len
= intel_dp_common_rates(intel_dp
, rates
);
1368 if (WARN_ON(len
<= 0))
1371 return rates
[rate_to_index(0, rates
) - 1];
1374 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1376 return rate_to_index(rate
, intel_dp
->sink_rates
);
1380 intel_dp_compute_config(struct intel_encoder
*encoder
,
1381 struct intel_crtc_state
*pipe_config
)
1383 struct drm_device
*dev
= encoder
->base
.dev
;
1384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1385 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1386 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1387 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1388 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1389 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1390 int lane_count
, clock
;
1391 int min_lane_count
= 1;
1392 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1393 /* Conveniently, the link BW constants become indices with a shift...*/
1397 int link_avail
, link_clock
;
1398 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1401 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1403 /* No common link rates between source and sink */
1404 WARN_ON(common_len
<= 0);
1406 max_clock
= common_len
- 1;
1408 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1409 pipe_config
->has_pch_encoder
= true;
1411 pipe_config
->has_dp_encoder
= true;
1412 pipe_config
->has_drrs
= false;
1413 pipe_config
->has_audio
= intel_dp
->has_audio
&& port
!= PORT_A
;
1415 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1416 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1419 if (INTEL_INFO(dev
)->gen
>= 9) {
1421 ret
= skl_update_scaler_crtc(pipe_config
);
1426 if (!HAS_PCH_SPLIT(dev
))
1427 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1428 intel_connector
->panel
.fitting_mode
);
1430 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1431 intel_connector
->panel
.fitting_mode
);
1434 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1437 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1438 "max bw %d pixel clock %iKHz\n",
1439 max_lane_count
, common_rates
[max_clock
],
1440 adjusted_mode
->crtc_clock
);
1442 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1443 * bpc in between. */
1444 bpp
= pipe_config
->pipe_bpp
;
1445 if (is_edp(intel_dp
)) {
1447 /* Get bpp from vbt only for panels that dont have bpp in edid */
1448 if (intel_connector
->base
.display_info
.bpc
== 0 &&
1449 (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
)) {
1450 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1451 dev_priv
->vbt
.edp_bpp
);
1452 bpp
= dev_priv
->vbt
.edp_bpp
;
1456 * Use the maximum clock and number of lanes the eDP panel
1457 * advertizes being capable of. The panels are generally
1458 * designed to support only a single clock and lane
1459 * configuration, and typically these values correspond to the
1460 * native resolution of the panel.
1462 min_lane_count
= max_lane_count
;
1463 min_clock
= max_clock
;
1466 for (; bpp
>= 6*3; bpp
-= 2*3) {
1467 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1470 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1471 for (lane_count
= min_lane_count
;
1472 lane_count
<= max_lane_count
;
1475 link_clock
= common_rates
[clock
];
1476 link_avail
= intel_dp_max_data_rate(link_clock
,
1479 if (mode_rate
<= link_avail
) {
1489 if (intel_dp
->color_range_auto
) {
1492 * CEA-861-E - 5.1 Default Encoding Parameters
1493 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1495 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1496 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1498 intel_dp
->color_range
= 0;
1501 if (intel_dp
->color_range
)
1502 pipe_config
->limited_color_range
= true;
1504 intel_dp
->lane_count
= lane_count
;
1506 if (intel_dp
->num_sink_rates
) {
1507 intel_dp
->link_bw
= 0;
1508 intel_dp
->rate_select
=
1509 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1512 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1513 intel_dp
->rate_select
= 0;
1516 pipe_config
->pipe_bpp
= bpp
;
1517 pipe_config
->port_clock
= common_rates
[clock
];
1519 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1520 intel_dp
->link_bw
, intel_dp
->lane_count
,
1521 pipe_config
->port_clock
, bpp
);
1522 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1523 mode_rate
, link_avail
);
1525 intel_link_compute_m_n(bpp
, lane_count
,
1526 adjusted_mode
->crtc_clock
,
1527 pipe_config
->port_clock
,
1528 &pipe_config
->dp_m_n
);
1530 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1531 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1532 pipe_config
->has_drrs
= true;
1533 intel_link_compute_m_n(bpp
, lane_count
,
1534 intel_connector
->panel
.downclock_mode
->clock
,
1535 pipe_config
->port_clock
,
1536 &pipe_config
->dp_m2_n2
);
1539 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1540 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1541 else if (IS_BROXTON(dev
))
1542 /* handled in ddi */;
1543 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1544 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1546 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1551 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1553 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1554 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1555 struct drm_device
*dev
= crtc
->base
.dev
;
1556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1559 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1560 crtc
->config
->port_clock
);
1561 dpa_ctl
= I915_READ(DP_A
);
1562 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1564 if (crtc
->config
->port_clock
== 162000) {
1565 /* For a long time we've carried around a ILK-DevA w/a for the
1566 * 160MHz clock. If we're really unlucky, it's still required.
1568 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1569 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1570 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1572 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1573 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1576 I915_WRITE(DP_A
, dpa_ctl
);
1582 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1584 struct drm_device
*dev
= encoder
->base
.dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1587 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1588 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1589 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1592 * There are four kinds of DP registers:
1599 * IBX PCH and CPU are the same for almost everything,
1600 * except that the CPU DP PLL is configured in this
1603 * CPT PCH is quite different, having many bits moved
1604 * to the TRANS_DP_CTL register instead. That
1605 * configuration happens (oddly) in ironlake_pch_enable
1608 /* Preserve the BIOS-computed detected bit. This is
1609 * supposed to be read-only.
1611 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1613 /* Handle DP bits in common between all three register formats */
1614 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1615 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1617 if (crtc
->config
->has_audio
)
1618 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1620 /* Split out the IBX/CPU vs CPT settings */
1622 if (IS_GEN7(dev
) && port
== PORT_A
) {
1623 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1624 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1625 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1626 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1627 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1629 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1630 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1632 intel_dp
->DP
|= crtc
->pipe
<< 29;
1633 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
1636 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1638 trans_dp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1639 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1640 trans_dp
|= TRANS_DP_ENH_FRAMING
;
1642 trans_dp
&= ~TRANS_DP_ENH_FRAMING
;
1643 I915_WRITE(TRANS_DP_CTL(crtc
->pipe
), trans_dp
);
1645 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1646 intel_dp
->DP
|= intel_dp
->color_range
;
1648 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1649 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1650 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1651 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1652 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1654 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1655 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1657 if (IS_CHERRYVIEW(dev
))
1658 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1659 else if (crtc
->pipe
== PIPE_B
)
1660 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1664 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1665 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1667 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1668 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1670 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1671 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1673 static void wait_panel_status(struct intel_dp
*intel_dp
,
1677 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1679 u32 pp_stat_reg
, pp_ctrl_reg
;
1681 lockdep_assert_held(&dev_priv
->pps_mutex
);
1683 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1684 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1686 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1688 I915_READ(pp_stat_reg
),
1689 I915_READ(pp_ctrl_reg
));
1691 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1692 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1693 I915_READ(pp_stat_reg
),
1694 I915_READ(pp_ctrl_reg
));
1697 DRM_DEBUG_KMS("Wait complete\n");
1700 static void wait_panel_on(struct intel_dp
*intel_dp
)
1702 DRM_DEBUG_KMS("Wait for panel power on\n");
1703 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1706 static void wait_panel_off(struct intel_dp
*intel_dp
)
1708 DRM_DEBUG_KMS("Wait for panel power off time\n");
1709 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1712 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1714 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1716 /* When we disable the VDD override bit last we have to do the manual
1718 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1719 intel_dp
->panel_power_cycle_delay
);
1721 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1724 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1726 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1727 intel_dp
->backlight_on_delay
);
1730 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1732 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1733 intel_dp
->backlight_off_delay
);
1736 /* Read the current pp_control value, unlocking the register if it
1740 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1742 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 lockdep_assert_held(&dev_priv
->pps_mutex
);
1748 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1749 if (!IS_BROXTON(dev
)) {
1750 control
&= ~PANEL_UNLOCK_MASK
;
1751 control
|= PANEL_UNLOCK_REGS
;
1757 * Must be paired with edp_panel_vdd_off().
1758 * Must hold pps_mutex around the whole on/off sequence.
1759 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1761 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1763 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1764 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1765 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1767 enum intel_display_power_domain power_domain
;
1769 u32 pp_stat_reg
, pp_ctrl_reg
;
1770 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1772 lockdep_assert_held(&dev_priv
->pps_mutex
);
1774 if (!is_edp(intel_dp
))
1777 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1778 intel_dp
->want_panel_vdd
= true;
1780 if (edp_have_panel_vdd(intel_dp
))
1781 return need_to_disable
;
1783 power_domain
= intel_display_port_power_domain(intel_encoder
);
1784 intel_display_power_get(dev_priv
, power_domain
);
1786 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1787 port_name(intel_dig_port
->port
));
1789 if (!edp_have_panel_power(intel_dp
))
1790 wait_panel_power_cycle(intel_dp
);
1792 pp
= ironlake_get_pp_control(intel_dp
);
1793 pp
|= EDP_FORCE_VDD
;
1795 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1796 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1798 I915_WRITE(pp_ctrl_reg
, pp
);
1799 POSTING_READ(pp_ctrl_reg
);
1800 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1801 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1803 * If the panel wasn't on, delay before accessing aux channel
1805 if (!edp_have_panel_power(intel_dp
)) {
1806 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1807 port_name(intel_dig_port
->port
));
1808 msleep(intel_dp
->panel_power_up_delay
);
1811 return need_to_disable
;
1815 * Must be paired with intel_edp_panel_vdd_off() or
1816 * intel_edp_panel_off().
1817 * Nested calls to these functions are not allowed since
1818 * we drop the lock. Caller must use some higher level
1819 * locking to prevent nested calls from other threads.
1821 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1825 if (!is_edp(intel_dp
))
1829 vdd
= edp_panel_vdd_on(intel_dp
);
1830 pps_unlock(intel_dp
);
1832 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1833 port_name(dp_to_dig_port(intel_dp
)->port
));
1836 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1838 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1840 struct intel_digital_port
*intel_dig_port
=
1841 dp_to_dig_port(intel_dp
);
1842 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1843 enum intel_display_power_domain power_domain
;
1845 u32 pp_stat_reg
, pp_ctrl_reg
;
1847 lockdep_assert_held(&dev_priv
->pps_mutex
);
1849 WARN_ON(intel_dp
->want_panel_vdd
);
1851 if (!edp_have_panel_vdd(intel_dp
))
1854 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1855 port_name(intel_dig_port
->port
));
1857 pp
= ironlake_get_pp_control(intel_dp
);
1858 pp
&= ~EDP_FORCE_VDD
;
1860 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1861 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1863 I915_WRITE(pp_ctrl_reg
, pp
);
1864 POSTING_READ(pp_ctrl_reg
);
1866 /* Make sure sequencer is idle before allowing subsequent activity */
1867 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1868 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1870 if ((pp
& POWER_TARGET_ON
) == 0)
1871 intel_dp
->last_power_cycle
= jiffies
;
1873 power_domain
= intel_display_port_power_domain(intel_encoder
);
1874 intel_display_power_put(dev_priv
, power_domain
);
1877 static void edp_panel_vdd_work(struct work_struct
*__work
)
1879 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1880 struct intel_dp
, panel_vdd_work
);
1883 if (!intel_dp
->want_panel_vdd
)
1884 edp_panel_vdd_off_sync(intel_dp
);
1885 pps_unlock(intel_dp
);
1888 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1890 unsigned long delay
;
1893 * Queue the timer to fire a long time from now (relative to the power
1894 * down delay) to keep the panel power up across a sequence of
1897 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1898 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1902 * Must be paired with edp_panel_vdd_on().
1903 * Must hold pps_mutex around the whole on/off sequence.
1904 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1906 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1908 struct drm_i915_private
*dev_priv
=
1909 intel_dp_to_dev(intel_dp
)->dev_private
;
1911 lockdep_assert_held(&dev_priv
->pps_mutex
);
1913 if (!is_edp(intel_dp
))
1916 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1917 port_name(dp_to_dig_port(intel_dp
)->port
));
1919 intel_dp
->want_panel_vdd
= false;
1922 edp_panel_vdd_off_sync(intel_dp
);
1924 edp_panel_vdd_schedule_off(intel_dp
);
1927 static void edp_panel_on(struct intel_dp
*intel_dp
)
1929 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1934 lockdep_assert_held(&dev_priv
->pps_mutex
);
1936 if (!is_edp(intel_dp
))
1939 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1940 port_name(dp_to_dig_port(intel_dp
)->port
));
1942 if (WARN(edp_have_panel_power(intel_dp
),
1943 "eDP port %c panel power already on\n",
1944 port_name(dp_to_dig_port(intel_dp
)->port
)))
1947 wait_panel_power_cycle(intel_dp
);
1949 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1950 pp
= ironlake_get_pp_control(intel_dp
);
1952 /* ILK workaround: disable reset around power sequence */
1953 pp
&= ~PANEL_POWER_RESET
;
1954 I915_WRITE(pp_ctrl_reg
, pp
);
1955 POSTING_READ(pp_ctrl_reg
);
1958 pp
|= POWER_TARGET_ON
;
1960 pp
|= PANEL_POWER_RESET
;
1962 I915_WRITE(pp_ctrl_reg
, pp
);
1963 POSTING_READ(pp_ctrl_reg
);
1965 wait_panel_on(intel_dp
);
1966 intel_dp
->last_power_on
= jiffies
;
1969 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1970 I915_WRITE(pp_ctrl_reg
, pp
);
1971 POSTING_READ(pp_ctrl_reg
);
1975 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1977 if (!is_edp(intel_dp
))
1981 edp_panel_on(intel_dp
);
1982 pps_unlock(intel_dp
);
1986 static void edp_panel_off(struct intel_dp
*intel_dp
)
1988 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1989 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1990 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1992 enum intel_display_power_domain power_domain
;
1996 lockdep_assert_held(&dev_priv
->pps_mutex
);
1998 if (!is_edp(intel_dp
))
2001 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2002 port_name(dp_to_dig_port(intel_dp
)->port
));
2004 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
2005 port_name(dp_to_dig_port(intel_dp
)->port
));
2007 pp
= ironlake_get_pp_control(intel_dp
);
2008 /* We need to switch off panel power _and_ force vdd, for otherwise some
2009 * panels get very unhappy and cease to work. */
2010 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
2013 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2015 intel_dp
->want_panel_vdd
= false;
2017 I915_WRITE(pp_ctrl_reg
, pp
);
2018 POSTING_READ(pp_ctrl_reg
);
2020 intel_dp
->last_power_cycle
= jiffies
;
2021 wait_panel_off(intel_dp
);
2023 /* We got a reference when we enabled the VDD. */
2024 power_domain
= intel_display_port_power_domain(intel_encoder
);
2025 intel_display_power_put(dev_priv
, power_domain
);
2028 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
2030 if (!is_edp(intel_dp
))
2034 edp_panel_off(intel_dp
);
2035 pps_unlock(intel_dp
);
2038 /* Enable backlight in the panel power control. */
2039 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2041 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2042 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2048 * If we enable the backlight right away following a panel power
2049 * on, we may see slight flicker as the panel syncs with the eDP
2050 * link. So delay a bit to make sure the image is solid before
2051 * allowing it to appear.
2053 wait_backlight_on(intel_dp
);
2057 pp
= ironlake_get_pp_control(intel_dp
);
2058 pp
|= EDP_BLC_ENABLE
;
2060 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2062 I915_WRITE(pp_ctrl_reg
, pp
);
2063 POSTING_READ(pp_ctrl_reg
);
2065 pps_unlock(intel_dp
);
2068 /* Enable backlight PWM and backlight PP control. */
2069 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2071 if (!is_edp(intel_dp
))
2074 DRM_DEBUG_KMS("\n");
2076 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2077 _intel_edp_backlight_on(intel_dp
);
2080 /* Disable backlight in the panel power control. */
2081 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2083 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2088 if (!is_edp(intel_dp
))
2093 pp
= ironlake_get_pp_control(intel_dp
);
2094 pp
&= ~EDP_BLC_ENABLE
;
2096 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2098 I915_WRITE(pp_ctrl_reg
, pp
);
2099 POSTING_READ(pp_ctrl_reg
);
2101 pps_unlock(intel_dp
);
2103 intel_dp
->last_backlight_off
= jiffies
;
2104 edp_wait_backlight_off(intel_dp
);
2107 /* Disable backlight PP control and backlight PWM. */
2108 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2110 if (!is_edp(intel_dp
))
2113 DRM_DEBUG_KMS("\n");
2115 _intel_edp_backlight_off(intel_dp
);
2116 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2120 * Hook for controlling the panel power control backlight through the bl_power
2121 * sysfs attribute. Take care to handle multiple calls.
2123 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2126 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2130 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2131 pps_unlock(intel_dp
);
2133 if (is_enabled
== enable
)
2136 DRM_DEBUG_KMS("panel power control backlight %s\n",
2137 enable
? "enable" : "disable");
2140 _intel_edp_backlight_on(intel_dp
);
2142 _intel_edp_backlight_off(intel_dp
);
2145 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2147 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2148 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2149 struct drm_device
*dev
= crtc
->dev
;
2150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 assert_pipe_disabled(dev_priv
,
2154 to_intel_crtc(crtc
)->pipe
);
2156 DRM_DEBUG_KMS("\n");
2157 dpa_ctl
= I915_READ(DP_A
);
2158 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2159 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2161 /* We don't adjust intel_dp->DP while tearing down the link, to
2162 * facilitate link retraining (e.g. after hotplug). Hence clear all
2163 * enable bits here to ensure that we don't enable too much. */
2164 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2165 intel_dp
->DP
|= DP_PLL_ENABLE
;
2166 I915_WRITE(DP_A
, intel_dp
->DP
);
2171 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2173 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2174 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2175 struct drm_device
*dev
= crtc
->dev
;
2176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2179 assert_pipe_disabled(dev_priv
,
2180 to_intel_crtc(crtc
)->pipe
);
2182 dpa_ctl
= I915_READ(DP_A
);
2183 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2184 "dp pll off, should be on\n");
2185 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2187 /* We can't rely on the value tracked for the DP register in
2188 * intel_dp->DP because link_down must not change that (otherwise link
2189 * re-training will fail. */
2190 dpa_ctl
&= ~DP_PLL_ENABLE
;
2191 I915_WRITE(DP_A
, dpa_ctl
);
2196 /* If the sink supports it, try to set the power state appropriately */
2197 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2201 /* Should have a valid DPCD by this point */
2202 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2205 if (mode
!= DRM_MODE_DPMS_ON
) {
2206 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2210 * When turning on, we need to retry for 1ms to give the sink
2213 for (i
= 0; i
< 3; i
++) {
2214 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2223 DRM_DEBUG_KMS("failed to %s sink power state\n",
2224 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2227 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2230 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2231 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2232 struct drm_device
*dev
= encoder
->base
.dev
;
2233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 enum intel_display_power_domain power_domain
;
2237 power_domain
= intel_display_port_power_domain(encoder
);
2238 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2241 tmp
= I915_READ(intel_dp
->output_reg
);
2243 if (!(tmp
& DP_PORT_EN
))
2246 if (IS_GEN7(dev
) && port
== PORT_A
) {
2247 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2248 } else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2251 for_each_pipe(dev_priv
, p
) {
2252 u32 trans_dp
= I915_READ(TRANS_DP_CTL(p
));
2253 if (TRANS_DP_PIPE_TO_PORT(trans_dp
) == port
) {
2259 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2260 intel_dp
->output_reg
);
2261 } else if (IS_CHERRYVIEW(dev
)) {
2262 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2264 *pipe
= PORT_TO_PIPE(tmp
);
2270 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2271 struct intel_crtc_state
*pipe_config
)
2273 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2275 struct drm_device
*dev
= encoder
->base
.dev
;
2276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2277 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2278 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2281 tmp
= I915_READ(intel_dp
->output_reg
);
2283 pipe_config
->has_audio
= tmp
& DP_AUDIO_OUTPUT_ENABLE
&& port
!= PORT_A
;
2285 if (HAS_PCH_CPT(dev
) && port
!= PORT_A
) {
2286 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2287 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2288 flags
|= DRM_MODE_FLAG_PHSYNC
;
2290 flags
|= DRM_MODE_FLAG_NHSYNC
;
2292 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2293 flags
|= DRM_MODE_FLAG_PVSYNC
;
2295 flags
|= DRM_MODE_FLAG_NVSYNC
;
2297 if (tmp
& DP_SYNC_HS_HIGH
)
2298 flags
|= DRM_MODE_FLAG_PHSYNC
;
2300 flags
|= DRM_MODE_FLAG_NHSYNC
;
2302 if (tmp
& DP_SYNC_VS_HIGH
)
2303 flags
|= DRM_MODE_FLAG_PVSYNC
;
2305 flags
|= DRM_MODE_FLAG_NVSYNC
;
2308 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2310 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2311 tmp
& DP_COLOR_RANGE_16_235
)
2312 pipe_config
->limited_color_range
= true;
2314 pipe_config
->has_dp_encoder
= true;
2316 intel_dp_get_m_n(crtc
, pipe_config
);
2318 if (port
== PORT_A
) {
2319 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2320 pipe_config
->port_clock
= 162000;
2322 pipe_config
->port_clock
= 270000;
2325 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2326 &pipe_config
->dp_m_n
);
2328 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2329 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2331 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2333 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2334 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2336 * This is a big fat ugly hack.
2338 * Some machines in UEFI boot mode provide us a VBT that has 18
2339 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2340 * unknown we fail to light up. Yet the same BIOS boots up with
2341 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2342 * max, not what it tells us to use.
2344 * Note: This will still be broken if the eDP panel is not lit
2345 * up by the BIOS, and thus we can't get the mode at module
2348 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2349 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2350 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2354 static void intel_disable_dp(struct intel_encoder
*encoder
)
2356 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2357 struct drm_device
*dev
= encoder
->base
.dev
;
2358 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2360 if (crtc
->config
->has_audio
)
2361 intel_audio_codec_disable(encoder
);
2363 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2364 intel_psr_disable(intel_dp
);
2366 /* Make sure the panel is off before trying to change the mode. But also
2367 * ensure that we have vdd while we switch off the panel. */
2368 intel_edp_panel_vdd_on(intel_dp
);
2369 intel_edp_backlight_off(intel_dp
);
2370 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2371 intel_edp_panel_off(intel_dp
);
2373 /* disable the port before the pipe on g4x */
2374 if (INTEL_INFO(dev
)->gen
< 5)
2375 intel_dp_link_down(intel_dp
);
2378 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2380 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2381 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2383 intel_dp_link_down(intel_dp
);
2385 ironlake_edp_pll_off(intel_dp
);
2388 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2390 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2392 intel_dp_link_down(intel_dp
);
2395 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2397 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2398 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2399 struct drm_device
*dev
= encoder
->base
.dev
;
2400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2401 struct intel_crtc
*intel_crtc
=
2402 to_intel_crtc(encoder
->base
.crtc
);
2403 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2404 enum pipe pipe
= intel_crtc
->pipe
;
2407 intel_dp_link_down(intel_dp
);
2409 mutex_lock(&dev_priv
->sb_lock
);
2411 /* Propagate soft reset to data lane reset */
2412 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2413 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2414 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2416 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2417 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2418 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2420 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2421 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2422 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2424 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2425 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2426 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2428 mutex_unlock(&dev_priv
->sb_lock
);
2432 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2434 uint8_t dp_train_pat
)
2436 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2437 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2439 enum port port
= intel_dig_port
->port
;
2442 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2444 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2445 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2447 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2449 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2450 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2451 case DP_TRAINING_PATTERN_DISABLE
:
2452 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2455 case DP_TRAINING_PATTERN_1
:
2456 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2458 case DP_TRAINING_PATTERN_2
:
2459 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2461 case DP_TRAINING_PATTERN_3
:
2462 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2465 I915_WRITE(DP_TP_CTL(port
), temp
);
2467 } else if ((IS_GEN7(dev
) && port
== PORT_A
) ||
2468 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
2469 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2471 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2472 case DP_TRAINING_PATTERN_DISABLE
:
2473 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2475 case DP_TRAINING_PATTERN_1
:
2476 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2478 case DP_TRAINING_PATTERN_2
:
2479 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2481 case DP_TRAINING_PATTERN_3
:
2482 DRM_ERROR("DP training pattern 3 not supported\n");
2483 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2488 if (IS_CHERRYVIEW(dev
))
2489 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2491 *DP
&= ~DP_LINK_TRAIN_MASK
;
2493 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2494 case DP_TRAINING_PATTERN_DISABLE
:
2495 *DP
|= DP_LINK_TRAIN_OFF
;
2497 case DP_TRAINING_PATTERN_1
:
2498 *DP
|= DP_LINK_TRAIN_PAT_1
;
2500 case DP_TRAINING_PATTERN_2
:
2501 *DP
|= DP_LINK_TRAIN_PAT_2
;
2503 case DP_TRAINING_PATTERN_3
:
2504 if (IS_CHERRYVIEW(dev
)) {
2505 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2507 DRM_ERROR("DP training pattern 3 not supported\n");
2508 *DP
|= DP_LINK_TRAIN_PAT_2
;
2515 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2520 /* enable with pattern 1 (as per spec) */
2521 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2522 DP_TRAINING_PATTERN_1
);
2524 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2525 POSTING_READ(intel_dp
->output_reg
);
2528 * Magic for VLV/CHV. We _must_ first set up the register
2529 * without actually enabling the port, and then do another
2530 * write to enable the port. Otherwise link training will
2531 * fail when the power sequencer is freshly used for this port.
2533 intel_dp
->DP
|= DP_PORT_EN
;
2535 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2536 POSTING_READ(intel_dp
->output_reg
);
2539 static void intel_enable_dp(struct intel_encoder
*encoder
)
2541 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2542 struct drm_device
*dev
= encoder
->base
.dev
;
2543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2544 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2545 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2546 unsigned int lane_mask
= 0x0;
2548 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2553 if (IS_VALLEYVIEW(dev
))
2554 vlv_init_panel_power_sequencer(intel_dp
);
2556 intel_dp_enable_port(intel_dp
);
2558 edp_panel_vdd_on(intel_dp
);
2559 edp_panel_on(intel_dp
);
2560 edp_panel_vdd_off(intel_dp
, true);
2562 pps_unlock(intel_dp
);
2564 if (IS_VALLEYVIEW(dev
))
2565 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
),
2568 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2569 intel_dp_start_link_train(intel_dp
);
2570 intel_dp_complete_link_train(intel_dp
);
2571 intel_dp_stop_link_train(intel_dp
);
2573 if (crtc
->config
->has_audio
) {
2574 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2575 pipe_name(crtc
->pipe
));
2576 intel_audio_codec_enable(encoder
);
2580 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2582 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2584 intel_enable_dp(encoder
);
2585 intel_edp_backlight_on(intel_dp
);
2588 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2590 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2592 intel_edp_backlight_on(intel_dp
);
2593 intel_psr_enable(intel_dp
);
2596 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2598 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2599 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2601 intel_dp_prepare(encoder
);
2603 /* Only ilk+ has port A */
2604 if (dport
->port
== PORT_A
) {
2605 ironlake_set_pll_cpu_edp(intel_dp
);
2606 ironlake_edp_pll_on(intel_dp
);
2610 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2612 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2613 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2614 enum pipe pipe
= intel_dp
->pps_pipe
;
2615 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2617 edp_panel_vdd_off_sync(intel_dp
);
2620 * VLV seems to get confused when multiple power seqeuencers
2621 * have the same port selected (even if only one has power/vdd
2622 * enabled). The failure manifests as vlv_wait_port_ready() failing
2623 * CHV on the other hand doesn't seem to mind having the same port
2624 * selected in multiple power seqeuencers, but let's clear the
2625 * port select always when logically disconnecting a power sequencer
2628 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2629 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2630 I915_WRITE(pp_on_reg
, 0);
2631 POSTING_READ(pp_on_reg
);
2633 intel_dp
->pps_pipe
= INVALID_PIPE
;
2636 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2640 struct intel_encoder
*encoder
;
2642 lockdep_assert_held(&dev_priv
->pps_mutex
);
2644 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2647 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2649 struct intel_dp
*intel_dp
;
2652 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2655 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2656 port
= dp_to_dig_port(intel_dp
)->port
;
2658 if (intel_dp
->pps_pipe
!= pipe
)
2661 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2662 pipe_name(pipe
), port_name(port
));
2664 WARN(encoder
->base
.crtc
,
2665 "stealing pipe %c power sequencer from active eDP port %c\n",
2666 pipe_name(pipe
), port_name(port
));
2668 /* make sure vdd is off before we steal it */
2669 vlv_detach_power_sequencer(intel_dp
);
2673 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2675 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2676 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2677 struct drm_device
*dev
= encoder
->base
.dev
;
2678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2679 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2681 lockdep_assert_held(&dev_priv
->pps_mutex
);
2683 if (!is_edp(intel_dp
))
2686 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2690 * If another power sequencer was being used on this
2691 * port previously make sure to turn off vdd there while
2692 * we still have control of it.
2694 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2695 vlv_detach_power_sequencer(intel_dp
);
2698 * We may be stealing the power
2699 * sequencer from another port.
2701 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2703 /* now it's all ours */
2704 intel_dp
->pps_pipe
= crtc
->pipe
;
2706 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2707 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2709 /* init power sequencer on this pipe and port */
2710 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2711 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2714 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2716 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2717 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2718 struct drm_device
*dev
= encoder
->base
.dev
;
2719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2720 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2721 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2722 int pipe
= intel_crtc
->pipe
;
2725 mutex_lock(&dev_priv
->sb_lock
);
2727 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2734 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2735 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2736 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2738 mutex_unlock(&dev_priv
->sb_lock
);
2740 intel_enable_dp(encoder
);
2743 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2745 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2746 struct drm_device
*dev
= encoder
->base
.dev
;
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 struct intel_crtc
*intel_crtc
=
2749 to_intel_crtc(encoder
->base
.crtc
);
2750 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2751 int pipe
= intel_crtc
->pipe
;
2753 intel_dp_prepare(encoder
);
2755 /* Program Tx lane resets to default */
2756 mutex_lock(&dev_priv
->sb_lock
);
2757 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2758 DPIO_PCS_TX_LANE2_RESET
|
2759 DPIO_PCS_TX_LANE1_RESET
);
2760 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2761 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2762 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2763 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2764 DPIO_PCS_CLK_SOFT_RESET
);
2766 /* Fix up inter-pair skew failure */
2767 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2768 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2769 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2770 mutex_unlock(&dev_priv
->sb_lock
);
2773 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2775 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2776 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2777 struct drm_device
*dev
= encoder
->base
.dev
;
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2779 struct intel_crtc
*intel_crtc
=
2780 to_intel_crtc(encoder
->base
.crtc
);
2781 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2782 int pipe
= intel_crtc
->pipe
;
2783 int data
, i
, stagger
;
2786 mutex_lock(&dev_priv
->sb_lock
);
2788 /* allow hardware to manage TX FIFO reset source */
2789 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2790 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2791 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2793 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2794 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2795 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2797 /* Deassert soft data lane reset*/
2798 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2799 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2800 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2802 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2803 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2804 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2806 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2807 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2808 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2810 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2811 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2812 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2814 /* Program Tx lane latency optimal setting*/
2815 for (i
= 0; i
< 4; i
++) {
2816 /* Set the upar bit */
2817 data
= (i
== 1) ? 0x0 : 0x1;
2818 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2819 data
<< DPIO_UPAR_SHIFT
);
2822 /* Data lane stagger programming */
2823 if (intel_crtc
->config
->port_clock
> 270000)
2825 else if (intel_crtc
->config
->port_clock
> 135000)
2827 else if (intel_crtc
->config
->port_clock
> 67500)
2829 else if (intel_crtc
->config
->port_clock
> 33750)
2834 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2835 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2836 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2838 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2839 val
|= DPIO_TX2_STAGGER_MASK(0x1f);
2840 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2842 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW12(ch
),
2843 DPIO_LANESTAGGER_STRAP(stagger
) |
2844 DPIO_LANESTAGGER_STRAP_OVRD
|
2845 DPIO_TX1_STAGGER_MASK(0x1f) |
2846 DPIO_TX1_STAGGER_MULT(6) |
2847 DPIO_TX2_STAGGER_MULT(0));
2849 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW12(ch
),
2850 DPIO_LANESTAGGER_STRAP(stagger
) |
2851 DPIO_LANESTAGGER_STRAP_OVRD
|
2852 DPIO_TX1_STAGGER_MASK(0x1f) |
2853 DPIO_TX1_STAGGER_MULT(7) |
2854 DPIO_TX2_STAGGER_MULT(5));
2856 mutex_unlock(&dev_priv
->sb_lock
);
2858 intel_enable_dp(encoder
);
2861 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2863 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2864 struct drm_device
*dev
= encoder
->base
.dev
;
2865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2866 struct intel_crtc
*intel_crtc
=
2867 to_intel_crtc(encoder
->base
.crtc
);
2868 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2869 enum pipe pipe
= intel_crtc
->pipe
;
2872 intel_dp_prepare(encoder
);
2874 mutex_lock(&dev_priv
->sb_lock
);
2876 /* program left/right clock distribution */
2877 if (pipe
!= PIPE_B
) {
2878 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2879 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2881 val
|= CHV_BUFLEFTENA1_FORCE
;
2883 val
|= CHV_BUFRIGHTENA1_FORCE
;
2884 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2886 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2887 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2889 val
|= CHV_BUFLEFTENA2_FORCE
;
2891 val
|= CHV_BUFRIGHTENA2_FORCE
;
2892 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2895 /* program clock channel usage */
2896 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2897 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2899 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2901 val
|= CHV_PCS_USEDCLKCHANNEL
;
2902 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2904 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2905 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2907 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2909 val
|= CHV_PCS_USEDCLKCHANNEL
;
2910 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2913 * This a a bit weird since generally CL
2914 * matches the pipe, but here we need to
2915 * pick the CL based on the port.
2917 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2919 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2921 val
|= CHV_CMN_USEDCLKCHANNEL
;
2922 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2924 mutex_unlock(&dev_priv
->sb_lock
);
2928 * Native read with retry for link status and receiver capability reads for
2929 * cases where the sink may still be asleep.
2931 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2932 * supposed to retry 3 times per the spec.
2935 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2936 void *buffer
, size_t size
)
2942 * Sometime we just get the same incorrect byte repeated
2943 * over the entire buffer. Doing just one throw away read
2944 * initially seems to "solve" it.
2946 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2948 for (i
= 0; i
< 3; i
++) {
2949 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2959 * Fetch AUX CH registers 0x202 - 0x207 which contain
2960 * link status information
2963 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2965 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2968 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2971 /* These are source-specific values. */
2973 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2975 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2977 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2979 if (IS_BROXTON(dev
))
2980 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2981 else if (INTEL_INFO(dev
)->gen
>= 9) {
2982 if (dev_priv
->edp_low_vswing
&& port
== PORT_A
)
2983 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2984 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2985 } else if (IS_VALLEYVIEW(dev
))
2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2987 else if (IS_GEN7(dev
) && port
== PORT_A
)
2988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2989 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2996 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2998 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2999 enum port port
= dp_to_dig_port(intel_dp
)->port
;
3001 if (INTEL_INFO(dev
)->gen
>= 9) {
3002 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3004 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3006 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3012 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3014 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3015 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3017 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3026 } else if (IS_VALLEYVIEW(dev
)) {
3027 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3029 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3031 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3033 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3038 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3039 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3041 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3046 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3049 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3053 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3055 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
3063 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
3065 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3067 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3068 struct intel_crtc
*intel_crtc
=
3069 to_intel_crtc(dport
->base
.base
.crtc
);
3070 unsigned long demph_reg_value
, preemph_reg_value
,
3071 uniqtranscale_reg_value
;
3072 uint8_t train_set
= intel_dp
->train_set
[0];
3073 enum dpio_channel port
= vlv_dport_to_channel(dport
);
3074 int pipe
= intel_crtc
->pipe
;
3076 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3077 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3078 preemph_reg_value
= 0x0004000;
3079 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3081 demph_reg_value
= 0x2B405555;
3082 uniqtranscale_reg_value
= 0x552AB83A;
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3085 demph_reg_value
= 0x2B404040;
3086 uniqtranscale_reg_value
= 0x5548B83A;
3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3089 demph_reg_value
= 0x2B245555;
3090 uniqtranscale_reg_value
= 0x5560B83A;
3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3093 demph_reg_value
= 0x2B405555;
3094 uniqtranscale_reg_value
= 0x5598DA3A;
3100 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3101 preemph_reg_value
= 0x0002000;
3102 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3104 demph_reg_value
= 0x2B404040;
3105 uniqtranscale_reg_value
= 0x5552B83A;
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3108 demph_reg_value
= 0x2B404848;
3109 uniqtranscale_reg_value
= 0x5580B83A;
3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3112 demph_reg_value
= 0x2B404040;
3113 uniqtranscale_reg_value
= 0x55ADDA3A;
3119 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3120 preemph_reg_value
= 0x0000000;
3121 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3123 demph_reg_value
= 0x2B305555;
3124 uniqtranscale_reg_value
= 0x5570B83A;
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3127 demph_reg_value
= 0x2B2B4040;
3128 uniqtranscale_reg_value
= 0x55ADDA3A;
3134 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3135 preemph_reg_value
= 0x0006000;
3136 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3138 demph_reg_value
= 0x1B405555;
3139 uniqtranscale_reg_value
= 0x55ADDA3A;
3149 mutex_lock(&dev_priv
->sb_lock
);
3150 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3151 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3152 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3153 uniqtranscale_reg_value
);
3154 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3155 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3156 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3157 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3158 mutex_unlock(&dev_priv
->sb_lock
);
3163 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3165 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3167 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3168 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3169 u32 deemph_reg_value
, margin_reg_value
, val
;
3170 uint8_t train_set
= intel_dp
->train_set
[0];
3171 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3172 enum pipe pipe
= intel_crtc
->pipe
;
3175 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3176 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3177 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3179 deemph_reg_value
= 128;
3180 margin_reg_value
= 52;
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3183 deemph_reg_value
= 128;
3184 margin_reg_value
= 77;
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3187 deemph_reg_value
= 128;
3188 margin_reg_value
= 102;
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3191 deemph_reg_value
= 128;
3192 margin_reg_value
= 154;
3193 /* FIXME extra to set for 1200 */
3199 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3200 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3202 deemph_reg_value
= 85;
3203 margin_reg_value
= 78;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3206 deemph_reg_value
= 85;
3207 margin_reg_value
= 116;
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3210 deemph_reg_value
= 85;
3211 margin_reg_value
= 154;
3217 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3218 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3220 deemph_reg_value
= 64;
3221 margin_reg_value
= 104;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3224 deemph_reg_value
= 64;
3225 margin_reg_value
= 154;
3231 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3232 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3234 deemph_reg_value
= 43;
3235 margin_reg_value
= 154;
3245 mutex_lock(&dev_priv
->sb_lock
);
3247 /* Clear calc init */
3248 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3249 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3250 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3251 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3252 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3254 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3255 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3256 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3257 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3258 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3260 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3261 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3262 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3263 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3265 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3266 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3267 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3268 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3270 /* Program swing deemph */
3271 for (i
= 0; i
< 4; i
++) {
3272 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3273 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3274 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3275 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3278 /* Program swing margin */
3279 for (i
= 0; i
< 4; i
++) {
3280 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3281 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3282 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3283 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3286 /* Disable unique transition scale */
3287 for (i
= 0; i
< 4; i
++) {
3288 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3289 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3290 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3293 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3294 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3295 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3296 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3299 * The document said it needs to set bit 27 for ch0 and bit 26
3300 * for ch1. Might be a typo in the doc.
3301 * For now, for this unique transition scale selection, set bit
3302 * 27 for ch0 and ch1.
3304 for (i
= 0; i
< 4; i
++) {
3305 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3306 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3307 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3310 for (i
= 0; i
< 4; i
++) {
3311 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3312 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3313 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3314 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3318 /* Start swing calculation */
3319 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3320 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3321 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3323 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3324 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3325 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3328 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3329 val
|= DPIO_LRC_BYPASS
;
3330 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3332 mutex_unlock(&dev_priv
->sb_lock
);
3338 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3339 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3344 uint8_t voltage_max
;
3345 uint8_t preemph_max
;
3347 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3348 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3349 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3357 voltage_max
= intel_dp_voltage_max(intel_dp
);
3358 if (v
>= voltage_max
)
3359 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3361 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3362 if (p
>= preemph_max
)
3363 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3365 for (lane
= 0; lane
< 4; lane
++)
3366 intel_dp
->train_set
[lane
] = v
| p
;
3370 gen4_signal_levels(uint8_t train_set
)
3372 uint32_t signal_levels
= 0;
3374 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3377 signal_levels
|= DP_VOLTAGE_0_4
;
3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3380 signal_levels
|= DP_VOLTAGE_0_6
;
3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3383 signal_levels
|= DP_VOLTAGE_0_8
;
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3386 signal_levels
|= DP_VOLTAGE_1_2
;
3389 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3390 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3392 signal_levels
|= DP_PRE_EMPHASIS_0
;
3394 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3395 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3397 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3398 signal_levels
|= DP_PRE_EMPHASIS_6
;
3400 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3401 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3404 return signal_levels
;
3407 /* Gen6's DP voltage swing and pre-emphasis control */
3409 gen6_edp_signal_levels(uint8_t train_set
)
3411 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3412 DP_TRAIN_PRE_EMPHASIS_MASK
);
3413 switch (signal_levels
) {
3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3416 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3418 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3421 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3424 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3427 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3429 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3430 "0x%x\n", signal_levels
);
3431 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3435 /* Gen7's DP voltage swing and pre-emphasis control */
3437 gen7_edp_signal_levels(uint8_t train_set
)
3439 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3440 DP_TRAIN_PRE_EMPHASIS_MASK
);
3441 switch (signal_levels
) {
3442 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3443 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3445 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3447 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3450 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3452 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3455 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3457 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3460 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3461 "0x%x\n", signal_levels
);
3462 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3466 /* Properly updates "DP" with the correct signal levels. */
3468 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3470 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3471 enum port port
= intel_dig_port
->port
;
3472 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3473 uint32_t signal_levels
, mask
= 0;
3474 uint8_t train_set
= intel_dp
->train_set
[0];
3477 signal_levels
= ddi_signal_levels(intel_dp
);
3479 if (IS_BROXTON(dev
))
3482 mask
= DDI_BUF_EMP_MASK
;
3483 } else if (IS_CHERRYVIEW(dev
)) {
3484 signal_levels
= chv_signal_levels(intel_dp
);
3485 } else if (IS_VALLEYVIEW(dev
)) {
3486 signal_levels
= vlv_signal_levels(intel_dp
);
3487 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3488 signal_levels
= gen7_edp_signal_levels(train_set
);
3489 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3490 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3491 signal_levels
= gen6_edp_signal_levels(train_set
);
3492 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3494 signal_levels
= gen4_signal_levels(train_set
);
3495 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3499 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3501 DRM_DEBUG_KMS("Using vswing level %d\n",
3502 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3503 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3504 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3505 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3507 *DP
= (*DP
& ~mask
) | signal_levels
;
3511 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3513 uint8_t dp_train_pat
)
3515 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3516 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3518 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3521 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3523 I915_WRITE(intel_dp
->output_reg
, *DP
);
3524 POSTING_READ(intel_dp
->output_reg
);
3526 buf
[0] = dp_train_pat
;
3527 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3528 DP_TRAINING_PATTERN_DISABLE
) {
3529 /* don't write DP_TRAINING_LANEx_SET on disable */
3532 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3533 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3534 len
= intel_dp
->lane_count
+ 1;
3537 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3544 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3545 uint8_t dp_train_pat
)
3547 if (!intel_dp
->train_set_valid
)
3548 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3549 intel_dp_set_signal_levels(intel_dp
, DP
);
3550 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3554 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3555 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3557 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3558 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3562 intel_get_adjust_train(intel_dp
, link_status
);
3563 intel_dp_set_signal_levels(intel_dp
, DP
);
3565 I915_WRITE(intel_dp
->output_reg
, *DP
);
3566 POSTING_READ(intel_dp
->output_reg
);
3568 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3569 intel_dp
->train_set
, intel_dp
->lane_count
);
3571 return ret
== intel_dp
->lane_count
;
3574 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3576 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3577 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3579 enum port port
= intel_dig_port
->port
;
3585 val
= I915_READ(DP_TP_CTL(port
));
3586 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3587 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3588 I915_WRITE(DP_TP_CTL(port
), val
);
3591 * On PORT_A we can have only eDP in SST mode. There the only reason
3592 * we need to set idle transmission mode is to work around a HW issue
3593 * where we enable the pipe while not in idle link-training mode.
3594 * In this case there is requirement to wait for a minimum number of
3595 * idle patterns to be sent.
3600 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3602 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3605 /* Enable corresponding port and start training pattern 1 */
3607 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3609 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3610 struct drm_device
*dev
= encoder
->dev
;
3613 int voltage_tries
, loop_tries
;
3614 uint32_t DP
= intel_dp
->DP
;
3615 uint8_t link_config
[2];
3618 intel_ddi_prepare_link_retrain(encoder
);
3620 /* Write the link configuration data */
3621 link_config
[0] = intel_dp
->link_bw
;
3622 link_config
[1] = intel_dp
->lane_count
;
3623 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3624 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3625 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3626 if (intel_dp
->num_sink_rates
)
3627 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3628 &intel_dp
->rate_select
, 1);
3631 link_config
[1] = DP_SET_ANSI_8B10B
;
3632 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3636 /* clock recovery */
3637 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3638 DP_TRAINING_PATTERN_1
|
3639 DP_LINK_SCRAMBLING_DISABLE
)) {
3640 DRM_ERROR("failed to enable link training\n");
3648 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3650 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3651 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3652 DRM_ERROR("failed to get link status\n");
3656 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3657 DRM_DEBUG_KMS("clock recovery OK\n");
3662 * if we used previously trained voltage and pre-emphasis values
3663 * and we don't get clock recovery, reset link training values
3665 if (intel_dp
->train_set_valid
) {
3666 DRM_DEBUG_KMS("clock recovery not ok, reset");
3667 /* clear the flag as we are not reusing train set */
3668 intel_dp
->train_set_valid
= false;
3669 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3670 DP_TRAINING_PATTERN_1
|
3671 DP_LINK_SCRAMBLING_DISABLE
)) {
3672 DRM_ERROR("failed to enable link training\n");
3678 /* Check to see if we've tried the max voltage */
3679 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3680 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3682 if (i
== intel_dp
->lane_count
) {
3684 if (loop_tries
== 5) {
3685 DRM_ERROR("too many full retries, give up\n");
3688 intel_dp_reset_link_train(intel_dp
, &DP
,
3689 DP_TRAINING_PATTERN_1
|
3690 DP_LINK_SCRAMBLING_DISABLE
);
3695 /* Check to see if we've tried the same voltage 5 times */
3696 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3698 if (voltage_tries
== 5) {
3699 DRM_ERROR("too many voltage retries, give up\n");
3704 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3706 /* Update training set as requested by target */
3707 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3708 DRM_ERROR("failed to update link training\n");
3717 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3719 bool channel_eq
= false;
3720 int tries
, cr_tries
;
3721 uint32_t DP
= intel_dp
->DP
;
3722 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3724 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3725 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3726 training_pattern
= DP_TRAINING_PATTERN_3
;
3728 /* channel equalization */
3729 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3731 DP_LINK_SCRAMBLING_DISABLE
)) {
3732 DRM_ERROR("failed to start channel equalization\n");
3740 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3743 DRM_ERROR("failed to train DP, aborting\n");
3747 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3748 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3749 DRM_ERROR("failed to get link status\n");
3753 /* Make sure clock is still ok */
3754 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3755 intel_dp
->train_set_valid
= false;
3756 intel_dp_start_link_train(intel_dp
);
3757 intel_dp_set_link_train(intel_dp
, &DP
,
3759 DP_LINK_SCRAMBLING_DISABLE
);
3764 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3769 /* Try 5 times, then try clock recovery if that fails */
3771 intel_dp
->train_set_valid
= false;
3772 intel_dp_start_link_train(intel_dp
);
3773 intel_dp_set_link_train(intel_dp
, &DP
,
3775 DP_LINK_SCRAMBLING_DISABLE
);
3781 /* Update training set as requested by target */
3782 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3783 DRM_ERROR("failed to update link training\n");
3789 intel_dp_set_idle_link_train(intel_dp
);
3794 intel_dp
->train_set_valid
= true;
3795 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3799 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3801 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3802 DP_TRAINING_PATTERN_DISABLE
);
3806 intel_dp_link_down(struct intel_dp
*intel_dp
)
3808 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3809 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3810 enum port port
= intel_dig_port
->port
;
3811 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3813 uint32_t DP
= intel_dp
->DP
;
3815 if (WARN_ON(HAS_DDI(dev
)))
3818 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3821 DRM_DEBUG_KMS("\n");
3823 if ((IS_GEN7(dev
) && port
== PORT_A
) ||
3824 (HAS_PCH_CPT(dev
) && port
!= PORT_A
)) {
3825 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3826 DP
|= DP_LINK_TRAIN_PAT_IDLE_CPT
;
3828 if (IS_CHERRYVIEW(dev
))
3829 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3831 DP
&= ~DP_LINK_TRAIN_MASK
;
3832 DP
|= DP_LINK_TRAIN_PAT_IDLE
;
3834 I915_WRITE(intel_dp
->output_reg
, DP
);
3835 POSTING_READ(intel_dp
->output_reg
);
3837 DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
3838 I915_WRITE(intel_dp
->output_reg
, DP
);
3839 POSTING_READ(intel_dp
->output_reg
);
3842 * HW workaround for IBX, we need to move the port
3843 * to transcoder A after disabling it to allow the
3844 * matching HDMI port to be enabled on transcoder A.
3846 if (HAS_PCH_IBX(dev
) && crtc
->pipe
== PIPE_B
&& port
!= PORT_A
) {
3847 /* always enable with pattern 1 (as per spec) */
3848 DP
&= ~(DP_PIPEB_SELECT
| DP_LINK_TRAIN_MASK
);
3849 DP
|= DP_PORT_EN
| DP_LINK_TRAIN_PAT_1
;
3850 I915_WRITE(intel_dp
->output_reg
, DP
);
3851 POSTING_READ(intel_dp
->output_reg
);
3854 I915_WRITE(intel_dp
->output_reg
, DP
);
3855 POSTING_READ(intel_dp
->output_reg
);
3858 msleep(intel_dp
->panel_power_down_delay
);
3862 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3864 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3865 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3869 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3870 sizeof(intel_dp
->dpcd
)) < 0)
3871 return false; /* aux transfer failed */
3873 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3875 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3876 return false; /* DPCD not present */
3878 /* Check if the panel supports PSR */
3879 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3880 if (is_edp(intel_dp
)) {
3881 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3883 sizeof(intel_dp
->psr_dpcd
));
3884 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3885 dev_priv
->psr
.sink_support
= true;
3886 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3889 if (INTEL_INFO(dev
)->gen
>= 9 &&
3890 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3891 uint8_t frame_sync_cap
;
3893 dev_priv
->psr
.sink_support
= true;
3894 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3895 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3896 &frame_sync_cap
, 1);
3897 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3898 /* PSR2 needs frame sync as well */
3899 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3900 DRM_DEBUG_KMS("PSR2 %s on sink",
3901 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3905 /* Training Pattern 3 support, both source and sink */
3906 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3907 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3908 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3909 intel_dp
->use_tps3
= true;
3910 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3912 intel_dp
->use_tps3
= false;
3914 /* Intermediate frequency support */
3915 if (is_edp(intel_dp
) &&
3916 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3917 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3918 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3919 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3922 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3923 DP_SUPPORTED_LINK_RATES
,
3925 sizeof(sink_rates
));
3927 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3928 int val
= le16_to_cpu(sink_rates
[i
]);
3933 /* Value read is in kHz while drm clock is saved in deca-kHz */
3934 intel_dp
->sink_rates
[i
] = (val
* 200) / 10;
3936 intel_dp
->num_sink_rates
= i
;
3939 intel_dp_print_rates(intel_dp
);
3941 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3942 DP_DWN_STRM_PORT_PRESENT
))
3943 return true; /* native DP sink */
3945 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3946 return true; /* no per-port downstream info */
3948 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3949 intel_dp
->downstream_ports
,
3950 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3951 return false; /* downstream port status fetch failed */
3957 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3961 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3964 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3965 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3966 buf
[0], buf
[1], buf
[2]);
3968 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3969 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3970 buf
[0], buf
[1], buf
[2]);
3974 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3978 if (!intel_dp
->can_mst
)
3981 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3984 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3985 if (buf
[0] & DP_MST_CAP
) {
3986 DRM_DEBUG_KMS("Sink is MST capable\n");
3987 intel_dp
->is_mst
= true;
3989 DRM_DEBUG_KMS("Sink is not MST capable\n");
3990 intel_dp
->is_mst
= false;
3994 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3995 return intel_dp
->is_mst
;
3998 static void intel_dp_sink_crc_stop(struct intel_dp
*intel_dp
)
4000 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4001 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4004 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0) {
4005 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4009 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4010 buf
& ~DP_TEST_SINK_START
) < 0)
4011 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4013 hsw_enable_ips(intel_crtc
);
4016 static int intel_dp_sink_crc_start(struct intel_dp
*intel_dp
)
4018 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4019 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4022 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
4025 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
4028 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4031 hsw_disable_ips(intel_crtc
);
4033 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4034 buf
| DP_TEST_SINK_START
) < 0) {
4035 hsw_enable_ips(intel_crtc
);
4042 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
4044 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
4045 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
4046 struct intel_crtc
*intel_crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
4052 ret
= intel_dp_sink_crc_start(intel_dp
);
4056 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0) {
4061 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4064 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4065 DP_TEST_SINK_MISC
, &buf
) < 0) {
4069 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4070 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4072 if (attempts
== 0) {
4073 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4078 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
4081 intel_dp_sink_crc_stop(intel_dp
);
4086 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4088 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4089 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4090 sink_irq_vector
, 1) == 1;
4094 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4098 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4100 sink_irq_vector
, 14);
4107 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4109 uint8_t test_result
= DP_TEST_ACK
;
4113 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4115 uint8_t test_result
= DP_TEST_NAK
;
4119 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4121 uint8_t test_result
= DP_TEST_NAK
;
4122 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4123 struct drm_connector
*connector
= &intel_connector
->base
;
4125 if (intel_connector
->detect_edid
== NULL
||
4126 connector
->edid_corrupt
||
4127 intel_dp
->aux
.i2c_defer_count
> 6) {
4128 /* Check EDID read for NACKs, DEFERs and corruption
4129 * (DP CTS 1.2 Core r1.1)
4130 * 4.2.2.4 : Failed EDID read, I2C_NAK
4131 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4132 * 4.2.2.6 : EDID corruption detected
4133 * Use failsafe mode for all cases
4135 if (intel_dp
->aux
.i2c_nack_count
> 0 ||
4136 intel_dp
->aux
.i2c_defer_count
> 0)
4137 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4138 intel_dp
->aux
.i2c_nack_count
,
4139 intel_dp
->aux
.i2c_defer_count
);
4140 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_FAILSAFE
;
4142 if (!drm_dp_dpcd_write(&intel_dp
->aux
,
4143 DP_TEST_EDID_CHECKSUM
,
4144 &intel_connector
->detect_edid
->checksum
,
4146 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4148 test_result
= DP_TEST_ACK
| DP_TEST_EDID_CHECKSUM_WRITE
;
4149 intel_dp
->compliance_test_data
= INTEL_DP_RESOLUTION_STANDARD
;
4152 /* Set test active flag here so userspace doesn't interrupt things */
4153 intel_dp
->compliance_test_active
= 1;
4158 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4160 uint8_t test_result
= DP_TEST_NAK
;
4164 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4166 uint8_t response
= DP_TEST_NAK
;
4170 intel_dp
->compliance_test_active
= 0;
4171 intel_dp
->compliance_test_type
= 0;
4172 intel_dp
->compliance_test_data
= 0;
4174 intel_dp
->aux
.i2c_nack_count
= 0;
4175 intel_dp
->aux
.i2c_defer_count
= 0;
4177 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4179 DRM_DEBUG_KMS("Could not read test request from sink\n");
4184 case DP_TEST_LINK_TRAINING
:
4185 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4186 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4187 response
= intel_dp_autotest_link_training(intel_dp
);
4189 case DP_TEST_LINK_VIDEO_PATTERN
:
4190 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4191 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4192 response
= intel_dp_autotest_video_pattern(intel_dp
);
4194 case DP_TEST_LINK_EDID_READ
:
4195 DRM_DEBUG_KMS("EDID test requested\n");
4196 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4197 response
= intel_dp_autotest_edid(intel_dp
);
4199 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4200 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4201 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4202 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4205 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4210 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4214 DRM_DEBUG_KMS("Could not write test response to sink\n");
4218 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4222 if (intel_dp
->is_mst
) {
4227 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4231 /* check link status - esi[10] = 0x200c */
4232 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4233 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4234 intel_dp_start_link_train(intel_dp
);
4235 intel_dp_complete_link_train(intel_dp
);
4236 intel_dp_stop_link_train(intel_dp
);
4239 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4240 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4243 for (retry
= 0; retry
< 3; retry
++) {
4245 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4246 DP_SINK_COUNT_ESI
+1,
4253 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4255 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4263 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4264 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4265 intel_dp
->is_mst
= false;
4266 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4267 /* send a hotplug event */
4268 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4275 * According to DP spec
4278 * 2. Configure link according to Receiver Capabilities
4279 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4280 * 4. Check link status on receipt of hot-plug interrupt
4283 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4285 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4286 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4288 u8 link_status
[DP_LINK_STATUS_SIZE
];
4290 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4292 if (!intel_encoder
->base
.crtc
)
4295 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4298 /* Try to read receiver status if the link appears to be up */
4299 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4303 /* Now read the DPCD to see if it's actually running */
4304 if (!intel_dp_get_dpcd(intel_dp
)) {
4308 /* Try to read the source of the interrupt */
4309 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4310 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4311 /* Clear interrupt source */
4312 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4313 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4316 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4317 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4318 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4319 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4322 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4323 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4324 intel_encoder
->base
.name
);
4325 intel_dp_start_link_train(intel_dp
);
4326 intel_dp_complete_link_train(intel_dp
);
4327 intel_dp_stop_link_train(intel_dp
);
4331 /* XXX this is probably wrong for multiple downstream ports */
4332 static enum drm_connector_status
4333 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4335 uint8_t *dpcd
= intel_dp
->dpcd
;
4338 if (!intel_dp_get_dpcd(intel_dp
))
4339 return connector_status_disconnected
;
4341 /* if there's no downstream port, we're done */
4342 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4343 return connector_status_connected
;
4345 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4346 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4347 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4350 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4352 return connector_status_unknown
;
4354 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4355 : connector_status_disconnected
;
4358 /* If no HPD, poke DDC gently */
4359 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4360 return connector_status_connected
;
4362 /* Well we tried, say unknown for unreliable port types */
4363 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4364 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4365 if (type
== DP_DS_PORT_TYPE_VGA
||
4366 type
== DP_DS_PORT_TYPE_NON_EDID
)
4367 return connector_status_unknown
;
4369 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4370 DP_DWN_STRM_PORT_TYPE_MASK
;
4371 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4372 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4373 return connector_status_unknown
;
4376 /* Anything else is out of spec, warn and ignore */
4377 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4378 return connector_status_disconnected
;
4381 static enum drm_connector_status
4382 edp_detect(struct intel_dp
*intel_dp
)
4384 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4385 enum drm_connector_status status
;
4387 status
= intel_panel_detect(dev
);
4388 if (status
== connector_status_unknown
)
4389 status
= connector_status_connected
;
4394 static enum drm_connector_status
4395 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4397 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4399 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4401 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4402 return connector_status_disconnected
;
4404 return intel_dp_detect_dpcd(intel_dp
);
4407 static int g4x_digital_port_connected(struct drm_device
*dev
,
4408 struct intel_digital_port
*intel_dig_port
)
4410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4413 if (IS_VALLEYVIEW(dev
)) {
4414 switch (intel_dig_port
->port
) {
4416 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4419 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4422 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4428 switch (intel_dig_port
->port
) {
4430 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4433 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4436 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4443 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4448 static enum drm_connector_status
4449 g4x_dp_detect(struct intel_dp
*intel_dp
)
4451 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4452 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4455 /* Can't disconnect eDP, but you can close the lid... */
4456 if (is_edp(intel_dp
)) {
4457 enum drm_connector_status status
;
4459 status
= intel_panel_detect(dev
);
4460 if (status
== connector_status_unknown
)
4461 status
= connector_status_connected
;
4465 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4467 return connector_status_unknown
;
4469 return connector_status_disconnected
;
4471 return intel_dp_detect_dpcd(intel_dp
);
4474 static struct edid
*
4475 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4477 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4479 /* use cached edid if we have one */
4480 if (intel_connector
->edid
) {
4482 if (IS_ERR(intel_connector
->edid
))
4485 return drm_edid_duplicate(intel_connector
->edid
);
4487 return drm_get_edid(&intel_connector
->base
,
4488 &intel_dp
->aux
.ddc
);
4492 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4494 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4497 edid
= intel_dp_get_edid(intel_dp
);
4498 intel_connector
->detect_edid
= edid
;
4500 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4501 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4503 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4507 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4509 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4511 kfree(intel_connector
->detect_edid
);
4512 intel_connector
->detect_edid
= NULL
;
4514 intel_dp
->has_audio
= false;
4517 static enum intel_display_power_domain
4518 intel_dp_power_get(struct intel_dp
*dp
)
4520 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4521 enum intel_display_power_domain power_domain
;
4523 power_domain
= intel_display_port_power_domain(encoder
);
4524 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4526 return power_domain
;
4530 intel_dp_power_put(struct intel_dp
*dp
,
4531 enum intel_display_power_domain power_domain
)
4533 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4534 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4537 static enum drm_connector_status
4538 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4540 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4541 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4542 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4543 struct drm_device
*dev
= connector
->dev
;
4544 enum drm_connector_status status
;
4545 enum intel_display_power_domain power_domain
;
4549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4550 connector
->base
.id
, connector
->name
);
4551 intel_dp_unset_edid(intel_dp
);
4553 if (intel_dp
->is_mst
) {
4554 /* MST devices are disconnected from a monitor POV */
4555 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4556 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4557 return connector_status_disconnected
;
4560 power_domain
= intel_dp_power_get(intel_dp
);
4562 /* Can't disconnect eDP, but you can close the lid... */
4563 if (is_edp(intel_dp
))
4564 status
= edp_detect(intel_dp
);
4565 else if (HAS_PCH_SPLIT(dev
))
4566 status
= ironlake_dp_detect(intel_dp
);
4568 status
= g4x_dp_detect(intel_dp
);
4569 if (status
!= connector_status_connected
)
4572 intel_dp_probe_oui(intel_dp
);
4574 ret
= intel_dp_probe_mst(intel_dp
);
4576 /* if we are in MST mode then this connector
4577 won't appear connected or have anything with EDID on it */
4578 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4579 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4580 status
= connector_status_disconnected
;
4584 intel_dp_set_edid(intel_dp
);
4586 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4587 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4588 status
= connector_status_connected
;
4590 /* Try to read the source of the interrupt */
4591 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4592 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4593 /* Clear interrupt source */
4594 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4595 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4598 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4599 intel_dp_handle_test_request(intel_dp
);
4600 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4601 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4605 intel_dp_power_put(intel_dp
, power_domain
);
4610 intel_dp_force(struct drm_connector
*connector
)
4612 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4613 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4614 enum intel_display_power_domain power_domain
;
4616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4617 connector
->base
.id
, connector
->name
);
4618 intel_dp_unset_edid(intel_dp
);
4620 if (connector
->status
!= connector_status_connected
)
4623 power_domain
= intel_dp_power_get(intel_dp
);
4625 intel_dp_set_edid(intel_dp
);
4627 intel_dp_power_put(intel_dp
, power_domain
);
4629 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4630 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4633 static int intel_dp_get_modes(struct drm_connector
*connector
)
4635 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4638 edid
= intel_connector
->detect_edid
;
4640 int ret
= intel_connector_update_modes(connector
, edid
);
4645 /* if eDP has no EDID, fall back to fixed mode */
4646 if (is_edp(intel_attached_dp(connector
)) &&
4647 intel_connector
->panel
.fixed_mode
) {
4648 struct drm_display_mode
*mode
;
4650 mode
= drm_mode_duplicate(connector
->dev
,
4651 intel_connector
->panel
.fixed_mode
);
4653 drm_mode_probed_add(connector
, mode
);
4662 intel_dp_detect_audio(struct drm_connector
*connector
)
4664 bool has_audio
= false;
4667 edid
= to_intel_connector(connector
)->detect_edid
;
4669 has_audio
= drm_detect_monitor_audio(edid
);
4675 intel_dp_set_property(struct drm_connector
*connector
,
4676 struct drm_property
*property
,
4679 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4680 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4681 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4682 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4685 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4689 if (property
== dev_priv
->force_audio_property
) {
4693 if (i
== intel_dp
->force_audio
)
4696 intel_dp
->force_audio
= i
;
4698 if (i
== HDMI_AUDIO_AUTO
)
4699 has_audio
= intel_dp_detect_audio(connector
);
4701 has_audio
= (i
== HDMI_AUDIO_ON
);
4703 if (has_audio
== intel_dp
->has_audio
)
4706 intel_dp
->has_audio
= has_audio
;
4710 if (property
== dev_priv
->broadcast_rgb_property
) {
4711 bool old_auto
= intel_dp
->color_range_auto
;
4712 uint32_t old_range
= intel_dp
->color_range
;
4715 case INTEL_BROADCAST_RGB_AUTO
:
4716 intel_dp
->color_range_auto
= true;
4718 case INTEL_BROADCAST_RGB_FULL
:
4719 intel_dp
->color_range_auto
= false;
4720 intel_dp
->color_range
= 0;
4722 case INTEL_BROADCAST_RGB_LIMITED
:
4723 intel_dp
->color_range_auto
= false;
4724 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4730 if (old_auto
== intel_dp
->color_range_auto
&&
4731 old_range
== intel_dp
->color_range
)
4737 if (is_edp(intel_dp
) &&
4738 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4739 if (val
== DRM_MODE_SCALE_NONE
) {
4740 DRM_DEBUG_KMS("no scaling not supported\n");
4744 if (intel_connector
->panel
.fitting_mode
== val
) {
4745 /* the eDP scaling property is not changed */
4748 intel_connector
->panel
.fitting_mode
= val
;
4756 if (intel_encoder
->base
.crtc
)
4757 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4763 intel_dp_connector_destroy(struct drm_connector
*connector
)
4765 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4767 kfree(intel_connector
->detect_edid
);
4769 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4770 kfree(intel_connector
->edid
);
4772 /* Can't call is_edp() since the encoder may have been destroyed
4774 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4775 intel_panel_fini(&intel_connector
->panel
);
4777 drm_connector_cleanup(connector
);
4781 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4783 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4784 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4786 drm_dp_aux_unregister(&intel_dp
->aux
);
4787 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4788 if (is_edp(intel_dp
)) {
4789 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4791 * vdd might still be enabled do to the delayed vdd off.
4792 * Make sure vdd is actually turned off here.
4795 edp_panel_vdd_off_sync(intel_dp
);
4796 pps_unlock(intel_dp
);
4798 if (intel_dp
->edp_notifier
.notifier_call
) {
4799 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4800 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4803 drm_encoder_cleanup(encoder
);
4804 kfree(intel_dig_port
);
4807 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4809 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4811 if (!is_edp(intel_dp
))
4815 * vdd might still be enabled do to the delayed vdd off.
4816 * Make sure vdd is actually turned off here.
4818 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4820 edp_panel_vdd_off_sync(intel_dp
);
4821 pps_unlock(intel_dp
);
4824 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4826 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4827 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4829 enum intel_display_power_domain power_domain
;
4831 lockdep_assert_held(&dev_priv
->pps_mutex
);
4833 if (!edp_have_panel_vdd(intel_dp
))
4837 * The VDD bit needs a power domain reference, so if the bit is
4838 * already enabled when we boot or resume, grab this reference and
4839 * schedule a vdd off, so we don't hold on to the reference
4842 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4843 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4844 intel_display_power_get(dev_priv
, power_domain
);
4846 edp_panel_vdd_schedule_off(intel_dp
);
4849 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4851 struct intel_dp
*intel_dp
;
4853 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4856 intel_dp
= enc_to_intel_dp(encoder
);
4861 * Read out the current power sequencer assignment,
4862 * in case the BIOS did something with it.
4864 if (IS_VALLEYVIEW(encoder
->dev
))
4865 vlv_initial_power_sequencer_setup(intel_dp
);
4867 intel_edp_panel_vdd_sanitize(intel_dp
);
4869 pps_unlock(intel_dp
);
4872 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4873 .dpms
= drm_atomic_helper_connector_dpms
,
4874 .detect
= intel_dp_detect
,
4875 .force
= intel_dp_force
,
4876 .fill_modes
= drm_helper_probe_single_connector_modes
,
4877 .set_property
= intel_dp_set_property
,
4878 .atomic_get_property
= intel_connector_atomic_get_property
,
4879 .destroy
= intel_dp_connector_destroy
,
4880 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4881 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4884 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4885 .get_modes
= intel_dp_get_modes
,
4886 .mode_valid
= intel_dp_mode_valid
,
4887 .best_encoder
= intel_best_encoder
,
4890 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4891 .reset
= intel_dp_encoder_reset
,
4892 .destroy
= intel_dp_encoder_destroy
,
4896 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4898 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4899 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4900 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4902 enum intel_display_power_domain power_domain
;
4903 enum irqreturn ret
= IRQ_NONE
;
4905 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4906 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4908 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4910 * vdd off can generate a long pulse on eDP which
4911 * would require vdd on to handle it, and thus we
4912 * would end up in an endless cycle of
4913 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4915 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4916 port_name(intel_dig_port
->port
));
4920 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4921 port_name(intel_dig_port
->port
),
4922 long_hpd
? "long" : "short");
4924 power_domain
= intel_display_port_power_domain(intel_encoder
);
4925 intel_display_power_get(dev_priv
, power_domain
);
4928 /* indicate that we need to restart link training */
4929 intel_dp
->train_set_valid
= false;
4931 if (HAS_PCH_SPLIT(dev
)) {
4932 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4935 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4939 if (!intel_dp_get_dpcd(intel_dp
)) {
4943 intel_dp_probe_oui(intel_dp
);
4945 if (!intel_dp_probe_mst(intel_dp
))
4949 if (intel_dp
->is_mst
) {
4950 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4954 if (!intel_dp
->is_mst
) {
4956 * we'll check the link status via the normal hot plug path later -
4957 * but for short hpds we should check it now
4959 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4960 intel_dp_check_link_status(intel_dp
);
4961 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4969 /* if we were in MST mode, and device is not there get out of MST mode */
4970 if (intel_dp
->is_mst
) {
4971 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4972 intel_dp
->is_mst
= false;
4973 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4976 intel_display_power_put(dev_priv
, power_domain
);
4981 /* Return which DP Port should be selected for Transcoder DP control */
4983 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4985 struct drm_device
*dev
= crtc
->dev
;
4986 struct intel_encoder
*intel_encoder
;
4987 struct intel_dp
*intel_dp
;
4989 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4990 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4992 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4993 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4994 return intel_dp
->output_reg
;
5000 /* check the VBT to see whether the eDP is on DP-D port */
5001 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
5003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5004 union child_device_config
*p_child
;
5006 static const short port_mapping
[] = {
5007 [PORT_B
] = PORT_IDPB
,
5008 [PORT_C
] = PORT_IDPC
,
5009 [PORT_D
] = PORT_IDPD
,
5015 if (!dev_priv
->vbt
.child_dev_num
)
5018 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
5019 p_child
= dev_priv
->vbt
.child_dev
+ i
;
5021 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
5022 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
5023 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
5030 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
5032 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
5034 intel_attach_force_audio_property(connector
);
5035 intel_attach_broadcast_rgb_property(connector
);
5036 intel_dp
->color_range_auto
= true;
5038 if (is_edp(intel_dp
)) {
5039 drm_mode_create_scaling_mode_property(connector
->dev
);
5040 drm_object_attach_property(
5042 connector
->dev
->mode_config
.scaling_mode_property
,
5043 DRM_MODE_SCALE_ASPECT
);
5044 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
5048 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
5050 intel_dp
->last_power_cycle
= jiffies
;
5051 intel_dp
->last_power_on
= jiffies
;
5052 intel_dp
->last_backlight_off
= jiffies
;
5056 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
5057 struct intel_dp
*intel_dp
)
5059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5060 struct edp_power_seq cur
, vbt
, spec
,
5061 *final
= &intel_dp
->pps_delays
;
5062 u32 pp_on
, pp_off
, pp_div
= 0, pp_ctl
= 0;
5063 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
= 0;
5065 lockdep_assert_held(&dev_priv
->pps_mutex
);
5067 /* already initialized? */
5068 if (final
->t11_t12
!= 0)
5071 if (IS_BROXTON(dev
)) {
5073 * TODO: BXT has 2 sets of PPS registers.
5074 * Correct Register for Broxton need to be identified
5075 * using VBT. hardcoding for now
5077 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5078 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5079 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5080 } else if (HAS_PCH_SPLIT(dev
)) {
5081 pp_ctrl_reg
= PCH_PP_CONTROL
;
5082 pp_on_reg
= PCH_PP_ON_DELAYS
;
5083 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5084 pp_div_reg
= PCH_PP_DIVISOR
;
5086 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5088 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
5089 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5090 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5091 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5094 /* Workaround: Need to write PP_CONTROL with the unlock key as
5095 * the very first thing. */
5096 pp_ctl
= ironlake_get_pp_control(intel_dp
);
5098 pp_on
= I915_READ(pp_on_reg
);
5099 pp_off
= I915_READ(pp_off_reg
);
5100 if (!IS_BROXTON(dev
)) {
5101 I915_WRITE(pp_ctrl_reg
, pp_ctl
);
5102 pp_div
= I915_READ(pp_div_reg
);
5105 /* Pull timing values out of registers */
5106 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
5107 PANEL_POWER_UP_DELAY_SHIFT
;
5109 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
5110 PANEL_LIGHT_ON_DELAY_SHIFT
;
5112 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
5113 PANEL_LIGHT_OFF_DELAY_SHIFT
;
5115 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5116 PANEL_POWER_DOWN_DELAY_SHIFT
;
5118 if (IS_BROXTON(dev
)) {
5119 u16 tmp
= (pp_ctl
& BXT_POWER_CYCLE_DELAY_MASK
) >>
5120 BXT_POWER_CYCLE_DELAY_SHIFT
;
5122 cur
.t11_t12
= (tmp
- 1) * 1000;
5126 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5127 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5130 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5131 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5133 vbt
= dev_priv
->vbt
.edp_pps
;
5135 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5136 * our hw here, which are all in 100usec. */
5137 spec
.t1_t3
= 210 * 10;
5138 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5139 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5140 spec
.t10
= 500 * 10;
5141 /* This one is special and actually in units of 100ms, but zero
5142 * based in the hw (so we need to add 100 ms). But the sw vbt
5143 * table multiplies it with 1000 to make it in units of 100usec,
5145 spec
.t11_t12
= (510 + 100) * 10;
5147 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5148 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5150 /* Use the max of the register settings and vbt. If both are
5151 * unset, fall back to the spec limits. */
5152 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5154 max(cur.field, vbt.field))
5155 assign_final(t1_t3
);
5159 assign_final(t11_t12
);
5162 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5163 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5164 intel_dp
->backlight_on_delay
= get_delay(t8
);
5165 intel_dp
->backlight_off_delay
= get_delay(t9
);
5166 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5167 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5170 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5171 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5172 intel_dp
->panel_power_cycle_delay
);
5174 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5175 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5179 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5180 struct intel_dp
*intel_dp
)
5182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5183 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5184 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5185 int pp_on_reg
, pp_off_reg
, pp_div_reg
= 0, pp_ctrl_reg
;
5186 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5187 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5189 lockdep_assert_held(&dev_priv
->pps_mutex
);
5191 if (IS_BROXTON(dev
)) {
5193 * TODO: BXT has 2 sets of PPS registers.
5194 * Correct Register for Broxton need to be identified
5195 * using VBT. hardcoding for now
5197 pp_ctrl_reg
= BXT_PP_CONTROL(0);
5198 pp_on_reg
= BXT_PP_ON_DELAYS(0);
5199 pp_off_reg
= BXT_PP_OFF_DELAYS(0);
5201 } else if (HAS_PCH_SPLIT(dev
)) {
5202 pp_on_reg
= PCH_PP_ON_DELAYS
;
5203 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5204 pp_div_reg
= PCH_PP_DIVISOR
;
5206 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5208 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5209 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5210 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5214 * And finally store the new values in the power sequencer. The
5215 * backlight delays are set to 1 because we do manual waits on them. For
5216 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5217 * we'll end up waiting for the backlight off delay twice: once when we
5218 * do the manual sleep, and once when we disable the panel and wait for
5219 * the PP_STATUS bit to become zero.
5221 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5222 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5223 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5224 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5225 /* Compute the divisor for the pp clock, simply match the Bspec
5227 if (IS_BROXTON(dev
)) {
5228 pp_div
= I915_READ(pp_ctrl_reg
);
5229 pp_div
&= ~BXT_POWER_CYCLE_DELAY_MASK
;
5230 pp_div
|= (DIV_ROUND_UP((seq
->t11_t12
+ 1), 1000)
5231 << BXT_POWER_CYCLE_DELAY_SHIFT
);
5233 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5234 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5235 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5238 /* Haswell doesn't have any port selection bits for the panel
5239 * power sequencer any more. */
5240 if (IS_VALLEYVIEW(dev
)) {
5241 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5242 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5244 port_sel
= PANEL_PORT_SELECT_DPA
;
5246 port_sel
= PANEL_PORT_SELECT_DPD
;
5251 I915_WRITE(pp_on_reg
, pp_on
);
5252 I915_WRITE(pp_off_reg
, pp_off
);
5253 if (IS_BROXTON(dev
))
5254 I915_WRITE(pp_ctrl_reg
, pp_div
);
5256 I915_WRITE(pp_div_reg
, pp_div
);
5258 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5259 I915_READ(pp_on_reg
),
5260 I915_READ(pp_off_reg
),
5262 (I915_READ(pp_ctrl_reg
) & BXT_POWER_CYCLE_DELAY_MASK
) :
5263 I915_READ(pp_div_reg
));
5267 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5269 * @refresh_rate: RR to be programmed
5271 * This function gets called when refresh rate (RR) has to be changed from
5272 * one frequency to another. Switches can be between high and low RR
5273 * supported by the panel or to any other RR based on media playback (in
5274 * this case, RR value needs to be passed from user space).
5276 * The caller of this function needs to take a lock on dev_priv->drrs.
5278 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5281 struct intel_encoder
*encoder
;
5282 struct intel_digital_port
*dig_port
= NULL
;
5283 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5284 struct intel_crtc_state
*config
= NULL
;
5285 struct intel_crtc
*intel_crtc
= NULL
;
5287 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5289 if (refresh_rate
<= 0) {
5290 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5294 if (intel_dp
== NULL
) {
5295 DRM_DEBUG_KMS("DRRS not supported.\n");
5300 * FIXME: This needs proper synchronization with psr state for some
5301 * platforms that cannot have PSR and DRRS enabled at the same time.
5304 dig_port
= dp_to_dig_port(intel_dp
);
5305 encoder
= &dig_port
->base
;
5306 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5309 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5313 config
= intel_crtc
->config
;
5315 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5316 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5320 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5322 index
= DRRS_LOW_RR
;
5324 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5326 "DRRS requested for previously set RR...ignoring\n");
5330 if (!intel_crtc
->active
) {
5331 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5335 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5338 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5341 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5345 DRM_ERROR("Unsupported refreshrate type\n");
5347 } else if (INTEL_INFO(dev
)->gen
> 6) {
5348 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5349 val
= I915_READ(reg
);
5351 if (index
> DRRS_HIGH_RR
) {
5352 if (IS_VALLEYVIEW(dev
))
5353 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5355 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5357 if (IS_VALLEYVIEW(dev
))
5358 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5360 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5362 I915_WRITE(reg
, val
);
5365 dev_priv
->drrs
.refresh_rate_type
= index
;
5367 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5371 * intel_edp_drrs_enable - init drrs struct if supported
5372 * @intel_dp: DP struct
5374 * Initializes frontbuffer_bits and drrs.dp
5376 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5378 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5380 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5381 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5384 if (!intel_crtc
->config
->has_drrs
) {
5385 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5389 mutex_lock(&dev_priv
->drrs
.mutex
);
5390 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5391 DRM_ERROR("DRRS already enabled\n");
5395 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5397 dev_priv
->drrs
.dp
= intel_dp
;
5400 mutex_unlock(&dev_priv
->drrs
.mutex
);
5404 * intel_edp_drrs_disable - Disable DRRS
5405 * @intel_dp: DP struct
5408 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5410 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5412 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5413 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5416 if (!intel_crtc
->config
->has_drrs
)
5419 mutex_lock(&dev_priv
->drrs
.mutex
);
5420 if (!dev_priv
->drrs
.dp
) {
5421 mutex_unlock(&dev_priv
->drrs
.mutex
);
5425 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5426 intel_dp_set_drrs_state(dev_priv
->dev
,
5427 intel_dp
->attached_connector
->panel
.
5428 fixed_mode
->vrefresh
);
5430 dev_priv
->drrs
.dp
= NULL
;
5431 mutex_unlock(&dev_priv
->drrs
.mutex
);
5433 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5436 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5438 struct drm_i915_private
*dev_priv
=
5439 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5440 struct intel_dp
*intel_dp
;
5442 mutex_lock(&dev_priv
->drrs
.mutex
);
5444 intel_dp
= dev_priv
->drrs
.dp
;
5450 * The delayed work can race with an invalidate hence we need to
5454 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5457 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5458 intel_dp_set_drrs_state(dev_priv
->dev
,
5459 intel_dp
->attached_connector
->panel
.
5460 downclock_mode
->vrefresh
);
5463 mutex_unlock(&dev_priv
->drrs
.mutex
);
5467 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5469 * @frontbuffer_bits: frontbuffer plane tracking bits
5471 * This function gets called everytime rendering on the given planes start.
5472 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5474 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5476 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5477 unsigned frontbuffer_bits
)
5479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5480 struct drm_crtc
*crtc
;
5483 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5486 cancel_delayed_work(&dev_priv
->drrs
.work
);
5488 mutex_lock(&dev_priv
->drrs
.mutex
);
5489 if (!dev_priv
->drrs
.dp
) {
5490 mutex_unlock(&dev_priv
->drrs
.mutex
);
5494 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5495 pipe
= to_intel_crtc(crtc
)->pipe
;
5497 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5498 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5500 /* invalidate means busy screen hence upclock */
5501 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5502 intel_dp_set_drrs_state(dev_priv
->dev
,
5503 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5504 fixed_mode
->vrefresh
);
5506 mutex_unlock(&dev_priv
->drrs
.mutex
);
5510 * intel_edp_drrs_flush - Restart Idleness DRRS
5512 * @frontbuffer_bits: frontbuffer plane tracking bits
5514 * This function gets called every time rendering on the given planes has
5515 * completed or flip on a crtc is completed. So DRRS should be upclocked
5516 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5517 * if no other planes are dirty.
5519 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5521 void intel_edp_drrs_flush(struct drm_device
*dev
,
5522 unsigned frontbuffer_bits
)
5524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5525 struct drm_crtc
*crtc
;
5528 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5531 cancel_delayed_work(&dev_priv
->drrs
.work
);
5533 mutex_lock(&dev_priv
->drrs
.mutex
);
5534 if (!dev_priv
->drrs
.dp
) {
5535 mutex_unlock(&dev_priv
->drrs
.mutex
);
5539 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5540 pipe
= to_intel_crtc(crtc
)->pipe
;
5542 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5543 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5545 /* flush means busy screen hence upclock */
5546 if (frontbuffer_bits
&& dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5547 intel_dp_set_drrs_state(dev_priv
->dev
,
5548 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5549 fixed_mode
->vrefresh
);
5552 * flush also means no more activity hence schedule downclock, if all
5553 * other fbs are quiescent too
5555 if (!dev_priv
->drrs
.busy_frontbuffer_bits
)
5556 schedule_delayed_work(&dev_priv
->drrs
.work
,
5557 msecs_to_jiffies(1000));
5558 mutex_unlock(&dev_priv
->drrs
.mutex
);
5562 * DOC: Display Refresh Rate Switching (DRRS)
5564 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5565 * which enables swtching between low and high refresh rates,
5566 * dynamically, based on the usage scenario. This feature is applicable
5567 * for internal panels.
5569 * Indication that the panel supports DRRS is given by the panel EDID, which
5570 * would list multiple refresh rates for one resolution.
5572 * DRRS is of 2 types - static and seamless.
5573 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5574 * (may appear as a blink on screen) and is used in dock-undock scenario.
5575 * Seamless DRRS involves changing RR without any visual effect to the user
5576 * and can be used during normal system usage. This is done by programming
5577 * certain registers.
5579 * Support for static/seamless DRRS may be indicated in the VBT based on
5580 * inputs from the panel spec.
5582 * DRRS saves power by switching to low RR based on usage scenarios.
5585 * The implementation is based on frontbuffer tracking implementation.
5586 * When there is a disturbance on the screen triggered by user activity or a
5587 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5588 * When there is no movement on screen, after a timeout of 1 second, a switch
5589 * to low RR is made.
5590 * For integration with frontbuffer tracking code,
5591 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5593 * DRRS can be further extended to support other internal panels and also
5594 * the scenario of video playback wherein RR is set based on the rate
5595 * requested by userspace.
5599 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5600 * @intel_connector: eDP connector
5601 * @fixed_mode: preferred mode of panel
5603 * This function is called only once at driver load to initialize basic
5607 * Downclock mode if panel supports it, else return NULL.
5608 * DRRS support is determined by the presence of downclock mode (apart
5609 * from VBT setting).
5611 static struct drm_display_mode
*
5612 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5613 struct drm_display_mode
*fixed_mode
)
5615 struct drm_connector
*connector
= &intel_connector
->base
;
5616 struct drm_device
*dev
= connector
->dev
;
5617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5618 struct drm_display_mode
*downclock_mode
= NULL
;
5620 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5621 mutex_init(&dev_priv
->drrs
.mutex
);
5623 if (INTEL_INFO(dev
)->gen
<= 6) {
5624 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5628 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5629 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5633 downclock_mode
= intel_find_panel_downclock
5634 (dev
, fixed_mode
, connector
);
5636 if (!downclock_mode
) {
5637 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5641 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5643 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5644 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5645 return downclock_mode
;
5648 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5649 struct intel_connector
*intel_connector
)
5651 struct drm_connector
*connector
= &intel_connector
->base
;
5652 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5653 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5654 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5656 struct drm_display_mode
*fixed_mode
= NULL
;
5657 struct drm_display_mode
*downclock_mode
= NULL
;
5659 struct drm_display_mode
*scan
;
5661 enum pipe pipe
= INVALID_PIPE
;
5663 if (!is_edp(intel_dp
))
5667 intel_edp_panel_vdd_sanitize(intel_dp
);
5668 pps_unlock(intel_dp
);
5670 /* Cache DPCD and EDID for edp. */
5671 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5674 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5675 dev_priv
->no_aux_handshake
=
5676 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5677 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5679 /* if this fails, presume the device is a ghost */
5680 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5684 /* We now know it's not a ghost, init power sequence regs. */
5686 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5687 pps_unlock(intel_dp
);
5689 mutex_lock(&dev
->mode_config
.mutex
);
5690 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5692 if (drm_add_edid_modes(connector
, edid
)) {
5693 drm_mode_connector_update_edid_property(connector
,
5695 drm_edid_to_eld(connector
, edid
);
5698 edid
= ERR_PTR(-EINVAL
);
5701 edid
= ERR_PTR(-ENOENT
);
5703 intel_connector
->edid
= edid
;
5705 /* prefer fixed mode from EDID if available */
5706 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5707 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5708 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5709 downclock_mode
= intel_dp_drrs_init(
5710 intel_connector
, fixed_mode
);
5715 /* fallback to VBT if available for eDP */
5716 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5717 fixed_mode
= drm_mode_duplicate(dev
,
5718 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5720 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5722 mutex_unlock(&dev
->mode_config
.mutex
);
5724 if (IS_VALLEYVIEW(dev
)) {
5725 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5726 register_reboot_notifier(&intel_dp
->edp_notifier
);
5729 * Figure out the current pipe for the initial backlight setup.
5730 * If the current pipe isn't valid, try the PPS pipe, and if that
5731 * fails just assume pipe A.
5733 if (IS_CHERRYVIEW(dev
))
5734 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5736 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5738 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5739 pipe
= intel_dp
->pps_pipe
;
5741 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5744 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5748 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5749 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5750 intel_panel_setup_backlight(connector
, pipe
);
5756 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5757 struct intel_connector
*intel_connector
)
5759 struct drm_connector
*connector
= &intel_connector
->base
;
5760 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5761 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5762 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5764 enum port port
= intel_dig_port
->port
;
5767 intel_dp
->pps_pipe
= INVALID_PIPE
;
5769 /* intel_dp vfuncs */
5770 if (INTEL_INFO(dev
)->gen
>= 9)
5771 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5772 else if (IS_VALLEYVIEW(dev
))
5773 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5774 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5775 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5776 else if (HAS_PCH_SPLIT(dev
))
5777 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5779 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5781 if (INTEL_INFO(dev
)->gen
>= 9)
5782 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5784 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5786 /* Preserve the current hw state. */
5787 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5788 intel_dp
->attached_connector
= intel_connector
;
5790 if (intel_dp_is_edp(dev
, port
))
5791 type
= DRM_MODE_CONNECTOR_eDP
;
5793 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5796 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5797 * for DP the encoder type can be set by the caller to
5798 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5800 if (type
== DRM_MODE_CONNECTOR_eDP
)
5801 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5803 /* eDP only on port B and/or C on vlv/chv */
5804 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5805 port
!= PORT_B
&& port
!= PORT_C
))
5808 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5809 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5812 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5813 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5815 connector
->interlace_allowed
= true;
5816 connector
->doublescan_allowed
= 0;
5818 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5819 edp_panel_vdd_work
);
5821 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5822 drm_connector_register(connector
);
5825 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5827 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5828 intel_connector
->unregister
= intel_dp_connector_unregister
;
5830 /* Set up the hotplug pin. */
5833 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5836 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5839 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5842 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5848 if (is_edp(intel_dp
)) {
5850 intel_dp_init_panel_power_timestamps(intel_dp
);
5851 if (IS_VALLEYVIEW(dev
))
5852 vlv_initial_power_sequencer_setup(intel_dp
);
5854 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5855 pps_unlock(intel_dp
);
5858 intel_dp_aux_init(intel_dp
, intel_connector
);
5860 /* init MST on ports that can support it */
5861 if (HAS_DP_MST(dev
) &&
5862 (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
))
5863 intel_dp_mst_encoder_init(intel_dig_port
,
5864 intel_connector
->base
.base
.id
);
5866 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5867 drm_dp_aux_unregister(&intel_dp
->aux
);
5868 if (is_edp(intel_dp
)) {
5869 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5871 * vdd might still be enabled do to the delayed vdd off.
5872 * Make sure vdd is actually turned off here.
5875 edp_panel_vdd_off_sync(intel_dp
);
5876 pps_unlock(intel_dp
);
5878 drm_connector_unregister(connector
);
5879 drm_connector_cleanup(connector
);
5883 intel_dp_add_properties(intel_dp
, connector
);
5885 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5886 * 0xd. Failure to do so will result in spurious interrupts being
5887 * generated on the port when a cable is not attached.
5889 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5890 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5891 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5894 i915_debugfs_connector_add(connector
);
5900 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5903 struct intel_digital_port
*intel_dig_port
;
5904 struct intel_encoder
*intel_encoder
;
5905 struct drm_encoder
*encoder
;
5906 struct intel_connector
*intel_connector
;
5908 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5909 if (!intel_dig_port
)
5912 intel_connector
= intel_connector_alloc();
5913 if (!intel_connector
) {
5914 kfree(intel_dig_port
);
5918 intel_encoder
= &intel_dig_port
->base
;
5919 encoder
= &intel_encoder
->base
;
5921 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5922 DRM_MODE_ENCODER_TMDS
);
5924 intel_encoder
->compute_config
= intel_dp_compute_config
;
5925 intel_encoder
->disable
= intel_disable_dp
;
5926 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5927 intel_encoder
->get_config
= intel_dp_get_config
;
5928 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5929 if (IS_CHERRYVIEW(dev
)) {
5930 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5931 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5932 intel_encoder
->enable
= vlv_enable_dp
;
5933 intel_encoder
->post_disable
= chv_post_disable_dp
;
5934 } else if (IS_VALLEYVIEW(dev
)) {
5935 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5936 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5937 intel_encoder
->enable
= vlv_enable_dp
;
5938 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5940 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5941 intel_encoder
->enable
= g4x_enable_dp
;
5942 if (INTEL_INFO(dev
)->gen
>= 5)
5943 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5946 intel_dig_port
->port
= port
;
5947 intel_dig_port
->dp
.output_reg
= output_reg
;
5949 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5950 if (IS_CHERRYVIEW(dev
)) {
5952 intel_encoder
->crtc_mask
= 1 << 2;
5954 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5956 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5958 intel_encoder
->cloneable
= 0;
5960 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5961 dev_priv
->hotplug
.irq_port
[port
] = intel_dig_port
;
5963 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5964 drm_encoder_cleanup(encoder
);
5965 kfree(intel_dig_port
);
5966 kfree(intel_connector
);
5970 void intel_dp_mst_suspend(struct drm_device
*dev
)
5972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5976 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5977 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5978 if (!intel_dig_port
)
5981 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5982 if (!intel_dig_port
->dp
.can_mst
)
5984 if (intel_dig_port
->dp
.is_mst
)
5985 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5990 void intel_dp_mst_resume(struct drm_device
*dev
)
5992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5995 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5996 struct intel_digital_port
*intel_dig_port
= dev_priv
->hotplug
.irq_port
[i
];
5997 if (!intel_dig_port
)
5999 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
6002 if (!intel_dig_port
->dp
.can_mst
)
6005 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
6007 intel_dp_check_mst_status(&intel_dig_port
->dp
);