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drm/i915: implement Haswell DP link train sequence
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "drm_crtc_helper.h"
35 #include "drm_edid.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44 /**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51 static bool is_edp(struct intel_dp *intel_dp)
52 {
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54 }
55
56 /**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64 static bool is_pch_edp(struct intel_dp *intel_dp)
65 {
66 return intel_dp->is_pch_edp;
67 }
68
69 /**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 {
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78 }
79
80 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81 {
82 return container_of(intel_attached_encoder(connector),
83 struct intel_dp, base);
84 }
85
86 /**
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
89 *
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 * by intel_display.c.
92 */
93 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94 {
95 struct intel_dp *intel_dp;
96
97 if (!encoder)
98 return false;
99
100 intel_dp = enc_to_intel_dp(encoder);
101
102 return is_pch_edp(intel_dp);
103 }
104
105 static void intel_dp_link_down(struct intel_dp *intel_dp);
106
107 void
108 intel_edp_link_config(struct intel_encoder *intel_encoder,
109 int *lane_num, int *link_bw)
110 {
111 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
112
113 *lane_num = intel_dp->lane_count;
114 if (intel_dp->link_bw == DP_LINK_BW_1_62)
115 *link_bw = 162000;
116 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
117 *link_bw = 270000;
118 }
119
120 int
121 intel_edp_target_clock(struct intel_encoder *intel_encoder,
122 struct drm_display_mode *mode)
123 {
124 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
125
126 if (intel_dp->panel_fixed_mode)
127 return intel_dp->panel_fixed_mode->clock;
128 else
129 return mode->clock;
130 }
131
132 static int
133 intel_dp_max_lane_count(struct intel_dp *intel_dp)
134 {
135 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
136 switch (max_lane_count) {
137 case 1: case 2: case 4:
138 break;
139 default:
140 max_lane_count = 4;
141 }
142 return max_lane_count;
143 }
144
145 static int
146 intel_dp_max_link_bw(struct intel_dp *intel_dp)
147 {
148 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
149
150 switch (max_link_bw) {
151 case DP_LINK_BW_1_62:
152 case DP_LINK_BW_2_7:
153 break;
154 default:
155 max_link_bw = DP_LINK_BW_1_62;
156 break;
157 }
158 return max_link_bw;
159 }
160
161 static int
162 intel_dp_link_clock(uint8_t link_bw)
163 {
164 if (link_bw == DP_LINK_BW_2_7)
165 return 270000;
166 else
167 return 162000;
168 }
169
170 /*
171 * The units on the numbers in the next two are... bizarre. Examples will
172 * make it clearer; this one parallels an example in the eDP spec.
173 *
174 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 *
176 * 270000 * 1 * 8 / 10 == 216000
177 *
178 * The actual data capacity of that configuration is 2.16Gbit/s, so the
179 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
180 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
181 * 119000. At 18bpp that's 2142000 kilobits per second.
182 *
183 * Thus the strange-looking division by 10 in intel_dp_link_required, to
184 * get the result in decakilobits instead of kilobits.
185 */
186
187 static int
188 intel_dp_link_required(int pixel_clock, int bpp)
189 {
190 return (pixel_clock * bpp + 9) / 10;
191 }
192
193 static int
194 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
195 {
196 return (max_link_clock * max_lanes * 8) / 10;
197 }
198
199 static bool
200 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
201 struct drm_display_mode *mode,
202 bool adjust_mode)
203 {
204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
205 int max_lanes = intel_dp_max_lane_count(intel_dp);
206 int max_rate, mode_rate;
207
208 mode_rate = intel_dp_link_required(mode->clock, 24);
209 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
210
211 if (mode_rate > max_rate) {
212 mode_rate = intel_dp_link_required(mode->clock, 18);
213 if (mode_rate > max_rate)
214 return false;
215
216 if (adjust_mode)
217 mode->private_flags
218 |= INTEL_MODE_DP_FORCE_6BPC;
219
220 return true;
221 }
222
223 return true;
224 }
225
226 static int
227 intel_dp_mode_valid(struct drm_connector *connector,
228 struct drm_display_mode *mode)
229 {
230 struct intel_dp *intel_dp = intel_attached_dp(connector);
231
232 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
233 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
234 return MODE_PANEL;
235
236 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
237 return MODE_PANEL;
238 }
239
240 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
241 return MODE_CLOCK_HIGH;
242
243 if (mode->clock < 10000)
244 return MODE_CLOCK_LOW;
245
246 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
247 return MODE_H_ILLEGAL;
248
249 return MODE_OK;
250 }
251
252 static uint32_t
253 pack_aux(uint8_t *src, int src_bytes)
254 {
255 int i;
256 uint32_t v = 0;
257
258 if (src_bytes > 4)
259 src_bytes = 4;
260 for (i = 0; i < src_bytes; i++)
261 v |= ((uint32_t) src[i]) << ((3-i) * 8);
262 return v;
263 }
264
265 static void
266 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
267 {
268 int i;
269 if (dst_bytes > 4)
270 dst_bytes = 4;
271 for (i = 0; i < dst_bytes; i++)
272 dst[i] = src >> ((3-i) * 8);
273 }
274
275 /* hrawclock is 1/4 the FSB frequency */
276 static int
277 intel_hrawclk(struct drm_device *dev)
278 {
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 uint32_t clkcfg;
281
282 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
283 if (IS_VALLEYVIEW(dev))
284 return 200;
285
286 clkcfg = I915_READ(CLKCFG);
287 switch (clkcfg & CLKCFG_FSB_MASK) {
288 case CLKCFG_FSB_400:
289 return 100;
290 case CLKCFG_FSB_533:
291 return 133;
292 case CLKCFG_FSB_667:
293 return 166;
294 case CLKCFG_FSB_800:
295 return 200;
296 case CLKCFG_FSB_1067:
297 return 266;
298 case CLKCFG_FSB_1333:
299 return 333;
300 /* these two are just a guess; one of them might be right */
301 case CLKCFG_FSB_1600:
302 case CLKCFG_FSB_1600_ALT:
303 return 400;
304 default:
305 return 133;
306 }
307 }
308
309 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
310 {
311 struct drm_device *dev = intel_dp->base.base.dev;
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
315 }
316
317 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
318 {
319 struct drm_device *dev = intel_dp->base.base.dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
321
322 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
323 }
324
325 static void
326 intel_dp_check_edp(struct intel_dp *intel_dp)
327 {
328 struct drm_device *dev = intel_dp->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330
331 if (!is_edp(intel_dp))
332 return;
333 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
334 WARN(1, "eDP powered off while attempting aux channel communication.\n");
335 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
336 I915_READ(PCH_PP_STATUS),
337 I915_READ(PCH_PP_CONTROL));
338 }
339 }
340
341 static int
342 intel_dp_aux_ch(struct intel_dp *intel_dp,
343 uint8_t *send, int send_bytes,
344 uint8_t *recv, int recv_size)
345 {
346 uint32_t output_reg = intel_dp->output_reg;
347 struct drm_device *dev = intel_dp->base.base.dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 uint32_t ch_ctl = output_reg + 0x10;
350 uint32_t ch_data = ch_ctl + 4;
351 int i;
352 int recv_bytes;
353 uint32_t status;
354 uint32_t aux_clock_divider;
355 int try, precharge;
356
357 if (IS_HASWELL(dev)) {
358 switch (intel_dp->port) {
359 case PORT_A:
360 ch_ctl = DPA_AUX_CH_CTL;
361 ch_data = DPA_AUX_CH_DATA1;
362 break;
363 case PORT_B:
364 ch_ctl = PCH_DPB_AUX_CH_CTL;
365 ch_data = PCH_DPB_AUX_CH_DATA1;
366 break;
367 case PORT_C:
368 ch_ctl = PCH_DPC_AUX_CH_CTL;
369 ch_data = PCH_DPC_AUX_CH_DATA1;
370 break;
371 case PORT_D:
372 ch_ctl = PCH_DPD_AUX_CH_CTL;
373 ch_data = PCH_DPD_AUX_CH_DATA1;
374 break;
375 default:
376 BUG();
377 }
378 }
379
380 intel_dp_check_edp(intel_dp);
381 /* The clock divider is based off the hrawclk,
382 * and would like to run at 2MHz. So, take the
383 * hrawclk value and divide by 2 and use that
384 *
385 * Note that PCH attached eDP panels should use a 125MHz input
386 * clock divider.
387 */
388 if (is_cpu_edp(intel_dp)) {
389 if (IS_VALLEYVIEW(dev))
390 aux_clock_divider = 100;
391 else if (IS_GEN6(dev) || IS_GEN7(dev))
392 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
393 else
394 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
395 } else if (HAS_PCH_SPLIT(dev))
396 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
397 else
398 aux_clock_divider = intel_hrawclk(dev) / 2;
399
400 if (IS_GEN6(dev))
401 precharge = 3;
402 else
403 precharge = 5;
404
405 /* Try to wait for any previous AUX channel activity */
406 for (try = 0; try < 3; try++) {
407 status = I915_READ(ch_ctl);
408 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
409 break;
410 msleep(1);
411 }
412
413 if (try == 3) {
414 WARN(1, "dp_aux_ch not started status 0x%08x\n",
415 I915_READ(ch_ctl));
416 return -EBUSY;
417 }
418
419 /* Must try at least 3 times according to DP spec */
420 for (try = 0; try < 5; try++) {
421 /* Load the send data into the aux channel data registers */
422 for (i = 0; i < send_bytes; i += 4)
423 I915_WRITE(ch_data + i,
424 pack_aux(send + i, send_bytes - i));
425
426 /* Send the command and wait for it to complete */
427 I915_WRITE(ch_ctl,
428 DP_AUX_CH_CTL_SEND_BUSY |
429 DP_AUX_CH_CTL_TIME_OUT_400us |
430 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
431 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
432 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
433 DP_AUX_CH_CTL_DONE |
434 DP_AUX_CH_CTL_TIME_OUT_ERROR |
435 DP_AUX_CH_CTL_RECEIVE_ERROR);
436 for (;;) {
437 status = I915_READ(ch_ctl);
438 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
439 break;
440 udelay(100);
441 }
442
443 /* Clear done status and any errors */
444 I915_WRITE(ch_ctl,
445 status |
446 DP_AUX_CH_CTL_DONE |
447 DP_AUX_CH_CTL_TIME_OUT_ERROR |
448 DP_AUX_CH_CTL_RECEIVE_ERROR);
449
450 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
451 DP_AUX_CH_CTL_RECEIVE_ERROR))
452 continue;
453 if (status & DP_AUX_CH_CTL_DONE)
454 break;
455 }
456
457 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
458 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
459 return -EBUSY;
460 }
461
462 /* Check for timeout or receive error.
463 * Timeouts occur when the sink is not connected
464 */
465 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
466 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
467 return -EIO;
468 }
469
470 /* Timeouts occur when the device isn't connected, so they're
471 * "normal" -- don't fill the kernel log with these */
472 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
473 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
474 return -ETIMEDOUT;
475 }
476
477 /* Unload any bytes sent back from the other side */
478 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
479 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
480 if (recv_bytes > recv_size)
481 recv_bytes = recv_size;
482
483 for (i = 0; i < recv_bytes; i += 4)
484 unpack_aux(I915_READ(ch_data + i),
485 recv + i, recv_bytes - i);
486
487 return recv_bytes;
488 }
489
490 /* Write data to the aux channel in native mode */
491 static int
492 intel_dp_aux_native_write(struct intel_dp *intel_dp,
493 uint16_t address, uint8_t *send, int send_bytes)
494 {
495 int ret;
496 uint8_t msg[20];
497 int msg_bytes;
498 uint8_t ack;
499
500 intel_dp_check_edp(intel_dp);
501 if (send_bytes > 16)
502 return -1;
503 msg[0] = AUX_NATIVE_WRITE << 4;
504 msg[1] = address >> 8;
505 msg[2] = address & 0xff;
506 msg[3] = send_bytes - 1;
507 memcpy(&msg[4], send, send_bytes);
508 msg_bytes = send_bytes + 4;
509 for (;;) {
510 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
511 if (ret < 0)
512 return ret;
513 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
514 break;
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
516 udelay(100);
517 else
518 return -EIO;
519 }
520 return send_bytes;
521 }
522
523 /* Write a single byte to the aux channel in native mode */
524 static int
525 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
526 uint16_t address, uint8_t byte)
527 {
528 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
529 }
530
531 /* read bytes from a native aux channel */
532 static int
533 intel_dp_aux_native_read(struct intel_dp *intel_dp,
534 uint16_t address, uint8_t *recv, int recv_bytes)
535 {
536 uint8_t msg[4];
537 int msg_bytes;
538 uint8_t reply[20];
539 int reply_bytes;
540 uint8_t ack;
541 int ret;
542
543 intel_dp_check_edp(intel_dp);
544 msg[0] = AUX_NATIVE_READ << 4;
545 msg[1] = address >> 8;
546 msg[2] = address & 0xff;
547 msg[3] = recv_bytes - 1;
548
549 msg_bytes = 4;
550 reply_bytes = recv_bytes + 1;
551
552 for (;;) {
553 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
554 reply, reply_bytes);
555 if (ret == 0)
556 return -EPROTO;
557 if (ret < 0)
558 return ret;
559 ack = reply[0];
560 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
561 memcpy(recv, reply + 1, ret - 1);
562 return ret - 1;
563 }
564 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
565 udelay(100);
566 else
567 return -EIO;
568 }
569 }
570
571 static int
572 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
573 uint8_t write_byte, uint8_t *read_byte)
574 {
575 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
576 struct intel_dp *intel_dp = container_of(adapter,
577 struct intel_dp,
578 adapter);
579 uint16_t address = algo_data->address;
580 uint8_t msg[5];
581 uint8_t reply[2];
582 unsigned retry;
583 int msg_bytes;
584 int reply_bytes;
585 int ret;
586
587 intel_dp_check_edp(intel_dp);
588 /* Set up the command byte */
589 if (mode & MODE_I2C_READ)
590 msg[0] = AUX_I2C_READ << 4;
591 else
592 msg[0] = AUX_I2C_WRITE << 4;
593
594 if (!(mode & MODE_I2C_STOP))
595 msg[0] |= AUX_I2C_MOT << 4;
596
597 msg[1] = address >> 8;
598 msg[2] = address;
599
600 switch (mode) {
601 case MODE_I2C_WRITE:
602 msg[3] = 0;
603 msg[4] = write_byte;
604 msg_bytes = 5;
605 reply_bytes = 1;
606 break;
607 case MODE_I2C_READ:
608 msg[3] = 0;
609 msg_bytes = 4;
610 reply_bytes = 2;
611 break;
612 default:
613 msg_bytes = 3;
614 reply_bytes = 1;
615 break;
616 }
617
618 for (retry = 0; retry < 5; retry++) {
619 ret = intel_dp_aux_ch(intel_dp,
620 msg, msg_bytes,
621 reply, reply_bytes);
622 if (ret < 0) {
623 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
624 return ret;
625 }
626
627 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
628 case AUX_NATIVE_REPLY_ACK:
629 /* I2C-over-AUX Reply field is only valid
630 * when paired with AUX ACK.
631 */
632 break;
633 case AUX_NATIVE_REPLY_NACK:
634 DRM_DEBUG_KMS("aux_ch native nack\n");
635 return -EREMOTEIO;
636 case AUX_NATIVE_REPLY_DEFER:
637 udelay(100);
638 continue;
639 default:
640 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
641 reply[0]);
642 return -EREMOTEIO;
643 }
644
645 switch (reply[0] & AUX_I2C_REPLY_MASK) {
646 case AUX_I2C_REPLY_ACK:
647 if (mode == MODE_I2C_READ) {
648 *read_byte = reply[1];
649 }
650 return reply_bytes - 1;
651 case AUX_I2C_REPLY_NACK:
652 DRM_DEBUG_KMS("aux_i2c nack\n");
653 return -EREMOTEIO;
654 case AUX_I2C_REPLY_DEFER:
655 DRM_DEBUG_KMS("aux_i2c defer\n");
656 udelay(100);
657 break;
658 default:
659 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
660 return -EREMOTEIO;
661 }
662 }
663
664 DRM_ERROR("too many retries, giving up\n");
665 return -EREMOTEIO;
666 }
667
668 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
669 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
670
671 static int
672 intel_dp_i2c_init(struct intel_dp *intel_dp,
673 struct intel_connector *intel_connector, const char *name)
674 {
675 int ret;
676
677 DRM_DEBUG_KMS("i2c_init %s\n", name);
678 intel_dp->algo.running = false;
679 intel_dp->algo.address = 0;
680 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
681
682 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
683 intel_dp->adapter.owner = THIS_MODULE;
684 intel_dp->adapter.class = I2C_CLASS_DDC;
685 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
686 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
687 intel_dp->adapter.algo_data = &intel_dp->algo;
688 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
689
690 ironlake_edp_panel_vdd_on(intel_dp);
691 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
692 ironlake_edp_panel_vdd_off(intel_dp, false);
693 return ret;
694 }
695
696 static bool
697 intel_dp_mode_fixup(struct drm_encoder *encoder,
698 const struct drm_display_mode *mode,
699 struct drm_display_mode *adjusted_mode)
700 {
701 struct drm_device *dev = encoder->dev;
702 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
703 int lane_count, clock;
704 int max_lane_count = intel_dp_max_lane_count(intel_dp);
705 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
706 int bpp, mode_rate;
707 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
708
709 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
710 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
711 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
712 mode, adjusted_mode);
713 }
714
715 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
716 return false;
717
718 DRM_DEBUG_KMS("DP link computation with max lane count %i "
719 "max bw %02x pixel clock %iKHz\n",
720 max_lane_count, bws[max_clock], adjusted_mode->clock);
721
722 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
723 return false;
724
725 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
726 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
727
728 for (clock = 0; clock <= max_clock; clock++) {
729 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
730 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
731
732 if (mode_rate <= link_avail) {
733 intel_dp->link_bw = bws[clock];
734 intel_dp->lane_count = lane_count;
735 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
736 DRM_DEBUG_KMS("DP link bw %02x lane "
737 "count %d clock %d bpp %d\n",
738 intel_dp->link_bw, intel_dp->lane_count,
739 adjusted_mode->clock, bpp);
740 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
741 mode_rate, link_avail);
742 return true;
743 }
744 }
745 }
746
747 return false;
748 }
749
750 struct intel_dp_m_n {
751 uint32_t tu;
752 uint32_t gmch_m;
753 uint32_t gmch_n;
754 uint32_t link_m;
755 uint32_t link_n;
756 };
757
758 static void
759 intel_reduce_ratio(uint32_t *num, uint32_t *den)
760 {
761 while (*num > 0xffffff || *den > 0xffffff) {
762 *num >>= 1;
763 *den >>= 1;
764 }
765 }
766
767 static void
768 intel_dp_compute_m_n(int bpp,
769 int nlanes,
770 int pixel_clock,
771 int link_clock,
772 struct intel_dp_m_n *m_n)
773 {
774 m_n->tu = 64;
775 m_n->gmch_m = (pixel_clock * bpp) >> 3;
776 m_n->gmch_n = link_clock * nlanes;
777 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
778 m_n->link_m = pixel_clock;
779 m_n->link_n = link_clock;
780 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
781 }
782
783 void
784 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
785 struct drm_display_mode *adjusted_mode)
786 {
787 struct drm_device *dev = crtc->dev;
788 struct intel_encoder *encoder;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
791 int lane_count = 4;
792 struct intel_dp_m_n m_n;
793 int pipe = intel_crtc->pipe;
794
795 /*
796 * Find the lane count in the intel_encoder private
797 */
798 for_each_encoder_on_crtc(dev, crtc, encoder) {
799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
800
801 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
802 intel_dp->base.type == INTEL_OUTPUT_EDP)
803 {
804 lane_count = intel_dp->lane_count;
805 break;
806 }
807 }
808
809 /*
810 * Compute the GMCH and Link ratios. The '3' here is
811 * the number of bytes_per_pixel post-LUT, which we always
812 * set up for 8-bits of R/G/B, or 3 bytes total.
813 */
814 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
815 mode->clock, adjusted_mode->clock, &m_n);
816
817 if (IS_HASWELL(dev)) {
818 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
819 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
820 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
821 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
822 } else if (HAS_PCH_SPLIT(dev)) {
823 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
824 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
825 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
826 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
827 } else if (IS_VALLEYVIEW(dev)) {
828 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
829 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
830 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
831 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
832 } else {
833 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
834 TU_SIZE(m_n.tu) | m_n.gmch_m);
835 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
836 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
837 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
838 }
839 }
840
841 void intel_dp_init_link_config(struct intel_dp *intel_dp)
842 {
843 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
844 intel_dp->link_configuration[0] = intel_dp->link_bw;
845 intel_dp->link_configuration[1] = intel_dp->lane_count;
846 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
847 /*
848 * Check for DPCD version > 1.1 and enhanced framing support
849 */
850 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
851 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
852 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
853 }
854 }
855
856 static void
857 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
858 struct drm_display_mode *adjusted_mode)
859 {
860 struct drm_device *dev = encoder->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
863 struct drm_crtc *crtc = intel_dp->base.base.crtc;
864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
865
866 /*
867 * There are four kinds of DP registers:
868 *
869 * IBX PCH
870 * SNB CPU
871 * IVB CPU
872 * CPT PCH
873 *
874 * IBX PCH and CPU are the same for almost everything,
875 * except that the CPU DP PLL is configured in this
876 * register
877 *
878 * CPT PCH is quite different, having many bits moved
879 * to the TRANS_DP_CTL register instead. That
880 * configuration happens (oddly) in ironlake_pch_enable
881 */
882
883 /* Preserve the BIOS-computed detected bit. This is
884 * supposed to be read-only.
885 */
886 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
887
888 /* Handle DP bits in common between all three register formats */
889 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
890
891 switch (intel_dp->lane_count) {
892 case 1:
893 intel_dp->DP |= DP_PORT_WIDTH_1;
894 break;
895 case 2:
896 intel_dp->DP |= DP_PORT_WIDTH_2;
897 break;
898 case 4:
899 intel_dp->DP |= DP_PORT_WIDTH_4;
900 break;
901 }
902 if (intel_dp->has_audio) {
903 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
904 pipe_name(intel_crtc->pipe));
905 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
906 intel_write_eld(encoder, adjusted_mode);
907 }
908
909 intel_dp_init_link_config(intel_dp);
910
911 /* Split out the IBX/CPU vs CPT settings */
912
913 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
914 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
915 intel_dp->DP |= DP_SYNC_HS_HIGH;
916 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
917 intel_dp->DP |= DP_SYNC_VS_HIGH;
918 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
919
920 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
921 intel_dp->DP |= DP_ENHANCED_FRAMING;
922
923 intel_dp->DP |= intel_crtc->pipe << 29;
924
925 /* don't miss out required setting for eDP */
926 if (adjusted_mode->clock < 200000)
927 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
928 else
929 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
930 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
931 intel_dp->DP |= intel_dp->color_range;
932
933 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
934 intel_dp->DP |= DP_SYNC_HS_HIGH;
935 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
936 intel_dp->DP |= DP_SYNC_VS_HIGH;
937 intel_dp->DP |= DP_LINK_TRAIN_OFF;
938
939 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
940 intel_dp->DP |= DP_ENHANCED_FRAMING;
941
942 if (intel_crtc->pipe == 1)
943 intel_dp->DP |= DP_PIPEB_SELECT;
944
945 if (is_cpu_edp(intel_dp)) {
946 /* don't miss out required setting for eDP */
947 if (adjusted_mode->clock < 200000)
948 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
949 else
950 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
951 }
952 } else {
953 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
954 }
955 }
956
957 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
959
960 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
961 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
962
963 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
964 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
965
966 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
967 u32 mask,
968 u32 value)
969 {
970 struct drm_device *dev = intel_dp->base.base.dev;
971 struct drm_i915_private *dev_priv = dev->dev_private;
972
973 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
974 mask, value,
975 I915_READ(PCH_PP_STATUS),
976 I915_READ(PCH_PP_CONTROL));
977
978 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
979 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
980 I915_READ(PCH_PP_STATUS),
981 I915_READ(PCH_PP_CONTROL));
982 }
983 }
984
985 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
986 {
987 DRM_DEBUG_KMS("Wait for panel power on\n");
988 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
989 }
990
991 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
992 {
993 DRM_DEBUG_KMS("Wait for panel power off time\n");
994 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
995 }
996
997 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
998 {
999 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1000 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1001 }
1002
1003
1004 /* Read the current pp_control value, unlocking the register if it
1005 * is locked
1006 */
1007
1008 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1009 {
1010 u32 control = I915_READ(PCH_PP_CONTROL);
1011
1012 control &= ~PANEL_UNLOCK_MASK;
1013 control |= PANEL_UNLOCK_REGS;
1014 return control;
1015 }
1016
1017 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1018 {
1019 struct drm_device *dev = intel_dp->base.base.dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 u32 pp;
1022
1023 if (!is_edp(intel_dp))
1024 return;
1025 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1026
1027 WARN(intel_dp->want_panel_vdd,
1028 "eDP VDD already requested on\n");
1029
1030 intel_dp->want_panel_vdd = true;
1031
1032 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1033 DRM_DEBUG_KMS("eDP VDD already on\n");
1034 return;
1035 }
1036
1037 if (!ironlake_edp_have_panel_power(intel_dp))
1038 ironlake_wait_panel_power_cycle(intel_dp);
1039
1040 pp = ironlake_get_pp_control(dev_priv);
1041 pp |= EDP_FORCE_VDD;
1042 I915_WRITE(PCH_PP_CONTROL, pp);
1043 POSTING_READ(PCH_PP_CONTROL);
1044 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1045 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1046
1047 /*
1048 * If the panel wasn't on, delay before accessing aux channel
1049 */
1050 if (!ironlake_edp_have_panel_power(intel_dp)) {
1051 DRM_DEBUG_KMS("eDP was not running\n");
1052 msleep(intel_dp->panel_power_up_delay);
1053 }
1054 }
1055
1056 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1057 {
1058 struct drm_device *dev = intel_dp->base.base.dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 u32 pp;
1061
1062 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1063 pp = ironlake_get_pp_control(dev_priv);
1064 pp &= ~EDP_FORCE_VDD;
1065 I915_WRITE(PCH_PP_CONTROL, pp);
1066 POSTING_READ(PCH_PP_CONTROL);
1067
1068 /* Make sure sequencer is idle before allowing subsequent activity */
1069 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1070 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1071
1072 msleep(intel_dp->panel_power_down_delay);
1073 }
1074 }
1075
1076 static void ironlake_panel_vdd_work(struct work_struct *__work)
1077 {
1078 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1079 struct intel_dp, panel_vdd_work);
1080 struct drm_device *dev = intel_dp->base.base.dev;
1081
1082 mutex_lock(&dev->mode_config.mutex);
1083 ironlake_panel_vdd_off_sync(intel_dp);
1084 mutex_unlock(&dev->mode_config.mutex);
1085 }
1086
1087 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1088 {
1089 if (!is_edp(intel_dp))
1090 return;
1091
1092 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1093 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1094
1095 intel_dp->want_panel_vdd = false;
1096
1097 if (sync) {
1098 ironlake_panel_vdd_off_sync(intel_dp);
1099 } else {
1100 /*
1101 * Queue the timer to fire a long
1102 * time from now (relative to the power down delay)
1103 * to keep the panel power up across a sequence of operations
1104 */
1105 schedule_delayed_work(&intel_dp->panel_vdd_work,
1106 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1107 }
1108 }
1109
1110 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1111 {
1112 struct drm_device *dev = intel_dp->base.base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 u32 pp;
1115
1116 if (!is_edp(intel_dp))
1117 return;
1118
1119 DRM_DEBUG_KMS("Turn eDP power on\n");
1120
1121 if (ironlake_edp_have_panel_power(intel_dp)) {
1122 DRM_DEBUG_KMS("eDP power already on\n");
1123 return;
1124 }
1125
1126 ironlake_wait_panel_power_cycle(intel_dp);
1127
1128 pp = ironlake_get_pp_control(dev_priv);
1129 if (IS_GEN5(dev)) {
1130 /* ILK workaround: disable reset around power sequence */
1131 pp &= ~PANEL_POWER_RESET;
1132 I915_WRITE(PCH_PP_CONTROL, pp);
1133 POSTING_READ(PCH_PP_CONTROL);
1134 }
1135
1136 pp |= POWER_TARGET_ON;
1137 if (!IS_GEN5(dev))
1138 pp |= PANEL_POWER_RESET;
1139
1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
1142
1143 ironlake_wait_panel_on(intel_dp);
1144
1145 if (IS_GEN5(dev)) {
1146 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1147 I915_WRITE(PCH_PP_CONTROL, pp);
1148 POSTING_READ(PCH_PP_CONTROL);
1149 }
1150 }
1151
1152 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1153 {
1154 struct drm_device *dev = intel_dp->base.base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 pp;
1157
1158 if (!is_edp(intel_dp))
1159 return;
1160
1161 DRM_DEBUG_KMS("Turn eDP power off\n");
1162
1163 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1164
1165 pp = ironlake_get_pp_control(dev_priv);
1166 /* We need to switch off panel power _and_ force vdd, for otherwise some
1167 * panels get very unhappy and cease to work. */
1168 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1169 I915_WRITE(PCH_PP_CONTROL, pp);
1170 POSTING_READ(PCH_PP_CONTROL);
1171
1172 intel_dp->want_panel_vdd = false;
1173
1174 ironlake_wait_panel_off(intel_dp);
1175 }
1176
1177 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1178 {
1179 struct drm_device *dev = intel_dp->base.base.dev;
1180 struct drm_i915_private *dev_priv = dev->dev_private;
1181 u32 pp;
1182
1183 if (!is_edp(intel_dp))
1184 return;
1185
1186 DRM_DEBUG_KMS("\n");
1187 /*
1188 * If we enable the backlight right away following a panel power
1189 * on, we may see slight flicker as the panel syncs with the eDP
1190 * link. So delay a bit to make sure the image is solid before
1191 * allowing it to appear.
1192 */
1193 msleep(intel_dp->backlight_on_delay);
1194 pp = ironlake_get_pp_control(dev_priv);
1195 pp |= EDP_BLC_ENABLE;
1196 I915_WRITE(PCH_PP_CONTROL, pp);
1197 POSTING_READ(PCH_PP_CONTROL);
1198 }
1199
1200 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1201 {
1202 struct drm_device *dev = intel_dp->base.base.dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 u32 pp;
1205
1206 if (!is_edp(intel_dp))
1207 return;
1208
1209 DRM_DEBUG_KMS("\n");
1210 pp = ironlake_get_pp_control(dev_priv);
1211 pp &= ~EDP_BLC_ENABLE;
1212 I915_WRITE(PCH_PP_CONTROL, pp);
1213 POSTING_READ(PCH_PP_CONTROL);
1214 msleep(intel_dp->backlight_off_delay);
1215 }
1216
1217 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1218 {
1219 struct drm_device *dev = intel_dp->base.base.dev;
1220 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 u32 dpa_ctl;
1223
1224 assert_pipe_disabled(dev_priv,
1225 to_intel_crtc(crtc)->pipe);
1226
1227 DRM_DEBUG_KMS("\n");
1228 dpa_ctl = I915_READ(DP_A);
1229 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1230 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1231
1232 /* We don't adjust intel_dp->DP while tearing down the link, to
1233 * facilitate link retraining (e.g. after hotplug). Hence clear all
1234 * enable bits here to ensure that we don't enable too much. */
1235 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1236 intel_dp->DP |= DP_PLL_ENABLE;
1237 I915_WRITE(DP_A, intel_dp->DP);
1238 POSTING_READ(DP_A);
1239 udelay(200);
1240 }
1241
1242 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1243 {
1244 struct drm_device *dev = intel_dp->base.base.dev;
1245 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1246 struct drm_i915_private *dev_priv = dev->dev_private;
1247 u32 dpa_ctl;
1248
1249 assert_pipe_disabled(dev_priv,
1250 to_intel_crtc(crtc)->pipe);
1251
1252 dpa_ctl = I915_READ(DP_A);
1253 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1254 "dp pll off, should be on\n");
1255 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1256
1257 /* We can't rely on the value tracked for the DP register in
1258 * intel_dp->DP because link_down must not change that (otherwise link
1259 * re-training will fail. */
1260 dpa_ctl &= ~DP_PLL_ENABLE;
1261 I915_WRITE(DP_A, dpa_ctl);
1262 POSTING_READ(DP_A);
1263 udelay(200);
1264 }
1265
1266 /* If the sink supports it, try to set the power state appropriately */
1267 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1268 {
1269 int ret, i;
1270
1271 /* Should have a valid DPCD by this point */
1272 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1273 return;
1274
1275 if (mode != DRM_MODE_DPMS_ON) {
1276 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1277 DP_SET_POWER_D3);
1278 if (ret != 1)
1279 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1280 } else {
1281 /*
1282 * When turning on, we need to retry for 1ms to give the sink
1283 * time to wake up.
1284 */
1285 for (i = 0; i < 3; i++) {
1286 ret = intel_dp_aux_native_write_1(intel_dp,
1287 DP_SET_POWER,
1288 DP_SET_POWER_D0);
1289 if (ret == 1)
1290 break;
1291 msleep(1);
1292 }
1293 }
1294 }
1295
1296 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1297 enum pipe *pipe)
1298 {
1299 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1300 struct drm_device *dev = encoder->base.dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 u32 tmp = I915_READ(intel_dp->output_reg);
1303
1304 if (!(tmp & DP_PORT_EN))
1305 return false;
1306
1307 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1308 *pipe = PORT_TO_PIPE_CPT(tmp);
1309 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1310 *pipe = PORT_TO_PIPE(tmp);
1311 } else {
1312 u32 trans_sel;
1313 u32 trans_dp;
1314 int i;
1315
1316 switch (intel_dp->output_reg) {
1317 case PCH_DP_B:
1318 trans_sel = TRANS_DP_PORT_SEL_B;
1319 break;
1320 case PCH_DP_C:
1321 trans_sel = TRANS_DP_PORT_SEL_C;
1322 break;
1323 case PCH_DP_D:
1324 trans_sel = TRANS_DP_PORT_SEL_D;
1325 break;
1326 default:
1327 return true;
1328 }
1329
1330 for_each_pipe(i) {
1331 trans_dp = I915_READ(TRANS_DP_CTL(i));
1332 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1333 *pipe = i;
1334 return true;
1335 }
1336 }
1337 }
1338
1339 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1340
1341 return true;
1342 }
1343
1344 static void intel_disable_dp(struct intel_encoder *encoder)
1345 {
1346 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1347
1348 /* Make sure the panel is off before trying to change the mode. But also
1349 * ensure that we have vdd while we switch off the panel. */
1350 ironlake_edp_panel_vdd_on(intel_dp);
1351 ironlake_edp_backlight_off(intel_dp);
1352 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1353 ironlake_edp_panel_off(intel_dp);
1354
1355 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1356 if (!is_cpu_edp(intel_dp))
1357 intel_dp_link_down(intel_dp);
1358 }
1359
1360 static void intel_post_disable_dp(struct intel_encoder *encoder)
1361 {
1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1363
1364 if (is_cpu_edp(intel_dp)) {
1365 intel_dp_link_down(intel_dp);
1366 ironlake_edp_pll_off(intel_dp);
1367 }
1368 }
1369
1370 static void intel_enable_dp(struct intel_encoder *encoder)
1371 {
1372 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1373 struct drm_device *dev = encoder->base.dev;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1376
1377 if (WARN_ON(dp_reg & DP_PORT_EN))
1378 return;
1379
1380 ironlake_edp_panel_vdd_on(intel_dp);
1381 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1382 intel_dp_start_link_train(intel_dp);
1383 ironlake_edp_panel_on(intel_dp);
1384 ironlake_edp_panel_vdd_off(intel_dp, true);
1385 intel_dp_complete_link_train(intel_dp);
1386 ironlake_edp_backlight_on(intel_dp);
1387 }
1388
1389 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1390 {
1391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1392
1393 if (is_cpu_edp(intel_dp))
1394 ironlake_edp_pll_on(intel_dp);
1395 }
1396
1397 /*
1398 * Native read with retry for link status and receiver capability reads for
1399 * cases where the sink may still be asleep.
1400 */
1401 static bool
1402 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1403 uint8_t *recv, int recv_bytes)
1404 {
1405 int ret, i;
1406
1407 /*
1408 * Sinks are *supposed* to come up within 1ms from an off state,
1409 * but we're also supposed to retry 3 times per the spec.
1410 */
1411 for (i = 0; i < 3; i++) {
1412 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1413 recv_bytes);
1414 if (ret == recv_bytes)
1415 return true;
1416 msleep(1);
1417 }
1418
1419 return false;
1420 }
1421
1422 /*
1423 * Fetch AUX CH registers 0x202 - 0x207 which contain
1424 * link status information
1425 */
1426 static bool
1427 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1428 {
1429 return intel_dp_aux_native_read_retry(intel_dp,
1430 DP_LANE0_1_STATUS,
1431 link_status,
1432 DP_LINK_STATUS_SIZE);
1433 }
1434
1435 static uint8_t
1436 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1437 int r)
1438 {
1439 return link_status[r - DP_LANE0_1_STATUS];
1440 }
1441
1442 static uint8_t
1443 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1444 int lane)
1445 {
1446 int s = ((lane & 1) ?
1447 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1448 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1449 uint8_t l = adjust_request[lane>>1];
1450
1451 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1452 }
1453
1454 static uint8_t
1455 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1456 int lane)
1457 {
1458 int s = ((lane & 1) ?
1459 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1460 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1461 uint8_t l = adjust_request[lane>>1];
1462
1463 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1464 }
1465
1466
1467 #if 0
1468 static char *voltage_names[] = {
1469 "0.4V", "0.6V", "0.8V", "1.2V"
1470 };
1471 static char *pre_emph_names[] = {
1472 "0dB", "3.5dB", "6dB", "9.5dB"
1473 };
1474 static char *link_train_names[] = {
1475 "pattern 1", "pattern 2", "idle", "off"
1476 };
1477 #endif
1478
1479 /*
1480 * These are source-specific values; current Intel hardware supports
1481 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1482 */
1483
1484 static uint8_t
1485 intel_dp_voltage_max(struct intel_dp *intel_dp)
1486 {
1487 struct drm_device *dev = intel_dp->base.base.dev;
1488
1489 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1490 return DP_TRAIN_VOLTAGE_SWING_800;
1491 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1492 return DP_TRAIN_VOLTAGE_SWING_1200;
1493 else
1494 return DP_TRAIN_VOLTAGE_SWING_800;
1495 }
1496
1497 static uint8_t
1498 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1499 {
1500 struct drm_device *dev = intel_dp->base.base.dev;
1501
1502 if (IS_HASWELL(dev)) {
1503 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1504 case DP_TRAIN_VOLTAGE_SWING_400:
1505 return DP_TRAIN_PRE_EMPHASIS_9_5;
1506 case DP_TRAIN_VOLTAGE_SWING_600:
1507 return DP_TRAIN_PRE_EMPHASIS_6;
1508 case DP_TRAIN_VOLTAGE_SWING_800:
1509 return DP_TRAIN_PRE_EMPHASIS_3_5;
1510 case DP_TRAIN_VOLTAGE_SWING_1200:
1511 default:
1512 return DP_TRAIN_PRE_EMPHASIS_0;
1513 }
1514 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1515 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1516 case DP_TRAIN_VOLTAGE_SWING_400:
1517 return DP_TRAIN_PRE_EMPHASIS_6;
1518 case DP_TRAIN_VOLTAGE_SWING_600:
1519 case DP_TRAIN_VOLTAGE_SWING_800:
1520 return DP_TRAIN_PRE_EMPHASIS_3_5;
1521 default:
1522 return DP_TRAIN_PRE_EMPHASIS_0;
1523 }
1524 } else {
1525 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1526 case DP_TRAIN_VOLTAGE_SWING_400:
1527 return DP_TRAIN_PRE_EMPHASIS_6;
1528 case DP_TRAIN_VOLTAGE_SWING_600:
1529 return DP_TRAIN_PRE_EMPHASIS_6;
1530 case DP_TRAIN_VOLTAGE_SWING_800:
1531 return DP_TRAIN_PRE_EMPHASIS_3_5;
1532 case DP_TRAIN_VOLTAGE_SWING_1200:
1533 default:
1534 return DP_TRAIN_PRE_EMPHASIS_0;
1535 }
1536 }
1537 }
1538
1539 static void
1540 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1541 {
1542 uint8_t v = 0;
1543 uint8_t p = 0;
1544 int lane;
1545 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1546 uint8_t voltage_max;
1547 uint8_t preemph_max;
1548
1549 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1550 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1551 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1552
1553 if (this_v > v)
1554 v = this_v;
1555 if (this_p > p)
1556 p = this_p;
1557 }
1558
1559 voltage_max = intel_dp_voltage_max(intel_dp);
1560 if (v >= voltage_max)
1561 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1562
1563 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1564 if (p >= preemph_max)
1565 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1566
1567 for (lane = 0; lane < 4; lane++)
1568 intel_dp->train_set[lane] = v | p;
1569 }
1570
1571 static uint32_t
1572 intel_dp_signal_levels(uint8_t train_set)
1573 {
1574 uint32_t signal_levels = 0;
1575
1576 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1577 case DP_TRAIN_VOLTAGE_SWING_400:
1578 default:
1579 signal_levels |= DP_VOLTAGE_0_4;
1580 break;
1581 case DP_TRAIN_VOLTAGE_SWING_600:
1582 signal_levels |= DP_VOLTAGE_0_6;
1583 break;
1584 case DP_TRAIN_VOLTAGE_SWING_800:
1585 signal_levels |= DP_VOLTAGE_0_8;
1586 break;
1587 case DP_TRAIN_VOLTAGE_SWING_1200:
1588 signal_levels |= DP_VOLTAGE_1_2;
1589 break;
1590 }
1591 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1592 case DP_TRAIN_PRE_EMPHASIS_0:
1593 default:
1594 signal_levels |= DP_PRE_EMPHASIS_0;
1595 break;
1596 case DP_TRAIN_PRE_EMPHASIS_3_5:
1597 signal_levels |= DP_PRE_EMPHASIS_3_5;
1598 break;
1599 case DP_TRAIN_PRE_EMPHASIS_6:
1600 signal_levels |= DP_PRE_EMPHASIS_6;
1601 break;
1602 case DP_TRAIN_PRE_EMPHASIS_9_5:
1603 signal_levels |= DP_PRE_EMPHASIS_9_5;
1604 break;
1605 }
1606 return signal_levels;
1607 }
1608
1609 /* Gen6's DP voltage swing and pre-emphasis control */
1610 static uint32_t
1611 intel_gen6_edp_signal_levels(uint8_t train_set)
1612 {
1613 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1614 DP_TRAIN_PRE_EMPHASIS_MASK);
1615 switch (signal_levels) {
1616 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1617 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1618 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1619 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1620 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1621 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1622 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1623 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1624 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1625 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1626 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1627 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1628 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1629 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1630 default:
1631 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1632 "0x%x\n", signal_levels);
1633 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1634 }
1635 }
1636
1637 /* Gen7's DP voltage swing and pre-emphasis control */
1638 static uint32_t
1639 intel_gen7_edp_signal_levels(uint8_t train_set)
1640 {
1641 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1642 DP_TRAIN_PRE_EMPHASIS_MASK);
1643 switch (signal_levels) {
1644 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1645 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1646 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1647 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1648 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1649 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1650
1651 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1652 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1653 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1654 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1655
1656 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1657 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1658 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1659 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1660
1661 default:
1662 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1663 "0x%x\n", signal_levels);
1664 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1665 }
1666 }
1667
1668 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1669 static uint32_t
1670 intel_dp_signal_levels_hsw(uint8_t train_set)
1671 {
1672 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1673 DP_TRAIN_PRE_EMPHASIS_MASK);
1674 switch (signal_levels) {
1675 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1676 return DDI_BUF_EMP_400MV_0DB_HSW;
1677 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1678 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1679 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1680 return DDI_BUF_EMP_400MV_6DB_HSW;
1681 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1682 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1683
1684 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1685 return DDI_BUF_EMP_600MV_0DB_HSW;
1686 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1687 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1688 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1689 return DDI_BUF_EMP_600MV_6DB_HSW;
1690
1691 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1692 return DDI_BUF_EMP_800MV_0DB_HSW;
1693 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1694 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1695 default:
1696 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1697 "0x%x\n", signal_levels);
1698 return DDI_BUF_EMP_400MV_0DB_HSW;
1699 }
1700 }
1701
1702 static uint8_t
1703 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1704 int lane)
1705 {
1706 int s = (lane & 1) * 4;
1707 uint8_t l = link_status[lane>>1];
1708
1709 return (l >> s) & 0xf;
1710 }
1711
1712 /* Check for clock recovery is done on all channels */
1713 static bool
1714 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1715 {
1716 int lane;
1717 uint8_t lane_status;
1718
1719 for (lane = 0; lane < lane_count; lane++) {
1720 lane_status = intel_get_lane_status(link_status, lane);
1721 if ((lane_status & DP_LANE_CR_DONE) == 0)
1722 return false;
1723 }
1724 return true;
1725 }
1726
1727 /* Check to see if channel eq is done on all channels */
1728 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1729 DP_LANE_CHANNEL_EQ_DONE|\
1730 DP_LANE_SYMBOL_LOCKED)
1731 static bool
1732 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1733 {
1734 uint8_t lane_align;
1735 uint8_t lane_status;
1736 int lane;
1737
1738 lane_align = intel_dp_link_status(link_status,
1739 DP_LANE_ALIGN_STATUS_UPDATED);
1740 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1741 return false;
1742 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1743 lane_status = intel_get_lane_status(link_status, lane);
1744 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1745 return false;
1746 }
1747 return true;
1748 }
1749
1750 static bool
1751 intel_dp_set_link_train(struct intel_dp *intel_dp,
1752 uint32_t dp_reg_value,
1753 uint8_t dp_train_pat)
1754 {
1755 struct drm_device *dev = intel_dp->base.base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 int ret;
1758 uint32_t temp;
1759
1760 if (IS_HASWELL(dev)) {
1761 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1762
1763 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1764 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1765 else
1766 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1767
1768 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1769 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1770 case DP_TRAINING_PATTERN_DISABLE:
1771 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1772 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1773
1774 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1775 DP_TP_STATUS_IDLE_DONE), 1))
1776 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1777
1778 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1779 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1780
1781 break;
1782 case DP_TRAINING_PATTERN_1:
1783 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1784 break;
1785 case DP_TRAINING_PATTERN_2:
1786 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1787 break;
1788 case DP_TRAINING_PATTERN_3:
1789 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1790 break;
1791 }
1792 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1793
1794 } else if (HAS_PCH_CPT(dev) &&
1795 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1796 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1797
1798 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1799 case DP_TRAINING_PATTERN_DISABLE:
1800 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1801 break;
1802 case DP_TRAINING_PATTERN_1:
1803 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1804 break;
1805 case DP_TRAINING_PATTERN_2:
1806 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1807 break;
1808 case DP_TRAINING_PATTERN_3:
1809 DRM_ERROR("DP training pattern 3 not supported\n");
1810 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1811 break;
1812 }
1813
1814 } else {
1815 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1816
1817 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1818 case DP_TRAINING_PATTERN_DISABLE:
1819 dp_reg_value |= DP_LINK_TRAIN_OFF;
1820 break;
1821 case DP_TRAINING_PATTERN_1:
1822 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1823 break;
1824 case DP_TRAINING_PATTERN_2:
1825 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1826 break;
1827 case DP_TRAINING_PATTERN_3:
1828 DRM_ERROR("DP training pattern 3 not supported\n");
1829 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1830 break;
1831 }
1832 }
1833
1834 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1835 POSTING_READ(intel_dp->output_reg);
1836
1837 intel_dp_aux_native_write_1(intel_dp,
1838 DP_TRAINING_PATTERN_SET,
1839 dp_train_pat);
1840
1841 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1842 DP_TRAINING_PATTERN_DISABLE) {
1843 ret = intel_dp_aux_native_write(intel_dp,
1844 DP_TRAINING_LANE0_SET,
1845 intel_dp->train_set,
1846 intel_dp->lane_count);
1847 if (ret != intel_dp->lane_count)
1848 return false;
1849 }
1850
1851 return true;
1852 }
1853
1854 /* Enable corresponding port and start training pattern 1 */
1855 void
1856 intel_dp_start_link_train(struct intel_dp *intel_dp)
1857 {
1858 struct drm_encoder *encoder = &intel_dp->base.base;
1859 struct drm_device *dev = encoder->dev;
1860 int i;
1861 uint8_t voltage;
1862 bool clock_recovery = false;
1863 int voltage_tries, loop_tries;
1864 uint32_t DP = intel_dp->DP;
1865
1866 if (IS_HASWELL(dev))
1867 intel_ddi_prepare_link_retrain(encoder);
1868
1869 /* Write the link configuration data */
1870 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1871 intel_dp->link_configuration,
1872 DP_LINK_CONFIGURATION_SIZE);
1873
1874 DP |= DP_PORT_EN;
1875
1876 memset(intel_dp->train_set, 0, 4);
1877 voltage = 0xff;
1878 voltage_tries = 0;
1879 loop_tries = 0;
1880 clock_recovery = false;
1881 for (;;) {
1882 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1883 uint8_t link_status[DP_LINK_STATUS_SIZE];
1884 uint32_t signal_levels;
1885
1886 if (IS_HASWELL(dev)) {
1887 signal_levels = intel_dp_signal_levels_hsw(
1888 intel_dp->train_set[0]);
1889 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1890 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1891 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1892 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1893 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1894 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1895 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1896 } else {
1897 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1898 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1899 }
1900 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1901 signal_levels);
1902
1903 if (!intel_dp_set_link_train(intel_dp, DP,
1904 DP_TRAINING_PATTERN_1 |
1905 DP_LINK_SCRAMBLING_DISABLE))
1906 break;
1907 /* Set training pattern 1 */
1908
1909 udelay(100);
1910 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1911 DRM_ERROR("failed to get link status\n");
1912 break;
1913 }
1914
1915 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1916 DRM_DEBUG_KMS("clock recovery OK\n");
1917 clock_recovery = true;
1918 break;
1919 }
1920
1921 /* Check to see if we've tried the max voltage */
1922 for (i = 0; i < intel_dp->lane_count; i++)
1923 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1924 break;
1925 if (i == intel_dp->lane_count && voltage_tries == 5) {
1926 ++loop_tries;
1927 if (loop_tries == 5) {
1928 DRM_DEBUG_KMS("too many full retries, give up\n");
1929 break;
1930 }
1931 memset(intel_dp->train_set, 0, 4);
1932 voltage_tries = 0;
1933 continue;
1934 }
1935
1936 /* Check to see if we've tried the same voltage 5 times */
1937 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1938 ++voltage_tries;
1939 if (voltage_tries == 5) {
1940 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1941 break;
1942 }
1943 } else
1944 voltage_tries = 0;
1945 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1946
1947 /* Compute new intel_dp->train_set as requested by target */
1948 intel_get_adjust_train(intel_dp, link_status);
1949 }
1950
1951 intel_dp->DP = DP;
1952 }
1953
1954 void
1955 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1956 {
1957 struct drm_device *dev = intel_dp->base.base.dev;
1958 bool channel_eq = false;
1959 int tries, cr_tries;
1960 uint32_t DP = intel_dp->DP;
1961
1962 /* channel equalization */
1963 tries = 0;
1964 cr_tries = 0;
1965 channel_eq = false;
1966 for (;;) {
1967 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1968 uint32_t signal_levels;
1969 uint8_t link_status[DP_LINK_STATUS_SIZE];
1970
1971 if (cr_tries > 5) {
1972 DRM_ERROR("failed to train DP, aborting\n");
1973 intel_dp_link_down(intel_dp);
1974 break;
1975 }
1976
1977 if (IS_HASWELL(dev)) {
1978 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1979 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1980 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1981 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1982 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1983 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1984 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1985 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1986 } else {
1987 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1988 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1989 }
1990
1991 /* channel eq pattern */
1992 if (!intel_dp_set_link_train(intel_dp, DP,
1993 DP_TRAINING_PATTERN_2 |
1994 DP_LINK_SCRAMBLING_DISABLE))
1995 break;
1996
1997 udelay(400);
1998 if (!intel_dp_get_link_status(intel_dp, link_status))
1999 break;
2000
2001 /* Make sure clock is still ok */
2002 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2003 intel_dp_start_link_train(intel_dp);
2004 cr_tries++;
2005 continue;
2006 }
2007
2008 if (intel_channel_eq_ok(intel_dp, link_status)) {
2009 channel_eq = true;
2010 break;
2011 }
2012
2013 /* Try 5 times, then try clock recovery if that fails */
2014 if (tries > 5) {
2015 intel_dp_link_down(intel_dp);
2016 intel_dp_start_link_train(intel_dp);
2017 tries = 0;
2018 cr_tries++;
2019 continue;
2020 }
2021
2022 /* Compute new intel_dp->train_set as requested by target */
2023 intel_get_adjust_train(intel_dp, link_status);
2024 ++tries;
2025 }
2026
2027 if (channel_eq)
2028 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2029
2030 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2031 }
2032
2033 static void
2034 intel_dp_link_down(struct intel_dp *intel_dp)
2035 {
2036 struct drm_device *dev = intel_dp->base.base.dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 uint32_t DP = intel_dp->DP;
2039
2040 /*
2041 * DDI code has a strict mode set sequence and we should try to respect
2042 * it, otherwise we might hang the machine in many different ways. So we
2043 * really should be disabling the port only on a complete crtc_disable
2044 * sequence. This function is just called under two conditions on DDI
2045 * code:
2046 * - Link train failed while doing crtc_enable, and on this case we
2047 * really should respect the mode set sequence and wait for a
2048 * crtc_disable.
2049 * - Someone turned the monitor off and intel_dp_check_link_status
2050 * called us. We don't need to disable the whole port on this case, so
2051 * when someone turns the monitor on again,
2052 * intel_ddi_prepare_link_retrain will take care of redoing the link
2053 * train.
2054 */
2055 if (IS_HASWELL(dev))
2056 return;
2057
2058 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2059 return;
2060
2061 DRM_DEBUG_KMS("\n");
2062
2063 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2064 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2065 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2066 } else {
2067 DP &= ~DP_LINK_TRAIN_MASK;
2068 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2069 }
2070 POSTING_READ(intel_dp->output_reg);
2071
2072 msleep(17);
2073
2074 if (HAS_PCH_IBX(dev) &&
2075 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2076 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2077
2078 /* Hardware workaround: leaving our transcoder select
2079 * set to transcoder B while it's off will prevent the
2080 * corresponding HDMI output on transcoder A.
2081 *
2082 * Combine this with another hardware workaround:
2083 * transcoder select bit can only be cleared while the
2084 * port is enabled.
2085 */
2086 DP &= ~DP_PIPEB_SELECT;
2087 I915_WRITE(intel_dp->output_reg, DP);
2088
2089 /* Changes to enable or select take place the vblank
2090 * after being written.
2091 */
2092 if (crtc == NULL) {
2093 /* We can arrive here never having been attached
2094 * to a CRTC, for instance, due to inheriting
2095 * random state from the BIOS.
2096 *
2097 * If the pipe is not running, play safe and
2098 * wait for the clocks to stabilise before
2099 * continuing.
2100 */
2101 POSTING_READ(intel_dp->output_reg);
2102 msleep(50);
2103 } else
2104 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2105 }
2106
2107 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2108 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2109 POSTING_READ(intel_dp->output_reg);
2110 msleep(intel_dp->panel_power_down_delay);
2111 }
2112
2113 static bool
2114 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2115 {
2116 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2117 sizeof(intel_dp->dpcd)) == 0)
2118 return false; /* aux transfer failed */
2119
2120 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2121 return false; /* DPCD not present */
2122
2123 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2124 DP_DWN_STRM_PORT_PRESENT))
2125 return true; /* native DP sink */
2126
2127 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2128 return true; /* no per-port downstream info */
2129
2130 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2131 intel_dp->downstream_ports,
2132 DP_MAX_DOWNSTREAM_PORTS) == 0)
2133 return false; /* downstream port status fetch failed */
2134
2135 return true;
2136 }
2137
2138 static void
2139 intel_dp_probe_oui(struct intel_dp *intel_dp)
2140 {
2141 u8 buf[3];
2142
2143 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2144 return;
2145
2146 ironlake_edp_panel_vdd_on(intel_dp);
2147
2148 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2149 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2150 buf[0], buf[1], buf[2]);
2151
2152 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2153 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2154 buf[0], buf[1], buf[2]);
2155
2156 ironlake_edp_panel_vdd_off(intel_dp, false);
2157 }
2158
2159 static bool
2160 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2161 {
2162 int ret;
2163
2164 ret = intel_dp_aux_native_read_retry(intel_dp,
2165 DP_DEVICE_SERVICE_IRQ_VECTOR,
2166 sink_irq_vector, 1);
2167 if (!ret)
2168 return false;
2169
2170 return true;
2171 }
2172
2173 static void
2174 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2175 {
2176 /* NAK by default */
2177 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2178 }
2179
2180 /*
2181 * According to DP spec
2182 * 5.1.2:
2183 * 1. Read DPCD
2184 * 2. Configure link according to Receiver Capabilities
2185 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2186 * 4. Check link status on receipt of hot-plug interrupt
2187 */
2188
2189 static void
2190 intel_dp_check_link_status(struct intel_dp *intel_dp)
2191 {
2192 u8 sink_irq_vector;
2193 u8 link_status[DP_LINK_STATUS_SIZE];
2194
2195 if (!intel_dp->base.connectors_active)
2196 return;
2197
2198 if (WARN_ON(!intel_dp->base.base.crtc))
2199 return;
2200
2201 /* Try to read receiver status if the link appears to be up */
2202 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2203 intel_dp_link_down(intel_dp);
2204 return;
2205 }
2206
2207 /* Now read the DPCD to see if it's actually running */
2208 if (!intel_dp_get_dpcd(intel_dp)) {
2209 intel_dp_link_down(intel_dp);
2210 return;
2211 }
2212
2213 /* Try to read the source of the interrupt */
2214 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2215 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2216 /* Clear interrupt source */
2217 intel_dp_aux_native_write_1(intel_dp,
2218 DP_DEVICE_SERVICE_IRQ_VECTOR,
2219 sink_irq_vector);
2220
2221 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2222 intel_dp_handle_test_request(intel_dp);
2223 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2224 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2225 }
2226
2227 if (!intel_channel_eq_ok(intel_dp, link_status)) {
2228 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2229 drm_get_encoder_name(&intel_dp->base.base));
2230 intel_dp_start_link_train(intel_dp);
2231 intel_dp_complete_link_train(intel_dp);
2232 }
2233 }
2234
2235 /* XXX this is probably wrong for multiple downstream ports */
2236 static enum drm_connector_status
2237 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2238 {
2239 uint8_t *dpcd = intel_dp->dpcd;
2240 bool hpd;
2241 uint8_t type;
2242
2243 if (!intel_dp_get_dpcd(intel_dp))
2244 return connector_status_disconnected;
2245
2246 /* if there's no downstream port, we're done */
2247 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2248 return connector_status_connected;
2249
2250 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2251 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2252 if (hpd) {
2253 uint8_t reg;
2254 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2255 &reg, 1))
2256 return connector_status_unknown;
2257 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2258 : connector_status_disconnected;
2259 }
2260
2261 /* If no HPD, poke DDC gently */
2262 if (drm_probe_ddc(&intel_dp->adapter))
2263 return connector_status_connected;
2264
2265 /* Well we tried, say unknown for unreliable port types */
2266 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2267 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2268 return connector_status_unknown;
2269
2270 /* Anything else is out of spec, warn and ignore */
2271 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2272 return connector_status_disconnected;
2273 }
2274
2275 static enum drm_connector_status
2276 ironlake_dp_detect(struct intel_dp *intel_dp)
2277 {
2278 enum drm_connector_status status;
2279
2280 /* Can't disconnect eDP, but you can close the lid... */
2281 if (is_edp(intel_dp)) {
2282 status = intel_panel_detect(intel_dp->base.base.dev);
2283 if (status == connector_status_unknown)
2284 status = connector_status_connected;
2285 return status;
2286 }
2287
2288 return intel_dp_detect_dpcd(intel_dp);
2289 }
2290
2291 static enum drm_connector_status
2292 g4x_dp_detect(struct intel_dp *intel_dp)
2293 {
2294 struct drm_device *dev = intel_dp->base.base.dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 uint32_t bit;
2297
2298 switch (intel_dp->output_reg) {
2299 case DP_B:
2300 bit = DPB_HOTPLUG_LIVE_STATUS;
2301 break;
2302 case DP_C:
2303 bit = DPC_HOTPLUG_LIVE_STATUS;
2304 break;
2305 case DP_D:
2306 bit = DPD_HOTPLUG_LIVE_STATUS;
2307 break;
2308 default:
2309 return connector_status_unknown;
2310 }
2311
2312 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2313 return connector_status_disconnected;
2314
2315 return intel_dp_detect_dpcd(intel_dp);
2316 }
2317
2318 static struct edid *
2319 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2320 {
2321 struct intel_dp *intel_dp = intel_attached_dp(connector);
2322 struct edid *edid;
2323 int size;
2324
2325 if (is_edp(intel_dp)) {
2326 if (!intel_dp->edid)
2327 return NULL;
2328
2329 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2330 edid = kmalloc(size, GFP_KERNEL);
2331 if (!edid)
2332 return NULL;
2333
2334 memcpy(edid, intel_dp->edid, size);
2335 return edid;
2336 }
2337
2338 edid = drm_get_edid(connector, adapter);
2339 return edid;
2340 }
2341
2342 static int
2343 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2344 {
2345 struct intel_dp *intel_dp = intel_attached_dp(connector);
2346 int ret;
2347
2348 if (is_edp(intel_dp)) {
2349 drm_mode_connector_update_edid_property(connector,
2350 intel_dp->edid);
2351 ret = drm_add_edid_modes(connector, intel_dp->edid);
2352 drm_edid_to_eld(connector,
2353 intel_dp->edid);
2354 return intel_dp->edid_mode_count;
2355 }
2356
2357 ret = intel_ddc_get_modes(connector, adapter);
2358 return ret;
2359 }
2360
2361
2362 /**
2363 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2364 *
2365 * \return true if DP port is connected.
2366 * \return false if DP port is disconnected.
2367 */
2368 static enum drm_connector_status
2369 intel_dp_detect(struct drm_connector *connector, bool force)
2370 {
2371 struct intel_dp *intel_dp = intel_attached_dp(connector);
2372 struct drm_device *dev = intel_dp->base.base.dev;
2373 enum drm_connector_status status;
2374 struct edid *edid = NULL;
2375
2376 intel_dp->has_audio = false;
2377
2378 if (HAS_PCH_SPLIT(dev))
2379 status = ironlake_dp_detect(intel_dp);
2380 else
2381 status = g4x_dp_detect(intel_dp);
2382
2383 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2384 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2385 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2386 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2387
2388 if (status != connector_status_connected)
2389 return status;
2390
2391 intel_dp_probe_oui(intel_dp);
2392
2393 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2394 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2395 } else {
2396 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2397 if (edid) {
2398 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2399 kfree(edid);
2400 }
2401 }
2402
2403 return connector_status_connected;
2404 }
2405
2406 static int intel_dp_get_modes(struct drm_connector *connector)
2407 {
2408 struct intel_dp *intel_dp = intel_attached_dp(connector);
2409 struct drm_device *dev = intel_dp->base.base.dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 int ret;
2412
2413 /* We should parse the EDID data and find out if it has an audio sink
2414 */
2415
2416 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2417 if (ret) {
2418 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2419 struct drm_display_mode *newmode;
2420 list_for_each_entry(newmode, &connector->probed_modes,
2421 head) {
2422 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2423 intel_dp->panel_fixed_mode =
2424 drm_mode_duplicate(dev, newmode);
2425 break;
2426 }
2427 }
2428 }
2429 return ret;
2430 }
2431
2432 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2433 if (is_edp(intel_dp)) {
2434 /* initialize panel mode from VBT if available for eDP */
2435 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2436 intel_dp->panel_fixed_mode =
2437 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2438 if (intel_dp->panel_fixed_mode) {
2439 intel_dp->panel_fixed_mode->type |=
2440 DRM_MODE_TYPE_PREFERRED;
2441 }
2442 }
2443 if (intel_dp->panel_fixed_mode) {
2444 struct drm_display_mode *mode;
2445 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2446 drm_mode_probed_add(connector, mode);
2447 return 1;
2448 }
2449 }
2450 return 0;
2451 }
2452
2453 static bool
2454 intel_dp_detect_audio(struct drm_connector *connector)
2455 {
2456 struct intel_dp *intel_dp = intel_attached_dp(connector);
2457 struct edid *edid;
2458 bool has_audio = false;
2459
2460 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2461 if (edid) {
2462 has_audio = drm_detect_monitor_audio(edid);
2463 kfree(edid);
2464 }
2465
2466 return has_audio;
2467 }
2468
2469 static int
2470 intel_dp_set_property(struct drm_connector *connector,
2471 struct drm_property *property,
2472 uint64_t val)
2473 {
2474 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2475 struct intel_dp *intel_dp = intel_attached_dp(connector);
2476 int ret;
2477
2478 ret = drm_connector_property_set_value(connector, property, val);
2479 if (ret)
2480 return ret;
2481
2482 if (property == dev_priv->force_audio_property) {
2483 int i = val;
2484 bool has_audio;
2485
2486 if (i == intel_dp->force_audio)
2487 return 0;
2488
2489 intel_dp->force_audio = i;
2490
2491 if (i == HDMI_AUDIO_AUTO)
2492 has_audio = intel_dp_detect_audio(connector);
2493 else
2494 has_audio = (i == HDMI_AUDIO_ON);
2495
2496 if (has_audio == intel_dp->has_audio)
2497 return 0;
2498
2499 intel_dp->has_audio = has_audio;
2500 goto done;
2501 }
2502
2503 if (property == dev_priv->broadcast_rgb_property) {
2504 if (val == !!intel_dp->color_range)
2505 return 0;
2506
2507 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2508 goto done;
2509 }
2510
2511 return -EINVAL;
2512
2513 done:
2514 if (intel_dp->base.base.crtc) {
2515 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2516 intel_set_mode(crtc, &crtc->mode,
2517 crtc->x, crtc->y, crtc->fb);
2518 }
2519
2520 return 0;
2521 }
2522
2523 static void
2524 intel_dp_destroy(struct drm_connector *connector)
2525 {
2526 struct drm_device *dev = connector->dev;
2527
2528 if (intel_dpd_is_edp(dev))
2529 intel_panel_destroy_backlight(dev);
2530
2531 drm_sysfs_connector_remove(connector);
2532 drm_connector_cleanup(connector);
2533 kfree(connector);
2534 }
2535
2536 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2537 {
2538 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2539
2540 i2c_del_adapter(&intel_dp->adapter);
2541 drm_encoder_cleanup(encoder);
2542 if (is_edp(intel_dp)) {
2543 kfree(intel_dp->edid);
2544 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2545 ironlake_panel_vdd_off_sync(intel_dp);
2546 }
2547 kfree(intel_dp);
2548 }
2549
2550 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2551 .mode_fixup = intel_dp_mode_fixup,
2552 .mode_set = intel_dp_mode_set,
2553 .disable = intel_encoder_noop,
2554 };
2555
2556 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2557 .dpms = intel_connector_dpms,
2558 .detect = intel_dp_detect,
2559 .fill_modes = drm_helper_probe_single_connector_modes,
2560 .set_property = intel_dp_set_property,
2561 .destroy = intel_dp_destroy,
2562 };
2563
2564 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2565 .get_modes = intel_dp_get_modes,
2566 .mode_valid = intel_dp_mode_valid,
2567 .best_encoder = intel_best_encoder,
2568 };
2569
2570 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2571 .destroy = intel_dp_encoder_destroy,
2572 };
2573
2574 static void
2575 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2576 {
2577 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2578
2579 intel_dp_check_link_status(intel_dp);
2580 }
2581
2582 /* Return which DP Port should be selected for Transcoder DP control */
2583 int
2584 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2585 {
2586 struct drm_device *dev = crtc->dev;
2587 struct intel_encoder *encoder;
2588
2589 for_each_encoder_on_crtc(dev, crtc, encoder) {
2590 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2591
2592 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2593 intel_dp->base.type == INTEL_OUTPUT_EDP)
2594 return intel_dp->output_reg;
2595 }
2596
2597 return -1;
2598 }
2599
2600 /* check the VBT to see whether the eDP is on DP-D port */
2601 bool intel_dpd_is_edp(struct drm_device *dev)
2602 {
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct child_device_config *p_child;
2605 int i;
2606
2607 if (!dev_priv->child_dev_num)
2608 return false;
2609
2610 for (i = 0; i < dev_priv->child_dev_num; i++) {
2611 p_child = dev_priv->child_dev + i;
2612
2613 if (p_child->dvo_port == PORT_IDPD &&
2614 p_child->device_type == DEVICE_TYPE_eDP)
2615 return true;
2616 }
2617 return false;
2618 }
2619
2620 static void
2621 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2622 {
2623 intel_attach_force_audio_property(connector);
2624 intel_attach_broadcast_rgb_property(connector);
2625 }
2626
2627 void
2628 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2629 {
2630 struct drm_i915_private *dev_priv = dev->dev_private;
2631 struct drm_connector *connector;
2632 struct intel_dp *intel_dp;
2633 struct intel_encoder *intel_encoder;
2634 struct intel_connector *intel_connector;
2635 const char *name = NULL;
2636 int type;
2637
2638 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2639 if (!intel_dp)
2640 return;
2641
2642 intel_dp->output_reg = output_reg;
2643 intel_dp->port = port;
2644 /* Preserve the current hw state. */
2645 intel_dp->DP = I915_READ(intel_dp->output_reg);
2646
2647 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2648 if (!intel_connector) {
2649 kfree(intel_dp);
2650 return;
2651 }
2652 intel_encoder = &intel_dp->base;
2653
2654 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2655 if (intel_dpd_is_edp(dev))
2656 intel_dp->is_pch_edp = true;
2657
2658 /*
2659 * FIXME : We need to initialize built-in panels before external panels.
2660 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2661 */
2662 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2663 type = DRM_MODE_CONNECTOR_eDP;
2664 intel_encoder->type = INTEL_OUTPUT_EDP;
2665 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2666 type = DRM_MODE_CONNECTOR_eDP;
2667 intel_encoder->type = INTEL_OUTPUT_EDP;
2668 } else {
2669 type = DRM_MODE_CONNECTOR_DisplayPort;
2670 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2671 }
2672
2673 connector = &intel_connector->base;
2674 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2675 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2676
2677 connector->polled = DRM_CONNECTOR_POLL_HPD;
2678
2679 intel_encoder->cloneable = false;
2680
2681 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2682 ironlake_panel_vdd_work);
2683
2684 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2685
2686 connector->interlace_allowed = true;
2687 connector->doublescan_allowed = 0;
2688
2689 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2690 DRM_MODE_ENCODER_TMDS);
2691 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2692
2693 intel_connector_attach_encoder(intel_connector, intel_encoder);
2694 drm_sysfs_connector_add(connector);
2695
2696 intel_encoder->enable = intel_enable_dp;
2697 intel_encoder->pre_enable = intel_pre_enable_dp;
2698 intel_encoder->disable = intel_disable_dp;
2699 intel_encoder->post_disable = intel_post_disable_dp;
2700 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2701 intel_connector->get_hw_state = intel_connector_get_hw_state;
2702
2703 /* Set up the DDC bus. */
2704 switch (port) {
2705 case PORT_A:
2706 name = "DPDDC-A";
2707 break;
2708 case PORT_B:
2709 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2710 name = "DPDDC-B";
2711 break;
2712 case PORT_C:
2713 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2714 name = "DPDDC-C";
2715 break;
2716 case PORT_D:
2717 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2718 name = "DPDDC-D";
2719 break;
2720 default:
2721 WARN(1, "Invalid port %c\n", port_name(port));
2722 break;
2723 }
2724
2725 /* Cache some DPCD data in the eDP case */
2726 if (is_edp(intel_dp)) {
2727 struct edp_power_seq cur, vbt;
2728 u32 pp_on, pp_off, pp_div;
2729
2730 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2731 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2732 pp_div = I915_READ(PCH_PP_DIVISOR);
2733
2734 if (!pp_on || !pp_off || !pp_div) {
2735 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2736 intel_dp_encoder_destroy(&intel_dp->base.base);
2737 intel_dp_destroy(&intel_connector->base);
2738 return;
2739 }
2740
2741 /* Pull timing values out of registers */
2742 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2743 PANEL_POWER_UP_DELAY_SHIFT;
2744
2745 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2746 PANEL_LIGHT_ON_DELAY_SHIFT;
2747
2748 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2749 PANEL_LIGHT_OFF_DELAY_SHIFT;
2750
2751 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2752 PANEL_POWER_DOWN_DELAY_SHIFT;
2753
2754 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2755 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2756
2757 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2758 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2759
2760 vbt = dev_priv->edp.pps;
2761
2762 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2763 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2764
2765 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2766
2767 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2768 intel_dp->backlight_on_delay = get_delay(t8);
2769 intel_dp->backlight_off_delay = get_delay(t9);
2770 intel_dp->panel_power_down_delay = get_delay(t10);
2771 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2772
2773 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2774 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2775 intel_dp->panel_power_cycle_delay);
2776
2777 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2778 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2779 }
2780
2781 intel_dp_i2c_init(intel_dp, intel_connector, name);
2782
2783 if (is_edp(intel_dp)) {
2784 bool ret;
2785 struct edid *edid;
2786
2787 ironlake_edp_panel_vdd_on(intel_dp);
2788 ret = intel_dp_get_dpcd(intel_dp);
2789 ironlake_edp_panel_vdd_off(intel_dp, false);
2790
2791 if (ret) {
2792 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2793 dev_priv->no_aux_handshake =
2794 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2795 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2796 } else {
2797 /* if this fails, presume the device is a ghost */
2798 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2799 intel_dp_encoder_destroy(&intel_dp->base.base);
2800 intel_dp_destroy(&intel_connector->base);
2801 return;
2802 }
2803
2804 ironlake_edp_panel_vdd_on(intel_dp);
2805 edid = drm_get_edid(connector, &intel_dp->adapter);
2806 if (edid) {
2807 drm_mode_connector_update_edid_property(connector,
2808 edid);
2809 intel_dp->edid_mode_count =
2810 drm_add_edid_modes(connector, edid);
2811 drm_edid_to_eld(connector, edid);
2812 intel_dp->edid = edid;
2813 }
2814 ironlake_edp_panel_vdd_off(intel_dp, false);
2815 }
2816
2817 intel_encoder->hot_plug = intel_dp_hot_plug;
2818
2819 if (is_edp(intel_dp)) {
2820 dev_priv->int_edp_connector = connector;
2821 intel_panel_setup_backlight(dev);
2822 }
2823
2824 intel_dp_add_properties(intel_dp, connector);
2825
2826 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2827 * 0xd. Failure to do so will result in spurious interrupts being
2828 * generated on the port when a cable is not attached.
2829 */
2830 if (IS_G4X(dev) && !IS_GM45(dev)) {
2831 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2832 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2833 }
2834 }
Linux kernel - Deliverables
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