2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
36 #include "intel_drv.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
51 static bool is_edp(struct intel_dp
*intel_dp
)
53 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
64 static bool is_pch_edp(struct intel_dp
*intel_dp
)
66 return intel_dp
->is_pch_edp
;
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
75 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
77 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
80 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
82 return container_of(encoder
, struct intel_dp
, base
.base
);
85 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
87 return container_of(intel_attached_encoder(connector
),
88 struct intel_dp
, base
);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
100 struct intel_dp
*intel_dp
;
105 intel_dp
= enc_to_intel_dp(encoder
);
107 return is_pch_edp(intel_dp
);
110 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
111 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
112 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
115 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
116 int *lane_num
, int *link_bw
)
118 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
120 *lane_num
= intel_dp
->lane_count
;
121 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
123 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
128 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
129 struct drm_display_mode
*mode
)
131 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
133 if (intel_dp
->panel_fixed_mode
)
134 return intel_dp
->panel_fixed_mode
->clock
;
140 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
142 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
143 switch (max_lane_count
) {
144 case 1: case 2: case 4:
149 return max_lane_count
;
153 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
155 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
157 switch (max_link_bw
) {
158 case DP_LINK_BW_1_62
:
162 max_link_bw
= DP_LINK_BW_1_62
;
169 intel_dp_link_clock(uint8_t link_bw
)
171 if (link_bw
== DP_LINK_BW_2_7
)
178 * The units on the numbers in the next two are... bizarre. Examples will
179 * make it clearer; this one parallels an example in the eDP spec.
181 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
183 * 270000 * 1 * 8 / 10 == 216000
185 * The actual data capacity of that configuration is 2.16Gbit/s, so the
186 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
187 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
188 * 119000. At 18bpp that's 2142000 kilobits per second.
190 * Thus the strange-looking division by 10 in intel_dp_link_required, to
191 * get the result in decakilobits instead of kilobits.
195 intel_dp_link_required(int pixel_clock
, int bpp
)
197 return (pixel_clock
* bpp
+ 9) / 10;
201 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
203 return (max_link_clock
* max_lanes
* 8) / 10;
207 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
208 struct drm_display_mode
*mode
,
211 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
212 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
213 int max_rate
, mode_rate
;
215 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
216 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
218 if (mode_rate
> max_rate
) {
219 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
220 if (mode_rate
> max_rate
)
225 |= INTEL_MODE_DP_FORCE_6BPC
;
234 intel_dp_mode_valid(struct drm_connector
*connector
,
235 struct drm_display_mode
*mode
)
237 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
239 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
240 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
243 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
247 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
248 return MODE_CLOCK_HIGH
;
250 if (mode
->clock
< 10000)
251 return MODE_CLOCK_LOW
;
253 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
254 return MODE_H_ILLEGAL
;
260 pack_aux(uint8_t *src
, int src_bytes
)
267 for (i
= 0; i
< src_bytes
; i
++)
268 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
273 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
278 for (i
= 0; i
< dst_bytes
; i
++)
279 dst
[i
] = src
>> ((3-i
) * 8);
282 /* hrawclock is 1/4 the FSB frequency */
284 intel_hrawclk(struct drm_device
*dev
)
286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
289 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
290 if (IS_VALLEYVIEW(dev
))
293 clkcfg
= I915_READ(CLKCFG
);
294 switch (clkcfg
& CLKCFG_FSB_MASK
) {
303 case CLKCFG_FSB_1067
:
305 case CLKCFG_FSB_1333
:
307 /* these two are just a guess; one of them might be right */
308 case CLKCFG_FSB_1600
:
309 case CLKCFG_FSB_1600_ALT
:
316 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
318 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
321 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
324 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
326 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
329 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
333 intel_dp_check_edp(struct intel_dp
*intel_dp
)
335 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
338 if (!is_edp(intel_dp
))
340 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
341 WARN(1, "eDP powered off while attempting aux channel communication.\n");
342 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
343 I915_READ(PCH_PP_STATUS
),
344 I915_READ(PCH_PP_CONTROL
));
349 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
350 uint8_t *send
, int send_bytes
,
351 uint8_t *recv
, int recv_size
)
353 uint32_t output_reg
= intel_dp
->output_reg
;
354 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
356 uint32_t ch_ctl
= output_reg
+ 0x10;
357 uint32_t ch_data
= ch_ctl
+ 4;
361 uint32_t aux_clock_divider
;
364 intel_dp_check_edp(intel_dp
);
365 /* The clock divider is based off the hrawclk,
366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
369 * Note that PCH attached eDP panels should use a 125MHz input
372 if (is_cpu_edp(intel_dp
)) {
373 if (IS_VALLEYVIEW(dev
))
374 aux_clock_divider
= 100;
375 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
376 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
378 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
379 } else if (HAS_PCH_SPLIT(dev
))
380 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
382 aux_clock_divider
= intel_hrawclk(dev
) / 2;
389 /* Try to wait for any previous AUX channel activity */
390 for (try = 0; try < 3; try++) {
391 status
= I915_READ(ch_ctl
);
392 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
398 WARN(1, "dp_aux_ch not started status 0x%08x\n",
403 /* Must try at least 3 times according to DP spec */
404 for (try = 0; try < 5; try++) {
405 /* Load the send data into the aux channel data registers */
406 for (i
= 0; i
< send_bytes
; i
+= 4)
407 I915_WRITE(ch_data
+ i
,
408 pack_aux(send
+ i
, send_bytes
- i
));
410 /* Send the command and wait for it to complete */
412 DP_AUX_CH_CTL_SEND_BUSY
|
413 DP_AUX_CH_CTL_TIME_OUT_400us
|
414 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
415 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
416 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
419 DP_AUX_CH_CTL_RECEIVE_ERROR
);
421 status
= I915_READ(ch_ctl
);
422 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
427 /* Clear done status and any errors */
431 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
432 DP_AUX_CH_CTL_RECEIVE_ERROR
);
434 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
435 DP_AUX_CH_CTL_RECEIVE_ERROR
))
437 if (status
& DP_AUX_CH_CTL_DONE
)
441 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
446 /* Check for timeout or receive error.
447 * Timeouts occur when the sink is not connected
449 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
456 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
461 /* Unload any bytes sent back from the other side */
462 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
464 if (recv_bytes
> recv_size
)
465 recv_bytes
= recv_size
;
467 for (i
= 0; i
< recv_bytes
; i
+= 4)
468 unpack_aux(I915_READ(ch_data
+ i
),
469 recv
+ i
, recv_bytes
- i
);
474 /* Write data to the aux channel in native mode */
476 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
477 uint16_t address
, uint8_t *send
, int send_bytes
)
484 intel_dp_check_edp(intel_dp
);
487 msg
[0] = AUX_NATIVE_WRITE
<< 4;
488 msg
[1] = address
>> 8;
489 msg
[2] = address
& 0xff;
490 msg
[3] = send_bytes
- 1;
491 memcpy(&msg
[4], send
, send_bytes
);
492 msg_bytes
= send_bytes
+ 4;
494 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
497 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
499 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
507 /* Write a single byte to the aux channel in native mode */
509 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
510 uint16_t address
, uint8_t byte
)
512 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
515 /* read bytes from a native aux channel */
517 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
518 uint16_t address
, uint8_t *recv
, int recv_bytes
)
527 intel_dp_check_edp(intel_dp
);
528 msg
[0] = AUX_NATIVE_READ
<< 4;
529 msg
[1] = address
>> 8;
530 msg
[2] = address
& 0xff;
531 msg
[3] = recv_bytes
- 1;
534 reply_bytes
= recv_bytes
+ 1;
537 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
544 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
545 memcpy(recv
, reply
+ 1, ret
- 1);
548 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
556 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
557 uint8_t write_byte
, uint8_t *read_byte
)
559 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
560 struct intel_dp
*intel_dp
= container_of(adapter
,
563 uint16_t address
= algo_data
->address
;
571 intel_dp_check_edp(intel_dp
);
572 /* Set up the command byte */
573 if (mode
& MODE_I2C_READ
)
574 msg
[0] = AUX_I2C_READ
<< 4;
576 msg
[0] = AUX_I2C_WRITE
<< 4;
578 if (!(mode
& MODE_I2C_STOP
))
579 msg
[0] |= AUX_I2C_MOT
<< 4;
581 msg
[1] = address
>> 8;
602 for (retry
= 0; retry
< 5; retry
++) {
603 ret
= intel_dp_aux_ch(intel_dp
,
607 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
611 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
612 case AUX_NATIVE_REPLY_ACK
:
613 /* I2C-over-AUX Reply field is only valid
614 * when paired with AUX ACK.
617 case AUX_NATIVE_REPLY_NACK
:
618 DRM_DEBUG_KMS("aux_ch native nack\n");
620 case AUX_NATIVE_REPLY_DEFER
:
624 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
629 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
630 case AUX_I2C_REPLY_ACK
:
631 if (mode
== MODE_I2C_READ
) {
632 *read_byte
= reply
[1];
634 return reply_bytes
- 1;
635 case AUX_I2C_REPLY_NACK
:
636 DRM_DEBUG_KMS("aux_i2c nack\n");
638 case AUX_I2C_REPLY_DEFER
:
639 DRM_DEBUG_KMS("aux_i2c defer\n");
643 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
648 DRM_ERROR("too many retries, giving up\n");
652 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
653 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
656 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
657 struct intel_connector
*intel_connector
, const char *name
)
661 DRM_DEBUG_KMS("i2c_init %s\n", name
);
662 intel_dp
->algo
.running
= false;
663 intel_dp
->algo
.address
= 0;
664 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
666 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
667 intel_dp
->adapter
.owner
= THIS_MODULE
;
668 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
669 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
670 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
671 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
672 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
674 ironlake_edp_panel_vdd_on(intel_dp
);
675 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
676 ironlake_edp_panel_vdd_off(intel_dp
, false);
681 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
682 const struct drm_display_mode
*mode
,
683 struct drm_display_mode
*adjusted_mode
)
685 struct drm_device
*dev
= encoder
->dev
;
686 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
687 int lane_count
, clock
;
688 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
689 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
691 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
693 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
694 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
695 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
696 mode
, adjusted_mode
);
699 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
702 DRM_DEBUG_KMS("DP link computation with max lane count %i "
703 "max bw %02x pixel clock %iKHz\n",
704 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
706 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
709 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
710 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
712 for (clock
= 0; clock
<= max_clock
; clock
++) {
713 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
714 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
716 if (mode_rate
<= link_avail
) {
717 intel_dp
->link_bw
= bws
[clock
];
718 intel_dp
->lane_count
= lane_count
;
719 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
720 DRM_DEBUG_KMS("DP link bw %02x lane "
721 "count %d clock %d bpp %d\n",
722 intel_dp
->link_bw
, intel_dp
->lane_count
,
723 adjusted_mode
->clock
, bpp
);
724 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
725 mode_rate
, link_avail
);
734 struct intel_dp_m_n
{
743 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
745 while (*num
> 0xffffff || *den
> 0xffffff) {
752 intel_dp_compute_m_n(int bpp
,
756 struct intel_dp_m_n
*m_n
)
759 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
760 m_n
->gmch_n
= link_clock
* nlanes
;
761 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
762 m_n
->link_m
= pixel_clock
;
763 m_n
->link_n
= link_clock
;
764 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
768 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
769 struct drm_display_mode
*adjusted_mode
)
771 struct drm_device
*dev
= crtc
->dev
;
772 struct intel_encoder
*encoder
;
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
776 struct intel_dp_m_n m_n
;
777 int pipe
= intel_crtc
->pipe
;
780 * Find the lane count in the intel_encoder private
782 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
783 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
785 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
786 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
788 lane_count
= intel_dp
->lane_count
;
794 * Compute the GMCH and Link ratios. The '3' here is
795 * the number of bytes_per_pixel post-LUT, which we always
796 * set up for 8-bits of R/G/B, or 3 bytes total.
798 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
799 mode
->clock
, adjusted_mode
->clock
, &m_n
);
801 if (HAS_PCH_SPLIT(dev
)) {
802 I915_WRITE(TRANSDATA_M1(pipe
),
803 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
805 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
806 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
807 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
808 } else if (IS_VALLEYVIEW(dev
)) {
809 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
810 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
811 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
812 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
814 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
815 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
817 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
818 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
819 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
824 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
825 struct drm_display_mode
*adjusted_mode
)
827 struct drm_device
*dev
= encoder
->dev
;
828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
829 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
830 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
831 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
834 * There are four kinds of DP registers:
841 * IBX PCH and CPU are the same for almost everything,
842 * except that the CPU DP PLL is configured in this
845 * CPT PCH is quite different, having many bits moved
846 * to the TRANS_DP_CTL register instead. That
847 * configuration happens (oddly) in ironlake_pch_enable
850 /* Preserve the BIOS-computed detected bit. This is
851 * supposed to be read-only.
853 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
855 /* Handle DP bits in common between all three register formats */
856 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
858 switch (intel_dp
->lane_count
) {
860 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
863 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
866 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
869 if (intel_dp
->has_audio
) {
870 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
871 pipe_name(intel_crtc
->pipe
));
872 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
873 intel_write_eld(encoder
, adjusted_mode
);
875 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
876 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
877 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
878 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
880 * Check for DPCD version > 1.1 and enhanced framing support
882 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
883 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
884 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
887 /* Split out the IBX/CPU vs CPT settings */
889 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
890 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
891 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
892 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
893 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
894 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
896 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
897 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
899 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
901 /* don't miss out required setting for eDP */
902 if (adjusted_mode
->clock
< 200000)
903 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
905 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
906 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
907 intel_dp
->DP
|= intel_dp
->color_range
;
909 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
910 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
911 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
912 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
913 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
915 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
916 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
918 if (intel_crtc
->pipe
== 1)
919 intel_dp
->DP
|= DP_PIPEB_SELECT
;
921 if (is_cpu_edp(intel_dp
)) {
922 /* don't miss out required setting for eDP */
923 if (adjusted_mode
->clock
< 200000)
924 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
926 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
929 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
933 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
934 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
936 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
937 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
939 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
940 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
942 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
946 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
949 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
951 I915_READ(PCH_PP_STATUS
),
952 I915_READ(PCH_PP_CONTROL
));
954 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
955 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
956 I915_READ(PCH_PP_STATUS
),
957 I915_READ(PCH_PP_CONTROL
));
961 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
963 DRM_DEBUG_KMS("Wait for panel power on\n");
964 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
967 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
969 DRM_DEBUG_KMS("Wait for panel power off time\n");
970 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
973 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
975 DRM_DEBUG_KMS("Wait for panel power cycle\n");
976 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
980 /* Read the current pp_control value, unlocking the register if it
984 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
986 u32 control
= I915_READ(PCH_PP_CONTROL
);
988 control
&= ~PANEL_UNLOCK_MASK
;
989 control
|= PANEL_UNLOCK_REGS
;
993 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
995 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
999 if (!is_edp(intel_dp
))
1001 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1003 WARN(intel_dp
->want_panel_vdd
,
1004 "eDP VDD already requested on\n");
1006 intel_dp
->want_panel_vdd
= true;
1008 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1009 DRM_DEBUG_KMS("eDP VDD already on\n");
1013 if (!ironlake_edp_have_panel_power(intel_dp
))
1014 ironlake_wait_panel_power_cycle(intel_dp
);
1016 pp
= ironlake_get_pp_control(dev_priv
);
1017 pp
|= EDP_FORCE_VDD
;
1018 I915_WRITE(PCH_PP_CONTROL
, pp
);
1019 POSTING_READ(PCH_PP_CONTROL
);
1020 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1021 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1024 * If the panel wasn't on, delay before accessing aux channel
1026 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1027 DRM_DEBUG_KMS("eDP was not running\n");
1028 msleep(intel_dp
->panel_power_up_delay
);
1032 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1034 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1038 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1039 pp
= ironlake_get_pp_control(dev_priv
);
1040 pp
&= ~EDP_FORCE_VDD
;
1041 I915_WRITE(PCH_PP_CONTROL
, pp
);
1042 POSTING_READ(PCH_PP_CONTROL
);
1044 /* Make sure sequencer is idle before allowing subsequent activity */
1045 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1046 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1048 msleep(intel_dp
->panel_power_down_delay
);
1052 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1054 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1055 struct intel_dp
, panel_vdd_work
);
1056 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1058 mutex_lock(&dev
->mode_config
.mutex
);
1059 ironlake_panel_vdd_off_sync(intel_dp
);
1060 mutex_unlock(&dev
->mode_config
.mutex
);
1063 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1065 if (!is_edp(intel_dp
))
1068 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1069 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1071 intel_dp
->want_panel_vdd
= false;
1074 ironlake_panel_vdd_off_sync(intel_dp
);
1077 * Queue the timer to fire a long
1078 * time from now (relative to the power down delay)
1079 * to keep the panel power up across a sequence of operations
1081 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1082 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1086 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1088 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1092 if (!is_edp(intel_dp
))
1095 DRM_DEBUG_KMS("Turn eDP power on\n");
1097 if (ironlake_edp_have_panel_power(intel_dp
)) {
1098 DRM_DEBUG_KMS("eDP power already on\n");
1102 ironlake_wait_panel_power_cycle(intel_dp
);
1104 pp
= ironlake_get_pp_control(dev_priv
);
1106 /* ILK workaround: disable reset around power sequence */
1107 pp
&= ~PANEL_POWER_RESET
;
1108 I915_WRITE(PCH_PP_CONTROL
, pp
);
1109 POSTING_READ(PCH_PP_CONTROL
);
1112 pp
|= POWER_TARGET_ON
;
1114 pp
|= PANEL_POWER_RESET
;
1116 I915_WRITE(PCH_PP_CONTROL
, pp
);
1117 POSTING_READ(PCH_PP_CONTROL
);
1119 ironlake_wait_panel_on(intel_dp
);
1122 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1123 I915_WRITE(PCH_PP_CONTROL
, pp
);
1124 POSTING_READ(PCH_PP_CONTROL
);
1128 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1130 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1134 if (!is_edp(intel_dp
))
1137 DRM_DEBUG_KMS("Turn eDP power off\n");
1139 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1141 pp
= ironlake_get_pp_control(dev_priv
);
1142 /* We need to switch off panel power _and_ force vdd, for otherwise some
1143 * panels get very unhappy and cease to work. */
1144 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1145 I915_WRITE(PCH_PP_CONTROL
, pp
);
1146 POSTING_READ(PCH_PP_CONTROL
);
1148 intel_dp
->want_panel_vdd
= false;
1150 ironlake_wait_panel_off(intel_dp
);
1153 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1155 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1159 if (!is_edp(intel_dp
))
1162 DRM_DEBUG_KMS("\n");
1164 * If we enable the backlight right away following a panel power
1165 * on, we may see slight flicker as the panel syncs with the eDP
1166 * link. So delay a bit to make sure the image is solid before
1167 * allowing it to appear.
1169 msleep(intel_dp
->backlight_on_delay
);
1170 pp
= ironlake_get_pp_control(dev_priv
);
1171 pp
|= EDP_BLC_ENABLE
;
1172 I915_WRITE(PCH_PP_CONTROL
, pp
);
1173 POSTING_READ(PCH_PP_CONTROL
);
1176 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1178 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1182 if (!is_edp(intel_dp
))
1185 DRM_DEBUG_KMS("\n");
1186 pp
= ironlake_get_pp_control(dev_priv
);
1187 pp
&= ~EDP_BLC_ENABLE
;
1188 I915_WRITE(PCH_PP_CONTROL
, pp
);
1189 POSTING_READ(PCH_PP_CONTROL
);
1190 msleep(intel_dp
->backlight_off_delay
);
1193 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1195 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1196 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1200 assert_pipe_disabled(dev_priv
,
1201 to_intel_crtc(crtc
)->pipe
);
1203 DRM_DEBUG_KMS("\n");
1204 dpa_ctl
= I915_READ(DP_A
);
1205 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1206 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1208 /* We don't adjust intel_dp->DP while tearing down the link, to
1209 * facilitate link retraining (e.g. after hotplug). Hence clear all
1210 * enable bits here to ensure that we don't enable too much. */
1211 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1212 intel_dp
->DP
|= DP_PLL_ENABLE
;
1213 I915_WRITE(DP_A
, intel_dp
->DP
);
1218 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1220 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1221 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 assert_pipe_disabled(dev_priv
,
1226 to_intel_crtc(crtc
)->pipe
);
1228 dpa_ctl
= I915_READ(DP_A
);
1229 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1230 "dp pll off, should be on\n");
1231 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1233 /* We can't rely on the value tracked for the DP register in
1234 * intel_dp->DP because link_down must not change that (otherwise link
1235 * re-training will fail. */
1236 dpa_ctl
&= ~DP_PLL_ENABLE
;
1237 I915_WRITE(DP_A
, dpa_ctl
);
1242 /* If the sink supports it, try to set the power state appropriately */
1243 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1247 /* Should have a valid DPCD by this point */
1248 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1251 if (mode
!= DRM_MODE_DPMS_ON
) {
1252 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1255 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1258 * When turning on, we need to retry for 1ms to give the sink
1261 for (i
= 0; i
< 3; i
++) {
1262 ret
= intel_dp_aux_native_write_1(intel_dp
,
1272 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1275 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1276 struct drm_device
*dev
= encoder
->base
.dev
;
1277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1278 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1280 if (!(tmp
& DP_PORT_EN
))
1283 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1284 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1285 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1286 *pipe
= PORT_TO_PIPE(tmp
);
1292 switch (intel_dp
->output_reg
) {
1294 trans_sel
= TRANS_DP_PORT_SEL_B
;
1297 trans_sel
= TRANS_DP_PORT_SEL_C
;
1300 trans_sel
= TRANS_DP_PORT_SEL_D
;
1307 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1308 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1315 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1320 static void intel_disable_dp(struct intel_encoder
*encoder
)
1322 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1324 /* Make sure the panel is off before trying to change the mode. But also
1325 * ensure that we have vdd while we switch off the panel. */
1326 ironlake_edp_panel_vdd_on(intel_dp
);
1327 ironlake_edp_backlight_off(intel_dp
);
1328 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1329 ironlake_edp_panel_off(intel_dp
);
1331 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1332 if (!is_cpu_edp(intel_dp
))
1333 intel_dp_link_down(intel_dp
);
1336 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1338 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1340 if (is_cpu_edp(intel_dp
)) {
1341 intel_dp_link_down(intel_dp
);
1342 ironlake_edp_pll_off(intel_dp
);
1346 static void intel_enable_dp(struct intel_encoder
*encoder
)
1348 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1349 struct drm_device
*dev
= encoder
->base
.dev
;
1350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1351 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1353 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1356 ironlake_edp_panel_vdd_on(intel_dp
);
1357 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1358 intel_dp_start_link_train(intel_dp
);
1359 ironlake_edp_panel_on(intel_dp
);
1360 ironlake_edp_panel_vdd_off(intel_dp
, true);
1361 intel_dp_complete_link_train(intel_dp
);
1362 ironlake_edp_backlight_on(intel_dp
);
1365 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1367 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1369 if (is_cpu_edp(intel_dp
))
1370 ironlake_edp_pll_on(intel_dp
);
1374 * Native read with retry for link status and receiver capability reads for
1375 * cases where the sink may still be asleep.
1378 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1379 uint8_t *recv
, int recv_bytes
)
1384 * Sinks are *supposed* to come up within 1ms from an off state,
1385 * but we're also supposed to retry 3 times per the spec.
1387 for (i
= 0; i
< 3; i
++) {
1388 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1390 if (ret
== recv_bytes
)
1399 * Fetch AUX CH registers 0x202 - 0x207 which contain
1400 * link status information
1403 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1405 return intel_dp_aux_native_read_retry(intel_dp
,
1408 DP_LINK_STATUS_SIZE
);
1412 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1415 return link_status
[r
- DP_LANE0_1_STATUS
];
1419 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1422 int s
= ((lane
& 1) ?
1423 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1424 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1425 uint8_t l
= adjust_request
[lane
>>1];
1427 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1431 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1434 int s
= ((lane
& 1) ?
1435 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1436 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1437 uint8_t l
= adjust_request
[lane
>>1];
1439 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1444 static char *voltage_names
[] = {
1445 "0.4V", "0.6V", "0.8V", "1.2V"
1447 static char *pre_emph_names
[] = {
1448 "0dB", "3.5dB", "6dB", "9.5dB"
1450 static char *link_train_names
[] = {
1451 "pattern 1", "pattern 2", "idle", "off"
1456 * These are source-specific values; current Intel hardware supports
1457 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1461 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1463 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1465 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1466 return DP_TRAIN_VOLTAGE_SWING_800
;
1467 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1468 return DP_TRAIN_VOLTAGE_SWING_1200
;
1470 return DP_TRAIN_VOLTAGE_SWING_800
;
1474 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1476 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1478 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1479 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1480 case DP_TRAIN_VOLTAGE_SWING_400
:
1481 return DP_TRAIN_PRE_EMPHASIS_6
;
1482 case DP_TRAIN_VOLTAGE_SWING_600
:
1483 case DP_TRAIN_VOLTAGE_SWING_800
:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1486 return DP_TRAIN_PRE_EMPHASIS_0
;
1489 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1490 case DP_TRAIN_VOLTAGE_SWING_400
:
1491 return DP_TRAIN_PRE_EMPHASIS_6
;
1492 case DP_TRAIN_VOLTAGE_SWING_600
:
1493 return DP_TRAIN_PRE_EMPHASIS_6
;
1494 case DP_TRAIN_VOLTAGE_SWING_800
:
1495 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1496 case DP_TRAIN_VOLTAGE_SWING_1200
:
1498 return DP_TRAIN_PRE_EMPHASIS_0
;
1504 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1509 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1510 uint8_t voltage_max
;
1511 uint8_t preemph_max
;
1513 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1514 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1515 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1523 voltage_max
= intel_dp_voltage_max(intel_dp
);
1524 if (v
>= voltage_max
)
1525 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1527 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1528 if (p
>= preemph_max
)
1529 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1531 for (lane
= 0; lane
< 4; lane
++)
1532 intel_dp
->train_set
[lane
] = v
| p
;
1536 intel_dp_signal_levels(uint8_t train_set
)
1538 uint32_t signal_levels
= 0;
1540 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1541 case DP_TRAIN_VOLTAGE_SWING_400
:
1543 signal_levels
|= DP_VOLTAGE_0_4
;
1545 case DP_TRAIN_VOLTAGE_SWING_600
:
1546 signal_levels
|= DP_VOLTAGE_0_6
;
1548 case DP_TRAIN_VOLTAGE_SWING_800
:
1549 signal_levels
|= DP_VOLTAGE_0_8
;
1551 case DP_TRAIN_VOLTAGE_SWING_1200
:
1552 signal_levels
|= DP_VOLTAGE_1_2
;
1555 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1556 case DP_TRAIN_PRE_EMPHASIS_0
:
1558 signal_levels
|= DP_PRE_EMPHASIS_0
;
1560 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1561 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1563 case DP_TRAIN_PRE_EMPHASIS_6
:
1564 signal_levels
|= DP_PRE_EMPHASIS_6
;
1566 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1567 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1570 return signal_levels
;
1573 /* Gen6's DP voltage swing and pre-emphasis control */
1575 intel_gen6_edp_signal_levels(uint8_t train_set
)
1577 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1578 DP_TRAIN_PRE_EMPHASIS_MASK
);
1579 switch (signal_levels
) {
1580 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1581 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1582 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1583 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1584 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1585 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1586 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1587 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1588 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1589 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1590 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1591 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1592 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1593 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1595 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1596 "0x%x\n", signal_levels
);
1597 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1601 /* Gen7's DP voltage swing and pre-emphasis control */
1603 intel_gen7_edp_signal_levels(uint8_t train_set
)
1605 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1606 DP_TRAIN_PRE_EMPHASIS_MASK
);
1607 switch (signal_levels
) {
1608 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1609 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1610 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1611 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1612 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1613 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1615 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1616 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1617 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1618 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1620 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1621 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1622 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1623 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1626 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1627 "0x%x\n", signal_levels
);
1628 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1633 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1636 int s
= (lane
& 1) * 4;
1637 uint8_t l
= link_status
[lane
>>1];
1639 return (l
>> s
) & 0xf;
1642 /* Check for clock recovery is done on all channels */
1644 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1647 uint8_t lane_status
;
1649 for (lane
= 0; lane
< lane_count
; lane
++) {
1650 lane_status
= intel_get_lane_status(link_status
, lane
);
1651 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1657 /* Check to see if channel eq is done on all channels */
1658 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1659 DP_LANE_CHANNEL_EQ_DONE|\
1660 DP_LANE_SYMBOL_LOCKED)
1662 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1665 uint8_t lane_status
;
1668 lane_align
= intel_dp_link_status(link_status
,
1669 DP_LANE_ALIGN_STATUS_UPDATED
);
1670 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1672 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1673 lane_status
= intel_get_lane_status(link_status
, lane
);
1674 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1681 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1682 uint32_t dp_reg_value
,
1683 uint8_t dp_train_pat
)
1685 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1689 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1690 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1692 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1693 case DP_TRAINING_PATTERN_DISABLE
:
1694 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1696 case DP_TRAINING_PATTERN_1
:
1697 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1699 case DP_TRAINING_PATTERN_2
:
1700 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1702 case DP_TRAINING_PATTERN_3
:
1703 DRM_ERROR("DP training pattern 3 not supported\n");
1704 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1709 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1711 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1712 case DP_TRAINING_PATTERN_DISABLE
:
1713 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1715 case DP_TRAINING_PATTERN_1
:
1716 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1718 case DP_TRAINING_PATTERN_2
:
1719 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1721 case DP_TRAINING_PATTERN_3
:
1722 DRM_ERROR("DP training pattern 3 not supported\n");
1723 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1728 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1729 POSTING_READ(intel_dp
->output_reg
);
1731 intel_dp_aux_native_write_1(intel_dp
,
1732 DP_TRAINING_PATTERN_SET
,
1735 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1736 DP_TRAINING_PATTERN_DISABLE
) {
1737 ret
= intel_dp_aux_native_write(intel_dp
,
1738 DP_TRAINING_LANE0_SET
,
1739 intel_dp
->train_set
,
1740 intel_dp
->lane_count
);
1741 if (ret
!= intel_dp
->lane_count
)
1748 /* Enable corresponding port and start training pattern 1 */
1750 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1752 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1755 bool clock_recovery
= false;
1756 int voltage_tries
, loop_tries
;
1757 uint32_t DP
= intel_dp
->DP
;
1759 /* Write the link configuration data */
1760 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1761 intel_dp
->link_configuration
,
1762 DP_LINK_CONFIGURATION_SIZE
);
1766 memset(intel_dp
->train_set
, 0, 4);
1770 clock_recovery
= false;
1772 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1773 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1774 uint32_t signal_levels
;
1777 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1778 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1779 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1780 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1781 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1782 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1784 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1785 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1786 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1789 if (!intel_dp_set_link_train(intel_dp
, DP
,
1790 DP_TRAINING_PATTERN_1
|
1791 DP_LINK_SCRAMBLING_DISABLE
))
1793 /* Set training pattern 1 */
1796 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1797 DRM_ERROR("failed to get link status\n");
1801 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1802 DRM_DEBUG_KMS("clock recovery OK\n");
1803 clock_recovery
= true;
1807 /* Check to see if we've tried the max voltage */
1808 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1809 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1811 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1813 if (loop_tries
== 5) {
1814 DRM_DEBUG_KMS("too many full retries, give up\n");
1817 memset(intel_dp
->train_set
, 0, 4);
1822 /* Check to see if we've tried the same voltage 5 times */
1823 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1825 if (voltage_tries
== 5) {
1826 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1831 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1833 /* Compute new intel_dp->train_set as requested by target */
1834 intel_get_adjust_train(intel_dp
, link_status
);
1841 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1843 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1844 bool channel_eq
= false;
1845 int tries
, cr_tries
;
1846 uint32_t DP
= intel_dp
->DP
;
1848 /* channel equalization */
1853 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1854 uint32_t signal_levels
;
1855 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1858 DRM_ERROR("failed to train DP, aborting\n");
1859 intel_dp_link_down(intel_dp
);
1863 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1864 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1865 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1866 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1867 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1868 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1870 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1871 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1874 /* channel eq pattern */
1875 if (!intel_dp_set_link_train(intel_dp
, DP
,
1876 DP_TRAINING_PATTERN_2
|
1877 DP_LINK_SCRAMBLING_DISABLE
))
1881 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1884 /* Make sure clock is still ok */
1885 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1886 intel_dp_start_link_train(intel_dp
);
1891 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1896 /* Try 5 times, then try clock recovery if that fails */
1898 intel_dp_link_down(intel_dp
);
1899 intel_dp_start_link_train(intel_dp
);
1905 /* Compute new intel_dp->train_set as requested by target */
1906 intel_get_adjust_train(intel_dp
, link_status
);
1910 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1914 intel_dp_link_down(struct intel_dp
*intel_dp
)
1916 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 uint32_t DP
= intel_dp
->DP
;
1920 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
1923 DRM_DEBUG_KMS("\n");
1925 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1926 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1927 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1929 DP
&= ~DP_LINK_TRAIN_MASK
;
1930 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1932 POSTING_READ(intel_dp
->output_reg
);
1936 if (HAS_PCH_IBX(dev
) &&
1937 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1938 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1940 /* Hardware workaround: leaving our transcoder select
1941 * set to transcoder B while it's off will prevent the
1942 * corresponding HDMI output on transcoder A.
1944 * Combine this with another hardware workaround:
1945 * transcoder select bit can only be cleared while the
1948 DP
&= ~DP_PIPEB_SELECT
;
1949 I915_WRITE(intel_dp
->output_reg
, DP
);
1951 /* Changes to enable or select take place the vblank
1952 * after being written.
1955 /* We can arrive here never having been attached
1956 * to a CRTC, for instance, due to inheriting
1957 * random state from the BIOS.
1959 * If the pipe is not running, play safe and
1960 * wait for the clocks to stabilise before
1963 POSTING_READ(intel_dp
->output_reg
);
1966 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1969 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
1970 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1971 POSTING_READ(intel_dp
->output_reg
);
1972 msleep(intel_dp
->panel_power_down_delay
);
1976 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1978 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1979 sizeof(intel_dp
->dpcd
)) == 0)
1980 return false; /* aux transfer failed */
1982 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
1983 return false; /* DPCD not present */
1985 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
1986 DP_DWN_STRM_PORT_PRESENT
))
1987 return true; /* native DP sink */
1989 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
1990 return true; /* no per-port downstream info */
1992 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
1993 intel_dp
->downstream_ports
,
1994 DP_MAX_DOWNSTREAM_PORTS
) == 0)
1995 return false; /* downstream port status fetch failed */
2001 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2005 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2008 ironlake_edp_panel_vdd_on(intel_dp
);
2010 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2011 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2012 buf
[0], buf
[1], buf
[2]);
2014 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2015 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2016 buf
[0], buf
[1], buf
[2]);
2018 ironlake_edp_panel_vdd_off(intel_dp
, false);
2022 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2026 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2027 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2028 sink_irq_vector
, 1);
2036 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2038 /* NAK by default */
2039 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2043 * According to DP spec
2046 * 2. Configure link according to Receiver Capabilities
2047 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2048 * 4. Check link status on receipt of hot-plug interrupt
2052 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2055 u8 link_status
[DP_LINK_STATUS_SIZE
];
2057 if (!intel_dp
->base
.connectors_active
)
2060 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2063 /* Try to read receiver status if the link appears to be up */
2064 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2065 intel_dp_link_down(intel_dp
);
2069 /* Now read the DPCD to see if it's actually running */
2070 if (!intel_dp_get_dpcd(intel_dp
)) {
2071 intel_dp_link_down(intel_dp
);
2075 /* Try to read the source of the interrupt */
2076 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2077 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2078 /* Clear interrupt source */
2079 intel_dp_aux_native_write_1(intel_dp
,
2080 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2083 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2084 intel_dp_handle_test_request(intel_dp
);
2085 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2086 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2089 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2090 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2091 drm_get_encoder_name(&intel_dp
->base
.base
));
2092 intel_dp_start_link_train(intel_dp
);
2093 intel_dp_complete_link_train(intel_dp
);
2097 /* XXX this is probably wrong for multiple downstream ports */
2098 static enum drm_connector_status
2099 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2101 uint8_t *dpcd
= intel_dp
->dpcd
;
2105 if (!intel_dp_get_dpcd(intel_dp
))
2106 return connector_status_disconnected
;
2108 /* if there's no downstream port, we're done */
2109 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2110 return connector_status_connected
;
2112 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2113 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2116 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2118 return connector_status_unknown
;
2119 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2120 : connector_status_disconnected
;
2123 /* If no HPD, poke DDC gently */
2124 if (drm_probe_ddc(&intel_dp
->adapter
))
2125 return connector_status_connected
;
2127 /* Well we tried, say unknown for unreliable port types */
2128 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2129 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2130 return connector_status_unknown
;
2132 /* Anything else is out of spec, warn and ignore */
2133 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2134 return connector_status_disconnected
;
2137 static enum drm_connector_status
2138 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2140 enum drm_connector_status status
;
2142 /* Can't disconnect eDP, but you can close the lid... */
2143 if (is_edp(intel_dp
)) {
2144 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2145 if (status
== connector_status_unknown
)
2146 status
= connector_status_connected
;
2150 return intel_dp_detect_dpcd(intel_dp
);
2153 static enum drm_connector_status
2154 g4x_dp_detect(struct intel_dp
*intel_dp
)
2156 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2160 switch (intel_dp
->output_reg
) {
2162 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2165 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2168 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2171 return connector_status_unknown
;
2174 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2175 return connector_status_disconnected
;
2177 return intel_dp_detect_dpcd(intel_dp
);
2180 static struct edid
*
2181 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2183 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2187 if (is_edp(intel_dp
)) {
2188 if (!intel_dp
->edid
)
2191 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2192 edid
= kmalloc(size
, GFP_KERNEL
);
2196 memcpy(edid
, intel_dp
->edid
, size
);
2200 edid
= drm_get_edid(connector
, adapter
);
2205 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2207 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2210 if (is_edp(intel_dp
)) {
2211 drm_mode_connector_update_edid_property(connector
,
2213 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2214 drm_edid_to_eld(connector
,
2216 return intel_dp
->edid_mode_count
;
2219 ret
= intel_ddc_get_modes(connector
, adapter
);
2225 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2227 * \return true if DP port is connected.
2228 * \return false if DP port is disconnected.
2230 static enum drm_connector_status
2231 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2233 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2234 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2235 enum drm_connector_status status
;
2236 struct edid
*edid
= NULL
;
2238 intel_dp
->has_audio
= false;
2240 if (HAS_PCH_SPLIT(dev
))
2241 status
= ironlake_dp_detect(intel_dp
);
2243 status
= g4x_dp_detect(intel_dp
);
2245 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2246 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2247 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2248 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2250 if (status
!= connector_status_connected
)
2253 intel_dp_probe_oui(intel_dp
);
2255 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2256 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2258 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2260 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2265 return connector_status_connected
;
2268 static int intel_dp_get_modes(struct drm_connector
*connector
)
2270 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2271 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 /* We should parse the EDID data and find out if it has an audio sink
2278 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2280 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2281 struct drm_display_mode
*newmode
;
2282 list_for_each_entry(newmode
, &connector
->probed_modes
,
2284 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2285 intel_dp
->panel_fixed_mode
=
2286 drm_mode_duplicate(dev
, newmode
);
2294 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2295 if (is_edp(intel_dp
)) {
2296 /* initialize panel mode from VBT if available for eDP */
2297 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2298 intel_dp
->panel_fixed_mode
=
2299 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2300 if (intel_dp
->panel_fixed_mode
) {
2301 intel_dp
->panel_fixed_mode
->type
|=
2302 DRM_MODE_TYPE_PREFERRED
;
2305 if (intel_dp
->panel_fixed_mode
) {
2306 struct drm_display_mode
*mode
;
2307 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2308 drm_mode_probed_add(connector
, mode
);
2316 intel_dp_detect_audio(struct drm_connector
*connector
)
2318 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2320 bool has_audio
= false;
2322 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2324 has_audio
= drm_detect_monitor_audio(edid
);
2332 intel_dp_set_property(struct drm_connector
*connector
,
2333 struct drm_property
*property
,
2336 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2337 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2340 ret
= drm_connector_property_set_value(connector
, property
, val
);
2344 if (property
== dev_priv
->force_audio_property
) {
2348 if (i
== intel_dp
->force_audio
)
2351 intel_dp
->force_audio
= i
;
2353 if (i
== HDMI_AUDIO_AUTO
)
2354 has_audio
= intel_dp_detect_audio(connector
);
2356 has_audio
= (i
== HDMI_AUDIO_ON
);
2358 if (has_audio
== intel_dp
->has_audio
)
2361 intel_dp
->has_audio
= has_audio
;
2365 if (property
== dev_priv
->broadcast_rgb_property
) {
2366 if (val
== !!intel_dp
->color_range
)
2369 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2376 if (intel_dp
->base
.base
.crtc
) {
2377 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2378 intel_set_mode(crtc
, &crtc
->mode
,
2379 crtc
->x
, crtc
->y
, crtc
->fb
);
2386 intel_dp_destroy(struct drm_connector
*connector
)
2388 struct drm_device
*dev
= connector
->dev
;
2390 if (intel_dpd_is_edp(dev
))
2391 intel_panel_destroy_backlight(dev
);
2393 drm_sysfs_connector_remove(connector
);
2394 drm_connector_cleanup(connector
);
2398 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2400 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2402 i2c_del_adapter(&intel_dp
->adapter
);
2403 drm_encoder_cleanup(encoder
);
2404 if (is_edp(intel_dp
)) {
2405 kfree(intel_dp
->edid
);
2406 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2407 ironlake_panel_vdd_off_sync(intel_dp
);
2412 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2413 .mode_fixup
= intel_dp_mode_fixup
,
2414 .mode_set
= intel_dp_mode_set
,
2415 .disable
= intel_encoder_noop
,
2418 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2419 .dpms
= intel_connector_dpms
,
2420 .detect
= intel_dp_detect
,
2421 .fill_modes
= drm_helper_probe_single_connector_modes
,
2422 .set_property
= intel_dp_set_property
,
2423 .destroy
= intel_dp_destroy
,
2426 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2427 .get_modes
= intel_dp_get_modes
,
2428 .mode_valid
= intel_dp_mode_valid
,
2429 .best_encoder
= intel_best_encoder
,
2432 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2433 .destroy
= intel_dp_encoder_destroy
,
2437 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2439 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2441 intel_dp_check_link_status(intel_dp
);
2444 /* Return which DP Port should be selected for Transcoder DP control */
2446 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2448 struct drm_device
*dev
= crtc
->dev
;
2449 struct intel_encoder
*encoder
;
2451 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2452 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2454 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2455 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2456 return intel_dp
->output_reg
;
2462 /* check the VBT to see whether the eDP is on DP-D port */
2463 bool intel_dpd_is_edp(struct drm_device
*dev
)
2465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2466 struct child_device_config
*p_child
;
2469 if (!dev_priv
->child_dev_num
)
2472 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2473 p_child
= dev_priv
->child_dev
+ i
;
2475 if (p_child
->dvo_port
== PORT_IDPD
&&
2476 p_child
->device_type
== DEVICE_TYPE_eDP
)
2483 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2485 intel_attach_force_audio_property(connector
);
2486 intel_attach_broadcast_rgb_property(connector
);
2490 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2493 struct drm_connector
*connector
;
2494 struct intel_dp
*intel_dp
;
2495 struct intel_encoder
*intel_encoder
;
2496 struct intel_connector
*intel_connector
;
2497 const char *name
= NULL
;
2500 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2504 intel_dp
->output_reg
= output_reg
;
2505 intel_dp
->port
= port
;
2506 /* Preserve the current hw state. */
2507 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2509 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2510 if (!intel_connector
) {
2514 intel_encoder
= &intel_dp
->base
;
2516 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2517 if (intel_dpd_is_edp(dev
))
2518 intel_dp
->is_pch_edp
= true;
2521 * FIXME : We need to initialize built-in panels before external panels.
2522 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2524 if (IS_VALLEYVIEW(dev
) && output_reg
== DP_C
) {
2525 type
= DRM_MODE_CONNECTOR_eDP
;
2526 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2527 } else if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2528 type
= DRM_MODE_CONNECTOR_eDP
;
2529 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2531 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2532 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2535 connector
= &intel_connector
->base
;
2536 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2537 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2539 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2541 intel_encoder
->cloneable
= false;
2543 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2544 ironlake_panel_vdd_work
);
2546 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2548 connector
->interlace_allowed
= true;
2549 connector
->doublescan_allowed
= 0;
2551 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2552 DRM_MODE_ENCODER_TMDS
);
2553 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2555 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2556 drm_sysfs_connector_add(connector
);
2558 intel_encoder
->enable
= intel_enable_dp
;
2559 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2560 intel_encoder
->disable
= intel_disable_dp
;
2561 intel_encoder
->post_disable
= intel_post_disable_dp
;
2562 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2563 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2565 /* Set up the DDC bus. */
2571 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2575 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2579 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2583 WARN(1, "Invalid port %c\n", port_name(port
));
2587 /* Cache some DPCD data in the eDP case */
2588 if (is_edp(intel_dp
)) {
2589 struct edp_power_seq cur
, vbt
;
2590 u32 pp_on
, pp_off
, pp_div
;
2592 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2593 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2594 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2596 if (!pp_on
|| !pp_off
|| !pp_div
) {
2597 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2598 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2599 intel_dp_destroy(&intel_connector
->base
);
2603 /* Pull timing values out of registers */
2604 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2605 PANEL_POWER_UP_DELAY_SHIFT
;
2607 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2608 PANEL_LIGHT_ON_DELAY_SHIFT
;
2610 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2611 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2613 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2614 PANEL_POWER_DOWN_DELAY_SHIFT
;
2616 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2617 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2619 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2620 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2622 vbt
= dev_priv
->edp
.pps
;
2624 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2625 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2627 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2629 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2630 intel_dp
->backlight_on_delay
= get_delay(t8
);
2631 intel_dp
->backlight_off_delay
= get_delay(t9
);
2632 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2633 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2635 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2636 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2637 intel_dp
->panel_power_cycle_delay
);
2639 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2640 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2643 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2645 if (is_edp(intel_dp
)) {
2649 ironlake_edp_panel_vdd_on(intel_dp
);
2650 ret
= intel_dp_get_dpcd(intel_dp
);
2651 ironlake_edp_panel_vdd_off(intel_dp
, false);
2654 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2655 dev_priv
->no_aux_handshake
=
2656 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2657 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2659 /* if this fails, presume the device is a ghost */
2660 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2661 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2662 intel_dp_destroy(&intel_connector
->base
);
2666 ironlake_edp_panel_vdd_on(intel_dp
);
2667 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2669 drm_mode_connector_update_edid_property(connector
,
2671 intel_dp
->edid_mode_count
=
2672 drm_add_edid_modes(connector
, edid
);
2673 drm_edid_to_eld(connector
, edid
);
2674 intel_dp
->edid
= edid
;
2676 ironlake_edp_panel_vdd_off(intel_dp
, false);
2679 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2681 if (is_edp(intel_dp
)) {
2682 dev_priv
->int_edp_connector
= connector
;
2683 intel_panel_setup_backlight(dev
);
2686 intel_dp_add_properties(intel_dp
, connector
);
2688 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2689 * 0xd. Failure to do so will result in spurious interrupts being
2690 * generated on the port when a cable is not attached.
2692 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2693 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2694 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);