2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
36 #include "intel_drv.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
50 static bool is_edp(struct intel_dp
*intel_dp
)
52 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp
*intel_dp
)
65 return intel_dp
->is_pch_edp
;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
76 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
79 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
81 return container_of(encoder
, struct intel_dp
, base
.base
);
84 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
86 return container_of(intel_attached_encoder(connector
),
87 struct intel_dp
, base
);
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
97 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
99 struct intel_dp
*intel_dp
;
104 intel_dp
= enc_to_intel_dp(encoder
);
106 return is_pch_edp(intel_dp
);
109 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
110 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
111 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
115 int *lane_num
, int *link_bw
)
117 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
119 *lane_num
= intel_dp
->lane_count
;
120 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
122 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
127 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
128 struct drm_display_mode
*mode
)
130 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
132 if (intel_dp
->panel_fixed_mode
)
133 return intel_dp
->panel_fixed_mode
->clock
;
139 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
141 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
142 switch (max_lane_count
) {
143 case 1: case 2: case 4:
148 return max_lane_count
;
152 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
154 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
156 switch (max_link_bw
) {
157 case DP_LINK_BW_1_62
:
161 max_link_bw
= DP_LINK_BW_1_62
;
168 intel_dp_link_clock(uint8_t link_bw
)
170 if (link_bw
== DP_LINK_BW_2_7
)
177 * The units on the numbers in the next two are... bizarre. Examples will
178 * make it clearer; this one parallels an example in the eDP spec.
180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
182 * 270000 * 1 * 8 / 10 == 216000
184 * The actual data capacity of that configuration is 2.16Gbit/s, so the
185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
187 * 119000. At 18bpp that's 2142000 kilobits per second.
189 * Thus the strange-looking division by 10 in intel_dp_link_required, to
190 * get the result in decakilobits instead of kilobits.
194 intel_dp_link_required(int pixel_clock
, int bpp
)
196 return (pixel_clock
* bpp
+ 9) / 10;
200 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
202 return (max_link_clock
* max_lanes
* 8) / 10;
206 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
207 struct drm_display_mode
*mode
,
210 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
211 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 int max_rate
, mode_rate
;
214 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
215 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
217 if (mode_rate
> max_rate
) {
218 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
219 if (mode_rate
> max_rate
)
224 |= INTEL_MODE_DP_FORCE_6BPC
;
233 intel_dp_mode_valid(struct drm_connector
*connector
,
234 struct drm_display_mode
*mode
)
236 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
238 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
239 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
242 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
246 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
247 return MODE_CLOCK_HIGH
;
249 if (mode
->clock
< 10000)
250 return MODE_CLOCK_LOW
;
252 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
253 return MODE_H_ILLEGAL
;
259 pack_aux(uint8_t *src
, int src_bytes
)
266 for (i
= 0; i
< src_bytes
; i
++)
267 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
272 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
277 for (i
= 0; i
< dst_bytes
; i
++)
278 dst
[i
] = src
>> ((3-i
) * 8);
281 /* hrawclock is 1/4 the FSB frequency */
283 intel_hrawclk(struct drm_device
*dev
)
285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
288 clkcfg
= I915_READ(CLKCFG
);
289 switch (clkcfg
& CLKCFG_FSB_MASK
) {
298 case CLKCFG_FSB_1067
:
300 case CLKCFG_FSB_1333
:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600
:
304 case CLKCFG_FSB_1600_ALT
:
311 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
328 intel_dp_check_edp(struct intel_dp
*intel_dp
)
330 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 if (!is_edp(intel_dp
))
335 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS
),
339 I915_READ(PCH_PP_CONTROL
));
344 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
345 uint8_t *send
, int send_bytes
,
346 uint8_t *recv
, int recv_size
)
348 uint32_t output_reg
= intel_dp
->output_reg
;
349 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 uint32_t ch_ctl
= output_reg
+ 0x10;
352 uint32_t ch_data
= ch_ctl
+ 4;
356 uint32_t aux_clock_divider
;
359 intel_dp_check_edp(intel_dp
);
360 /* The clock divider is based off the hrawclk,
361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
364 * Note that PCH attached eDP panels should use a 125MHz input
367 if (is_cpu_edp(intel_dp
)) {
368 if (IS_GEN6(dev
) || IS_GEN7(dev
))
369 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
371 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev
))
373 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
375 aux_clock_divider
= intel_hrawclk(dev
) / 2;
382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status
= I915_READ(ch_ctl
);
385 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
399 for (i
= 0; i
< send_bytes
; i
+= 4)
400 I915_WRITE(ch_data
+ i
,
401 pack_aux(send
+ i
, send_bytes
- i
));
403 /* Send the command and wait for it to complete */
405 DP_AUX_CH_CTL_SEND_BUSY
|
406 DP_AUX_CH_CTL_TIME_OUT_400us
|
407 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
408 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
409 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
412 DP_AUX_CH_CTL_RECEIVE_ERROR
);
414 status
= I915_READ(ch_ctl
);
415 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
420 /* Clear done status and any errors */
424 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
425 DP_AUX_CH_CTL_RECEIVE_ERROR
);
427 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
428 DP_AUX_CH_CTL_RECEIVE_ERROR
))
430 if (status
& DP_AUX_CH_CTL_DONE
)
434 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
439 /* Check for timeout or receive error.
440 * Timeouts occur when the sink is not connected
442 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
447 /* Timeouts occur when the device isn't connected, so they're
448 * "normal" -- don't fill the kernel log with these */
449 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
454 /* Unload any bytes sent back from the other side */
455 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
457 if (recv_bytes
> recv_size
)
458 recv_bytes
= recv_size
;
460 for (i
= 0; i
< recv_bytes
; i
+= 4)
461 unpack_aux(I915_READ(ch_data
+ i
),
462 recv
+ i
, recv_bytes
- i
);
467 /* Write data to the aux channel in native mode */
469 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
470 uint16_t address
, uint8_t *send
, int send_bytes
)
477 intel_dp_check_edp(intel_dp
);
480 msg
[0] = AUX_NATIVE_WRITE
<< 4;
481 msg
[1] = address
>> 8;
482 msg
[2] = address
& 0xff;
483 msg
[3] = send_bytes
- 1;
484 memcpy(&msg
[4], send
, send_bytes
);
485 msg_bytes
= send_bytes
+ 4;
487 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
490 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
492 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
500 /* Write a single byte to the aux channel in native mode */
502 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
503 uint16_t address
, uint8_t byte
)
505 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
508 /* read bytes from a native aux channel */
510 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
511 uint16_t address
, uint8_t *recv
, int recv_bytes
)
520 intel_dp_check_edp(intel_dp
);
521 msg
[0] = AUX_NATIVE_READ
<< 4;
522 msg
[1] = address
>> 8;
523 msg
[2] = address
& 0xff;
524 msg
[3] = recv_bytes
- 1;
527 reply_bytes
= recv_bytes
+ 1;
530 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
537 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
538 memcpy(recv
, reply
+ 1, ret
- 1);
541 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
549 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
550 uint8_t write_byte
, uint8_t *read_byte
)
552 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
553 struct intel_dp
*intel_dp
= container_of(adapter
,
556 uint16_t address
= algo_data
->address
;
564 intel_dp_check_edp(intel_dp
);
565 /* Set up the command byte */
566 if (mode
& MODE_I2C_READ
)
567 msg
[0] = AUX_I2C_READ
<< 4;
569 msg
[0] = AUX_I2C_WRITE
<< 4;
571 if (!(mode
& MODE_I2C_STOP
))
572 msg
[0] |= AUX_I2C_MOT
<< 4;
574 msg
[1] = address
>> 8;
595 for (retry
= 0; retry
< 5; retry
++) {
596 ret
= intel_dp_aux_ch(intel_dp
,
600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
604 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
605 case AUX_NATIVE_REPLY_ACK
:
606 /* I2C-over-AUX Reply field is only valid
607 * when paired with AUX ACK.
610 case AUX_NATIVE_REPLY_NACK
:
611 DRM_DEBUG_KMS("aux_ch native nack\n");
613 case AUX_NATIVE_REPLY_DEFER
:
617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
622 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
623 case AUX_I2C_REPLY_ACK
:
624 if (mode
== MODE_I2C_READ
) {
625 *read_byte
= reply
[1];
627 return reply_bytes
- 1;
628 case AUX_I2C_REPLY_NACK
:
629 DRM_DEBUG_KMS("aux_i2c nack\n");
631 case AUX_I2C_REPLY_DEFER
:
632 DRM_DEBUG_KMS("aux_i2c defer\n");
636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
641 DRM_ERROR("too many retries, giving up\n");
645 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
646 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
649 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
650 struct intel_connector
*intel_connector
, const char *name
)
654 DRM_DEBUG_KMS("i2c_init %s\n", name
);
655 intel_dp
->algo
.running
= false;
656 intel_dp
->algo
.address
= 0;
657 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
659 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
660 intel_dp
->adapter
.owner
= THIS_MODULE
;
661 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
662 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
663 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
664 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
665 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
667 ironlake_edp_panel_vdd_on(intel_dp
);
668 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
669 ironlake_edp_panel_vdd_off(intel_dp
, false);
674 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
675 const struct drm_display_mode
*mode
,
676 struct drm_display_mode
*adjusted_mode
)
678 struct drm_device
*dev
= encoder
->dev
;
679 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
680 int lane_count
, clock
;
681 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
682 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
684 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
686 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
687 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
688 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
689 mode
, adjusted_mode
);
692 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
695 DRM_DEBUG_KMS("DP link computation with max lane count %i "
696 "max bw %02x pixel clock %iKHz\n",
697 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
699 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
702 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
703 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
705 for (clock
= 0; clock
<= max_clock
; clock
++) {
706 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
707 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
709 if (mode_rate
<= link_avail
) {
710 intel_dp
->link_bw
= bws
[clock
];
711 intel_dp
->lane_count
= lane_count
;
712 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
713 DRM_DEBUG_KMS("DP link bw %02x lane "
714 "count %d clock %d bpp %d\n",
715 intel_dp
->link_bw
, intel_dp
->lane_count
,
716 adjusted_mode
->clock
, bpp
);
717 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
718 mode_rate
, link_avail
);
727 struct intel_dp_m_n
{
736 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
738 while (*num
> 0xffffff || *den
> 0xffffff) {
745 intel_dp_compute_m_n(int bpp
,
749 struct intel_dp_m_n
*m_n
)
752 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
753 m_n
->gmch_n
= link_clock
* nlanes
;
754 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
755 m_n
->link_m
= pixel_clock
;
756 m_n
->link_n
= link_clock
;
757 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
761 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
762 struct drm_display_mode
*adjusted_mode
)
764 struct drm_device
*dev
= crtc
->dev
;
765 struct intel_encoder
*encoder
;
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
769 struct intel_dp_m_n m_n
;
770 int pipe
= intel_crtc
->pipe
;
773 * Find the lane count in the intel_encoder private
775 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
776 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
778 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
779 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
781 lane_count
= intel_dp
->lane_count
;
787 * Compute the GMCH and Link ratios. The '3' here is
788 * the number of bytes_per_pixel post-LUT, which we always
789 * set up for 8-bits of R/G/B, or 3 bytes total.
791 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
792 mode
->clock
, adjusted_mode
->clock
, &m_n
);
794 if (HAS_PCH_SPLIT(dev
)) {
795 I915_WRITE(TRANSDATA_M1(pipe
),
796 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
798 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
799 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
800 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
802 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
803 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
805 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
806 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
807 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
811 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
812 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
815 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
816 struct drm_display_mode
*adjusted_mode
)
818 struct drm_device
*dev
= encoder
->dev
;
819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
821 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
822 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
824 /* Turn on the eDP PLL if needed */
825 if (is_edp(intel_dp
)) {
826 if (!is_pch_edp(intel_dp
))
827 ironlake_edp_pll_on(encoder
);
829 ironlake_edp_pll_off(encoder
);
833 * There are four kinds of DP registers:
840 * IBX PCH and CPU are the same for almost everything,
841 * except that the CPU DP PLL is configured in this
844 * CPT PCH is quite different, having many bits moved
845 * to the TRANS_DP_CTL register instead. That
846 * configuration happens (oddly) in ironlake_pch_enable
849 /* Preserve the BIOS-computed detected bit. This is
850 * supposed to be read-only.
852 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
853 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
855 /* Handle DP bits in common between all three register formats */
857 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
859 switch (intel_dp
->lane_count
) {
861 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
864 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
867 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
870 if (intel_dp
->has_audio
) {
871 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
872 pipe_name(intel_crtc
->pipe
));
873 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
874 intel_write_eld(encoder
, adjusted_mode
);
876 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
877 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
878 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
879 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
881 * Check for DPCD version > 1.1 and enhanced framing support
883 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
884 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
885 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
888 /* Split out the IBX/CPU vs CPT settings */
890 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
891 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
892 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
893 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
894 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
895 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
897 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
898 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
900 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
902 /* don't miss out required setting for eDP */
903 intel_dp
->DP
|= DP_PLL_ENABLE
;
904 if (adjusted_mode
->clock
< 200000)
905 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
907 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
908 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
909 intel_dp
->DP
|= intel_dp
->color_range
;
911 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
912 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
913 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
914 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
915 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
917 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
918 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
920 if (intel_crtc
->pipe
== 1)
921 intel_dp
->DP
|= DP_PIPEB_SELECT
;
923 if (is_cpu_edp(intel_dp
)) {
924 /* don't miss out required setting for eDP */
925 intel_dp
->DP
|= DP_PLL_ENABLE
;
926 if (adjusted_mode
->clock
< 200000)
927 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
929 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
932 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
936 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
937 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
939 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
940 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
942 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
943 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
945 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
949 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
954 I915_READ(PCH_PP_STATUS
),
955 I915_READ(PCH_PP_CONTROL
));
957 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
958 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
959 I915_READ(PCH_PP_STATUS
),
960 I915_READ(PCH_PP_CONTROL
));
964 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
966 DRM_DEBUG_KMS("Wait for panel power on\n");
967 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
970 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
972 DRM_DEBUG_KMS("Wait for panel power off time\n");
973 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
976 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
978 DRM_DEBUG_KMS("Wait for panel power cycle\n");
979 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
983 /* Read the current pp_control value, unlocking the register if it
987 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
989 u32 control
= I915_READ(PCH_PP_CONTROL
);
991 control
&= ~PANEL_UNLOCK_MASK
;
992 control
|= PANEL_UNLOCK_REGS
;
996 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
998 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1002 if (!is_edp(intel_dp
))
1004 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1006 WARN(intel_dp
->want_panel_vdd
,
1007 "eDP VDD already requested on\n");
1009 intel_dp
->want_panel_vdd
= true;
1011 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1012 DRM_DEBUG_KMS("eDP VDD already on\n");
1016 if (!ironlake_edp_have_panel_power(intel_dp
))
1017 ironlake_wait_panel_power_cycle(intel_dp
);
1019 pp
= ironlake_get_pp_control(dev_priv
);
1020 pp
|= EDP_FORCE_VDD
;
1021 I915_WRITE(PCH_PP_CONTROL
, pp
);
1022 POSTING_READ(PCH_PP_CONTROL
);
1023 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1024 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1027 * If the panel wasn't on, delay before accessing aux channel
1029 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1030 DRM_DEBUG_KMS("eDP was not running\n");
1031 msleep(intel_dp
->panel_power_up_delay
);
1035 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1037 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1042 pp
= ironlake_get_pp_control(dev_priv
);
1043 pp
&= ~EDP_FORCE_VDD
;
1044 I915_WRITE(PCH_PP_CONTROL
, pp
);
1045 POSTING_READ(PCH_PP_CONTROL
);
1047 /* Make sure sequencer is idle before allowing subsequent activity */
1048 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1051 msleep(intel_dp
->panel_power_down_delay
);
1055 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1057 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1058 struct intel_dp
, panel_vdd_work
);
1059 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1061 mutex_lock(&dev
->mode_config
.mutex
);
1062 ironlake_panel_vdd_off_sync(intel_dp
);
1063 mutex_unlock(&dev
->mode_config
.mutex
);
1066 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1068 if (!is_edp(intel_dp
))
1071 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1072 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1074 intel_dp
->want_panel_vdd
= false;
1077 ironlake_panel_vdd_off_sync(intel_dp
);
1080 * Queue the timer to fire a long
1081 * time from now (relative to the power down delay)
1082 * to keep the panel power up across a sequence of operations
1084 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1085 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1089 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1091 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1095 if (!is_edp(intel_dp
))
1098 DRM_DEBUG_KMS("Turn eDP power on\n");
1100 if (ironlake_edp_have_panel_power(intel_dp
)) {
1101 DRM_DEBUG_KMS("eDP power already on\n");
1105 ironlake_wait_panel_power_cycle(intel_dp
);
1107 pp
= ironlake_get_pp_control(dev_priv
);
1109 /* ILK workaround: disable reset around power sequence */
1110 pp
&= ~PANEL_POWER_RESET
;
1111 I915_WRITE(PCH_PP_CONTROL
, pp
);
1112 POSTING_READ(PCH_PP_CONTROL
);
1115 pp
|= POWER_TARGET_ON
;
1117 pp
|= PANEL_POWER_RESET
;
1119 I915_WRITE(PCH_PP_CONTROL
, pp
);
1120 POSTING_READ(PCH_PP_CONTROL
);
1122 ironlake_wait_panel_on(intel_dp
);
1125 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1126 I915_WRITE(PCH_PP_CONTROL
, pp
);
1127 POSTING_READ(PCH_PP_CONTROL
);
1131 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1133 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1137 if (!is_edp(intel_dp
))
1140 DRM_DEBUG_KMS("Turn eDP power off\n");
1142 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1144 pp
= ironlake_get_pp_control(dev_priv
);
1145 /* We need to switch off panel power _and_ force vdd, for otherwise some
1146 * panels get very unhappy and cease to work. */
1147 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1148 I915_WRITE(PCH_PP_CONTROL
, pp
);
1149 POSTING_READ(PCH_PP_CONTROL
);
1151 intel_dp
->want_panel_vdd
= false;
1153 ironlake_wait_panel_off(intel_dp
);
1156 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1158 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1162 if (!is_edp(intel_dp
))
1165 DRM_DEBUG_KMS("\n");
1167 * If we enable the backlight right away following a panel power
1168 * on, we may see slight flicker as the panel syncs with the eDP
1169 * link. So delay a bit to make sure the image is solid before
1170 * allowing it to appear.
1172 msleep(intel_dp
->backlight_on_delay
);
1173 pp
= ironlake_get_pp_control(dev_priv
);
1174 pp
|= EDP_BLC_ENABLE
;
1175 I915_WRITE(PCH_PP_CONTROL
, pp
);
1176 POSTING_READ(PCH_PP_CONTROL
);
1179 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1181 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1185 if (!is_edp(intel_dp
))
1188 DRM_DEBUG_KMS("\n");
1189 pp
= ironlake_get_pp_control(dev_priv
);
1190 pp
&= ~EDP_BLC_ENABLE
;
1191 I915_WRITE(PCH_PP_CONTROL
, pp
);
1192 POSTING_READ(PCH_PP_CONTROL
);
1193 msleep(intel_dp
->backlight_off_delay
);
1196 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1198 struct drm_device
*dev
= encoder
->dev
;
1199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1202 DRM_DEBUG_KMS("\n");
1203 dpa_ctl
= I915_READ(DP_A
);
1204 dpa_ctl
|= DP_PLL_ENABLE
;
1205 I915_WRITE(DP_A
, dpa_ctl
);
1210 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1212 struct drm_device
*dev
= encoder
->dev
;
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1216 dpa_ctl
= I915_READ(DP_A
);
1217 dpa_ctl
&= ~DP_PLL_ENABLE
;
1218 I915_WRITE(DP_A
, dpa_ctl
);
1223 /* If the sink supports it, try to set the power state appropriately */
1224 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1228 /* Should have a valid DPCD by this point */
1229 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1232 if (mode
!= DRM_MODE_DPMS_ON
) {
1233 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1236 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1239 * When turning on, we need to retry for 1ms to give the sink
1242 for (i
= 0; i
< 3; i
++) {
1243 ret
= intel_dp_aux_native_write_1(intel_dp
,
1253 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1256 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1257 struct drm_device
*dev
= encoder
->base
.dev
;
1258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1261 if (!(tmp
& DP_PORT_EN
))
1264 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1265 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1266 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1267 *pipe
= PORT_TO_PIPE(tmp
);
1273 switch (intel_dp
->output_reg
) {
1275 trans_sel
= TRANS_DP_PORT_SEL_B
;
1278 trans_sel
= TRANS_DP_PORT_SEL_C
;
1281 trans_sel
= TRANS_DP_PORT_SEL_D
;
1288 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1289 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1296 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1301 static void intel_disable_dp(struct intel_encoder
*encoder
)
1303 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1305 /* Make sure the panel is off before trying to change the mode. But also
1306 * ensure that we have vdd while we switch off the panel. */
1307 ironlake_edp_panel_vdd_on(intel_dp
);
1308 ironlake_edp_backlight_off(intel_dp
);
1309 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1310 ironlake_edp_panel_off(intel_dp
);
1311 intel_dp_link_down(intel_dp
);
1314 static void intel_enable_dp(struct intel_encoder
*encoder
)
1316 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1317 struct drm_device
*dev
= encoder
->base
.dev
;
1318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1319 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1321 ironlake_edp_panel_vdd_on(intel_dp
);
1322 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1323 if (!(dp_reg
& DP_PORT_EN
)) {
1324 intel_dp_start_link_train(intel_dp
);
1325 ironlake_edp_panel_on(intel_dp
);
1326 ironlake_edp_panel_vdd_off(intel_dp
, true);
1327 intel_dp_complete_link_train(intel_dp
);
1329 ironlake_edp_panel_vdd_off(intel_dp
, false);
1330 ironlake_edp_backlight_on(intel_dp
);
1334 intel_dp_dpms(struct drm_connector
*connector
, int mode
)
1336 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
1338 /* DP supports only 2 dpms states. */
1339 if (mode
!= DRM_MODE_DPMS_ON
)
1340 mode
= DRM_MODE_DPMS_OFF
;
1342 if (mode
== connector
->dpms
)
1345 connector
->dpms
= mode
;
1347 /* Only need to change hw state when actually enabled */
1348 if (!intel_dp
->base
.base
.crtc
) {
1349 intel_dp
->base
.connectors_active
= false;
1353 if (mode
!= DRM_MODE_DPMS_ON
) {
1354 intel_encoder_dpms(&intel_dp
->base
, mode
);
1356 if (is_cpu_edp(intel_dp
))
1357 ironlake_edp_pll_off(&intel_dp
->base
.base
);
1359 if (is_cpu_edp(intel_dp
))
1360 ironlake_edp_pll_on(&intel_dp
->base
.base
);
1362 intel_encoder_dpms(&intel_dp
->base
, mode
);
1365 intel_modeset_check_state(connector
->dev
);
1369 * Native read with retry for link status and receiver capability reads for
1370 * cases where the sink may still be asleep.
1373 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1374 uint8_t *recv
, int recv_bytes
)
1379 * Sinks are *supposed* to come up within 1ms from an off state,
1380 * but we're also supposed to retry 3 times per the spec.
1382 for (i
= 0; i
< 3; i
++) {
1383 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1385 if (ret
== recv_bytes
)
1394 * Fetch AUX CH registers 0x202 - 0x207 which contain
1395 * link status information
1398 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1400 return intel_dp_aux_native_read_retry(intel_dp
,
1403 DP_LINK_STATUS_SIZE
);
1407 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1410 return link_status
[r
- DP_LANE0_1_STATUS
];
1414 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1417 int s
= ((lane
& 1) ?
1418 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1419 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1420 uint8_t l
= adjust_request
[lane
>>1];
1422 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1426 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1429 int s
= ((lane
& 1) ?
1430 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1431 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1432 uint8_t l
= adjust_request
[lane
>>1];
1434 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1439 static char *voltage_names
[] = {
1440 "0.4V", "0.6V", "0.8V", "1.2V"
1442 static char *pre_emph_names
[] = {
1443 "0dB", "3.5dB", "6dB", "9.5dB"
1445 static char *link_train_names
[] = {
1446 "pattern 1", "pattern 2", "idle", "off"
1451 * These are source-specific values; current Intel hardware supports
1452 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1456 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1458 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1460 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1461 return DP_TRAIN_VOLTAGE_SWING_800
;
1462 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1463 return DP_TRAIN_VOLTAGE_SWING_1200
;
1465 return DP_TRAIN_VOLTAGE_SWING_800
;
1469 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1471 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1473 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1474 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1475 case DP_TRAIN_VOLTAGE_SWING_400
:
1476 return DP_TRAIN_PRE_EMPHASIS_6
;
1477 case DP_TRAIN_VOLTAGE_SWING_600
:
1478 case DP_TRAIN_VOLTAGE_SWING_800
:
1479 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1481 return DP_TRAIN_PRE_EMPHASIS_0
;
1484 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1485 case DP_TRAIN_VOLTAGE_SWING_400
:
1486 return DP_TRAIN_PRE_EMPHASIS_6
;
1487 case DP_TRAIN_VOLTAGE_SWING_600
:
1488 return DP_TRAIN_PRE_EMPHASIS_6
;
1489 case DP_TRAIN_VOLTAGE_SWING_800
:
1490 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1491 case DP_TRAIN_VOLTAGE_SWING_1200
:
1493 return DP_TRAIN_PRE_EMPHASIS_0
;
1499 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1504 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1505 uint8_t voltage_max
;
1506 uint8_t preemph_max
;
1508 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1509 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1510 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1518 voltage_max
= intel_dp_voltage_max(intel_dp
);
1519 if (v
>= voltage_max
)
1520 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1522 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1523 if (p
>= preemph_max
)
1524 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1526 for (lane
= 0; lane
< 4; lane
++)
1527 intel_dp
->train_set
[lane
] = v
| p
;
1531 intel_dp_signal_levels(uint8_t train_set
)
1533 uint32_t signal_levels
= 0;
1535 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1536 case DP_TRAIN_VOLTAGE_SWING_400
:
1538 signal_levels
|= DP_VOLTAGE_0_4
;
1540 case DP_TRAIN_VOLTAGE_SWING_600
:
1541 signal_levels
|= DP_VOLTAGE_0_6
;
1543 case DP_TRAIN_VOLTAGE_SWING_800
:
1544 signal_levels
|= DP_VOLTAGE_0_8
;
1546 case DP_TRAIN_VOLTAGE_SWING_1200
:
1547 signal_levels
|= DP_VOLTAGE_1_2
;
1550 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1551 case DP_TRAIN_PRE_EMPHASIS_0
:
1553 signal_levels
|= DP_PRE_EMPHASIS_0
;
1555 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1556 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1558 case DP_TRAIN_PRE_EMPHASIS_6
:
1559 signal_levels
|= DP_PRE_EMPHASIS_6
;
1561 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1562 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1565 return signal_levels
;
1568 /* Gen6's DP voltage swing and pre-emphasis control */
1570 intel_gen6_edp_signal_levels(uint8_t train_set
)
1572 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1573 DP_TRAIN_PRE_EMPHASIS_MASK
);
1574 switch (signal_levels
) {
1575 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1576 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1577 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1578 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1579 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1580 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1581 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1582 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1583 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1584 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1585 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1586 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1587 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1588 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1590 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1591 "0x%x\n", signal_levels
);
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1596 /* Gen7's DP voltage swing and pre-emphasis control */
1598 intel_gen7_edp_signal_levels(uint8_t train_set
)
1600 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1601 DP_TRAIN_PRE_EMPHASIS_MASK
);
1602 switch (signal_levels
) {
1603 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1604 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1605 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1606 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1607 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1608 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1610 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1611 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1612 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1613 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1615 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1616 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1617 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1618 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1621 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1622 "0x%x\n", signal_levels
);
1623 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1628 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1631 int s
= (lane
& 1) * 4;
1632 uint8_t l
= link_status
[lane
>>1];
1634 return (l
>> s
) & 0xf;
1637 /* Check for clock recovery is done on all channels */
1639 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1642 uint8_t lane_status
;
1644 for (lane
= 0; lane
< lane_count
; lane
++) {
1645 lane_status
= intel_get_lane_status(link_status
, lane
);
1646 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1652 /* Check to see if channel eq is done on all channels */
1653 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1654 DP_LANE_CHANNEL_EQ_DONE|\
1655 DP_LANE_SYMBOL_LOCKED)
1657 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1660 uint8_t lane_status
;
1663 lane_align
= intel_dp_link_status(link_status
,
1664 DP_LANE_ALIGN_STATUS_UPDATED
);
1665 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1667 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1668 lane_status
= intel_get_lane_status(link_status
, lane
);
1669 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1676 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1677 uint32_t dp_reg_value
,
1678 uint8_t dp_train_pat
)
1680 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1684 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1685 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1687 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1688 case DP_TRAINING_PATTERN_DISABLE
:
1689 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1691 case DP_TRAINING_PATTERN_1
:
1692 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1694 case DP_TRAINING_PATTERN_2
:
1695 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1697 case DP_TRAINING_PATTERN_3
:
1698 DRM_ERROR("DP training pattern 3 not supported\n");
1699 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1704 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1706 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1707 case DP_TRAINING_PATTERN_DISABLE
:
1708 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1710 case DP_TRAINING_PATTERN_1
:
1711 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1713 case DP_TRAINING_PATTERN_2
:
1714 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1716 case DP_TRAINING_PATTERN_3
:
1717 DRM_ERROR("DP training pattern 3 not supported\n");
1718 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1723 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1724 POSTING_READ(intel_dp
->output_reg
);
1726 intel_dp_aux_native_write_1(intel_dp
,
1727 DP_TRAINING_PATTERN_SET
,
1730 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1731 DP_TRAINING_PATTERN_DISABLE
) {
1732 ret
= intel_dp_aux_native_write(intel_dp
,
1733 DP_TRAINING_LANE0_SET
,
1734 intel_dp
->train_set
,
1735 intel_dp
->lane_count
);
1736 if (ret
!= intel_dp
->lane_count
)
1743 /* Enable corresponding port and start training pattern 1 */
1745 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1747 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1749 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1752 bool clock_recovery
= false;
1753 int voltage_tries
, loop_tries
;
1754 uint32_t DP
= intel_dp
->DP
;
1757 * On CPT we have to enable the port in training pattern 1, which
1758 * will happen below in intel_dp_set_link_train. Otherwise, enable
1759 * the port and wait for it to become active.
1761 if (!HAS_PCH_CPT(dev
)) {
1762 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1763 POSTING_READ(intel_dp
->output_reg
);
1764 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1767 /* Write the link configuration data */
1768 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1769 intel_dp
->link_configuration
,
1770 DP_LINK_CONFIGURATION_SIZE
);
1774 memset(intel_dp
->train_set
, 0, 4);
1778 clock_recovery
= false;
1780 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1781 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1782 uint32_t signal_levels
;
1785 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1786 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1787 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1788 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1789 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1790 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1792 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1793 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1794 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1797 if (!intel_dp_set_link_train(intel_dp
, DP
,
1798 DP_TRAINING_PATTERN_1
|
1799 DP_LINK_SCRAMBLING_DISABLE
))
1801 /* Set training pattern 1 */
1804 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1805 DRM_ERROR("failed to get link status\n");
1809 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1810 DRM_DEBUG_KMS("clock recovery OK\n");
1811 clock_recovery
= true;
1815 /* Check to see if we've tried the max voltage */
1816 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1817 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1819 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1821 if (loop_tries
== 5) {
1822 DRM_DEBUG_KMS("too many full retries, give up\n");
1825 memset(intel_dp
->train_set
, 0, 4);
1830 /* Check to see if we've tried the same voltage 5 times */
1831 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1833 if (voltage_tries
== 5) {
1834 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1839 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1841 /* Compute new intel_dp->train_set as requested by target */
1842 intel_get_adjust_train(intel_dp
, link_status
);
1849 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1851 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1852 bool channel_eq
= false;
1853 int tries
, cr_tries
;
1854 uint32_t DP
= intel_dp
->DP
;
1856 /* channel equalization */
1861 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1862 uint32_t signal_levels
;
1863 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1866 DRM_ERROR("failed to train DP, aborting\n");
1867 intel_dp_link_down(intel_dp
);
1871 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1872 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1873 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1874 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1875 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1876 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1878 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1879 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1882 /* channel eq pattern */
1883 if (!intel_dp_set_link_train(intel_dp
, DP
,
1884 DP_TRAINING_PATTERN_2
|
1885 DP_LINK_SCRAMBLING_DISABLE
))
1889 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1892 /* Make sure clock is still ok */
1893 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1894 intel_dp_start_link_train(intel_dp
);
1899 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1904 /* Try 5 times, then try clock recovery if that fails */
1906 intel_dp_link_down(intel_dp
);
1907 intel_dp_start_link_train(intel_dp
);
1913 /* Compute new intel_dp->train_set as requested by target */
1914 intel_get_adjust_train(intel_dp
, link_status
);
1918 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
1922 intel_dp_link_down(struct intel_dp
*intel_dp
)
1924 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1926 uint32_t DP
= intel_dp
->DP
;
1928 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1931 DRM_DEBUG_KMS("\n");
1933 if (is_edp(intel_dp
)) {
1934 DP
&= ~DP_PLL_ENABLE
;
1935 I915_WRITE(intel_dp
->output_reg
, DP
);
1936 POSTING_READ(intel_dp
->output_reg
);
1940 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1941 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1942 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1944 DP
&= ~DP_LINK_TRAIN_MASK
;
1945 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1947 POSTING_READ(intel_dp
->output_reg
);
1951 if (is_edp(intel_dp
)) {
1952 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1953 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1955 DP
|= DP_LINK_TRAIN_OFF
;
1958 if (HAS_PCH_IBX(dev
) &&
1959 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1960 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1962 /* Hardware workaround: leaving our transcoder select
1963 * set to transcoder B while it's off will prevent the
1964 * corresponding HDMI output on transcoder A.
1966 * Combine this with another hardware workaround:
1967 * transcoder select bit can only be cleared while the
1970 DP
&= ~DP_PIPEB_SELECT
;
1971 I915_WRITE(intel_dp
->output_reg
, DP
);
1973 /* Changes to enable or select take place the vblank
1974 * after being written.
1977 /* We can arrive here never having been attached
1978 * to a CRTC, for instance, due to inheriting
1979 * random state from the BIOS.
1981 * If the pipe is not running, play safe and
1982 * wait for the clocks to stabilise before
1985 POSTING_READ(intel_dp
->output_reg
);
1988 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1991 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
1992 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1993 POSTING_READ(intel_dp
->output_reg
);
1994 msleep(intel_dp
->panel_power_down_delay
);
1998 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2000 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2001 sizeof(intel_dp
->dpcd
)) &&
2002 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
2010 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2014 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2017 ironlake_edp_panel_vdd_on(intel_dp
);
2019 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2020 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2021 buf
[0], buf
[1], buf
[2]);
2023 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2024 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2025 buf
[0], buf
[1], buf
[2]);
2027 ironlake_edp_panel_vdd_off(intel_dp
, false);
2031 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2035 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2036 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2037 sink_irq_vector
, 1);
2045 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2047 /* NAK by default */
2048 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2052 * According to DP spec
2055 * 2. Configure link according to Receiver Capabilities
2056 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2057 * 4. Check link status on receipt of hot-plug interrupt
2061 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2064 u8 link_status
[DP_LINK_STATUS_SIZE
];
2066 if (!intel_dp
->base
.connectors_active
)
2069 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2072 /* Try to read receiver status if the link appears to be up */
2073 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2074 intel_dp_link_down(intel_dp
);
2078 /* Now read the DPCD to see if it's actually running */
2079 if (!intel_dp_get_dpcd(intel_dp
)) {
2080 intel_dp_link_down(intel_dp
);
2084 /* Try to read the source of the interrupt */
2085 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2086 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2087 /* Clear interrupt source */
2088 intel_dp_aux_native_write_1(intel_dp
,
2089 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2092 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2093 intel_dp_handle_test_request(intel_dp
);
2094 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2095 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2098 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2099 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2100 drm_get_encoder_name(&intel_dp
->base
.base
));
2101 intel_dp_start_link_train(intel_dp
);
2102 intel_dp_complete_link_train(intel_dp
);
2106 static enum drm_connector_status
2107 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2109 if (intel_dp_get_dpcd(intel_dp
))
2110 return connector_status_connected
;
2111 return connector_status_disconnected
;
2114 static enum drm_connector_status
2115 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2117 enum drm_connector_status status
;
2119 /* Can't disconnect eDP, but you can close the lid... */
2120 if (is_edp(intel_dp
)) {
2121 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2122 if (status
== connector_status_unknown
)
2123 status
= connector_status_connected
;
2127 return intel_dp_detect_dpcd(intel_dp
);
2130 static enum drm_connector_status
2131 g4x_dp_detect(struct intel_dp
*intel_dp
)
2133 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2137 switch (intel_dp
->output_reg
) {
2139 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2142 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2145 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2148 return connector_status_unknown
;
2151 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2152 return connector_status_disconnected
;
2154 return intel_dp_detect_dpcd(intel_dp
);
2157 static struct edid
*
2158 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2160 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2164 if (is_edp(intel_dp
)) {
2165 if (!intel_dp
->edid
)
2168 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2169 edid
= kmalloc(size
, GFP_KERNEL
);
2173 memcpy(edid
, intel_dp
->edid
, size
);
2177 edid
= drm_get_edid(connector
, adapter
);
2182 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2184 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2187 if (is_edp(intel_dp
)) {
2188 drm_mode_connector_update_edid_property(connector
,
2190 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2191 drm_edid_to_eld(connector
,
2193 connector
->display_info
.raw_edid
= NULL
;
2194 return intel_dp
->edid_mode_count
;
2197 ret
= intel_ddc_get_modes(connector
, adapter
);
2203 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2205 * \return true if DP port is connected.
2206 * \return false if DP port is disconnected.
2208 static enum drm_connector_status
2209 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2211 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2212 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2213 enum drm_connector_status status
;
2214 struct edid
*edid
= NULL
;
2216 intel_dp
->has_audio
= false;
2218 if (HAS_PCH_SPLIT(dev
))
2219 status
= ironlake_dp_detect(intel_dp
);
2221 status
= g4x_dp_detect(intel_dp
);
2223 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2224 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2225 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2226 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2228 if (status
!= connector_status_connected
)
2231 intel_dp_probe_oui(intel_dp
);
2233 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2234 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2236 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2238 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2239 connector
->display_info
.raw_edid
= NULL
;
2244 return connector_status_connected
;
2247 static int intel_dp_get_modes(struct drm_connector
*connector
)
2249 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2250 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2254 /* We should parse the EDID data and find out if it has an audio sink
2257 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2259 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2260 struct drm_display_mode
*newmode
;
2261 list_for_each_entry(newmode
, &connector
->probed_modes
,
2263 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2264 intel_dp
->panel_fixed_mode
=
2265 drm_mode_duplicate(dev
, newmode
);
2273 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2274 if (is_edp(intel_dp
)) {
2275 /* initialize panel mode from VBT if available for eDP */
2276 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2277 intel_dp
->panel_fixed_mode
=
2278 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2279 if (intel_dp
->panel_fixed_mode
) {
2280 intel_dp
->panel_fixed_mode
->type
|=
2281 DRM_MODE_TYPE_PREFERRED
;
2284 if (intel_dp
->panel_fixed_mode
) {
2285 struct drm_display_mode
*mode
;
2286 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2287 drm_mode_probed_add(connector
, mode
);
2295 intel_dp_detect_audio(struct drm_connector
*connector
)
2297 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2299 bool has_audio
= false;
2301 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2303 has_audio
= drm_detect_monitor_audio(edid
);
2305 connector
->display_info
.raw_edid
= NULL
;
2313 intel_dp_set_property(struct drm_connector
*connector
,
2314 struct drm_property
*property
,
2317 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2318 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2321 ret
= drm_connector_property_set_value(connector
, property
, val
);
2325 if (property
== dev_priv
->force_audio_property
) {
2329 if (i
== intel_dp
->force_audio
)
2332 intel_dp
->force_audio
= i
;
2334 if (i
== HDMI_AUDIO_AUTO
)
2335 has_audio
= intel_dp_detect_audio(connector
);
2337 has_audio
= (i
== HDMI_AUDIO_ON
);
2339 if (has_audio
== intel_dp
->has_audio
)
2342 intel_dp
->has_audio
= has_audio
;
2346 if (property
== dev_priv
->broadcast_rgb_property
) {
2347 if (val
== !!intel_dp
->color_range
)
2350 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2357 if (intel_dp
->base
.base
.crtc
) {
2358 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2359 intel_set_mode(crtc
, &crtc
->mode
,
2360 crtc
->x
, crtc
->y
, crtc
->fb
);
2367 intel_dp_destroy(struct drm_connector
*connector
)
2369 struct drm_device
*dev
= connector
->dev
;
2371 if (intel_dpd_is_edp(dev
))
2372 intel_panel_destroy_backlight(dev
);
2374 drm_sysfs_connector_remove(connector
);
2375 drm_connector_cleanup(connector
);
2379 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2381 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2383 i2c_del_adapter(&intel_dp
->adapter
);
2384 drm_encoder_cleanup(encoder
);
2385 if (is_edp(intel_dp
)) {
2386 kfree(intel_dp
->edid
);
2387 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2388 ironlake_panel_vdd_off_sync(intel_dp
);
2393 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2394 .mode_fixup
= intel_dp_mode_fixup
,
2395 .mode_set
= intel_dp_mode_set
,
2396 .disable
= intel_encoder_noop
,
2399 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2400 .dpms
= intel_dp_dpms
,
2401 .detect
= intel_dp_detect
,
2402 .fill_modes
= drm_helper_probe_single_connector_modes
,
2403 .set_property
= intel_dp_set_property
,
2404 .destroy
= intel_dp_destroy
,
2407 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2408 .get_modes
= intel_dp_get_modes
,
2409 .mode_valid
= intel_dp_mode_valid
,
2410 .best_encoder
= intel_best_encoder
,
2413 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2414 .destroy
= intel_dp_encoder_destroy
,
2418 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2420 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2422 intel_dp_check_link_status(intel_dp
);
2425 /* Return which DP Port should be selected for Transcoder DP control */
2427 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2429 struct drm_device
*dev
= crtc
->dev
;
2430 struct intel_encoder
*encoder
;
2432 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2433 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2435 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2436 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2437 return intel_dp
->output_reg
;
2443 /* check the VBT to see whether the eDP is on DP-D port */
2444 bool intel_dpd_is_edp(struct drm_device
*dev
)
2446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2447 struct child_device_config
*p_child
;
2450 if (!dev_priv
->child_dev_num
)
2453 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2454 p_child
= dev_priv
->child_dev
+ i
;
2456 if (p_child
->dvo_port
== PORT_IDPD
&&
2457 p_child
->device_type
== DEVICE_TYPE_eDP
)
2464 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2466 intel_attach_force_audio_property(connector
);
2467 intel_attach_broadcast_rgb_property(connector
);
2471 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2474 struct drm_connector
*connector
;
2475 struct intel_dp
*intel_dp
;
2476 struct intel_encoder
*intel_encoder
;
2477 struct intel_connector
*intel_connector
;
2478 const char *name
= NULL
;
2481 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2485 intel_dp
->output_reg
= output_reg
;
2486 intel_dp
->port
= port
;
2488 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2489 if (!intel_connector
) {
2493 intel_encoder
= &intel_dp
->base
;
2495 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2496 if (intel_dpd_is_edp(dev
))
2497 intel_dp
->is_pch_edp
= true;
2499 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2500 type
= DRM_MODE_CONNECTOR_eDP
;
2501 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2503 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2504 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2507 connector
= &intel_connector
->base
;
2508 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2509 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2511 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2513 intel_encoder
->cloneable
= false;
2515 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2516 ironlake_panel_vdd_work
);
2518 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2520 connector
->interlace_allowed
= true;
2521 connector
->doublescan_allowed
= 0;
2523 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2524 DRM_MODE_ENCODER_TMDS
);
2525 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2527 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2528 drm_sysfs_connector_add(connector
);
2530 intel_encoder
->enable
= intel_enable_dp
;
2531 intel_encoder
->disable
= intel_disable_dp
;
2532 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2533 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2535 /* Set up the DDC bus. */
2541 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2545 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2549 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2553 WARN(1, "Invalid port %c\n", port_name(port
));
2557 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2559 /* Cache some DPCD data in the eDP case */
2560 if (is_edp(intel_dp
)) {
2562 struct edp_power_seq cur
, vbt
;
2563 u32 pp_on
, pp_off
, pp_div
;
2566 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2567 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2568 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2570 if (!pp_on
|| !pp_off
|| !pp_div
) {
2571 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2572 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2573 intel_dp_destroy(&intel_connector
->base
);
2577 /* Pull timing values out of registers */
2578 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2579 PANEL_POWER_UP_DELAY_SHIFT
;
2581 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2582 PANEL_LIGHT_ON_DELAY_SHIFT
;
2584 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2585 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2587 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2588 PANEL_POWER_DOWN_DELAY_SHIFT
;
2590 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2591 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2593 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2594 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2596 vbt
= dev_priv
->edp
.pps
;
2598 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2599 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2601 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2603 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2604 intel_dp
->backlight_on_delay
= get_delay(t8
);
2605 intel_dp
->backlight_off_delay
= get_delay(t9
);
2606 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2607 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2609 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2610 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2611 intel_dp
->panel_power_cycle_delay
);
2613 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2614 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2616 ironlake_edp_panel_vdd_on(intel_dp
);
2617 ret
= intel_dp_get_dpcd(intel_dp
);
2618 ironlake_edp_panel_vdd_off(intel_dp
, false);
2621 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2622 dev_priv
->no_aux_handshake
=
2623 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2624 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2626 /* if this fails, presume the device is a ghost */
2627 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2628 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2629 intel_dp_destroy(&intel_connector
->base
);
2633 ironlake_edp_panel_vdd_on(intel_dp
);
2634 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2636 drm_mode_connector_update_edid_property(connector
,
2638 intel_dp
->edid_mode_count
=
2639 drm_add_edid_modes(connector
, edid
);
2640 drm_edid_to_eld(connector
, edid
);
2641 intel_dp
->edid
= edid
;
2643 ironlake_edp_panel_vdd_off(intel_dp
, false);
2646 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2648 if (is_edp(intel_dp
)) {
2649 dev_priv
->int_edp_connector
= connector
;
2650 intel_panel_setup_backlight(dev
);
2653 intel_dp_add_properties(intel_dp
, connector
);
2655 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2656 * 0xd. Failure to do so will result in spurious interrupts being
2657 * generated on the port when a cable is not attached.
2659 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2660 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2661 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);