2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
36 #include "intel_drv.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
51 static bool is_edp(struct intel_dp
*intel_dp
)
53 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
64 static bool is_pch_edp(struct intel_dp
*intel_dp
)
66 return intel_dp
->is_pch_edp
;
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
75 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
77 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
80 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
82 return container_of(intel_attached_encoder(connector
),
83 struct intel_dp
, base
);
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
93 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
95 struct intel_dp
*intel_dp
;
100 intel_dp
= enc_to_intel_dp(encoder
);
102 return is_pch_edp(intel_dp
);
105 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
106 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
107 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
110 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
111 int *lane_num
, int *link_bw
)
113 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
115 *lane_num
= intel_dp
->lane_count
;
116 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
118 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
123 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
124 struct drm_display_mode
*mode
)
126 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
128 if (intel_dp
->panel_fixed_mode
)
129 return intel_dp
->panel_fixed_mode
->clock
;
135 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
137 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
138 switch (max_lane_count
) {
139 case 1: case 2: case 4:
144 return max_lane_count
;
148 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
150 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
152 switch (max_link_bw
) {
153 case DP_LINK_BW_1_62
:
157 max_link_bw
= DP_LINK_BW_1_62
;
164 intel_dp_link_clock(uint8_t link_bw
)
166 if (link_bw
== DP_LINK_BW_2_7
)
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
178 * 270000 * 1 * 8 / 10 == 216000
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
190 intel_dp_link_required(int pixel_clock
, int bpp
)
192 return (pixel_clock
* bpp
+ 9) / 10;
196 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
198 return (max_link_clock
* max_lanes
* 8) / 10;
202 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
203 struct drm_display_mode
*mode
,
206 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
207 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
208 int max_rate
, mode_rate
;
210 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
211 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 if (mode_rate
> max_rate
) {
214 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
215 if (mode_rate
> max_rate
)
220 |= INTEL_MODE_DP_FORCE_6BPC
;
229 intel_dp_mode_valid(struct drm_connector
*connector
,
230 struct drm_display_mode
*mode
)
232 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
234 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
235 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
238 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
242 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
243 return MODE_CLOCK_HIGH
;
245 if (mode
->clock
< 10000)
246 return MODE_CLOCK_LOW
;
248 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
249 return MODE_H_ILLEGAL
;
255 pack_aux(uint8_t *src
, int src_bytes
)
262 for (i
= 0; i
< src_bytes
; i
++)
263 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
268 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
273 for (i
= 0; i
< dst_bytes
; i
++)
274 dst
[i
] = src
>> ((3-i
) * 8);
277 /* hrawclock is 1/4 the FSB frequency */
279 intel_hrawclk(struct drm_device
*dev
)
281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev
))
288 clkcfg
= I915_READ(CLKCFG
);
289 switch (clkcfg
& CLKCFG_FSB_MASK
) {
298 case CLKCFG_FSB_1067
:
300 case CLKCFG_FSB_1333
:
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600
:
304 case CLKCFG_FSB_1600_ALT
:
311 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
313 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
319 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
328 intel_dp_check_edp(struct intel_dp
*intel_dp
)
330 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 if (!is_edp(intel_dp
))
335 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
338 I915_READ(PCH_PP_STATUS
),
339 I915_READ(PCH_PP_CONTROL
));
344 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
345 uint8_t *send
, int send_bytes
,
346 uint8_t *recv
, int recv_size
)
348 uint32_t output_reg
= intel_dp
->output_reg
;
349 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 uint32_t ch_ctl
= output_reg
+ 0x10;
352 uint32_t ch_data
= ch_ctl
+ 4;
356 uint32_t aux_clock_divider
;
359 intel_dp_check_edp(intel_dp
);
360 /* The clock divider is based off the hrawclk,
361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
364 * Note that PCH attached eDP panels should use a 125MHz input
367 if (is_cpu_edp(intel_dp
)) {
368 if (IS_VALLEYVIEW(dev
))
369 aux_clock_divider
= 100;
370 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
371 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
373 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
374 } else if (HAS_PCH_SPLIT(dev
))
375 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
377 aux_clock_divider
= intel_hrawclk(dev
) / 2;
384 /* Try to wait for any previous AUX channel activity */
385 for (try = 0; try < 3; try++) {
386 status
= I915_READ(ch_ctl
);
387 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
393 WARN(1, "dp_aux_ch not started status 0x%08x\n",
398 /* Must try at least 3 times according to DP spec */
399 for (try = 0; try < 5; try++) {
400 /* Load the send data into the aux channel data registers */
401 for (i
= 0; i
< send_bytes
; i
+= 4)
402 I915_WRITE(ch_data
+ i
,
403 pack_aux(send
+ i
, send_bytes
- i
));
405 /* Send the command and wait for it to complete */
407 DP_AUX_CH_CTL_SEND_BUSY
|
408 DP_AUX_CH_CTL_TIME_OUT_400us
|
409 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
410 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
411 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
413 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
414 DP_AUX_CH_CTL_RECEIVE_ERROR
);
416 status
= I915_READ(ch_ctl
);
417 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
422 /* Clear done status and any errors */
426 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
427 DP_AUX_CH_CTL_RECEIVE_ERROR
);
429 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
430 DP_AUX_CH_CTL_RECEIVE_ERROR
))
432 if (status
& DP_AUX_CH_CTL_DONE
)
436 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
437 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
441 /* Check for timeout or receive error.
442 * Timeouts occur when the sink is not connected
444 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
445 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
449 /* Timeouts occur when the device isn't connected, so they're
450 * "normal" -- don't fill the kernel log with these */
451 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
452 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
456 /* Unload any bytes sent back from the other side */
457 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
458 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
459 if (recv_bytes
> recv_size
)
460 recv_bytes
= recv_size
;
462 for (i
= 0; i
< recv_bytes
; i
+= 4)
463 unpack_aux(I915_READ(ch_data
+ i
),
464 recv
+ i
, recv_bytes
- i
);
469 /* Write data to the aux channel in native mode */
471 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
472 uint16_t address
, uint8_t *send
, int send_bytes
)
479 intel_dp_check_edp(intel_dp
);
482 msg
[0] = AUX_NATIVE_WRITE
<< 4;
483 msg
[1] = address
>> 8;
484 msg
[2] = address
& 0xff;
485 msg
[3] = send_bytes
- 1;
486 memcpy(&msg
[4], send
, send_bytes
);
487 msg_bytes
= send_bytes
+ 4;
489 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
492 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
494 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
502 /* Write a single byte to the aux channel in native mode */
504 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
505 uint16_t address
, uint8_t byte
)
507 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
510 /* read bytes from a native aux channel */
512 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
513 uint16_t address
, uint8_t *recv
, int recv_bytes
)
522 intel_dp_check_edp(intel_dp
);
523 msg
[0] = AUX_NATIVE_READ
<< 4;
524 msg
[1] = address
>> 8;
525 msg
[2] = address
& 0xff;
526 msg
[3] = recv_bytes
- 1;
529 reply_bytes
= recv_bytes
+ 1;
532 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
539 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
540 memcpy(recv
, reply
+ 1, ret
- 1);
543 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
551 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
552 uint8_t write_byte
, uint8_t *read_byte
)
554 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
555 struct intel_dp
*intel_dp
= container_of(adapter
,
558 uint16_t address
= algo_data
->address
;
566 intel_dp_check_edp(intel_dp
);
567 /* Set up the command byte */
568 if (mode
& MODE_I2C_READ
)
569 msg
[0] = AUX_I2C_READ
<< 4;
571 msg
[0] = AUX_I2C_WRITE
<< 4;
573 if (!(mode
& MODE_I2C_STOP
))
574 msg
[0] |= AUX_I2C_MOT
<< 4;
576 msg
[1] = address
>> 8;
597 for (retry
= 0; retry
< 5; retry
++) {
598 ret
= intel_dp_aux_ch(intel_dp
,
602 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
606 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
607 case AUX_NATIVE_REPLY_ACK
:
608 /* I2C-over-AUX Reply field is only valid
609 * when paired with AUX ACK.
612 case AUX_NATIVE_REPLY_NACK
:
613 DRM_DEBUG_KMS("aux_ch native nack\n");
615 case AUX_NATIVE_REPLY_DEFER
:
619 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
624 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
625 case AUX_I2C_REPLY_ACK
:
626 if (mode
== MODE_I2C_READ
) {
627 *read_byte
= reply
[1];
629 return reply_bytes
- 1;
630 case AUX_I2C_REPLY_NACK
:
631 DRM_DEBUG_KMS("aux_i2c nack\n");
633 case AUX_I2C_REPLY_DEFER
:
634 DRM_DEBUG_KMS("aux_i2c defer\n");
638 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
643 DRM_ERROR("too many retries, giving up\n");
647 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
648 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
651 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
652 struct intel_connector
*intel_connector
, const char *name
)
656 DRM_DEBUG_KMS("i2c_init %s\n", name
);
657 intel_dp
->algo
.running
= false;
658 intel_dp
->algo
.address
= 0;
659 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
661 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
662 intel_dp
->adapter
.owner
= THIS_MODULE
;
663 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
664 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
665 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
666 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
667 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
669 ironlake_edp_panel_vdd_on(intel_dp
);
670 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
671 ironlake_edp_panel_vdd_off(intel_dp
, false);
676 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
677 const struct drm_display_mode
*mode
,
678 struct drm_display_mode
*adjusted_mode
)
680 struct drm_device
*dev
= encoder
->dev
;
681 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
682 int lane_count
, clock
;
683 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
684 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
686 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
688 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
689 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
690 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
691 mode
, adjusted_mode
);
694 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
697 DRM_DEBUG_KMS("DP link computation with max lane count %i "
698 "max bw %02x pixel clock %iKHz\n",
699 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
701 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
704 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
705 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
707 for (clock
= 0; clock
<= max_clock
; clock
++) {
708 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
709 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
711 if (mode_rate
<= link_avail
) {
712 intel_dp
->link_bw
= bws
[clock
];
713 intel_dp
->lane_count
= lane_count
;
714 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
715 DRM_DEBUG_KMS("DP link bw %02x lane "
716 "count %d clock %d bpp %d\n",
717 intel_dp
->link_bw
, intel_dp
->lane_count
,
718 adjusted_mode
->clock
, bpp
);
719 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
720 mode_rate
, link_avail
);
729 struct intel_dp_m_n
{
738 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
740 while (*num
> 0xffffff || *den
> 0xffffff) {
747 intel_dp_compute_m_n(int bpp
,
751 struct intel_dp_m_n
*m_n
)
754 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
755 m_n
->gmch_n
= link_clock
* nlanes
;
756 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
757 m_n
->link_m
= pixel_clock
;
758 m_n
->link_n
= link_clock
;
759 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
763 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
764 struct drm_display_mode
*adjusted_mode
)
766 struct drm_device
*dev
= crtc
->dev
;
767 struct intel_encoder
*encoder
;
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
771 struct intel_dp_m_n m_n
;
772 int pipe
= intel_crtc
->pipe
;
775 * Find the lane count in the intel_encoder private
777 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
778 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
780 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
781 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
783 lane_count
= intel_dp
->lane_count
;
789 * Compute the GMCH and Link ratios. The '3' here is
790 * the number of bytes_per_pixel post-LUT, which we always
791 * set up for 8-bits of R/G/B, or 3 bytes total.
793 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
794 mode
->clock
, adjusted_mode
->clock
, &m_n
);
796 if (HAS_PCH_SPLIT(dev
)) {
797 I915_WRITE(TRANSDATA_M1(pipe
),
798 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
800 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
801 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
802 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
803 } else if (IS_VALLEYVIEW(dev
)) {
804 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
805 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
806 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
807 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
809 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
810 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
812 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
813 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
814 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
819 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
820 struct drm_display_mode
*adjusted_mode
)
822 struct drm_device
*dev
= encoder
->dev
;
823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
824 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
825 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
826 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
829 * There are four kinds of DP registers:
836 * IBX PCH and CPU are the same for almost everything,
837 * except that the CPU DP PLL is configured in this
840 * CPT PCH is quite different, having many bits moved
841 * to the TRANS_DP_CTL register instead. That
842 * configuration happens (oddly) in ironlake_pch_enable
845 /* Preserve the BIOS-computed detected bit. This is
846 * supposed to be read-only.
848 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
850 /* Handle DP bits in common between all three register formats */
851 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
853 switch (intel_dp
->lane_count
) {
855 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
858 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
861 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
864 if (intel_dp
->has_audio
) {
865 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
866 pipe_name(intel_crtc
->pipe
));
867 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
868 intel_write_eld(encoder
, adjusted_mode
);
870 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
871 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
872 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
873 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
875 * Check for DPCD version > 1.1 and enhanced framing support
877 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
878 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
879 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
882 /* Split out the IBX/CPU vs CPT settings */
884 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
885 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
886 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
887 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
888 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
889 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
891 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
892 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
894 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
896 /* don't miss out required setting for eDP */
897 if (adjusted_mode
->clock
< 200000)
898 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
900 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
901 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
902 intel_dp
->DP
|= intel_dp
->color_range
;
904 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
905 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
906 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
907 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
908 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
910 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
911 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
913 if (intel_crtc
->pipe
== 1)
914 intel_dp
->DP
|= DP_PIPEB_SELECT
;
916 if (is_cpu_edp(intel_dp
)) {
917 /* don't miss out required setting for eDP */
918 if (adjusted_mode
->clock
< 200000)
919 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
921 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
924 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
928 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
929 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
931 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
932 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
934 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
935 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
937 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
941 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
944 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
946 I915_READ(PCH_PP_STATUS
),
947 I915_READ(PCH_PP_CONTROL
));
949 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
950 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
951 I915_READ(PCH_PP_STATUS
),
952 I915_READ(PCH_PP_CONTROL
));
956 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
958 DRM_DEBUG_KMS("Wait for panel power on\n");
959 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
962 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
964 DRM_DEBUG_KMS("Wait for panel power off time\n");
965 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
968 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
970 DRM_DEBUG_KMS("Wait for panel power cycle\n");
971 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
975 /* Read the current pp_control value, unlocking the register if it
979 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
981 u32 control
= I915_READ(PCH_PP_CONTROL
);
983 control
&= ~PANEL_UNLOCK_MASK
;
984 control
|= PANEL_UNLOCK_REGS
;
988 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
990 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 if (!is_edp(intel_dp
))
996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
998 WARN(intel_dp
->want_panel_vdd
,
999 "eDP VDD already requested on\n");
1001 intel_dp
->want_panel_vdd
= true;
1003 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1008 if (!ironlake_edp_have_panel_power(intel_dp
))
1009 ironlake_wait_panel_power_cycle(intel_dp
);
1011 pp
= ironlake_get_pp_control(dev_priv
);
1012 pp
|= EDP_FORCE_VDD
;
1013 I915_WRITE(PCH_PP_CONTROL
, pp
);
1014 POSTING_READ(PCH_PP_CONTROL
);
1015 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1016 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1019 * If the panel wasn't on, delay before accessing aux channel
1021 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1022 DRM_DEBUG_KMS("eDP was not running\n");
1023 msleep(intel_dp
->panel_power_up_delay
);
1027 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1029 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1034 pp
= ironlake_get_pp_control(dev_priv
);
1035 pp
&= ~EDP_FORCE_VDD
;
1036 I915_WRITE(PCH_PP_CONTROL
, pp
);
1037 POSTING_READ(PCH_PP_CONTROL
);
1039 /* Make sure sequencer is idle before allowing subsequent activity */
1040 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1041 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1043 msleep(intel_dp
->panel_power_down_delay
);
1047 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1049 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1050 struct intel_dp
, panel_vdd_work
);
1051 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1053 mutex_lock(&dev
->mode_config
.mutex
);
1054 ironlake_panel_vdd_off_sync(intel_dp
);
1055 mutex_unlock(&dev
->mode_config
.mutex
);
1058 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1060 if (!is_edp(intel_dp
))
1063 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1064 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1066 intel_dp
->want_panel_vdd
= false;
1069 ironlake_panel_vdd_off_sync(intel_dp
);
1072 * Queue the timer to fire a long
1073 * time from now (relative to the power down delay)
1074 * to keep the panel power up across a sequence of operations
1076 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1077 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1081 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1083 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1087 if (!is_edp(intel_dp
))
1090 DRM_DEBUG_KMS("Turn eDP power on\n");
1092 if (ironlake_edp_have_panel_power(intel_dp
)) {
1093 DRM_DEBUG_KMS("eDP power already on\n");
1097 ironlake_wait_panel_power_cycle(intel_dp
);
1099 pp
= ironlake_get_pp_control(dev_priv
);
1101 /* ILK workaround: disable reset around power sequence */
1102 pp
&= ~PANEL_POWER_RESET
;
1103 I915_WRITE(PCH_PP_CONTROL
, pp
);
1104 POSTING_READ(PCH_PP_CONTROL
);
1107 pp
|= POWER_TARGET_ON
;
1109 pp
|= PANEL_POWER_RESET
;
1111 I915_WRITE(PCH_PP_CONTROL
, pp
);
1112 POSTING_READ(PCH_PP_CONTROL
);
1114 ironlake_wait_panel_on(intel_dp
);
1117 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1118 I915_WRITE(PCH_PP_CONTROL
, pp
);
1119 POSTING_READ(PCH_PP_CONTROL
);
1123 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1125 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1129 if (!is_edp(intel_dp
))
1132 DRM_DEBUG_KMS("Turn eDP power off\n");
1134 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1136 pp
= ironlake_get_pp_control(dev_priv
);
1137 /* We need to switch off panel power _and_ force vdd, for otherwise some
1138 * panels get very unhappy and cease to work. */
1139 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1140 I915_WRITE(PCH_PP_CONTROL
, pp
);
1141 POSTING_READ(PCH_PP_CONTROL
);
1143 intel_dp
->want_panel_vdd
= false;
1145 ironlake_wait_panel_off(intel_dp
);
1148 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1150 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1154 if (!is_edp(intel_dp
))
1157 DRM_DEBUG_KMS("\n");
1159 * If we enable the backlight right away following a panel power
1160 * on, we may see slight flicker as the panel syncs with the eDP
1161 * link. So delay a bit to make sure the image is solid before
1162 * allowing it to appear.
1164 msleep(intel_dp
->backlight_on_delay
);
1165 pp
= ironlake_get_pp_control(dev_priv
);
1166 pp
|= EDP_BLC_ENABLE
;
1167 I915_WRITE(PCH_PP_CONTROL
, pp
);
1168 POSTING_READ(PCH_PP_CONTROL
);
1171 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1173 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1177 if (!is_edp(intel_dp
))
1180 DRM_DEBUG_KMS("\n");
1181 pp
= ironlake_get_pp_control(dev_priv
);
1182 pp
&= ~EDP_BLC_ENABLE
;
1183 I915_WRITE(PCH_PP_CONTROL
, pp
);
1184 POSTING_READ(PCH_PP_CONTROL
);
1185 msleep(intel_dp
->backlight_off_delay
);
1188 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1190 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1191 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1195 assert_pipe_disabled(dev_priv
,
1196 to_intel_crtc(crtc
)->pipe
);
1198 DRM_DEBUG_KMS("\n");
1199 dpa_ctl
= I915_READ(DP_A
);
1200 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1201 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1203 /* We don't adjust intel_dp->DP while tearing down the link, to
1204 * facilitate link retraining (e.g. after hotplug). Hence clear all
1205 * enable bits here to ensure that we don't enable too much. */
1206 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1207 intel_dp
->DP
|= DP_PLL_ENABLE
;
1208 I915_WRITE(DP_A
, intel_dp
->DP
);
1213 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1215 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1216 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1220 assert_pipe_disabled(dev_priv
,
1221 to_intel_crtc(crtc
)->pipe
);
1223 dpa_ctl
= I915_READ(DP_A
);
1224 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1225 "dp pll off, should be on\n");
1226 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1228 /* We can't rely on the value tracked for the DP register in
1229 * intel_dp->DP because link_down must not change that (otherwise link
1230 * re-training will fail. */
1231 dpa_ctl
&= ~DP_PLL_ENABLE
;
1232 I915_WRITE(DP_A
, dpa_ctl
);
1237 /* If the sink supports it, try to set the power state appropriately */
1238 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1242 /* Should have a valid DPCD by this point */
1243 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1246 if (mode
!= DRM_MODE_DPMS_ON
) {
1247 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1250 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1253 * When turning on, we need to retry for 1ms to give the sink
1256 for (i
= 0; i
< 3; i
++) {
1257 ret
= intel_dp_aux_native_write_1(intel_dp
,
1267 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1270 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1271 struct drm_device
*dev
= encoder
->base
.dev
;
1272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1273 u32 tmp
= I915_READ(intel_dp
->output_reg
);
1275 if (!(tmp
& DP_PORT_EN
))
1278 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
1279 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1280 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
1281 *pipe
= PORT_TO_PIPE(tmp
);
1287 switch (intel_dp
->output_reg
) {
1289 trans_sel
= TRANS_DP_PORT_SEL_B
;
1292 trans_sel
= TRANS_DP_PORT_SEL_C
;
1295 trans_sel
= TRANS_DP_PORT_SEL_D
;
1302 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1303 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1310 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp
->output_reg
);
1315 static void intel_disable_dp(struct intel_encoder
*encoder
)
1317 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1319 /* Make sure the panel is off before trying to change the mode. But also
1320 * ensure that we have vdd while we switch off the panel. */
1321 ironlake_edp_panel_vdd_on(intel_dp
);
1322 ironlake_edp_backlight_off(intel_dp
);
1323 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1324 ironlake_edp_panel_off(intel_dp
);
1326 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1327 if (!is_cpu_edp(intel_dp
))
1328 intel_dp_link_down(intel_dp
);
1331 static void intel_post_disable_dp(struct intel_encoder
*encoder
)
1333 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1335 if (is_cpu_edp(intel_dp
)) {
1336 intel_dp_link_down(intel_dp
);
1337 ironlake_edp_pll_off(intel_dp
);
1341 static void intel_enable_dp(struct intel_encoder
*encoder
)
1343 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1344 struct drm_device
*dev
= encoder
->base
.dev
;
1345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1348 if (WARN_ON(dp_reg
& DP_PORT_EN
))
1351 ironlake_edp_panel_vdd_on(intel_dp
);
1352 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1353 intel_dp_start_link_train(intel_dp
);
1354 ironlake_edp_panel_on(intel_dp
);
1355 ironlake_edp_panel_vdd_off(intel_dp
, true);
1356 intel_dp_complete_link_train(intel_dp
);
1357 ironlake_edp_backlight_on(intel_dp
);
1360 static void intel_pre_enable_dp(struct intel_encoder
*encoder
)
1362 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1364 if (is_cpu_edp(intel_dp
))
1365 ironlake_edp_pll_on(intel_dp
);
1369 * Native read with retry for link status and receiver capability reads for
1370 * cases where the sink may still be asleep.
1373 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1374 uint8_t *recv
, int recv_bytes
)
1379 * Sinks are *supposed* to come up within 1ms from an off state,
1380 * but we're also supposed to retry 3 times per the spec.
1382 for (i
= 0; i
< 3; i
++) {
1383 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1385 if (ret
== recv_bytes
)
1394 * Fetch AUX CH registers 0x202 - 0x207 which contain
1395 * link status information
1398 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1400 return intel_dp_aux_native_read_retry(intel_dp
,
1403 DP_LINK_STATUS_SIZE
);
1407 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1410 return link_status
[r
- DP_LANE0_1_STATUS
];
1414 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1417 int s
= ((lane
& 1) ?
1418 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1419 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1420 uint8_t l
= adjust_request
[lane
>>1];
1422 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1426 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1429 int s
= ((lane
& 1) ?
1430 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1431 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1432 uint8_t l
= adjust_request
[lane
>>1];
1434 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1439 static char *voltage_names
[] = {
1440 "0.4V", "0.6V", "0.8V", "1.2V"
1442 static char *pre_emph_names
[] = {
1443 "0dB", "3.5dB", "6dB", "9.5dB"
1445 static char *link_train_names
[] = {
1446 "pattern 1", "pattern 2", "idle", "off"
1451 * These are source-specific values; current Intel hardware supports
1452 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1456 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1458 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1460 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1461 return DP_TRAIN_VOLTAGE_SWING_800
;
1462 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1463 return DP_TRAIN_VOLTAGE_SWING_1200
;
1465 return DP_TRAIN_VOLTAGE_SWING_800
;
1469 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1471 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1473 if (IS_HASWELL(dev
)) {
1474 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1475 case DP_TRAIN_VOLTAGE_SWING_400
:
1476 return DP_TRAIN_PRE_EMPHASIS_9_5
;
1477 case DP_TRAIN_VOLTAGE_SWING_600
:
1478 return DP_TRAIN_PRE_EMPHASIS_6
;
1479 case DP_TRAIN_VOLTAGE_SWING_800
:
1480 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1481 case DP_TRAIN_VOLTAGE_SWING_1200
:
1483 return DP_TRAIN_PRE_EMPHASIS_0
;
1485 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1486 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1487 case DP_TRAIN_VOLTAGE_SWING_400
:
1488 return DP_TRAIN_PRE_EMPHASIS_6
;
1489 case DP_TRAIN_VOLTAGE_SWING_600
:
1490 case DP_TRAIN_VOLTAGE_SWING_800
:
1491 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1493 return DP_TRAIN_PRE_EMPHASIS_0
;
1496 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1497 case DP_TRAIN_VOLTAGE_SWING_400
:
1498 return DP_TRAIN_PRE_EMPHASIS_6
;
1499 case DP_TRAIN_VOLTAGE_SWING_600
:
1500 return DP_TRAIN_PRE_EMPHASIS_6
;
1501 case DP_TRAIN_VOLTAGE_SWING_800
:
1502 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1503 case DP_TRAIN_VOLTAGE_SWING_1200
:
1505 return DP_TRAIN_PRE_EMPHASIS_0
;
1511 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1516 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1517 uint8_t voltage_max
;
1518 uint8_t preemph_max
;
1520 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1521 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1522 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1530 voltage_max
= intel_dp_voltage_max(intel_dp
);
1531 if (v
>= voltage_max
)
1532 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1534 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1535 if (p
>= preemph_max
)
1536 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1538 for (lane
= 0; lane
< 4; lane
++)
1539 intel_dp
->train_set
[lane
] = v
| p
;
1543 intel_dp_signal_levels(uint8_t train_set
)
1545 uint32_t signal_levels
= 0;
1547 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1548 case DP_TRAIN_VOLTAGE_SWING_400
:
1550 signal_levels
|= DP_VOLTAGE_0_4
;
1552 case DP_TRAIN_VOLTAGE_SWING_600
:
1553 signal_levels
|= DP_VOLTAGE_0_6
;
1555 case DP_TRAIN_VOLTAGE_SWING_800
:
1556 signal_levels
|= DP_VOLTAGE_0_8
;
1558 case DP_TRAIN_VOLTAGE_SWING_1200
:
1559 signal_levels
|= DP_VOLTAGE_1_2
;
1562 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1563 case DP_TRAIN_PRE_EMPHASIS_0
:
1565 signal_levels
|= DP_PRE_EMPHASIS_0
;
1567 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1568 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1570 case DP_TRAIN_PRE_EMPHASIS_6
:
1571 signal_levels
|= DP_PRE_EMPHASIS_6
;
1573 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1574 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1577 return signal_levels
;
1580 /* Gen6's DP voltage swing and pre-emphasis control */
1582 intel_gen6_edp_signal_levels(uint8_t train_set
)
1584 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1585 DP_TRAIN_PRE_EMPHASIS_MASK
);
1586 switch (signal_levels
) {
1587 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1588 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1589 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1590 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1591 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1592 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1593 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1594 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1595 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1596 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1597 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1598 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1599 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1600 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1602 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1603 "0x%x\n", signal_levels
);
1604 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1608 /* Gen7's DP voltage swing and pre-emphasis control */
1610 intel_gen7_edp_signal_levels(uint8_t train_set
)
1612 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1613 DP_TRAIN_PRE_EMPHASIS_MASK
);
1614 switch (signal_levels
) {
1615 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1616 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1617 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1618 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1619 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1620 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1622 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1623 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1624 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1625 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1627 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1628 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1629 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1630 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1633 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1634 "0x%x\n", signal_levels
);
1635 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1639 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1641 intel_dp_signal_levels_hsw(uint8_t train_set
)
1643 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1644 DP_TRAIN_PRE_EMPHASIS_MASK
);
1645 switch (signal_levels
) {
1646 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1647 return DDI_BUF_EMP_400MV_0DB_HSW
;
1648 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1649 return DDI_BUF_EMP_400MV_3_5DB_HSW
;
1650 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1651 return DDI_BUF_EMP_400MV_6DB_HSW
;
1652 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_9_5
:
1653 return DDI_BUF_EMP_400MV_9_5DB_HSW
;
1655 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1656 return DDI_BUF_EMP_600MV_0DB_HSW
;
1657 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1658 return DDI_BUF_EMP_600MV_3_5DB_HSW
;
1659 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1660 return DDI_BUF_EMP_600MV_6DB_HSW
;
1662 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1663 return DDI_BUF_EMP_800MV_0DB_HSW
;
1664 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1665 return DDI_BUF_EMP_800MV_3_5DB_HSW
;
1667 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1668 "0x%x\n", signal_levels
);
1669 return DDI_BUF_EMP_400MV_0DB_HSW
;
1674 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1677 int s
= (lane
& 1) * 4;
1678 uint8_t l
= link_status
[lane
>>1];
1680 return (l
>> s
) & 0xf;
1683 /* Check for clock recovery is done on all channels */
1685 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1688 uint8_t lane_status
;
1690 for (lane
= 0; lane
< lane_count
; lane
++) {
1691 lane_status
= intel_get_lane_status(link_status
, lane
);
1692 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1698 /* Check to see if channel eq is done on all channels */
1699 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1700 DP_LANE_CHANNEL_EQ_DONE|\
1701 DP_LANE_SYMBOL_LOCKED)
1703 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1706 uint8_t lane_status
;
1709 lane_align
= intel_dp_link_status(link_status
,
1710 DP_LANE_ALIGN_STATUS_UPDATED
);
1711 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1713 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1714 lane_status
= intel_get_lane_status(link_status
, lane
);
1715 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1722 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1723 uint32_t dp_reg_value
,
1724 uint8_t dp_train_pat
)
1726 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1731 if (IS_HASWELL(dev
)) {
1732 temp
= I915_READ(DP_TP_CTL(intel_dp
->port
));
1734 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
1735 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
1737 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
1739 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1740 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1741 case DP_TRAINING_PATTERN_DISABLE
:
1742 temp
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
1743 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1745 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp
->port
)) &
1746 DP_TP_STATUS_IDLE_DONE
), 1))
1747 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1749 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
1750 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
1753 case DP_TRAINING_PATTERN_1
:
1754 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1756 case DP_TRAINING_PATTERN_2
:
1757 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
1759 case DP_TRAINING_PATTERN_3
:
1760 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
1763 I915_WRITE(DP_TP_CTL(intel_dp
->port
), temp
);
1765 } else if (HAS_PCH_CPT(dev
) &&
1766 (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1767 dp_reg_value
&= ~DP_LINK_TRAIN_MASK_CPT
;
1769 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1770 case DP_TRAINING_PATTERN_DISABLE
:
1771 dp_reg_value
|= DP_LINK_TRAIN_OFF_CPT
;
1773 case DP_TRAINING_PATTERN_1
:
1774 dp_reg_value
|= DP_LINK_TRAIN_PAT_1_CPT
;
1776 case DP_TRAINING_PATTERN_2
:
1777 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1779 case DP_TRAINING_PATTERN_3
:
1780 DRM_ERROR("DP training pattern 3 not supported\n");
1781 dp_reg_value
|= DP_LINK_TRAIN_PAT_2_CPT
;
1786 dp_reg_value
&= ~DP_LINK_TRAIN_MASK
;
1788 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
1789 case DP_TRAINING_PATTERN_DISABLE
:
1790 dp_reg_value
|= DP_LINK_TRAIN_OFF
;
1792 case DP_TRAINING_PATTERN_1
:
1793 dp_reg_value
|= DP_LINK_TRAIN_PAT_1
;
1795 case DP_TRAINING_PATTERN_2
:
1796 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1798 case DP_TRAINING_PATTERN_3
:
1799 DRM_ERROR("DP training pattern 3 not supported\n");
1800 dp_reg_value
|= DP_LINK_TRAIN_PAT_2
;
1805 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1806 POSTING_READ(intel_dp
->output_reg
);
1808 intel_dp_aux_native_write_1(intel_dp
,
1809 DP_TRAINING_PATTERN_SET
,
1812 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) !=
1813 DP_TRAINING_PATTERN_DISABLE
) {
1814 ret
= intel_dp_aux_native_write(intel_dp
,
1815 DP_TRAINING_LANE0_SET
,
1816 intel_dp
->train_set
,
1817 intel_dp
->lane_count
);
1818 if (ret
!= intel_dp
->lane_count
)
1825 /* Enable corresponding port and start training pattern 1 */
1827 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1829 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1832 bool clock_recovery
= false;
1833 int voltage_tries
, loop_tries
;
1834 uint32_t DP
= intel_dp
->DP
;
1836 /* Write the link configuration data */
1837 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1838 intel_dp
->link_configuration
,
1839 DP_LINK_CONFIGURATION_SIZE
);
1843 memset(intel_dp
->train_set
, 0, 4);
1847 clock_recovery
= false;
1849 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1850 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1851 uint32_t signal_levels
;
1853 if (IS_HASWELL(dev
)) {
1854 signal_levels
= intel_dp_signal_levels_hsw(
1855 intel_dp
->train_set
[0]);
1856 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1857 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1858 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1859 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1860 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1861 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1862 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1864 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1865 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1867 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1870 if (!intel_dp_set_link_train(intel_dp
, DP
,
1871 DP_TRAINING_PATTERN_1
|
1872 DP_LINK_SCRAMBLING_DISABLE
))
1874 /* Set training pattern 1 */
1877 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1878 DRM_ERROR("failed to get link status\n");
1882 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1883 DRM_DEBUG_KMS("clock recovery OK\n");
1884 clock_recovery
= true;
1888 /* Check to see if we've tried the max voltage */
1889 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1890 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1892 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1894 if (loop_tries
== 5) {
1895 DRM_DEBUG_KMS("too many full retries, give up\n");
1898 memset(intel_dp
->train_set
, 0, 4);
1903 /* Check to see if we've tried the same voltage 5 times */
1904 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1906 if (voltage_tries
== 5) {
1907 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1912 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1914 /* Compute new intel_dp->train_set as requested by target */
1915 intel_get_adjust_train(intel_dp
, link_status
);
1922 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1924 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1925 bool channel_eq
= false;
1926 int tries
, cr_tries
;
1927 uint32_t DP
= intel_dp
->DP
;
1929 /* channel equalization */
1934 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1935 uint32_t signal_levels
;
1936 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1939 DRM_ERROR("failed to train DP, aborting\n");
1940 intel_dp_link_down(intel_dp
);
1944 if (IS_HASWELL(dev
)) {
1945 signal_levels
= intel_dp_signal_levels_hsw(intel_dp
->train_set
[0]);
1946 DP
= (DP
& ~DDI_BUF_EMP_MASK
) | signal_levels
;
1947 } else if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
) && !IS_VALLEYVIEW(dev
)) {
1948 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1949 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1950 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1951 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1952 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1954 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1955 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1958 /* channel eq pattern */
1959 if (!intel_dp_set_link_train(intel_dp
, DP
,
1960 DP_TRAINING_PATTERN_2
|
1961 DP_LINK_SCRAMBLING_DISABLE
))
1965 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1968 /* Make sure clock is still ok */
1969 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1970 intel_dp_start_link_train(intel_dp
);
1975 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1980 /* Try 5 times, then try clock recovery if that fails */
1982 intel_dp_link_down(intel_dp
);
1983 intel_dp_start_link_train(intel_dp
);
1989 /* Compute new intel_dp->train_set as requested by target */
1990 intel_get_adjust_train(intel_dp
, link_status
);
1995 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1997 intel_dp_set_link_train(intel_dp
, DP
, DP_TRAINING_PATTERN_DISABLE
);
2001 intel_dp_link_down(struct intel_dp
*intel_dp
)
2003 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2005 uint32_t DP
= intel_dp
->DP
;
2007 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
2010 DRM_DEBUG_KMS("\n");
2012 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
2013 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2014 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
2016 DP
&= ~DP_LINK_TRAIN_MASK
;
2017 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
2019 POSTING_READ(intel_dp
->output_reg
);
2023 if (HAS_PCH_IBX(dev
) &&
2024 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
2025 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2027 /* Hardware workaround: leaving our transcoder select
2028 * set to transcoder B while it's off will prevent the
2029 * corresponding HDMI output on transcoder A.
2031 * Combine this with another hardware workaround:
2032 * transcoder select bit can only be cleared while the
2035 DP
&= ~DP_PIPEB_SELECT
;
2036 I915_WRITE(intel_dp
->output_reg
, DP
);
2038 /* Changes to enable or select take place the vblank
2039 * after being written.
2042 /* We can arrive here never having been attached
2043 * to a CRTC, for instance, due to inheriting
2044 * random state from the BIOS.
2046 * If the pipe is not running, play safe and
2047 * wait for the clocks to stabilise before
2050 POSTING_READ(intel_dp
->output_reg
);
2053 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
2056 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
2057 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
2058 POSTING_READ(intel_dp
->output_reg
);
2059 msleep(intel_dp
->panel_power_down_delay
);
2063 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
2065 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
2066 sizeof(intel_dp
->dpcd
)) == 0)
2067 return false; /* aux transfer failed */
2069 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
2070 return false; /* DPCD not present */
2072 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
2073 DP_DWN_STRM_PORT_PRESENT
))
2074 return true; /* native DP sink */
2076 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
2077 return true; /* no per-port downstream info */
2079 if (intel_dp_aux_native_read_retry(intel_dp
, DP_DOWNSTREAM_PORT_0
,
2080 intel_dp
->downstream_ports
,
2081 DP_MAX_DOWNSTREAM_PORTS
) == 0)
2082 return false; /* downstream port status fetch failed */
2088 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
2092 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
2095 ironlake_edp_panel_vdd_on(intel_dp
);
2097 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
2098 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2099 buf
[0], buf
[1], buf
[2]);
2101 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
2102 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2103 buf
[0], buf
[1], buf
[2]);
2105 ironlake_edp_panel_vdd_off(intel_dp
, false);
2109 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2113 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2114 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2115 sink_irq_vector
, 1);
2123 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2125 /* NAK by default */
2126 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2130 * According to DP spec
2133 * 2. Configure link according to Receiver Capabilities
2134 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2135 * 4. Check link status on receipt of hot-plug interrupt
2139 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2142 u8 link_status
[DP_LINK_STATUS_SIZE
];
2144 if (!intel_dp
->base
.connectors_active
)
2147 if (WARN_ON(!intel_dp
->base
.base
.crtc
))
2150 /* Try to read receiver status if the link appears to be up */
2151 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2152 intel_dp_link_down(intel_dp
);
2156 /* Now read the DPCD to see if it's actually running */
2157 if (!intel_dp_get_dpcd(intel_dp
)) {
2158 intel_dp_link_down(intel_dp
);
2162 /* Try to read the source of the interrupt */
2163 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2164 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2165 /* Clear interrupt source */
2166 intel_dp_aux_native_write_1(intel_dp
,
2167 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2170 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2171 intel_dp_handle_test_request(intel_dp
);
2172 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2173 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2176 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2177 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2178 drm_get_encoder_name(&intel_dp
->base
.base
));
2179 intel_dp_start_link_train(intel_dp
);
2180 intel_dp_complete_link_train(intel_dp
);
2184 /* XXX this is probably wrong for multiple downstream ports */
2185 static enum drm_connector_status
2186 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2188 uint8_t *dpcd
= intel_dp
->dpcd
;
2192 if (!intel_dp_get_dpcd(intel_dp
))
2193 return connector_status_disconnected
;
2195 /* if there's no downstream port, we're done */
2196 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
2197 return connector_status_connected
;
2199 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2200 hpd
= !!(intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
);
2203 if (!intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_COUNT
,
2205 return connector_status_unknown
;
2206 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
2207 : connector_status_disconnected
;
2210 /* If no HPD, poke DDC gently */
2211 if (drm_probe_ddc(&intel_dp
->adapter
))
2212 return connector_status_connected
;
2214 /* Well we tried, say unknown for unreliable port types */
2215 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
2216 if (type
== DP_DS_PORT_TYPE_VGA
|| type
== DP_DS_PORT_TYPE_NON_EDID
)
2217 return connector_status_unknown
;
2219 /* Anything else is out of spec, warn and ignore */
2220 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2221 return connector_status_disconnected
;
2224 static enum drm_connector_status
2225 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2227 enum drm_connector_status status
;
2229 /* Can't disconnect eDP, but you can close the lid... */
2230 if (is_edp(intel_dp
)) {
2231 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2232 if (status
== connector_status_unknown
)
2233 status
= connector_status_connected
;
2237 return intel_dp_detect_dpcd(intel_dp
);
2240 static enum drm_connector_status
2241 g4x_dp_detect(struct intel_dp
*intel_dp
)
2243 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2247 switch (intel_dp
->output_reg
) {
2249 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2252 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2255 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2258 return connector_status_unknown
;
2261 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2262 return connector_status_disconnected
;
2264 return intel_dp_detect_dpcd(intel_dp
);
2267 static struct edid
*
2268 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2270 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2274 if (is_edp(intel_dp
)) {
2275 if (!intel_dp
->edid
)
2278 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2279 edid
= kmalloc(size
, GFP_KERNEL
);
2283 memcpy(edid
, intel_dp
->edid
, size
);
2287 edid
= drm_get_edid(connector
, adapter
);
2292 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2294 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2297 if (is_edp(intel_dp
)) {
2298 drm_mode_connector_update_edid_property(connector
,
2300 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2301 drm_edid_to_eld(connector
,
2303 return intel_dp
->edid_mode_count
;
2306 ret
= intel_ddc_get_modes(connector
, adapter
);
2312 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2314 * \return true if DP port is connected.
2315 * \return false if DP port is disconnected.
2317 static enum drm_connector_status
2318 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2320 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2321 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2322 enum drm_connector_status status
;
2323 struct edid
*edid
= NULL
;
2325 intel_dp
->has_audio
= false;
2327 if (HAS_PCH_SPLIT(dev
))
2328 status
= ironlake_dp_detect(intel_dp
);
2330 status
= g4x_dp_detect(intel_dp
);
2332 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2333 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2334 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2335 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2337 if (status
!= connector_status_connected
)
2340 intel_dp_probe_oui(intel_dp
);
2342 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2343 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2345 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2347 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2352 return connector_status_connected
;
2355 static int intel_dp_get_modes(struct drm_connector
*connector
)
2357 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2358 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2362 /* We should parse the EDID data and find out if it has an audio sink
2365 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2367 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2368 struct drm_display_mode
*newmode
;
2369 list_for_each_entry(newmode
, &connector
->probed_modes
,
2371 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2372 intel_dp
->panel_fixed_mode
=
2373 drm_mode_duplicate(dev
, newmode
);
2381 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2382 if (is_edp(intel_dp
)) {
2383 /* initialize panel mode from VBT if available for eDP */
2384 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2385 intel_dp
->panel_fixed_mode
=
2386 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2387 if (intel_dp
->panel_fixed_mode
) {
2388 intel_dp
->panel_fixed_mode
->type
|=
2389 DRM_MODE_TYPE_PREFERRED
;
2392 if (intel_dp
->panel_fixed_mode
) {
2393 struct drm_display_mode
*mode
;
2394 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2395 drm_mode_probed_add(connector
, mode
);
2403 intel_dp_detect_audio(struct drm_connector
*connector
)
2405 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2407 bool has_audio
= false;
2409 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2411 has_audio
= drm_detect_monitor_audio(edid
);
2419 intel_dp_set_property(struct drm_connector
*connector
,
2420 struct drm_property
*property
,
2423 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2424 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2427 ret
= drm_connector_property_set_value(connector
, property
, val
);
2431 if (property
== dev_priv
->force_audio_property
) {
2435 if (i
== intel_dp
->force_audio
)
2438 intel_dp
->force_audio
= i
;
2440 if (i
== HDMI_AUDIO_AUTO
)
2441 has_audio
= intel_dp_detect_audio(connector
);
2443 has_audio
= (i
== HDMI_AUDIO_ON
);
2445 if (has_audio
== intel_dp
->has_audio
)
2448 intel_dp
->has_audio
= has_audio
;
2452 if (property
== dev_priv
->broadcast_rgb_property
) {
2453 if (val
== !!intel_dp
->color_range
)
2456 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2463 if (intel_dp
->base
.base
.crtc
) {
2464 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2465 intel_set_mode(crtc
, &crtc
->mode
,
2466 crtc
->x
, crtc
->y
, crtc
->fb
);
2473 intel_dp_destroy(struct drm_connector
*connector
)
2475 struct drm_device
*dev
= connector
->dev
;
2477 if (intel_dpd_is_edp(dev
))
2478 intel_panel_destroy_backlight(dev
);
2480 drm_sysfs_connector_remove(connector
);
2481 drm_connector_cleanup(connector
);
2485 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2487 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2489 i2c_del_adapter(&intel_dp
->adapter
);
2490 drm_encoder_cleanup(encoder
);
2491 if (is_edp(intel_dp
)) {
2492 kfree(intel_dp
->edid
);
2493 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2494 ironlake_panel_vdd_off_sync(intel_dp
);
2499 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2500 .mode_fixup
= intel_dp_mode_fixup
,
2501 .mode_set
= intel_dp_mode_set
,
2502 .disable
= intel_encoder_noop
,
2505 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2506 .dpms
= intel_connector_dpms
,
2507 .detect
= intel_dp_detect
,
2508 .fill_modes
= drm_helper_probe_single_connector_modes
,
2509 .set_property
= intel_dp_set_property
,
2510 .destroy
= intel_dp_destroy
,
2513 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2514 .get_modes
= intel_dp_get_modes
,
2515 .mode_valid
= intel_dp_mode_valid
,
2516 .best_encoder
= intel_best_encoder
,
2519 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2520 .destroy
= intel_dp_encoder_destroy
,
2524 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2526 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2528 intel_dp_check_link_status(intel_dp
);
2531 /* Return which DP Port should be selected for Transcoder DP control */
2533 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2535 struct drm_device
*dev
= crtc
->dev
;
2536 struct intel_encoder
*encoder
;
2538 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2539 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2541 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2542 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2543 return intel_dp
->output_reg
;
2549 /* check the VBT to see whether the eDP is on DP-D port */
2550 bool intel_dpd_is_edp(struct drm_device
*dev
)
2552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2553 struct child_device_config
*p_child
;
2556 if (!dev_priv
->child_dev_num
)
2559 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2560 p_child
= dev_priv
->child_dev
+ i
;
2562 if (p_child
->dvo_port
== PORT_IDPD
&&
2563 p_child
->device_type
== DEVICE_TYPE_eDP
)
2570 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2572 intel_attach_force_audio_property(connector
);
2573 intel_attach_broadcast_rgb_property(connector
);
2577 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
2579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2580 struct drm_connector
*connector
;
2581 struct intel_dp
*intel_dp
;
2582 struct intel_encoder
*intel_encoder
;
2583 struct intel_connector
*intel_connector
;
2584 const char *name
= NULL
;
2587 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2591 intel_dp
->output_reg
= output_reg
;
2592 intel_dp
->port
= port
;
2593 /* Preserve the current hw state. */
2594 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
2596 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2597 if (!intel_connector
) {
2601 intel_encoder
= &intel_dp
->base
;
2603 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2604 if (intel_dpd_is_edp(dev
))
2605 intel_dp
->is_pch_edp
= true;
2608 * FIXME : We need to initialize built-in panels before external panels.
2609 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2611 if (IS_VALLEYVIEW(dev
) && output_reg
== DP_C
) {
2612 type
= DRM_MODE_CONNECTOR_eDP
;
2613 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2614 } else if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2615 type
= DRM_MODE_CONNECTOR_eDP
;
2616 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2618 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2619 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2622 connector
= &intel_connector
->base
;
2623 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2624 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2626 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2628 intel_encoder
->cloneable
= false;
2630 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2631 ironlake_panel_vdd_work
);
2633 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2635 connector
->interlace_allowed
= true;
2636 connector
->doublescan_allowed
= 0;
2638 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2639 DRM_MODE_ENCODER_TMDS
);
2640 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2642 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2643 drm_sysfs_connector_add(connector
);
2645 intel_encoder
->enable
= intel_enable_dp
;
2646 intel_encoder
->pre_enable
= intel_pre_enable_dp
;
2647 intel_encoder
->disable
= intel_disable_dp
;
2648 intel_encoder
->post_disable
= intel_post_disable_dp
;
2649 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
2650 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
2652 /* Set up the DDC bus. */
2658 dev_priv
->hotplug_supported_mask
|= DPB_HOTPLUG_INT_STATUS
;
2662 dev_priv
->hotplug_supported_mask
|= DPC_HOTPLUG_INT_STATUS
;
2666 dev_priv
->hotplug_supported_mask
|= DPD_HOTPLUG_INT_STATUS
;
2670 WARN(1, "Invalid port %c\n", port_name(port
));
2674 /* Cache some DPCD data in the eDP case */
2675 if (is_edp(intel_dp
)) {
2676 struct edp_power_seq cur
, vbt
;
2677 u32 pp_on
, pp_off
, pp_div
;
2679 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2680 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2681 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2683 if (!pp_on
|| !pp_off
|| !pp_div
) {
2684 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2685 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2686 intel_dp_destroy(&intel_connector
->base
);
2690 /* Pull timing values out of registers */
2691 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2692 PANEL_POWER_UP_DELAY_SHIFT
;
2694 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2695 PANEL_LIGHT_ON_DELAY_SHIFT
;
2697 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2698 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2700 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2701 PANEL_POWER_DOWN_DELAY_SHIFT
;
2703 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2704 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2706 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2707 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2709 vbt
= dev_priv
->edp
.pps
;
2711 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2712 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2714 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2716 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2717 intel_dp
->backlight_on_delay
= get_delay(t8
);
2718 intel_dp
->backlight_off_delay
= get_delay(t9
);
2719 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2720 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2722 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2723 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2724 intel_dp
->panel_power_cycle_delay
);
2726 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2727 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2730 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2732 if (is_edp(intel_dp
)) {
2736 ironlake_edp_panel_vdd_on(intel_dp
);
2737 ret
= intel_dp_get_dpcd(intel_dp
);
2738 ironlake_edp_panel_vdd_off(intel_dp
, false);
2741 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2742 dev_priv
->no_aux_handshake
=
2743 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2744 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2746 /* if this fails, presume the device is a ghost */
2747 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2748 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2749 intel_dp_destroy(&intel_connector
->base
);
2753 ironlake_edp_panel_vdd_on(intel_dp
);
2754 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2756 drm_mode_connector_update_edid_property(connector
,
2758 intel_dp
->edid_mode_count
=
2759 drm_add_edid_modes(connector
, edid
);
2760 drm_edid_to_eld(connector
, edid
);
2761 intel_dp
->edid
= edid
;
2763 ironlake_edp_panel_vdd_off(intel_dp
, false);
2766 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2768 if (is_edp(intel_dp
)) {
2769 dev_priv
->int_edp_connector
= connector
;
2770 intel_panel_setup_backlight(dev
);
2773 intel_dp_add_properties(intel_dp
, connector
);
2775 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2776 * 0xd. Failure to do so will result in spurious interrupts being
2777 * generated on the port when a cable is not attached.
2779 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2780 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2781 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);