2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
48 static const struct dp_link_dpll gen4_dpll
[] = {
50 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
52 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
55 static const struct dp_link_dpll pch_dpll
[] = {
57 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
59 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
62 static const struct dp_link_dpll vlv_dpll
[] = {
64 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
66 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
73 static const struct dp_link_dpll chv_dpll
[] = {
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
79 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
81 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
82 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
83 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
84 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
94 static bool is_edp(struct intel_dp
*intel_dp
)
96 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
98 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
101 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
103 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
105 return intel_dig_port
->base
.base
.dev
;
108 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
110 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
113 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
114 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
115 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
118 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
120 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
121 struct drm_device
*dev
= intel_dp
->attached_connector
->base
.dev
;
123 switch (max_link_bw
) {
124 case DP_LINK_BW_1_62
:
127 case DP_LINK_BW_5_4
: /* 1.2 capable displays may advertise higher bw */
128 if (((IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)) ||
129 INTEL_INFO(dev
)->gen
>= 8) &&
130 intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12)
131 max_link_bw
= DP_LINK_BW_5_4
;
133 max_link_bw
= DP_LINK_BW_2_7
;
136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw
= DP_LINK_BW_1_62
;
144 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
146 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
147 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
148 u8 source_max
, sink_max
;
151 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
152 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
155 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
157 return min(source_max
, sink_max
);
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 * 270000 * 1 * 8 / 10 == 216000
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
178 intel_dp_link_required(int pixel_clock
, int bpp
)
180 return (pixel_clock
* bpp
+ 9) / 10;
184 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
186 return (max_link_clock
* max_lanes
* 8) / 10;
189 static enum drm_mode_status
190 intel_dp_mode_valid(struct drm_connector
*connector
,
191 struct drm_display_mode
*mode
)
193 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
194 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
195 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
196 int target_clock
= mode
->clock
;
197 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
199 if (is_edp(intel_dp
) && fixed_mode
) {
200 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
203 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
206 target_clock
= fixed_mode
->clock
;
209 max_link_clock
= drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp
));
210 max_lanes
= intel_dp_max_lane_count(intel_dp
);
212 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
213 mode_rate
= intel_dp_link_required(target_clock
, 18);
215 if (mode_rate
> max_rate
)
216 return MODE_CLOCK_HIGH
;
218 if (mode
->clock
< 10000)
219 return MODE_CLOCK_LOW
;
221 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
222 return MODE_H_ILLEGAL
;
228 pack_aux(uint8_t *src
, int src_bytes
)
235 for (i
= 0; i
< src_bytes
; i
++)
236 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
241 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
246 for (i
= 0; i
< dst_bytes
; i
++)
247 dst
[i
] = src
>> ((3-i
) * 8);
250 /* hrawclock is 1/4 the FSB frequency */
252 intel_hrawclk(struct drm_device
*dev
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev
))
261 clkcfg
= I915_READ(CLKCFG
);
262 switch (clkcfg
& CLKCFG_FSB_MASK
) {
271 case CLKCFG_FSB_1067
:
273 case CLKCFG_FSB_1333
:
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600
:
277 case CLKCFG_FSB_1600_ALT
:
285 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
286 struct intel_dp
*intel_dp
,
287 struct edp_power_seq
*out
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
,
291 struct edp_power_seq
*out
);
293 static void pps_lock(struct intel_dp
*intel_dp
)
295 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
296 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
297 struct drm_device
*dev
= encoder
->base
.dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 enum intel_display_power_domain power_domain
;
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
305 power_domain
= intel_display_port_power_domain(encoder
);
306 intel_display_power_get(dev_priv
, power_domain
);
308 mutex_lock(&dev_priv
->pps_mutex
);
311 static void pps_unlock(struct intel_dp
*intel_dp
)
313 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
314 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
315 struct drm_device
*dev
= encoder
->base
.dev
;
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
317 enum intel_display_power_domain power_domain
;
319 mutex_unlock(&dev_priv
->pps_mutex
);
321 power_domain
= intel_display_port_power_domain(encoder
);
322 intel_display_power_put(dev_priv
, power_domain
);
326 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
328 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
329 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
331 struct intel_encoder
*encoder
;
332 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
333 struct edp_power_seq power_seq
;
335 lockdep_assert_held(&dev_priv
->pps_mutex
);
337 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
338 return intel_dp
->pps_pipe
;
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
344 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
346 struct intel_dp
*tmp
;
348 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
351 tmp
= enc_to_intel_dp(&encoder
->base
);
353 if (tmp
->pps_pipe
!= INVALID_PIPE
)
354 pipes
&= ~(1 << tmp
->pps_pipe
);
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
361 if (WARN_ON(pipes
== 0))
364 intel_dp
->pps_pipe
= ffs(pipes
) - 1;
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp
->pps_pipe
),
368 port_name(intel_dig_port
->port
));
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
372 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
375 return intel_dp
->pps_pipe
;
378 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
381 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
387 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
393 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
400 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
402 vlv_pipe_check pipe_check
)
406 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
407 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
408 PANEL_PORT_SELECT_MASK
;
410 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
413 if (!pipe_check(dev_priv
, pipe
))
423 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
425 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
426 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
428 struct edp_power_seq power_seq
;
429 enum port port
= intel_dig_port
->port
;
431 lockdep_assert_held(&dev_priv
->pps_mutex
);
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
439 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
440 vlv_pipe_has_vdd_on
);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
443 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
456 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
457 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
461 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
463 struct drm_device
*dev
= dev_priv
->dev
;
464 struct intel_encoder
*encoder
;
466 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
479 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
480 struct intel_dp
*intel_dp
;
482 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
485 intel_dp
= enc_to_intel_dp(&encoder
->base
);
486 intel_dp
->pps_pipe
= INVALID_PIPE
;
490 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
492 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
494 if (HAS_PCH_SPLIT(dev
))
495 return PCH_PP_CONTROL
;
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
500 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
502 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
504 if (HAS_PCH_SPLIT(dev
))
505 return PCH_PP_STATUS
;
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
510 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
515 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
517 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
520 u32 pp_ctrl_reg
, pp_div_reg
;
522 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
527 if (IS_VALLEYVIEW(dev
)) {
528 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
530 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
531 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
532 pp_div
= I915_READ(pp_div_reg
);
533 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
537 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
538 msleep(intel_dp
->panel_power_cycle_delay
);
541 pps_unlock(intel_dp
);
546 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
548 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
551 lockdep_assert_held(&dev_priv
->pps_mutex
);
553 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
558 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
559 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 lockdep_assert_held(&dev_priv
->pps_mutex
);
563 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
567 intel_dp_check_edp(struct intel_dp
*intel_dp
)
569 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
572 if (!is_edp(intel_dp
))
575 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp
)),
579 I915_READ(_pp_ctrl_reg(intel_dp
)));
584 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
586 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
587 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
596 msecs_to_jiffies_timeout(10));
598 done
= wait_for_atomic(C
, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
609 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
610 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index
? 0 : intel_hrawclk(dev
) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
622 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
627 if (intel_dig_port
->port
== PORT_A
) {
628 if (IS_GEN6(dev
) || IS_GEN7(dev
))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
639 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
640 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
643 if (intel_dig_port
->port
== PORT_A
) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv
), 2000);
647 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
648 /* Workaround for non-ULT HSW */
655 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
661 return index
? 0 : 100;
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
667 uint32_t aux_clock_divider
)
669 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
670 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
671 uint32_t precharge
, timeout
;
678 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
679 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
681 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
683 return DP_AUX_CH_CTL_SEND_BUSY
|
685 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
686 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
688 DP_AUX_CH_CTL_RECEIVE_ERROR
|
689 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
690 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
691 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
695 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
696 uint8_t *send
, int send_bytes
,
697 uint8_t *recv
, int recv_size
)
699 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
700 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
703 uint32_t ch_data
= ch_ctl
+ 4;
704 uint32_t aux_clock_divider
;
705 int i
, ret
, recv_bytes
;
708 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
719 vdd
= edp_panel_vdd_on(intel_dp
);
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
725 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
727 intel_dp_check_edp(intel_dp
);
729 intel_aux_display_runtime_get(dev_priv
);
731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
733 status
= I915_READ_NOTRACE(ch_ctl
);
734 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
752 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
753 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i
= 0; i
< send_bytes
; i
+= 4)
762 I915_WRITE(ch_data
+ i
,
763 pack_aux(send
+ i
, send_bytes
- i
));
765 /* Send the command and wait for it to complete */
766 I915_WRITE(ch_ctl
, send_ctl
);
768 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
770 /* Clear done status and any errors */
774 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
775 DP_AUX_CH_CTL_RECEIVE_ERROR
);
777 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
778 DP_AUX_CH_CTL_RECEIVE_ERROR
))
780 if (status
& DP_AUX_CH_CTL_DONE
)
783 if (status
& DP_AUX_CH_CTL_DONE
)
787 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
796 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
804 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
810 /* Unload any bytes sent back from the other side */
811 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
813 if (recv_bytes
> recv_size
)
814 recv_bytes
= recv_size
;
816 for (i
= 0; i
< recv_bytes
; i
+= 4)
817 unpack_aux(I915_READ(ch_data
+ i
),
818 recv
+ i
, recv_bytes
- i
);
822 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
823 intel_aux_display_runtime_put(dev_priv
);
826 edp_panel_vdd_off(intel_dp
, false);
828 pps_unlock(intel_dp
);
833 #define BARE_ADDRESS_SIZE 3
834 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
836 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
838 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
839 uint8_t txbuf
[20], rxbuf
[20];
840 size_t txsize
, rxsize
;
843 txbuf
[0] = msg
->request
<< 4;
844 txbuf
[1] = msg
->address
>> 8;
845 txbuf
[2] = msg
->address
& 0xff;
846 txbuf
[3] = msg
->size
- 1;
848 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
849 case DP_AUX_NATIVE_WRITE
:
850 case DP_AUX_I2C_WRITE
:
851 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
854 if (WARN_ON(txsize
> 20))
857 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
859 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
861 msg
->reply
= rxbuf
[0] >> 4;
863 /* Return payload size. */
868 case DP_AUX_NATIVE_READ
:
869 case DP_AUX_I2C_READ
:
870 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
871 rxsize
= msg
->size
+ 1;
873 if (WARN_ON(rxsize
> 20))
876 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
878 msg
->reply
= rxbuf
[0] >> 4;
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
883 * Return payload size.
886 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
899 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
901 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
902 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
903 enum port port
= intel_dig_port
->port
;
904 const char *name
= NULL
;
909 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
913 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
917 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
921 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
929 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
931 intel_dp
->aux
.name
= name
;
932 intel_dp
->aux
.dev
= dev
->dev
;
933 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
935 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
936 connector
->base
.kdev
->kobj
.name
);
938 ret
= drm_dp_aux_register(&intel_dp
->aux
);
940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
945 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
946 &intel_dp
->aux
.ddc
.dev
.kobj
,
947 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
950 drm_dp_aux_unregister(&intel_dp
->aux
);
955 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
957 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
959 if (!intel_connector
->mst_port
)
960 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
961 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
962 intel_connector_unregister(intel_connector
);
966 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config
*pipe_config
, int link_bw
)
969 case DP_LINK_BW_1_62
:
970 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
973 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
976 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
982 intel_dp_set_clock(struct intel_encoder
*encoder
,
983 struct intel_crtc_config
*pipe_config
, int link_bw
)
985 struct drm_device
*dev
= encoder
->base
.dev
;
986 const struct dp_link_dpll
*divisor
= NULL
;
991 count
= ARRAY_SIZE(gen4_dpll
);
992 } else if (HAS_PCH_SPLIT(dev
)) {
994 count
= ARRAY_SIZE(pch_dpll
);
995 } else if (IS_CHERRYVIEW(dev
)) {
997 count
= ARRAY_SIZE(chv_dpll
);
998 } else if (IS_VALLEYVIEW(dev
)) {
1000 count
= ARRAY_SIZE(vlv_dpll
);
1003 if (divisor
&& count
) {
1004 for (i
= 0; i
< count
; i
++) {
1005 if (link_bw
== divisor
[i
].link_bw
) {
1006 pipe_config
->dpll
= divisor
[i
].dpll
;
1007 pipe_config
->clock_set
= true;
1015 intel_dp_compute_config(struct intel_encoder
*encoder
,
1016 struct intel_crtc_config
*pipe_config
)
1018 struct drm_device
*dev
= encoder
->base
.dev
;
1019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1020 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
1021 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1022 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1023 struct intel_crtc
*intel_crtc
= encoder
->new_crtc
;
1024 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1025 int lane_count
, clock
;
1026 int min_lane_count
= 1;
1027 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1028 /* Conveniently, the link BW constants become indices with a shift...*/
1030 int max_clock
= intel_dp_max_link_bw(intel_dp
) >> 3;
1032 static int bws
[] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
, DP_LINK_BW_5_4
};
1033 int link_avail
, link_clock
;
1035 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1036 pipe_config
->has_pch_encoder
= true;
1038 pipe_config
->has_dp_encoder
= true;
1039 pipe_config
->has_drrs
= false;
1040 pipe_config
->has_audio
= intel_dp
->has_audio
;
1042 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1043 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1045 if (!HAS_PCH_SPLIT(dev
))
1046 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1047 intel_connector
->panel
.fitting_mode
);
1049 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1050 intel_connector
->panel
.fitting_mode
);
1053 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
1058 max_lane_count
, bws
[max_clock
],
1059 adjusted_mode
->crtc_clock
);
1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
1063 bpp
= pipe_config
->pipe_bpp
;
1064 if (is_edp(intel_dp
)) {
1065 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv
->vbt
.edp_bpp
);
1068 bpp
= dev_priv
->vbt
.edp_bpp
;
1071 if (IS_BROADWELL(dev
)) {
1072 /* Yes, it's an ugly hack. */
1073 min_lane_count
= max_lane_count
;
1074 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1076 } else if (dev_priv
->vbt
.edp_lanes
) {
1077 min_lane_count
= min(dev_priv
->vbt
.edp_lanes
,
1079 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1083 if (dev_priv
->vbt
.edp_rate
) {
1084 min_clock
= min(dev_priv
->vbt
.edp_rate
>> 3, max_clock
);
1085 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1090 for (; bpp
>= 6*3; bpp
-= 2*3) {
1091 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1094 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1095 for (lane_count
= min_lane_count
; lane_count
<= max_lane_count
; lane_count
<<= 1) {
1096 link_clock
= drm_dp_bw_code_to_link_rate(bws
[clock
]);
1097 link_avail
= intel_dp_max_data_rate(link_clock
,
1100 if (mode_rate
<= link_avail
) {
1110 if (intel_dp
->color_range_auto
) {
1113 * CEA-861-E - 5.1 Default Encoding Parameters
1114 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1116 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1117 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1119 intel_dp
->color_range
= 0;
1122 if (intel_dp
->color_range
)
1123 pipe_config
->limited_color_range
= true;
1125 intel_dp
->link_bw
= bws
[clock
];
1126 intel_dp
->lane_count
= lane_count
;
1127 pipe_config
->pipe_bpp
= bpp
;
1128 pipe_config
->port_clock
= drm_dp_bw_code_to_link_rate(intel_dp
->link_bw
);
1130 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1131 intel_dp
->link_bw
, intel_dp
->lane_count
,
1132 pipe_config
->port_clock
, bpp
);
1133 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1134 mode_rate
, link_avail
);
1136 intel_link_compute_m_n(bpp
, lane_count
,
1137 adjusted_mode
->crtc_clock
,
1138 pipe_config
->port_clock
,
1139 &pipe_config
->dp_m_n
);
1141 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1142 intel_dp
->drrs_state
.type
== SEAMLESS_DRRS_SUPPORT
) {
1143 pipe_config
->has_drrs
= true;
1144 intel_link_compute_m_n(bpp
, lane_count
,
1145 intel_connector
->panel
.downclock_mode
->clock
,
1146 pipe_config
->port_clock
,
1147 &pipe_config
->dp_m2_n2
);
1150 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1151 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1153 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1158 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1160 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1161 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1162 struct drm_device
*dev
= crtc
->base
.dev
;
1163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1166 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc
->config
.port_clock
);
1167 dpa_ctl
= I915_READ(DP_A
);
1168 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1170 if (crtc
->config
.port_clock
== 162000) {
1171 /* For a long time we've carried around a ILK-DevA w/a for the
1172 * 160MHz clock. If we're really unlucky, it's still required.
1174 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1175 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1176 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1178 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1179 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1182 I915_WRITE(DP_A
, dpa_ctl
);
1188 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1190 struct drm_device
*dev
= encoder
->base
.dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1192 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1193 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1194 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1195 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
1198 * There are four kinds of DP registers:
1205 * IBX PCH and CPU are the same for almost everything,
1206 * except that the CPU DP PLL is configured in this
1209 * CPT PCH is quite different, having many bits moved
1210 * to the TRANS_DP_CTL register instead. That
1211 * configuration happens (oddly) in ironlake_pch_enable
1214 /* Preserve the BIOS-computed detected bit. This is
1215 * supposed to be read-only.
1217 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1219 /* Handle DP bits in common between all three register formats */
1220 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1221 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1223 if (crtc
->config
.has_audio
) {
1224 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1225 pipe_name(crtc
->pipe
));
1226 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1227 intel_write_eld(&encoder
->base
, adjusted_mode
);
1230 /* Split out the IBX/CPU vs CPT settings */
1232 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1233 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1234 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1235 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1236 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1237 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1239 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1240 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1242 intel_dp
->DP
|= crtc
->pipe
<< 29;
1243 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1244 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1245 intel_dp
->DP
|= intel_dp
->color_range
;
1247 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1248 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1249 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1250 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1251 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1253 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1254 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1256 if (!IS_CHERRYVIEW(dev
)) {
1257 if (crtc
->pipe
== 1)
1258 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1260 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1263 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1267 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1268 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1270 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1271 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1273 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1274 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1276 static void wait_panel_status(struct intel_dp
*intel_dp
,
1280 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1282 u32 pp_stat_reg
, pp_ctrl_reg
;
1284 lockdep_assert_held(&dev_priv
->pps_mutex
);
1286 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1287 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1289 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1291 I915_READ(pp_stat_reg
),
1292 I915_READ(pp_ctrl_reg
));
1294 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1295 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1296 I915_READ(pp_stat_reg
),
1297 I915_READ(pp_ctrl_reg
));
1300 DRM_DEBUG_KMS("Wait complete\n");
1303 static void wait_panel_on(struct intel_dp
*intel_dp
)
1305 DRM_DEBUG_KMS("Wait for panel power on\n");
1306 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1309 static void wait_panel_off(struct intel_dp
*intel_dp
)
1311 DRM_DEBUG_KMS("Wait for panel power off time\n");
1312 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1315 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1317 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1319 /* When we disable the VDD override bit last we have to do the manual
1321 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1322 intel_dp
->panel_power_cycle_delay
);
1324 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1327 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1329 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1330 intel_dp
->backlight_on_delay
);
1333 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1335 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1336 intel_dp
->backlight_off_delay
);
1339 /* Read the current pp_control value, unlocking the register if it
1343 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1345 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1349 lockdep_assert_held(&dev_priv
->pps_mutex
);
1351 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1352 control
&= ~PANEL_UNLOCK_MASK
;
1353 control
|= PANEL_UNLOCK_REGS
;
1358 * Must be paired with edp_panel_vdd_off().
1359 * Must hold pps_mutex around the whole on/off sequence.
1360 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1362 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1364 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1365 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1366 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 enum intel_display_power_domain power_domain
;
1370 u32 pp_stat_reg
, pp_ctrl_reg
;
1371 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1373 lockdep_assert_held(&dev_priv
->pps_mutex
);
1375 if (!is_edp(intel_dp
))
1378 intel_dp
->want_panel_vdd
= true;
1380 if (edp_have_panel_vdd(intel_dp
))
1381 return need_to_disable
;
1383 power_domain
= intel_display_port_power_domain(intel_encoder
);
1384 intel_display_power_get(dev_priv
, power_domain
);
1386 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1388 if (!edp_have_panel_power(intel_dp
))
1389 wait_panel_power_cycle(intel_dp
);
1391 pp
= ironlake_get_pp_control(intel_dp
);
1392 pp
|= EDP_FORCE_VDD
;
1394 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1395 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1397 I915_WRITE(pp_ctrl_reg
, pp
);
1398 POSTING_READ(pp_ctrl_reg
);
1399 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1400 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1402 * If the panel wasn't on, delay before accessing aux channel
1404 if (!edp_have_panel_power(intel_dp
)) {
1405 DRM_DEBUG_KMS("eDP was not running\n");
1406 msleep(intel_dp
->panel_power_up_delay
);
1409 return need_to_disable
;
1413 * Must be paired with intel_edp_panel_vdd_off() or
1414 * intel_edp_panel_off().
1415 * Nested calls to these functions are not allowed since
1416 * we drop the lock. Caller must use some higher level
1417 * locking to prevent nested calls from other threads.
1419 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1423 if (!is_edp(intel_dp
))
1427 vdd
= edp_panel_vdd_on(intel_dp
);
1428 pps_unlock(intel_dp
);
1430 WARN(!vdd
, "eDP VDD already requested on\n");
1433 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1435 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1437 struct intel_digital_port
*intel_dig_port
=
1438 dp_to_dig_port(intel_dp
);
1439 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1440 enum intel_display_power_domain power_domain
;
1442 u32 pp_stat_reg
, pp_ctrl_reg
;
1444 lockdep_assert_held(&dev_priv
->pps_mutex
);
1446 WARN_ON(intel_dp
->want_panel_vdd
);
1448 if (!edp_have_panel_vdd(intel_dp
))
1451 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1453 pp
= ironlake_get_pp_control(intel_dp
);
1454 pp
&= ~EDP_FORCE_VDD
;
1456 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1457 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1459 I915_WRITE(pp_ctrl_reg
, pp
);
1460 POSTING_READ(pp_ctrl_reg
);
1462 /* Make sure sequencer is idle before allowing subsequent activity */
1463 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1464 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1466 if ((pp
& POWER_TARGET_ON
) == 0)
1467 intel_dp
->last_power_cycle
= jiffies
;
1469 power_domain
= intel_display_port_power_domain(intel_encoder
);
1470 intel_display_power_put(dev_priv
, power_domain
);
1473 static void edp_panel_vdd_work(struct work_struct
*__work
)
1475 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1476 struct intel_dp
, panel_vdd_work
);
1479 if (!intel_dp
->want_panel_vdd
)
1480 edp_panel_vdd_off_sync(intel_dp
);
1481 pps_unlock(intel_dp
);
1484 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1486 unsigned long delay
;
1489 * Queue the timer to fire a long time from now (relative to the power
1490 * down delay) to keep the panel power up across a sequence of
1493 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1494 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1498 * Must be paired with edp_panel_vdd_on().
1499 * Must hold pps_mutex around the whole on/off sequence.
1500 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1502 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1504 struct drm_i915_private
*dev_priv
=
1505 intel_dp_to_dev(intel_dp
)->dev_private
;
1507 lockdep_assert_held(&dev_priv
->pps_mutex
);
1509 if (!is_edp(intel_dp
))
1512 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1514 intel_dp
->want_panel_vdd
= false;
1517 edp_panel_vdd_off_sync(intel_dp
);
1519 edp_panel_vdd_schedule_off(intel_dp
);
1523 * Must be paired with intel_edp_panel_vdd_on().
1524 * Nested calls to these functions are not allowed since
1525 * we drop the lock. Caller must use some higher level
1526 * locking to prevent nested calls from other threads.
1528 static void intel_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1530 if (!is_edp(intel_dp
))
1534 edp_panel_vdd_off(intel_dp
, sync
);
1535 pps_unlock(intel_dp
);
1538 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1540 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1545 if (!is_edp(intel_dp
))
1548 DRM_DEBUG_KMS("Turn eDP power on\n");
1552 if (edp_have_panel_power(intel_dp
)) {
1553 DRM_DEBUG_KMS("eDP power already on\n");
1557 wait_panel_power_cycle(intel_dp
);
1559 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1560 pp
= ironlake_get_pp_control(intel_dp
);
1562 /* ILK workaround: disable reset around power sequence */
1563 pp
&= ~PANEL_POWER_RESET
;
1564 I915_WRITE(pp_ctrl_reg
, pp
);
1565 POSTING_READ(pp_ctrl_reg
);
1568 pp
|= POWER_TARGET_ON
;
1570 pp
|= PANEL_POWER_RESET
;
1572 I915_WRITE(pp_ctrl_reg
, pp
);
1573 POSTING_READ(pp_ctrl_reg
);
1575 wait_panel_on(intel_dp
);
1576 intel_dp
->last_power_on
= jiffies
;
1579 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1580 I915_WRITE(pp_ctrl_reg
, pp
);
1581 POSTING_READ(pp_ctrl_reg
);
1585 pps_unlock(intel_dp
);
1588 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1590 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1591 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1592 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1594 enum intel_display_power_domain power_domain
;
1598 if (!is_edp(intel_dp
))
1601 DRM_DEBUG_KMS("Turn eDP power off\n");
1605 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1607 pp
= ironlake_get_pp_control(intel_dp
);
1608 /* We need to switch off panel power _and_ force vdd, for otherwise some
1609 * panels get very unhappy and cease to work. */
1610 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1613 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1615 intel_dp
->want_panel_vdd
= false;
1617 I915_WRITE(pp_ctrl_reg
, pp
);
1618 POSTING_READ(pp_ctrl_reg
);
1620 intel_dp
->last_power_cycle
= jiffies
;
1621 wait_panel_off(intel_dp
);
1623 /* We got a reference when we enabled the VDD. */
1624 power_domain
= intel_display_port_power_domain(intel_encoder
);
1625 intel_display_power_put(dev_priv
, power_domain
);
1627 pps_unlock(intel_dp
);
1630 /* Enable backlight in the panel power control. */
1631 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1633 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1634 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1640 * If we enable the backlight right away following a panel power
1641 * on, we may see slight flicker as the panel syncs with the eDP
1642 * link. So delay a bit to make sure the image is solid before
1643 * allowing it to appear.
1645 wait_backlight_on(intel_dp
);
1649 pp
= ironlake_get_pp_control(intel_dp
);
1650 pp
|= EDP_BLC_ENABLE
;
1652 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1654 I915_WRITE(pp_ctrl_reg
, pp
);
1655 POSTING_READ(pp_ctrl_reg
);
1657 pps_unlock(intel_dp
);
1660 /* Enable backlight PWM and backlight PP control. */
1661 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1663 if (!is_edp(intel_dp
))
1666 DRM_DEBUG_KMS("\n");
1668 intel_panel_enable_backlight(intel_dp
->attached_connector
);
1669 _intel_edp_backlight_on(intel_dp
);
1672 /* Disable backlight in the panel power control. */
1673 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1675 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 if (!is_edp(intel_dp
))
1685 pp
= ironlake_get_pp_control(intel_dp
);
1686 pp
&= ~EDP_BLC_ENABLE
;
1688 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1690 I915_WRITE(pp_ctrl_reg
, pp
);
1691 POSTING_READ(pp_ctrl_reg
);
1693 pps_unlock(intel_dp
);
1695 intel_dp
->last_backlight_off
= jiffies
;
1696 edp_wait_backlight_off(intel_dp
);
1699 /* Disable backlight PP control and backlight PWM. */
1700 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
1702 if (!is_edp(intel_dp
))
1705 DRM_DEBUG_KMS("\n");
1707 _intel_edp_backlight_off(intel_dp
);
1708 intel_panel_disable_backlight(intel_dp
->attached_connector
);
1712 * Hook for controlling the panel power control backlight through the bl_power
1713 * sysfs attribute. Take care to handle multiple calls.
1715 static void intel_edp_backlight_power(struct intel_connector
*connector
,
1718 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
1722 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
1723 pps_unlock(intel_dp
);
1725 if (is_enabled
== enable
)
1728 DRM_DEBUG_KMS("panel power control backlight %s\n",
1729 enable
? "enable" : "disable");
1732 _intel_edp_backlight_on(intel_dp
);
1734 _intel_edp_backlight_off(intel_dp
);
1737 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
1739 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1740 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1741 struct drm_device
*dev
= crtc
->dev
;
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 assert_pipe_disabled(dev_priv
,
1746 to_intel_crtc(crtc
)->pipe
);
1748 DRM_DEBUG_KMS("\n");
1749 dpa_ctl
= I915_READ(DP_A
);
1750 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
1751 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1753 /* We don't adjust intel_dp->DP while tearing down the link, to
1754 * facilitate link retraining (e.g. after hotplug). Hence clear all
1755 * enable bits here to ensure that we don't enable too much. */
1756 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
1757 intel_dp
->DP
|= DP_PLL_ENABLE
;
1758 I915_WRITE(DP_A
, intel_dp
->DP
);
1763 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
1765 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1766 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
1767 struct drm_device
*dev
= crtc
->dev
;
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1771 assert_pipe_disabled(dev_priv
,
1772 to_intel_crtc(crtc
)->pipe
);
1774 dpa_ctl
= I915_READ(DP_A
);
1775 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
1776 "dp pll off, should be on\n");
1777 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
1779 /* We can't rely on the value tracked for the DP register in
1780 * intel_dp->DP because link_down must not change that (otherwise link
1781 * re-training will fail. */
1782 dpa_ctl
&= ~DP_PLL_ENABLE
;
1783 I915_WRITE(DP_A
, dpa_ctl
);
1788 /* If the sink supports it, try to set the power state appropriately */
1789 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1793 /* Should have a valid DPCD by this point */
1794 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1797 if (mode
!= DRM_MODE_DPMS_ON
) {
1798 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1802 * When turning on, we need to retry for 1ms to give the sink
1805 for (i
= 0; i
< 3; i
++) {
1806 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
1815 DRM_DEBUG_KMS("failed to %s sink power state\n",
1816 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
1819 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
1822 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1823 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1824 struct drm_device
*dev
= encoder
->base
.dev
;
1825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1826 enum intel_display_power_domain power_domain
;
1829 power_domain
= intel_display_port_power_domain(encoder
);
1830 if (!intel_display_power_enabled(dev_priv
, power_domain
))
1833 tmp
= I915_READ(intel_dp
->output_reg
);
1835 if (!(tmp
& DP_PORT_EN
))
1838 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1839 *pipe
= PORT_TO_PIPE_CPT(tmp
);
1840 } else if (IS_CHERRYVIEW(dev
)) {
1841 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
1842 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1843 *pipe
= PORT_TO_PIPE(tmp
);
1849 switch (intel_dp
->output_reg
) {
1851 trans_sel
= TRANS_DP_PORT_SEL_B
;
1854 trans_sel
= TRANS_DP_PORT_SEL_C
;
1857 trans_sel
= TRANS_DP_PORT_SEL_D
;
1863 for_each_pipe(dev_priv
, i
) {
1864 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
1865 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
1871 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1872 intel_dp
->output_reg
);
1878 static void intel_dp_get_config(struct intel_encoder
*encoder
,
1879 struct intel_crtc_config
*pipe_config
)
1881 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1883 struct drm_device
*dev
= encoder
->base
.dev
;
1884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1885 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1886 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1889 tmp
= I915_READ(intel_dp
->output_reg
);
1890 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
1891 pipe_config
->has_audio
= true;
1893 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
1894 if (tmp
& DP_SYNC_HS_HIGH
)
1895 flags
|= DRM_MODE_FLAG_PHSYNC
;
1897 flags
|= DRM_MODE_FLAG_NHSYNC
;
1899 if (tmp
& DP_SYNC_VS_HIGH
)
1900 flags
|= DRM_MODE_FLAG_PVSYNC
;
1902 flags
|= DRM_MODE_FLAG_NVSYNC
;
1904 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
1905 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
1906 flags
|= DRM_MODE_FLAG_PHSYNC
;
1908 flags
|= DRM_MODE_FLAG_NHSYNC
;
1910 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
1911 flags
|= DRM_MODE_FLAG_PVSYNC
;
1913 flags
|= DRM_MODE_FLAG_NVSYNC
;
1916 pipe_config
->adjusted_mode
.flags
|= flags
;
1918 pipe_config
->has_dp_encoder
= true;
1920 intel_dp_get_m_n(crtc
, pipe_config
);
1922 if (port
== PORT_A
) {
1923 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
1924 pipe_config
->port_clock
= 162000;
1926 pipe_config
->port_clock
= 270000;
1929 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
1930 &pipe_config
->dp_m_n
);
1932 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
1933 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
1935 pipe_config
->adjusted_mode
.crtc_clock
= dotclock
;
1937 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
1938 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
1940 * This is a big fat ugly hack.
1942 * Some machines in UEFI boot mode provide us a VBT that has 18
1943 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1944 * unknown we fail to light up. Yet the same BIOS boots up with
1945 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1946 * max, not what it tells us to use.
1948 * Note: This will still be broken if the eDP panel is not lit
1949 * up by the BIOS, and thus we can't get the mode at module
1952 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1953 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
1954 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
1958 static bool is_edp_psr(struct intel_dp
*intel_dp
)
1960 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
1963 static bool intel_edp_is_psr_enabled(struct drm_device
*dev
)
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1970 return I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1973 static void intel_edp_psr_write_vsc(struct intel_dp
*intel_dp
,
1974 struct edp_vsc_psr
*vsc_psr
)
1976 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1977 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
1978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1979 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1980 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(crtc
->config
.cpu_transcoder
);
1981 u32 data_reg
= HSW_TVIDEO_DIP_VSC_DATA(crtc
->config
.cpu_transcoder
);
1982 uint32_t *data
= (uint32_t *) vsc_psr
;
1985 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1986 the video DIP being updated before program video DIP data buffer
1987 registers for DIP being updated. */
1988 I915_WRITE(ctl_reg
, 0);
1989 POSTING_READ(ctl_reg
);
1991 for (i
= 0; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4) {
1992 if (i
< sizeof(struct edp_vsc_psr
))
1993 I915_WRITE(data_reg
+ i
, *data
++);
1995 I915_WRITE(data_reg
+ i
, 0);
1998 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
1999 POSTING_READ(ctl_reg
);
2002 static void intel_edp_psr_setup(struct intel_dp
*intel_dp
)
2004 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2006 struct edp_vsc_psr psr_vsc
;
2008 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2009 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
2010 psr_vsc
.sdp_header
.HB0
= 0;
2011 psr_vsc
.sdp_header
.HB1
= 0x7;
2012 psr_vsc
.sdp_header
.HB2
= 0x2;
2013 psr_vsc
.sdp_header
.HB3
= 0x8;
2014 intel_edp_psr_write_vsc(intel_dp
, &psr_vsc
);
2016 /* Avoid continuous PSR exit by masking memup and hpd */
2017 I915_WRITE(EDP_PSR_DEBUG_CTL(dev
), EDP_PSR_DEBUG_MASK_MEMUP
|
2018 EDP_PSR_DEBUG_MASK_HPD
| EDP_PSR_DEBUG_MASK_LPSP
);
2021 static void intel_edp_psr_enable_sink(struct intel_dp
*intel_dp
)
2023 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2024 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2026 uint32_t aux_clock_divider
;
2027 int precharge
= 0x3;
2028 int msg_size
= 5; /* Header(4) + Message(1) */
2029 bool only_standby
= false;
2031 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
2033 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2034 only_standby
= true;
2036 /* Enable PSR in sink */
2037 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
)
2038 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2039 DP_PSR_ENABLE
& ~DP_PSR_MAIN_LINK_ACTIVE
);
2041 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
2042 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
2044 /* Setup AUX registers */
2045 I915_WRITE(EDP_PSR_AUX_DATA1(dev
), EDP_PSR_DPCD_COMMAND
);
2046 I915_WRITE(EDP_PSR_AUX_DATA2(dev
), EDP_PSR_DPCD_NORMAL_OPERATION
);
2047 I915_WRITE(EDP_PSR_AUX_CTL(dev
),
2048 DP_AUX_CH_CTL_TIME_OUT_400us
|
2049 (msg_size
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
2050 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
2051 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
));
2054 static void intel_edp_psr_enable_source(struct intel_dp
*intel_dp
)
2056 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2057 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2059 uint32_t max_sleep_time
= 0x1f;
2060 uint32_t idle_frames
= 1;
2062 const uint32_t link_entry_time
= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
2063 bool only_standby
= false;
2065 if (IS_BROADWELL(dev
) && dig_port
->port
!= PORT_A
)
2066 only_standby
= true;
2068 if (intel_dp
->psr_dpcd
[1] & DP_PSR_NO_TRAIN_ON_EXIT
|| only_standby
) {
2069 val
|= EDP_PSR_LINK_STANDBY
;
2070 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
2071 val
|= EDP_PSR_TP1_TIME_0us
;
2072 val
|= EDP_PSR_SKIP_AUX_EXIT
;
2073 val
|= IS_BROADWELL(dev
) ? BDW_PSR_SINGLE_FRAME
: 0;
2075 val
|= EDP_PSR_LINK_DISABLE
;
2077 I915_WRITE(EDP_PSR_CTL(dev
), val
|
2078 (IS_BROADWELL(dev
) ? 0 : link_entry_time
) |
2079 max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
|
2080 idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
|
2084 static bool intel_edp_psr_match_conditions(struct intel_dp
*intel_dp
)
2086 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
2087 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
2088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2089 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
2090 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2092 lockdep_assert_held(&dev_priv
->psr
.lock
);
2093 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
2094 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
2096 dev_priv
->psr
.source_ok
= false;
2098 if (IS_HASWELL(dev
) && dig_port
->port
!= PORT_A
) {
2099 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2103 if (!i915
.enable_psr
) {
2104 DRM_DEBUG_KMS("PSR disable by flag\n");
2108 /* Below limitations aren't valid for Broadwell */
2109 if (IS_BROADWELL(dev
))
2112 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
.cpu_transcoder
)) &
2114 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2118 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
2119 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2124 dev_priv
->psr
.source_ok
= true;
2128 static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp
)
2130 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2131 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2135 WARN_ON(dev_priv
->psr
.active
);
2136 lockdep_assert_held(&dev_priv
->psr
.lock
);
2138 /* Enable PSR on the panel */
2139 intel_edp_psr_enable_sink(intel_dp
);
2141 /* Enable PSR on the host */
2142 intel_edp_psr_enable_source(intel_dp
);
2144 dev_priv
->psr
.active
= true;
2147 void intel_edp_psr_enable(struct intel_dp
*intel_dp
)
2149 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2152 if (!HAS_PSR(dev
)) {
2153 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2157 if (!is_edp_psr(intel_dp
)) {
2158 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2162 mutex_lock(&dev_priv
->psr
.lock
);
2163 if (dev_priv
->psr
.enabled
) {
2164 DRM_DEBUG_KMS("PSR already in use\n");
2165 mutex_unlock(&dev_priv
->psr
.lock
);
2169 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
2171 /* Setup PSR once */
2172 intel_edp_psr_setup(intel_dp
);
2174 if (intel_edp_psr_match_conditions(intel_dp
))
2175 dev_priv
->psr
.enabled
= intel_dp
;
2176 mutex_unlock(&dev_priv
->psr
.lock
);
2179 void intel_edp_psr_disable(struct intel_dp
*intel_dp
)
2181 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2184 mutex_lock(&dev_priv
->psr
.lock
);
2185 if (!dev_priv
->psr
.enabled
) {
2186 mutex_unlock(&dev_priv
->psr
.lock
);
2190 if (dev_priv
->psr
.active
) {
2191 I915_WRITE(EDP_PSR_CTL(dev
),
2192 I915_READ(EDP_PSR_CTL(dev
)) & ~EDP_PSR_ENABLE
);
2194 /* Wait till PSR is idle */
2195 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev
)) &
2196 EDP_PSR_STATUS_STATE_MASK
) == 0, 2000, 10))
2197 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2199 dev_priv
->psr
.active
= false;
2201 WARN_ON(I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
);
2204 dev_priv
->psr
.enabled
= NULL
;
2205 mutex_unlock(&dev_priv
->psr
.lock
);
2207 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
2210 static void intel_edp_psr_work(struct work_struct
*work
)
2212 struct drm_i915_private
*dev_priv
=
2213 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
2214 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
2216 mutex_lock(&dev_priv
->psr
.lock
);
2217 intel_dp
= dev_priv
->psr
.enabled
;
2223 * The delayed work can race with an invalidate hence we need to
2224 * recheck. Since psr_flush first clears this and then reschedules we
2225 * won't ever miss a flush when bailing out here.
2227 if (dev_priv
->psr
.busy_frontbuffer_bits
)
2230 intel_edp_psr_do_enable(intel_dp
);
2232 mutex_unlock(&dev_priv
->psr
.lock
);
2235 static void intel_edp_psr_do_exit(struct drm_device
*dev
)
2237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2239 if (dev_priv
->psr
.active
) {
2240 u32 val
= I915_READ(EDP_PSR_CTL(dev
));
2242 WARN_ON(!(val
& EDP_PSR_ENABLE
));
2244 I915_WRITE(EDP_PSR_CTL(dev
), val
& ~EDP_PSR_ENABLE
);
2246 dev_priv
->psr
.active
= false;
2251 void intel_edp_psr_invalidate(struct drm_device
*dev
,
2252 unsigned frontbuffer_bits
)
2254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2255 struct drm_crtc
*crtc
;
2258 mutex_lock(&dev_priv
->psr
.lock
);
2259 if (!dev_priv
->psr
.enabled
) {
2260 mutex_unlock(&dev_priv
->psr
.lock
);
2264 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2265 pipe
= to_intel_crtc(crtc
)->pipe
;
2267 intel_edp_psr_do_exit(dev
);
2269 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
2271 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
2272 mutex_unlock(&dev_priv
->psr
.lock
);
2275 void intel_edp_psr_flush(struct drm_device
*dev
,
2276 unsigned frontbuffer_bits
)
2278 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2279 struct drm_crtc
*crtc
;
2282 mutex_lock(&dev_priv
->psr
.lock
);
2283 if (!dev_priv
->psr
.enabled
) {
2284 mutex_unlock(&dev_priv
->psr
.lock
);
2288 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
2289 pipe
= to_intel_crtc(crtc
)->pipe
;
2290 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
2293 * On Haswell sprite plane updates don't result in a psr invalidating
2294 * signal in the hardware. Which means we need to manually fake this in
2295 * software for all flushes, not just when we've seen a preceding
2296 * invalidation through frontbuffer rendering.
2298 if (IS_HASWELL(dev
) &&
2299 (frontbuffer_bits
& INTEL_FRONTBUFFER_SPRITE(pipe
)))
2300 intel_edp_psr_do_exit(dev
);
2302 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
2303 schedule_delayed_work(&dev_priv
->psr
.work
,
2304 msecs_to_jiffies(100));
2305 mutex_unlock(&dev_priv
->psr
.lock
);
2308 void intel_edp_psr_init(struct drm_device
*dev
)
2310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2312 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_edp_psr_work
);
2313 mutex_init(&dev_priv
->psr
.lock
);
2316 static void intel_disable_dp(struct intel_encoder
*encoder
)
2318 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2319 struct drm_device
*dev
= encoder
->base
.dev
;
2321 /* Make sure the panel is off before trying to change the mode. But also
2322 * ensure that we have vdd while we switch off the panel. */
2323 intel_edp_panel_vdd_on(intel_dp
);
2324 intel_edp_backlight_off(intel_dp
);
2325 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2326 intel_edp_panel_off(intel_dp
);
2328 /* disable the port before the pipe on g4x */
2329 if (INTEL_INFO(dev
)->gen
< 5)
2330 intel_dp_link_down(intel_dp
);
2333 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2335 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2336 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2338 intel_dp_link_down(intel_dp
);
2340 ironlake_edp_pll_off(intel_dp
);
2343 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2345 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2347 intel_dp_link_down(intel_dp
);
2350 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2352 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2353 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2354 struct drm_device
*dev
= encoder
->base
.dev
;
2355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2356 struct intel_crtc
*intel_crtc
=
2357 to_intel_crtc(encoder
->base
.crtc
);
2358 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2359 enum pipe pipe
= intel_crtc
->pipe
;
2362 intel_dp_link_down(intel_dp
);
2364 mutex_lock(&dev_priv
->dpio_lock
);
2366 /* Propagate soft reset to data lane reset */
2367 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2368 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2369 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2371 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2372 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2373 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2375 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2376 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2377 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2379 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2380 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2381 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2383 mutex_unlock(&dev_priv
->dpio_lock
);
2387 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2389 uint8_t dp_train_pat
)
2391 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2392 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2394 enum port port
= intel_dig_port
->port
;
2397 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2399 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2400 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2402 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2404 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2405 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2406 case DP_TRAINING_PATTERN_DISABLE
:
2407 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2410 case DP_TRAINING_PATTERN_1
:
2411 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2413 case DP_TRAINING_PATTERN_2
:
2414 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2416 case DP_TRAINING_PATTERN_3
:
2417 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2420 I915_WRITE(DP_TP_CTL(port
), temp
);
2422 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2423 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2425 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2426 case DP_TRAINING_PATTERN_DISABLE
:
2427 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2429 case DP_TRAINING_PATTERN_1
:
2430 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2432 case DP_TRAINING_PATTERN_2
:
2433 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2435 case DP_TRAINING_PATTERN_3
:
2436 DRM_ERROR("DP training pattern 3 not supported\n");
2437 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2442 if (IS_CHERRYVIEW(dev
))
2443 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2445 *DP
&= ~DP_LINK_TRAIN_MASK
;
2447 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2448 case DP_TRAINING_PATTERN_DISABLE
:
2449 *DP
|= DP_LINK_TRAIN_OFF
;
2451 case DP_TRAINING_PATTERN_1
:
2452 *DP
|= DP_LINK_TRAIN_PAT_1
;
2454 case DP_TRAINING_PATTERN_2
:
2455 *DP
|= DP_LINK_TRAIN_PAT_2
;
2457 case DP_TRAINING_PATTERN_3
:
2458 if (IS_CHERRYVIEW(dev
)) {
2459 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2461 DRM_ERROR("DP training pattern 3 not supported\n");
2462 *DP
|= DP_LINK_TRAIN_PAT_2
;
2469 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2471 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2474 intel_dp
->DP
|= DP_PORT_EN
;
2476 /* enable with pattern 1 (as per spec) */
2477 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2478 DP_TRAINING_PATTERN_1
);
2480 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2481 POSTING_READ(intel_dp
->output_reg
);
2484 static void intel_enable_dp(struct intel_encoder
*encoder
)
2486 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2487 struct drm_device
*dev
= encoder
->base
.dev
;
2488 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2489 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2491 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2494 intel_dp_enable_port(intel_dp
);
2495 intel_edp_panel_vdd_on(intel_dp
);
2496 intel_edp_panel_on(intel_dp
);
2497 intel_edp_panel_vdd_off(intel_dp
, true);
2498 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2499 intel_dp_start_link_train(intel_dp
);
2500 intel_dp_complete_link_train(intel_dp
);
2501 intel_dp_stop_link_train(intel_dp
);
2504 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2506 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2508 intel_enable_dp(encoder
);
2509 intel_edp_backlight_on(intel_dp
);
2512 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2514 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2516 intel_edp_backlight_on(intel_dp
);
2519 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2521 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2522 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2524 intel_dp_prepare(encoder
);
2526 /* Only ilk+ has port A */
2527 if (dport
->port
== PORT_A
) {
2528 ironlake_set_pll_cpu_edp(intel_dp
);
2529 ironlake_edp_pll_on(intel_dp
);
2533 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2537 struct intel_encoder
*encoder
;
2539 lockdep_assert_held(&dev_priv
->pps_mutex
);
2541 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2543 struct intel_dp
*intel_dp
;
2546 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2549 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2550 port
= dp_to_dig_port(intel_dp
)->port
;
2552 if (intel_dp
->pps_pipe
!= pipe
)
2555 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2556 pipe_name(pipe
), port_name(port
));
2558 /* make sure vdd is off before we steal it */
2559 edp_panel_vdd_off_sync(intel_dp
);
2561 intel_dp
->pps_pipe
= INVALID_PIPE
;
2565 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2567 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2568 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2569 struct drm_device
*dev
= encoder
->base
.dev
;
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2572 struct edp_power_seq power_seq
;
2574 lockdep_assert_held(&dev_priv
->pps_mutex
);
2576 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2580 * If another power sequencer was being used on this
2581 * port previously make sure to turn off vdd there while
2582 * we still have control of it.
2584 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2585 edp_panel_vdd_off_sync(intel_dp
);
2588 * We may be stealing the power
2589 * sequencer from another port.
2591 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2593 /* now it's all ours */
2594 intel_dp
->pps_pipe
= crtc
->pipe
;
2596 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2597 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2599 /* init power sequencer on this pipe and port */
2600 intel_dp_init_panel_power_sequencer(dev
, intel_dp
, &power_seq
);
2601 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
,
2605 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2607 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2608 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2609 struct drm_device
*dev
= encoder
->base
.dev
;
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2611 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2612 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2613 int pipe
= intel_crtc
->pipe
;
2616 mutex_lock(&dev_priv
->dpio_lock
);
2618 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2625 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2626 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2627 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2629 mutex_unlock(&dev_priv
->dpio_lock
);
2631 if (is_edp(intel_dp
)) {
2633 vlv_init_panel_power_sequencer(intel_dp
);
2634 pps_unlock(intel_dp
);
2637 intel_enable_dp(encoder
);
2639 vlv_wait_port_ready(dev_priv
, dport
);
2642 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2644 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2645 struct drm_device
*dev
= encoder
->base
.dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 struct intel_crtc
*intel_crtc
=
2648 to_intel_crtc(encoder
->base
.crtc
);
2649 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2650 int pipe
= intel_crtc
->pipe
;
2652 intel_dp_prepare(encoder
);
2654 /* Program Tx lane resets to default */
2655 mutex_lock(&dev_priv
->dpio_lock
);
2656 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2657 DPIO_PCS_TX_LANE2_RESET
|
2658 DPIO_PCS_TX_LANE1_RESET
);
2659 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2660 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2661 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2662 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2663 DPIO_PCS_CLK_SOFT_RESET
);
2665 /* Fix up inter-pair skew failure */
2666 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2667 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2668 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2669 mutex_unlock(&dev_priv
->dpio_lock
);
2672 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2674 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2675 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2676 struct drm_device
*dev
= encoder
->base
.dev
;
2677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2678 struct intel_crtc
*intel_crtc
=
2679 to_intel_crtc(encoder
->base
.crtc
);
2680 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2681 int pipe
= intel_crtc
->pipe
;
2685 mutex_lock(&dev_priv
->dpio_lock
);
2687 /* Deassert soft data lane reset*/
2688 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2689 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2690 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2692 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2693 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2694 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2696 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2697 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2698 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2700 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2701 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2702 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2704 /* Program Tx lane latency optimal setting*/
2705 for (i
= 0; i
< 4; i
++) {
2706 /* Set the latency optimal bit */
2707 data
= (i
== 1) ? 0x0 : 0x6;
2708 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW11(ch
, i
),
2709 data
<< DPIO_FRC_LATENCY_SHFIT
);
2711 /* Set the upar bit */
2712 data
= (i
== 1) ? 0x0 : 0x1;
2713 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2714 data
<< DPIO_UPAR_SHIFT
);
2717 /* Data lane stagger programming */
2718 /* FIXME: Fix up value only after power analysis */
2720 mutex_unlock(&dev_priv
->dpio_lock
);
2722 if (is_edp(intel_dp
)) {
2724 vlv_init_panel_power_sequencer(intel_dp
);
2725 pps_unlock(intel_dp
);
2728 intel_enable_dp(encoder
);
2730 vlv_wait_port_ready(dev_priv
, dport
);
2733 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2735 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2736 struct drm_device
*dev
= encoder
->base
.dev
;
2737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2738 struct intel_crtc
*intel_crtc
=
2739 to_intel_crtc(encoder
->base
.crtc
);
2740 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2741 enum pipe pipe
= intel_crtc
->pipe
;
2744 intel_dp_prepare(encoder
);
2746 mutex_lock(&dev_priv
->dpio_lock
);
2748 /* program left/right clock distribution */
2749 if (pipe
!= PIPE_B
) {
2750 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2751 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2753 val
|= CHV_BUFLEFTENA1_FORCE
;
2755 val
|= CHV_BUFRIGHTENA1_FORCE
;
2756 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2758 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2759 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2761 val
|= CHV_BUFLEFTENA2_FORCE
;
2763 val
|= CHV_BUFRIGHTENA2_FORCE
;
2764 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2767 /* program clock channel usage */
2768 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2769 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2771 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2773 val
|= CHV_PCS_USEDCLKCHANNEL
;
2774 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2776 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2777 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2779 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2781 val
|= CHV_PCS_USEDCLKCHANNEL
;
2782 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2785 * This a a bit weird since generally CL
2786 * matches the pipe, but here we need to
2787 * pick the CL based on the port.
2789 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2791 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2793 val
|= CHV_CMN_USEDCLKCHANNEL
;
2794 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2796 mutex_unlock(&dev_priv
->dpio_lock
);
2800 * Native read with retry for link status and receiver capability reads for
2801 * cases where the sink may still be asleep.
2803 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2804 * supposed to retry 3 times per the spec.
2807 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2808 void *buffer
, size_t size
)
2813 for (i
= 0; i
< 3; i
++) {
2814 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2824 * Fetch AUX CH registers 0x202 - 0x207 which contain
2825 * link status information
2828 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2830 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2833 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2836 /* These are source-specific values. */
2838 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2840 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2841 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2843 if (IS_VALLEYVIEW(dev
))
2844 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2845 else if (IS_GEN7(dev
) && port
== PORT_A
)
2846 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2847 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2848 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2850 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2854 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2856 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2857 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2859 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2860 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2862 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2864 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2871 } else if (IS_VALLEYVIEW(dev
)) {
2872 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2873 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2874 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2876 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2878 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2881 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2883 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2884 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2886 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2891 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2894 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2896 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2903 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2908 static uint32_t intel_vlv_signal_levels(struct intel_dp
*intel_dp
)
2910 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2912 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2913 struct intel_crtc
*intel_crtc
=
2914 to_intel_crtc(dport
->base
.base
.crtc
);
2915 unsigned long demph_reg_value
, preemph_reg_value
,
2916 uniqtranscale_reg_value
;
2917 uint8_t train_set
= intel_dp
->train_set
[0];
2918 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2919 int pipe
= intel_crtc
->pipe
;
2921 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2922 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2923 preemph_reg_value
= 0x0004000;
2924 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2926 demph_reg_value
= 0x2B405555;
2927 uniqtranscale_reg_value
= 0x552AB83A;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2930 demph_reg_value
= 0x2B404040;
2931 uniqtranscale_reg_value
= 0x5548B83A;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2934 demph_reg_value
= 0x2B245555;
2935 uniqtranscale_reg_value
= 0x5560B83A;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2938 demph_reg_value
= 0x2B405555;
2939 uniqtranscale_reg_value
= 0x5598DA3A;
2945 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
2946 preemph_reg_value
= 0x0002000;
2947 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2949 demph_reg_value
= 0x2B404040;
2950 uniqtranscale_reg_value
= 0x5552B83A;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2953 demph_reg_value
= 0x2B404848;
2954 uniqtranscale_reg_value
= 0x5580B83A;
2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2957 demph_reg_value
= 0x2B404040;
2958 uniqtranscale_reg_value
= 0x55ADDA3A;
2964 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
2965 preemph_reg_value
= 0x0000000;
2966 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2968 demph_reg_value
= 0x2B305555;
2969 uniqtranscale_reg_value
= 0x5570B83A;
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2972 demph_reg_value
= 0x2B2B4040;
2973 uniqtranscale_reg_value
= 0x55ADDA3A;
2979 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
2980 preemph_reg_value
= 0x0006000;
2981 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2983 demph_reg_value
= 0x1B405555;
2984 uniqtranscale_reg_value
= 0x55ADDA3A;
2994 mutex_lock(&dev_priv
->dpio_lock
);
2995 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
2996 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
2997 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
2998 uniqtranscale_reg_value
);
2999 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3000 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3001 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3002 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3003 mutex_unlock(&dev_priv
->dpio_lock
);
3008 static uint32_t intel_chv_signal_levels(struct intel_dp
*intel_dp
)
3010 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3012 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3013 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3014 u32 deemph_reg_value
, margin_reg_value
, val
;
3015 uint8_t train_set
= intel_dp
->train_set
[0];
3016 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3017 enum pipe pipe
= intel_crtc
->pipe
;
3020 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3021 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3022 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3024 deemph_reg_value
= 128;
3025 margin_reg_value
= 52;
3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3028 deemph_reg_value
= 128;
3029 margin_reg_value
= 77;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3032 deemph_reg_value
= 128;
3033 margin_reg_value
= 102;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3036 deemph_reg_value
= 128;
3037 margin_reg_value
= 154;
3038 /* FIXME extra to set for 1200 */
3044 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3045 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3047 deemph_reg_value
= 85;
3048 margin_reg_value
= 78;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3051 deemph_reg_value
= 85;
3052 margin_reg_value
= 116;
3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3055 deemph_reg_value
= 85;
3056 margin_reg_value
= 154;
3062 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3063 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3065 deemph_reg_value
= 64;
3066 margin_reg_value
= 104;
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3069 deemph_reg_value
= 64;
3070 margin_reg_value
= 154;
3076 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3077 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3079 deemph_reg_value
= 43;
3080 margin_reg_value
= 154;
3090 mutex_lock(&dev_priv
->dpio_lock
);
3092 /* Clear calc init */
3093 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3094 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3095 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3097 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3098 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3099 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3101 /* Program swing deemph */
3102 for (i
= 0; i
< 4; i
++) {
3103 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3104 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3105 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3106 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3109 /* Program swing margin */
3110 for (i
= 0; i
< 4; i
++) {
3111 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3112 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3113 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3114 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3117 /* Disable unique transition scale */
3118 for (i
= 0; i
< 4; i
++) {
3119 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3120 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3121 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3124 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3125 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3126 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3127 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3130 * The document said it needs to set bit 27 for ch0 and bit 26
3131 * for ch1. Might be a typo in the doc.
3132 * For now, for this unique transition scale selection, set bit
3133 * 27 for ch0 and ch1.
3135 for (i
= 0; i
< 4; i
++) {
3136 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3137 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3138 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3141 for (i
= 0; i
< 4; i
++) {
3142 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3143 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3144 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3145 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3149 /* Start swing calculation */
3150 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3151 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3152 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3154 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3155 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3156 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3159 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3160 val
|= DPIO_LRC_BYPASS
;
3161 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3163 mutex_unlock(&dev_priv
->dpio_lock
);
3169 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3170 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3175 uint8_t voltage_max
;
3176 uint8_t preemph_max
;
3178 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3179 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3180 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3188 voltage_max
= intel_dp_voltage_max(intel_dp
);
3189 if (v
>= voltage_max
)
3190 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3192 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3193 if (p
>= preemph_max
)
3194 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3196 for (lane
= 0; lane
< 4; lane
++)
3197 intel_dp
->train_set
[lane
] = v
| p
;
3201 intel_gen4_signal_levels(uint8_t train_set
)
3203 uint32_t signal_levels
= 0;
3205 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3208 signal_levels
|= DP_VOLTAGE_0_4
;
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3211 signal_levels
|= DP_VOLTAGE_0_6
;
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3214 signal_levels
|= DP_VOLTAGE_0_8
;
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3217 signal_levels
|= DP_VOLTAGE_1_2
;
3220 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3221 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3223 signal_levels
|= DP_PRE_EMPHASIS_0
;
3225 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3226 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3228 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3229 signal_levels
|= DP_PRE_EMPHASIS_6
;
3231 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3232 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3235 return signal_levels
;
3238 /* Gen6's DP voltage swing and pre-emphasis control */
3240 intel_gen6_edp_signal_levels(uint8_t train_set
)
3242 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3243 DP_TRAIN_PRE_EMPHASIS_MASK
);
3244 switch (signal_levels
) {
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3247 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3249 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3252 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3255 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3258 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3260 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3261 "0x%x\n", signal_levels
);
3262 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3266 /* Gen7's DP voltage swing and pre-emphasis control */
3268 intel_gen7_edp_signal_levels(uint8_t train_set
)
3270 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3271 DP_TRAIN_PRE_EMPHASIS_MASK
);
3272 switch (signal_levels
) {
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3274 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3276 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3278 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3281 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3283 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3286 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3288 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3291 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3292 "0x%x\n", signal_levels
);
3293 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3297 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3299 intel_hsw_signal_levels(uint8_t train_set
)
3301 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3302 DP_TRAIN_PRE_EMPHASIS_MASK
);
3303 switch (signal_levels
) {
3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3305 return DDI_BUF_TRANS_SELECT(0);
3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3307 return DDI_BUF_TRANS_SELECT(1);
3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3309 return DDI_BUF_TRANS_SELECT(2);
3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3311 return DDI_BUF_TRANS_SELECT(3);
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3314 return DDI_BUF_TRANS_SELECT(4);
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3316 return DDI_BUF_TRANS_SELECT(5);
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3318 return DDI_BUF_TRANS_SELECT(6);
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3321 return DDI_BUF_TRANS_SELECT(7);
3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3323 return DDI_BUF_TRANS_SELECT(8);
3325 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3326 "0x%x\n", signal_levels
);
3327 return DDI_BUF_TRANS_SELECT(0);
3331 /* Properly updates "DP" with the correct signal levels. */
3333 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3335 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3336 enum port port
= intel_dig_port
->port
;
3337 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3338 uint32_t signal_levels
, mask
;
3339 uint8_t train_set
= intel_dp
->train_set
[0];
3341 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
3342 signal_levels
= intel_hsw_signal_levels(train_set
);
3343 mask
= DDI_BUF_EMP_MASK
;
3344 } else if (IS_CHERRYVIEW(dev
)) {
3345 signal_levels
= intel_chv_signal_levels(intel_dp
);
3347 } else if (IS_VALLEYVIEW(dev
)) {
3348 signal_levels
= intel_vlv_signal_levels(intel_dp
);
3350 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3351 signal_levels
= intel_gen7_edp_signal_levels(train_set
);
3352 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3353 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3354 signal_levels
= intel_gen6_edp_signal_levels(train_set
);
3355 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3357 signal_levels
= intel_gen4_signal_levels(train_set
);
3358 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3361 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3363 *DP
= (*DP
& ~mask
) | signal_levels
;
3367 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3369 uint8_t dp_train_pat
)
3371 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3372 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3374 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3377 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3379 I915_WRITE(intel_dp
->output_reg
, *DP
);
3380 POSTING_READ(intel_dp
->output_reg
);
3382 buf
[0] = dp_train_pat
;
3383 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3384 DP_TRAINING_PATTERN_DISABLE
) {
3385 /* don't write DP_TRAINING_LANEx_SET on disable */
3388 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3389 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3390 len
= intel_dp
->lane_count
+ 1;
3393 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3400 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3401 uint8_t dp_train_pat
)
3403 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3404 intel_dp_set_signal_levels(intel_dp
, DP
);
3405 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3409 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3410 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3412 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3413 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3417 intel_get_adjust_train(intel_dp
, link_status
);
3418 intel_dp_set_signal_levels(intel_dp
, DP
);
3420 I915_WRITE(intel_dp
->output_reg
, *DP
);
3421 POSTING_READ(intel_dp
->output_reg
);
3423 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3424 intel_dp
->train_set
, intel_dp
->lane_count
);
3426 return ret
== intel_dp
->lane_count
;
3429 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3431 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3432 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3434 enum port port
= intel_dig_port
->port
;
3440 val
= I915_READ(DP_TP_CTL(port
));
3441 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3442 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3443 I915_WRITE(DP_TP_CTL(port
), val
);
3446 * On PORT_A we can have only eDP in SST mode. There the only reason
3447 * we need to set idle transmission mode is to work around a HW issue
3448 * where we enable the pipe while not in idle link-training mode.
3449 * In this case there is requirement to wait for a minimum number of
3450 * idle patterns to be sent.
3455 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3457 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3460 /* Enable corresponding port and start training pattern 1 */
3462 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3464 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3465 struct drm_device
*dev
= encoder
->dev
;
3468 int voltage_tries
, loop_tries
;
3469 uint32_t DP
= intel_dp
->DP
;
3470 uint8_t link_config
[2];
3473 intel_ddi_prepare_link_retrain(encoder
);
3475 /* Write the link configuration data */
3476 link_config
[0] = intel_dp
->link_bw
;
3477 link_config
[1] = intel_dp
->lane_count
;
3478 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3479 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3480 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3483 link_config
[1] = DP_SET_ANSI_8B10B
;
3484 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3488 /* clock recovery */
3489 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3490 DP_TRAINING_PATTERN_1
|
3491 DP_LINK_SCRAMBLING_DISABLE
)) {
3492 DRM_ERROR("failed to enable link training\n");
3500 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3502 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3503 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3504 DRM_ERROR("failed to get link status\n");
3508 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3509 DRM_DEBUG_KMS("clock recovery OK\n");
3513 /* Check to see if we've tried the max voltage */
3514 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3515 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3517 if (i
== intel_dp
->lane_count
) {
3519 if (loop_tries
== 5) {
3520 DRM_ERROR("too many full retries, give up\n");
3523 intel_dp_reset_link_train(intel_dp
, &DP
,
3524 DP_TRAINING_PATTERN_1
|
3525 DP_LINK_SCRAMBLING_DISABLE
);
3530 /* Check to see if we've tried the same voltage 5 times */
3531 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3533 if (voltage_tries
== 5) {
3534 DRM_ERROR("too many voltage retries, give up\n");
3539 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3541 /* Update training set as requested by target */
3542 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3543 DRM_ERROR("failed to update link training\n");
3552 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3554 bool channel_eq
= false;
3555 int tries
, cr_tries
;
3556 uint32_t DP
= intel_dp
->DP
;
3557 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3559 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3560 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3561 training_pattern
= DP_TRAINING_PATTERN_3
;
3563 /* channel equalization */
3564 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3566 DP_LINK_SCRAMBLING_DISABLE
)) {
3567 DRM_ERROR("failed to start channel equalization\n");
3575 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3578 DRM_ERROR("failed to train DP, aborting\n");
3582 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3583 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3584 DRM_ERROR("failed to get link status\n");
3588 /* Make sure clock is still ok */
3589 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3590 intel_dp_start_link_train(intel_dp
);
3591 intel_dp_set_link_train(intel_dp
, &DP
,
3593 DP_LINK_SCRAMBLING_DISABLE
);
3598 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3603 /* Try 5 times, then try clock recovery if that fails */
3605 intel_dp_link_down(intel_dp
);
3606 intel_dp_start_link_train(intel_dp
);
3607 intel_dp_set_link_train(intel_dp
, &DP
,
3609 DP_LINK_SCRAMBLING_DISABLE
);
3615 /* Update training set as requested by target */
3616 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3617 DRM_ERROR("failed to update link training\n");
3623 intel_dp_set_idle_link_train(intel_dp
);
3628 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3632 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3634 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3635 DP_TRAINING_PATTERN_DISABLE
);
3639 intel_dp_link_down(struct intel_dp
*intel_dp
)
3641 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3642 enum port port
= intel_dig_port
->port
;
3643 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3645 struct intel_crtc
*intel_crtc
=
3646 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3647 uint32_t DP
= intel_dp
->DP
;
3649 if (WARN_ON(HAS_DDI(dev
)))
3652 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3655 DRM_DEBUG_KMS("\n");
3657 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3658 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3659 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3661 if (IS_CHERRYVIEW(dev
))
3662 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3664 DP
&= ~DP_LINK_TRAIN_MASK
;
3665 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3667 POSTING_READ(intel_dp
->output_reg
);
3669 if (HAS_PCH_IBX(dev
) &&
3670 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3671 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
3673 /* Hardware workaround: leaving our transcoder select
3674 * set to transcoder B while it's off will prevent the
3675 * corresponding HDMI output on transcoder A.
3677 * Combine this with another hardware workaround:
3678 * transcoder select bit can only be cleared while the
3681 DP
&= ~DP_PIPEB_SELECT
;
3682 I915_WRITE(intel_dp
->output_reg
, DP
);
3684 /* Changes to enable or select take place the vblank
3685 * after being written.
3687 if (WARN_ON(crtc
== NULL
)) {
3688 /* We should never try to disable a port without a crtc
3689 * attached. For paranoia keep the code around for a
3691 POSTING_READ(intel_dp
->output_reg
);
3694 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3697 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3698 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3699 POSTING_READ(intel_dp
->output_reg
);
3700 msleep(intel_dp
->panel_power_down_delay
);
3704 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3706 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3707 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3710 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3711 sizeof(intel_dp
->dpcd
)) < 0)
3712 return false; /* aux transfer failed */
3714 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3716 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3717 return false; /* DPCD not present */
3719 /* Check if the panel supports PSR */
3720 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3721 if (is_edp(intel_dp
)) {
3722 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3724 sizeof(intel_dp
->psr_dpcd
));
3725 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3726 dev_priv
->psr
.sink_support
= true;
3727 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3731 /* Training Pattern 3 support */
3732 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3733 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
) {
3734 intel_dp
->use_tps3
= true;
3735 DRM_DEBUG_KMS("Displayport TPS3 supported");
3737 intel_dp
->use_tps3
= false;
3739 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3740 DP_DWN_STRM_PORT_PRESENT
))
3741 return true; /* native DP sink */
3743 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3744 return true; /* no per-port downstream info */
3746 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3747 intel_dp
->downstream_ports
,
3748 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3749 return false; /* downstream port status fetch failed */
3755 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3759 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3762 intel_edp_panel_vdd_on(intel_dp
);
3764 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3765 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3766 buf
[0], buf
[1], buf
[2]);
3768 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3769 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3770 buf
[0], buf
[1], buf
[2]);
3772 intel_edp_panel_vdd_off(intel_dp
, false);
3776 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3780 if (!intel_dp
->can_mst
)
3783 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3786 intel_edp_panel_vdd_on(intel_dp
);
3787 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3788 if (buf
[0] & DP_MST_CAP
) {
3789 DRM_DEBUG_KMS("Sink is MST capable\n");
3790 intel_dp
->is_mst
= true;
3792 DRM_DEBUG_KMS("Sink is not MST capable\n");
3793 intel_dp
->is_mst
= false;
3796 intel_edp_panel_vdd_off(intel_dp
, false);
3798 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3799 return intel_dp
->is_mst
;
3802 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3804 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3805 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3806 struct intel_crtc
*intel_crtc
=
3807 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3810 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, buf
) < 0)
3813 if (!(buf
[0] & DP_TEST_CRC_SUPPORTED
))
3816 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3817 DP_TEST_SINK_START
) < 0)
3820 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3821 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3822 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3824 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
3827 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
, 0);
3832 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3834 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3835 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3836 sink_irq_vector
, 1) == 1;
3840 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
3844 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3846 sink_irq_vector
, 14);
3854 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
3856 /* NAK by default */
3857 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_RESPONSE
, DP_TEST_NAK
);
3861 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
3865 if (intel_dp
->is_mst
) {
3870 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3874 /* check link status - esi[10] = 0x200c */
3875 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
3876 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3877 intel_dp_start_link_train(intel_dp
);
3878 intel_dp_complete_link_train(intel_dp
);
3879 intel_dp_stop_link_train(intel_dp
);
3882 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3883 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
3886 for (retry
= 0; retry
< 3; retry
++) {
3888 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
3889 DP_SINK_COUNT_ESI
+1,
3896 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
3898 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi
[0], esi
[1], esi
[2]);
3906 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3907 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3908 intel_dp
->is_mst
= false;
3909 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3910 /* send a hotplug event */
3911 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
3918 * According to DP spec
3921 * 2. Configure link according to Receiver Capabilities
3922 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3923 * 4. Check link status on receipt of hot-plug interrupt
3926 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
3928 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3929 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
3931 u8 link_status
[DP_LINK_STATUS_SIZE
];
3933 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
3935 if (!intel_encoder
->connectors_active
)
3938 if (WARN_ON(!intel_encoder
->base
.crtc
))
3941 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
3944 /* Try to read receiver status if the link appears to be up */
3945 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3949 /* Now read the DPCD to see if it's actually running */
3950 if (!intel_dp_get_dpcd(intel_dp
)) {
3954 /* Try to read the source of the interrupt */
3955 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3956 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
3957 /* Clear interrupt source */
3958 drm_dp_dpcd_writeb(&intel_dp
->aux
,
3959 DP_DEVICE_SERVICE_IRQ_VECTOR
,
3962 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
3963 intel_dp_handle_test_request(intel_dp
);
3964 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
3965 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3968 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3969 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3970 intel_encoder
->base
.name
);
3971 intel_dp_start_link_train(intel_dp
);
3972 intel_dp_complete_link_train(intel_dp
);
3973 intel_dp_stop_link_train(intel_dp
);
3977 /* XXX this is probably wrong for multiple downstream ports */
3978 static enum drm_connector_status
3979 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
3981 uint8_t *dpcd
= intel_dp
->dpcd
;
3984 if (!intel_dp_get_dpcd(intel_dp
))
3985 return connector_status_disconnected
;
3987 /* if there's no downstream port, we're done */
3988 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
3989 return connector_status_connected
;
3991 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3992 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
3993 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
3996 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
3998 return connector_status_unknown
;
4000 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4001 : connector_status_disconnected
;
4004 /* If no HPD, poke DDC gently */
4005 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4006 return connector_status_connected
;
4008 /* Well we tried, say unknown for unreliable port types */
4009 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4010 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4011 if (type
== DP_DS_PORT_TYPE_VGA
||
4012 type
== DP_DS_PORT_TYPE_NON_EDID
)
4013 return connector_status_unknown
;
4015 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4016 DP_DWN_STRM_PORT_TYPE_MASK
;
4017 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4018 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4019 return connector_status_unknown
;
4022 /* Anything else is out of spec, warn and ignore */
4023 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4024 return connector_status_disconnected
;
4027 static enum drm_connector_status
4028 edp_detect(struct intel_dp
*intel_dp
)
4030 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4031 enum drm_connector_status status
;
4033 status
= intel_panel_detect(dev
);
4034 if (status
== connector_status_unknown
)
4035 status
= connector_status_connected
;
4040 static enum drm_connector_status
4041 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4043 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4045 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4047 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4048 return connector_status_disconnected
;
4050 return intel_dp_detect_dpcd(intel_dp
);
4053 static int g4x_digital_port_connected(struct drm_device
*dev
,
4054 struct intel_digital_port
*intel_dig_port
)
4056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4059 if (IS_VALLEYVIEW(dev
)) {
4060 switch (intel_dig_port
->port
) {
4062 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4065 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4068 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4074 switch (intel_dig_port
->port
) {
4076 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4079 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4082 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4089 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4094 static enum drm_connector_status
4095 g4x_dp_detect(struct intel_dp
*intel_dp
)
4097 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4098 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4101 /* Can't disconnect eDP, but you can close the lid... */
4102 if (is_edp(intel_dp
)) {
4103 enum drm_connector_status status
;
4105 status
= intel_panel_detect(dev
);
4106 if (status
== connector_status_unknown
)
4107 status
= connector_status_connected
;
4111 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4113 return connector_status_unknown
;
4115 return connector_status_disconnected
;
4117 return intel_dp_detect_dpcd(intel_dp
);
4120 static struct edid
*
4121 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4123 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4125 /* use cached edid if we have one */
4126 if (intel_connector
->edid
) {
4128 if (IS_ERR(intel_connector
->edid
))
4131 return drm_edid_duplicate(intel_connector
->edid
);
4133 return drm_get_edid(&intel_connector
->base
,
4134 &intel_dp
->aux
.ddc
);
4138 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4140 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4143 edid
= intel_dp_get_edid(intel_dp
);
4144 intel_connector
->detect_edid
= edid
;
4146 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4147 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4149 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4153 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4155 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4157 kfree(intel_connector
->detect_edid
);
4158 intel_connector
->detect_edid
= NULL
;
4160 intel_dp
->has_audio
= false;
4163 static enum intel_display_power_domain
4164 intel_dp_power_get(struct intel_dp
*dp
)
4166 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4167 enum intel_display_power_domain power_domain
;
4169 power_domain
= intel_display_port_power_domain(encoder
);
4170 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4172 return power_domain
;
4176 intel_dp_power_put(struct intel_dp
*dp
,
4177 enum intel_display_power_domain power_domain
)
4179 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4180 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4183 static enum drm_connector_status
4184 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4186 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4187 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4188 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4189 struct drm_device
*dev
= connector
->dev
;
4190 enum drm_connector_status status
;
4191 enum intel_display_power_domain power_domain
;
4194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4195 connector
->base
.id
, connector
->name
);
4196 intel_dp_unset_edid(intel_dp
);
4198 if (intel_dp
->is_mst
) {
4199 /* MST devices are disconnected from a monitor POV */
4200 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4201 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4202 return connector_status_disconnected
;
4205 power_domain
= intel_dp_power_get(intel_dp
);
4207 /* Can't disconnect eDP, but you can close the lid... */
4208 if (is_edp(intel_dp
))
4209 status
= edp_detect(intel_dp
);
4210 else if (HAS_PCH_SPLIT(dev
))
4211 status
= ironlake_dp_detect(intel_dp
);
4213 status
= g4x_dp_detect(intel_dp
);
4214 if (status
!= connector_status_connected
)
4217 intel_dp_probe_oui(intel_dp
);
4219 ret
= intel_dp_probe_mst(intel_dp
);
4221 /* if we are in MST mode then this connector
4222 won't appear connected or have anything with EDID on it */
4223 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4224 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4225 status
= connector_status_disconnected
;
4229 intel_dp_set_edid(intel_dp
);
4231 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4232 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4233 status
= connector_status_connected
;
4236 intel_dp_power_put(intel_dp
, power_domain
);
4241 intel_dp_force(struct drm_connector
*connector
)
4243 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4244 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4245 enum intel_display_power_domain power_domain
;
4247 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4248 connector
->base
.id
, connector
->name
);
4249 intel_dp_unset_edid(intel_dp
);
4251 if (connector
->status
!= connector_status_connected
)
4254 power_domain
= intel_dp_power_get(intel_dp
);
4256 intel_dp_set_edid(intel_dp
);
4258 intel_dp_power_put(intel_dp
, power_domain
);
4260 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4261 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4264 static int intel_dp_get_modes(struct drm_connector
*connector
)
4266 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4269 edid
= intel_connector
->detect_edid
;
4271 int ret
= intel_connector_update_modes(connector
, edid
);
4276 /* if eDP has no EDID, fall back to fixed mode */
4277 if (is_edp(intel_attached_dp(connector
)) &&
4278 intel_connector
->panel
.fixed_mode
) {
4279 struct drm_display_mode
*mode
;
4281 mode
= drm_mode_duplicate(connector
->dev
,
4282 intel_connector
->panel
.fixed_mode
);
4284 drm_mode_probed_add(connector
, mode
);
4293 intel_dp_detect_audio(struct drm_connector
*connector
)
4295 bool has_audio
= false;
4298 edid
= to_intel_connector(connector
)->detect_edid
;
4300 has_audio
= drm_detect_monitor_audio(edid
);
4306 intel_dp_set_property(struct drm_connector
*connector
,
4307 struct drm_property
*property
,
4310 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4311 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4312 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4313 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4316 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4320 if (property
== dev_priv
->force_audio_property
) {
4324 if (i
== intel_dp
->force_audio
)
4327 intel_dp
->force_audio
= i
;
4329 if (i
== HDMI_AUDIO_AUTO
)
4330 has_audio
= intel_dp_detect_audio(connector
);
4332 has_audio
= (i
== HDMI_AUDIO_ON
);
4334 if (has_audio
== intel_dp
->has_audio
)
4337 intel_dp
->has_audio
= has_audio
;
4341 if (property
== dev_priv
->broadcast_rgb_property
) {
4342 bool old_auto
= intel_dp
->color_range_auto
;
4343 uint32_t old_range
= intel_dp
->color_range
;
4346 case INTEL_BROADCAST_RGB_AUTO
:
4347 intel_dp
->color_range_auto
= true;
4349 case INTEL_BROADCAST_RGB_FULL
:
4350 intel_dp
->color_range_auto
= false;
4351 intel_dp
->color_range
= 0;
4353 case INTEL_BROADCAST_RGB_LIMITED
:
4354 intel_dp
->color_range_auto
= false;
4355 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4361 if (old_auto
== intel_dp
->color_range_auto
&&
4362 old_range
== intel_dp
->color_range
)
4368 if (is_edp(intel_dp
) &&
4369 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4370 if (val
== DRM_MODE_SCALE_NONE
) {
4371 DRM_DEBUG_KMS("no scaling not supported\n");
4375 if (intel_connector
->panel
.fitting_mode
== val
) {
4376 /* the eDP scaling property is not changed */
4379 intel_connector
->panel
.fitting_mode
= val
;
4387 if (intel_encoder
->base
.crtc
)
4388 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4394 intel_dp_connector_destroy(struct drm_connector
*connector
)
4396 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4398 intel_dp_unset_edid(intel_attached_dp(connector
));
4400 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4401 kfree(intel_connector
->edid
);
4403 /* Can't call is_edp() since the encoder may have been destroyed
4405 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4406 intel_panel_fini(&intel_connector
->panel
);
4408 drm_connector_cleanup(connector
);
4412 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4414 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4415 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4417 drm_dp_aux_unregister(&intel_dp
->aux
);
4418 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4419 drm_encoder_cleanup(encoder
);
4420 if (is_edp(intel_dp
)) {
4421 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4423 * vdd might still be enabled do to the delayed vdd off.
4424 * Make sure vdd is actually turned off here.
4427 edp_panel_vdd_off_sync(intel_dp
);
4428 pps_unlock(intel_dp
);
4430 if (intel_dp
->edp_notifier
.notifier_call
) {
4431 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4432 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4435 kfree(intel_dig_port
);
4438 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4440 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4442 if (!is_edp(intel_dp
))
4446 * vdd might still be enabled do to the delayed vdd off.
4447 * Make sure vdd is actually turned off here.
4450 edp_panel_vdd_off_sync(intel_dp
);
4451 pps_unlock(intel_dp
);
4454 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4456 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder
));
4459 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4460 .dpms
= intel_connector_dpms
,
4461 .detect
= intel_dp_detect
,
4462 .force
= intel_dp_force
,
4463 .fill_modes
= drm_helper_probe_single_connector_modes
,
4464 .set_property
= intel_dp_set_property
,
4465 .destroy
= intel_dp_connector_destroy
,
4468 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4469 .get_modes
= intel_dp_get_modes
,
4470 .mode_valid
= intel_dp_mode_valid
,
4471 .best_encoder
= intel_best_encoder
,
4474 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4475 .reset
= intel_dp_encoder_reset
,
4476 .destroy
= intel_dp_encoder_destroy
,
4480 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4486 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4488 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4489 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4490 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4492 enum intel_display_power_domain power_domain
;
4495 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4496 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4498 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4499 port_name(intel_dig_port
->port
),
4500 long_hpd
? "long" : "short");
4502 power_domain
= intel_display_port_power_domain(intel_encoder
);
4503 intel_display_power_get(dev_priv
, power_domain
);
4507 if (HAS_PCH_SPLIT(dev
)) {
4508 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4511 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4515 if (!intel_dp_get_dpcd(intel_dp
)) {
4519 intel_dp_probe_oui(intel_dp
);
4521 if (!intel_dp_probe_mst(intel_dp
))
4525 if (intel_dp
->is_mst
) {
4526 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4530 if (!intel_dp
->is_mst
) {
4532 * we'll check the link status via the normal hot plug path later -
4533 * but for short hpds we should check it now
4535 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4536 intel_dp_check_link_status(intel_dp
);
4537 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4543 /* if we were in MST mode, and device is not there get out of MST mode */
4544 if (intel_dp
->is_mst
) {
4545 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4546 intel_dp
->is_mst
= false;
4547 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4550 intel_display_power_put(dev_priv
, power_domain
);
4555 /* Return which DP Port should be selected for Transcoder DP control */
4557 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4559 struct drm_device
*dev
= crtc
->dev
;
4560 struct intel_encoder
*intel_encoder
;
4561 struct intel_dp
*intel_dp
;
4563 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4564 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4566 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4567 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4568 return intel_dp
->output_reg
;
4574 /* check the VBT to see whether the eDP is on DP-D port */
4575 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4578 union child_device_config
*p_child
;
4580 static const short port_mapping
[] = {
4581 [PORT_B
] = PORT_IDPB
,
4582 [PORT_C
] = PORT_IDPC
,
4583 [PORT_D
] = PORT_IDPD
,
4589 if (!dev_priv
->vbt
.child_dev_num
)
4592 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4593 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4595 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4596 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4597 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4604 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4606 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4608 intel_attach_force_audio_property(connector
);
4609 intel_attach_broadcast_rgb_property(connector
);
4610 intel_dp
->color_range_auto
= true;
4612 if (is_edp(intel_dp
)) {
4613 drm_mode_create_scaling_mode_property(connector
->dev
);
4614 drm_object_attach_property(
4616 connector
->dev
->mode_config
.scaling_mode_property
,
4617 DRM_MODE_SCALE_ASPECT
);
4618 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4622 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4624 intel_dp
->last_power_cycle
= jiffies
;
4625 intel_dp
->last_power_on
= jiffies
;
4626 intel_dp
->last_backlight_off
= jiffies
;
4630 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4631 struct intel_dp
*intel_dp
,
4632 struct edp_power_seq
*out
)
4634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4635 struct edp_power_seq cur
, vbt
, spec
, final
;
4636 u32 pp_on
, pp_off
, pp_div
, pp
;
4637 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4639 lockdep_assert_held(&dev_priv
->pps_mutex
);
4641 if (HAS_PCH_SPLIT(dev
)) {
4642 pp_ctrl_reg
= PCH_PP_CONTROL
;
4643 pp_on_reg
= PCH_PP_ON_DELAYS
;
4644 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4645 pp_div_reg
= PCH_PP_DIVISOR
;
4647 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4649 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4650 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4651 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4652 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4655 /* Workaround: Need to write PP_CONTROL with the unlock key as
4656 * the very first thing. */
4657 pp
= ironlake_get_pp_control(intel_dp
);
4658 I915_WRITE(pp_ctrl_reg
, pp
);
4660 pp_on
= I915_READ(pp_on_reg
);
4661 pp_off
= I915_READ(pp_off_reg
);
4662 pp_div
= I915_READ(pp_div_reg
);
4664 /* Pull timing values out of registers */
4665 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4666 PANEL_POWER_UP_DELAY_SHIFT
;
4668 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4669 PANEL_LIGHT_ON_DELAY_SHIFT
;
4671 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4672 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4674 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
4675 PANEL_POWER_DOWN_DELAY_SHIFT
;
4677 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
4678 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
4680 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4681 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
4683 vbt
= dev_priv
->vbt
.edp_pps
;
4685 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4686 * our hw here, which are all in 100usec. */
4687 spec
.t1_t3
= 210 * 10;
4688 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
4689 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
4690 spec
.t10
= 500 * 10;
4691 /* This one is special and actually in units of 100ms, but zero
4692 * based in the hw (so we need to add 100 ms). But the sw vbt
4693 * table multiplies it with 1000 to make it in units of 100usec,
4695 spec
.t11_t12
= (510 + 100) * 10;
4697 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4698 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
4700 /* Use the max of the register settings and vbt. If both are
4701 * unset, fall back to the spec limits. */
4702 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4704 max(cur.field, vbt.field))
4705 assign_final(t1_t3
);
4709 assign_final(t11_t12
);
4712 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4713 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
4714 intel_dp
->backlight_on_delay
= get_delay(t8
);
4715 intel_dp
->backlight_off_delay
= get_delay(t9
);
4716 intel_dp
->panel_power_down_delay
= get_delay(t10
);
4717 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
4720 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4721 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
4722 intel_dp
->panel_power_cycle_delay
);
4724 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4725 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
4732 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
4733 struct intel_dp
*intel_dp
,
4734 struct edp_power_seq
*seq
)
4736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4737 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
4738 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
4739 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
4740 enum port port
= dp_to_dig_port(intel_dp
)->port
;
4742 lockdep_assert_held(&dev_priv
->pps_mutex
);
4744 if (HAS_PCH_SPLIT(dev
)) {
4745 pp_on_reg
= PCH_PP_ON_DELAYS
;
4746 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4747 pp_div_reg
= PCH_PP_DIVISOR
;
4749 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4751 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4752 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4753 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4757 * And finally store the new values in the power sequencer. The
4758 * backlight delays are set to 1 because we do manual waits on them. For
4759 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4760 * we'll end up waiting for the backlight off delay twice: once when we
4761 * do the manual sleep, and once when we disable the panel and wait for
4762 * the PP_STATUS bit to become zero.
4764 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
4765 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
4766 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
4767 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
4768 /* Compute the divisor for the pp clock, simply match the Bspec
4770 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
4771 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
4772 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
4774 /* Haswell doesn't have any port selection bits for the panel
4775 * power sequencer any more. */
4776 if (IS_VALLEYVIEW(dev
)) {
4777 port_sel
= PANEL_PORT_SELECT_VLV(port
);
4778 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
4780 port_sel
= PANEL_PORT_SELECT_DPA
;
4782 port_sel
= PANEL_PORT_SELECT_DPD
;
4787 I915_WRITE(pp_on_reg
, pp_on
);
4788 I915_WRITE(pp_off_reg
, pp_off
);
4789 I915_WRITE(pp_div_reg
, pp_div
);
4791 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4792 I915_READ(pp_on_reg
),
4793 I915_READ(pp_off_reg
),
4794 I915_READ(pp_div_reg
));
4797 void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
4799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4800 struct intel_encoder
*encoder
;
4801 struct intel_dp
*intel_dp
= NULL
;
4802 struct intel_crtc_config
*config
= NULL
;
4803 struct intel_crtc
*intel_crtc
= NULL
;
4804 struct intel_connector
*intel_connector
= dev_priv
->drrs
.connector
;
4806 enum edp_drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
4808 if (refresh_rate
<= 0) {
4809 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4813 if (intel_connector
== NULL
) {
4814 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4819 * FIXME: This needs proper synchronization with psr state. But really
4820 * hard to tell without seeing the user of this function of this code.
4821 * Check locking and ordering once that lands.
4823 if (INTEL_INFO(dev
)->gen
< 8 && intel_edp_is_psr_enabled(dev
)) {
4824 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4828 encoder
= intel_attached_encoder(&intel_connector
->base
);
4829 intel_dp
= enc_to_intel_dp(&encoder
->base
);
4830 intel_crtc
= encoder
->new_crtc
;
4833 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4837 config
= &intel_crtc
->config
;
4839 if (intel_dp
->drrs_state
.type
< SEAMLESS_DRRS_SUPPORT
) {
4840 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4844 if (intel_connector
->panel
.downclock_mode
->vrefresh
== refresh_rate
)
4845 index
= DRRS_LOW_RR
;
4847 if (index
== intel_dp
->drrs_state
.refresh_rate_type
) {
4849 "DRRS requested for previously set RR...ignoring\n");
4853 if (!intel_crtc
->active
) {
4854 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4858 if (INTEL_INFO(dev
)->gen
> 6 && INTEL_INFO(dev
)->gen
< 8) {
4859 reg
= PIPECONF(intel_crtc
->config
.cpu_transcoder
);
4860 val
= I915_READ(reg
);
4861 if (index
> DRRS_HIGH_RR
) {
4862 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
4863 intel_dp_set_m_n(intel_crtc
);
4865 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
4867 I915_WRITE(reg
, val
);
4871 * mutex taken to ensure that there is no race between differnt
4872 * drrs calls trying to update refresh rate. This scenario may occur
4873 * in future when idleness detection based DRRS in kernel and
4874 * possible calls from user space to set differnt RR are made.
4877 mutex_lock(&intel_dp
->drrs_state
.mutex
);
4879 intel_dp
->drrs_state
.refresh_rate_type
= index
;
4881 mutex_unlock(&intel_dp
->drrs_state
.mutex
);
4883 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
4886 static struct drm_display_mode
*
4887 intel_dp_drrs_init(struct intel_digital_port
*intel_dig_port
,
4888 struct intel_connector
*intel_connector
,
4889 struct drm_display_mode
*fixed_mode
)
4891 struct drm_connector
*connector
= &intel_connector
->base
;
4892 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4893 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4895 struct drm_display_mode
*downclock_mode
= NULL
;
4897 if (INTEL_INFO(dev
)->gen
<= 6) {
4898 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4902 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
4903 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4907 downclock_mode
= intel_find_panel_downclock
4908 (dev
, fixed_mode
, connector
);
4910 if (!downclock_mode
) {
4911 DRM_DEBUG_KMS("DRRS not supported\n");
4915 dev_priv
->drrs
.connector
= intel_connector
;
4917 mutex_init(&intel_dp
->drrs_state
.mutex
);
4919 intel_dp
->drrs_state
.type
= dev_priv
->vbt
.drrs_type
;
4921 intel_dp
->drrs_state
.refresh_rate_type
= DRRS_HIGH_RR
;
4922 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4923 return downclock_mode
;
4926 void intel_edp_panel_vdd_sanitize(struct intel_encoder
*intel_encoder
)
4928 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4930 struct intel_dp
*intel_dp
;
4931 enum intel_display_power_domain power_domain
;
4933 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4936 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4940 if (!edp_have_panel_vdd(intel_dp
))
4943 * The VDD bit needs a power domain reference, so if the bit is
4944 * already enabled when we boot or resume, grab this reference and
4945 * schedule a vdd off, so we don't hold on to the reference
4948 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4949 power_domain
= intel_display_port_power_domain(intel_encoder
);
4950 intel_display_power_get(dev_priv
, power_domain
);
4952 edp_panel_vdd_schedule_off(intel_dp
);
4954 pps_unlock(intel_dp
);
4957 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
4958 struct intel_connector
*intel_connector
,
4959 struct edp_power_seq
*power_seq
)
4961 struct drm_connector
*connector
= &intel_connector
->base
;
4962 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4963 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4964 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4966 struct drm_display_mode
*fixed_mode
= NULL
;
4967 struct drm_display_mode
*downclock_mode
= NULL
;
4969 struct drm_display_mode
*scan
;
4972 intel_dp
->drrs_state
.type
= DRRS_NOT_SUPPORTED
;
4974 if (!is_edp(intel_dp
))
4977 intel_edp_panel_vdd_sanitize(intel_encoder
);
4979 /* Cache DPCD and EDID for edp. */
4980 intel_edp_panel_vdd_on(intel_dp
);
4981 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
4982 intel_edp_panel_vdd_off(intel_dp
, false);
4985 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
4986 dev_priv
->no_aux_handshake
=
4987 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
4988 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
4990 /* if this fails, presume the device is a ghost */
4991 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4995 /* We now know it's not a ghost, init power sequence regs. */
4997 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
, power_seq
);
4998 pps_unlock(intel_dp
);
5000 mutex_lock(&dev
->mode_config
.mutex
);
5001 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5003 if (drm_add_edid_modes(connector
, edid
)) {
5004 drm_mode_connector_update_edid_property(connector
,
5006 drm_edid_to_eld(connector
, edid
);
5009 edid
= ERR_PTR(-EINVAL
);
5012 edid
= ERR_PTR(-ENOENT
);
5014 intel_connector
->edid
= edid
;
5016 /* prefer fixed mode from EDID if available */
5017 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5018 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5019 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5020 downclock_mode
= intel_dp_drrs_init(
5022 intel_connector
, fixed_mode
);
5027 /* fallback to VBT if available for eDP */
5028 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5029 fixed_mode
= drm_mode_duplicate(dev
,
5030 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5032 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5034 mutex_unlock(&dev
->mode_config
.mutex
);
5036 if (IS_VALLEYVIEW(dev
)) {
5037 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5038 register_reboot_notifier(&intel_dp
->edp_notifier
);
5041 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5042 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5043 intel_panel_setup_backlight(connector
);
5049 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5050 struct intel_connector
*intel_connector
)
5052 struct drm_connector
*connector
= &intel_connector
->base
;
5053 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5054 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5055 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5057 enum port port
= intel_dig_port
->port
;
5058 struct edp_power_seq power_seq
= { 0 };
5061 intel_dp
->pps_pipe
= INVALID_PIPE
;
5063 /* intel_dp vfuncs */
5064 if (IS_VALLEYVIEW(dev
))
5065 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5066 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5067 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5068 else if (HAS_PCH_SPLIT(dev
))
5069 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5071 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5073 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5075 /* Preserve the current hw state. */
5076 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5077 intel_dp
->attached_connector
= intel_connector
;
5079 if (intel_dp_is_edp(dev
, port
))
5080 type
= DRM_MODE_CONNECTOR_eDP
;
5082 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5085 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5086 * for DP the encoder type can be set by the caller to
5087 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5089 if (type
== DRM_MODE_CONNECTOR_eDP
)
5090 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5092 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5093 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5096 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5097 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5099 connector
->interlace_allowed
= true;
5100 connector
->doublescan_allowed
= 0;
5102 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5103 edp_panel_vdd_work
);
5105 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5106 drm_connector_register(connector
);
5109 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5111 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5112 intel_connector
->unregister
= intel_dp_connector_unregister
;
5114 /* Set up the hotplug pin. */
5117 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5120 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5123 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5126 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5132 if (is_edp(intel_dp
)) {
5134 if (IS_VALLEYVIEW(dev
)) {
5135 vlv_initial_power_sequencer_setup(intel_dp
);
5137 intel_dp_init_panel_power_timestamps(intel_dp
);
5138 intel_dp_init_panel_power_sequencer(dev
, intel_dp
,
5141 pps_unlock(intel_dp
);
5144 intel_dp_aux_init(intel_dp
, intel_connector
);
5146 /* init MST on ports that can support it */
5147 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5148 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5149 intel_dp_mst_encoder_init(intel_dig_port
,
5150 intel_connector
->base
.base
.id
);
5154 if (!intel_edp_init_connector(intel_dp
, intel_connector
, &power_seq
)) {
5155 drm_dp_aux_unregister(&intel_dp
->aux
);
5156 if (is_edp(intel_dp
)) {
5157 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5159 * vdd might still be enabled do to the delayed vdd off.
5160 * Make sure vdd is actually turned off here.
5163 edp_panel_vdd_off_sync(intel_dp
);
5164 pps_unlock(intel_dp
);
5166 drm_connector_unregister(connector
);
5167 drm_connector_cleanup(connector
);
5171 intel_dp_add_properties(intel_dp
, connector
);
5173 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5174 * 0xd. Failure to do so will result in spurious interrupts being
5175 * generated on the port when a cable is not attached.
5177 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5178 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5179 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5186 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5189 struct intel_digital_port
*intel_dig_port
;
5190 struct intel_encoder
*intel_encoder
;
5191 struct drm_encoder
*encoder
;
5192 struct intel_connector
*intel_connector
;
5194 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5195 if (!intel_dig_port
)
5198 intel_connector
= kzalloc(sizeof(*intel_connector
), GFP_KERNEL
);
5199 if (!intel_connector
) {
5200 kfree(intel_dig_port
);
5204 intel_encoder
= &intel_dig_port
->base
;
5205 encoder
= &intel_encoder
->base
;
5207 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5208 DRM_MODE_ENCODER_TMDS
);
5210 intel_encoder
->compute_config
= intel_dp_compute_config
;
5211 intel_encoder
->disable
= intel_disable_dp
;
5212 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5213 intel_encoder
->get_config
= intel_dp_get_config
;
5214 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5215 if (IS_CHERRYVIEW(dev
)) {
5216 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5217 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5218 intel_encoder
->enable
= vlv_enable_dp
;
5219 intel_encoder
->post_disable
= chv_post_disable_dp
;
5220 } else if (IS_VALLEYVIEW(dev
)) {
5221 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5222 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5223 intel_encoder
->enable
= vlv_enable_dp
;
5224 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5226 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5227 intel_encoder
->enable
= g4x_enable_dp
;
5228 if (INTEL_INFO(dev
)->gen
>= 5)
5229 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5232 intel_dig_port
->port
= port
;
5233 intel_dig_port
->dp
.output_reg
= output_reg
;
5235 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5236 if (IS_CHERRYVIEW(dev
)) {
5238 intel_encoder
->crtc_mask
= 1 << 2;
5240 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5242 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5244 intel_encoder
->cloneable
= 0;
5245 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5247 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5248 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5250 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5251 drm_encoder_cleanup(encoder
);
5252 kfree(intel_dig_port
);
5253 kfree(intel_connector
);
5257 void intel_dp_mst_suspend(struct drm_device
*dev
)
5259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5263 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5264 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5265 if (!intel_dig_port
)
5268 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5269 if (!intel_dig_port
->dp
.can_mst
)
5271 if (intel_dig_port
->dp
.is_mst
)
5272 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5277 void intel_dp_mst_resume(struct drm_device
*dev
)
5279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5282 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5283 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5284 if (!intel_dig_port
)
5286 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5289 if (!intel_dig_port
->dp
.can_mst
)
5292 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5294 intel_dp_check_mst_status(&intel_dig_port
->dp
);