2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
26 struct intel_shared_dpll
*
27 intel_get_shared_dpll_by_id(struct drm_i915_private
*dev_priv
,
28 enum intel_dpll_id id
)
30 return &dev_priv
->shared_dplls
[id
];
34 intel_get_shared_dpll_id(struct drm_i915_private
*dev_priv
,
35 struct intel_shared_dpll
*pll
)
37 if (WARN_ON(pll
< dev_priv
->shared_dplls
||
38 pll
> &dev_priv
->shared_dplls
[dev_priv
->num_shared_dpll
]))
41 return (enum intel_dpll_id
) (pll
- dev_priv
->shared_dplls
);
45 intel_shared_dpll_config_get(struct intel_shared_dpll_config
*config
,
46 struct intel_shared_dpll
*pll
,
47 struct intel_crtc
*crtc
)
49 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
50 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
52 config
[id
].crtc_mask
|= 1 << crtc
->pipe
;
56 intel_shared_dpll_config_put(struct intel_shared_dpll_config
*config
,
57 struct intel_shared_dpll
*pll
,
58 struct intel_crtc
*crtc
)
60 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
61 enum intel_dpll_id id
= intel_get_shared_dpll_id(dev_priv
, pll
);
63 config
[id
].crtc_mask
&= ~(1 << crtc
->pipe
);
67 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
68 struct intel_shared_dpll
*pll
,
72 struct intel_dpll_hw_state hw_state
;
74 if (WARN(!pll
, "asserting DPLL %s with no DPLL\n", onoff(state
)))
77 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
78 I915_STATE_WARN(cur_state
!= state
,
79 "%s assertion failure (expected %s, current %s)\n",
80 pll
->name
, onoff(state
), onoff(cur_state
));
83 void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
85 struct drm_device
*dev
= crtc
->base
.dev
;
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
87 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
89 if (WARN_ON(pll
== NULL
))
92 WARN_ON(!pll
->config
.crtc_mask
);
93 if (pll
->active
== 0) {
94 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
96 assert_shared_dpll_disabled(dev_priv
, pll
);
98 pll
->mode_set(dev_priv
, pll
);
103 * intel_enable_shared_dpll - enable PCH PLL
104 * @dev_priv: i915 private structure
105 * @pipe: pipe PLL to enable
107 * The PCH PLL needs to be enabled before the PCH transcoder, since it
108 * drives the transcoder clock.
110 void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
112 struct drm_device
*dev
= crtc
->base
.dev
;
113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
114 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
116 if (WARN_ON(pll
== NULL
))
119 if (WARN_ON(pll
->config
.crtc_mask
== 0))
122 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
123 pll
->name
, pll
->active
, pll
->on
,
128 assert_shared_dpll_enabled(dev_priv
, pll
);
133 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
135 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
136 pll
->enable(dev_priv
, pll
);
140 void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
142 struct drm_device
*dev
= crtc
->base
.dev
;
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 struct intel_shared_dpll
*pll
= crtc
->config
->shared_dpll
;
146 /* PCH only available on ILK+ */
147 if (INTEL_INFO(dev
)->gen
< 5)
153 if (WARN_ON(!(pll
->config
.crtc_mask
& (1 << drm_crtc_index(&crtc
->base
)))))
156 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
157 pll
->name
, pll
->active
, pll
->on
,
160 if (WARN_ON(pll
->active
== 0)) {
161 assert_shared_dpll_disabled(dev_priv
, pll
);
165 assert_shared_dpll_enabled(dev_priv
, pll
);
170 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
171 pll
->disable(dev_priv
, pll
);
174 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
177 static enum intel_dpll_id
178 ibx_get_fixed_dpll(struct intel_crtc
*crtc
,
179 struct intel_crtc_state
*crtc_state
)
181 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
182 struct intel_shared_dpll
*pll
;
183 enum intel_dpll_id i
;
185 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
186 i
= (enum intel_dpll_id
) crtc
->pipe
;
187 pll
= &dev_priv
->shared_dplls
[i
];
189 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
190 crtc
->base
.base
.id
, pll
->name
);
195 static enum intel_dpll_id
196 bxt_get_fixed_dpll(struct intel_crtc
*crtc
,
197 struct intel_crtc_state
*crtc_state
)
199 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
200 struct intel_encoder
*encoder
;
201 struct intel_digital_port
*intel_dig_port
;
202 struct intel_shared_dpll
*pll
;
203 enum intel_dpll_id i
;
205 /* PLL is attached to port in bxt */
206 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
207 if (WARN_ON(!encoder
))
208 return DPLL_ID_PRIVATE
;
210 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
211 /* 1:1 mapping between ports and PLLs */
212 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
213 pll
= &dev_priv
->shared_dplls
[i
];
214 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
215 crtc
->base
.base
.id
, pll
->name
);
220 static enum intel_dpll_id
221 intel_find_shared_dpll(struct intel_crtc
*crtc
,
222 struct intel_crtc_state
*crtc_state
)
224 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
225 struct intel_shared_dpll
*pll
;
226 struct intel_shared_dpll_config
*shared_dpll
;
227 enum intel_dpll_id i
;
228 int max
= dev_priv
->num_shared_dpll
;
230 if (INTEL_INFO(dev_priv
)->gen
< 9 && HAS_DDI(dev_priv
))
231 /* Do not consider SPLL */
234 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
236 for (i
= 0; i
< max
; i
++) {
237 pll
= &dev_priv
->shared_dplls
[i
];
239 /* Only want to check enabled timings first */
240 if (shared_dpll
[i
].crtc_mask
== 0)
243 if (memcmp(&crtc_state
->dpll_hw_state
,
244 &shared_dpll
[i
].hw_state
,
245 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
246 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
247 crtc
->base
.base
.id
, pll
->name
,
248 shared_dpll
[i
].crtc_mask
,
254 /* Ok no matching timings, maybe there's a free one? */
255 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
256 pll
= &dev_priv
->shared_dplls
[i
];
257 if (shared_dpll
[i
].crtc_mask
== 0) {
258 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
259 crtc
->base
.base
.id
, pll
->name
);
264 return DPLL_ID_PRIVATE
;
267 struct intel_shared_dpll
*
268 intel_get_shared_dpll(struct intel_crtc
*crtc
,
269 struct intel_crtc_state
*crtc_state
)
271 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
272 struct intel_shared_dpll
*pll
;
273 struct intel_shared_dpll_config
*shared_dpll
;
274 enum intel_dpll_id i
;
276 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
278 if (HAS_PCH_IBX(dev_priv
->dev
)) {
279 i
= ibx_get_fixed_dpll(crtc
, crtc_state
);
280 WARN_ON(shared_dpll
[i
].crtc_mask
);
281 } else if (IS_BROXTON(dev_priv
->dev
)) {
282 i
= bxt_get_fixed_dpll(crtc
, crtc_state
);
283 WARN_ON(shared_dpll
[i
].crtc_mask
);
285 i
= intel_find_shared_dpll(crtc
, crtc_state
);
291 pll
= &dev_priv
->shared_dplls
[i
];
293 if (shared_dpll
[i
].crtc_mask
== 0)
294 shared_dpll
[i
].hw_state
=
295 crtc_state
->dpll_hw_state
;
297 crtc_state
->shared_dpll
= pll
;
298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
299 pipe_name(crtc
->pipe
));
301 intel_shared_dpll_config_get(shared_dpll
, pll
, crtc
);
306 void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
308 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
309 struct intel_shared_dpll_config
*shared_dpll
;
310 struct intel_shared_dpll
*pll
;
311 enum intel_dpll_id i
;
313 if (!to_intel_atomic_state(state
)->dpll_set
)
316 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
317 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
318 pll
= &dev_priv
->shared_dplls
[i
];
319 pll
->config
= shared_dpll
[i
];
323 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
324 struct intel_shared_dpll
*pll
,
325 struct intel_dpll_hw_state
*hw_state
)
329 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
332 val
= I915_READ(PCH_DPLL(pll
->id
));
333 hw_state
->dpll
= val
;
334 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
335 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
337 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
339 return val
& DPLL_VCO_ENABLE
;
342 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
343 struct intel_shared_dpll
*pll
)
345 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
346 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
349 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
354 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
356 val
= I915_READ(PCH_DREF_CONTROL
);
357 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
358 DREF_SUPERSPREAD_SOURCE_MASK
));
359 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
362 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
363 struct intel_shared_dpll
*pll
)
365 /* PCH refclock must be enabled first */
366 ibx_assert_pch_refclk_enabled(dev_priv
);
368 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
370 /* Wait for the clocks to stabilize. */
371 POSTING_READ(PCH_DPLL(pll
->id
));
374 /* The pixel multiplier can only be updated once the
375 * DPLL is enabled and the clocks are stable.
379 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
380 POSTING_READ(PCH_DPLL(pll
->id
));
384 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
385 struct intel_shared_dpll
*pll
)
387 struct drm_device
*dev
= dev_priv
->dev
;
388 struct intel_crtc
*crtc
;
390 /* Make sure no transcoder isn't still depending on us. */
391 for_each_intel_crtc(dev
, crtc
) {
392 if (crtc
->config
->shared_dpll
== pll
)
393 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
396 I915_WRITE(PCH_DPLL(pll
->id
), 0);
397 POSTING_READ(PCH_DPLL(pll
->id
));
401 static char *ibx_pch_dpll_names
[] = {
406 static void ibx_pch_dpll_init(struct drm_device
*dev
)
408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
411 dev_priv
->num_shared_dpll
= 2;
413 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
414 dev_priv
->shared_dplls
[i
].id
= i
;
415 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
416 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
417 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
418 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
419 dev_priv
->shared_dplls
[i
].get_hw_state
=
420 ibx_pch_dpll_get_hw_state
;
424 static void hsw_ddi_wrpll_enable(struct drm_i915_private
*dev_priv
,
425 struct intel_shared_dpll
*pll
)
427 I915_WRITE(WRPLL_CTL(pll
->id
), pll
->config
.hw_state
.wrpll
);
428 POSTING_READ(WRPLL_CTL(pll
->id
));
432 static void hsw_ddi_spll_enable(struct drm_i915_private
*dev_priv
,
433 struct intel_shared_dpll
*pll
)
435 I915_WRITE(SPLL_CTL
, pll
->config
.hw_state
.spll
);
436 POSTING_READ(SPLL_CTL
);
440 static void hsw_ddi_wrpll_disable(struct drm_i915_private
*dev_priv
,
441 struct intel_shared_dpll
*pll
)
445 val
= I915_READ(WRPLL_CTL(pll
->id
));
446 I915_WRITE(WRPLL_CTL(pll
->id
), val
& ~WRPLL_PLL_ENABLE
);
447 POSTING_READ(WRPLL_CTL(pll
->id
));
450 static void hsw_ddi_spll_disable(struct drm_i915_private
*dev_priv
,
451 struct intel_shared_dpll
*pll
)
455 val
= I915_READ(SPLL_CTL
);
456 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
457 POSTING_READ(SPLL_CTL
);
460 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private
*dev_priv
,
461 struct intel_shared_dpll
*pll
,
462 struct intel_dpll_hw_state
*hw_state
)
466 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
469 val
= I915_READ(WRPLL_CTL(pll
->id
));
470 hw_state
->wrpll
= val
;
472 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
474 return val
& WRPLL_PLL_ENABLE
;
477 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private
*dev_priv
,
478 struct intel_shared_dpll
*pll
,
479 struct intel_dpll_hw_state
*hw_state
)
483 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
486 val
= I915_READ(SPLL_CTL
);
487 hw_state
->spll
= val
;
489 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
491 return val
& SPLL_PLL_ENABLE
;
495 static const char * const hsw_ddi_pll_names
[] = {
501 static void hsw_shared_dplls_init(struct drm_i915_private
*dev_priv
)
505 dev_priv
->num_shared_dpll
= 3;
507 for (i
= 0; i
< 2; i
++) {
508 dev_priv
->shared_dplls
[i
].id
= i
;
509 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
510 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_wrpll_disable
;
511 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_wrpll_enable
;
512 dev_priv
->shared_dplls
[i
].get_hw_state
=
513 hsw_ddi_wrpll_get_hw_state
;
516 /* SPLL is special, but needs to be initialized anyway.. */
517 dev_priv
->shared_dplls
[i
].id
= i
;
518 dev_priv
->shared_dplls
[i
].name
= hsw_ddi_pll_names
[i
];
519 dev_priv
->shared_dplls
[i
].disable
= hsw_ddi_spll_disable
;
520 dev_priv
->shared_dplls
[i
].enable
= hsw_ddi_spll_enable
;
521 dev_priv
->shared_dplls
[i
].get_hw_state
= hsw_ddi_spll_get_hw_state
;
525 static const char * const skl_ddi_pll_names
[] = {
531 struct skl_dpll_regs
{
532 i915_reg_t ctl
, cfgcr1
, cfgcr2
;
535 /* this array is indexed by the *shared* pll id */
536 static const struct skl_dpll_regs skl_dpll_regs
[3] = {
540 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL1
),
541 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL1
),
546 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL2
),
547 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL2
),
552 .cfgcr1
= DPLL_CFGCR1(SKL_DPLL3
),
553 .cfgcr2
= DPLL_CFGCR2(SKL_DPLL3
),
557 static void skl_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
558 struct intel_shared_dpll
*pll
)
562 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
564 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
567 val
= I915_READ(DPLL_CTRL1
);
569 val
&= ~(DPLL_CTRL1_HDMI_MODE(dpll
) | DPLL_CTRL1_SSC(dpll
) |
570 DPLL_CTRL1_LINK_RATE_MASK(dpll
));
571 val
|= pll
->config
.hw_state
.ctrl1
<< (dpll
* 6);
573 I915_WRITE(DPLL_CTRL1
, val
);
574 POSTING_READ(DPLL_CTRL1
);
576 I915_WRITE(regs
[pll
->id
].cfgcr1
, pll
->config
.hw_state
.cfgcr1
);
577 I915_WRITE(regs
[pll
->id
].cfgcr2
, pll
->config
.hw_state
.cfgcr2
);
578 POSTING_READ(regs
[pll
->id
].cfgcr1
);
579 POSTING_READ(regs
[pll
->id
].cfgcr2
);
581 /* the enable bit is always bit 31 */
582 I915_WRITE(regs
[pll
->id
].ctl
,
583 I915_READ(regs
[pll
->id
].ctl
) | LCPLL_PLL_ENABLE
);
585 if (wait_for(I915_READ(DPLL_STATUS
) & DPLL_LOCK(dpll
), 5))
586 DRM_ERROR("DPLL %d not locked\n", dpll
);
589 static void skl_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
590 struct intel_shared_dpll
*pll
)
592 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
594 /* the enable bit is always bit 31 */
595 I915_WRITE(regs
[pll
->id
].ctl
,
596 I915_READ(regs
[pll
->id
].ctl
) & ~LCPLL_PLL_ENABLE
);
597 POSTING_READ(regs
[pll
->id
].ctl
);
600 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
601 struct intel_shared_dpll
*pll
,
602 struct intel_dpll_hw_state
*hw_state
)
606 const struct skl_dpll_regs
*regs
= skl_dpll_regs
;
609 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
614 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
617 val
= I915_READ(regs
[pll
->id
].ctl
);
618 if (!(val
& LCPLL_PLL_ENABLE
))
621 val
= I915_READ(DPLL_CTRL1
);
622 hw_state
->ctrl1
= (val
>> (dpll
* 6)) & 0x3f;
624 /* avoid reading back stale values if HDMI mode is not enabled */
625 if (val
& DPLL_CTRL1_HDMI_MODE(dpll
)) {
626 hw_state
->cfgcr1
= I915_READ(regs
[pll
->id
].cfgcr1
);
627 hw_state
->cfgcr2
= I915_READ(regs
[pll
->id
].cfgcr2
);
632 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
637 static void skl_shared_dplls_init(struct drm_i915_private
*dev_priv
)
641 dev_priv
->num_shared_dpll
= 3;
643 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
644 dev_priv
->shared_dplls
[i
].id
= i
;
645 dev_priv
->shared_dplls
[i
].name
= skl_ddi_pll_names
[i
];
646 dev_priv
->shared_dplls
[i
].disable
= skl_ddi_pll_disable
;
647 dev_priv
->shared_dplls
[i
].enable
= skl_ddi_pll_enable
;
648 dev_priv
->shared_dplls
[i
].get_hw_state
=
649 skl_ddi_pll_get_hw_state
;
653 static const char * const bxt_ddi_pll_names
[] = {
659 static void bxt_ddi_pll_enable(struct drm_i915_private
*dev_priv
,
660 struct intel_shared_dpll
*pll
)
663 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
665 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
666 temp
&= ~PORT_PLL_REF_SEL
;
667 /* Non-SSC reference */
668 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
670 /* Disable 10 bit clock */
671 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
672 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
673 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
676 temp
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
677 temp
&= ~(PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
);
678 temp
|= pll
->config
.hw_state
.ebb0
;
679 I915_WRITE(BXT_PORT_PLL_EBB_0(port
), temp
);
681 /* Write M2 integer */
682 temp
= I915_READ(BXT_PORT_PLL(port
, 0));
683 temp
&= ~PORT_PLL_M2_MASK
;
684 temp
|= pll
->config
.hw_state
.pll0
;
685 I915_WRITE(BXT_PORT_PLL(port
, 0), temp
);
688 temp
= I915_READ(BXT_PORT_PLL(port
, 1));
689 temp
&= ~PORT_PLL_N_MASK
;
690 temp
|= pll
->config
.hw_state
.pll1
;
691 I915_WRITE(BXT_PORT_PLL(port
, 1), temp
);
693 /* Write M2 fraction */
694 temp
= I915_READ(BXT_PORT_PLL(port
, 2));
695 temp
&= ~PORT_PLL_M2_FRAC_MASK
;
696 temp
|= pll
->config
.hw_state
.pll2
;
697 I915_WRITE(BXT_PORT_PLL(port
, 2), temp
);
699 /* Write M2 fraction enable */
700 temp
= I915_READ(BXT_PORT_PLL(port
, 3));
701 temp
&= ~PORT_PLL_M2_FRAC_ENABLE
;
702 temp
|= pll
->config
.hw_state
.pll3
;
703 I915_WRITE(BXT_PORT_PLL(port
, 3), temp
);
706 temp
= I915_READ(BXT_PORT_PLL(port
, 6));
707 temp
&= ~PORT_PLL_PROP_COEFF_MASK
;
708 temp
&= ~PORT_PLL_INT_COEFF_MASK
;
709 temp
&= ~PORT_PLL_GAIN_CTL_MASK
;
710 temp
|= pll
->config
.hw_state
.pll6
;
711 I915_WRITE(BXT_PORT_PLL(port
, 6), temp
);
713 /* Write calibration val */
714 temp
= I915_READ(BXT_PORT_PLL(port
, 8));
715 temp
&= ~PORT_PLL_TARGET_CNT_MASK
;
716 temp
|= pll
->config
.hw_state
.pll8
;
717 I915_WRITE(BXT_PORT_PLL(port
, 8), temp
);
719 temp
= I915_READ(BXT_PORT_PLL(port
, 9));
720 temp
&= ~PORT_PLL_LOCK_THRESHOLD_MASK
;
721 temp
|= pll
->config
.hw_state
.pll9
;
722 I915_WRITE(BXT_PORT_PLL(port
, 9), temp
);
724 temp
= I915_READ(BXT_PORT_PLL(port
, 10));
725 temp
&= ~PORT_PLL_DCO_AMP_OVR_EN_H
;
726 temp
&= ~PORT_PLL_DCO_AMP_MASK
;
727 temp
|= pll
->config
.hw_state
.pll10
;
728 I915_WRITE(BXT_PORT_PLL(port
, 10), temp
);
730 /* Recalibrate with new settings */
731 temp
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
732 temp
|= PORT_PLL_RECALIBRATE
;
733 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
734 temp
&= ~PORT_PLL_10BIT_CLK_ENABLE
;
735 temp
|= pll
->config
.hw_state
.ebb4
;
736 I915_WRITE(BXT_PORT_PLL_EBB_4(port
), temp
);
739 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
740 temp
|= PORT_PLL_ENABLE
;
741 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
742 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
744 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port
)) &
745 PORT_PLL_LOCK
), 200))
746 DRM_ERROR("PLL %d not locked\n", port
);
749 * While we write to the group register to program all lanes at once we
750 * can read only lane registers and we pick lanes 0/1 for that.
752 temp
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
753 temp
&= ~LANE_STAGGER_MASK
;
754 temp
&= ~LANESTAGGER_STRAP_OVRD
;
755 temp
|= pll
->config
.hw_state
.pcsdw12
;
756 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port
), temp
);
759 static void bxt_ddi_pll_disable(struct drm_i915_private
*dev_priv
,
760 struct intel_shared_dpll
*pll
)
762 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
765 temp
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
766 temp
&= ~PORT_PLL_ENABLE
;
767 I915_WRITE(BXT_PORT_PLL_ENABLE(port
), temp
);
768 POSTING_READ(BXT_PORT_PLL_ENABLE(port
));
771 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private
*dev_priv
,
772 struct intel_shared_dpll
*pll
,
773 struct intel_dpll_hw_state
*hw_state
)
775 enum port port
= (enum port
)pll
->id
; /* 1:1 port->PLL mapping */
779 if (!intel_display_power_get_if_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
784 val
= I915_READ(BXT_PORT_PLL_ENABLE(port
));
785 if (!(val
& PORT_PLL_ENABLE
))
788 hw_state
->ebb0
= I915_READ(BXT_PORT_PLL_EBB_0(port
));
789 hw_state
->ebb0
&= PORT_PLL_P1_MASK
| PORT_PLL_P2_MASK
;
791 hw_state
->ebb4
= I915_READ(BXT_PORT_PLL_EBB_4(port
));
792 hw_state
->ebb4
&= PORT_PLL_10BIT_CLK_ENABLE
;
794 hw_state
->pll0
= I915_READ(BXT_PORT_PLL(port
, 0));
795 hw_state
->pll0
&= PORT_PLL_M2_MASK
;
797 hw_state
->pll1
= I915_READ(BXT_PORT_PLL(port
, 1));
798 hw_state
->pll1
&= PORT_PLL_N_MASK
;
800 hw_state
->pll2
= I915_READ(BXT_PORT_PLL(port
, 2));
801 hw_state
->pll2
&= PORT_PLL_M2_FRAC_MASK
;
803 hw_state
->pll3
= I915_READ(BXT_PORT_PLL(port
, 3));
804 hw_state
->pll3
&= PORT_PLL_M2_FRAC_ENABLE
;
806 hw_state
->pll6
= I915_READ(BXT_PORT_PLL(port
, 6));
807 hw_state
->pll6
&= PORT_PLL_PROP_COEFF_MASK
|
808 PORT_PLL_INT_COEFF_MASK
|
809 PORT_PLL_GAIN_CTL_MASK
;
811 hw_state
->pll8
= I915_READ(BXT_PORT_PLL(port
, 8));
812 hw_state
->pll8
&= PORT_PLL_TARGET_CNT_MASK
;
814 hw_state
->pll9
= I915_READ(BXT_PORT_PLL(port
, 9));
815 hw_state
->pll9
&= PORT_PLL_LOCK_THRESHOLD_MASK
;
817 hw_state
->pll10
= I915_READ(BXT_PORT_PLL(port
, 10));
818 hw_state
->pll10
&= PORT_PLL_DCO_AMP_OVR_EN_H
|
819 PORT_PLL_DCO_AMP_MASK
;
822 * While we write to the group register to program all lanes at once we
823 * can read only lane registers. We configure all lanes the same way, so
824 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
826 hw_state
->pcsdw12
= I915_READ(BXT_PORT_PCS_DW12_LN01(port
));
827 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port
)) != hw_state
->pcsdw12
)
828 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
830 I915_READ(BXT_PORT_PCS_DW12_LN23(port
)));
831 hw_state
->pcsdw12
&= LANE_STAGGER_MASK
| LANESTAGGER_STRAP_OVRD
;
836 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
841 static void bxt_shared_dplls_init(struct drm_i915_private
*dev_priv
)
845 dev_priv
->num_shared_dpll
= 3;
847 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
848 dev_priv
->shared_dplls
[i
].id
= i
;
849 dev_priv
->shared_dplls
[i
].name
= bxt_ddi_pll_names
[i
];
850 dev_priv
->shared_dplls
[i
].disable
= bxt_ddi_pll_disable
;
851 dev_priv
->shared_dplls
[i
].enable
= bxt_ddi_pll_enable
;
852 dev_priv
->shared_dplls
[i
].get_hw_state
=
853 bxt_ddi_pll_get_hw_state
;
857 static void intel_ddi_pll_init(struct drm_device
*dev
)
859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 uint32_t val
= I915_READ(LCPLL_CTL
);
862 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
863 skl_shared_dplls_init(dev_priv
);
864 else if (IS_BROXTON(dev
))
865 bxt_shared_dplls_init(dev_priv
);
867 hsw_shared_dplls_init(dev_priv
);
869 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
872 cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
873 dev_priv
->skl_boot_cdclk
= cdclk_freq
;
874 if (skl_sanitize_cdclk(dev_priv
))
875 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
876 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
))
877 DRM_ERROR("LCPLL1 is disabled\n");
878 } else if (IS_BROXTON(dev
)) {
879 broxton_init_cdclk(dev
);
880 broxton_ddi_phy_init(dev
);
883 * The LCPLL register should be turned on by the BIOS. For now
884 * let's just check its state and print errors in case
885 * something is wrong. Don't even try to turn it on.
888 if (val
& LCPLL_CD_SOURCE_FCLK
)
889 DRM_ERROR("CDCLK source is not LCPLL\n");
891 if (val
& LCPLL_PLL_DISABLE
)
892 DRM_ERROR("LCPLL is disabled\n");
896 void intel_shared_dpll_init(struct drm_device
*dev
)
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 intel_ddi_pll_init(dev
);
902 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
903 ibx_pch_dpll_init(dev
);
905 dev_priv
->num_shared_dpll
= 0;
907 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);