drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 /* Maximum cursor sizes */
  82 #define GEN2_CURSOR_WIDTH 64
  83 #define GEN2_CURSOR_HEIGHT 64
  84 #define CURSOR_WIDTH 256
  85 #define CURSOR_HEIGHT 256
  86
  87 #define INTEL_I2C_BUS_DVO 1
  88 #define INTEL_I2C_BUS_SDVO 2
  89
  90 /* these are outputs from the chip - integrated only
  91    external chips are via DVO or SDVO output */
  92 #define INTEL_OUTPUT_UNUSED 0
  93 #define INTEL_OUTPUT_ANALOG 1
  94 #define INTEL_OUTPUT_DVO 2
  95 #define INTEL_OUTPUT_SDVO 3
  96 #define INTEL_OUTPUT_LVDS 4
  97 #define INTEL_OUTPUT_TVOUT 5
  98 #define INTEL_OUTPUT_HDMI 6
  99 #define INTEL_OUTPUT_DISPLAYPORT 7
 100 #define INTEL_OUTPUT_EDP 8
 101 #define INTEL_OUTPUT_DSI 9
 102 #define INTEL_OUTPUT_UNKNOWN 10
 103
 104 #define INTEL_DVO_CHIP_NONE 0
 105 #define INTEL_DVO_CHIP_LVDS 1
 106 #define INTEL_DVO_CHIP_TMDS 2
 107 #define INTEL_DVO_CHIP_TVOUT 4
 108
 109 #define INTEL_DSI_COMMAND_MODE  0
 110 #define INTEL_DSI_VIDEO_MODE    1
 111
 112 struct intel_framebuffer {
 113         struct drm_framebuffer base;
 114         struct drm_i915_gem_object *obj;
 115 };
 116
 117 struct intel_fbdev {
 118         struct drm_fb_helper helper;
 119         struct intel_framebuffer *fb;
 120         struct list_head fbdev_list;
 121         struct drm_display_mode *our_mode;
 122         int preferred_bpp;
 123 };
 124
 125 struct intel_encoder {
 126         struct drm_encoder base;
 127         /*
 128          * The new crtc this encoder will be driven from. Only differs from
 129          * base->crtc while a modeset is in progress.
 130          */
 131         struct intel_crtc *new_crtc;
 132
 133         int type;
 134         unsigned int cloneable;
 135         bool connectors_active;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_config *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         /* Read out the current hw state of this connector, returning true if
 146          * the encoder is active. If the encoder is enabled it also set the pipe
 147          * it is connected to in the pipe parameter. */
 148         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 149         /* Reconstructs the equivalent mode flags for the current hardware
 150          * state. This must be called _after_ display->get_pipe_config has
 151          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 152          * be set correctly before calling this function. */
 153         void (*get_config)(struct intel_encoder *,
 154                            struct intel_crtc_config *pipe_config);
 155         int crtc_mask;
 156         enum hpd_pin hpd_pin;
 157 };
 158
 159 struct intel_panel {
 160         struct drm_display_mode *fixed_mode;
 161         struct drm_display_mode *downclock_mode;
 162         int fitting_mode;
 163
 164         /* backlight */
 165         struct {
 166                 bool present;
 167                 u32 level;
 168                 u32 max;
 169                 bool enabled;
 170                 bool combination_mode;  /* gen 2/4 only */
 171                 bool active_low_pwm;
 172                 struct backlight_device *device;
 173         } backlight;
 174 };
 175
 176 struct intel_connector {
 177         struct drm_connector base;
 178         /*
 179          * The fixed encoder this connector is connected to.
 180          */
 181         struct intel_encoder *encoder;
 182
 183         /*
 184          * The new encoder this connector will be driven. Only differs from
 185          * encoder while a modeset is in progress.
 186          */
 187         struct intel_encoder *new_encoder;
 188
 189         /* Reads out the current hw, returning true if the connector is enabled
 190          * and active (i.e. dpms ON state). */
 191         bool (*get_hw_state)(struct intel_connector *);
 192
 193         /*
 194          * Removes all interfaces through which the connector is accessible
 195          * - like sysfs, debugfs entries -, so that no new operations can be
 196          * started on the connector. Also makes sure all currently pending
 197          * operations finish before returing.
 198          */
 199         void (*unregister)(struct intel_connector *);
 200
 201         /* Panel info for eDP and LVDS */
 202         struct intel_panel panel;
 203
 204         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 205         struct edid *edid;
 206
 207         /* since POLL and HPD connectors may use the same HPD line keep the native
 208            state of connector->polled in case hotplug storm detection changes it */
 209         u8 polled;
 210 };
 211
 212 typedef struct dpll {
 213         /* given values */
 214         int n;
 215         int m1, m2;
 216         int p1, p2;
 217         /* derived values */
 218         int     dot;
 219         int     vco;
 220         int     m;
 221         int     p;
 222 } intel_clock_t;
 223
 224 struct intel_plane_config {
 225         bool tiled;
 226         int size;
 227         u32 base;
 228 };
 229
 230 struct intel_crtc_config {
 231         /**
 232          * quirks - bitfield with hw state readout quirks
 233          *
 234          * For various reasons the hw state readout code might not be able to
 235          * completely faithfully read out the current state. These cases are
 236          * tracked with quirk flags so that fastboot and state checker can act
 237          * accordingly.
 238          */
 239 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 240 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 241         unsigned long quirks;
 242
 243         /* User requested mode, only valid as a starting point to
 244          * compute adjusted_mode, except in the case of (S)DVO where
 245          * it's also for the output timings of the (S)DVO chip.
 246          * adjusted_mode will then correspond to the S(DVO) chip's
 247          * preferred input timings. */
 248         struct drm_display_mode requested_mode;
 249         /* Actual pipe timings ie. what we program into the pipe timing
 250          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 251         struct drm_display_mode adjusted_mode;
 252
 253         /* Pipe source size (ie. panel fitter input size)
 254          * All planes will be positioned inside this space,
 255          * and get clipped at the edges. */
 256         int pipe_src_w, pipe_src_h;
 257
 258         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 259          * between pch encoders and cpu encoders. */
 260         bool has_pch_encoder;
 261
 262         /* CPU Transcoder for the pipe. Currently this can only differ from the
 263          * pipe on Haswell (where we have a special eDP transcoder). */
 264         enum transcoder cpu_transcoder;
 265
 266         /*
 267          * Use reduced/limited/broadcast rbg range, compressing from the full
 268          * range fed into the crtcs.
 269          */
 270         bool limited_color_range;
 271
 272         /* DP has a bunch of special case unfortunately, so mark the pipe
 273          * accordingly. */
 274         bool has_dp_encoder;
 275
 276         /*
 277          * Enable dithering, used when the selected pipe bpp doesn't match the
 278          * plane bpp.
 279          */
 280         bool dither;
 281
 282         /* Controls for the clock computation, to override various stages. */
 283         bool clock_set;
 284
 285         /* SDVO TV has a bunch of special case. To make multifunction encoders
 286          * work correctly, we need to track this at runtime.*/
 287         bool sdvo_tv_clock;
 288
 289         /*
 290          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 291          * required. This is set in the 2nd loop of calling encoder's
 292          * ->compute_config if the first pick doesn't work out.
 293          */
 294         bool bw_constrained;
 295
 296         /* Settings for the intel dpll used on pretty much everything but
 297          * haswell. */
 298         struct dpll dpll;
 299
 300         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 301         enum intel_dpll_id shared_dpll;
 302
 303         /* Actual register state of the dpll, for shared dpll cross-checking. */
 304         struct intel_dpll_hw_state dpll_hw_state;
 305
 306         int pipe_bpp;
 307         struct intel_link_m_n dp_m_n;
 308
 309         /*
 310          * Frequence the dpll for the port should run at. Differs from the
 311          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 312          * already multiplied by pixel_multiplier.
 313          */
 314         int port_clock;
 315
 316         /* Used by SDVO (and if we ever fix it, HDMI). */
 317         unsigned pixel_multiplier;
 318
 319         /* Panel fitter controls for gen2-gen4 + VLV */
 320         struct {
 321                 u32 control;
 322                 u32 pgm_ratios;
 323                 u32 lvds_border_bits;
 324         } gmch_pfit;
 325
 326         /* Panel fitter placement and size for Ironlake+ */
 327         struct {
 328                 u32 pos;
 329                 u32 size;
 330                 bool enabled;
 331         } pch_pfit;
 332
 333         /* FDI configuration, only valid if has_pch_encoder is set. */
 334         int fdi_lanes;
 335         struct intel_link_m_n fdi_m_n;
 336
 337         bool ips_enabled;
 338
 339         bool double_wide;
 340 };
 341
 342 struct intel_pipe_wm {
 343         struct intel_wm_level wm[5];
 344         uint32_t linetime;
 345         bool fbc_wm_enabled;
 346 };
 347
 348 struct intel_crtc {
 349         struct drm_crtc base;
 350         enum pipe pipe;
 351         enum plane plane;
 352         u8 lut_r[256], lut_g[256], lut_b[256];
 353         /*
 354          * Whether the crtc and the connected output pipeline is active. Implies
 355          * that crtc->enabled is set, i.e. the current mode configuration has
 356          * some outputs connected to this crtc.
 357          */
 358         bool active;
 359         unsigned long enabled_power_domains;
 360         bool eld_vld;
 361         bool primary_enabled; /* is the primary plane (partially) visible? */
 362         bool lowfreq_avail;
 363         struct intel_overlay *overlay;
 364         struct intel_unpin_work *unpin_work;
 365
 366         atomic_t unpin_work_count;
 367
 368         /* Display surface base address adjustement for pageflips. Note that on
 369          * gen4+ this only adjusts up to a tile, offsets within a tile are
 370          * handled in the hw itself (with the TILEOFF register). */
 371         unsigned long dspaddr_offset;
 372
 373         struct drm_i915_gem_object *cursor_bo;
 374         uint32_t cursor_addr;
 375         int16_t cursor_x, cursor_y;
 376         int16_t cursor_width, cursor_height;
 377         int16_t max_cursor_width, max_cursor_height;
 378         bool cursor_visible;
 379
 380         struct intel_plane_config plane_config;
 381         struct intel_crtc_config config;
 382         struct intel_crtc_config *new_config;
 383         bool new_enabled;
 384
 385         uint32_t ddi_pll_sel;
 386
 387         /* reset counter value when the last flip was submitted */
 388         unsigned int reset_counter;
 389
 390         /* Access to these should be protected by dev_priv->irq_lock. */
 391         bool cpu_fifo_underrun_disabled;
 392         bool pch_fifo_underrun_disabled;
 393
 394         /* per-pipe watermark state */
 395         struct {
 396                 /* watermarks currently being used  */
 397                 struct intel_pipe_wm active;
 398         } wm;
 399 };
 400
 401 struct intel_plane_wm_parameters {
 402         uint32_t horiz_pixels;
 403         uint8_t bytes_per_pixel;
 404         bool enabled;
 405         bool scaled;
 406 };
 407
 408 struct intel_plane {
 409         struct drm_plane base;
 410         int plane;
 411         enum pipe pipe;
 412         struct drm_i915_gem_object *obj;
 413         bool can_scale;
 414         int max_downscale;
 415         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 416         int crtc_x, crtc_y;
 417         unsigned int crtc_w, crtc_h;
 418         uint32_t src_x, src_y;
 419         uint32_t src_w, src_h;
 420
 421         /* Since we need to change the watermarks before/after
 422          * enabling/disabling the planes, we need to store the parameters here
 423          * as the other pieces of the struct may not reflect the values we want
 424          * for the watermark calculations. Currently only Haswell uses this.
 425          */
 426         struct intel_plane_wm_parameters wm;
 427
 428         void (*update_plane)(struct drm_plane *plane,
 429                              struct drm_crtc *crtc,
 430                              struct drm_framebuffer *fb,
 431                              struct drm_i915_gem_object *obj,
 432                              int crtc_x, int crtc_y,
 433                              unsigned int crtc_w, unsigned int crtc_h,
 434                              uint32_t x, uint32_t y,
 435                              uint32_t src_w, uint32_t src_h);
 436         void (*disable_plane)(struct drm_plane *plane,
 437                               struct drm_crtc *crtc);
 438         int (*update_colorkey)(struct drm_plane *plane,
 439                                struct drm_intel_sprite_colorkey *key);
 440         void (*get_colorkey)(struct drm_plane *plane,
 441                              struct drm_intel_sprite_colorkey *key);
 442 };
 443
 444 struct intel_watermark_params {
 445         unsigned long fifo_size;
 446         unsigned long max_wm;
 447         unsigned long default_wm;
 448         unsigned long guard_size;
 449         unsigned long cacheline_size;
 450 };
 451
 452 struct cxsr_latency {
 453         int is_desktop;
 454         int is_ddr3;
 455         unsigned long fsb_freq;
 456         unsigned long mem_freq;
 457         unsigned long display_sr;
 458         unsigned long display_hpll_disable;
 459         unsigned long cursor_sr;
 460         unsigned long cursor_hpll_disable;
 461 };
 462
 463 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 464 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 465 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 466 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 467 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 468
 469 struct intel_hdmi {
 470         u32 hdmi_reg;
 471         int ddc_bus;
 472         uint32_t color_range;
 473         bool color_range_auto;
 474         bool has_hdmi_sink;
 475         bool has_audio;
 476         enum hdmi_force_audio force_audio;
 477         bool rgb_quant_range_selectable;
 478         void (*write_infoframe)(struct drm_encoder *encoder,
 479                                 enum hdmi_infoframe_type type,
 480                                 const void *frame, ssize_t len);
 481         void (*set_infoframes)(struct drm_encoder *encoder,
 482                                struct drm_display_mode *adjusted_mode);
 483 };
 484
 485 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 486
 487 struct intel_dp {
 488         uint32_t output_reg;
 489         uint32_t aux_ch_ctl_reg;
 490         uint32_t DP;
 491         bool has_audio;
 492         enum hdmi_force_audio force_audio;
 493         uint32_t color_range;
 494         bool color_range_auto;
 495         uint8_t link_bw;
 496         uint8_t lane_count;
 497         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 498         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 499         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 500         struct drm_dp_aux aux;
 501         uint8_t train_set[4];
 502         int panel_power_up_delay;
 503         int panel_power_down_delay;
 504         int panel_power_cycle_delay;
 505         int backlight_on_delay;
 506         int backlight_off_delay;
 507         struct delayed_work panel_vdd_work;
 508         bool want_panel_vdd;
 509         unsigned long last_power_cycle;
 510         unsigned long last_power_on;
 511         unsigned long last_backlight_off;
 512         bool psr_setup_done;
 513         bool use_tps3;
 514         struct intel_connector *attached_connector;
 515
 516         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 517         /*
 518          * This function returns the value we have to program the AUX_CTL
 519          * register with to kick off an AUX transaction.
 520          */
 521         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 522                                      bool has_aux_irq,
 523                                      int send_bytes,
 524                                      uint32_t aux_clock_divider);
 525 };
 526
 527 struct intel_digital_port {
 528         struct intel_encoder base;
 529         enum port port;
 530         u32 saved_port_bits;
 531         struct intel_dp dp;
 532         struct intel_hdmi hdmi;
 533 };
 534
 535 static inline int
 536 vlv_dport_to_channel(struct intel_digital_port *dport)
 537 {
 538         switch (dport->port) {
 539         case PORT_B:
 540                 return DPIO_CH0;
 541         case PORT_C:
 542                 return DPIO_CH1;
 543         default:
 544                 BUG();
 545         }
 546 }
 547
 548 static inline struct drm_crtc *
 549 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 550 {
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552         return dev_priv->pipe_to_crtc_mapping[pipe];
 553 }
 554
 555 static inline struct drm_crtc *
 556 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 557 {
 558         struct drm_i915_private *dev_priv = dev->dev_private;
 559         return dev_priv->plane_to_crtc_mapping[plane];
 560 }
 561
 562 struct intel_unpin_work {
 563         struct work_struct work;
 564         struct drm_crtc *crtc;
 565         struct drm_i915_gem_object *old_fb_obj;
 566         struct drm_i915_gem_object *pending_flip_obj;
 567         struct drm_pending_vblank_event *event;
 568         atomic_t pending;
 569 #define INTEL_FLIP_INACTIVE     0
 570 #define INTEL_FLIP_PENDING      1
 571 #define INTEL_FLIP_COMPLETE     2
 572         bool enable_stall_check;
 573 };
 574
 575 struct intel_set_config {
 576         struct drm_encoder **save_connector_encoders;
 577         struct drm_crtc **save_encoder_crtcs;
 578         bool *save_crtc_enabled;
 579
 580         bool fb_changed;
 581         bool mode_changed;
 582 };
 583
 584 struct intel_load_detect_pipe {
 585         struct drm_framebuffer *release_fb;
 586         bool load_detect_temp;
 587         int dpms_mode;
 588 };
 589
 590 static inline struct intel_encoder *
 591 intel_attached_encoder(struct drm_connector *connector)
 592 {
 593         return to_intel_connector(connector)->encoder;
 594 }
 595
 596 static inline struct intel_digital_port *
 597 enc_to_dig_port(struct drm_encoder *encoder)
 598 {
 599         return container_of(encoder, struct intel_digital_port, base.base);
 600 }
 601
 602 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 603 {
 604         return &enc_to_dig_port(encoder)->dp;
 605 }
 606
 607 static inline struct intel_digital_port *
 608 dp_to_dig_port(struct intel_dp *intel_dp)
 609 {
 610         return container_of(intel_dp, struct intel_digital_port, dp);
 611 }
 612
 613 static inline struct intel_digital_port *
 614 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 615 {
 616         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 617 }
 618
 619
 620 /* i915_irq.c */
 621 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 622                                            enum pipe pipe, bool enable);
 623 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 624                                              enum pipe pipe, bool enable);
 625 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 626                                            enum transcoder pch_transcoder,
 627                                            bool enable);
 628 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 629 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 630 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 631 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 632 void hsw_runtime_pm_disable_interrupts(struct drm_device *dev);
 633 void hsw_runtime_pm_restore_interrupts(struct drm_device *dev);
 634
 635
 636 /* intel_crt.c */
 637 void intel_crt_init(struct drm_device *dev);
 638
 639
 640 /* intel_ddi.c */
 641 void intel_prepare_ddi(struct drm_device *dev);
 642 void hsw_fdi_link_train(struct drm_crtc *crtc);
 643 void intel_ddi_init(struct drm_device *dev, enum port port);
 644 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 645 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 646 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 647 void intel_ddi_pll_init(struct drm_device *dev);
 648 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 649 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 650                                        enum transcoder cpu_transcoder);
 651 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 652 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 653 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 654 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 655 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 656 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 657 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 658 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 659 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 660 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 661 void intel_ddi_get_config(struct intel_encoder *encoder,
 662                           struct intel_crtc_config *pipe_config);
 663
 664
 665 /* intel_display.c */
 666 const char *intel_output_name(int output);
 667 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 668 int intel_pch_rawclk(struct drm_device *dev);
 669 void intel_mark_busy(struct drm_device *dev);
 670 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 671                         struct intel_ring_buffer *ring);
 672 void intel_mark_idle(struct drm_device *dev);
 673 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 674 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 675 void intel_encoder_destroy(struct drm_encoder *encoder);
 676 void intel_connector_dpms(struct drm_connector *, int mode);
 677 bool intel_connector_get_hw_state(struct intel_connector *connector);
 678 void intel_modeset_check_state(struct drm_device *dev);
 679 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 680                                 struct intel_digital_port *port);
 681 void intel_connector_attach_encoder(struct intel_connector *connector,
 682                                     struct intel_encoder *encoder);
 683 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 684 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 685                                              struct drm_crtc *crtc);
 686 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 687 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 688                                 struct drm_file *file_priv);
 689 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 690                                              enum pipe pipe);
 691 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 692 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 693 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 694 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 695                          struct intel_digital_port *dport);
 696 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 697                                 struct drm_display_mode *mode,
 698                                 struct intel_load_detect_pipe *old);
 699 void intel_release_load_detect_pipe(struct drm_connector *connector,
 700                                     struct intel_load_detect_pipe *old);
 701 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 702                                struct drm_i915_gem_object *obj,
 703                                struct intel_ring_buffer *pipelined);
 704 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 705 struct drm_framebuffer *
 706 __intel_framebuffer_create(struct drm_device *dev,
 707                            struct drm_mode_fb_cmd2 *mode_cmd,
 708                            struct drm_i915_gem_object *obj);
 709 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 710 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 711 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 712 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 713 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 714                         struct intel_shared_dpll *pll,
 715                         bool state);
 716 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 717 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 718 void assert_pll(struct drm_i915_private *dev_priv,
 719                 enum pipe pipe, bool state);
 720 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 721 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 722 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 723                        enum pipe pipe, bool state);
 724 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 725 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 726 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 727 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 728 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 729 void intel_write_eld(struct drm_encoder *encoder,
 730                      struct drm_display_mode *mode);
 731 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 732                                              unsigned int tiling_mode,
 733                                              unsigned int bpp,
 734                                              unsigned int pitch);
 735 void intel_display_handle_reset(struct drm_device *dev);
 736 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 737 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 738 void intel_dp_get_m_n(struct intel_crtc *crtc,
 739                       struct intel_crtc_config *pipe_config);
 740 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 741 void
 742 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 743                                 int dotclock);
 744 bool intel_crtc_active(struct drm_crtc *crtc);
 745 void hsw_enable_ips(struct intel_crtc *crtc);
 746 void hsw_disable_ips(struct intel_crtc *crtc);
 747 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 748 enum intel_display_power_domain
 749 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
 750 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 751 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 752                                  struct intel_crtc_config *pipe_config);
 753 int intel_format_to_fourcc(int format);
 754
 755 /* intel_dp.c */
 756 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 757 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 758                              struct intel_connector *intel_connector);
 759 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 760 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 761 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 762 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 763 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 764 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 765 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 766 bool intel_dp_compute_config(struct intel_encoder *encoder,
 767                              struct intel_crtc_config *pipe_config);
 768 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 769 void intel_edp_backlight_on(struct intel_dp *intel_dp);
 770 void intel_edp_backlight_off(struct intel_dp *intel_dp);
 771 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
 772 void intel_edp_panel_on(struct intel_dp *intel_dp);
 773 void intel_edp_panel_off(struct intel_dp *intel_dp);
 774 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 775 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 776 void intel_edp_psr_update(struct drm_device *dev);
 777
 778
 779 /* intel_dsi.c */
 780 bool intel_dsi_init(struct drm_device *dev);
 781
 782
 783 /* intel_dvo.c */
 784 void intel_dvo_init(struct drm_device *dev);
 785
 786
 787 /* legacy fbdev emulation in intel_fbdev.c */
 788 #ifdef CONFIG_DRM_I915_FBDEV
 789 extern int intel_fbdev_init(struct drm_device *dev);
 790 extern void intel_fbdev_initial_config(struct drm_device *dev);
 791 extern void intel_fbdev_fini(struct drm_device *dev);
 792 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 793 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 794 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 795 #else
 796 static inline int intel_fbdev_init(struct drm_device *dev)
 797 {
 798         return 0;
 799 }
 800
 801 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 802 {
 803 }
 804
 805 static inline void intel_fbdev_fini(struct drm_device *dev)
 806 {
 807 }
 808
 809 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 810 {
 811 }
 812
 813 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 814 {
 815 }
 816 #endif
 817
 818 /* intel_hdmi.c */
 819 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 820 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 821                                struct intel_connector *intel_connector);
 822 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 823 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 824                                struct intel_crtc_config *pipe_config);
 825
 826
 827 /* intel_lvds.c */
 828 void intel_lvds_init(struct drm_device *dev);
 829 bool intel_is_dual_link_lvds(struct drm_device *dev);
 830
 831
 832 /* intel_modes.c */
 833 int intel_connector_update_modes(struct drm_connector *connector,
 834                                  struct edid *edid);
 835 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 836 void intel_attach_force_audio_property(struct drm_connector *connector);
 837 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 838
 839
 840 /* intel_overlay.c */
 841 void intel_setup_overlay(struct drm_device *dev);
 842 void intel_cleanup_overlay(struct drm_device *dev);
 843 int intel_overlay_switch_off(struct intel_overlay *overlay);
 844 int intel_overlay_put_image(struct drm_device *dev, void *data,
 845                             struct drm_file *file_priv);
 846 int intel_overlay_attrs(struct drm_device *dev, void *data,
 847                         struct drm_file *file_priv);
 848
 849
 850 /* intel_panel.c */
 851 int intel_panel_init(struct intel_panel *panel,
 852                      struct drm_display_mode *fixed_mode,
 853                      struct drm_display_mode *downclock_mode);
 854 void intel_panel_fini(struct intel_panel *panel);
 855 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 856                             struct drm_display_mode *adjusted_mode);
 857 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 858                              struct intel_crtc_config *pipe_config,
 859                              int fitting_mode);
 860 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 861                               struct intel_crtc_config *pipe_config,
 862                               int fitting_mode);
 863 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 864                                u32 max);
 865 int intel_panel_setup_backlight(struct drm_connector *connector);
 866 void intel_panel_enable_backlight(struct intel_connector *connector);
 867 void intel_panel_disable_backlight(struct intel_connector *connector);
 868 void intel_panel_destroy_backlight(struct drm_connector *connector);
 869 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 870 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 871 extern struct drm_display_mode *intel_find_panel_downclock(
 872                                 struct drm_device *dev,
 873                                 struct drm_display_mode *fixed_mode,
 874                                 struct drm_connector *connector);
 875
 876 /* intel_pm.c */
 877 void intel_init_clock_gating(struct drm_device *dev);
 878 void intel_suspend_hw(struct drm_device *dev);
 879 void intel_update_watermarks(struct drm_crtc *crtc);
 880 void intel_update_sprite_watermarks(struct drm_plane *plane,
 881                                     struct drm_crtc *crtc,
 882                                     uint32_t sprite_width, int pixel_size,
 883                                     bool enabled, bool scaled);
 884 void intel_init_pm(struct drm_device *dev);
 885 void intel_pm_setup(struct drm_device *dev);
 886 bool intel_fbc_enabled(struct drm_device *dev);
 887 void intel_update_fbc(struct drm_device *dev);
 888 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 889 void intel_gpu_ips_teardown(void);
 890 int intel_power_domains_init(struct drm_i915_private *);
 891 void intel_power_domains_remove(struct drm_i915_private *);
 892 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
 893                                  enum intel_display_power_domain domain);
 894 bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
 895                                     enum intel_display_power_domain domain);
 896 void intel_display_power_get(struct drm_i915_private *dev_priv,
 897                              enum intel_display_power_domain domain);
 898 void intel_display_power_put(struct drm_i915_private *dev_priv,
 899                              enum intel_display_power_domain domain);
 900 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
 901 void intel_init_gt_powersave(struct drm_device *dev);
 902 void intel_cleanup_gt_powersave(struct drm_device *dev);
 903 void intel_enable_gt_powersave(struct drm_device *dev);
 904 void intel_disable_gt_powersave(struct drm_device *dev);
 905 void ironlake_teardown_rc6(struct drm_device *dev);
 906 void gen6_update_ring_freq(struct drm_device *dev);
 907 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 908 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 909 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 910 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 911 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 912 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 913 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 914 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 915 void ilk_wm_get_hw_state(struct drm_device *dev);
 916
 917
 918 /* intel_sdvo.c */
 919 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 920
 921
 922 /* intel_sprite.c */
 923 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 924 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 925                                enum plane plane);
 926 void intel_plane_restore(struct drm_plane *plane);
 927 void intel_plane_disable(struct drm_plane *plane);
 928 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 929                               struct drm_file *file_priv);
 930 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 931                               struct drm_file *file_priv);
 932
 933
 934 /* intel_tv.c */
 935 void intel_tv_init(struct drm_device *dev);
 936
 937 #endif /* __INTEL_DRV_H__ */