drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         int preferred_bpp;
 127 };
 128
 129 struct intel_encoder {
 130         struct drm_encoder base;
 131
 132         enum intel_output_type type;
 133         unsigned int cloneable;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_state *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         void (*post_pll_disable)(struct intel_encoder *);
 144         /* Read out the current hw state of this connector, returning true if
 145          * the encoder is active. If the encoder is enabled it also set the pipe
 146          * it is connected to in the pipe parameter. */
 147         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 148         /* Reconstructs the equivalent mode flags for the current hardware
 149          * state. This must be called _after_ display->get_pipe_config has
 150          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 151          * be set correctly before calling this function. */
 152         void (*get_config)(struct intel_encoder *,
 153                            struct intel_crtc_state *pipe_config);
 154         /*
 155          * Called during system suspend after all pending requests for the
 156          * encoder are flushed (for example for DP AUX transactions) and
 157          * device interrupts are disabled.
 158          */
 159         void (*suspend)(struct intel_encoder *);
 160         int crtc_mask;
 161         enum hpd_pin hpd_pin;
 162 };
 163
 164 struct intel_panel {
 165         struct drm_display_mode *fixed_mode;
 166         struct drm_display_mode *downclock_mode;
 167         int fitting_mode;
 168
 169         /* backlight */
 170         struct {
 171                 bool present;
 172                 u32 level;
 173                 u32 min;
 174                 u32 max;
 175                 bool enabled;
 176                 bool combination_mode;  /* gen 2/4 only */
 177                 bool active_low_pwm;
 178
 179                 /* PWM chip */
 180                 bool util_pin_active_low;       /* bxt+ */
 181                 u8 controller;          /* bxt+ only */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185
 186                 /* Connector and platform specific backlight functions */
 187                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 188                 uint32_t (*get)(struct intel_connector *connector);
 189                 void (*set)(struct intel_connector *connector, uint32_t level);
 190                 void (*disable)(struct intel_connector *connector);
 191                 void (*enable)(struct intel_connector *connector);
 192                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 193                                       uint32_t hz);
 194                 void (*power)(struct intel_connector *, bool enable);
 195         } backlight;
 196 };
 197
 198 struct intel_connector {
 199         struct drm_connector base;
 200         /*
 201          * The fixed encoder this connector is connected to.
 202          */
 203         struct intel_encoder *encoder;
 204
 205         /* Reads out the current hw, returning true if the connector is enabled
 206          * and active (i.e. dpms ON state). */
 207         bool (*get_hw_state)(struct intel_connector *);
 208
 209         /*
 210          * Removes all interfaces through which the connector is accessible
 211          * - like sysfs, debugfs entries -, so that no new operations can be
 212          * started on the connector. Also makes sure all currently pending
 213          * operations finish before returing.
 214          */
 215         void (*unregister)(struct intel_connector *);
 216
 217         /* Panel info for eDP and LVDS */
 218         struct intel_panel panel;
 219
 220         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 221         struct edid *edid;
 222         struct edid *detect_edid;
 223
 224         /* since POLL and HPD connectors may use the same HPD line keep the native
 225            state of connector->polled in case hotplug storm detection changes it */
 226         u8 polled;
 227
 228         void *port; /* store this opaque as its illegal to dereference it */
 229
 230         struct intel_dp *mst_port;
 231 };
 232
 233 typedef struct dpll {
 234         /* given values */
 235         int n;
 236         int m1, m2;
 237         int p1, p2;
 238         /* derived values */
 239         int     dot;
 240         int     vco;
 241         int     m;
 242         int     p;
 243 } intel_clock_t;
 244
 245 struct intel_atomic_state {
 246         struct drm_atomic_state base;
 247
 248         unsigned int cdclk;
 249
 250         /*
 251          * Calculated device cdclk, can be different from cdclk
 252          * only when all crtc's are DPMS off.
 253          */
 254         unsigned int dev_cdclk;
 255
 256         bool dpll_set, modeset;
 257
 258         unsigned int active_crtcs;
 259         unsigned int min_pixclk[I915_MAX_PIPES];
 260
 261         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 262         struct intel_wm_config wm_config;
 263
 264         /*
 265          * Current watermarks can't be trusted during hardware readout, so
 266          * don't bother calculating intermediate watermarks.
 267          */
 268         bool skip_intermediate_wm;
 269 };
 270
 271 struct intel_plane_state {
 272         struct drm_plane_state base;
 273         struct drm_rect src;
 274         struct drm_rect dst;
 275         struct drm_rect clip;
 276         bool visible;
 277
 278         /*
 279          * scaler_id
 280          *    = -1 : not using a scaler
 281          *    >=  0 : using a scalers
 282          *
 283          * plane requiring a scaler:
 284          *   - During check_plane, its bit is set in
 285          *     crtc_state->scaler_state.scaler_users by calling helper function
 286          *     update_scaler_plane.
 287          *   - scaler_id indicates the scaler it got assigned.
 288          *
 289          * plane doesn't require a scaler:
 290          *   - this can happen when scaling is no more required or plane simply
 291          *     got disabled.
 292          *   - During check_plane, corresponding bit is reset in
 293          *     crtc_state->scaler_state.scaler_users by calling helper function
 294          *     update_scaler_plane.
 295          */
 296         int scaler_id;
 297
 298         struct drm_intel_sprite_colorkey ckey;
 299
 300         /* async flip related structures */
 301         struct drm_i915_gem_request *wait_req;
 302 };
 303
 304 struct intel_initial_plane_config {
 305         struct intel_framebuffer *fb;
 306         unsigned int tiling;
 307         int size;
 308         u32 base;
 309 };
 310
 311 #define SKL_MIN_SRC_W 8
 312 #define SKL_MAX_SRC_W 4096
 313 #define SKL_MIN_SRC_H 8
 314 #define SKL_MAX_SRC_H 4096
 315 #define SKL_MIN_DST_W 8
 316 #define SKL_MAX_DST_W 4096
 317 #define SKL_MIN_DST_H 8
 318 #define SKL_MAX_DST_H 4096
 319
 320 struct intel_scaler {
 321         int in_use;
 322         uint32_t mode;
 323 };
 324
 325 struct intel_crtc_scaler_state {
 326 #define SKL_NUM_SCALERS 2
 327         struct intel_scaler scalers[SKL_NUM_SCALERS];
 328
 329         /*
 330          * scaler_users: keeps track of users requesting scalers on this crtc.
 331          *
 332          *     If a bit is set, a user is using a scaler.
 333          *     Here user can be a plane or crtc as defined below:
 334          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 335          *       bit 31    - crtc
 336          *
 337          * Instead of creating a new index to cover planes and crtc, using
 338          * existing drm_plane_index for planes which is well less than 31
 339          * planes and bit 31 for crtc. This should be fine to cover all
 340          * our platforms.
 341          *
 342          * intel_atomic_setup_scalers will setup available scalers to users
 343          * requesting scalers. It will gracefully fail if request exceeds
 344          * avilability.
 345          */
 346 #define SKL_CRTC_INDEX 31
 347         unsigned scaler_users;
 348
 349         /* scaler used by crtc for panel fitting purpose */
 350         int scaler_id;
 351 };
 352
 353 /* drm_mode->private_flags */
 354 #define I915_MODE_FLAG_INHERITED 1
 355
 356 struct intel_pipe_wm {
 357         struct intel_wm_level wm[5];
 358         uint32_t linetime;
 359         bool fbc_wm_enabled;
 360         bool pipe_enabled;
 361         bool sprites_enabled;
 362         bool sprites_scaled;
 363 };
 364
 365 struct skl_pipe_wm {
 366         struct skl_wm_level wm[8];
 367         struct skl_wm_level trans_wm;
 368         uint32_t linetime;
 369 };
 370
 371 struct intel_crtc_state {
 372         struct drm_crtc_state base;
 373
 374         /**
 375          * quirks - bitfield with hw state readout quirks
 376          *
 377          * For various reasons the hw state readout code might not be able to
 378          * completely faithfully read out the current state. These cases are
 379          * tracked with quirk flags so that fastboot and state checker can act
 380          * accordingly.
 381          */
 382 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 383         unsigned long quirks;
 384
 385         bool update_pipe; /* can a fast modeset be performed? */
 386         bool disable_cxsr;
 387         bool wm_changed; /* watermarks are updated */
 388         bool fb_changed; /* fb on any of the planes is changed */
 389
 390         /* Pipe source size (ie. panel fitter input size)
 391          * All planes will be positioned inside this space,
 392          * and get clipped at the edges. */
 393         int pipe_src_w, pipe_src_h;
 394
 395         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 396          * between pch encoders and cpu encoders. */
 397         bool has_pch_encoder;
 398
 399         /* Are we sending infoframes on the attached port */
 400         bool has_infoframe;
 401
 402         /* CPU Transcoder for the pipe. Currently this can only differ from the
 403          * pipe on Haswell (where we have a special eDP transcoder). */
 404         enum transcoder cpu_transcoder;
 405
 406         /*
 407          * Use reduced/limited/broadcast rbg range, compressing from the full
 408          * range fed into the crtcs.
 409          */
 410         bool limited_color_range;
 411
 412         /* DP has a bunch of special case unfortunately, so mark the pipe
 413          * accordingly. */
 414         bool has_dp_encoder;
 415
 416         /* DSI has special cases */
 417         bool has_dsi_encoder;
 418
 419         /* Whether we should send NULL infoframes. Required for audio. */
 420         bool has_hdmi_sink;
 421
 422         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 423          * has_dp_encoder is set. */
 424         bool has_audio;
 425
 426         /*
 427          * Enable dithering, used when the selected pipe bpp doesn't match the
 428          * plane bpp.
 429          */
 430         bool dither;
 431
 432         /* Controls for the clock computation, to override various stages. */
 433         bool clock_set;
 434
 435         /* SDVO TV has a bunch of special case. To make multifunction encoders
 436          * work correctly, we need to track this at runtime.*/
 437         bool sdvo_tv_clock;
 438
 439         /*
 440          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 441          * required. This is set in the 2nd loop of calling encoder's
 442          * ->compute_config if the first pick doesn't work out.
 443          */
 444         bool bw_constrained;
 445
 446         /* Settings for the intel dpll used on pretty much everything but
 447          * haswell. */
 448         struct dpll dpll;
 449
 450         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 451         enum intel_dpll_id shared_dpll;
 452
 453         /*
 454          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 455          * - enum skl_dpll on SKL
 456          */
 457         uint32_t ddi_pll_sel;
 458
 459         /* Actual register state of the dpll, for shared dpll cross-checking. */
 460         struct intel_dpll_hw_state dpll_hw_state;
 461
 462         int pipe_bpp;
 463         struct intel_link_m_n dp_m_n;
 464
 465         /* m2_n2 for eDP downclock */
 466         struct intel_link_m_n dp_m2_n2;
 467         bool has_drrs;
 468
 469         /*
 470          * Frequence the dpll for the port should run at. Differs from the
 471          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 472          * already multiplied by pixel_multiplier.
 473          */
 474         int port_clock;
 475
 476         /* Used by SDVO (and if we ever fix it, HDMI). */
 477         unsigned pixel_multiplier;
 478
 479         uint8_t lane_count;
 480
 481         /* Panel fitter controls for gen2-gen4 + VLV */
 482         struct {
 483                 u32 control;
 484                 u32 pgm_ratios;
 485                 u32 lvds_border_bits;
 486         } gmch_pfit;
 487
 488         /* Panel fitter placement and size for Ironlake+ */
 489         struct {
 490                 u32 pos;
 491                 u32 size;
 492                 bool enabled;
 493                 bool force_thru;
 494         } pch_pfit;
 495
 496         /* FDI configuration, only valid if has_pch_encoder is set. */
 497         int fdi_lanes;
 498         struct intel_link_m_n fdi_m_n;
 499
 500         bool ips_enabled;
 501
 502         bool enable_fbc;
 503
 504         bool double_wide;
 505
 506         bool dp_encoder_is_mst;
 507         int pbn;
 508
 509         struct intel_crtc_scaler_state scaler_state;
 510
 511         /* w/a for waiting 2 vblanks during crtc enable */
 512         enum pipe hsw_workaround_pipe;
 513
 514         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 515         bool disable_lp_wm;
 516
 517         struct {
 518                 /*
 519                  * Optimal watermarks, programmed post-vblank when this state
 520                  * is committed.
 521                  */
 522                 union {
 523                         struct intel_pipe_wm ilk;
 524                         struct skl_pipe_wm skl;
 525                 } optimal;
 526
 527                 /*
 528                  * Intermediate watermarks; these can be programmed immediately
 529                  * since they satisfy both the current configuration we're
 530                  * switching away from and the new configuration we're switching
 531                  * to.
 532                  */
 533                 struct intel_pipe_wm intermediate;
 534
 535                 /*
 536                  * Platforms with two-step watermark programming will need to
 537                  * update watermark programming post-vblank to switch from the
 538                  * safe intermediate watermarks to the optimal final
 539                  * watermarks.
 540                  */
 541                 bool need_postvbl_update;
 542         } wm;
 543 };
 544
 545 struct vlv_wm_state {
 546         struct vlv_pipe_wm wm[3];
 547         struct vlv_sr_wm sr[3];
 548         uint8_t num_active_planes;
 549         uint8_t num_levels;
 550         uint8_t level;
 551         bool cxsr;
 552 };
 553
 554 struct intel_mmio_flip {
 555         struct work_struct work;
 556         struct drm_i915_private *i915;
 557         struct drm_i915_gem_request *req;
 558         struct intel_crtc *crtc;
 559         unsigned int rotation;
 560 };
 561
 562 /*
 563  * Tracking of operations that need to be performed at the beginning/end of an
 564  * atomic commit, outside the atomic section where interrupts are disabled.
 565  * These are generally operations that grab mutexes or might otherwise sleep
 566  * and thus can't be run with interrupts disabled.
 567  */
 568 struct intel_crtc_atomic_commit {
 569         /* Sleepable operations to perform before commit */
 570
 571         /* Sleepable operations to perform after commit */
 572         unsigned fb_bits;
 573         bool post_enable_primary;
 574
 575         /* Sleepable operations to perform before and after commit */
 576         bool update_fbc;
 577 };
 578
 579 struct intel_crtc {
 580         struct drm_crtc base;
 581         enum pipe pipe;
 582         enum plane plane;
 583         u8 lut_r[256], lut_g[256], lut_b[256];
 584         /*
 585          * Whether the crtc and the connected output pipeline is active. Implies
 586          * that crtc->enabled is set, i.e. the current mode configuration has
 587          * some outputs connected to this crtc.
 588          */
 589         bool active;
 590         unsigned long enabled_power_domains;
 591         bool lowfreq_avail;
 592         struct intel_overlay *overlay;
 593         struct intel_unpin_work *unpin_work;
 594
 595         atomic_t unpin_work_count;
 596
 597         /* Display surface base address adjustement for pageflips. Note that on
 598          * gen4+ this only adjusts up to a tile, offsets within a tile are
 599          * handled in the hw itself (with the TILEOFF register). */
 600         u32 dspaddr_offset;
 601         int adjusted_x;
 602         int adjusted_y;
 603
 604         uint32_t cursor_addr;
 605         uint32_t cursor_cntl;
 606         uint32_t cursor_size;
 607         uint32_t cursor_base;
 608
 609         struct intel_crtc_state *config;
 610
 611         /* reset counter value when the last flip was submitted */
 612         unsigned int reset_counter;
 613
 614         /* Access to these should be protected by dev_priv->irq_lock. */
 615         bool cpu_fifo_underrun_disabled;
 616         bool pch_fifo_underrun_disabled;
 617
 618         /* per-pipe watermark state */
 619         struct {
 620                 /* watermarks currently being used  */
 621                 union {
 622                         struct intel_pipe_wm ilk;
 623                         struct skl_pipe_wm skl;
 624                 } active;
 625
 626                 /* allow CxSR on this pipe */
 627                 bool cxsr_allowed;
 628         } wm;
 629
 630         int scanline_offset;
 631
 632         struct {
 633                 unsigned start_vbl_count;
 634                 ktime_t start_vbl_time;
 635                 int min_vbl, max_vbl;
 636                 int scanline_start;
 637         } debug;
 638
 639         struct intel_crtc_atomic_commit atomic;
 640
 641         /* scalers available on this crtc */
 642         int num_scalers;
 643
 644         struct vlv_wm_state wm_state;
 645 };
 646
 647 struct intel_plane_wm_parameters {
 648         uint32_t horiz_pixels;
 649         uint32_t vert_pixels;
 650         /*
 651          *   For packed pixel formats:
 652          *     bytes_per_pixel - holds bytes per pixel
 653          *   For planar pixel formats:
 654          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 655          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 656          */
 657         uint8_t bytes_per_pixel;
 658         uint8_t y_bytes_per_pixel;
 659         bool enabled;
 660         bool scaled;
 661         u64 tiling;
 662         unsigned int rotation;
 663         uint16_t fifo_size;
 664 };
 665
 666 struct intel_plane {
 667         struct drm_plane base;
 668         int plane;
 669         enum pipe pipe;
 670         bool can_scale;
 671         int max_downscale;
 672         uint32_t frontbuffer_bit;
 673
 674         /* Since we need to change the watermarks before/after
 675          * enabling/disabling the planes, we need to store the parameters here
 676          * as the other pieces of the struct may not reflect the values we want
 677          * for the watermark calculations. Currently only Haswell uses this.
 678          */
 679         struct intel_plane_wm_parameters wm;
 680
 681         /*
 682          * NOTE: Do not place new plane state fields here (e.g., when adding
 683          * new plane properties).  New runtime state should now be placed in
 684          * the intel_plane_state structure and accessed via plane_state.
 685          */
 686
 687         void (*update_plane)(struct drm_plane *plane,
 688                              const struct intel_crtc_state *crtc_state,
 689                              const struct intel_plane_state *plane_state);
 690         void (*disable_plane)(struct drm_plane *plane,
 691                               struct drm_crtc *crtc);
 692         int (*check_plane)(struct drm_plane *plane,
 693                            struct intel_crtc_state *crtc_state,
 694                            struct intel_plane_state *state);
 695 };
 696
 697 struct intel_watermark_params {
 698         unsigned long fifo_size;
 699         unsigned long max_wm;
 700         unsigned long default_wm;
 701         unsigned long guard_size;
 702         unsigned long cacheline_size;
 703 };
 704
 705 struct cxsr_latency {
 706         int is_desktop;
 707         int is_ddr3;
 708         unsigned long fsb_freq;
 709         unsigned long mem_freq;
 710         unsigned long display_sr;
 711         unsigned long display_hpll_disable;
 712         unsigned long cursor_sr;
 713         unsigned long cursor_hpll_disable;
 714 };
 715
 716 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 717 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 718 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 719 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 720 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 721 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 722 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 723 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 724 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 725
 726 struct intel_hdmi {
 727         i915_reg_t hdmi_reg;
 728         int ddc_bus;
 729         bool limited_color_range;
 730         bool color_range_auto;
 731         bool has_hdmi_sink;
 732         bool has_audio;
 733         enum hdmi_force_audio force_audio;
 734         bool rgb_quant_range_selectable;
 735         enum hdmi_picture_aspect aspect_ratio;
 736         struct intel_connector *attached_connector;
 737         void (*write_infoframe)(struct drm_encoder *encoder,
 738                                 enum hdmi_infoframe_type type,
 739                                 const void *frame, ssize_t len);
 740         void (*set_infoframes)(struct drm_encoder *encoder,
 741                                bool enable,
 742                                const struct drm_display_mode *adjusted_mode);
 743         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 744                                   const struct intel_crtc_state *pipe_config);
 745 };
 746
 747 struct intel_dp_mst_encoder;
 748 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 749
 750 /*
 751  * enum link_m_n_set:
 752  *      When platform provides two set of M_N registers for dp, we can
 753  *      program them and switch between them incase of DRRS.
 754  *      But When only one such register is provided, we have to program the
 755  *      required divider value on that registers itself based on the DRRS state.
 756  *
 757  * M1_N1        : Program dp_m_n on M1_N1 registers
 758  *                        dp_m2_n2 on M2_N2 registers (If supported)
 759  *
 760  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 761  *                        M2_N2 registers are not supported
 762  */
 763
 764 enum link_m_n_set {
 765         /* Sets the m1_n1 and m2_n2 */
 766         M1_N1 = 0,
 767         M2_N2
 768 };
 769
 770 struct intel_dp {
 771         i915_reg_t output_reg;
 772         i915_reg_t aux_ch_ctl_reg;
 773         i915_reg_t aux_ch_data_reg[5];
 774         uint32_t DP;
 775         int link_rate;
 776         uint8_t lane_count;
 777         bool has_audio;
 778         enum hdmi_force_audio force_audio;
 779         bool limited_color_range;
 780         bool color_range_auto;
 781         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 782         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 783         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 784         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 785         uint8_t num_sink_rates;
 786         int sink_rates[DP_MAX_SUPPORTED_RATES];
 787         struct drm_dp_aux aux;
 788         uint8_t train_set[4];
 789         int panel_power_up_delay;
 790         int panel_power_down_delay;
 791         int panel_power_cycle_delay;
 792         int backlight_on_delay;
 793         int backlight_off_delay;
 794         struct delayed_work panel_vdd_work;
 795         bool want_panel_vdd;
 796         unsigned long last_power_on;
 797         unsigned long last_backlight_off;
 798         ktime_t panel_power_off_time;
 799
 800         struct notifier_block edp_notifier;
 801
 802         /*
 803          * Pipe whose power sequencer is currently locked into
 804          * this port. Only relevant on VLV/CHV.
 805          */
 806         enum pipe pps_pipe;
 807         struct edp_power_seq pps_delays;
 808
 809         bool can_mst; /* this port supports mst */
 810         bool is_mst;
 811         int active_mst_links;
 812         /* connector directly attached - won't be use for modeset in mst world */
 813         struct intel_connector *attached_connector;
 814
 815         /* mst connector list */
 816         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 817         struct drm_dp_mst_topology_mgr mst_mgr;
 818
 819         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 820         /*
 821          * This function returns the value we have to program the AUX_CTL
 822          * register with to kick off an AUX transaction.
 823          */
 824         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 825                                      bool has_aux_irq,
 826                                      int send_bytes,
 827                                      uint32_t aux_clock_divider);
 828
 829         /* This is called before a link training is starterd */
 830         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 831
 832         bool train_set_valid;
 833
 834         /* Displayport compliance testing */
 835         unsigned long compliance_test_type;
 836         unsigned long compliance_test_data;
 837         bool compliance_test_active;
 838 };
 839
 840 struct intel_digital_port {
 841         struct intel_encoder base;
 842         enum port port;
 843         u32 saved_port_bits;
 844         struct intel_dp dp;
 845         struct intel_hdmi hdmi;
 846         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 847         bool release_cl2_override;
 848         uint8_t max_lanes;
 849         /* for communication with audio component; protected by av_mutex */
 850         const struct drm_connector *audio_connector;
 851 };
 852
 853 struct intel_dp_mst_encoder {
 854         struct intel_encoder base;
 855         enum pipe pipe;
 856         struct intel_digital_port *primary;
 857         void *port; /* store this opaque as its illegal to dereference it */
 858 };
 859
 860 static inline enum dpio_channel
 861 vlv_dport_to_channel(struct intel_digital_port *dport)
 862 {
 863         switch (dport->port) {
 864         case PORT_B:
 865         case PORT_D:
 866                 return DPIO_CH0;
 867         case PORT_C:
 868                 return DPIO_CH1;
 869         default:
 870                 BUG();
 871         }
 872 }
 873
 874 static inline enum dpio_phy
 875 vlv_dport_to_phy(struct intel_digital_port *dport)
 876 {
 877         switch (dport->port) {
 878         case PORT_B:
 879         case PORT_C:
 880                 return DPIO_PHY0;
 881         case PORT_D:
 882                 return DPIO_PHY1;
 883         default:
 884                 BUG();
 885         }
 886 }
 887
 888 static inline enum dpio_channel
 889 vlv_pipe_to_channel(enum pipe pipe)
 890 {
 891         switch (pipe) {
 892         case PIPE_A:
 893         case PIPE_C:
 894                 return DPIO_CH0;
 895         case PIPE_B:
 896                 return DPIO_CH1;
 897         default:
 898                 BUG();
 899         }
 900 }
 901
 902 static inline struct drm_crtc *
 903 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 904 {
 905         struct drm_i915_private *dev_priv = dev->dev_private;
 906         return dev_priv->pipe_to_crtc_mapping[pipe];
 907 }
 908
 909 static inline struct drm_crtc *
 910 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         return dev_priv->plane_to_crtc_mapping[plane];
 914 }
 915
 916 struct intel_unpin_work {
 917         struct work_struct work;
 918         struct drm_crtc *crtc;
 919         struct drm_framebuffer *old_fb;
 920         struct drm_i915_gem_object *pending_flip_obj;
 921         struct drm_pending_vblank_event *event;
 922         atomic_t pending;
 923 #define INTEL_FLIP_INACTIVE     0
 924 #define INTEL_FLIP_PENDING      1
 925 #define INTEL_FLIP_COMPLETE     2
 926         u32 flip_count;
 927         u32 gtt_offset;
 928         struct drm_i915_gem_request *flip_queued_req;
 929         u32 flip_queued_vblank;
 930         u32 flip_ready_vblank;
 931         bool enable_stall_check;
 932 };
 933
 934 struct intel_load_detect_pipe {
 935         struct drm_atomic_state *restore_state;
 936 };
 937
 938 static inline struct intel_encoder *
 939 intel_attached_encoder(struct drm_connector *connector)
 940 {
 941         return to_intel_connector(connector)->encoder;
 942 }
 943
 944 static inline struct intel_digital_port *
 945 enc_to_dig_port(struct drm_encoder *encoder)
 946 {
 947         return container_of(encoder, struct intel_digital_port, base.base);
 948 }
 949
 950 static inline struct intel_dp_mst_encoder *
 951 enc_to_mst(struct drm_encoder *encoder)
 952 {
 953         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 954 }
 955
 956 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 957 {
 958         return &enc_to_dig_port(encoder)->dp;
 959 }
 960
 961 static inline struct intel_digital_port *
 962 dp_to_dig_port(struct intel_dp *intel_dp)
 963 {
 964         return container_of(intel_dp, struct intel_digital_port, dp);
 965 }
 966
 967 static inline struct intel_digital_port *
 968 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 969 {
 970         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 971 }
 972
 973 /*
 974  * Returns the number of planes for this pipe, ie the number of sprites + 1
 975  * (primary plane). This doesn't count the cursor plane then.
 976  */
 977 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 978 {
 979         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 980 }
 981
 982 /* intel_fifo_underrun.c */
 983 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 984                                            enum pipe pipe, bool enable);
 985 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 986                                            enum transcoder pch_transcoder,
 987                                            bool enable);
 988 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 989                                          enum pipe pipe);
 990 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 991                                          enum transcoder pch_transcoder);
 992 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 993 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 994
 995 /* i915_irq.c */
 996 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 997 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 998 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 999 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1000 void gen6_reset_rps_interrupts(struct drm_device *dev);
1001 void gen6_enable_rps_interrupts(struct drm_device *dev);
1002 void gen6_disable_rps_interrupts(struct drm_device *dev);
1003 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1004 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1005 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1006 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1007 {
1008         /*
1009          * We only use drm_irq_uninstall() at unload and VT switch, so
1010          * this is the only thing we need to check.
1011          */
1012         return dev_priv->pm.irqs_enabled;
1013 }
1014
1015 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1016 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1017                                      unsigned int pipe_mask);
1018 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1019                                      unsigned int pipe_mask);
1020
1021 /* intel_crt.c */
1022 void intel_crt_init(struct drm_device *dev);
1023
1024
1025 /* intel_ddi.c */
1026 void intel_ddi_clk_select(struct intel_encoder *encoder,
1027                           const struct intel_crtc_state *pipe_config);
1028 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1029 void hsw_fdi_link_train(struct drm_crtc *crtc);
1030 void intel_ddi_init(struct drm_device *dev, enum port port);
1031 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1032 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1033 void intel_ddi_pll_init(struct drm_device *dev);
1034 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1035 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1036                                        enum transcoder cpu_transcoder);
1037 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1038 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1039 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1040                           struct intel_crtc_state *crtc_state);
1041 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1042 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1043 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1044 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1045 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1046                                  struct intel_crtc *intel_crtc);
1047 void intel_ddi_get_config(struct intel_encoder *encoder,
1048                           struct intel_crtc_state *pipe_config);
1049 struct intel_encoder *
1050 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1051
1052 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1053 void intel_ddi_clock_get(struct intel_encoder *encoder,
1054                          struct intel_crtc_state *pipe_config);
1055 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1056 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1057
1058 /* intel_frontbuffer.c */
1059 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1060                              enum fb_op_origin origin);
1061 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1062                                     unsigned frontbuffer_bits);
1063 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1064                                      unsigned frontbuffer_bits);
1065 void intel_frontbuffer_flip(struct drm_device *dev,
1066                             unsigned frontbuffer_bits);
1067 unsigned int intel_fb_align_height(struct drm_device *dev,
1068                                    unsigned int height,
1069                                    uint32_t pixel_format,
1070                                    uint64_t fb_format_modifier);
1071 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1072                         enum fb_op_origin origin);
1073 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1074                               uint64_t fb_modifier, uint32_t pixel_format);
1075
1076 /* intel_audio.c */
1077 void intel_init_audio(struct drm_device *dev);
1078 void intel_audio_codec_enable(struct intel_encoder *encoder);
1079 void intel_audio_codec_disable(struct intel_encoder *encoder);
1080 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1081 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1082
1083 /* intel_display.c */
1084 extern const struct drm_plane_funcs intel_plane_funcs;
1085 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1086 int intel_pch_rawclk(struct drm_device *dev);
1087 int intel_hrawclk(struct drm_device *dev);
1088 void intel_mark_busy(struct drm_device *dev);
1089 void intel_mark_idle(struct drm_device *dev);
1090 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1091 int intel_display_suspend(struct drm_device *dev);
1092 void intel_encoder_destroy(struct drm_encoder *encoder);
1093 int intel_connector_init(struct intel_connector *);
1094 struct intel_connector *intel_connector_alloc(void);
1095 bool intel_connector_get_hw_state(struct intel_connector *connector);
1096 void intel_connector_attach_encoder(struct intel_connector *connector,
1097                                     struct intel_encoder *encoder);
1098 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1099 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1100                                              struct drm_crtc *crtc);
1101 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1102 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1103                                 struct drm_file *file_priv);
1104 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1105                                              enum pipe pipe);
1106 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1107 static inline void
1108 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1109 {
1110         drm_wait_one_vblank(dev, pipe);
1111 }
1112 static inline void
1113 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1114 {
1115         const struct intel_crtc *crtc =
1116                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1117
1118         if (crtc->active)
1119                 intel_wait_for_vblank(dev, pipe);
1120 }
1121 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1122 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1123                          struct intel_digital_port *dport,
1124                          unsigned int expected_mask);
1125 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1126                                 struct drm_display_mode *mode,
1127                                 struct intel_load_detect_pipe *old,
1128                                 struct drm_modeset_acquire_ctx *ctx);
1129 void intel_release_load_detect_pipe(struct drm_connector *connector,
1130                                     struct intel_load_detect_pipe *old,
1131                                     struct drm_modeset_acquire_ctx *ctx);
1132 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1133                                unsigned int rotation);
1134 struct drm_framebuffer *
1135 __intel_framebuffer_create(struct drm_device *dev,
1136                            struct drm_mode_fb_cmd2 *mode_cmd,
1137                            struct drm_i915_gem_object *obj);
1138 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1139 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1140 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1141 void intel_check_page_flip(struct drm_device *dev, int pipe);
1142 int intel_prepare_plane_fb(struct drm_plane *plane,
1143                            const struct drm_plane_state *new_state);
1144 void intel_cleanup_plane_fb(struct drm_plane *plane,
1145                             const struct drm_plane_state *old_state);
1146 int intel_plane_atomic_get_property(struct drm_plane *plane,
1147                                     const struct drm_plane_state *state,
1148                                     struct drm_property *property,
1149                                     uint64_t *val);
1150 int intel_plane_atomic_set_property(struct drm_plane *plane,
1151                                     struct drm_plane_state *state,
1152                                     struct drm_property *property,
1153                                     uint64_t val);
1154 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1155                                     struct drm_plane_state *plane_state);
1156
1157 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1158                                uint64_t fb_modifier, unsigned int cpp);
1159
1160 static inline bool
1161 intel_rotation_90_or_270(unsigned int rotation)
1162 {
1163         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1164 }
1165
1166 void intel_create_rotation_property(struct drm_device *dev,
1167                                         struct intel_plane *plane);
1168
1169 /* shared dpll functions */
1170 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1171 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1172                         struct intel_shared_dpll *pll,
1173                         bool state);
1174 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1175 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1176 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1177                                                 struct intel_crtc_state *state);
1178
1179 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1180                      const struct dpll *dpll);
1181 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1182
1183 /* modesetting asserts */
1184 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185                            enum pipe pipe);
1186 void assert_pll(struct drm_i915_private *dev_priv,
1187                 enum pipe pipe, bool state);
1188 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1189 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1190 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1191                        enum pipe pipe, bool state);
1192 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1193 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1194 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1195 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1196 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1197 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
1198                               int *x, int *y,
1199                               uint64_t fb_modifier,
1200                               unsigned int cpp,
1201                               unsigned int pitch,
1202                               unsigned int rotation);
1203 void intel_prepare_reset(struct drm_device *dev);
1204 void intel_finish_reset(struct drm_device *dev);
1205 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1206 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1207 void broxton_init_cdclk(struct drm_device *dev);
1208 void broxton_uninit_cdclk(struct drm_device *dev);
1209 void broxton_ddi_phy_init(struct drm_device *dev);
1210 void broxton_ddi_phy_uninit(struct drm_device *dev);
1211 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1212 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1213 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1214 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1215 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1216 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1217 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1218 void intel_dp_get_m_n(struct intel_crtc *crtc,
1219                       struct intel_crtc_state *pipe_config);
1220 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1221 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1222 void
1223 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1224                                 int dotclock);
1225 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1226                         intel_clock_t *best_clock);
1227 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1228
1229 bool intel_crtc_active(struct drm_crtc *crtc);
1230 void hsw_enable_ips(struct intel_crtc *crtc);
1231 void hsw_disable_ips(struct intel_crtc *crtc);
1232 enum intel_display_power_domain
1233 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1234 enum intel_display_power_domain
1235 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1236 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1237                                  struct intel_crtc_state *pipe_config);
1238
1239 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1240 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1241
1242 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1243                            struct drm_i915_gem_object *obj,
1244                            unsigned int plane);
1245
1246 u32 skl_plane_ctl_format(uint32_t pixel_format);
1247 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1248 u32 skl_plane_ctl_rotation(unsigned int rotation);
1249
1250 /* intel_csr.c */
1251 void intel_csr_ucode_init(struct drm_i915_private *);
1252 bool intel_csr_load_program(struct drm_i915_private *);
1253 void intel_csr_ucode_fini(struct drm_i915_private *);
1254
1255 /* intel_dp.c */
1256 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1257 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1258                              struct intel_connector *intel_connector);
1259 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1260                               const struct intel_crtc_state *pipe_config);
1261 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1262 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1263 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1264 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1265 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1266 bool intel_dp_compute_config(struct intel_encoder *encoder,
1267                              struct intel_crtc_state *pipe_config);
1268 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1269 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1270                                   bool long_hpd);
1271 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1272 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1273 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1274 void intel_edp_panel_on(struct intel_dp *intel_dp);
1275 void intel_edp_panel_off(struct intel_dp *intel_dp);
1276 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1277 void intel_dp_mst_suspend(struct drm_device *dev);
1278 void intel_dp_mst_resume(struct drm_device *dev);
1279 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1280 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1281 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1282 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1283 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1284 void intel_plane_destroy(struct drm_plane *plane);
1285 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1286 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1287 void intel_edp_drrs_invalidate(struct drm_device *dev,
1288                 unsigned frontbuffer_bits);
1289 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1290 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1291                                          struct intel_digital_port *port);
1292 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1293
1294 void
1295 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1296                                        uint8_t dp_train_pat);
1297 void
1298 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1299 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1300 uint8_t
1301 intel_dp_voltage_max(struct intel_dp *intel_dp);
1302 uint8_t
1303 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1304 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1305                            uint8_t *link_bw, uint8_t *rate_select);
1306 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1307 bool
1308 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1309
1310 /* intel_dp_mst.c */
1311 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1312 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1313 /* intel_dsi.c */
1314 void intel_dsi_init(struct drm_device *dev);
1315
1316
1317 /* intel_dvo.c */
1318 void intel_dvo_init(struct drm_device *dev);
1319
1320
1321 /* legacy fbdev emulation in intel_fbdev.c */
1322 #ifdef CONFIG_DRM_FBDEV_EMULATION
1323 extern int intel_fbdev_init(struct drm_device *dev);
1324 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1325 extern void intel_fbdev_fini(struct drm_device *dev);
1326 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1327 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1328 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1329 #else
1330 static inline int intel_fbdev_init(struct drm_device *dev)
1331 {
1332         return 0;
1333 }
1334
1335 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1336 {
1337 }
1338
1339 static inline void intel_fbdev_fini(struct drm_device *dev)
1340 {
1341 }
1342
1343 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1344 {
1345 }
1346
1347 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1348 {
1349 }
1350 #endif
1351
1352 /* intel_fbc.c */
1353 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1354                            struct drm_atomic_state *state);
1355 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1356 void intel_fbc_pre_update(struct intel_crtc *crtc);
1357 void intel_fbc_post_update(struct intel_crtc *crtc);
1358 void intel_fbc_init(struct drm_i915_private *dev_priv);
1359 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1360 void intel_fbc_enable(struct intel_crtc *crtc);
1361 void intel_fbc_disable(struct intel_crtc *crtc);
1362 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1363 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1364                           unsigned int frontbuffer_bits,
1365                           enum fb_op_origin origin);
1366 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1367                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1368 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1369
1370 /* intel_hdmi.c */
1371 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1372 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1373                                struct intel_connector *intel_connector);
1374 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1375 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1376                                struct intel_crtc_state *pipe_config);
1377
1378
1379 /* intel_lvds.c */
1380 void intel_lvds_init(struct drm_device *dev);
1381 bool intel_is_dual_link_lvds(struct drm_device *dev);
1382
1383
1384 /* intel_modes.c */
1385 int intel_connector_update_modes(struct drm_connector *connector,
1386                                  struct edid *edid);
1387 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1388 void intel_attach_force_audio_property(struct drm_connector *connector);
1389 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1390 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1391
1392
1393 /* intel_overlay.c */
1394 void intel_setup_overlay(struct drm_device *dev);
1395 void intel_cleanup_overlay(struct drm_device *dev);
1396 int intel_overlay_switch_off(struct intel_overlay *overlay);
1397 int intel_overlay_put_image(struct drm_device *dev, void *data,
1398                             struct drm_file *file_priv);
1399 int intel_overlay_attrs(struct drm_device *dev, void *data,
1400                         struct drm_file *file_priv);
1401 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1402
1403
1404 /* intel_panel.c */
1405 int intel_panel_init(struct intel_panel *panel,
1406                      struct drm_display_mode *fixed_mode,
1407                      struct drm_display_mode *downclock_mode);
1408 void intel_panel_fini(struct intel_panel *panel);
1409 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1410                             struct drm_display_mode *adjusted_mode);
1411 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1412                              struct intel_crtc_state *pipe_config,
1413                              int fitting_mode);
1414 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1415                               struct intel_crtc_state *pipe_config,
1416                               int fitting_mode);
1417 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1418                                     u32 level, u32 max);
1419 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1420 void intel_panel_enable_backlight(struct intel_connector *connector);
1421 void intel_panel_disable_backlight(struct intel_connector *connector);
1422 void intel_panel_destroy_backlight(struct drm_connector *connector);
1423 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1424 extern struct drm_display_mode *intel_find_panel_downclock(
1425                                 struct drm_device *dev,
1426                                 struct drm_display_mode *fixed_mode,
1427                                 struct drm_connector *connector);
1428 void intel_backlight_register(struct drm_device *dev);
1429 void intel_backlight_unregister(struct drm_device *dev);
1430
1431
1432 /* intel_psr.c */
1433 void intel_psr_enable(struct intel_dp *intel_dp);
1434 void intel_psr_disable(struct intel_dp *intel_dp);
1435 void intel_psr_invalidate(struct drm_device *dev,
1436                           unsigned frontbuffer_bits);
1437 void intel_psr_flush(struct drm_device *dev,
1438                      unsigned frontbuffer_bits,
1439                      enum fb_op_origin origin);
1440 void intel_psr_init(struct drm_device *dev);
1441 void intel_psr_single_frame_update(struct drm_device *dev,
1442                                    unsigned frontbuffer_bits);
1443
1444 /* intel_runtime_pm.c */
1445 int intel_power_domains_init(struct drm_i915_private *);
1446 void intel_power_domains_fini(struct drm_i915_private *);
1447 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1448 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1449 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1450 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1451 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1452 const char *
1453 intel_display_power_domain_str(enum intel_display_power_domain domain);
1454
1455 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1456                                     enum intel_display_power_domain domain);
1457 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1458                                       enum intel_display_power_domain domain);
1459 void intel_display_power_get(struct drm_i915_private *dev_priv,
1460                              enum intel_display_power_domain domain);
1461 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1462                                         enum intel_display_power_domain domain);
1463 void intel_display_power_put(struct drm_i915_private *dev_priv,
1464                              enum intel_display_power_domain domain);
1465
1466 static inline void
1467 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1468 {
1469         WARN_ONCE(dev_priv->pm.suspended,
1470                   "Device suspended during HW access\n");
1471 }
1472
1473 static inline void
1474 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1475 {
1476         assert_rpm_device_not_suspended(dev_priv);
1477         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1478          * too much noise. */
1479         if (!atomic_read(&dev_priv->pm.wakeref_count))
1480                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1481 }
1482
1483 static inline int
1484 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1485 {
1486         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1487
1488         assert_rpm_wakelock_held(dev_priv);
1489
1490         return seq;
1491 }
1492
1493 static inline void
1494 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1495 {
1496         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1497                   "HW access outside of RPM atomic section\n");
1498 }
1499
1500 /**
1501  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1502  * @dev_priv: i915 device instance
1503  *
1504  * This function disable asserts that check if we hold an RPM wakelock
1505  * reference, while keeping the device-not-suspended checks still enabled.
1506  * It's meant to be used only in special circumstances where our rule about
1507  * the wakelock refcount wrt. the device power state doesn't hold. According
1508  * to this rule at any point where we access the HW or want to keep the HW in
1509  * an active state we must hold an RPM wakelock reference acquired via one of
1510  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1511  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1512  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1513  * users should avoid using this function.
1514  *
1515  * Any calls to this function must have a symmetric call to
1516  * enable_rpm_wakeref_asserts().
1517  */
1518 static inline void
1519 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1520 {
1521         atomic_inc(&dev_priv->pm.wakeref_count);
1522 }
1523
1524 /**
1525  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1526  * @dev_priv: i915 device instance
1527  *
1528  * This function re-enables the RPM assert checks after disabling them with
1529  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1530  * circumstances otherwise its use should be avoided.
1531  *
1532  * Any calls to this function must have a symmetric call to
1533  * disable_rpm_wakeref_asserts().
1534  */
1535 static inline void
1536 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1537 {
1538         atomic_dec(&dev_priv->pm.wakeref_count);
1539 }
1540
1541 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1542 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
1543         disable_rpm_wakeref_asserts(dev_priv)
1544
1545 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
1546         enable_rpm_wakeref_asserts(dev_priv)
1547
1548 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1549 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1550 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1551 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1552
1553 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1554
1555 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1556                              bool override, unsigned int mask);
1557 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1558                           enum dpio_channel ch, bool override);
1559
1560
1561 /* intel_pm.c */
1562 void intel_init_clock_gating(struct drm_device *dev);
1563 void intel_suspend_hw(struct drm_device *dev);
1564 int ilk_wm_max_level(const struct drm_device *dev);
1565 void intel_update_watermarks(struct drm_crtc *crtc);
1566 void intel_init_pm(struct drm_device *dev);
1567 void intel_pm_setup(struct drm_device *dev);
1568 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1569 void intel_gpu_ips_teardown(void);
1570 void intel_init_gt_powersave(struct drm_device *dev);
1571 void intel_cleanup_gt_powersave(struct drm_device *dev);
1572 void intel_enable_gt_powersave(struct drm_device *dev);
1573 void intel_disable_gt_powersave(struct drm_device *dev);
1574 void intel_suspend_gt_powersave(struct drm_device *dev);
1575 void intel_reset_gt_powersave(struct drm_device *dev);
1576 void gen6_update_ring_freq(struct drm_device *dev);
1577 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1578 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1579 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1580 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1581                     struct intel_rps_client *rps,
1582                     unsigned long submitted);
1583 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1584                                        struct drm_i915_gem_request *req);
1585 void vlv_wm_get_hw_state(struct drm_device *dev);
1586 void ilk_wm_get_hw_state(struct drm_device *dev);
1587 void skl_wm_get_hw_state(struct drm_device *dev);
1588 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1589                           struct skl_ddb_allocation *ddb /* out */);
1590 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1591 bool ilk_disable_lp_wm(struct drm_device *dev);
1592 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
1593
1594 /* intel_sdvo.c */
1595 bool intel_sdvo_init(struct drm_device *dev,
1596                      i915_reg_t reg, enum port port);
1597
1598
1599 /* intel_sprite.c */
1600 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1601 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1602                               struct drm_file *file_priv);
1603 void intel_pipe_update_start(struct intel_crtc *crtc);
1604 void intel_pipe_update_end(struct intel_crtc *crtc);
1605
1606 /* intel_tv.c */
1607 void intel_tv_init(struct drm_device *dev);
1608
1609 /* intel_atomic.c */
1610 int intel_connector_atomic_get_property(struct drm_connector *connector,
1611                                         const struct drm_connector_state *state,
1612                                         struct drm_property *property,
1613                                         uint64_t *val);
1614 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1615 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1616                                struct drm_crtc_state *state);
1617 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1618 void intel_atomic_state_clear(struct drm_atomic_state *);
1619 struct intel_shared_dpll_config *
1620 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1621
1622 static inline struct intel_crtc_state *
1623 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1624                             struct intel_crtc *crtc)
1625 {
1626         struct drm_crtc_state *crtc_state;
1627         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1628         if (IS_ERR(crtc_state))
1629                 return ERR_CAST(crtc_state);
1630
1631         return to_intel_crtc_state(crtc_state);
1632 }
1633 int intel_atomic_setup_scalers(struct drm_device *dev,
1634         struct intel_crtc *intel_crtc,
1635         struct intel_crtc_state *crtc_state);
1636
1637 /* intel_atomic_plane.c */
1638 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1639 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1640 void intel_plane_destroy_state(struct drm_plane *plane,
1641                                struct drm_plane_state *state);
1642 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1643
1644 #endif /* __INTEL_DRV_H__ */