drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000*x)
  69 #define MHz(x) KHz(1000*x)
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_DSI 9
  96 #define INTEL_OUTPUT_UNKNOWN 10
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 #define INTEL_DSI_COMMAND_MODE  0
 104 #define INTEL_DSI_VIDEO_MODE    1
 105
 106 struct intel_framebuffer {
 107         struct drm_framebuffer base;
 108         struct drm_i915_gem_object *obj;
 109 };
 110
 111 struct intel_fbdev {
 112         struct drm_fb_helper helper;
 113         struct intel_framebuffer ifb;
 114         struct list_head fbdev_list;
 115         struct drm_display_mode *our_mode;
 116 };
 117
 118 struct intel_encoder {
 119         struct drm_encoder base;
 120         /*
 121          * The new crtc this encoder will be driven from. Only differs from
 122          * base->crtc while a modeset is in progress.
 123          */
 124         struct intel_crtc *new_crtc;
 125
 126         int type;
 127         /*
 128          * Intel hw has only one MUX where encoders could be clone, hence a
 129          * simple flag is enough to compute the possible_clones mask.
 130          */
 131         bool cloneable;
 132         bool connectors_active;
 133         void (*hot_plug)(struct intel_encoder *);
 134         bool (*compute_config)(struct intel_encoder *,
 135                                struct intel_crtc_config *);
 136         void (*pre_pll_enable)(struct intel_encoder *);
 137         void (*pre_enable)(struct intel_encoder *);
 138         void (*enable)(struct intel_encoder *);
 139         void (*mode_set)(struct intel_encoder *intel_encoder);
 140         void (*disable)(struct intel_encoder *);
 141         void (*post_disable)(struct intel_encoder *);
 142         /* Read out the current hw state of this connector, returning true if
 143          * the encoder is active. If the encoder is enabled it also set the pipe
 144          * it is connected to in the pipe parameter. */
 145         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 146         /* Reconstructs the equivalent mode flags for the current hardware
 147          * state. This must be called _after_ display->get_pipe_config has
 148          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 149          * be set correctly before calling this function. */
 150         void (*get_config)(struct intel_encoder *,
 151                            struct intel_crtc_config *pipe_config);
 152         int crtc_mask;
 153         enum hpd_pin hpd_pin;
 154 };
 155
 156 struct intel_panel {
 157         struct drm_display_mode *fixed_mode;
 158         int fitting_mode;
 159 };
 160
 161 struct intel_connector {
 162         struct drm_connector base;
 163         /*
 164          * The fixed encoder this connector is connected to.
 165          */
 166         struct intel_encoder *encoder;
 167
 168         /*
 169          * The new encoder this connector will be driven. Only differs from
 170          * encoder while a modeset is in progress.
 171          */
 172         struct intel_encoder *new_encoder;
 173
 174         /* Reads out the current hw, returning true if the connector is enabled
 175          * and active (i.e. dpms ON state). */
 176         bool (*get_hw_state)(struct intel_connector *);
 177
 178         /* Panel info for eDP and LVDS */
 179         struct intel_panel panel;
 180
 181         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 182         struct edid *edid;
 183
 184         /* since POLL and HPD connectors may use the same HPD line keep the native
 185            state of connector->polled in case hotplug storm detection changes it */
 186         u8 polled;
 187 };
 188
 189 typedef struct dpll {
 190         /* given values */
 191         int n;
 192         int m1, m2;
 193         int p1, p2;
 194         /* derived values */
 195         int     dot;
 196         int     vco;
 197         int     m;
 198         int     p;
 199 } intel_clock_t;
 200
 201 struct intel_crtc_config {
 202         /**
 203          * quirks - bitfield with hw state readout quirks
 204          *
 205          * For various reasons the hw state readout code might not be able to
 206          * completely faithfully read out the current state. These cases are
 207          * tracked with quirk flags so that fastboot and state checker can act
 208          * accordingly.
 209          */
 210 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 211         unsigned long quirks;
 212
 213         /* User requested mode, only valid as a starting point to
 214          * compute adjusted_mode, except in the case of (S)DVO where
 215          * it's also for the output timings of the (S)DVO chip.
 216          * adjusted_mode will then correspond to the S(DVO) chip's
 217          * preferred input timings. */
 218         struct drm_display_mode requested_mode;
 219         /* Actual pipe timings ie. what we program into the pipe timing
 220          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 221         struct drm_display_mode adjusted_mode;
 222
 223         /* Pipe source size (ie. panel fitter input size)
 224          * All planes will be positioned inside this space,
 225          * and get clipped at the edges. */
 226         int pipe_src_w, pipe_src_h;
 227
 228         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 229          * between pch encoders and cpu encoders. */
 230         bool has_pch_encoder;
 231
 232         /* CPU Transcoder for the pipe. Currently this can only differ from the
 233          * pipe on Haswell (where we have a special eDP transcoder). */
 234         enum transcoder cpu_transcoder;
 235
 236         /*
 237          * Use reduced/limited/broadcast rbg range, compressing from the full
 238          * range fed into the crtcs.
 239          */
 240         bool limited_color_range;
 241
 242         /* DP has a bunch of special case unfortunately, so mark the pipe
 243          * accordingly. */
 244         bool has_dp_encoder;
 245
 246         /*
 247          * Enable dithering, used when the selected pipe bpp doesn't match the
 248          * plane bpp.
 249          */
 250         bool dither;
 251
 252         /* Controls for the clock computation, to override various stages. */
 253         bool clock_set;
 254
 255         /* SDVO TV has a bunch of special case. To make multifunction encoders
 256          * work correctly, we need to track this at runtime.*/
 257         bool sdvo_tv_clock;
 258
 259         /*
 260          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 261          * required. This is set in the 2nd loop of calling encoder's
 262          * ->compute_config if the first pick doesn't work out.
 263          */
 264         bool bw_constrained;
 265
 266         /* Settings for the intel dpll used on pretty much everything but
 267          * haswell. */
 268         struct dpll dpll;
 269
 270         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 271         enum intel_dpll_id shared_dpll;
 272
 273         /* Actual register state of the dpll, for shared dpll cross-checking. */
 274         struct intel_dpll_hw_state dpll_hw_state;
 275
 276         int pipe_bpp;
 277         struct intel_link_m_n dp_m_n;
 278
 279         /*
 280          * Frequence the dpll for the port should run at. Differs from the
 281          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 282          * already multiplied by pixel_multiplier.
 283          */
 284         int port_clock;
 285
 286         /* Used by SDVO (and if we ever fix it, HDMI). */
 287         unsigned pixel_multiplier;
 288
 289         /* Panel fitter controls for gen2-gen4 + VLV */
 290         struct {
 291                 u32 control;
 292                 u32 pgm_ratios;
 293                 u32 lvds_border_bits;
 294         } gmch_pfit;
 295
 296         /* Panel fitter placement and size for Ironlake+ */
 297         struct {
 298                 u32 pos;
 299                 u32 size;
 300                 bool enabled;
 301         } pch_pfit;
 302
 303         /* FDI configuration, only valid if has_pch_encoder is set. */
 304         int fdi_lanes;
 305         struct intel_link_m_n fdi_m_n;
 306
 307         bool ips_enabled;
 308
 309         bool double_wide;
 310 };
 311
 312 struct intel_crtc {
 313         struct drm_crtc base;
 314         enum pipe pipe;
 315         enum plane plane;
 316         u8 lut_r[256], lut_g[256], lut_b[256];
 317         /*
 318          * Whether the crtc and the connected output pipeline is active. Implies
 319          * that crtc->enabled is set, i.e. the current mode configuration has
 320          * some outputs connected to this crtc.
 321          */
 322         bool active;
 323         bool eld_vld;
 324         bool primary_enabled; /* is the primary plane (partially) visible? */
 325         bool lowfreq_avail;
 326         struct intel_overlay *overlay;
 327         struct intel_unpin_work *unpin_work;
 328
 329         atomic_t unpin_work_count;
 330
 331         /* Display surface base address adjustement for pageflips. Note that on
 332          * gen4+ this only adjusts up to a tile, offsets within a tile are
 333          * handled in the hw itself (with the TILEOFF register). */
 334         unsigned long dspaddr_offset;
 335
 336         struct drm_i915_gem_object *cursor_bo;
 337         uint32_t cursor_addr;
 338         int16_t cursor_x, cursor_y;
 339         int16_t cursor_width, cursor_height;
 340         bool cursor_visible;
 341
 342         struct intel_crtc_config config;
 343
 344         uint32_t ddi_pll_sel;
 345
 346         /* reset counter value when the last flip was submitted */
 347         unsigned int reset_counter;
 348
 349         /* Access to these should be protected by dev_priv->irq_lock. */
 350         bool cpu_fifo_underrun_disabled;
 351         bool pch_fifo_underrun_disabled;
 352 };
 353
 354 struct intel_plane_wm_parameters {
 355         uint32_t horiz_pixels;
 356         uint8_t bytes_per_pixel;
 357         bool enabled;
 358         bool scaled;
 359 };
 360
 361 struct intel_plane {
 362         struct drm_plane base;
 363         int plane;
 364         enum pipe pipe;
 365         struct drm_i915_gem_object *obj;
 366         bool can_scale;
 367         int max_downscale;
 368         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 369         int crtc_x, crtc_y;
 370         unsigned int crtc_w, crtc_h;
 371         uint32_t src_x, src_y;
 372         uint32_t src_w, src_h;
 373
 374         /* Since we need to change the watermarks before/after
 375          * enabling/disabling the planes, we need to store the parameters here
 376          * as the other pieces of the struct may not reflect the values we want
 377          * for the watermark calculations. Currently only Haswell uses this.
 378          */
 379         struct intel_plane_wm_parameters wm;
 380
 381         void (*update_plane)(struct drm_plane *plane,
 382                              struct drm_crtc *crtc,
 383                              struct drm_framebuffer *fb,
 384                              struct drm_i915_gem_object *obj,
 385                              int crtc_x, int crtc_y,
 386                              unsigned int crtc_w, unsigned int crtc_h,
 387                              uint32_t x, uint32_t y,
 388                              uint32_t src_w, uint32_t src_h);
 389         void (*disable_plane)(struct drm_plane *plane,
 390                               struct drm_crtc *crtc);
 391         int (*update_colorkey)(struct drm_plane *plane,
 392                                struct drm_intel_sprite_colorkey *key);
 393         void (*get_colorkey)(struct drm_plane *plane,
 394                              struct drm_intel_sprite_colorkey *key);
 395 };
 396
 397 struct intel_watermark_params {
 398         unsigned long fifo_size;
 399         unsigned long max_wm;
 400         unsigned long default_wm;
 401         unsigned long guard_size;
 402         unsigned long cacheline_size;
 403 };
 404
 405 struct cxsr_latency {
 406         int is_desktop;
 407         int is_ddr3;
 408         unsigned long fsb_freq;
 409         unsigned long mem_freq;
 410         unsigned long display_sr;
 411         unsigned long display_hpll_disable;
 412         unsigned long cursor_sr;
 413         unsigned long cursor_hpll_disable;
 414 };
 415
 416 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 417 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 418 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 419 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 420 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 421
 422 struct intel_hdmi {
 423         u32 hdmi_reg;
 424         int ddc_bus;
 425         uint32_t color_range;
 426         bool color_range_auto;
 427         bool has_hdmi_sink;
 428         bool has_audio;
 429         enum hdmi_force_audio force_audio;
 430         bool rgb_quant_range_selectable;
 431         void (*write_infoframe)(struct drm_encoder *encoder,
 432                                 enum hdmi_infoframe_type type,
 433                                 const uint8_t *frame, ssize_t len);
 434         void (*set_infoframes)(struct drm_encoder *encoder,
 435                                struct drm_display_mode *adjusted_mode);
 436 };
 437
 438 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 439
 440 struct intel_dp {
 441         uint32_t output_reg;
 442         uint32_t aux_ch_ctl_reg;
 443         uint32_t DP;
 444         bool has_audio;
 445         enum hdmi_force_audio force_audio;
 446         uint32_t color_range;
 447         bool color_range_auto;
 448         uint8_t link_bw;
 449         uint8_t lane_count;
 450         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 451         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 452         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 453         struct i2c_adapter adapter;
 454         struct i2c_algo_dp_aux_data algo;
 455         uint8_t train_set[4];
 456         int panel_power_up_delay;
 457         int panel_power_down_delay;
 458         int panel_power_cycle_delay;
 459         int backlight_on_delay;
 460         int backlight_off_delay;
 461         struct delayed_work panel_vdd_work;
 462         bool want_panel_vdd;
 463         bool psr_setup_done;
 464         struct intel_connector *attached_connector;
 465 };
 466
 467 struct intel_digital_port {
 468         struct intel_encoder base;
 469         enum port port;
 470         u32 saved_port_bits;
 471         struct intel_dp dp;
 472         struct intel_hdmi hdmi;
 473 };
 474
 475 static inline int
 476 vlv_dport_to_channel(struct intel_digital_port *dport)
 477 {
 478         switch (dport->port) {
 479         case PORT_B:
 480                 return 0;
 481         case PORT_C:
 482                 return 1;
 483         default:
 484                 BUG();
 485         }
 486 }
 487
 488 static inline struct drm_crtc *
 489 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 490 {
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         return dev_priv->pipe_to_crtc_mapping[pipe];
 493 }
 494
 495 static inline struct drm_crtc *
 496 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 497 {
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         return dev_priv->plane_to_crtc_mapping[plane];
 500 }
 501
 502 struct intel_unpin_work {
 503         struct work_struct work;
 504         struct drm_crtc *crtc;
 505         struct drm_i915_gem_object *old_fb_obj;
 506         struct drm_i915_gem_object *pending_flip_obj;
 507         struct drm_pending_vblank_event *event;
 508         atomic_t pending;
 509 #define INTEL_FLIP_INACTIVE     0
 510 #define INTEL_FLIP_PENDING      1
 511 #define INTEL_FLIP_COMPLETE     2
 512         bool enable_stall_check;
 513 };
 514
 515 struct intel_set_config {
 516         struct drm_encoder **save_connector_encoders;
 517         struct drm_crtc **save_encoder_crtcs;
 518
 519         bool fb_changed;
 520         bool mode_changed;
 521 };
 522
 523 struct intel_load_detect_pipe {
 524         struct drm_framebuffer *release_fb;
 525         bool load_detect_temp;
 526         int dpms_mode;
 527 };
 528
 529 static inline struct intel_encoder *
 530 intel_attached_encoder(struct drm_connector *connector)
 531 {
 532         return to_intel_connector(connector)->encoder;
 533 }
 534
 535 static inline struct intel_digital_port *
 536 enc_to_dig_port(struct drm_encoder *encoder)
 537 {
 538         return container_of(encoder, struct intel_digital_port, base.base);
 539 }
 540
 541 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 542 {
 543         return &enc_to_dig_port(encoder)->dp;
 544 }
 545
 546 static inline struct intel_digital_port *
 547 dp_to_dig_port(struct intel_dp *intel_dp)
 548 {
 549         return container_of(intel_dp, struct intel_digital_port, dp);
 550 }
 551
 552 static inline struct intel_digital_port *
 553 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 554 {
 555         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 556 }
 557
 558
 559 /* i915_irq.c */
 560 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 561                                            enum pipe pipe, bool enable);
 562 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 563                                            enum transcoder pch_transcoder,
 564                                            bool enable);
 565 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 566 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 567 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 568 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 569 void hsw_pc8_disable_interrupts(struct drm_device *dev);
 570 void hsw_pc8_restore_interrupts(struct drm_device *dev);
 571
 572
 573 /* intel_crt.c */
 574 void intel_crt_init(struct drm_device *dev);
 575
 576
 577 /* intel_ddi.c */
 578 void intel_prepare_ddi(struct drm_device *dev);
 579 void hsw_fdi_link_train(struct drm_crtc *crtc);
 580 void intel_ddi_init(struct drm_device *dev, enum port port);
 581 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 582 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 583 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 584 void intel_ddi_pll_init(struct drm_device *dev);
 585 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 586 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 587                                        enum transcoder cpu_transcoder);
 588 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 589 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 590 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 591 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
 592 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 593 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 594 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 595 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 596 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 597 void intel_ddi_get_config(struct intel_encoder *encoder,
 598                           struct intel_crtc_config *pipe_config);
 599
 600
 601 /* intel_display.c */
 602 int intel_pch_rawclk(struct drm_device *dev);
 603 void intel_mark_busy(struct drm_device *dev);
 604 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 605                         struct intel_ring_buffer *ring);
 606 void intel_mark_idle(struct drm_device *dev);
 607 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 608 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 609 void intel_encoder_destroy(struct drm_encoder *encoder);
 610 void intel_connector_dpms(struct drm_connector *, int mode);
 611 bool intel_connector_get_hw_state(struct intel_connector *connector);
 612 void intel_modeset_check_state(struct drm_device *dev);
 613 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 614                                 struct intel_digital_port *port);
 615 void intel_connector_attach_encoder(struct intel_connector *connector,
 616                                     struct intel_encoder *encoder);
 617 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 618 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 619                                              struct drm_crtc *crtc);
 620 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 621                                 struct drm_file *file_priv);
 622 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 623                                              enum pipe pipe);
 624 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 625 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 626 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 627 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
 628 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 629                                 struct drm_display_mode *mode,
 630                                 struct intel_load_detect_pipe *old);
 631 void intel_release_load_detect_pipe(struct drm_connector *connector,
 632                                     struct intel_load_detect_pipe *old);
 633 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 634                                struct drm_i915_gem_object *obj,
 635                                struct intel_ring_buffer *pipelined);
 636 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 637 int intel_framebuffer_init(struct drm_device *dev,
 638                            struct intel_framebuffer *ifb,
 639                            struct drm_mode_fb_cmd2 *mode_cmd,
 640                            struct drm_i915_gem_object *obj);
 641 void intel_framebuffer_fini(struct intel_framebuffer *fb);
 642 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 643 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 644 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 645 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 646 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 647                         struct intel_shared_dpll *pll,
 648                         bool state);
 649 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 650 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 651 void assert_pll(struct drm_i915_private *dev_priv,
 652                 enum pipe pipe, bool state);
 653 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 654 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 655 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 656                        enum pipe pipe, bool state);
 657 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 658 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 659 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 660 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 661 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 662 void intel_write_eld(struct drm_encoder *encoder,
 663                      struct drm_display_mode *mode);
 664 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 665                                              unsigned int tiling_mode,
 666                                              unsigned int bpp,
 667                                              unsigned int pitch);
 668 void intel_display_handle_reset(struct drm_device *dev);
 669 void hsw_enable_pc8_work(struct work_struct *__work);
 670 void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 671 void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 672 void intel_dp_get_m_n(struct intel_crtc *crtc,
 673                       struct intel_crtc_config *pipe_config);
 674 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 675 void
 676 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 677                                 int dotclock);
 678 bool intel_crtc_active(struct drm_crtc *crtc);
 679 void i915_disable_vga_mem(struct drm_device *dev);
 680 void hsw_enable_ips(struct intel_crtc *crtc);
 681 void hsw_disable_ips(struct intel_crtc *crtc);
 682
 683
 684 /* intel_dp.c */
 685 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 686 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 687                              struct intel_connector *intel_connector);
 688 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 689 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 690 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 691 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 692 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 693 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 694 bool intel_dp_compute_config(struct intel_encoder *encoder,
 695                              struct intel_crtc_config *pipe_config);
 696 bool intel_dpd_is_edp(struct drm_device *dev);
 697 void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 698 void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 699 void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 700 void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 701 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 702 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 703 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 704 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 705 void intel_edp_psr_update(struct drm_device *dev);
 706
 707
 708 /* intel_dsi.c */
 709 bool intel_dsi_init(struct drm_device *dev);
 710
 711
 712 /* intel_dvo.c */
 713 void intel_dvo_init(struct drm_device *dev);
 714
 715
 716 /* legacy fbdev emulation in intel_fb.c */
 717 #ifdef CONFIG_DRM_I915_FBDEV
 718 extern int intel_fbdev_init(struct drm_device *dev);
 719 extern void intel_fbdev_initial_config(struct drm_device *dev);
 720 extern void intel_fbdev_fini(struct drm_device *dev);
 721 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 722 extern void intel_fb_output_poll_changed(struct drm_device *dev);
 723 extern void intel_fb_restore_mode(struct drm_device *dev);
 724 #else
 725 static inline int intel_fbdev_init(struct drm_device *dev)
 726 {
 727         return 0;
 728 }
 729
 730 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 731 {
 732 }
 733
 734 static inline void intel_fbdev_fini(struct drm_device *dev)
 735 {
 736 }
 737
 738 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 739 {
 740 }
 741
 742 static inline void intel_fb_restore_mode(struct drm_device *dev)
 743 {
 744 }
 745 #endif
 746
 747 /* intel_hdmi.c */
 748 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 749 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 750                                struct intel_connector *intel_connector);
 751 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 752 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 753                                struct intel_crtc_config *pipe_config);
 754
 755
 756 /* intel_lvds.c */
 757 void intel_lvds_init(struct drm_device *dev);
 758 bool intel_is_dual_link_lvds(struct drm_device *dev);
 759
 760
 761 /* intel_modes.c */
 762 int intel_connector_update_modes(struct drm_connector *connector,
 763                                  struct edid *edid);
 764 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 765 void intel_attach_force_audio_property(struct drm_connector *connector);
 766 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 767
 768
 769 /* intel_overlay.c */
 770 void intel_setup_overlay(struct drm_device *dev);
 771 void intel_cleanup_overlay(struct drm_device *dev);
 772 int intel_overlay_switch_off(struct intel_overlay *overlay);
 773 int intel_overlay_put_image(struct drm_device *dev, void *data,
 774                             struct drm_file *file_priv);
 775 int intel_overlay_attrs(struct drm_device *dev, void *data,
 776                         struct drm_file *file_priv);
 777
 778
 779 /* intel_panel.c */
 780 int intel_panel_init(struct intel_panel *panel,
 781                      struct drm_display_mode *fixed_mode);
 782 void intel_panel_fini(struct intel_panel *panel);
 783 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 784                             struct drm_display_mode *adjusted_mode);
 785 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 786                              struct intel_crtc_config *pipe_config,
 787                              int fitting_mode);
 788 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 789                               struct intel_crtc_config *pipe_config,
 790                               int fitting_mode);
 791 void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max);
 792 int intel_panel_setup_backlight(struct drm_connector *connector);
 793 void intel_panel_enable_backlight(struct drm_device *dev, enum pipe pipe);
 794 void intel_panel_disable_backlight(struct drm_device *dev);
 795 void intel_panel_destroy_backlight(struct drm_device *dev);
 796 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 797
 798
 799 /* intel_pm.c */
 800 void intel_init_clock_gating(struct drm_device *dev);
 801 void intel_suspend_hw(struct drm_device *dev);
 802 void intel_update_watermarks(struct drm_crtc *crtc);
 803 void intel_update_sprite_watermarks(struct drm_plane *plane,
 804                                     struct drm_crtc *crtc,
 805                                     uint32_t sprite_width, int pixel_size,
 806                                     bool enabled, bool scaled);
 807 void intel_init_pm(struct drm_device *dev);
 808 bool intel_fbc_enabled(struct drm_device *dev);
 809 void intel_update_fbc(struct drm_device *dev);
 810 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 811 void intel_gpu_ips_teardown(void);
 812 int i915_init_power_well(struct drm_device *dev);
 813 void i915_remove_power_well(struct drm_device *dev);
 814 bool intel_display_power_enabled(struct drm_device *dev,
 815                                  enum intel_display_power_domain domain);
 816 void intel_display_power_get(struct drm_device *dev,
 817                              enum intel_display_power_domain domain);
 818 void intel_display_power_put(struct drm_device *dev,
 819                              enum intel_display_power_domain domain);
 820 void intel_init_power_well(struct drm_device *dev);
 821 void intel_set_power_well(struct drm_device *dev, bool enable);
 822 void intel_enable_gt_powersave(struct drm_device *dev);
 823 void intel_disable_gt_powersave(struct drm_device *dev);
 824 void ironlake_teardown_rc6(struct drm_device *dev);
 825 void gen6_update_ring_freq(struct drm_device *dev);
 826 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 827 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 828 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 829 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 830
 831
 832 /* intel_sdvo.c */
 833 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 834
 835
 836 /* intel_sprite.c */
 837 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 838 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 839                                enum plane plane);
 840 void intel_plane_restore(struct drm_plane *plane);
 841 void intel_plane_disable(struct drm_plane *plane);
 842 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 843                               struct drm_file *file_priv);
 844 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 845                               struct drm_file *file_priv);
 846
 847
 848 /* intel_tv.c */
 849 void intel_tv_init(struct drm_device *dev);
 850
 851 #endif /* __INTEL_DRV_H__ */