2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type
{
96 INTEL_OUTPUT_UNUSED
= 0,
97 INTEL_OUTPUT_ANALOG
= 1,
99 INTEL_OUTPUT_SDVO
= 3,
100 INTEL_OUTPUT_LVDS
= 4,
101 INTEL_OUTPUT_TVOUT
= 5,
102 INTEL_OUTPUT_HDMI
= 6,
103 INTEL_OUTPUT_DISPLAYPORT
= 7,
104 INTEL_OUTPUT_EDP
= 8,
105 INTEL_OUTPUT_DSI
= 9,
106 INTEL_OUTPUT_UNKNOWN
= 10,
107 INTEL_OUTPUT_DP_MST
= 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer
{
119 struct drm_framebuffer base
;
120 struct drm_i915_gem_object
*obj
;
124 struct drm_fb_helper helper
;
125 struct intel_framebuffer
*fb
;
129 struct intel_encoder
{
130 struct drm_encoder base
;
132 enum intel_output_type type
;
133 unsigned int cloneable
;
134 void (*hot_plug
)(struct intel_encoder
*);
135 bool (*compute_config
)(struct intel_encoder
*,
136 struct intel_crtc_state
*);
137 void (*pre_pll_enable
)(struct intel_encoder
*);
138 void (*pre_enable
)(struct intel_encoder
*);
139 void (*enable
)(struct intel_encoder
*);
140 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
141 void (*disable
)(struct intel_encoder
*);
142 void (*post_disable
)(struct intel_encoder
*);
143 void (*post_pll_disable
)(struct intel_encoder
*);
144 /* Read out the current hw state of this connector, returning true if
145 * the encoder is active. If the encoder is enabled it also set the pipe
146 * it is connected to in the pipe parameter. */
147 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
148 /* Reconstructs the equivalent mode flags for the current hardware
149 * state. This must be called _after_ display->get_pipe_config has
150 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
151 * be set correctly before calling this function. */
152 void (*get_config
)(struct intel_encoder
*,
153 struct intel_crtc_state
*pipe_config
);
155 * Called during system suspend after all pending requests for the
156 * encoder are flushed (for example for DP AUX transactions) and
157 * device interrupts are disabled.
159 void (*suspend
)(struct intel_encoder
*);
161 enum hpd_pin hpd_pin
;
165 struct drm_display_mode
*fixed_mode
;
166 struct drm_display_mode
*downclock_mode
;
176 bool combination_mode
; /* gen 2/4 only */
180 bool util_pin_active_low
; /* bxt+ */
181 u8 controller
; /* bxt+ only */
182 struct pwm_device
*pwm
;
184 struct backlight_device
*device
;
186 /* Connector and platform specific backlight functions */
187 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
188 uint32_t (*get
)(struct intel_connector
*connector
);
189 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
190 void (*disable
)(struct intel_connector
*connector
);
191 void (*enable
)(struct intel_connector
*connector
);
192 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
194 void (*power
)(struct intel_connector
*, bool enable
);
198 struct intel_connector
{
199 struct drm_connector base
;
201 * The fixed encoder this connector is connected to.
203 struct intel_encoder
*encoder
;
205 /* Reads out the current hw, returning true if the connector is enabled
206 * and active (i.e. dpms ON state). */
207 bool (*get_hw_state
)(struct intel_connector
*);
210 * Removes all interfaces through which the connector is accessible
211 * - like sysfs, debugfs entries -, so that no new operations can be
212 * started on the connector. Also makes sure all currently pending
213 * operations finish before returing.
215 void (*unregister
)(struct intel_connector
*);
217 /* Panel info for eDP and LVDS */
218 struct intel_panel panel
;
220 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
222 struct edid
*detect_edid
;
224 /* since POLL and HPD connectors may use the same HPD line keep the native
225 state of connector->polled in case hotplug storm detection changes it */
228 void *port
; /* store this opaque as its illegal to dereference it */
230 struct intel_dp
*mst_port
;
233 typedef struct dpll
{
245 struct intel_atomic_state
{
246 struct drm_atomic_state base
;
250 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
251 struct intel_wm_config wm_config
;
254 struct intel_plane_state
{
255 struct drm_plane_state base
;
258 struct drm_rect clip
;
263 * = -1 : not using a scaler
264 * >= 0 : using a scalers
266 * plane requiring a scaler:
267 * - During check_plane, its bit is set in
268 * crtc_state->scaler_state.scaler_users by calling helper function
269 * update_scaler_plane.
270 * - scaler_id indicates the scaler it got assigned.
272 * plane doesn't require a scaler:
273 * - this can happen when scaling is no more required or plane simply
275 * - During check_plane, corresponding bit is reset in
276 * crtc_state->scaler_state.scaler_users by calling helper function
277 * update_scaler_plane.
281 struct drm_intel_sprite_colorkey ckey
;
283 /* async flip related structures */
284 struct drm_i915_gem_request
*wait_req
;
287 struct intel_initial_plane_config
{
288 struct intel_framebuffer
*fb
;
294 #define SKL_MIN_SRC_W 8
295 #define SKL_MAX_SRC_W 4096
296 #define SKL_MIN_SRC_H 8
297 #define SKL_MAX_SRC_H 4096
298 #define SKL_MIN_DST_W 8
299 #define SKL_MAX_DST_W 4096
300 #define SKL_MIN_DST_H 8
301 #define SKL_MAX_DST_H 4096
303 struct intel_scaler
{
308 struct intel_crtc_scaler_state
{
309 #define SKL_NUM_SCALERS 2
310 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
313 * scaler_users: keeps track of users requesting scalers on this crtc.
315 * If a bit is set, a user is using a scaler.
316 * Here user can be a plane or crtc as defined below:
317 * bits 0-30 - plane (bit position is index from drm_plane_index)
320 * Instead of creating a new index to cover planes and crtc, using
321 * existing drm_plane_index for planes which is well less than 31
322 * planes and bit 31 for crtc. This should be fine to cover all
325 * intel_atomic_setup_scalers will setup available scalers to users
326 * requesting scalers. It will gracefully fail if request exceeds
329 #define SKL_CRTC_INDEX 31
330 unsigned scaler_users
;
332 /* scaler used by crtc for panel fitting purpose */
336 /* drm_mode->private_flags */
337 #define I915_MODE_FLAG_INHERITED 1
339 struct intel_pipe_wm
{
340 struct intel_wm_level wm
[5];
344 bool sprites_enabled
;
349 struct skl_wm_level wm
[8];
350 struct skl_wm_level trans_wm
;
354 struct intel_crtc_state
{
355 struct drm_crtc_state base
;
358 * quirks - bitfield with hw state readout quirks
360 * For various reasons the hw state readout code might not be able to
361 * completely faithfully read out the current state. These cases are
362 * tracked with quirk flags so that fastboot and state checker can act
365 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
366 unsigned long quirks
;
368 bool update_pipe
; /* can a fast modeset be performed? */
370 bool wm_changed
; /* watermarks are updated */
372 /* Pipe source size (ie. panel fitter input size)
373 * All planes will be positioned inside this space,
374 * and get clipped at the edges. */
375 int pipe_src_w
, pipe_src_h
;
377 /* Whether to set up the PCH/FDI. Note that we never allow sharing
378 * between pch encoders and cpu encoders. */
379 bool has_pch_encoder
;
381 /* Are we sending infoframes on the attached port */
384 /* CPU Transcoder for the pipe. Currently this can only differ from the
385 * pipe on Haswell (where we have a special eDP transcoder). */
386 enum transcoder cpu_transcoder
;
389 * Use reduced/limited/broadcast rbg range, compressing from the full
390 * range fed into the crtcs.
392 bool limited_color_range
;
394 /* DP has a bunch of special case unfortunately, so mark the pipe
398 /* DSI has special cases */
399 bool has_dsi_encoder
;
401 /* Whether we should send NULL infoframes. Required for audio. */
404 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
405 * has_dp_encoder is set. */
409 * Enable dithering, used when the selected pipe bpp doesn't match the
414 /* Controls for the clock computation, to override various stages. */
417 /* SDVO TV has a bunch of special case. To make multifunction encoders
418 * work correctly, we need to track this at runtime.*/
422 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
423 * required. This is set in the 2nd loop of calling encoder's
424 * ->compute_config if the first pick doesn't work out.
428 /* Settings for the intel dpll used on pretty much everything but
432 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
433 enum intel_dpll_id shared_dpll
;
436 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
437 * - enum skl_dpll on SKL
439 uint32_t ddi_pll_sel
;
441 /* Actual register state of the dpll, for shared dpll cross-checking. */
442 struct intel_dpll_hw_state dpll_hw_state
;
445 struct intel_link_m_n dp_m_n
;
447 /* m2_n2 for eDP downclock */
448 struct intel_link_m_n dp_m2_n2
;
452 * Frequence the dpll for the port should run at. Differs from the
453 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
454 * already multiplied by pixel_multiplier.
458 /* Used by SDVO (and if we ever fix it, HDMI). */
459 unsigned pixel_multiplier
;
463 /* Panel fitter controls for gen2-gen4 + VLV */
467 u32 lvds_border_bits
;
470 /* Panel fitter placement and size for Ironlake+ */
478 /* FDI configuration, only valid if has_pch_encoder is set. */
480 struct intel_link_m_n fdi_m_n
;
486 bool dp_encoder_is_mst
;
489 struct intel_crtc_scaler_state scaler_state
;
491 /* w/a for waiting 2 vblanks during crtc enable */
492 enum pipe hsw_workaround_pipe
;
494 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
499 * optimal watermarks, programmed post-vblank when this state
503 struct intel_pipe_wm ilk
;
504 struct skl_pipe_wm skl
;
509 struct vlv_wm_state
{
510 struct vlv_pipe_wm wm
[3];
511 struct vlv_sr_wm sr
[3];
512 uint8_t num_active_planes
;
518 struct intel_mmio_flip
{
519 struct work_struct work
;
520 struct drm_i915_private
*i915
;
521 struct drm_i915_gem_request
*req
;
522 struct intel_crtc
*crtc
;
523 unsigned int rotation
;
527 * Tracking of operations that need to be performed at the beginning/end of an
528 * atomic commit, outside the atomic section where interrupts are disabled.
529 * These are generally operations that grab mutexes or might otherwise sleep
530 * and thus can't be run with interrupts disabled.
532 struct intel_crtc_atomic_commit
{
533 /* Sleepable operations to perform before commit */
536 bool pre_disable_primary
;
538 /* Sleepable operations to perform after commit */
542 bool post_enable_primary
;
543 unsigned update_sprite_watermarks
;
547 struct drm_crtc base
;
550 u8 lut_r
[256], lut_g
[256], lut_b
[256];
552 * Whether the crtc and the connected output pipeline is active. Implies
553 * that crtc->enabled is set, i.e. the current mode configuration has
554 * some outputs connected to this crtc.
557 unsigned long enabled_power_domains
;
559 struct intel_overlay
*overlay
;
560 struct intel_unpin_work
*unpin_work
;
562 atomic_t unpin_work_count
;
564 /* Display surface base address adjustement for pageflips. Note that on
565 * gen4+ this only adjusts up to a tile, offsets within a tile are
566 * handled in the hw itself (with the TILEOFF register). */
567 unsigned long dspaddr_offset
;
571 uint32_t cursor_addr
;
572 uint32_t cursor_cntl
;
573 uint32_t cursor_size
;
574 uint32_t cursor_base
;
576 struct intel_crtc_state
*config
;
578 /* reset counter value when the last flip was submitted */
579 unsigned int reset_counter
;
581 /* Access to these should be protected by dev_priv->irq_lock. */
582 bool cpu_fifo_underrun_disabled
;
583 bool pch_fifo_underrun_disabled
;
585 /* per-pipe watermark state */
587 /* watermarks currently being used */
589 struct intel_pipe_wm ilk
;
590 struct skl_pipe_wm skl
;
592 /* allow CxSR on this pipe */
599 unsigned start_vbl_count
;
600 ktime_t start_vbl_time
;
601 int min_vbl
, max_vbl
;
605 struct intel_crtc_atomic_commit atomic
;
607 /* scalers available on this crtc */
610 struct vlv_wm_state wm_state
;
613 struct intel_plane_wm_parameters
{
614 uint32_t horiz_pixels
;
615 uint32_t vert_pixels
;
617 * For packed pixel formats:
618 * bytes_per_pixel - holds bytes per pixel
619 * For planar pixel formats:
620 * bytes_per_pixel - holds bytes per pixel for uv-plane
621 * y_bytes_per_pixel - holds bytes per pixel for y-plane
623 uint8_t bytes_per_pixel
;
624 uint8_t y_bytes_per_pixel
;
628 unsigned int rotation
;
633 struct drm_plane base
;
638 uint32_t frontbuffer_bit
;
640 /* Since we need to change the watermarks before/after
641 * enabling/disabling the planes, we need to store the parameters here
642 * as the other pieces of the struct may not reflect the values we want
643 * for the watermark calculations. Currently only Haswell uses this.
645 struct intel_plane_wm_parameters wm
;
648 * NOTE: Do not place new plane state fields here (e.g., when adding
649 * new plane properties). New runtime state should now be placed in
650 * the intel_plane_state structure and accessed via drm_plane->state.
653 void (*update_plane
)(struct drm_plane
*plane
,
654 struct drm_crtc
*crtc
,
655 struct drm_framebuffer
*fb
,
656 int crtc_x
, int crtc_y
,
657 unsigned int crtc_w
, unsigned int crtc_h
,
658 uint32_t x
, uint32_t y
,
659 uint32_t src_w
, uint32_t src_h
);
660 void (*disable_plane
)(struct drm_plane
*plane
,
661 struct drm_crtc
*crtc
);
662 int (*check_plane
)(struct drm_plane
*plane
,
663 struct intel_crtc_state
*crtc_state
,
664 struct intel_plane_state
*state
);
665 void (*commit_plane
)(struct drm_plane
*plane
,
666 struct intel_plane_state
*state
);
669 struct intel_watermark_params
{
670 unsigned long fifo_size
;
671 unsigned long max_wm
;
672 unsigned long default_wm
;
673 unsigned long guard_size
;
674 unsigned long cacheline_size
;
677 struct cxsr_latency
{
680 unsigned long fsb_freq
;
681 unsigned long mem_freq
;
682 unsigned long display_sr
;
683 unsigned long display_hpll_disable
;
684 unsigned long cursor_sr
;
685 unsigned long cursor_hpll_disable
;
688 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
689 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
690 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
691 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
692 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
693 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
694 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
695 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
696 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
701 bool limited_color_range
;
702 bool color_range_auto
;
705 enum hdmi_force_audio force_audio
;
706 bool rgb_quant_range_selectable
;
707 enum hdmi_picture_aspect aspect_ratio
;
708 struct intel_connector
*attached_connector
;
709 void (*write_infoframe
)(struct drm_encoder
*encoder
,
710 enum hdmi_infoframe_type type
,
711 const void *frame
, ssize_t len
);
712 void (*set_infoframes
)(struct drm_encoder
*encoder
,
714 const struct drm_display_mode
*adjusted_mode
);
715 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
716 const struct intel_crtc_state
*pipe_config
);
719 struct intel_dp_mst_encoder
;
720 #define DP_MAX_DOWNSTREAM_PORTS 0x10
724 * When platform provides two set of M_N registers for dp, we can
725 * program them and switch between them incase of DRRS.
726 * But When only one such register is provided, we have to program the
727 * required divider value on that registers itself based on the DRRS state.
729 * M1_N1 : Program dp_m_n on M1_N1 registers
730 * dp_m2_n2 on M2_N2 registers (If supported)
732 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
733 * M2_N2 registers are not supported
737 /* Sets the m1_n1 and m2_n2 */
743 i915_reg_t output_reg
;
744 i915_reg_t aux_ch_ctl_reg
;
745 i915_reg_t aux_ch_data_reg
[5];
750 enum hdmi_force_audio force_audio
;
751 bool limited_color_range
;
752 bool color_range_auto
;
753 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
754 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
755 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
756 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
757 uint8_t num_sink_rates
;
758 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
759 struct drm_dp_aux aux
;
760 uint8_t train_set
[4];
761 int panel_power_up_delay
;
762 int panel_power_down_delay
;
763 int panel_power_cycle_delay
;
764 int backlight_on_delay
;
765 int backlight_off_delay
;
766 struct delayed_work panel_vdd_work
;
768 unsigned long last_power_cycle
;
769 unsigned long last_power_on
;
770 unsigned long last_backlight_off
;
772 struct notifier_block edp_notifier
;
775 * Pipe whose power sequencer is currently locked into
776 * this port. Only relevant on VLV/CHV.
779 struct edp_power_seq pps_delays
;
781 bool can_mst
; /* this port supports mst */
783 int active_mst_links
;
784 /* connector directly attached - won't be use for modeset in mst world */
785 struct intel_connector
*attached_connector
;
787 /* mst connector list */
788 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
789 struct drm_dp_mst_topology_mgr mst_mgr
;
791 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
793 * This function returns the value we have to program the AUX_CTL
794 * register with to kick off an AUX transaction.
796 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
799 uint32_t aux_clock_divider
);
801 /* This is called before a link training is starterd */
802 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
804 bool train_set_valid
;
806 /* Displayport compliance testing */
807 unsigned long compliance_test_type
;
808 unsigned long compliance_test_data
;
809 bool compliance_test_active
;
812 struct intel_digital_port
{
813 struct intel_encoder base
;
817 struct intel_hdmi hdmi
;
818 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
819 bool release_cl2_override
;
820 /* for communication with audio component; protected by av_mutex */
821 const struct drm_connector
*audio_connector
;
824 struct intel_dp_mst_encoder
{
825 struct intel_encoder base
;
827 struct intel_digital_port
*primary
;
828 void *port
; /* store this opaque as its illegal to dereference it */
831 static inline enum dpio_channel
832 vlv_dport_to_channel(struct intel_digital_port
*dport
)
834 switch (dport
->port
) {
845 static inline enum dpio_phy
846 vlv_dport_to_phy(struct intel_digital_port
*dport
)
848 switch (dport
->port
) {
859 static inline enum dpio_channel
860 vlv_pipe_to_channel(enum pipe pipe
)
873 static inline struct drm_crtc
*
874 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
880 static inline struct drm_crtc
*
881 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
884 return dev_priv
->plane_to_crtc_mapping
[plane
];
887 struct intel_unpin_work
{
888 struct work_struct work
;
889 struct drm_crtc
*crtc
;
890 struct drm_framebuffer
*old_fb
;
891 struct drm_i915_gem_object
*pending_flip_obj
;
892 struct drm_pending_vblank_event
*event
;
894 #define INTEL_FLIP_INACTIVE 0
895 #define INTEL_FLIP_PENDING 1
896 #define INTEL_FLIP_COMPLETE 2
899 struct drm_i915_gem_request
*flip_queued_req
;
900 u32 flip_queued_vblank
;
901 u32 flip_ready_vblank
;
902 bool enable_stall_check
;
905 struct intel_load_detect_pipe
{
906 struct drm_framebuffer
*release_fb
;
907 bool load_detect_temp
;
911 static inline struct intel_encoder
*
912 intel_attached_encoder(struct drm_connector
*connector
)
914 return to_intel_connector(connector
)->encoder
;
917 static inline struct intel_digital_port
*
918 enc_to_dig_port(struct drm_encoder
*encoder
)
920 return container_of(encoder
, struct intel_digital_port
, base
.base
);
923 static inline struct intel_dp_mst_encoder
*
924 enc_to_mst(struct drm_encoder
*encoder
)
926 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
929 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
931 return &enc_to_dig_port(encoder
)->dp
;
934 static inline struct intel_digital_port
*
935 dp_to_dig_port(struct intel_dp
*intel_dp
)
937 return container_of(intel_dp
, struct intel_digital_port
, dp
);
940 static inline struct intel_digital_port
*
941 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
943 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
947 * Returns the number of planes for this pipe, ie the number of sprites + 1
948 * (primary plane). This doesn't count the cursor plane then.
950 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
952 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
955 /* intel_fifo_underrun.c */
956 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
957 enum pipe pipe
, bool enable
);
958 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
959 enum transcoder pch_transcoder
,
961 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
963 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
964 enum transcoder pch_transcoder
);
965 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
966 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
969 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
970 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
971 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
972 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
973 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
974 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
975 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
976 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
977 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
978 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
979 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
982 * We only use drm_irq_uninstall() at unload and VT switch, so
983 * this is the only thing we need to check.
985 return dev_priv
->pm
.irqs_enabled
;
988 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
989 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
990 unsigned int pipe_mask
);
993 void intel_crt_init(struct drm_device
*dev
);
997 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
998 const struct intel_crtc_state
*pipe_config
);
999 void intel_prepare_ddi(struct drm_device
*dev
);
1000 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1001 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1002 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1003 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1004 void intel_ddi_pll_init(struct drm_device
*dev
);
1005 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1006 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1007 enum transcoder cpu_transcoder
);
1008 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1009 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1010 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1011 struct intel_crtc_state
*crtc_state
);
1012 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1013 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1014 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1015 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
1016 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1017 struct intel_crtc
*intel_crtc
);
1018 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1019 struct intel_crtc_state
*pipe_config
);
1020 struct intel_encoder
*
1021 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1023 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1024 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1025 struct intel_crtc_state
*pipe_config
);
1026 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1027 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1029 /* intel_frontbuffer.c */
1030 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
1031 enum fb_op_origin origin
);
1032 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
1033 unsigned frontbuffer_bits
);
1034 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
1035 unsigned frontbuffer_bits
);
1036 void intel_frontbuffer_flip(struct drm_device
*dev
,
1037 unsigned frontbuffer_bits
);
1038 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1039 unsigned int height
,
1040 uint32_t pixel_format
,
1041 uint64_t fb_format_modifier
);
1042 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
,
1043 enum fb_op_origin origin
);
1044 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
1045 uint32_t pixel_format
);
1048 void intel_init_audio(struct drm_device
*dev
);
1049 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
1050 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1051 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1052 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1054 /* intel_display.c */
1055 extern const struct drm_plane_funcs intel_plane_funcs
;
1056 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1057 int intel_pch_rawclk(struct drm_device
*dev
);
1058 int intel_hrawclk(struct drm_device
*dev
);
1059 void intel_mark_busy(struct drm_device
*dev
);
1060 void intel_mark_idle(struct drm_device
*dev
);
1061 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1062 int intel_display_suspend(struct drm_device
*dev
);
1063 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1064 int intel_connector_init(struct intel_connector
*);
1065 struct intel_connector
*intel_connector_alloc(void);
1066 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1067 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1068 struct intel_encoder
*encoder
);
1069 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
1070 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1071 struct drm_crtc
*crtc
);
1072 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1073 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1074 struct drm_file
*file_priv
);
1075 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1077 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
1079 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1081 drm_wait_one_vblank(dev
, pipe
);
1084 intel_wait_for_vblank_if_active(struct drm_device
*dev
, int pipe
)
1086 const struct intel_crtc
*crtc
=
1087 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1090 intel_wait_for_vblank(dev
, pipe
);
1092 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1093 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1094 struct intel_digital_port
*dport
,
1095 unsigned int expected_mask
);
1096 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1097 struct drm_display_mode
*mode
,
1098 struct intel_load_detect_pipe
*old
,
1099 struct drm_modeset_acquire_ctx
*ctx
);
1100 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1101 struct intel_load_detect_pipe
*old
,
1102 struct drm_modeset_acquire_ctx
*ctx
);
1103 int intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
1104 struct drm_framebuffer
*fb
,
1105 const struct drm_plane_state
*plane_state
);
1106 struct drm_framebuffer
*
1107 __intel_framebuffer_create(struct drm_device
*dev
,
1108 struct drm_mode_fb_cmd2
*mode_cmd
,
1109 struct drm_i915_gem_object
*obj
);
1110 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
1111 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
1112 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
1113 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
1114 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1115 const struct drm_plane_state
*new_state
);
1116 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1117 const struct drm_plane_state
*old_state
);
1118 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1119 const struct drm_plane_state
*state
,
1120 struct drm_property
*property
,
1122 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1123 struct drm_plane_state
*state
,
1124 struct drm_property
*property
,
1126 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1127 struct drm_plane_state
*plane_state
);
1130 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
1131 uint64_t fb_format_modifier
, unsigned int plane
);
1134 intel_rotation_90_or_270(unsigned int rotation
)
1136 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1139 void intel_create_rotation_property(struct drm_device
*dev
,
1140 struct intel_plane
*plane
);
1142 /* shared dpll functions */
1143 struct intel_shared_dpll
*intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
);
1144 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1145 struct intel_shared_dpll
*pll
,
1147 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1148 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1149 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
1150 struct intel_crtc_state
*state
);
1152 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1153 const struct dpll
*dpll
);
1154 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1156 /* modesetting asserts */
1157 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1159 void assert_pll(struct drm_i915_private
*dev_priv
,
1160 enum pipe pipe
, bool state
);
1161 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1162 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1163 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1164 enum pipe pipe
, bool state
);
1165 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1166 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1167 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1168 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1169 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1170 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
1172 unsigned int tiling_mode
,
1174 unsigned int pitch
);
1175 void intel_prepare_reset(struct drm_device
*dev
);
1176 void intel_finish_reset(struct drm_device
*dev
);
1177 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1178 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1179 void broxton_init_cdclk(struct drm_device
*dev
);
1180 void broxton_uninit_cdclk(struct drm_device
*dev
);
1181 void broxton_ddi_phy_init(struct drm_device
*dev
);
1182 void broxton_ddi_phy_uninit(struct drm_device
*dev
);
1183 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1184 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1185 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1186 int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
1187 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1188 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1189 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1190 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1191 struct intel_crtc_state
*pipe_config
);
1192 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1193 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1195 ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
1197 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1198 intel_clock_t
*best_clock
);
1199 int chv_calc_dpll_params(int refclk
, intel_clock_t
*pll_clock
);
1201 bool intel_crtc_active(struct drm_crtc
*crtc
);
1202 void hsw_enable_ips(struct intel_crtc
*crtc
);
1203 void hsw_disable_ips(struct intel_crtc
*crtc
);
1204 enum intel_display_power_domain
1205 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1206 enum intel_display_power_domain
1207 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1208 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1209 struct intel_crtc_state
*pipe_config
);
1210 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
);
1212 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1213 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1215 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1216 struct drm_i915_gem_object
*obj
,
1217 unsigned int plane
);
1219 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1220 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1221 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1224 void intel_csr_ucode_init(struct drm_i915_private
*);
1225 void intel_csr_load_program(struct drm_i915_private
*);
1226 void intel_csr_ucode_fini(struct drm_i915_private
*);
1229 void intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1230 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1231 struct intel_connector
*intel_connector
);
1232 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1233 const struct intel_crtc_state
*pipe_config
);
1234 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1235 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1236 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1237 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1238 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1239 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1240 struct intel_crtc_state
*pipe_config
);
1241 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1242 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1244 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1245 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1246 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1247 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1248 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1249 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1250 void intel_dp_mst_suspend(struct drm_device
*dev
);
1251 void intel_dp_mst_resume(struct drm_device
*dev
);
1252 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1253 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1254 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1255 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1256 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1257 void intel_plane_destroy(struct drm_plane
*plane
);
1258 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1259 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1260 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1261 unsigned frontbuffer_bits
);
1262 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1263 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1264 struct intel_digital_port
*port
);
1265 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
);
1268 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1269 uint8_t dp_train_pat
);
1271 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1272 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1274 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1276 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1277 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1278 uint8_t *link_bw
, uint8_t *rate_select
);
1279 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1281 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1283 /* intel_dp_mst.c */
1284 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1285 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1287 void intel_dsi_init(struct drm_device
*dev
);
1291 void intel_dvo_init(struct drm_device
*dev
);
1294 /* legacy fbdev emulation in intel_fbdev.c */
1295 #ifdef CONFIG_DRM_FBDEV_EMULATION
1296 extern int intel_fbdev_init(struct drm_device
*dev
);
1297 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1298 extern void intel_fbdev_fini(struct drm_device
*dev
);
1299 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1300 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1301 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1303 static inline int intel_fbdev_init(struct drm_device
*dev
)
1308 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1312 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1316 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1320 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1326 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1327 void intel_fbc_deactivate(struct intel_crtc
*crtc
);
1328 void intel_fbc_update(struct intel_crtc
*crtc
);
1329 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1330 void intel_fbc_enable(struct intel_crtc
*crtc
);
1331 void intel_fbc_disable(struct drm_i915_private
*dev_priv
);
1332 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
);
1333 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1334 unsigned int frontbuffer_bits
,
1335 enum fb_op_origin origin
);
1336 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1337 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1338 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1341 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1342 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1343 struct intel_connector
*intel_connector
);
1344 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1345 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1346 struct intel_crtc_state
*pipe_config
);
1350 void intel_lvds_init(struct drm_device
*dev
);
1351 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1355 int intel_connector_update_modes(struct drm_connector
*connector
,
1357 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1358 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1359 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1360 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1363 /* intel_overlay.c */
1364 void intel_setup_overlay(struct drm_device
*dev
);
1365 void intel_cleanup_overlay(struct drm_device
*dev
);
1366 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1367 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1368 struct drm_file
*file_priv
);
1369 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1370 struct drm_file
*file_priv
);
1371 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1375 int intel_panel_init(struct intel_panel
*panel
,
1376 struct drm_display_mode
*fixed_mode
,
1377 struct drm_display_mode
*downclock_mode
);
1378 void intel_panel_fini(struct intel_panel
*panel
);
1379 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1380 struct drm_display_mode
*adjusted_mode
);
1381 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1382 struct intel_crtc_state
*pipe_config
,
1384 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1385 struct intel_crtc_state
*pipe_config
,
1387 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1388 u32 level
, u32 max
);
1389 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1390 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1391 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1392 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1393 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1394 extern struct drm_display_mode
*intel_find_panel_downclock(
1395 struct drm_device
*dev
,
1396 struct drm_display_mode
*fixed_mode
,
1397 struct drm_connector
*connector
);
1398 void intel_backlight_register(struct drm_device
*dev
);
1399 void intel_backlight_unregister(struct drm_device
*dev
);
1403 void intel_psr_enable(struct intel_dp
*intel_dp
);
1404 void intel_psr_disable(struct intel_dp
*intel_dp
);
1405 void intel_psr_invalidate(struct drm_device
*dev
,
1406 unsigned frontbuffer_bits
);
1407 void intel_psr_flush(struct drm_device
*dev
,
1408 unsigned frontbuffer_bits
,
1409 enum fb_op_origin origin
);
1410 void intel_psr_init(struct drm_device
*dev
);
1411 void intel_psr_single_frame_update(struct drm_device
*dev
,
1412 unsigned frontbuffer_bits
);
1414 /* intel_runtime_pm.c */
1415 int intel_power_domains_init(struct drm_i915_private
*);
1416 void intel_power_domains_fini(struct drm_i915_private
*);
1417 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1418 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1419 void skl_pw1_misc_io_init(struct drm_i915_private
*dev_priv
);
1420 void skl_pw1_misc_io_fini(struct drm_i915_private
*dev_priv
);
1421 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1423 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1425 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1426 enum intel_display_power_domain domain
);
1427 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1428 enum intel_display_power_domain domain
);
1429 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1430 enum intel_display_power_domain domain
);
1431 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1432 enum intel_display_power_domain domain
);
1433 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1434 enum intel_display_power_domain domain
);
1437 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1439 WARN_ONCE(dev_priv
->pm
.suspended
,
1440 "Device suspended during HW access\n");
1444 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1446 assert_rpm_device_not_suspended(dev_priv
);
1447 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1448 * too much noise. */
1449 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1450 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1454 assert_rpm_atomic_begin(struct drm_i915_private
*dev_priv
)
1456 int seq
= atomic_read(&dev_priv
->pm
.atomic_seq
);
1458 assert_rpm_wakelock_held(dev_priv
);
1464 assert_rpm_atomic_end(struct drm_i915_private
*dev_priv
, int begin_seq
)
1466 WARN_ONCE(atomic_read(&dev_priv
->pm
.atomic_seq
) != begin_seq
,
1467 "HW access outside of RPM atomic section\n");
1471 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1472 * @dev_priv: i915 device instance
1474 * This function disable asserts that check if we hold an RPM wakelock
1475 * reference, while keeping the device-not-suspended checks still enabled.
1476 * It's meant to be used only in special circumstances where our rule about
1477 * the wakelock refcount wrt. the device power state doesn't hold. According
1478 * to this rule at any point where we access the HW or want to keep the HW in
1479 * an active state we must hold an RPM wakelock reference acquired via one of
1480 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1481 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1482 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1483 * users should avoid using this function.
1485 * Any calls to this function must have a symmetric call to
1486 * enable_rpm_wakeref_asserts().
1489 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1491 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1495 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1496 * @dev_priv: i915 device instance
1498 * This function re-enables the RPM assert checks after disabling them with
1499 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1500 * circumstances otherwise its use should be avoided.
1502 * Any calls to this function must have a symmetric call to
1503 * disable_rpm_wakeref_asserts().
1506 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1508 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1511 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1512 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1513 disable_rpm_wakeref_asserts(dev_priv)
1515 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1516 enable_rpm_wakeref_asserts(dev_priv)
1518 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1519 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1520 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1521 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1523 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1525 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1526 bool override
, unsigned int mask
);
1527 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1528 enum dpio_channel ch
, bool override
);
1532 void intel_init_clock_gating(struct drm_device
*dev
);
1533 void intel_suspend_hw(struct drm_device
*dev
);
1534 int ilk_wm_max_level(const struct drm_device
*dev
);
1535 void intel_update_watermarks(struct drm_crtc
*crtc
);
1536 void intel_init_pm(struct drm_device
*dev
);
1537 void intel_pm_setup(struct drm_device
*dev
);
1538 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1539 void intel_gpu_ips_teardown(void);
1540 void intel_init_gt_powersave(struct drm_device
*dev
);
1541 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1542 void intel_enable_gt_powersave(struct drm_device
*dev
);
1543 void intel_disable_gt_powersave(struct drm_device
*dev
);
1544 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1545 void intel_reset_gt_powersave(struct drm_device
*dev
);
1546 void gen6_update_ring_freq(struct drm_device
*dev
);
1547 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1548 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1549 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1550 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1551 struct intel_rps_client
*rps
,
1552 unsigned long submitted
);
1553 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
1554 struct drm_i915_gem_request
*req
);
1555 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1556 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1557 void skl_wm_get_hw_state(struct drm_device
*dev
);
1558 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1559 struct skl_ddb_allocation
*ddb
/* out */);
1560 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1563 bool intel_sdvo_init(struct drm_device
*dev
,
1564 i915_reg_t reg
, enum port port
);
1567 /* intel_sprite.c */
1568 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1569 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1570 struct drm_file
*file_priv
);
1571 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1572 void intel_pipe_update_end(struct intel_crtc
*crtc
);
1575 void intel_tv_init(struct drm_device
*dev
);
1577 /* intel_atomic.c */
1578 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1579 const struct drm_connector_state
*state
,
1580 struct drm_property
*property
,
1582 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1583 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1584 struct drm_crtc_state
*state
);
1585 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1586 void intel_atomic_state_clear(struct drm_atomic_state
*);
1587 struct intel_shared_dpll_config
*
1588 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1590 static inline struct intel_crtc_state
*
1591 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1592 struct intel_crtc
*crtc
)
1594 struct drm_crtc_state
*crtc_state
;
1595 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1596 if (IS_ERR(crtc_state
))
1597 return ERR_CAST(crtc_state
);
1599 return to_intel_crtc_state(crtc_state
);
1601 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1602 struct intel_crtc
*intel_crtc
,
1603 struct intel_crtc_state
*crtc_state
);
1605 /* intel_atomic_plane.c */
1606 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1607 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1608 void intel_plane_destroy_state(struct drm_plane
*plane
,
1609 struct drm_plane_state
*state
);
1610 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1612 #endif /* __INTEL_DRV_H__ */