drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         int preferred_bpp;
 127 };
 128
 129 struct intel_encoder {
 130         struct drm_encoder base;
 131
 132         enum intel_output_type type;
 133         unsigned int cloneable;
 134         void (*hot_plug)(struct intel_encoder *);
 135         bool (*compute_config)(struct intel_encoder *,
 136                                struct intel_crtc_state *);
 137         void (*pre_pll_enable)(struct intel_encoder *);
 138         void (*pre_enable)(struct intel_encoder *);
 139         void (*enable)(struct intel_encoder *);
 140         void (*mode_set)(struct intel_encoder *intel_encoder);
 141         void (*disable)(struct intel_encoder *);
 142         void (*post_disable)(struct intel_encoder *);
 143         void (*post_pll_disable)(struct intel_encoder *);
 144         /* Read out the current hw state of this connector, returning true if
 145          * the encoder is active. If the encoder is enabled it also set the pipe
 146          * it is connected to in the pipe parameter. */
 147         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 148         /* Reconstructs the equivalent mode flags for the current hardware
 149          * state. This must be called _after_ display->get_pipe_config has
 150          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 151          * be set correctly before calling this function. */
 152         void (*get_config)(struct intel_encoder *,
 153                            struct intel_crtc_state *pipe_config);
 154         /*
 155          * Called during system suspend after all pending requests for the
 156          * encoder are flushed (for example for DP AUX transactions) and
 157          * device interrupts are disabled.
 158          */
 159         void (*suspend)(struct intel_encoder *);
 160         int crtc_mask;
 161         enum hpd_pin hpd_pin;
 162 };
 163
 164 struct intel_panel {
 165         struct drm_display_mode *fixed_mode;
 166         struct drm_display_mode *downclock_mode;
 167         int fitting_mode;
 168
 169         /* backlight */
 170         struct {
 171                 bool present;
 172                 u32 level;
 173                 u32 min;
 174                 u32 max;
 175                 bool enabled;
 176                 bool combination_mode;  /* gen 2/4 only */
 177                 bool active_low_pwm;
 178
 179                 /* PWM chip */
 180                 bool util_pin_active_low;       /* bxt+ */
 181                 u8 controller;          /* bxt+ only */
 182                 struct pwm_device *pwm;
 183
 184                 struct backlight_device *device;
 185
 186                 /* Connector and platform specific backlight functions */
 187                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 188                 uint32_t (*get)(struct intel_connector *connector);
 189                 void (*set)(struct intel_connector *connector, uint32_t level);
 190                 void (*disable)(struct intel_connector *connector);
 191                 void (*enable)(struct intel_connector *connector);
 192                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 193                                       uint32_t hz);
 194                 void (*power)(struct intel_connector *, bool enable);
 195         } backlight;
 196 };
 197
 198 struct intel_connector {
 199         struct drm_connector base;
 200         /*
 201          * The fixed encoder this connector is connected to.
 202          */
 203         struct intel_encoder *encoder;
 204
 205         /* Reads out the current hw, returning true if the connector is enabled
 206          * and active (i.e. dpms ON state). */
 207         bool (*get_hw_state)(struct intel_connector *);
 208
 209         /*
 210          * Removes all interfaces through which the connector is accessible
 211          * - like sysfs, debugfs entries -, so that no new operations can be
 212          * started on the connector. Also makes sure all currently pending
 213          * operations finish before returing.
 214          */
 215         void (*unregister)(struct intel_connector *);
 216
 217         /* Panel info for eDP and LVDS */
 218         struct intel_panel panel;
 219
 220         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 221         struct edid *edid;
 222         struct edid *detect_edid;
 223
 224         /* since POLL and HPD connectors may use the same HPD line keep the native
 225            state of connector->polled in case hotplug storm detection changes it */
 226         u8 polled;
 227
 228         void *port; /* store this opaque as its illegal to dereference it */
 229
 230         struct intel_dp *mst_port;
 231 };
 232
 233 typedef struct dpll {
 234         /* given values */
 235         int n;
 236         int m1, m2;
 237         int p1, p2;
 238         /* derived values */
 239         int     dot;
 240         int     vco;
 241         int     m;
 242         int     p;
 243 } intel_clock_t;
 244
 245 struct intel_atomic_state {
 246         struct drm_atomic_state base;
 247
 248         unsigned int cdclk;
 249         bool dpll_set;
 250         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 251         struct intel_wm_config wm_config;
 252 };
 253
 254 struct intel_plane_state {
 255         struct drm_plane_state base;
 256         struct drm_rect src;
 257         struct drm_rect dst;
 258         struct drm_rect clip;
 259         bool visible;
 260
 261         /*
 262          * scaler_id
 263          *    = -1 : not using a scaler
 264          *    >=  0 : using a scalers
 265          *
 266          * plane requiring a scaler:
 267          *   - During check_plane, its bit is set in
 268          *     crtc_state->scaler_state.scaler_users by calling helper function
 269          *     update_scaler_plane.
 270          *   - scaler_id indicates the scaler it got assigned.
 271          *
 272          * plane doesn't require a scaler:
 273          *   - this can happen when scaling is no more required or plane simply
 274          *     got disabled.
 275          *   - During check_plane, corresponding bit is reset in
 276          *     crtc_state->scaler_state.scaler_users by calling helper function
 277          *     update_scaler_plane.
 278          */
 279         int scaler_id;
 280
 281         struct drm_intel_sprite_colorkey ckey;
 282
 283         /* async flip related structures */
 284         struct drm_i915_gem_request *wait_req;
 285 };
 286
 287 struct intel_initial_plane_config {
 288         struct intel_framebuffer *fb;
 289         unsigned int tiling;
 290         int size;
 291         u32 base;
 292 };
 293
 294 #define SKL_MIN_SRC_W 8
 295 #define SKL_MAX_SRC_W 4096
 296 #define SKL_MIN_SRC_H 8
 297 #define SKL_MAX_SRC_H 4096
 298 #define SKL_MIN_DST_W 8
 299 #define SKL_MAX_DST_W 4096
 300 #define SKL_MIN_DST_H 8
 301 #define SKL_MAX_DST_H 4096
 302
 303 struct intel_scaler {
 304         int in_use;
 305         uint32_t mode;
 306 };
 307
 308 struct intel_crtc_scaler_state {
 309 #define SKL_NUM_SCALERS 2
 310         struct intel_scaler scalers[SKL_NUM_SCALERS];
 311
 312         /*
 313          * scaler_users: keeps track of users requesting scalers on this crtc.
 314          *
 315          *     If a bit is set, a user is using a scaler.
 316          *     Here user can be a plane or crtc as defined below:
 317          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 318          *       bit 31    - crtc
 319          *
 320          * Instead of creating a new index to cover planes and crtc, using
 321          * existing drm_plane_index for planes which is well less than 31
 322          * planes and bit 31 for crtc. This should be fine to cover all
 323          * our platforms.
 324          *
 325          * intel_atomic_setup_scalers will setup available scalers to users
 326          * requesting scalers. It will gracefully fail if request exceeds
 327          * avilability.
 328          */
 329 #define SKL_CRTC_INDEX 31
 330         unsigned scaler_users;
 331
 332         /* scaler used by crtc for panel fitting purpose */
 333         int scaler_id;
 334 };
 335
 336 /* drm_mode->private_flags */
 337 #define I915_MODE_FLAG_INHERITED 1
 338
 339 struct intel_pipe_wm {
 340         struct intel_wm_level wm[5];
 341         uint32_t linetime;
 342         bool fbc_wm_enabled;
 343         bool pipe_enabled;
 344         bool sprites_enabled;
 345         bool sprites_scaled;
 346 };
 347
 348 struct skl_pipe_wm {
 349         struct skl_wm_level wm[8];
 350         struct skl_wm_level trans_wm;
 351         uint32_t linetime;
 352 };
 353
 354 struct intel_crtc_state {
 355         struct drm_crtc_state base;
 356
 357         /**
 358          * quirks - bitfield with hw state readout quirks
 359          *
 360          * For various reasons the hw state readout code might not be able to
 361          * completely faithfully read out the current state. These cases are
 362          * tracked with quirk flags so that fastboot and state checker can act
 363          * accordingly.
 364          */
 365 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 366         unsigned long quirks;
 367
 368         bool update_pipe;
 369
 370         /* Pipe source size (ie. panel fitter input size)
 371          * All planes will be positioned inside this space,
 372          * and get clipped at the edges. */
 373         int pipe_src_w, pipe_src_h;
 374
 375         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 376          * between pch encoders and cpu encoders. */
 377         bool has_pch_encoder;
 378
 379         /* Are we sending infoframes on the attached port */
 380         bool has_infoframe;
 381
 382         /* CPU Transcoder for the pipe. Currently this can only differ from the
 383          * pipe on Haswell (where we have a special eDP transcoder). */
 384         enum transcoder cpu_transcoder;
 385
 386         /*
 387          * Use reduced/limited/broadcast rbg range, compressing from the full
 388          * range fed into the crtcs.
 389          */
 390         bool limited_color_range;
 391
 392         /* DP has a bunch of special case unfortunately, so mark the pipe
 393          * accordingly. */
 394         bool has_dp_encoder;
 395
 396         /* Whether we should send NULL infoframes. Required for audio. */
 397         bool has_hdmi_sink;
 398
 399         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 400          * has_dp_encoder is set. */
 401         bool has_audio;
 402
 403         /*
 404          * Enable dithering, used when the selected pipe bpp doesn't match the
 405          * plane bpp.
 406          */
 407         bool dither;
 408
 409         /* Controls for the clock computation, to override various stages. */
 410         bool clock_set;
 411
 412         /* SDVO TV has a bunch of special case. To make multifunction encoders
 413          * work correctly, we need to track this at runtime.*/
 414         bool sdvo_tv_clock;
 415
 416         /*
 417          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 418          * required. This is set in the 2nd loop of calling encoder's
 419          * ->compute_config if the first pick doesn't work out.
 420          */
 421         bool bw_constrained;
 422
 423         /* Settings for the intel dpll used on pretty much everything but
 424          * haswell. */
 425         struct dpll dpll;
 426
 427         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 428         enum intel_dpll_id shared_dpll;
 429
 430         /*
 431          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 432          * - enum skl_dpll on SKL
 433          */
 434         uint32_t ddi_pll_sel;
 435
 436         /* Actual register state of the dpll, for shared dpll cross-checking. */
 437         struct intel_dpll_hw_state dpll_hw_state;
 438
 439         int pipe_bpp;
 440         struct intel_link_m_n dp_m_n;
 441
 442         /* m2_n2 for eDP downclock */
 443         struct intel_link_m_n dp_m2_n2;
 444         bool has_drrs;
 445
 446         /*
 447          * Frequence the dpll for the port should run at. Differs from the
 448          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 449          * already multiplied by pixel_multiplier.
 450          */
 451         int port_clock;
 452
 453         /* Used by SDVO (and if we ever fix it, HDMI). */
 454         unsigned pixel_multiplier;
 455
 456         uint8_t lane_count;
 457
 458         /* Panel fitter controls for gen2-gen4 + VLV */
 459         struct {
 460                 u32 control;
 461                 u32 pgm_ratios;
 462                 u32 lvds_border_bits;
 463         } gmch_pfit;
 464
 465         /* Panel fitter placement and size for Ironlake+ */
 466         struct {
 467                 u32 pos;
 468                 u32 size;
 469                 bool enabled;
 470                 bool force_thru;
 471         } pch_pfit;
 472
 473         /* FDI configuration, only valid if has_pch_encoder is set. */
 474         int fdi_lanes;
 475         struct intel_link_m_n fdi_m_n;
 476
 477         bool ips_enabled;
 478
 479         bool double_wide;
 480
 481         bool dp_encoder_is_mst;
 482         int pbn;
 483
 484         struct intel_crtc_scaler_state scaler_state;
 485
 486         /* w/a for waiting 2 vblanks during crtc enable */
 487         enum pipe hsw_workaround_pipe;
 488
 489         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 490         bool disable_lp_wm;
 491
 492         struct {
 493                 /*
 494                  * optimal watermarks, programmed post-vblank when this state
 495                  * is committed
 496                  */
 497                 union {
 498                         struct intel_pipe_wm ilk;
 499                         struct skl_pipe_wm skl;
 500                 } optimal;
 501         } wm;
 502 };
 503
 504 struct vlv_wm_state {
 505         struct vlv_pipe_wm wm[3];
 506         struct vlv_sr_wm sr[3];
 507         uint8_t num_active_planes;
 508         uint8_t num_levels;
 509         uint8_t level;
 510         bool cxsr;
 511 };
 512
 513 struct intel_mmio_flip {
 514         struct work_struct work;
 515         struct drm_i915_private *i915;
 516         struct drm_i915_gem_request *req;
 517         struct intel_crtc *crtc;
 518         unsigned int rotation;
 519 };
 520
 521 /*
 522  * Tracking of operations that need to be performed at the beginning/end of an
 523  * atomic commit, outside the atomic section where interrupts are disabled.
 524  * These are generally operations that grab mutexes or might otherwise sleep
 525  * and thus can't be run with interrupts disabled.
 526  */
 527 struct intel_crtc_atomic_commit {
 528         /* Sleepable operations to perform before commit */
 529         bool disable_fbc;
 530         bool disable_ips;
 531         bool disable_cxsr;
 532         bool pre_disable_primary;
 533         bool update_wm_pre, update_wm_post;
 534
 535         /* Sleepable operations to perform after commit */
 536         unsigned fb_bits;
 537         bool wait_vblank;
 538         bool update_fbc;
 539         bool post_enable_primary;
 540         unsigned update_sprite_watermarks;
 541 };
 542
 543 struct intel_crtc {
 544         struct drm_crtc base;
 545         enum pipe pipe;
 546         enum plane plane;
 547         u8 lut_r[256], lut_g[256], lut_b[256];
 548         /*
 549          * Whether the crtc and the connected output pipeline is active. Implies
 550          * that crtc->enabled is set, i.e. the current mode configuration has
 551          * some outputs connected to this crtc.
 552          */
 553         bool active;
 554         unsigned long enabled_power_domains;
 555         bool lowfreq_avail;
 556         struct intel_overlay *overlay;
 557         struct intel_unpin_work *unpin_work;
 558
 559         atomic_t unpin_work_count;
 560
 561         /* Display surface base address adjustement for pageflips. Note that on
 562          * gen4+ this only adjusts up to a tile, offsets within a tile are
 563          * handled in the hw itself (with the TILEOFF register). */
 564         unsigned long dspaddr_offset;
 565         int adjusted_x;
 566         int adjusted_y;
 567
 568         struct drm_i915_gem_object *cursor_bo;
 569         uint32_t cursor_addr;
 570         uint32_t cursor_cntl;
 571         uint32_t cursor_size;
 572         uint32_t cursor_base;
 573
 574         struct intel_crtc_state *config;
 575
 576         /* reset counter value when the last flip was submitted */
 577         unsigned int reset_counter;
 578
 579         /* Access to these should be protected by dev_priv->irq_lock. */
 580         bool cpu_fifo_underrun_disabled;
 581         bool pch_fifo_underrun_disabled;
 582
 583         /* per-pipe watermark state */
 584         struct {
 585                 /* watermarks currently being used  */
 586                 union {
 587                         struct intel_pipe_wm ilk;
 588                         struct skl_pipe_wm skl;
 589                 } active;
 590                 /* allow CxSR on this pipe */
 591                 bool cxsr_allowed;
 592         } wm;
 593
 594         int scanline_offset;
 595
 596         struct {
 597                 unsigned start_vbl_count;
 598                 ktime_t start_vbl_time;
 599                 int min_vbl, max_vbl;
 600                 int scanline_start;
 601         } debug;
 602
 603         struct intel_crtc_atomic_commit atomic;
 604
 605         /* scalers available on this crtc */
 606         int num_scalers;
 607
 608         struct vlv_wm_state wm_state;
 609 };
 610
 611 struct intel_plane_wm_parameters {
 612         uint32_t horiz_pixels;
 613         uint32_t vert_pixels;
 614         /*
 615          *   For packed pixel formats:
 616          *     bytes_per_pixel - holds bytes per pixel
 617          *   For planar pixel formats:
 618          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 619          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 620          */
 621         uint8_t bytes_per_pixel;
 622         uint8_t y_bytes_per_pixel;
 623         bool enabled;
 624         bool scaled;
 625         u64 tiling;
 626         unsigned int rotation;
 627         uint16_t fifo_size;
 628 };
 629
 630 struct intel_plane {
 631         struct drm_plane base;
 632         int plane;
 633         enum pipe pipe;
 634         bool can_scale;
 635         int max_downscale;
 636         uint32_t frontbuffer_bit;
 637
 638         /* Since we need to change the watermarks before/after
 639          * enabling/disabling the planes, we need to store the parameters here
 640          * as the other pieces of the struct may not reflect the values we want
 641          * for the watermark calculations. Currently only Haswell uses this.
 642          */
 643         struct intel_plane_wm_parameters wm;
 644
 645         /*
 646          * NOTE: Do not place new plane state fields here (e.g., when adding
 647          * new plane properties).  New runtime state should now be placed in
 648          * the intel_plane_state structure and accessed via drm_plane->state.
 649          */
 650
 651         void (*update_plane)(struct drm_plane *plane,
 652                              struct drm_crtc *crtc,
 653                              struct drm_framebuffer *fb,
 654                              int crtc_x, int crtc_y,
 655                              unsigned int crtc_w, unsigned int crtc_h,
 656                              uint32_t x, uint32_t y,
 657                              uint32_t src_w, uint32_t src_h);
 658         void (*disable_plane)(struct drm_plane *plane,
 659                               struct drm_crtc *crtc);
 660         int (*check_plane)(struct drm_plane *plane,
 661                            struct intel_crtc_state *crtc_state,
 662                            struct intel_plane_state *state);
 663         void (*commit_plane)(struct drm_plane *plane,
 664                              struct intel_plane_state *state);
 665 };
 666
 667 struct intel_watermark_params {
 668         unsigned long fifo_size;
 669         unsigned long max_wm;
 670         unsigned long default_wm;
 671         unsigned long guard_size;
 672         unsigned long cacheline_size;
 673 };
 674
 675 struct cxsr_latency {
 676         int is_desktop;
 677         int is_ddr3;
 678         unsigned long fsb_freq;
 679         unsigned long mem_freq;
 680         unsigned long display_sr;
 681         unsigned long display_hpll_disable;
 682         unsigned long cursor_sr;
 683         unsigned long cursor_hpll_disable;
 684 };
 685
 686 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 687 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 688 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 689 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 690 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 691 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 692 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 693 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 694 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 695
 696 struct intel_hdmi {
 697         i915_reg_t hdmi_reg;
 698         int ddc_bus;
 699         bool limited_color_range;
 700         bool color_range_auto;
 701         bool has_hdmi_sink;
 702         bool has_audio;
 703         enum hdmi_force_audio force_audio;
 704         bool rgb_quant_range_selectable;
 705         enum hdmi_picture_aspect aspect_ratio;
 706         struct intel_connector *attached_connector;
 707         void (*write_infoframe)(struct drm_encoder *encoder,
 708                                 enum hdmi_infoframe_type type,
 709                                 const void *frame, ssize_t len);
 710         void (*set_infoframes)(struct drm_encoder *encoder,
 711                                bool enable,
 712                                const struct drm_display_mode *adjusted_mode);
 713         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 714 };
 715
 716 struct intel_dp_mst_encoder;
 717 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 718
 719 /*
 720  * enum link_m_n_set:
 721  *      When platform provides two set of M_N registers for dp, we can
 722  *      program them and switch between them incase of DRRS.
 723  *      But When only one such register is provided, we have to program the
 724  *      required divider value on that registers itself based on the DRRS state.
 725  *
 726  * M1_N1        : Program dp_m_n on M1_N1 registers
 727  *                        dp_m2_n2 on M2_N2 registers (If supported)
 728  *
 729  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 730  *                        M2_N2 registers are not supported
 731  */
 732
 733 enum link_m_n_set {
 734         /* Sets the m1_n1 and m2_n2 */
 735         M1_N1 = 0,
 736         M2_N2
 737 };
 738
 739 struct intel_dp {
 740         i915_reg_t output_reg;
 741         i915_reg_t aux_ch_ctl_reg;
 742         i915_reg_t aux_ch_data_reg[5];
 743         uint32_t DP;
 744         int link_rate;
 745         uint8_t lane_count;
 746         bool has_audio;
 747         enum hdmi_force_audio force_audio;
 748         bool limited_color_range;
 749         bool color_range_auto;
 750         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 751         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 752         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 753         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 754         uint8_t num_sink_rates;
 755         int sink_rates[DP_MAX_SUPPORTED_RATES];
 756         struct drm_dp_aux aux;
 757         uint8_t train_set[4];
 758         int panel_power_up_delay;
 759         int panel_power_down_delay;
 760         int panel_power_cycle_delay;
 761         int backlight_on_delay;
 762         int backlight_off_delay;
 763         struct delayed_work panel_vdd_work;
 764         bool want_panel_vdd;
 765         unsigned long last_power_cycle;
 766         unsigned long last_power_on;
 767         unsigned long last_backlight_off;
 768
 769         struct notifier_block edp_notifier;
 770
 771         /*
 772          * Pipe whose power sequencer is currently locked into
 773          * this port. Only relevant on VLV/CHV.
 774          */
 775         enum pipe pps_pipe;
 776         struct edp_power_seq pps_delays;
 777
 778         bool can_mst; /* this port supports mst */
 779         bool is_mst;
 780         int active_mst_links;
 781         /* connector directly attached - won't be use for modeset in mst world */
 782         struct intel_connector *attached_connector;
 783
 784         /* mst connector list */
 785         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 786         struct drm_dp_mst_topology_mgr mst_mgr;
 787
 788         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 789         /*
 790          * This function returns the value we have to program the AUX_CTL
 791          * register with to kick off an AUX transaction.
 792          */
 793         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 794                                      bool has_aux_irq,
 795                                      int send_bytes,
 796                                      uint32_t aux_clock_divider);
 797
 798         /* This is called before a link training is starterd */
 799         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 800
 801         bool train_set_valid;
 802
 803         /* Displayport compliance testing */
 804         unsigned long compliance_test_type;
 805         unsigned long compliance_test_data;
 806         bool compliance_test_active;
 807 };
 808
 809 struct intel_digital_port {
 810         struct intel_encoder base;
 811         enum port port;
 812         u32 saved_port_bits;
 813         struct intel_dp dp;
 814         struct intel_hdmi hdmi;
 815         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 816         bool release_cl2_override;
 817 };
 818
 819 struct intel_dp_mst_encoder {
 820         struct intel_encoder base;
 821         enum pipe pipe;
 822         struct intel_digital_port *primary;
 823         void *port; /* store this opaque as its illegal to dereference it */
 824 };
 825
 826 static inline enum dpio_channel
 827 vlv_dport_to_channel(struct intel_digital_port *dport)
 828 {
 829         switch (dport->port) {
 830         case PORT_B:
 831         case PORT_D:
 832                 return DPIO_CH0;
 833         case PORT_C:
 834                 return DPIO_CH1;
 835         default:
 836                 BUG();
 837         }
 838 }
 839
 840 static inline enum dpio_phy
 841 vlv_dport_to_phy(struct intel_digital_port *dport)
 842 {
 843         switch (dport->port) {
 844         case PORT_B:
 845         case PORT_C:
 846                 return DPIO_PHY0;
 847         case PORT_D:
 848                 return DPIO_PHY1;
 849         default:
 850                 BUG();
 851         }
 852 }
 853
 854 static inline enum dpio_channel
 855 vlv_pipe_to_channel(enum pipe pipe)
 856 {
 857         switch (pipe) {
 858         case PIPE_A:
 859         case PIPE_C:
 860                 return DPIO_CH0;
 861         case PIPE_B:
 862                 return DPIO_CH1;
 863         default:
 864                 BUG();
 865         }
 866 }
 867
 868 static inline struct drm_crtc *
 869 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 870 {
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         return dev_priv->pipe_to_crtc_mapping[pipe];
 873 }
 874
 875 static inline struct drm_crtc *
 876 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 877 {
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         return dev_priv->plane_to_crtc_mapping[plane];
 880 }
 881
 882 struct intel_unpin_work {
 883         struct work_struct work;
 884         struct drm_crtc *crtc;
 885         struct drm_framebuffer *old_fb;
 886         struct drm_i915_gem_object *pending_flip_obj;
 887         struct drm_pending_vblank_event *event;
 888         atomic_t pending;
 889 #define INTEL_FLIP_INACTIVE     0
 890 #define INTEL_FLIP_PENDING      1
 891 #define INTEL_FLIP_COMPLETE     2
 892         u32 flip_count;
 893         u32 gtt_offset;
 894         struct drm_i915_gem_request *flip_queued_req;
 895         u32 flip_queued_vblank;
 896         u32 flip_ready_vblank;
 897         bool enable_stall_check;
 898 };
 899
 900 struct intel_load_detect_pipe {
 901         struct drm_framebuffer *release_fb;
 902         bool load_detect_temp;
 903         int dpms_mode;
 904 };
 905
 906 static inline struct intel_encoder *
 907 intel_attached_encoder(struct drm_connector *connector)
 908 {
 909         return to_intel_connector(connector)->encoder;
 910 }
 911
 912 static inline struct intel_digital_port *
 913 enc_to_dig_port(struct drm_encoder *encoder)
 914 {
 915         return container_of(encoder, struct intel_digital_port, base.base);
 916 }
 917
 918 static inline struct intel_dp_mst_encoder *
 919 enc_to_mst(struct drm_encoder *encoder)
 920 {
 921         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 922 }
 923
 924 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 925 {
 926         return &enc_to_dig_port(encoder)->dp;
 927 }
 928
 929 static inline struct intel_digital_port *
 930 dp_to_dig_port(struct intel_dp *intel_dp)
 931 {
 932         return container_of(intel_dp, struct intel_digital_port, dp);
 933 }
 934
 935 static inline struct intel_digital_port *
 936 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 937 {
 938         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 939 }
 940
 941 /*
 942  * Returns the number of planes for this pipe, ie the number of sprites + 1
 943  * (primary plane). This doesn't count the cursor plane then.
 944  */
 945 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 946 {
 947         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 948 }
 949
 950 /* intel_fifo_underrun.c */
 951 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 952                                            enum pipe pipe, bool enable);
 953 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 954                                            enum transcoder pch_transcoder,
 955                                            bool enable);
 956 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 957                                          enum pipe pipe);
 958 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 959                                          enum transcoder pch_transcoder);
 960 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 961 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 962
 963 /* i915_irq.c */
 964 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 965 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 966 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 967 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 968 void gen6_reset_rps_interrupts(struct drm_device *dev);
 969 void gen6_enable_rps_interrupts(struct drm_device *dev);
 970 void gen6_disable_rps_interrupts(struct drm_device *dev);
 971 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 972 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 973 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 974 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 975 {
 976         /*
 977          * We only use drm_irq_uninstall() at unload and VT switch, so
 978          * this is the only thing we need to check.
 979          */
 980         return dev_priv->pm.irqs_enabled;
 981 }
 982
 983 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 984 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 985                                      unsigned int pipe_mask);
 986
 987 /* intel_crt.c */
 988 void intel_crt_init(struct drm_device *dev);
 989
 990
 991 /* intel_ddi.c */
 992 void intel_ddi_clk_select(struct intel_encoder *encoder,
 993                           const struct intel_crtc_state *pipe_config);
 994 void intel_prepare_ddi(struct drm_device *dev);
 995 void hsw_fdi_link_train(struct drm_crtc *crtc);
 996 void intel_ddi_init(struct drm_device *dev, enum port port);
 997 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 998 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 999 void intel_ddi_pll_init(struct drm_device *dev);
1000 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1001 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1002                                        enum transcoder cpu_transcoder);
1003 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1004 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1005 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1006                           struct intel_crtc_state *crtc_state);
1007 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1008 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1009 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1010 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1011 void intel_ddi_get_config(struct intel_encoder *encoder,
1012                           struct intel_crtc_state *pipe_config);
1013 struct intel_encoder *
1014 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1015
1016 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1017 void intel_ddi_clock_get(struct intel_encoder *encoder,
1018                          struct intel_crtc_state *pipe_config);
1019 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1020 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1021
1022 /* intel_frontbuffer.c */
1023 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1024                              enum fb_op_origin origin);
1025 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1026                                     unsigned frontbuffer_bits);
1027 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1028                                      unsigned frontbuffer_bits);
1029 void intel_frontbuffer_flip(struct drm_device *dev,
1030                             unsigned frontbuffer_bits);
1031 unsigned int intel_fb_align_height(struct drm_device *dev,
1032                                    unsigned int height,
1033                                    uint32_t pixel_format,
1034                                    uint64_t fb_format_modifier);
1035 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1036                         enum fb_op_origin origin);
1037 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1038                               uint32_t pixel_format);
1039
1040 /* intel_audio.c */
1041 void intel_init_audio(struct drm_device *dev);
1042 void intel_audio_codec_enable(struct intel_encoder *encoder);
1043 void intel_audio_codec_disable(struct intel_encoder *encoder);
1044 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1045 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1046
1047 /* intel_display.c */
1048 extern const struct drm_plane_funcs intel_plane_funcs;
1049 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1050 int intel_pch_rawclk(struct drm_device *dev);
1051 int intel_hrawclk(struct drm_device *dev);
1052 void intel_mark_busy(struct drm_device *dev);
1053 void intel_mark_idle(struct drm_device *dev);
1054 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1055 int intel_display_suspend(struct drm_device *dev);
1056 void intel_encoder_destroy(struct drm_encoder *encoder);
1057 int intel_connector_init(struct intel_connector *);
1058 struct intel_connector *intel_connector_alloc(void);
1059 bool intel_connector_get_hw_state(struct intel_connector *connector);
1060 void intel_connector_attach_encoder(struct intel_connector *connector,
1061                                     struct intel_encoder *encoder);
1062 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1063 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1064                                              struct drm_crtc *crtc);
1065 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1066 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1067                                 struct drm_file *file_priv);
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069                                              enum pipe pipe);
1070 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1071 static inline void
1072 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1073 {
1074         drm_wait_one_vblank(dev, pipe);
1075 }
1076 static inline void
1077 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1078 {
1079         const struct intel_crtc *crtc =
1080                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1081
1082         if (crtc->active)
1083                 intel_wait_for_vblank(dev, pipe);
1084 }
1085 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1086 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1087                          struct intel_digital_port *dport,
1088                          unsigned int expected_mask);
1089 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1090                                 struct drm_display_mode *mode,
1091                                 struct intel_load_detect_pipe *old,
1092                                 struct drm_modeset_acquire_ctx *ctx);
1093 void intel_release_load_detect_pipe(struct drm_connector *connector,
1094                                     struct intel_load_detect_pipe *old,
1095                                     struct drm_modeset_acquire_ctx *ctx);
1096 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1097                                struct drm_framebuffer *fb,
1098                                const struct drm_plane_state *plane_state);
1099 struct drm_framebuffer *
1100 __intel_framebuffer_create(struct drm_device *dev,
1101                            struct drm_mode_fb_cmd2 *mode_cmd,
1102                            struct drm_i915_gem_object *obj);
1103 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1104 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1105 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1106 void intel_check_page_flip(struct drm_device *dev, int pipe);
1107 int intel_prepare_plane_fb(struct drm_plane *plane,
1108                            const struct drm_plane_state *new_state);
1109 void intel_cleanup_plane_fb(struct drm_plane *plane,
1110                             const struct drm_plane_state *old_state);
1111 int intel_plane_atomic_get_property(struct drm_plane *plane,
1112                                     const struct drm_plane_state *state,
1113                                     struct drm_property *property,
1114                                     uint64_t *val);
1115 int intel_plane_atomic_set_property(struct drm_plane *plane,
1116                                     struct drm_plane_state *state,
1117                                     struct drm_property *property,
1118                                     uint64_t val);
1119 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1120                                     struct drm_plane_state *plane_state);
1121
1122 unsigned int
1123 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1124                   uint64_t fb_format_modifier, unsigned int plane);
1125
1126 static inline bool
1127 intel_rotation_90_or_270(unsigned int rotation)
1128 {
1129         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1130 }
1131
1132 void intel_create_rotation_property(struct drm_device *dev,
1133                                         struct intel_plane *plane);
1134
1135 /* shared dpll functions */
1136 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1137 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1138                         struct intel_shared_dpll *pll,
1139                         bool state);
1140 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1141 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1142 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1143                                                 struct intel_crtc_state *state);
1144
1145 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1146                       const struct dpll *dpll);
1147 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1148
1149 /* modesetting asserts */
1150 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1151                            enum pipe pipe);
1152 void assert_pll(struct drm_i915_private *dev_priv,
1153                 enum pipe pipe, bool state);
1154 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1155 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1156 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1157                        enum pipe pipe, bool state);
1158 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1159 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1160 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1161 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1162 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1163 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1164                                              int *x, int *y,
1165                                              unsigned int tiling_mode,
1166                                              unsigned int bpp,
1167                                              unsigned int pitch);
1168 void intel_prepare_reset(struct drm_device *dev);
1169 void intel_finish_reset(struct drm_device *dev);
1170 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1171 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1172 void broxton_init_cdclk(struct drm_device *dev);
1173 void broxton_uninit_cdclk(struct drm_device *dev);
1174 void broxton_ddi_phy_init(struct drm_device *dev);
1175 void broxton_ddi_phy_uninit(struct drm_device *dev);
1176 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1177 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1178 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1179 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1180 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1181 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1182 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1183 void intel_dp_get_m_n(struct intel_crtc *crtc,
1184                       struct intel_crtc_state *pipe_config);
1185 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1186 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1187 void
1188 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1189                                 int dotclock);
1190 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1191                         intel_clock_t *best_clock);
1192 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1193
1194 bool intel_crtc_active(struct drm_crtc *crtc);
1195 void hsw_enable_ips(struct intel_crtc *crtc);
1196 void hsw_disable_ips(struct intel_crtc *crtc);
1197 enum intel_display_power_domain
1198 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1199 enum intel_display_power_domain
1200 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1201 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1202                                  struct intel_crtc_state *pipe_config);
1203 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1204
1205 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1206 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1207
1208 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1209                            struct drm_i915_gem_object *obj,
1210                            unsigned int plane);
1211
1212 u32 skl_plane_ctl_format(uint32_t pixel_format);
1213 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1214 u32 skl_plane_ctl_rotation(unsigned int rotation);
1215
1216 /* intel_csr.c */
1217 void intel_csr_ucode_init(struct drm_i915_private *);
1218 void intel_csr_load_program(struct drm_i915_private *);
1219 void intel_csr_ucode_fini(struct drm_i915_private *);
1220
1221 /* intel_dp.c */
1222 void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1223 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1224                              struct intel_connector *intel_connector);
1225 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1226                               const struct intel_crtc_state *pipe_config);
1227 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1228 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1229 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1230 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1231 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1232 bool intel_dp_compute_config(struct intel_encoder *encoder,
1233                              struct intel_crtc_state *pipe_config);
1234 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1235 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1236                                   bool long_hpd);
1237 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1238 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1239 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1240 void intel_edp_panel_on(struct intel_dp *intel_dp);
1241 void intel_edp_panel_off(struct intel_dp *intel_dp);
1242 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1243 void intel_dp_mst_suspend(struct drm_device *dev);
1244 void intel_dp_mst_resume(struct drm_device *dev);
1245 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1246 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1247 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1248 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1249 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1250 void intel_plane_destroy(struct drm_plane *plane);
1251 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1252 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1253 void intel_edp_drrs_invalidate(struct drm_device *dev,
1254                 unsigned frontbuffer_bits);
1255 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1256 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1257                                          struct intel_digital_port *port);
1258 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1259
1260 void
1261 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1262                                        uint8_t dp_train_pat);
1263 void
1264 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1265 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1266 uint8_t
1267 intel_dp_voltage_max(struct intel_dp *intel_dp);
1268 uint8_t
1269 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1270 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1271                            uint8_t *link_bw, uint8_t *rate_select);
1272 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1273 bool
1274 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1275
1276 /* intel_dp_mst.c */
1277 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1278 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1279 /* intel_dsi.c */
1280 void intel_dsi_init(struct drm_device *dev);
1281
1282
1283 /* intel_dvo.c */
1284 void intel_dvo_init(struct drm_device *dev);
1285
1286
1287 /* legacy fbdev emulation in intel_fbdev.c */
1288 #ifdef CONFIG_DRM_FBDEV_EMULATION
1289 extern int intel_fbdev_init(struct drm_device *dev);
1290 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1291 extern void intel_fbdev_fini(struct drm_device *dev);
1292 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1293 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1294 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1295 #else
1296 static inline int intel_fbdev_init(struct drm_device *dev)
1297 {
1298         return 0;
1299 }
1300
1301 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1302 {
1303 }
1304
1305 static inline void intel_fbdev_fini(struct drm_device *dev)
1306 {
1307 }
1308
1309 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1310 {
1311 }
1312
1313 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1314 {
1315 }
1316 #endif
1317
1318 /* intel_fbc.c */
1319 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1320 void intel_fbc_update(struct drm_i915_private *dev_priv);
1321 void intel_fbc_init(struct drm_i915_private *dev_priv);
1322 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1323 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1324 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1325                           unsigned int frontbuffer_bits,
1326                           enum fb_op_origin origin);
1327 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1328                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1329 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1330
1331 /* intel_hdmi.c */
1332 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1333 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1334                                struct intel_connector *intel_connector);
1335 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1336 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1337                                struct intel_crtc_state *pipe_config);
1338
1339
1340 /* intel_lvds.c */
1341 void intel_lvds_init(struct drm_device *dev);
1342 bool intel_is_dual_link_lvds(struct drm_device *dev);
1343
1344
1345 /* intel_modes.c */
1346 int intel_connector_update_modes(struct drm_connector *connector,
1347                                  struct edid *edid);
1348 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1349 void intel_attach_force_audio_property(struct drm_connector *connector);
1350 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1351 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1352
1353
1354 /* intel_overlay.c */
1355 void intel_setup_overlay(struct drm_device *dev);
1356 void intel_cleanup_overlay(struct drm_device *dev);
1357 int intel_overlay_switch_off(struct intel_overlay *overlay);
1358 int intel_overlay_put_image(struct drm_device *dev, void *data,
1359                             struct drm_file *file_priv);
1360 int intel_overlay_attrs(struct drm_device *dev, void *data,
1361                         struct drm_file *file_priv);
1362 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1363
1364
1365 /* intel_panel.c */
1366 int intel_panel_init(struct intel_panel *panel,
1367                      struct drm_display_mode *fixed_mode,
1368                      struct drm_display_mode *downclock_mode);
1369 void intel_panel_fini(struct intel_panel *panel);
1370 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1371                             struct drm_display_mode *adjusted_mode);
1372 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1373                              struct intel_crtc_state *pipe_config,
1374                              int fitting_mode);
1375 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1376                               struct intel_crtc_state *pipe_config,
1377                               int fitting_mode);
1378 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1379                                     u32 level, u32 max);
1380 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1381 void intel_panel_enable_backlight(struct intel_connector *connector);
1382 void intel_panel_disable_backlight(struct intel_connector *connector);
1383 void intel_panel_destroy_backlight(struct drm_connector *connector);
1384 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1385 extern struct drm_display_mode *intel_find_panel_downclock(
1386                                 struct drm_device *dev,
1387                                 struct drm_display_mode *fixed_mode,
1388                                 struct drm_connector *connector);
1389 void intel_backlight_register(struct drm_device *dev);
1390 void intel_backlight_unregister(struct drm_device *dev);
1391
1392
1393 /* intel_psr.c */
1394 void intel_psr_enable(struct intel_dp *intel_dp);
1395 void intel_psr_disable(struct intel_dp *intel_dp);
1396 void intel_psr_invalidate(struct drm_device *dev,
1397                           unsigned frontbuffer_bits);
1398 void intel_psr_flush(struct drm_device *dev,
1399                      unsigned frontbuffer_bits,
1400                      enum fb_op_origin origin);
1401 void intel_psr_init(struct drm_device *dev);
1402 void intel_psr_single_frame_update(struct drm_device *dev,
1403                                    unsigned frontbuffer_bits);
1404
1405 /* intel_runtime_pm.c */
1406 int intel_power_domains_init(struct drm_i915_private *);
1407 void intel_power_domains_fini(struct drm_i915_private *);
1408 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1409 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1410 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1411 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1412 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1413
1414 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1415                                     enum intel_display_power_domain domain);
1416 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1417                                       enum intel_display_power_domain domain);
1418 void intel_display_power_get(struct drm_i915_private *dev_priv,
1419                              enum intel_display_power_domain domain);
1420 void intel_display_power_put(struct drm_i915_private *dev_priv,
1421                              enum intel_display_power_domain domain);
1422 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1423 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1424 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1425
1426 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1427
1428 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1429                              bool override, unsigned int mask);
1430 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1431                           enum dpio_channel ch, bool override);
1432
1433
1434 /* intel_pm.c */
1435 void intel_init_clock_gating(struct drm_device *dev);
1436 void intel_suspend_hw(struct drm_device *dev);
1437 int ilk_wm_max_level(const struct drm_device *dev);
1438 void intel_update_watermarks(struct drm_crtc *crtc);
1439 void intel_init_pm(struct drm_device *dev);
1440 void intel_pm_setup(struct drm_device *dev);
1441 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1442 void intel_gpu_ips_teardown(void);
1443 void intel_init_gt_powersave(struct drm_device *dev);
1444 void intel_cleanup_gt_powersave(struct drm_device *dev);
1445 void intel_enable_gt_powersave(struct drm_device *dev);
1446 void intel_disable_gt_powersave(struct drm_device *dev);
1447 void intel_suspend_gt_powersave(struct drm_device *dev);
1448 void intel_reset_gt_powersave(struct drm_device *dev);
1449 void gen6_update_ring_freq(struct drm_device *dev);
1450 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1451 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1452 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1453 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1454                     struct intel_rps_client *rps,
1455                     unsigned long submitted);
1456 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1457                                        struct drm_i915_gem_request *req);
1458 void vlv_wm_get_hw_state(struct drm_device *dev);
1459 void ilk_wm_get_hw_state(struct drm_device *dev);
1460 void skl_wm_get_hw_state(struct drm_device *dev);
1461 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1462                           struct skl_ddb_allocation *ddb /* out */);
1463 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1464
1465 /* intel_sdvo.c */
1466 bool intel_sdvo_init(struct drm_device *dev,
1467                      i915_reg_t reg, enum port port);
1468
1469
1470 /* intel_sprite.c */
1471 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1472 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1473                               struct drm_file *file_priv);
1474 void intel_pipe_update_start(struct intel_crtc *crtc);
1475 void intel_pipe_update_end(struct intel_crtc *crtc);
1476
1477 /* intel_tv.c */
1478 void intel_tv_init(struct drm_device *dev);
1479
1480 /* intel_atomic.c */
1481 int intel_connector_atomic_get_property(struct drm_connector *connector,
1482                                         const struct drm_connector_state *state,
1483                                         struct drm_property *property,
1484                                         uint64_t *val);
1485 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1486 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1487                                struct drm_crtc_state *state);
1488 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1489 void intel_atomic_state_clear(struct drm_atomic_state *);
1490 struct intel_shared_dpll_config *
1491 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1492
1493 static inline struct intel_crtc_state *
1494 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1495                             struct intel_crtc *crtc)
1496 {
1497         struct drm_crtc_state *crtc_state;
1498         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1499         if (IS_ERR(crtc_state))
1500                 return ERR_CAST(crtc_state);
1501
1502         return to_intel_crtc_state(crtc_state);
1503 }
1504 int intel_atomic_setup_scalers(struct drm_device *dev,
1505         struct intel_crtc *intel_crtc,
1506         struct intel_crtc_state *crtc_state);
1507
1508 /* intel_atomic_plane.c */
1509 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1510 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1511 void intel_plane_destroy_state(struct drm_plane *plane,
1512                                struct drm_plane_state *state);
1513 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1514
1515 #endif /* __INTEL_DRV_H__ */