2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 * TODO: When modesetting has fully transitioned to atomic, the below
49 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
52 #define _wait_for(COND, US, W) ({ \
53 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
56 if (time_after(jiffies, timeout__)) { \
61 if ((W) && drm_can_sleep()) { \
62 usleep_range((W), (W)*2); \
70 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
71 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
80 #define _wait_for_atomic(COND, US) ({ \
81 unsigned long end__; \
83 _WAIT_FOR_ATOMIC_CHECK; \
84 BUILD_BUG_ON((US) > 50000); \
85 end__ = (local_clock() >> 10) + (US) + 1; \
87 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
88 /* Unlike the regular wait_for(), this atomic variant \
89 * cannot be preempted (and we'll just ignore the issue\
90 * of irq interruptions) and so we know that no time \
91 * has passed since the last check of COND and can \
92 * immediately report the timeout. \
102 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
103 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
105 #define KHz(x) (1000 * (x))
106 #define MHz(x) KHz(1000 * (x))
109 * Display related stuff
112 /* store information about an Ixxx DVO */
113 /* The i830->i865 use multiple DVOs with multiple i2cs */
114 /* the i915, i945 have a single sDVO i2c bus - which is different */
115 #define MAX_OUTPUTS 6
116 /* maximum connectors per crtcs in the mode set */
118 /* Maximum cursor sizes */
119 #define GEN2_CURSOR_WIDTH 64
120 #define GEN2_CURSOR_HEIGHT 64
121 #define MAX_CURSOR_WIDTH 256
122 #define MAX_CURSOR_HEIGHT 256
124 #define INTEL_I2C_BUS_DVO 1
125 #define INTEL_I2C_BUS_SDVO 2
127 /* these are outputs from the chip - integrated only
128 external chips are via DVO or SDVO output */
129 enum intel_output_type
{
130 INTEL_OUTPUT_UNUSED
= 0,
131 INTEL_OUTPUT_ANALOG
= 1,
132 INTEL_OUTPUT_DVO
= 2,
133 INTEL_OUTPUT_SDVO
= 3,
134 INTEL_OUTPUT_LVDS
= 4,
135 INTEL_OUTPUT_TVOUT
= 5,
136 INTEL_OUTPUT_HDMI
= 6,
137 INTEL_OUTPUT_DISPLAYPORT
= 7,
138 INTEL_OUTPUT_EDP
= 8,
139 INTEL_OUTPUT_DSI
= 9,
140 INTEL_OUTPUT_UNKNOWN
= 10,
141 INTEL_OUTPUT_DP_MST
= 11,
144 #define INTEL_DVO_CHIP_NONE 0
145 #define INTEL_DVO_CHIP_LVDS 1
146 #define INTEL_DVO_CHIP_TMDS 2
147 #define INTEL_DVO_CHIP_TVOUT 4
149 #define INTEL_DSI_VIDEO_MODE 0
150 #define INTEL_DSI_COMMAND_MODE 1
152 struct intel_framebuffer
{
153 struct drm_framebuffer base
;
154 struct drm_i915_gem_object
*obj
;
155 struct intel_rotation_info rot_info
;
159 struct drm_fb_helper helper
;
160 struct intel_framebuffer
*fb
;
164 struct intel_encoder
{
165 struct drm_encoder base
;
167 enum intel_output_type type
;
168 unsigned int cloneable
;
169 void (*hot_plug
)(struct intel_encoder
*);
170 bool (*compute_config
)(struct intel_encoder
*,
171 struct intel_crtc_state
*);
172 void (*pre_pll_enable
)(struct intel_encoder
*);
173 void (*pre_enable
)(struct intel_encoder
*);
174 void (*enable
)(struct intel_encoder
*);
175 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
176 void (*disable
)(struct intel_encoder
*);
177 void (*post_disable
)(struct intel_encoder
*);
178 void (*post_pll_disable
)(struct intel_encoder
*);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config
)(struct intel_encoder
*,
188 struct intel_crtc_state
*pipe_config
);
190 * Called during system suspend after all pending requests for the
191 * encoder are flushed (for example for DP AUX transactions) and
192 * device interrupts are disabled.
194 void (*suspend
)(struct intel_encoder
*);
196 enum hpd_pin hpd_pin
;
200 struct drm_display_mode
*fixed_mode
;
201 struct drm_display_mode
*downclock_mode
;
211 bool combination_mode
; /* gen 2/4 only */
215 bool util_pin_active_low
; /* bxt+ */
216 u8 controller
; /* bxt+ only */
217 struct pwm_device
*pwm
;
219 struct backlight_device
*device
;
221 /* Connector and platform specific backlight functions */
222 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
223 uint32_t (*get
)(struct intel_connector
*connector
);
224 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
225 void (*disable
)(struct intel_connector
*connector
);
226 void (*enable
)(struct intel_connector
*connector
);
227 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
229 void (*power
)(struct intel_connector
*, bool enable
);
233 struct intel_connector
{
234 struct drm_connector base
;
236 * The fixed encoder this connector is connected to.
238 struct intel_encoder
*encoder
;
240 /* Reads out the current hw, returning true if the connector is enabled
241 * and active (i.e. dpms ON state). */
242 bool (*get_hw_state
)(struct intel_connector
*);
245 * Removes all interfaces through which the connector is accessible
246 * - like sysfs, debugfs entries -, so that no new operations can be
247 * started on the connector. Also makes sure all currently pending
248 * operations finish before returing.
250 void (*unregister
)(struct intel_connector
*);
252 /* Panel info for eDP and LVDS */
253 struct intel_panel panel
;
255 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
257 struct edid
*detect_edid
;
259 /* since POLL and HPD connectors may use the same HPD line keep the native
260 state of connector->polled in case hotplug storm detection changes it */
263 void *port
; /* store this opaque as its illegal to dereference it */
265 struct intel_dp
*mst_port
;
268 typedef struct dpll
{
280 struct intel_atomic_state
{
281 struct drm_atomic_state base
;
286 * Calculated device cdclk, can be different from cdclk
287 * only when all crtc's are DPMS off.
289 unsigned int dev_cdclk
;
291 bool dpll_set
, modeset
;
293 unsigned int active_crtcs
;
294 unsigned int min_pixclk
[I915_MAX_PIPES
];
296 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
297 struct intel_wm_config wm_config
;
300 * Current watermarks can't be trusted during hardware readout, so
301 * don't bother calculating intermediate watermarks.
303 bool skip_intermediate_wm
;
306 struct intel_plane_state
{
307 struct drm_plane_state base
;
310 struct drm_rect clip
;
315 * = -1 : not using a scaler
316 * >= 0 : using a scalers
318 * plane requiring a scaler:
319 * - During check_plane, its bit is set in
320 * crtc_state->scaler_state.scaler_users by calling helper function
321 * update_scaler_plane.
322 * - scaler_id indicates the scaler it got assigned.
324 * plane doesn't require a scaler:
325 * - this can happen when scaling is no more required or plane simply
327 * - During check_plane, corresponding bit is reset in
328 * crtc_state->scaler_state.scaler_users by calling helper function
329 * update_scaler_plane.
333 struct drm_intel_sprite_colorkey ckey
;
335 /* async flip related structures */
336 struct drm_i915_gem_request
*wait_req
;
339 struct intel_initial_plane_config
{
340 struct intel_framebuffer
*fb
;
346 #define SKL_MIN_SRC_W 8
347 #define SKL_MAX_SRC_W 4096
348 #define SKL_MIN_SRC_H 8
349 #define SKL_MAX_SRC_H 4096
350 #define SKL_MIN_DST_W 8
351 #define SKL_MAX_DST_W 4096
352 #define SKL_MIN_DST_H 8
353 #define SKL_MAX_DST_H 4096
355 struct intel_scaler
{
360 struct intel_crtc_scaler_state
{
361 #define SKL_NUM_SCALERS 2
362 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
365 * scaler_users: keeps track of users requesting scalers on this crtc.
367 * If a bit is set, a user is using a scaler.
368 * Here user can be a plane or crtc as defined below:
369 * bits 0-30 - plane (bit position is index from drm_plane_index)
372 * Instead of creating a new index to cover planes and crtc, using
373 * existing drm_plane_index for planes which is well less than 31
374 * planes and bit 31 for crtc. This should be fine to cover all
377 * intel_atomic_setup_scalers will setup available scalers to users
378 * requesting scalers. It will gracefully fail if request exceeds
381 #define SKL_CRTC_INDEX 31
382 unsigned scaler_users
;
384 /* scaler used by crtc for panel fitting purpose */
388 /* drm_mode->private_flags */
389 #define I915_MODE_FLAG_INHERITED 1
391 struct intel_pipe_wm
{
392 struct intel_wm_level wm
[5];
393 struct intel_wm_level raw_wm
[5];
397 bool sprites_enabled
;
402 struct skl_wm_level wm
[8];
403 struct skl_wm_level trans_wm
;
407 struct intel_crtc_state
{
408 struct drm_crtc_state base
;
411 * quirks - bitfield with hw state readout quirks
413 * For various reasons the hw state readout code might not be able to
414 * completely faithfully read out the current state. These cases are
415 * tracked with quirk flags so that fastboot and state checker can act
418 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
419 unsigned long quirks
;
421 unsigned fb_bits
; /* framebuffers to flip */
422 bool update_pipe
; /* can a fast modeset be performed? */
424 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
425 bool fb_changed
; /* fb on any of the planes is changed */
427 /* Pipe source size (ie. panel fitter input size)
428 * All planes will be positioned inside this space,
429 * and get clipped at the edges. */
430 int pipe_src_w
, pipe_src_h
;
432 /* Whether to set up the PCH/FDI. Note that we never allow sharing
433 * between pch encoders and cpu encoders. */
434 bool has_pch_encoder
;
436 /* Are we sending infoframes on the attached port */
439 /* CPU Transcoder for the pipe. Currently this can only differ from the
440 * pipe on Haswell (where we have a special eDP transcoder). */
441 enum transcoder cpu_transcoder
;
444 * Use reduced/limited/broadcast rbg range, compressing from the full
445 * range fed into the crtcs.
447 bool limited_color_range
;
449 /* DP has a bunch of special case unfortunately, so mark the pipe
453 /* DSI has special cases */
454 bool has_dsi_encoder
;
456 /* Whether we should send NULL infoframes. Required for audio. */
459 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
460 * has_dp_encoder is set. */
464 * Enable dithering, used when the selected pipe bpp doesn't match the
469 /* Controls for the clock computation, to override various stages. */
472 /* SDVO TV has a bunch of special case. To make multifunction encoders
473 * work correctly, we need to track this at runtime.*/
477 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
478 * required. This is set in the 2nd loop of calling encoder's
479 * ->compute_config if the first pick doesn't work out.
483 /* Settings for the intel dpll used on pretty much everything but
487 /* Selected dpll when shared or NULL. */
488 struct intel_shared_dpll
*shared_dpll
;
491 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
492 * - enum skl_dpll on SKL
494 uint32_t ddi_pll_sel
;
496 /* Actual register state of the dpll, for shared dpll cross-checking. */
497 struct intel_dpll_hw_state dpll_hw_state
;
500 struct intel_link_m_n dp_m_n
;
502 /* m2_n2 for eDP downclock */
503 struct intel_link_m_n dp_m2_n2
;
507 * Frequence the dpll for the port should run at. Differs from the
508 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
509 * already multiplied by pixel_multiplier.
513 /* Used by SDVO (and if we ever fix it, HDMI). */
514 unsigned pixel_multiplier
;
518 /* Panel fitter controls for gen2-gen4 + VLV */
522 u32 lvds_border_bits
;
525 /* Panel fitter placement and size for Ironlake+ */
533 /* FDI configuration, only valid if has_pch_encoder is set. */
535 struct intel_link_m_n fdi_m_n
;
543 bool dp_encoder_is_mst
;
546 struct intel_crtc_scaler_state scaler_state
;
548 /* w/a for waiting 2 vblanks during crtc enable */
549 enum pipe hsw_workaround_pipe
;
551 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
556 * Optimal watermarks, programmed post-vblank when this state
560 struct intel_pipe_wm ilk
;
561 struct skl_pipe_wm skl
;
565 * Intermediate watermarks; these can be programmed immediately
566 * since they satisfy both the current configuration we're
567 * switching away from and the new configuration we're switching
570 struct intel_pipe_wm intermediate
;
573 * Platforms with two-step watermark programming will need to
574 * update watermark programming post-vblank to switch from the
575 * safe intermediate watermarks to the optimal final
578 bool need_postvbl_update
;
582 struct vlv_wm_state
{
583 struct vlv_pipe_wm wm
[3];
584 struct vlv_sr_wm sr
[3];
585 uint8_t num_active_planes
;
591 struct intel_mmio_flip
{
592 struct work_struct work
;
593 struct drm_i915_private
*i915
;
594 struct drm_i915_gem_request
*req
;
595 struct intel_crtc
*crtc
;
596 unsigned int rotation
;
600 struct drm_crtc base
;
603 u8 lut_r
[256], lut_g
[256], lut_b
[256];
605 * Whether the crtc and the connected output pipeline is active. Implies
606 * that crtc->enabled is set, i.e. the current mode configuration has
607 * some outputs connected to this crtc.
610 unsigned long enabled_power_domains
;
612 struct intel_overlay
*overlay
;
613 struct intel_unpin_work
*unpin_work
;
615 atomic_t unpin_work_count
;
617 /* Display surface base address adjustement for pageflips. Note that on
618 * gen4+ this only adjusts up to a tile, offsets within a tile are
619 * handled in the hw itself (with the TILEOFF register). */
624 uint32_t cursor_addr
;
625 uint32_t cursor_cntl
;
626 uint32_t cursor_size
;
627 uint32_t cursor_base
;
629 struct intel_crtc_state
*config
;
631 /* reset counter value when the last flip was submitted */
632 unsigned int reset_counter
;
634 /* Access to these should be protected by dev_priv->irq_lock. */
635 bool cpu_fifo_underrun_disabled
;
636 bool pch_fifo_underrun_disabled
;
638 /* per-pipe watermark state */
640 /* watermarks currently being used */
642 struct intel_pipe_wm ilk
;
643 struct skl_pipe_wm skl
;
646 /* allow CxSR on this pipe */
653 unsigned start_vbl_count
;
654 ktime_t start_vbl_time
;
655 int min_vbl
, max_vbl
;
659 /* scalers available on this crtc */
662 struct vlv_wm_state wm_state
;
665 struct intel_plane_wm_parameters
{
666 uint32_t horiz_pixels
;
667 uint32_t vert_pixels
;
669 * For packed pixel formats:
670 * bytes_per_pixel - holds bytes per pixel
671 * For planar pixel formats:
672 * bytes_per_pixel - holds bytes per pixel for uv-plane
673 * y_bytes_per_pixel - holds bytes per pixel for y-plane
675 uint8_t bytes_per_pixel
;
676 uint8_t y_bytes_per_pixel
;
680 unsigned int rotation
;
685 struct drm_plane base
;
690 uint32_t frontbuffer_bit
;
692 /* Since we need to change the watermarks before/after
693 * enabling/disabling the planes, we need to store the parameters here
694 * as the other pieces of the struct may not reflect the values we want
695 * for the watermark calculations. Currently only Haswell uses this.
697 struct intel_plane_wm_parameters wm
;
700 * NOTE: Do not place new plane state fields here (e.g., when adding
701 * new plane properties). New runtime state should now be placed in
702 * the intel_plane_state structure and accessed via plane_state.
705 void (*update_plane
)(struct drm_plane
*plane
,
706 const struct intel_crtc_state
*crtc_state
,
707 const struct intel_plane_state
*plane_state
);
708 void (*disable_plane
)(struct drm_plane
*plane
,
709 struct drm_crtc
*crtc
);
710 int (*check_plane
)(struct drm_plane
*plane
,
711 struct intel_crtc_state
*crtc_state
,
712 struct intel_plane_state
*state
);
715 struct intel_watermark_params
{
716 unsigned long fifo_size
;
717 unsigned long max_wm
;
718 unsigned long default_wm
;
719 unsigned long guard_size
;
720 unsigned long cacheline_size
;
723 struct cxsr_latency
{
726 unsigned long fsb_freq
;
727 unsigned long mem_freq
;
728 unsigned long display_sr
;
729 unsigned long display_hpll_disable
;
730 unsigned long cursor_sr
;
731 unsigned long cursor_hpll_disable
;
734 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
735 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
736 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
737 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
738 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
739 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
740 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
741 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
742 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
747 bool limited_color_range
;
748 bool color_range_auto
;
751 enum hdmi_force_audio force_audio
;
752 bool rgb_quant_range_selectable
;
753 enum hdmi_picture_aspect aspect_ratio
;
754 struct intel_connector
*attached_connector
;
755 void (*write_infoframe
)(struct drm_encoder
*encoder
,
756 enum hdmi_infoframe_type type
,
757 const void *frame
, ssize_t len
);
758 void (*set_infoframes
)(struct drm_encoder
*encoder
,
760 const struct drm_display_mode
*adjusted_mode
);
761 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
762 const struct intel_crtc_state
*pipe_config
);
765 struct intel_dp_mst_encoder
;
766 #define DP_MAX_DOWNSTREAM_PORTS 0x10
770 * When platform provides two set of M_N registers for dp, we can
771 * program them and switch between them incase of DRRS.
772 * But When only one such register is provided, we have to program the
773 * required divider value on that registers itself based on the DRRS state.
775 * M1_N1 : Program dp_m_n on M1_N1 registers
776 * dp_m2_n2 on M2_N2 registers (If supported)
778 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
779 * M2_N2 registers are not supported
783 /* Sets the m1_n1 and m2_n2 */
789 i915_reg_t output_reg
;
790 i915_reg_t aux_ch_ctl_reg
;
791 i915_reg_t aux_ch_data_reg
[5];
796 enum hdmi_force_audio force_audio
;
797 bool limited_color_range
;
798 bool color_range_auto
;
799 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
800 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
801 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
802 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
803 uint8_t num_sink_rates
;
804 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
805 struct drm_dp_aux aux
;
806 uint8_t train_set
[4];
807 int panel_power_up_delay
;
808 int panel_power_down_delay
;
809 int panel_power_cycle_delay
;
810 int backlight_on_delay
;
811 int backlight_off_delay
;
812 struct delayed_work panel_vdd_work
;
814 unsigned long last_power_on
;
815 unsigned long last_backlight_off
;
816 ktime_t panel_power_off_time
;
818 struct notifier_block edp_notifier
;
821 * Pipe whose power sequencer is currently locked into
822 * this port. Only relevant on VLV/CHV.
825 struct edp_power_seq pps_delays
;
827 bool can_mst
; /* this port supports mst */
829 int active_mst_links
;
830 /* connector directly attached - won't be use for modeset in mst world */
831 struct intel_connector
*attached_connector
;
833 /* mst connector list */
834 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
835 struct drm_dp_mst_topology_mgr mst_mgr
;
837 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
839 * This function returns the value we have to program the AUX_CTL
840 * register with to kick off an AUX transaction.
842 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
845 uint32_t aux_clock_divider
);
847 /* This is called before a link training is starterd */
848 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
850 bool train_set_valid
;
852 /* Displayport compliance testing */
853 unsigned long compliance_test_type
;
854 unsigned long compliance_test_data
;
855 bool compliance_test_active
;
858 struct intel_digital_port
{
859 struct intel_encoder base
;
863 struct intel_hdmi hdmi
;
864 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
865 bool release_cl2_override
;
867 /* for communication with audio component; protected by av_mutex */
868 const struct drm_connector
*audio_connector
;
871 struct intel_dp_mst_encoder
{
872 struct intel_encoder base
;
874 struct intel_digital_port
*primary
;
875 void *port
; /* store this opaque as its illegal to dereference it */
878 static inline enum dpio_channel
879 vlv_dport_to_channel(struct intel_digital_port
*dport
)
881 switch (dport
->port
) {
892 static inline enum dpio_phy
893 vlv_dport_to_phy(struct intel_digital_port
*dport
)
895 switch (dport
->port
) {
906 static inline enum dpio_channel
907 vlv_pipe_to_channel(enum pipe pipe
)
920 static inline struct drm_crtc
*
921 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
924 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
927 static inline struct drm_crtc
*
928 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
931 return dev_priv
->plane_to_crtc_mapping
[plane
];
934 struct intel_unpin_work
{
935 struct work_struct work
;
936 struct drm_crtc
*crtc
;
937 struct drm_framebuffer
*old_fb
;
938 struct drm_i915_gem_object
*pending_flip_obj
;
939 struct drm_pending_vblank_event
*event
;
941 #define INTEL_FLIP_INACTIVE 0
942 #define INTEL_FLIP_PENDING 1
943 #define INTEL_FLIP_COMPLETE 2
946 struct drm_i915_gem_request
*flip_queued_req
;
947 u32 flip_queued_vblank
;
948 u32 flip_ready_vblank
;
949 bool enable_stall_check
;
952 struct intel_load_detect_pipe
{
953 struct drm_atomic_state
*restore_state
;
956 static inline struct intel_encoder
*
957 intel_attached_encoder(struct drm_connector
*connector
)
959 return to_intel_connector(connector
)->encoder
;
962 static inline struct intel_digital_port
*
963 enc_to_dig_port(struct drm_encoder
*encoder
)
965 return container_of(encoder
, struct intel_digital_port
, base
.base
);
968 static inline struct intel_dp_mst_encoder
*
969 enc_to_mst(struct drm_encoder
*encoder
)
971 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
974 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
976 return &enc_to_dig_port(encoder
)->dp
;
979 static inline struct intel_digital_port
*
980 dp_to_dig_port(struct intel_dp
*intel_dp
)
982 return container_of(intel_dp
, struct intel_digital_port
, dp
);
985 static inline struct intel_digital_port
*
986 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
988 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
992 * Returns the number of planes for this pipe, ie the number of sprites + 1
993 * (primary plane). This doesn't count the cursor plane then.
995 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
997 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
1000 /* intel_fifo_underrun.c */
1001 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1002 enum pipe pipe
, bool enable
);
1003 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1004 enum transcoder pch_transcoder
,
1006 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1008 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1009 enum transcoder pch_transcoder
);
1010 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1011 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1014 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1015 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1016 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1017 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1018 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
1019 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
1020 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
1021 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
1022 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1023 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1024 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1027 * We only use drm_irq_uninstall() at unload and VT switch, so
1028 * this is the only thing we need to check.
1030 return dev_priv
->pm
.irqs_enabled
;
1033 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1034 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1035 unsigned int pipe_mask
);
1036 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1037 unsigned int pipe_mask
);
1040 void intel_crt_init(struct drm_device
*dev
);
1044 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1045 const struct intel_crtc_state
*pipe_config
);
1046 void intel_prepare_ddi_buffer(struct intel_encoder
*encoder
);
1047 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1048 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1049 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1050 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1051 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1052 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1053 enum transcoder cpu_transcoder
);
1054 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1055 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1056 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1057 struct intel_crtc_state
*crtc_state
);
1058 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1059 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1060 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1061 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
1062 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1063 struct intel_crtc
*intel_crtc
);
1064 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1065 struct intel_crtc_state
*pipe_config
);
1066 struct intel_encoder
*
1067 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1069 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1070 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1071 struct intel_crtc_state
*pipe_config
);
1072 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1073 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1075 /* intel_frontbuffer.c */
1076 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
1077 enum fb_op_origin origin
);
1078 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
1079 unsigned frontbuffer_bits
);
1080 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
1081 unsigned frontbuffer_bits
);
1082 void intel_frontbuffer_flip(struct drm_device
*dev
,
1083 unsigned frontbuffer_bits
);
1084 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1085 unsigned int height
,
1086 uint32_t pixel_format
,
1087 uint64_t fb_format_modifier
);
1088 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
,
1089 enum fb_op_origin origin
);
1090 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
1091 uint64_t fb_modifier
, uint32_t pixel_format
);
1094 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1095 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
1096 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1097 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1098 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1100 /* intel_display.c */
1101 extern const struct drm_plane_funcs intel_plane_funcs
;
1102 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1103 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1104 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1105 void intel_mark_busy(struct drm_device
*dev
);
1106 void intel_mark_idle(struct drm_device
*dev
);
1107 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1108 int intel_display_suspend(struct drm_device
*dev
);
1109 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1110 int intel_connector_init(struct intel_connector
*);
1111 struct intel_connector
*intel_connector_alloc(void);
1112 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1113 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1114 struct intel_encoder
*encoder
);
1115 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
1116 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1117 struct drm_crtc
*crtc
);
1118 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1119 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1120 struct drm_file
*file_priv
);
1121 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1123 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
1125 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1127 drm_wait_one_vblank(dev
, pipe
);
1130 intel_wait_for_vblank_if_active(struct drm_device
*dev
, int pipe
)
1132 const struct intel_crtc
*crtc
=
1133 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1136 intel_wait_for_vblank(dev
, pipe
);
1138 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1139 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1140 struct intel_digital_port
*dport
,
1141 unsigned int expected_mask
);
1142 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1143 struct drm_display_mode
*mode
,
1144 struct intel_load_detect_pipe
*old
,
1145 struct drm_modeset_acquire_ctx
*ctx
);
1146 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1147 struct intel_load_detect_pipe
*old
,
1148 struct drm_modeset_acquire_ctx
*ctx
);
1149 int intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1150 unsigned int rotation
);
1151 struct drm_framebuffer
*
1152 __intel_framebuffer_create(struct drm_device
*dev
,
1153 struct drm_mode_fb_cmd2
*mode_cmd
,
1154 struct drm_i915_gem_object
*obj
);
1155 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
1156 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
1157 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
1158 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
1159 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1160 const struct drm_plane_state
*new_state
);
1161 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1162 const struct drm_plane_state
*old_state
);
1163 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1164 const struct drm_plane_state
*state
,
1165 struct drm_property
*property
,
1167 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1168 struct drm_plane_state
*state
,
1169 struct drm_property
*property
,
1171 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1172 struct drm_plane_state
*plane_state
);
1174 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
1175 uint64_t fb_modifier
, unsigned int cpp
);
1178 intel_rotation_90_or_270(unsigned int rotation
)
1180 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1183 void intel_create_rotation_property(struct drm_device
*dev
,
1184 struct intel_plane
*plane
);
1186 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1189 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1190 const struct dpll
*dpll
);
1191 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1192 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1194 /* modesetting asserts */
1195 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1197 void assert_pll(struct drm_i915_private
*dev_priv
,
1198 enum pipe pipe
, bool state
);
1199 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1200 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1201 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1202 enum pipe pipe
, bool state
);
1203 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1204 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1205 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1206 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1207 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1208 u32
intel_compute_tile_offset(int *x
, int *y
,
1209 const struct drm_framebuffer
*fb
, int plane
,
1211 unsigned int rotation
);
1212 void intel_prepare_reset(struct drm_device
*dev
);
1213 void intel_finish_reset(struct drm_device
*dev
);
1214 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1215 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1216 void broxton_init_cdclk(struct drm_device
*dev
);
1217 void broxton_uninit_cdclk(struct drm_device
*dev
);
1218 void broxton_ddi_phy_init(struct drm_device
*dev
);
1219 void broxton_ddi_phy_uninit(struct drm_device
*dev
);
1220 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1221 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1222 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1223 int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
1224 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1225 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1226 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1227 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1228 struct intel_crtc_state
*pipe_config
);
1229 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1230 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1231 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1232 intel_clock_t
*best_clock
);
1233 int chv_calc_dpll_params(int refclk
, intel_clock_t
*pll_clock
);
1235 bool intel_crtc_active(struct drm_crtc
*crtc
);
1236 void hsw_enable_ips(struct intel_crtc
*crtc
);
1237 void hsw_disable_ips(struct intel_crtc
*crtc
);
1238 enum intel_display_power_domain
1239 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1240 enum intel_display_power_domain
1241 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1242 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1243 struct intel_crtc_state
*pipe_config
);
1245 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1246 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1248 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1249 struct drm_i915_gem_object
*obj
,
1250 unsigned int plane
);
1252 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1253 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1254 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1257 void intel_csr_ucode_init(struct drm_i915_private
*);
1258 void intel_csr_load_program(struct drm_i915_private
*);
1259 void intel_csr_ucode_fini(struct drm_i915_private
*);
1262 void intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1263 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1264 struct intel_connector
*intel_connector
);
1265 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1266 const struct intel_crtc_state
*pipe_config
);
1267 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1268 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1269 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1270 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1271 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1272 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1273 struct intel_crtc_state
*pipe_config
);
1274 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1275 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1277 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1278 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1279 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1280 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1281 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1282 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1283 void intel_dp_mst_suspend(struct drm_device
*dev
);
1284 void intel_dp_mst_resume(struct drm_device
*dev
);
1285 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1286 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1287 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1288 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1289 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1290 void intel_plane_destroy(struct drm_plane
*plane
);
1291 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1292 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1293 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1294 unsigned frontbuffer_bits
);
1295 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1296 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1297 struct intel_digital_port
*port
);
1300 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1301 uint8_t dp_train_pat
);
1303 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1304 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1306 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1308 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1309 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1310 uint8_t *link_bw
, uint8_t *rate_select
);
1311 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1313 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1315 /* intel_dp_mst.c */
1316 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1317 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1319 void intel_dsi_init(struct drm_device
*dev
);
1323 void intel_dvo_init(struct drm_device
*dev
);
1326 /* legacy fbdev emulation in intel_fbdev.c */
1327 #ifdef CONFIG_DRM_FBDEV_EMULATION
1328 extern int intel_fbdev_init(struct drm_device
*dev
);
1329 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1330 extern void intel_fbdev_fini(struct drm_device
*dev
);
1331 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1332 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1333 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1335 static inline int intel_fbdev_init(struct drm_device
*dev
)
1340 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1344 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1348 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1352 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1358 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1359 struct drm_atomic_state
*state
);
1360 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1361 void intel_fbc_pre_update(struct intel_crtc
*crtc
);
1362 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1363 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1364 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1365 void intel_fbc_enable(struct intel_crtc
*crtc
);
1366 void intel_fbc_disable(struct intel_crtc
*crtc
);
1367 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1368 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1369 unsigned int frontbuffer_bits
,
1370 enum fb_op_origin origin
);
1371 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1372 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1373 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1376 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1377 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1378 struct intel_connector
*intel_connector
);
1379 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1380 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1381 struct intel_crtc_state
*pipe_config
);
1385 void intel_lvds_init(struct drm_device
*dev
);
1386 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1390 int intel_connector_update_modes(struct drm_connector
*connector
,
1392 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1393 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1394 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1395 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1398 /* intel_overlay.c */
1399 void intel_setup_overlay(struct drm_device
*dev
);
1400 void intel_cleanup_overlay(struct drm_device
*dev
);
1401 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1402 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1403 struct drm_file
*file_priv
);
1404 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1405 struct drm_file
*file_priv
);
1406 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1410 int intel_panel_init(struct intel_panel
*panel
,
1411 struct drm_display_mode
*fixed_mode
,
1412 struct drm_display_mode
*downclock_mode
);
1413 void intel_panel_fini(struct intel_panel
*panel
);
1414 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1415 struct drm_display_mode
*adjusted_mode
);
1416 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1417 struct intel_crtc_state
*pipe_config
,
1419 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1420 struct intel_crtc_state
*pipe_config
,
1422 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1423 u32 level
, u32 max
);
1424 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1425 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1426 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1427 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1428 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1429 extern struct drm_display_mode
*intel_find_panel_downclock(
1430 struct drm_device
*dev
,
1431 struct drm_display_mode
*fixed_mode
,
1432 struct drm_connector
*connector
);
1433 void intel_backlight_register(struct drm_device
*dev
);
1434 void intel_backlight_unregister(struct drm_device
*dev
);
1438 void intel_psr_enable(struct intel_dp
*intel_dp
);
1439 void intel_psr_disable(struct intel_dp
*intel_dp
);
1440 void intel_psr_invalidate(struct drm_device
*dev
,
1441 unsigned frontbuffer_bits
);
1442 void intel_psr_flush(struct drm_device
*dev
,
1443 unsigned frontbuffer_bits
,
1444 enum fb_op_origin origin
);
1445 void intel_psr_init(struct drm_device
*dev
);
1446 void intel_psr_single_frame_update(struct drm_device
*dev
,
1447 unsigned frontbuffer_bits
);
1449 /* intel_runtime_pm.c */
1450 int intel_power_domains_init(struct drm_i915_private
*);
1451 void intel_power_domains_fini(struct drm_i915_private
*);
1452 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1453 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1454 void skl_pw1_misc_io_init(struct drm_i915_private
*dev_priv
);
1455 void skl_pw1_misc_io_fini(struct drm_i915_private
*dev_priv
);
1456 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1458 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1460 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1461 enum intel_display_power_domain domain
);
1462 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1463 enum intel_display_power_domain domain
);
1464 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1465 enum intel_display_power_domain domain
);
1466 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1467 enum intel_display_power_domain domain
);
1468 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1469 enum intel_display_power_domain domain
);
1472 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1474 WARN_ONCE(dev_priv
->pm
.suspended
,
1475 "Device suspended during HW access\n");
1479 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1481 assert_rpm_device_not_suspended(dev_priv
);
1482 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1483 * too much noise. */
1484 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1485 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1489 assert_rpm_atomic_begin(struct drm_i915_private
*dev_priv
)
1491 int seq
= atomic_read(&dev_priv
->pm
.atomic_seq
);
1493 assert_rpm_wakelock_held(dev_priv
);
1499 assert_rpm_atomic_end(struct drm_i915_private
*dev_priv
, int begin_seq
)
1501 WARN_ONCE(atomic_read(&dev_priv
->pm
.atomic_seq
) != begin_seq
,
1502 "HW access outside of RPM atomic section\n");
1506 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1507 * @dev_priv: i915 device instance
1509 * This function disable asserts that check if we hold an RPM wakelock
1510 * reference, while keeping the device-not-suspended checks still enabled.
1511 * It's meant to be used only in special circumstances where our rule about
1512 * the wakelock refcount wrt. the device power state doesn't hold. According
1513 * to this rule at any point where we access the HW or want to keep the HW in
1514 * an active state we must hold an RPM wakelock reference acquired via one of
1515 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1516 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1517 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1518 * users should avoid using this function.
1520 * Any calls to this function must have a symmetric call to
1521 * enable_rpm_wakeref_asserts().
1524 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1526 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1530 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1531 * @dev_priv: i915 device instance
1533 * This function re-enables the RPM assert checks after disabling them with
1534 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1535 * circumstances otherwise its use should be avoided.
1537 * Any calls to this function must have a symmetric call to
1538 * disable_rpm_wakeref_asserts().
1541 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1543 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1546 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1547 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1548 disable_rpm_wakeref_asserts(dev_priv)
1550 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1551 enable_rpm_wakeref_asserts(dev_priv)
1553 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1554 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1555 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1556 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1558 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1560 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1561 bool override
, unsigned int mask
);
1562 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1563 enum dpio_channel ch
, bool override
);
1567 void intel_init_clock_gating(struct drm_device
*dev
);
1568 void intel_suspend_hw(struct drm_device
*dev
);
1569 int ilk_wm_max_level(const struct drm_device
*dev
);
1570 void intel_update_watermarks(struct drm_crtc
*crtc
);
1571 void intel_init_pm(struct drm_device
*dev
);
1572 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1573 void intel_pm_setup(struct drm_device
*dev
);
1574 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1575 void intel_gpu_ips_teardown(void);
1576 void intel_init_gt_powersave(struct drm_device
*dev
);
1577 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1578 void intel_enable_gt_powersave(struct drm_device
*dev
);
1579 void intel_disable_gt_powersave(struct drm_device
*dev
);
1580 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1581 void intel_reset_gt_powersave(struct drm_device
*dev
);
1582 void gen6_update_ring_freq(struct drm_device
*dev
);
1583 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1584 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1585 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1586 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1587 struct intel_rps_client
*rps
,
1588 unsigned long submitted
);
1589 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
1590 struct drm_i915_gem_request
*req
);
1591 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1592 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1593 void skl_wm_get_hw_state(struct drm_device
*dev
);
1594 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1595 struct skl_ddb_allocation
*ddb
/* out */);
1596 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1597 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1598 int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
);
1601 bool intel_sdvo_init(struct drm_device
*dev
,
1602 i915_reg_t reg
, enum port port
);
1605 /* intel_sprite.c */
1606 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1607 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1608 struct drm_file
*file_priv
);
1609 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1610 void intel_pipe_update_end(struct intel_crtc
*crtc
);
1613 void intel_tv_init(struct drm_device
*dev
);
1615 /* intel_atomic.c */
1616 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1617 const struct drm_connector_state
*state
,
1618 struct drm_property
*property
,
1620 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1621 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1622 struct drm_crtc_state
*state
);
1623 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1624 void intel_atomic_state_clear(struct drm_atomic_state
*);
1625 struct intel_shared_dpll_config
*
1626 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1628 static inline struct intel_crtc_state
*
1629 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1630 struct intel_crtc
*crtc
)
1632 struct drm_crtc_state
*crtc_state
;
1633 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1634 if (IS_ERR(crtc_state
))
1635 return ERR_CAST(crtc_state
);
1637 return to_intel_crtc_state(crtc_state
);
1640 static inline struct intel_plane_state
*
1641 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1642 struct intel_plane
*plane
)
1644 struct drm_plane_state
*plane_state
;
1646 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1648 return to_intel_plane_state(plane_state
);
1651 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1652 struct intel_crtc
*intel_crtc
,
1653 struct intel_crtc_state
*crtc_state
);
1655 /* intel_atomic_plane.c */
1656 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1657 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1658 void intel_plane_destroy_state(struct drm_plane
*plane
,
1659 struct drm_plane_state
*state
);
1660 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1662 #endif /* __INTEL_DRV_H__ */