2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 * TODO: When modesetting has fully transitioned to atomic, the below
49 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
52 #define _wait_for(COND, US, W) ({ \
53 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
56 if (time_after(jiffies, timeout__)) { \
61 if ((W) && drm_can_sleep()) { \
62 usleep_range((W), (W)*2); \
70 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
71 #define wait_for_us(COND, US) _wait_for((COND), (US), 1)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
80 #define _wait_for_atomic(COND, US) ({ \
81 unsigned long end__; \
83 _WAIT_FOR_ATOMIC_CHECK; \
84 BUILD_BUG_ON((US) > 50000); \
85 end__ = (local_clock() >> 10) + (US) + 1; \
87 if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
88 /* Unlike the regular wait_for(), this atomic variant \
89 * cannot be preempted (and we'll just ignore the issue\
90 * of irq interruptions) and so we know that no time \
91 * has passed since the last check of COND and can \
92 * immediately report the timeout. \
102 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
103 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
105 #define KHz(x) (1000 * (x))
106 #define MHz(x) KHz(1000 * (x))
109 * Display related stuff
112 /* store information about an Ixxx DVO */
113 /* The i830->i865 use multiple DVOs with multiple i2cs */
114 /* the i915, i945 have a single sDVO i2c bus - which is different */
115 #define MAX_OUTPUTS 6
116 /* maximum connectors per crtcs in the mode set */
118 /* Maximum cursor sizes */
119 #define GEN2_CURSOR_WIDTH 64
120 #define GEN2_CURSOR_HEIGHT 64
121 #define MAX_CURSOR_WIDTH 256
122 #define MAX_CURSOR_HEIGHT 256
124 #define INTEL_I2C_BUS_DVO 1
125 #define INTEL_I2C_BUS_SDVO 2
127 /* these are outputs from the chip - integrated only
128 external chips are via DVO or SDVO output */
129 enum intel_output_type
{
130 INTEL_OUTPUT_UNUSED
= 0,
131 INTEL_OUTPUT_ANALOG
= 1,
132 INTEL_OUTPUT_DVO
= 2,
133 INTEL_OUTPUT_SDVO
= 3,
134 INTEL_OUTPUT_LVDS
= 4,
135 INTEL_OUTPUT_TVOUT
= 5,
136 INTEL_OUTPUT_HDMI
= 6,
137 INTEL_OUTPUT_DISPLAYPORT
= 7,
138 INTEL_OUTPUT_EDP
= 8,
139 INTEL_OUTPUT_DSI
= 9,
140 INTEL_OUTPUT_UNKNOWN
= 10,
141 INTEL_OUTPUT_DP_MST
= 11,
144 #define INTEL_DVO_CHIP_NONE 0
145 #define INTEL_DVO_CHIP_LVDS 1
146 #define INTEL_DVO_CHIP_TMDS 2
147 #define INTEL_DVO_CHIP_TVOUT 4
149 #define INTEL_DSI_VIDEO_MODE 0
150 #define INTEL_DSI_COMMAND_MODE 1
152 struct intel_framebuffer
{
153 struct drm_framebuffer base
;
154 struct drm_i915_gem_object
*obj
;
155 struct intel_rotation_info rot_info
;
159 struct drm_fb_helper helper
;
160 struct intel_framebuffer
*fb
;
164 struct intel_encoder
{
165 struct drm_encoder base
;
167 enum intel_output_type type
;
168 unsigned int cloneable
;
169 void (*hot_plug
)(struct intel_encoder
*);
170 bool (*compute_config
)(struct intel_encoder
*,
171 struct intel_crtc_state
*);
172 void (*pre_pll_enable
)(struct intel_encoder
*);
173 void (*pre_enable
)(struct intel_encoder
*);
174 void (*enable
)(struct intel_encoder
*);
175 void (*mode_set
)(struct intel_encoder
*intel_encoder
);
176 void (*disable
)(struct intel_encoder
*);
177 void (*post_disable
)(struct intel_encoder
*);
178 void (*post_pll_disable
)(struct intel_encoder
*);
179 /* Read out the current hw state of this connector, returning true if
180 * the encoder is active. If the encoder is enabled it also set the pipe
181 * it is connected to in the pipe parameter. */
182 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
183 /* Reconstructs the equivalent mode flags for the current hardware
184 * state. This must be called _after_ display->get_pipe_config has
185 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
186 * be set correctly before calling this function. */
187 void (*get_config
)(struct intel_encoder
*,
188 struct intel_crtc_state
*pipe_config
);
190 * Called during system suspend after all pending requests for the
191 * encoder are flushed (for example for DP AUX transactions) and
192 * device interrupts are disabled.
194 void (*suspend
)(struct intel_encoder
*);
196 enum hpd_pin hpd_pin
;
200 struct drm_display_mode
*fixed_mode
;
201 struct drm_display_mode
*downclock_mode
;
211 bool combination_mode
; /* gen 2/4 only */
215 bool util_pin_active_low
; /* bxt+ */
216 u8 controller
; /* bxt+ only */
217 struct pwm_device
*pwm
;
219 struct backlight_device
*device
;
221 /* Connector and platform specific backlight functions */
222 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
223 uint32_t (*get
)(struct intel_connector
*connector
);
224 void (*set
)(struct intel_connector
*connector
, uint32_t level
);
225 void (*disable
)(struct intel_connector
*connector
);
226 void (*enable
)(struct intel_connector
*connector
);
227 uint32_t (*hz_to_pwm
)(struct intel_connector
*connector
,
229 void (*power
)(struct intel_connector
*, bool enable
);
233 struct intel_connector
{
234 struct drm_connector base
;
236 * The fixed encoder this connector is connected to.
238 struct intel_encoder
*encoder
;
240 /* Reads out the current hw, returning true if the connector is enabled
241 * and active (i.e. dpms ON state). */
242 bool (*get_hw_state
)(struct intel_connector
*);
245 * Removes all interfaces through which the connector is accessible
246 * - like sysfs, debugfs entries -, so that no new operations can be
247 * started on the connector. Also makes sure all currently pending
248 * operations finish before returing.
250 void (*unregister
)(struct intel_connector
*);
252 /* Panel info for eDP and LVDS */
253 struct intel_panel panel
;
255 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
257 struct edid
*detect_edid
;
259 /* since POLL and HPD connectors may use the same HPD line keep the native
260 state of connector->polled in case hotplug storm detection changes it */
263 void *port
; /* store this opaque as its illegal to dereference it */
265 struct intel_dp
*mst_port
;
268 typedef struct dpll
{
280 struct intel_atomic_state
{
281 struct drm_atomic_state base
;
286 * Calculated device cdclk, can be different from cdclk
287 * only when all crtc's are DPMS off.
289 unsigned int dev_cdclk
;
291 bool dpll_set
, modeset
;
293 unsigned int active_crtcs
;
294 unsigned int min_pixclk
[I915_MAX_PIPES
];
296 struct intel_shared_dpll_config shared_dpll
[I915_NUM_PLLS
];
297 struct intel_wm_config wm_config
;
300 * Current watermarks can't be trusted during hardware readout, so
301 * don't bother calculating intermediate watermarks.
303 bool skip_intermediate_wm
;
306 struct intel_plane_state
{
307 struct drm_plane_state base
;
310 struct drm_rect clip
;
315 * = -1 : not using a scaler
316 * >= 0 : using a scalers
318 * plane requiring a scaler:
319 * - During check_plane, its bit is set in
320 * crtc_state->scaler_state.scaler_users by calling helper function
321 * update_scaler_plane.
322 * - scaler_id indicates the scaler it got assigned.
324 * plane doesn't require a scaler:
325 * - this can happen when scaling is no more required or plane simply
327 * - During check_plane, corresponding bit is reset in
328 * crtc_state->scaler_state.scaler_users by calling helper function
329 * update_scaler_plane.
333 struct drm_intel_sprite_colorkey ckey
;
335 /* async flip related structures */
336 struct drm_i915_gem_request
*wait_req
;
339 struct intel_initial_plane_config
{
340 struct intel_framebuffer
*fb
;
346 #define SKL_MIN_SRC_W 8
347 #define SKL_MAX_SRC_W 4096
348 #define SKL_MIN_SRC_H 8
349 #define SKL_MAX_SRC_H 4096
350 #define SKL_MIN_DST_W 8
351 #define SKL_MAX_DST_W 4096
352 #define SKL_MIN_DST_H 8
353 #define SKL_MAX_DST_H 4096
355 struct intel_scaler
{
360 struct intel_crtc_scaler_state
{
361 #define SKL_NUM_SCALERS 2
362 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
365 * scaler_users: keeps track of users requesting scalers on this crtc.
367 * If a bit is set, a user is using a scaler.
368 * Here user can be a plane or crtc as defined below:
369 * bits 0-30 - plane (bit position is index from drm_plane_index)
372 * Instead of creating a new index to cover planes and crtc, using
373 * existing drm_plane_index for planes which is well less than 31
374 * planes and bit 31 for crtc. This should be fine to cover all
377 * intel_atomic_setup_scalers will setup available scalers to users
378 * requesting scalers. It will gracefully fail if request exceeds
381 #define SKL_CRTC_INDEX 31
382 unsigned scaler_users
;
384 /* scaler used by crtc for panel fitting purpose */
388 /* drm_mode->private_flags */
389 #define I915_MODE_FLAG_INHERITED 1
391 struct intel_pipe_wm
{
392 struct intel_wm_level wm
[5];
393 struct intel_wm_level raw_wm
[5];
397 bool sprites_enabled
;
402 struct skl_wm_level wm
[8];
403 struct skl_wm_level trans_wm
;
407 struct intel_crtc_state
{
408 struct drm_crtc_state base
;
411 * quirks - bitfield with hw state readout quirks
413 * For various reasons the hw state readout code might not be able to
414 * completely faithfully read out the current state. These cases are
415 * tracked with quirk flags so that fastboot and state checker can act
418 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
419 unsigned long quirks
;
421 unsigned fb_bits
; /* framebuffers to flip */
422 bool update_pipe
; /* can a fast modeset be performed? */
424 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
425 bool fb_changed
; /* fb on any of the planes is changed */
427 /* Pipe source size (ie. panel fitter input size)
428 * All planes will be positioned inside this space,
429 * and get clipped at the edges. */
430 int pipe_src_w
, pipe_src_h
;
432 /* Whether to set up the PCH/FDI. Note that we never allow sharing
433 * between pch encoders and cpu encoders. */
434 bool has_pch_encoder
;
436 /* Are we sending infoframes on the attached port */
439 /* CPU Transcoder for the pipe. Currently this can only differ from the
440 * pipe on Haswell and later (where we have a special eDP transcoder)
441 * and Broxton (where we have special DSI transcoders). */
442 enum transcoder cpu_transcoder
;
445 * Use reduced/limited/broadcast rbg range, compressing from the full
446 * range fed into the crtcs.
448 bool limited_color_range
;
450 /* DP has a bunch of special case unfortunately, so mark the pipe
454 /* DSI has special cases */
455 bool has_dsi_encoder
;
457 /* Whether we should send NULL infoframes. Required for audio. */
460 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
461 * has_dp_encoder is set. */
465 * Enable dithering, used when the selected pipe bpp doesn't match the
470 /* Controls for the clock computation, to override various stages. */
473 /* SDVO TV has a bunch of special case. To make multifunction encoders
474 * work correctly, we need to track this at runtime.*/
478 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
479 * required. This is set in the 2nd loop of calling encoder's
480 * ->compute_config if the first pick doesn't work out.
484 /* Settings for the intel dpll used on pretty much everything but
488 /* Selected dpll when shared or NULL. */
489 struct intel_shared_dpll
*shared_dpll
;
492 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
493 * - enum skl_dpll on SKL
495 uint32_t ddi_pll_sel
;
497 /* Actual register state of the dpll, for shared dpll cross-checking. */
498 struct intel_dpll_hw_state dpll_hw_state
;
500 /* DSI PLL registers */
506 struct intel_link_m_n dp_m_n
;
508 /* m2_n2 for eDP downclock */
509 struct intel_link_m_n dp_m2_n2
;
513 * Frequence the dpll for the port should run at. Differs from the
514 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
515 * already multiplied by pixel_multiplier.
519 /* Used by SDVO (and if we ever fix it, HDMI). */
520 unsigned pixel_multiplier
;
524 /* Panel fitter controls for gen2-gen4 + VLV */
528 u32 lvds_border_bits
;
531 /* Panel fitter placement and size for Ironlake+ */
539 /* FDI configuration, only valid if has_pch_encoder is set. */
541 struct intel_link_m_n fdi_m_n
;
549 bool dp_encoder_is_mst
;
552 struct intel_crtc_scaler_state scaler_state
;
554 /* w/a for waiting 2 vblanks during crtc enable */
555 enum pipe hsw_workaround_pipe
;
557 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
562 * Optimal watermarks, programmed post-vblank when this state
566 struct intel_pipe_wm ilk
;
567 struct skl_pipe_wm skl
;
571 * Intermediate watermarks; these can be programmed immediately
572 * since they satisfy both the current configuration we're
573 * switching away from and the new configuration we're switching
576 struct intel_pipe_wm intermediate
;
579 * Platforms with two-step watermark programming will need to
580 * update watermark programming post-vblank to switch from the
581 * safe intermediate watermarks to the optimal final
584 bool need_postvbl_update
;
587 /* Gamma mode programmed on the pipe */
591 struct vlv_wm_state
{
592 struct vlv_pipe_wm wm
[3];
593 struct vlv_sr_wm sr
[3];
594 uint8_t num_active_planes
;
600 struct intel_mmio_flip
{
601 struct work_struct work
;
602 struct drm_i915_private
*i915
;
603 struct drm_i915_gem_request
*req
;
604 struct intel_crtc
*crtc
;
605 unsigned int rotation
;
609 struct drm_crtc base
;
612 u8 lut_r
[256], lut_g
[256], lut_b
[256];
614 * Whether the crtc and the connected output pipeline is active. Implies
615 * that crtc->enabled is set, i.e. the current mode configuration has
616 * some outputs connected to this crtc.
619 unsigned long enabled_power_domains
;
621 struct intel_overlay
*overlay
;
622 struct intel_unpin_work
*unpin_work
;
624 atomic_t unpin_work_count
;
626 /* Display surface base address adjustement for pageflips. Note that on
627 * gen4+ this only adjusts up to a tile, offsets within a tile are
628 * handled in the hw itself (with the TILEOFF register). */
633 uint32_t cursor_addr
;
634 uint32_t cursor_cntl
;
635 uint32_t cursor_size
;
636 uint32_t cursor_base
;
638 struct intel_crtc_state
*config
;
640 /* reset counter value when the last flip was submitted */
641 unsigned int reset_counter
;
643 /* Access to these should be protected by dev_priv->irq_lock. */
644 bool cpu_fifo_underrun_disabled
;
645 bool pch_fifo_underrun_disabled
;
647 /* per-pipe watermark state */
649 /* watermarks currently being used */
651 struct intel_pipe_wm ilk
;
652 struct skl_pipe_wm skl
;
655 /* allow CxSR on this pipe */
662 unsigned start_vbl_count
;
663 ktime_t start_vbl_time
;
664 int min_vbl
, max_vbl
;
668 /* scalers available on this crtc */
671 struct vlv_wm_state wm_state
;
674 struct intel_plane_wm_parameters
{
675 uint32_t horiz_pixels
;
676 uint32_t vert_pixels
;
678 * For packed pixel formats:
679 * bytes_per_pixel - holds bytes per pixel
680 * For planar pixel formats:
681 * bytes_per_pixel - holds bytes per pixel for uv-plane
682 * y_bytes_per_pixel - holds bytes per pixel for y-plane
684 uint8_t bytes_per_pixel
;
685 uint8_t y_bytes_per_pixel
;
689 unsigned int rotation
;
694 struct drm_plane base
;
699 uint32_t frontbuffer_bit
;
701 /* Since we need to change the watermarks before/after
702 * enabling/disabling the planes, we need to store the parameters here
703 * as the other pieces of the struct may not reflect the values we want
704 * for the watermark calculations. Currently only Haswell uses this.
706 struct intel_plane_wm_parameters wm
;
709 * NOTE: Do not place new plane state fields here (e.g., when adding
710 * new plane properties). New runtime state should now be placed in
711 * the intel_plane_state structure and accessed via plane_state.
714 void (*update_plane
)(struct drm_plane
*plane
,
715 const struct intel_crtc_state
*crtc_state
,
716 const struct intel_plane_state
*plane_state
);
717 void (*disable_plane
)(struct drm_plane
*plane
,
718 struct drm_crtc
*crtc
);
719 int (*check_plane
)(struct drm_plane
*plane
,
720 struct intel_crtc_state
*crtc_state
,
721 struct intel_plane_state
*state
);
724 struct intel_watermark_params
{
725 unsigned long fifo_size
;
726 unsigned long max_wm
;
727 unsigned long default_wm
;
728 unsigned long guard_size
;
729 unsigned long cacheline_size
;
732 struct cxsr_latency
{
735 unsigned long fsb_freq
;
736 unsigned long mem_freq
;
737 unsigned long display_sr
;
738 unsigned long display_hpll_disable
;
739 unsigned long cursor_sr
;
740 unsigned long cursor_hpll_disable
;
743 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
744 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
745 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
746 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
747 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
748 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
749 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
750 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
751 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
756 bool limited_color_range
;
757 bool color_range_auto
;
760 enum hdmi_force_audio force_audio
;
761 bool rgb_quant_range_selectable
;
762 enum hdmi_picture_aspect aspect_ratio
;
763 struct intel_connector
*attached_connector
;
764 void (*write_infoframe
)(struct drm_encoder
*encoder
,
765 enum hdmi_infoframe_type type
,
766 const void *frame
, ssize_t len
);
767 void (*set_infoframes
)(struct drm_encoder
*encoder
,
769 const struct drm_display_mode
*adjusted_mode
);
770 bool (*infoframe_enabled
)(struct drm_encoder
*encoder
,
771 const struct intel_crtc_state
*pipe_config
);
774 struct intel_dp_mst_encoder
;
775 #define DP_MAX_DOWNSTREAM_PORTS 0x10
779 * When platform provides two set of M_N registers for dp, we can
780 * program them and switch between them incase of DRRS.
781 * But When only one such register is provided, we have to program the
782 * required divider value on that registers itself based on the DRRS state.
784 * M1_N1 : Program dp_m_n on M1_N1 registers
785 * dp_m2_n2 on M2_N2 registers (If supported)
787 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
788 * M2_N2 registers are not supported
792 /* Sets the m1_n1 and m2_n2 */
798 i915_reg_t output_reg
;
799 i915_reg_t aux_ch_ctl_reg
;
800 i915_reg_t aux_ch_data_reg
[5];
807 enum hdmi_force_audio force_audio
;
808 bool limited_color_range
;
809 bool color_range_auto
;
810 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
811 uint8_t psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
812 uint8_t downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
813 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
814 uint8_t num_sink_rates
;
815 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
816 struct drm_dp_aux aux
;
817 uint8_t train_set
[4];
818 int panel_power_up_delay
;
819 int panel_power_down_delay
;
820 int panel_power_cycle_delay
;
821 int backlight_on_delay
;
822 int backlight_off_delay
;
823 struct delayed_work panel_vdd_work
;
825 unsigned long last_power_on
;
826 unsigned long last_backlight_off
;
827 ktime_t panel_power_off_time
;
829 struct notifier_block edp_notifier
;
832 * Pipe whose power sequencer is currently locked into
833 * this port. Only relevant on VLV/CHV.
836 struct edp_power_seq pps_delays
;
838 bool can_mst
; /* this port supports mst */
840 int active_mst_links
;
841 /* connector directly attached - won't be use for modeset in mst world */
842 struct intel_connector
*attached_connector
;
844 /* mst connector list */
845 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
846 struct drm_dp_mst_topology_mgr mst_mgr
;
848 uint32_t (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
850 * This function returns the value we have to program the AUX_CTL
851 * register with to kick off an AUX transaction.
853 uint32_t (*get_aux_send_ctl
)(struct intel_dp
*dp
,
856 uint32_t aux_clock_divider
);
858 /* This is called before a link training is starterd */
859 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
);
861 bool train_set_valid
;
863 /* Displayport compliance testing */
864 unsigned long compliance_test_type
;
865 unsigned long compliance_test_data
;
866 bool compliance_test_active
;
869 struct intel_digital_port
{
870 struct intel_encoder base
;
874 struct intel_hdmi hdmi
;
875 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
876 bool release_cl2_override
;
878 /* for communication with audio component; protected by av_mutex */
879 const struct drm_connector
*audio_connector
;
882 struct intel_dp_mst_encoder
{
883 struct intel_encoder base
;
885 struct intel_digital_port
*primary
;
886 void *port
; /* store this opaque as its illegal to dereference it */
889 static inline enum dpio_channel
890 vlv_dport_to_channel(struct intel_digital_port
*dport
)
892 switch (dport
->port
) {
903 static inline enum dpio_phy
904 vlv_dport_to_phy(struct intel_digital_port
*dport
)
906 switch (dport
->port
) {
917 static inline enum dpio_channel
918 vlv_pipe_to_channel(enum pipe pipe
)
931 static inline struct drm_crtc
*
932 intel_get_crtc_for_pipe(struct drm_device
*dev
, int pipe
)
934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
935 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
938 static inline struct drm_crtc
*
939 intel_get_crtc_for_plane(struct drm_device
*dev
, int plane
)
941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
942 return dev_priv
->plane_to_crtc_mapping
[plane
];
945 struct intel_unpin_work
{
946 struct work_struct work
;
947 struct drm_crtc
*crtc
;
948 struct drm_framebuffer
*old_fb
;
949 struct drm_i915_gem_object
*pending_flip_obj
;
950 struct drm_pending_vblank_event
*event
;
952 #define INTEL_FLIP_INACTIVE 0
953 #define INTEL_FLIP_PENDING 1
954 #define INTEL_FLIP_COMPLETE 2
957 struct drm_i915_gem_request
*flip_queued_req
;
958 u32 flip_queued_vblank
;
959 u32 flip_ready_vblank
;
960 bool enable_stall_check
;
963 struct intel_load_detect_pipe
{
964 struct drm_atomic_state
*restore_state
;
967 static inline struct intel_encoder
*
968 intel_attached_encoder(struct drm_connector
*connector
)
970 return to_intel_connector(connector
)->encoder
;
973 static inline struct intel_digital_port
*
974 enc_to_dig_port(struct drm_encoder
*encoder
)
976 return container_of(encoder
, struct intel_digital_port
, base
.base
);
979 static inline struct intel_dp_mst_encoder
*
980 enc_to_mst(struct drm_encoder
*encoder
)
982 return container_of(encoder
, struct intel_dp_mst_encoder
, base
.base
);
985 static inline struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
987 return &enc_to_dig_port(encoder
)->dp
;
990 static inline struct intel_digital_port
*
991 dp_to_dig_port(struct intel_dp
*intel_dp
)
993 return container_of(intel_dp
, struct intel_digital_port
, dp
);
996 static inline struct intel_digital_port
*
997 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
999 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1003 * Returns the number of planes for this pipe, ie the number of sprites + 1
1004 * (primary plane). This doesn't count the cursor plane then.
1006 static inline unsigned int intel_num_planes(struct intel_crtc
*crtc
)
1008 return INTEL_INFO(crtc
->base
.dev
)->num_sprites
[crtc
->pipe
] + 1;
1011 /* intel_fifo_underrun.c */
1012 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1013 enum pipe pipe
, bool enable
);
1014 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
1015 enum transcoder pch_transcoder
,
1017 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1019 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
1020 enum transcoder pch_transcoder
);
1021 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
);
1022 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
);
1025 void gen5_enable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1026 void gen5_disable_gt_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1027 void gen6_enable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1028 void gen6_disable_pm_irq(struct drm_i915_private
*dev_priv
, uint32_t mask
);
1029 void gen6_reset_rps_interrupts(struct drm_device
*dev
);
1030 void gen6_enable_rps_interrupts(struct drm_device
*dev
);
1031 void gen6_disable_rps_interrupts(struct drm_device
*dev
);
1032 u32
gen6_sanitize_rps_pm_mask(struct drm_i915_private
*dev_priv
, u32 mask
);
1033 void intel_runtime_pm_disable_interrupts(struct drm_i915_private
*dev_priv
);
1034 void intel_runtime_pm_enable_interrupts(struct drm_i915_private
*dev_priv
);
1035 static inline bool intel_irqs_enabled(struct drm_i915_private
*dev_priv
)
1038 * We only use drm_irq_uninstall() at unload and VT switch, so
1039 * this is the only thing we need to check.
1041 return dev_priv
->pm
.irqs_enabled
;
1044 int intel_get_crtc_scanline(struct intel_crtc
*crtc
);
1045 void gen8_irq_power_well_post_enable(struct drm_i915_private
*dev_priv
,
1046 unsigned int pipe_mask
);
1047 void gen8_irq_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
1048 unsigned int pipe_mask
);
1051 void intel_crt_init(struct drm_device
*dev
);
1055 void intel_ddi_clk_select(struct intel_encoder
*encoder
,
1056 const struct intel_crtc_state
*pipe_config
);
1057 void intel_prepare_ddi_buffer(struct intel_encoder
*encoder
);
1058 void hsw_fdi_link_train(struct drm_crtc
*crtc
);
1059 void intel_ddi_init(struct drm_device
*dev
, enum port port
);
1060 enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
);
1061 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
, enum pipe
*pipe
);
1062 void intel_ddi_enable_transcoder_func(struct drm_crtc
*crtc
);
1063 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1064 enum transcoder cpu_transcoder
);
1065 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
);
1066 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
);
1067 bool intel_ddi_pll_select(struct intel_crtc
*crtc
,
1068 struct intel_crtc_state
*crtc_state
);
1069 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
);
1070 void intel_ddi_prepare_link_retrain(struct intel_dp
*intel_dp
);
1071 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
);
1072 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
);
1073 bool intel_ddi_is_audio_enabled(struct drm_i915_private
*dev_priv
,
1074 struct intel_crtc
*intel_crtc
);
1075 void intel_ddi_get_config(struct intel_encoder
*encoder
,
1076 struct intel_crtc_state
*pipe_config
);
1077 struct intel_encoder
*
1078 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
*crtc_state
);
1080 void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder
);
1081 void intel_ddi_clock_get(struct intel_encoder
*encoder
,
1082 struct intel_crtc_state
*pipe_config
);
1083 void intel_ddi_set_vc_payload_alloc(struct drm_crtc
*crtc
, bool state
);
1084 uint32_t ddi_signal_levels(struct intel_dp
*intel_dp
);
1086 /* intel_frontbuffer.c */
1087 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
1088 enum fb_op_origin origin
);
1089 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
1090 unsigned frontbuffer_bits
);
1091 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
1092 unsigned frontbuffer_bits
);
1093 void intel_frontbuffer_flip(struct drm_device
*dev
,
1094 unsigned frontbuffer_bits
);
1095 unsigned int intel_fb_align_height(struct drm_device
*dev
,
1096 unsigned int height
,
1097 uint32_t pixel_format
,
1098 uint64_t fb_format_modifier
);
1099 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
, bool retire
,
1100 enum fb_op_origin origin
);
1101 u32
intel_fb_stride_alignment(const struct drm_i915_private
*dev_priv
,
1102 uint64_t fb_modifier
, uint32_t pixel_format
);
1105 void intel_init_audio_hooks(struct drm_i915_private
*dev_priv
);
1106 void intel_audio_codec_enable(struct intel_encoder
*encoder
);
1107 void intel_audio_codec_disable(struct intel_encoder
*encoder
);
1108 void i915_audio_component_init(struct drm_i915_private
*dev_priv
);
1109 void i915_audio_component_cleanup(struct drm_i915_private
*dev_priv
);
1111 /* intel_display.c */
1112 int vlv_get_cck_clock(struct drm_i915_private
*dev_priv
,
1113 const char *name
, u32 reg
, int ref_freq
);
1114 extern const struct drm_plane_funcs intel_plane_funcs
;
1115 void intel_init_display_hooks(struct drm_i915_private
*dev_priv
);
1116 unsigned int intel_rotation_info_size(const struct intel_rotation_info
*rot_info
);
1117 bool intel_has_pending_fb_unpin(struct drm_device
*dev
);
1118 void intel_mark_busy(struct drm_device
*dev
);
1119 void intel_mark_idle(struct drm_device
*dev
);
1120 void intel_crtc_restore_mode(struct drm_crtc
*crtc
);
1121 int intel_display_suspend(struct drm_device
*dev
);
1122 void intel_encoder_destroy(struct drm_encoder
*encoder
);
1123 int intel_connector_init(struct intel_connector
*);
1124 struct intel_connector
*intel_connector_alloc(void);
1125 bool intel_connector_get_hw_state(struct intel_connector
*connector
);
1126 void intel_connector_attach_encoder(struct intel_connector
*connector
,
1127 struct intel_encoder
*encoder
);
1128 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
);
1129 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1130 struct drm_crtc
*crtc
);
1131 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
);
1132 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
1133 struct drm_file
*file_priv
);
1134 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1136 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
);
1138 intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
1140 drm_wait_one_vblank(dev
, pipe
);
1143 intel_wait_for_vblank_if_active(struct drm_device
*dev
, int pipe
)
1145 const struct intel_crtc
*crtc
=
1146 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
1149 intel_wait_for_vblank(dev
, pipe
);
1151 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
);
1152 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1153 struct intel_digital_port
*dport
,
1154 unsigned int expected_mask
);
1155 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
1156 struct drm_display_mode
*mode
,
1157 struct intel_load_detect_pipe
*old
,
1158 struct drm_modeset_acquire_ctx
*ctx
);
1159 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
1160 struct intel_load_detect_pipe
*old
,
1161 struct drm_modeset_acquire_ctx
*ctx
);
1162 int intel_pin_and_fence_fb_obj(struct drm_framebuffer
*fb
,
1163 unsigned int rotation
);
1164 struct drm_framebuffer
*
1165 __intel_framebuffer_create(struct drm_device
*dev
,
1166 struct drm_mode_fb_cmd2
*mode_cmd
,
1167 struct drm_i915_gem_object
*obj
);
1168 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
);
1169 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
);
1170 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
);
1171 void intel_check_page_flip(struct drm_device
*dev
, int pipe
);
1172 int intel_prepare_plane_fb(struct drm_plane
*plane
,
1173 const struct drm_plane_state
*new_state
);
1174 void intel_cleanup_plane_fb(struct drm_plane
*plane
,
1175 const struct drm_plane_state
*old_state
);
1176 int intel_plane_atomic_get_property(struct drm_plane
*plane
,
1177 const struct drm_plane_state
*state
,
1178 struct drm_property
*property
,
1180 int intel_plane_atomic_set_property(struct drm_plane
*plane
,
1181 struct drm_plane_state
*state
,
1182 struct drm_property
*property
,
1184 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
1185 struct drm_plane_state
*plane_state
);
1187 unsigned int intel_tile_height(const struct drm_i915_private
*dev_priv
,
1188 uint64_t fb_modifier
, unsigned int cpp
);
1191 intel_rotation_90_or_270(unsigned int rotation
)
1193 return rotation
& (BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
));
1196 void intel_create_rotation_property(struct drm_device
*dev
,
1197 struct intel_plane
*plane
);
1199 void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1202 int vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
1203 const struct dpll
*dpll
);
1204 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
);
1205 int lpt_get_iclkip(struct drm_i915_private
*dev_priv
);
1207 /* modesetting asserts */
1208 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1210 void assert_pll(struct drm_i915_private
*dev_priv
,
1211 enum pipe pipe
, bool state
);
1212 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1213 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1214 void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
);
1215 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1216 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1217 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
);
1219 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1220 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1221 void assert_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, bool state
);
1222 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1223 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1224 u32
intel_compute_tile_offset(int *x
, int *y
,
1225 const struct drm_framebuffer
*fb
, int plane
,
1227 unsigned int rotation
);
1228 void intel_prepare_reset(struct drm_device
*dev
);
1229 void intel_finish_reset(struct drm_device
*dev
);
1230 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
);
1231 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
);
1232 void broxton_init_cdclk(struct drm_i915_private
*dev_priv
);
1233 void broxton_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1234 bool broxton_cdclk_verify_state(struct drm_i915_private
*dev_priv
);
1235 void broxton_ddi_phy_init(struct drm_i915_private
*dev_priv
);
1236 void broxton_ddi_phy_uninit(struct drm_i915_private
*dev_priv
);
1237 void broxton_ddi_phy_verify_state(struct drm_i915_private
*dev_priv
);
1238 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
);
1239 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
);
1240 void skl_init_cdclk(struct drm_i915_private
*dev_priv
);
1241 int skl_sanitize_cdclk(struct drm_i915_private
*dev_priv
);
1242 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
);
1243 void skl_enable_dc6(struct drm_i915_private
*dev_priv
);
1244 void skl_disable_dc6(struct drm_i915_private
*dev_priv
);
1245 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
1246 struct intel_crtc_state
*pipe_config
);
1247 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
);
1248 int intel_dotclock_calculate(int link_freq
, const struct intel_link_m_n
*m_n
);
1249 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1250 intel_clock_t
*best_clock
);
1251 int chv_calc_dpll_params(int refclk
, intel_clock_t
*pll_clock
);
1253 bool intel_crtc_active(struct drm_crtc
*crtc
);
1254 void hsw_enable_ips(struct intel_crtc
*crtc
);
1255 void hsw_disable_ips(struct intel_crtc
*crtc
);
1256 enum intel_display_power_domain
1257 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
);
1258 enum intel_display_power_domain
1259 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
);
1260 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
1261 struct intel_crtc_state
*pipe_config
);
1263 int skl_update_scaler_crtc(struct intel_crtc_state
*crtc_state
);
1264 int skl_max_scale(struct intel_crtc
*crtc
, struct intel_crtc_state
*crtc_state
);
1266 u32
intel_plane_obj_offset(struct intel_plane
*intel_plane
,
1267 struct drm_i915_gem_object
*obj
,
1268 unsigned int plane
);
1270 u32
skl_plane_ctl_format(uint32_t pixel_format
);
1271 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
);
1272 u32
skl_plane_ctl_rotation(unsigned int rotation
);
1275 void intel_csr_ucode_init(struct drm_i915_private
*);
1276 void intel_csr_load_program(struct drm_i915_private
*);
1277 void intel_csr_ucode_fini(struct drm_i915_private
*);
1280 void intel_dp_init(struct drm_device
*dev
, i915_reg_t output_reg
, enum port port
);
1281 bool intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
1282 struct intel_connector
*intel_connector
);
1283 void intel_dp_set_link_params(struct intel_dp
*intel_dp
,
1284 const struct intel_crtc_state
*pipe_config
);
1285 void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
1286 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
);
1287 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
);
1288 void intel_dp_encoder_reset(struct drm_encoder
*encoder
);
1289 void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
);
1290 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
);
1291 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
);
1292 bool intel_dp_compute_config(struct intel_encoder
*encoder
,
1293 struct intel_crtc_state
*pipe_config
);
1294 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
);
1295 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
,
1297 void intel_edp_backlight_on(struct intel_dp
*intel_dp
);
1298 void intel_edp_backlight_off(struct intel_dp
*intel_dp
);
1299 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
1300 void intel_edp_panel_on(struct intel_dp
*intel_dp
);
1301 void intel_edp_panel_off(struct intel_dp
*intel_dp
);
1302 void intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
);
1303 void intel_dp_mst_suspend(struct drm_device
*dev
);
1304 void intel_dp_mst_resume(struct drm_device
*dev
);
1305 int intel_dp_max_link_rate(struct intel_dp
*intel_dp
);
1306 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
);
1307 void intel_dp_hot_plug(struct intel_encoder
*intel_encoder
);
1308 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
);
1309 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
);
1310 void intel_plane_destroy(struct drm_plane
*plane
);
1311 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
);
1312 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
);
1313 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
1314 unsigned frontbuffer_bits
);
1315 void intel_edp_drrs_flush(struct drm_device
*dev
, unsigned frontbuffer_bits
);
1316 bool intel_digital_port_connected(struct drm_i915_private
*dev_priv
,
1317 struct intel_digital_port
*port
);
1320 intel_dp_program_link_training_pattern(struct intel_dp
*intel_dp
,
1321 uint8_t dp_train_pat
);
1323 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
);
1324 void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
);
1326 intel_dp_voltage_max(struct intel_dp
*intel_dp
);
1328 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
);
1329 void intel_dp_compute_rate(struct intel_dp
*intel_dp
, int port_clock
,
1330 uint8_t *link_bw
, uint8_t *rate_select
);
1331 bool intel_dp_source_supports_hbr2(struct intel_dp
*intel_dp
);
1333 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
]);
1335 /* intel_dp_mst.c */
1336 int intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port
, int conn_id
);
1337 void intel_dp_mst_encoder_cleanup(struct intel_digital_port
*intel_dig_port
);
1339 void intel_dsi_init(struct drm_device
*dev
);
1343 void intel_dvo_init(struct drm_device
*dev
);
1346 /* legacy fbdev emulation in intel_fbdev.c */
1347 #ifdef CONFIG_DRM_FBDEV_EMULATION
1348 extern int intel_fbdev_init(struct drm_device
*dev
);
1349 extern void intel_fbdev_initial_config_async(struct drm_device
*dev
);
1350 extern void intel_fbdev_fini(struct drm_device
*dev
);
1351 extern void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
);
1352 extern void intel_fbdev_output_poll_changed(struct drm_device
*dev
);
1353 extern void intel_fbdev_restore_mode(struct drm_device
*dev
);
1355 static inline int intel_fbdev_init(struct drm_device
*dev
)
1360 static inline void intel_fbdev_initial_config_async(struct drm_device
*dev
)
1364 static inline void intel_fbdev_fini(struct drm_device
*dev
)
1368 static inline void intel_fbdev_set_suspend(struct drm_device
*dev
, int state
, bool synchronous
)
1372 static inline void intel_fbdev_restore_mode(struct drm_device
*dev
)
1378 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1379 struct drm_atomic_state
*state
);
1380 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
);
1381 void intel_fbc_pre_update(struct intel_crtc
*crtc
);
1382 void intel_fbc_post_update(struct intel_crtc
*crtc
);
1383 void intel_fbc_init(struct drm_i915_private
*dev_priv
);
1384 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
);
1385 void intel_fbc_enable(struct intel_crtc
*crtc
);
1386 void intel_fbc_disable(struct intel_crtc
*crtc
);
1387 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
);
1388 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
1389 unsigned int frontbuffer_bits
,
1390 enum fb_op_origin origin
);
1391 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1392 unsigned int frontbuffer_bits
, enum fb_op_origin origin
);
1393 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
);
1396 void intel_hdmi_init(struct drm_device
*dev
, i915_reg_t hdmi_reg
, enum port port
);
1397 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1398 struct intel_connector
*intel_connector
);
1399 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
);
1400 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
1401 struct intel_crtc_state
*pipe_config
);
1405 void intel_lvds_init(struct drm_device
*dev
);
1406 bool intel_is_dual_link_lvds(struct drm_device
*dev
);
1410 int intel_connector_update_modes(struct drm_connector
*connector
,
1412 int intel_ddc_get_modes(struct drm_connector
*c
, struct i2c_adapter
*adapter
);
1413 void intel_attach_force_audio_property(struct drm_connector
*connector
);
1414 void intel_attach_broadcast_rgb_property(struct drm_connector
*connector
);
1415 void intel_attach_aspect_ratio_property(struct drm_connector
*connector
);
1418 /* intel_overlay.c */
1419 void intel_setup_overlay(struct drm_device
*dev
);
1420 void intel_cleanup_overlay(struct drm_device
*dev
);
1421 int intel_overlay_switch_off(struct intel_overlay
*overlay
);
1422 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1423 struct drm_file
*file_priv
);
1424 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1425 struct drm_file
*file_priv
);
1426 void intel_overlay_reset(struct drm_i915_private
*dev_priv
);
1430 int intel_panel_init(struct intel_panel
*panel
,
1431 struct drm_display_mode
*fixed_mode
,
1432 struct drm_display_mode
*downclock_mode
);
1433 void intel_panel_fini(struct intel_panel
*panel
);
1434 void intel_fixed_panel_mode(const struct drm_display_mode
*fixed_mode
,
1435 struct drm_display_mode
*adjusted_mode
);
1436 void intel_pch_panel_fitting(struct intel_crtc
*crtc
,
1437 struct intel_crtc_state
*pipe_config
,
1439 void intel_gmch_panel_fitting(struct intel_crtc
*crtc
,
1440 struct intel_crtc_state
*pipe_config
,
1442 void intel_panel_set_backlight_acpi(struct intel_connector
*connector
,
1443 u32 level
, u32 max
);
1444 int intel_panel_setup_backlight(struct drm_connector
*connector
, enum pipe pipe
);
1445 void intel_panel_enable_backlight(struct intel_connector
*connector
);
1446 void intel_panel_disable_backlight(struct intel_connector
*connector
);
1447 void intel_panel_destroy_backlight(struct drm_connector
*connector
);
1448 enum drm_connector_status
intel_panel_detect(struct drm_device
*dev
);
1449 extern struct drm_display_mode
*intel_find_panel_downclock(
1450 struct drm_device
*dev
,
1451 struct drm_display_mode
*fixed_mode
,
1452 struct drm_connector
*connector
);
1453 void intel_backlight_register(struct drm_device
*dev
);
1454 void intel_backlight_unregister(struct drm_device
*dev
);
1458 void intel_psr_enable(struct intel_dp
*intel_dp
);
1459 void intel_psr_disable(struct intel_dp
*intel_dp
);
1460 void intel_psr_invalidate(struct drm_device
*dev
,
1461 unsigned frontbuffer_bits
);
1462 void intel_psr_flush(struct drm_device
*dev
,
1463 unsigned frontbuffer_bits
,
1464 enum fb_op_origin origin
);
1465 void intel_psr_init(struct drm_device
*dev
);
1466 void intel_psr_single_frame_update(struct drm_device
*dev
,
1467 unsigned frontbuffer_bits
);
1469 /* intel_runtime_pm.c */
1470 int intel_power_domains_init(struct drm_i915_private
*);
1471 void intel_power_domains_fini(struct drm_i915_private
*);
1472 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
);
1473 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
);
1474 void bxt_display_core_init(struct drm_i915_private
*dev_priv
, bool resume
);
1475 void bxt_display_core_uninit(struct drm_i915_private
*dev_priv
);
1476 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
);
1478 intel_display_power_domain_str(enum intel_display_power_domain domain
);
1480 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1481 enum intel_display_power_domain domain
);
1482 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
1483 enum intel_display_power_domain domain
);
1484 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1485 enum intel_display_power_domain domain
);
1486 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1487 enum intel_display_power_domain domain
);
1488 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1489 enum intel_display_power_domain domain
);
1492 assert_rpm_device_not_suspended(struct drm_i915_private
*dev_priv
)
1494 WARN_ONCE(dev_priv
->pm
.suspended
,
1495 "Device suspended during HW access\n");
1499 assert_rpm_wakelock_held(struct drm_i915_private
*dev_priv
)
1501 assert_rpm_device_not_suspended(dev_priv
);
1502 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1503 * too much noise. */
1504 if (!atomic_read(&dev_priv
->pm
.wakeref_count
))
1505 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1509 assert_rpm_atomic_begin(struct drm_i915_private
*dev_priv
)
1511 int seq
= atomic_read(&dev_priv
->pm
.atomic_seq
);
1513 assert_rpm_wakelock_held(dev_priv
);
1519 assert_rpm_atomic_end(struct drm_i915_private
*dev_priv
, int begin_seq
)
1521 WARN_ONCE(atomic_read(&dev_priv
->pm
.atomic_seq
) != begin_seq
,
1522 "HW access outside of RPM atomic section\n");
1526 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1527 * @dev_priv: i915 device instance
1529 * This function disable asserts that check if we hold an RPM wakelock
1530 * reference, while keeping the device-not-suspended checks still enabled.
1531 * It's meant to be used only in special circumstances where our rule about
1532 * the wakelock refcount wrt. the device power state doesn't hold. According
1533 * to this rule at any point where we access the HW or want to keep the HW in
1534 * an active state we must hold an RPM wakelock reference acquired via one of
1535 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1536 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1537 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1538 * users should avoid using this function.
1540 * Any calls to this function must have a symmetric call to
1541 * enable_rpm_wakeref_asserts().
1544 disable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1546 atomic_inc(&dev_priv
->pm
.wakeref_count
);
1550 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1551 * @dev_priv: i915 device instance
1553 * This function re-enables the RPM assert checks after disabling them with
1554 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1555 * circumstances otherwise its use should be avoided.
1557 * Any calls to this function must have a symmetric call to
1558 * disable_rpm_wakeref_asserts().
1561 enable_rpm_wakeref_asserts(struct drm_i915_private
*dev_priv
)
1563 atomic_dec(&dev_priv
->pm
.wakeref_count
);
1566 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1567 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1568 disable_rpm_wakeref_asserts(dev_priv)
1570 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1571 enable_rpm_wakeref_asserts(dev_priv)
1573 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
);
1574 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
);
1575 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
);
1576 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
);
1578 void intel_display_set_init_power(struct drm_i915_private
*dev
, bool enable
);
1580 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1581 bool override
, unsigned int mask
);
1582 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1583 enum dpio_channel ch
, bool override
);
1587 void intel_init_clock_gating(struct drm_device
*dev
);
1588 void intel_suspend_hw(struct drm_device
*dev
);
1589 int ilk_wm_max_level(const struct drm_device
*dev
);
1590 void intel_update_watermarks(struct drm_crtc
*crtc
);
1591 void intel_init_pm(struct drm_device
*dev
);
1592 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
);
1593 void intel_pm_setup(struct drm_device
*dev
);
1594 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
);
1595 void intel_gpu_ips_teardown(void);
1596 void intel_init_gt_powersave(struct drm_device
*dev
);
1597 void intel_cleanup_gt_powersave(struct drm_device
*dev
);
1598 void intel_enable_gt_powersave(struct drm_device
*dev
);
1599 void intel_disable_gt_powersave(struct drm_device
*dev
);
1600 void intel_suspend_gt_powersave(struct drm_device
*dev
);
1601 void intel_reset_gt_powersave(struct drm_device
*dev
);
1602 void gen6_update_ring_freq(struct drm_device
*dev
);
1603 void gen6_rps_busy(struct drm_i915_private
*dev_priv
);
1604 void gen6_rps_reset_ei(struct drm_i915_private
*dev_priv
);
1605 void gen6_rps_idle(struct drm_i915_private
*dev_priv
);
1606 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
1607 struct intel_rps_client
*rps
,
1608 unsigned long submitted
);
1609 void intel_queue_rps_boost_for_request(struct drm_device
*dev
,
1610 struct drm_i915_gem_request
*req
);
1611 void vlv_wm_get_hw_state(struct drm_device
*dev
);
1612 void ilk_wm_get_hw_state(struct drm_device
*dev
);
1613 void skl_wm_get_hw_state(struct drm_device
*dev
);
1614 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
1615 struct skl_ddb_allocation
*ddb
/* out */);
1616 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
);
1617 bool ilk_disable_lp_wm(struct drm_device
*dev
);
1618 int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
);
1621 bool intel_sdvo_init(struct drm_device
*dev
,
1622 i915_reg_t reg
, enum port port
);
1625 /* intel_sprite.c */
1626 int intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
);
1627 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
1628 struct drm_file
*file_priv
);
1629 void intel_pipe_update_start(struct intel_crtc
*crtc
);
1630 void intel_pipe_update_end(struct intel_crtc
*crtc
);
1633 void intel_tv_init(struct drm_device
*dev
);
1635 /* intel_atomic.c */
1636 int intel_connector_atomic_get_property(struct drm_connector
*connector
,
1637 const struct drm_connector_state
*state
,
1638 struct drm_property
*property
,
1640 struct drm_crtc_state
*intel_crtc_duplicate_state(struct drm_crtc
*crtc
);
1641 void intel_crtc_destroy_state(struct drm_crtc
*crtc
,
1642 struct drm_crtc_state
*state
);
1643 struct drm_atomic_state
*intel_atomic_state_alloc(struct drm_device
*dev
);
1644 void intel_atomic_state_clear(struct drm_atomic_state
*);
1645 struct intel_shared_dpll_config
*
1646 intel_atomic_get_shared_dpll_state(struct drm_atomic_state
*s
);
1648 static inline struct intel_crtc_state
*
1649 intel_atomic_get_crtc_state(struct drm_atomic_state
*state
,
1650 struct intel_crtc
*crtc
)
1652 struct drm_crtc_state
*crtc_state
;
1653 crtc_state
= drm_atomic_get_crtc_state(state
, &crtc
->base
);
1654 if (IS_ERR(crtc_state
))
1655 return ERR_CAST(crtc_state
);
1657 return to_intel_crtc_state(crtc_state
);
1660 static inline struct intel_plane_state
*
1661 intel_atomic_get_existing_plane_state(struct drm_atomic_state
*state
,
1662 struct intel_plane
*plane
)
1664 struct drm_plane_state
*plane_state
;
1666 plane_state
= drm_atomic_get_existing_plane_state(state
, &plane
->base
);
1668 return to_intel_plane_state(plane_state
);
1671 int intel_atomic_setup_scalers(struct drm_device
*dev
,
1672 struct intel_crtc
*intel_crtc
,
1673 struct intel_crtc_state
*crtc_state
);
1675 /* intel_atomic_plane.c */
1676 struct intel_plane_state
*intel_create_plane_state(struct drm_plane
*plane
);
1677 struct drm_plane_state
*intel_plane_duplicate_state(struct drm_plane
*plane
);
1678 void intel_plane_destroy_state(struct drm_plane
*plane
,
1679 struct drm_plane_state
*state
);
1680 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs
;
1683 void intel_color_init(struct drm_crtc
*crtc
);
1684 int intel_color_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
);
1685 void intel_color_set_csc(struct drm_crtc_state
*crtc_state
);
1686 void intel_color_load_luts(struct drm_crtc_state
*crtc_state
);
1688 #endif /* __INTEL_DRV_H__ */