2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 enum mipi_dsi_pixel_format
pixel_format_from_register_bits(u32 fmt
)
51 /* It just so happens the VBT matches register contents. */
53 case VID_MODE_FORMAT_RGB888
:
54 return MIPI_DSI_FMT_RGB888
;
55 case VID_MODE_FORMAT_RGB666
:
56 return MIPI_DSI_FMT_RGB666
;
57 case VID_MODE_FORMAT_RGB666_PACKED
:
58 return MIPI_DSI_FMT_RGB666_PACKED
;
59 case VID_MODE_FORMAT_RGB565
:
60 return MIPI_DSI_FMT_RGB565
;
63 return MIPI_DSI_FMT_RGB666
;
67 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
69 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
70 struct drm_device
*dev
= encoder
->dev
;
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
75 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
77 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
78 DRM_ERROR("DPI FIFOs are not empty\n");
81 static void write_data(struct drm_i915_private
*dev_priv
,
83 const u8
*data
, u32 len
)
87 for (i
= 0; i
< len
; i
+= 4) {
90 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
91 val
|= *data
++ << 8 * j
;
97 static void read_data(struct drm_i915_private
*dev_priv
,
103 for (i
= 0; i
< len
; i
+= 4) {
104 u32 val
= I915_READ(reg
);
106 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
107 *data
++ = val
>> 8 * j
;
111 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
112 const struct mipi_dsi_msg
*msg
)
114 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
115 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 enum port port
= intel_dsi_host
->port
;
118 struct mipi_dsi_packet packet
;
120 const u8
*header
, *data
;
121 i915_reg_t data_reg
, ctrl_reg
;
122 u32 data_mask
, ctrl_mask
;
124 ret
= mipi_dsi_create_packet(&packet
, msg
);
128 header
= packet
.header
;
129 data
= packet
.payload
;
131 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
132 data_reg
= MIPI_LP_GEN_DATA(port
);
133 data_mask
= LP_DATA_FIFO_FULL
;
134 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
135 ctrl_mask
= LP_CTRL_FIFO_FULL
;
137 data_reg
= MIPI_HS_GEN_DATA(port
);
138 data_mask
= HS_DATA_FIFO_FULL
;
139 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
140 ctrl_mask
= HS_CTRL_FIFO_FULL
;
143 /* note: this is never true for reads */
144 if (packet
.payload_length
) {
146 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
147 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
149 write_data(dev_priv
, data_reg
, packet
.payload
,
150 packet
.payload_length
);
154 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
157 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
158 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
161 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
163 /* ->rx_len is set only for reads */
165 data_mask
= GEN_READ_DATA_AVAIL
;
166 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
167 DRM_ERROR("Timeout waiting for read data.\n");
169 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
172 /* XXX: fix for reads and writes */
173 return 4 + packet
.payload_length
;
176 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
177 struct mipi_dsi_device
*dsi
)
182 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
183 struct mipi_dsi_device
*dsi
)
188 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
189 .attach
= intel_dsi_host_attach
,
190 .detach
= intel_dsi_host_detach
,
191 .transfer
= intel_dsi_host_transfer
,
194 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
197 struct intel_dsi_host
*host
;
198 struct mipi_dsi_device
*device
;
200 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
204 host
->base
.ops
= &intel_dsi_host_ops
;
205 host
->intel_dsi
= intel_dsi
;
209 * We should call mipi_dsi_host_register(&host->base) here, but we don't
210 * have a host->dev, and we don't have OF stuff either. So just use the
211 * dsi framework as a library and hope for the best. Create the dsi
212 * devices by ourselves here too. Need to be careful though, because we
213 * don't initialize any of the driver model devices here.
215 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
221 device
->host
= &host
->base
;
222 host
->device
= device
;
228 * send a video mode command
230 * XXX: commands with data in MIPI_DPI_DATA?
232 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
235 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
236 struct drm_device
*dev
= encoder
->dev
;
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
249 /* XXX: old code skips write if control unchanged */
250 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
251 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
253 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
255 mask
= SPL_PKT_SENT_INTERRUPT
;
256 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
257 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
262 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
264 mutex_lock(&dev_priv
->sb_lock
);
266 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
267 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
268 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
270 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
271 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
273 mutex_unlock(&dev_priv
->sb_lock
);
276 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
278 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
281 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
283 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
286 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
287 struct intel_crtc_state
*pipe_config
)
289 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
290 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
292 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
293 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
294 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
298 pipe_config
->has_dsi_encoder
= true;
301 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
303 /* DSI uses short packets for sync events, so clear mode flags for DSI */
304 adjusted_mode
->flags
= 0;
306 if (IS_BROXTON(dev_priv
)) {
307 /* Dual link goes to DSI transcoder A. */
308 if (intel_dsi
->ports
== BIT(PORT_C
))
309 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_C
;
311 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_A
;
315 * FIXME move the DSI PLL calc from vlv_enable_dsi_pll()
316 * to .compute_config().
318 pipe_config
->clock_set
= true;
323 static void bxt_dsi_device_ready(struct intel_encoder
*encoder
)
325 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
326 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
332 /* Exit Low power state in 4 steps*/
333 for_each_dsi_port(port
, intel_dsi
->ports
) {
335 /* 1. Enable MIPI PHY transparent latch */
336 val
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
337 I915_WRITE(BXT_MIPI_PORT_CTRL(port
), val
| LP_OUTPUT_HOLD
);
338 usleep_range(2000, 2500);
341 val
= I915_READ(MIPI_DEVICE_READY(port
));
342 val
&= ~ULPS_STATE_MASK
;
343 val
|= (ULPS_STATE_ENTER
| DEVICE_READY
);
344 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
348 val
= I915_READ(MIPI_DEVICE_READY(port
));
349 val
&= ~ULPS_STATE_MASK
;
350 val
|= (ULPS_STATE_EXIT
| DEVICE_READY
);
351 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
352 usleep_range(1000, 1500);
354 /* Clear ULPS and set device ready */
355 val
= I915_READ(MIPI_DEVICE_READY(port
));
356 val
&= ~ULPS_STATE_MASK
;
358 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
362 static void vlv_dsi_device_ready(struct intel_encoder
*encoder
)
364 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
365 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
371 mutex_lock(&dev_priv
->sb_lock
);
372 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
373 * needed everytime after power gate */
374 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
375 mutex_unlock(&dev_priv
->sb_lock
);
377 /* bandgap reset is needed after everytime we do power gate */
378 band_gap_reset(dev_priv
);
380 for_each_dsi_port(port
, intel_dsi
->ports
) {
382 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
383 usleep_range(2500, 3000);
385 /* Enable MIPI PHY transparent latch
386 * Common bit for both MIPI Port A & MIPI Port C
387 * No similar bit in MIPI Port C reg
389 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
390 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
391 usleep_range(1000, 1500);
393 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
394 usleep_range(2500, 3000);
396 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
397 usleep_range(2500, 3000);
401 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
403 struct drm_device
*dev
= encoder
->base
.dev
;
405 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
406 vlv_dsi_device_ready(encoder
);
407 else if (IS_BROXTON(dev
))
408 bxt_dsi_device_ready(encoder
);
411 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
413 struct drm_device
*dev
= encoder
->base
.dev
;
414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
415 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
416 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
419 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
422 temp
= I915_READ(VLV_CHICKEN_3
);
423 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
424 intel_dsi
->pixel_overlap
<<
425 PIXEL_OVERLAP_CNT_SHIFT
;
426 I915_WRITE(VLV_CHICKEN_3
, temp
);
429 for_each_dsi_port(port
, intel_dsi
->ports
) {
430 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
431 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
434 temp
= I915_READ(port_ctrl
);
436 temp
&= ~LANE_CONFIGURATION_MASK
;
437 temp
&= ~DUAL_LINK_MODE_MASK
;
439 if (intel_dsi
->ports
== (BIT(PORT_A
) | BIT(PORT_C
))) {
440 temp
|= (intel_dsi
->dual_link
- 1)
441 << DUAL_LINK_MODE_SHIFT
;
442 temp
|= intel_crtc
->pipe
?
443 LANE_CONFIGURATION_DUAL_LINK_B
:
444 LANE_CONFIGURATION_DUAL_LINK_A
;
446 /* assert ip_tg_enable signal */
447 I915_WRITE(port_ctrl
, temp
| DPI_ENABLE
);
448 POSTING_READ(port_ctrl
);
452 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
454 struct drm_device
*dev
= encoder
->base
.dev
;
455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
456 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
459 for_each_dsi_port(port
, intel_dsi
->ports
) {
460 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
461 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
464 /* de-assert ip_tg_enable signal */
465 temp
= I915_READ(port_ctrl
);
466 I915_WRITE(port_ctrl
, temp
& ~DPI_ENABLE
);
467 POSTING_READ(port_ctrl
);
471 static void intel_dsi_enable(struct intel_encoder
*encoder
)
473 struct drm_device
*dev
= encoder
->base
.dev
;
474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
475 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
480 if (is_cmd_mode(intel_dsi
)) {
481 for_each_dsi_port(port
, intel_dsi
->ports
)
482 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
484 msleep(20); /* XXX */
485 for_each_dsi_port(port
, intel_dsi
->ports
)
486 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
489 drm_panel_enable(intel_dsi
->panel
);
491 for_each_dsi_port(port
, intel_dsi
->ports
)
492 wait_for_dsi_fifo_empty(intel_dsi
, port
);
494 intel_dsi_port_enable(encoder
);
497 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
500 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
);
502 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
504 struct drm_device
*dev
= encoder
->base
.dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
513 * The BIOS may leave the PLL in a wonky state where it doesn't
514 * lock. It needs to be fully powered down to fix it.
516 intel_disable_dsi_pll(encoder
);
517 intel_enable_dsi_pll(encoder
);
519 intel_dsi_prepare(encoder
);
521 /* Panel Enable over CRC PMIC */
522 if (intel_dsi
->gpio_panel
)
523 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
525 msleep(intel_dsi
->panel_on_delay
);
527 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
528 /* Disable DPOunit clock gating, can stall pipe */
529 tmp
= I915_READ(DSPCLK_GATE_D
);
530 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
531 I915_WRITE(DSPCLK_GATE_D
, tmp
);
534 /* put device in ready state */
535 intel_dsi_device_ready(encoder
);
537 drm_panel_prepare(intel_dsi
->panel
);
539 for_each_dsi_port(port
, intel_dsi
->ports
)
540 wait_for_dsi_fifo_empty(intel_dsi
, port
);
542 /* Enable port in pre-enable phase itself because as per hw team
543 * recommendation, port should be enabled befor plane & pipe */
544 intel_dsi_enable(encoder
);
547 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
551 /* for DSI port enable has to be done before pipe
552 * and plane enable, so port enable is done in
553 * pre_enable phase itself unlike other encoders
557 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
559 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
564 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
566 if (is_vid_mode(intel_dsi
)) {
567 /* Send Shutdown command to the panel in LP mode */
568 for_each_dsi_port(port
, intel_dsi
->ports
)
569 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
574 static void intel_dsi_disable(struct intel_encoder
*encoder
)
576 struct drm_device
*dev
= encoder
->base
.dev
;
577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
578 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
584 if (is_vid_mode(intel_dsi
)) {
585 for_each_dsi_port(port
, intel_dsi
->ports
)
586 wait_for_dsi_fifo_empty(intel_dsi
, port
);
588 intel_dsi_port_disable(encoder
);
592 for_each_dsi_port(port
, intel_dsi
->ports
) {
593 /* Panel commands can be sent when clock is in LP11 */
594 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
596 intel_dsi_reset_clocks(encoder
, port
);
597 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
599 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
600 temp
&= ~VID_MODE_FORMAT_MASK
;
601 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
603 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
605 /* if disable packets are sent before sending shutdown packet then in
606 * some next enable sequence send turn on packet error is observed */
607 drm_panel_disable(intel_dsi
->panel
);
609 for_each_dsi_port(port
, intel_dsi
->ports
)
610 wait_for_dsi_fifo_empty(intel_dsi
, port
);
613 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
615 struct drm_device
*dev
= encoder
->base
.dev
;
616 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
617 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
621 for_each_dsi_port(port
, intel_dsi
->ports
) {
622 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
623 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
624 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(PORT_A
);
627 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
629 usleep_range(2000, 2500);
631 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
633 usleep_range(2000, 2500);
635 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
637 usleep_range(2000, 2500);
639 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
640 * only. MIPI Port C has no similar bit for checking
642 if (wait_for(((I915_READ(port_ctrl
) & AFE_LATCHOUT
)
644 DRM_ERROR("DSI LP not going Low\n");
646 /* Disable MIPI PHY transparent latch */
647 val
= I915_READ(port_ctrl
);
648 I915_WRITE(port_ctrl
, val
& ~LP_OUTPUT_HOLD
);
649 usleep_range(1000, 1500);
651 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
652 usleep_range(2000, 2500);
655 intel_disable_dsi_pll(encoder
);
658 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
660 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
661 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
665 intel_dsi_disable(encoder
);
667 intel_dsi_clear_device_ready(encoder
);
669 if (!IS_BROXTON(dev_priv
)) {
672 val
= I915_READ(DSPCLK_GATE_D
);
673 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
674 I915_WRITE(DSPCLK_GATE_D
, val
);
677 drm_panel_unprepare(intel_dsi
->panel
);
679 msleep(intel_dsi
->panel_off_delay
);
680 msleep(intel_dsi
->panel_pwr_cycle_delay
);
682 /* Panel Disable over CRC PMIC */
683 if (intel_dsi
->gpio_panel
)
684 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
687 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
690 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
691 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
692 struct drm_device
*dev
= encoder
->base
.dev
;
693 enum intel_display_power_domain power_domain
;
699 power_domain
= intel_display_port_power_domain(encoder
);
700 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
704 * On Broxton the PLL needs to be enabled with a valid divider
705 * configuration, otherwise accessing DSI registers will hang the
706 * machine. See BSpec North Display Engine registers/MIPI[BXT].
708 if (IS_BROXTON(dev_priv
) && !intel_dsi_pll_is_enabled(dev_priv
))
711 /* XXX: this only works for one DSI output */
712 for_each_dsi_port(port
, intel_dsi
->ports
) {
713 i915_reg_t ctrl_reg
= IS_BROXTON(dev
) ?
714 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
715 bool enabled
= I915_READ(ctrl_reg
) & DPI_ENABLE
;
717 /* Due to some hardware limitations on BYT, MIPI Port C DPI
718 * Enable bit does not get set. To check whether DSI Port C
719 * was enabled in BIOS, check the Pipe B enable bit
721 if (IS_VALLEYVIEW(dev
) && port
== PORT_C
)
722 enabled
= I915_READ(PIPECONF(PIPE_B
)) & PIPECONF_ENABLE
;
724 /* Try command mode if video mode not enabled */
726 u32 tmp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
727 enabled
= tmp
& CMD_MODE_DATA_WIDTH_MASK
;
733 if (!(I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
))
736 if (IS_BROXTON(dev_priv
)) {
737 u32 tmp
= I915_READ(MIPI_CTRL(port
));
738 tmp
&= BXT_PIPE_SELECT_MASK
;
739 tmp
>>= BXT_PIPE_SELECT_SHIFT
;
741 if (WARN_ON(tmp
> PIPE_C
))
746 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
754 intel_display_power_put(dev_priv
, power_domain
);
759 static void bxt_dsi_get_pipe_config(struct intel_encoder
*encoder
,
760 struct intel_crtc_state
*pipe_config
)
762 struct drm_device
*dev
= encoder
->base
.dev
;
763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
764 struct drm_display_mode
*adjusted_mode
=
765 &pipe_config
->base
.adjusted_mode
;
766 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
767 unsigned int bpp
, fmt
;
772 * Atleast one port is active as encoder->get_config called only if
773 * encoder->get_hw_state() returns true.
775 for_each_dsi_port(port
, intel_dsi
->ports
) {
776 if (I915_READ(BXT_MIPI_PORT_CTRL(port
)) & DPI_ENABLE
)
780 fmt
= I915_READ(MIPI_DSI_FUNC_PRG(port
)) & VID_MODE_FORMAT_MASK
;
781 pipe_config
->pipe_bpp
=
782 mipi_dsi_pixel_format_to_bpp(
783 pixel_format_from_register_bits(fmt
));
784 bpp
= pipe_config
->pipe_bpp
;
786 /* In terms of pixels */
787 adjusted_mode
->crtc_hdisplay
=
788 I915_READ(BXT_MIPI_TRANS_HACTIVE(port
));
789 adjusted_mode
->crtc_vdisplay
=
790 I915_READ(BXT_MIPI_TRANS_VACTIVE(port
));
791 adjusted_mode
->crtc_vtotal
=
792 I915_READ(BXT_MIPI_TRANS_VTOTAL(port
));
795 * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and
796 * calculate hsync_start, hsync_end, htotal and hblank_end
799 /* vertical values are in terms of lines */
800 vfp
= I915_READ(MIPI_VFP_COUNT(port
));
801 vsync
= I915_READ(MIPI_VSYNC_PADDING_COUNT(port
));
802 vbp
= I915_READ(MIPI_VBP_COUNT(port
));
804 adjusted_mode
->crtc_hblank_start
= adjusted_mode
->crtc_hdisplay
;
806 adjusted_mode
->crtc_vsync_start
=
807 vfp
+ adjusted_mode
->crtc_vdisplay
;
808 adjusted_mode
->crtc_vsync_end
=
809 vsync
+ adjusted_mode
->crtc_vsync_start
;
810 adjusted_mode
->crtc_vblank_start
= adjusted_mode
->crtc_vdisplay
;
811 adjusted_mode
->crtc_vblank_end
= adjusted_mode
->crtc_vtotal
;
815 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
816 struct intel_crtc_state
*pipe_config
)
818 struct drm_device
*dev
= encoder
->base
.dev
;
822 pipe_config
->has_dsi_encoder
= true;
825 bxt_dsi_get_pipe_config(encoder
, pipe_config
);
827 pclk
= intel_dsi_get_pclk(encoder
, pipe_config
->pipe_bpp
);
831 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
832 pipe_config
->port_clock
= pclk
;
835 static enum drm_mode_status
836 intel_dsi_mode_valid(struct drm_connector
*connector
,
837 struct drm_display_mode
*mode
)
839 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
840 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
841 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
845 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
846 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
847 return MODE_NO_DBLESCAN
;
851 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
853 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
855 if (fixed_mode
->clock
> max_dotclk
)
856 return MODE_CLOCK_HIGH
;
862 /* return txclkesc cycles in terms of divider and duration in us */
863 static u16
txclkesc(u32 divider
, unsigned int us
)
866 case ESCAPE_CLOCK_DIVIDER_1
:
869 case ESCAPE_CLOCK_DIVIDER_2
:
871 case ESCAPE_CLOCK_DIVIDER_4
:
876 /* return pixels in terms of txbyteclkhs */
877 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
878 u16 burst_mode_ratio
)
880 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
881 8 * 100), lane_count
);
884 static void set_dsi_timings(struct drm_encoder
*encoder
,
885 const struct drm_display_mode
*adjusted_mode
)
887 struct drm_device
*dev
= encoder
->dev
;
888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
889 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
891 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
892 unsigned int lane_count
= intel_dsi
->lane_count
;
894 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
896 hactive
= adjusted_mode
->crtc_hdisplay
;
897 hfp
= adjusted_mode
->crtc_hsync_start
- adjusted_mode
->crtc_hdisplay
;
898 hsync
= adjusted_mode
->crtc_hsync_end
- adjusted_mode
->crtc_hsync_start
;
899 hbp
= adjusted_mode
->crtc_htotal
- adjusted_mode
->crtc_hsync_end
;
901 if (intel_dsi
->dual_link
) {
903 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
904 hactive
+= intel_dsi
->pixel_overlap
;
910 vfp
= adjusted_mode
->crtc_vsync_start
- adjusted_mode
->crtc_vdisplay
;
911 vsync
= adjusted_mode
->crtc_vsync_end
- adjusted_mode
->crtc_vsync_start
;
912 vbp
= adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vsync_end
;
914 /* horizontal values are in terms of high speed byte clock */
915 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
916 intel_dsi
->burst_mode_ratio
);
917 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
918 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
919 intel_dsi
->burst_mode_ratio
);
920 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
922 for_each_dsi_port(port
, intel_dsi
->ports
) {
923 if (IS_BROXTON(dev
)) {
925 * Program hdisplay and vdisplay on MIPI transcoder.
926 * This is different from calculated hactive and
927 * vactive, as they are calculated per channel basis,
928 * whereas these values should be based on resolution.
930 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port
),
931 adjusted_mode
->crtc_hdisplay
);
932 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port
),
933 adjusted_mode
->crtc_vdisplay
);
934 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port
),
935 adjusted_mode
->crtc_vtotal
);
938 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
939 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
941 /* meaningful for video mode non-burst sync pulse mode only,
942 * can be zero for non-burst sync events and burst modes */
943 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
944 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
946 /* vertical values are in terms of lines */
947 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
948 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
949 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
953 static u32
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt
)
956 case MIPI_DSI_FMT_RGB888
:
957 return VID_MODE_FORMAT_RGB888
;
958 case MIPI_DSI_FMT_RGB666
:
959 return VID_MODE_FORMAT_RGB666
;
960 case MIPI_DSI_FMT_RGB666_PACKED
:
961 return VID_MODE_FORMAT_RGB666_PACKED
;
962 case MIPI_DSI_FMT_RGB565
:
963 return VID_MODE_FORMAT_RGB565
;
966 return VID_MODE_FORMAT_RGB666
;
970 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
972 struct drm_encoder
*encoder
= &intel_encoder
->base
;
973 struct drm_device
*dev
= encoder
->dev
;
974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
975 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
976 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
977 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
979 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
983 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
985 mode_hdisplay
= adjusted_mode
->crtc_hdisplay
;
987 if (intel_dsi
->dual_link
) {
989 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
990 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
993 for_each_dsi_port(port
, intel_dsi
->ports
) {
994 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
996 * escape clock divider, 20MHz, shared for A and C.
997 * device ready must be off when doing this! txclkesc?
999 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
1000 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
1001 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
|
1002 ESCAPE_CLOCK_DIVIDER_1
);
1004 /* read request priority is per pipe */
1005 tmp
= I915_READ(MIPI_CTRL(port
));
1006 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
1007 I915_WRITE(MIPI_CTRL(port
), tmp
|
1008 READ_REQUEST_PRIORITY_HIGH
);
1009 } else if (IS_BROXTON(dev
)) {
1010 enum pipe pipe
= intel_crtc
->pipe
;
1012 tmp
= I915_READ(MIPI_CTRL(port
));
1013 tmp
&= ~BXT_PIPE_SELECT_MASK
;
1015 tmp
|= BXT_PIPE_SELECT(pipe
);
1016 I915_WRITE(MIPI_CTRL(port
), tmp
);
1019 /* XXX: why here, why like this? handling in irq handler?! */
1020 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
1021 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
1023 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
1025 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
1026 adjusted_mode
->crtc_vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
1027 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
1030 set_dsi_timings(encoder
, adjusted_mode
);
1032 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
1033 if (is_cmd_mode(intel_dsi
)) {
1034 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
1035 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
1037 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
1038 val
|= pixel_format_to_reg(intel_dsi
->pixel_format
);
1042 if (intel_dsi
->eotp_pkt
== 0)
1044 if (intel_dsi
->clock_stop
)
1047 for_each_dsi_port(port
, intel_dsi
->ports
) {
1048 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
1050 /* timeouts for recovery. one frame IIUC. if counter expires,
1051 * EOT and stop state. */
1054 * In burst mode, value greater than one DPI line Time in byte
1055 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1056 * said value is recommended.
1058 * In non-burst mode, Value greater than one DPI frame time in
1059 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1060 * said value is recommended.
1062 * In DBI only mode, value greater than one DBI frame time in
1063 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1064 * said value is recommended.
1067 if (is_vid_mode(intel_dsi
) &&
1068 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
1069 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1070 txbyteclkhs(adjusted_mode
->crtc_htotal
, bpp
,
1071 intel_dsi
->lane_count
,
1072 intel_dsi
->burst_mode_ratio
) + 1);
1074 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1075 txbyteclkhs(adjusted_mode
->crtc_vtotal
*
1076 adjusted_mode
->crtc_htotal
,
1077 bpp
, intel_dsi
->lane_count
,
1078 intel_dsi
->burst_mode_ratio
) + 1);
1080 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
1081 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
1082 intel_dsi
->turn_arnd_val
);
1083 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
1084 intel_dsi
->rst_timer_val
);
1088 /* in terms of low power clock */
1089 I915_WRITE(MIPI_INIT_COUNT(port
),
1090 txclkesc(intel_dsi
->escape_clk_div
, 100));
1092 if (IS_BROXTON(dev
) && (!intel_dsi
->dual_link
)) {
1094 * BXT spec says write MIPI_INIT_COUNT for
1095 * both the ports, even if only one is
1096 * getting used. So write the other port
1097 * if not in dual link mode.
1099 I915_WRITE(MIPI_INIT_COUNT(port
==
1100 PORT_A
? PORT_C
: PORT_A
),
1101 intel_dsi
->init_count
);
1104 /* recovery disables */
1105 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
1107 /* in terms of low power clock */
1108 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
1110 /* in terms of txbyteclkhs. actual high to low switch +
1111 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1113 * XXX: write MIPI_STOP_STATE_STALL?
1115 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
1116 intel_dsi
->hs_to_lp_count
);
1118 /* XXX: low power clock equivalence in terms of byte clock.
1119 * the number of byte clocks occupied in one low power clock.
1120 * based on txbyteclkhs and txclkesc.
1121 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1124 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
1126 /* the bw essential for transmitting 16 long packets containing
1127 * 252 bytes meant for dcs write memory command is programmed in
1128 * this register in terms of byte clocks. based on dsi transfer
1129 * rate and the number of lanes configured the time taken to
1130 * transmit 16 long packets in a dsi stream varies. */
1131 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
1133 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
1134 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
1135 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
1137 if (is_vid_mode(intel_dsi
))
1138 /* Some panels might have resolution which is not a
1139 * multiple of 64 like 1366 x 768. Enable RANDOM
1140 * resolution support for such panels by default */
1141 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
1142 intel_dsi
->video_frmt_cfg_bits
|
1143 intel_dsi
->video_mode_format
|
1145 RANDOM_DPI_DISPLAY_RESOLUTION
);
1149 static enum drm_connector_status
1150 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
1152 return connector_status_connected
;
1155 static int intel_dsi_get_modes(struct drm_connector
*connector
)
1157 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1158 struct drm_display_mode
*mode
;
1160 DRM_DEBUG_KMS("\n");
1162 if (!intel_connector
->panel
.fixed_mode
) {
1163 DRM_DEBUG_KMS("no fixed mode\n");
1167 mode
= drm_mode_duplicate(connector
->dev
,
1168 intel_connector
->panel
.fixed_mode
);
1170 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1174 drm_mode_probed_add(connector
, mode
);
1178 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
1180 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1182 DRM_DEBUG_KMS("\n");
1183 intel_panel_fini(&intel_connector
->panel
);
1184 drm_connector_cleanup(connector
);
1188 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1190 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1192 if (intel_dsi
->panel
) {
1193 drm_panel_detach(intel_dsi
->panel
);
1194 /* XXX: Logically this call belongs in the panel driver. */
1195 drm_panel_remove(intel_dsi
->panel
);
1198 /* dispose of the gpios */
1199 if (intel_dsi
->gpio_panel
)
1200 gpiod_put(intel_dsi
->gpio_panel
);
1202 intel_encoder_destroy(encoder
);
1205 static const struct drm_encoder_funcs intel_dsi_funcs
= {
1206 .destroy
= intel_dsi_encoder_destroy
,
1209 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
1210 .get_modes
= intel_dsi_get_modes
,
1211 .mode_valid
= intel_dsi_mode_valid
,
1212 .best_encoder
= intel_best_encoder
,
1215 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
1216 .dpms
= drm_atomic_helper_connector_dpms
,
1217 .detect
= intel_dsi_detect
,
1218 .destroy
= intel_dsi_connector_destroy
,
1219 .fill_modes
= drm_helper_probe_single_connector_modes
,
1220 .atomic_get_property
= intel_connector_atomic_get_property
,
1221 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1222 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1225 void intel_dsi_init(struct drm_device
*dev
)
1227 struct intel_dsi
*intel_dsi
;
1228 struct intel_encoder
*intel_encoder
;
1229 struct drm_encoder
*encoder
;
1230 struct intel_connector
*intel_connector
;
1231 struct drm_connector
*connector
;
1232 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1237 DRM_DEBUG_KMS("\n");
1239 /* There is no detection method for MIPI so rely on VBT */
1240 if (!intel_bios_is_dsi_present(dev_priv
, &port
))
1243 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1244 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1245 } else if (IS_BROXTON(dev
)) {
1246 dev_priv
->mipi_mmio_base
= BXT_MIPI_BASE
;
1248 DRM_ERROR("Unsupported Mipi device to reg base");
1252 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1256 intel_connector
= intel_connector_alloc();
1257 if (!intel_connector
) {
1262 intel_encoder
= &intel_dsi
->base
;
1263 encoder
= &intel_encoder
->base
;
1264 intel_dsi
->attached_connector
= intel_connector
;
1266 connector
= &intel_connector
->base
;
1268 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
,
1271 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1272 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1273 intel_encoder
->enable
= intel_dsi_enable_nop
;
1274 intel_encoder
->disable
= intel_dsi_pre_disable
;
1275 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1276 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1277 intel_encoder
->get_config
= intel_dsi_get_config
;
1279 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1280 intel_connector
->unregister
= intel_connector_unregister
;
1283 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1284 * port C. BXT isn't limited like this.
1286 if (IS_BROXTON(dev_priv
))
1287 intel_encoder
->crtc_mask
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
);
1288 else if (port
== PORT_A
)
1289 intel_encoder
->crtc_mask
= BIT(PIPE_A
);
1291 intel_encoder
->crtc_mask
= BIT(PIPE_B
);
1293 if (dev_priv
->vbt
.dsi
.config
->dual_link
)
1294 intel_dsi
->ports
= BIT(PORT_A
) | BIT(PORT_C
);
1296 intel_dsi
->ports
= BIT(port
);
1298 /* Create a DSI host (and a device) for each port. */
1299 for_each_dsi_port(port
, intel_dsi
->ports
) {
1300 struct intel_dsi_host
*host
;
1302 host
= intel_dsi_host_init(intel_dsi
, port
);
1306 intel_dsi
->dsi_hosts
[port
] = host
;
1309 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1310 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1311 intel_dsi_drivers
[i
].panel_id
);
1312 if (intel_dsi
->panel
)
1316 if (!intel_dsi
->panel
) {
1317 DRM_DEBUG_KMS("no device found\n");
1322 * In case of BYT with CRC PMIC, we need to use GPIO for
1325 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1326 intel_dsi
->gpio_panel
=
1327 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1329 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1330 DRM_ERROR("Failed to own gpio for panel control\n");
1331 intel_dsi
->gpio_panel
= NULL
;
1335 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1336 intel_encoder
->cloneable
= 0;
1337 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1338 DRM_MODE_CONNECTOR_DSI
);
1340 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1342 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1343 connector
->interlace_allowed
= false;
1344 connector
->doublescan_allowed
= false;
1346 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1348 drm_connector_register(connector
);
1350 drm_panel_attach(intel_dsi
->panel
, connector
);
1352 mutex_lock(&dev
->mode_config
.mutex
);
1353 drm_panel_get_modes(intel_dsi
->panel
);
1354 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1355 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1356 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1360 mutex_unlock(&dev
->mode_config
.mutex
);
1363 DRM_DEBUG_KMS("no fixed mode\n");
1367 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1368 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1373 drm_encoder_cleanup(&intel_encoder
->base
);
1375 kfree(intel_connector
);