2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 /* return pixels in terms of txbyteclkhs */
50 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
53 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
54 8 * 100), lane_count
);
57 /* return pixels equvalent to txbyteclkhs */
58 static u16
pixels_from_txbyteclkhs(u16 clk_hs
, int bpp
, int lane_count
,
61 return DIV_ROUND_UP((clk_hs
* lane_count
* 8 * 100),
62 (bpp
* burst_mode_ratio
));
65 enum mipi_dsi_pixel_format
pixel_format_from_register_bits(u32 fmt
)
67 /* It just so happens the VBT matches register contents. */
69 case VID_MODE_FORMAT_RGB888
:
70 return MIPI_DSI_FMT_RGB888
;
71 case VID_MODE_FORMAT_RGB666
:
72 return MIPI_DSI_FMT_RGB666
;
73 case VID_MODE_FORMAT_RGB666_PACKED
:
74 return MIPI_DSI_FMT_RGB666_PACKED
;
75 case VID_MODE_FORMAT_RGB565
:
76 return MIPI_DSI_FMT_RGB565
;
79 return MIPI_DSI_FMT_RGB666
;
83 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
85 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
86 struct drm_device
*dev
= encoder
->dev
;
87 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
90 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
91 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
93 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
94 DRM_ERROR("DPI FIFOs are not empty\n");
97 static void write_data(struct drm_i915_private
*dev_priv
,
99 const u8
*data
, u32 len
)
103 for (i
= 0; i
< len
; i
+= 4) {
106 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
107 val
|= *data
++ << 8 * j
;
109 I915_WRITE(reg
, val
);
113 static void read_data(struct drm_i915_private
*dev_priv
,
119 for (i
= 0; i
< len
; i
+= 4) {
120 u32 val
= I915_READ(reg
);
122 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
123 *data
++ = val
>> 8 * j
;
127 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
128 const struct mipi_dsi_msg
*msg
)
130 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
131 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 enum port port
= intel_dsi_host
->port
;
134 struct mipi_dsi_packet packet
;
136 const u8
*header
, *data
;
137 i915_reg_t data_reg
, ctrl_reg
;
138 u32 data_mask
, ctrl_mask
;
140 ret
= mipi_dsi_create_packet(&packet
, msg
);
144 header
= packet
.header
;
145 data
= packet
.payload
;
147 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
148 data_reg
= MIPI_LP_GEN_DATA(port
);
149 data_mask
= LP_DATA_FIFO_FULL
;
150 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
151 ctrl_mask
= LP_CTRL_FIFO_FULL
;
153 data_reg
= MIPI_HS_GEN_DATA(port
);
154 data_mask
= HS_DATA_FIFO_FULL
;
155 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
156 ctrl_mask
= HS_CTRL_FIFO_FULL
;
159 /* note: this is never true for reads */
160 if (packet
.payload_length
) {
162 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
163 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
165 write_data(dev_priv
, data_reg
, packet
.payload
,
166 packet
.payload_length
);
170 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
173 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
174 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
177 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
179 /* ->rx_len is set only for reads */
181 data_mask
= GEN_READ_DATA_AVAIL
;
182 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
183 DRM_ERROR("Timeout waiting for read data.\n");
185 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
188 /* XXX: fix for reads and writes */
189 return 4 + packet
.payload_length
;
192 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
193 struct mipi_dsi_device
*dsi
)
198 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
199 struct mipi_dsi_device
*dsi
)
204 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
205 .attach
= intel_dsi_host_attach
,
206 .detach
= intel_dsi_host_detach
,
207 .transfer
= intel_dsi_host_transfer
,
210 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
213 struct intel_dsi_host
*host
;
214 struct mipi_dsi_device
*device
;
216 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
220 host
->base
.ops
= &intel_dsi_host_ops
;
221 host
->intel_dsi
= intel_dsi
;
225 * We should call mipi_dsi_host_register(&host->base) here, but we don't
226 * have a host->dev, and we don't have OF stuff either. So just use the
227 * dsi framework as a library and hope for the best. Create the dsi
228 * devices by ourselves here too. Need to be careful though, because we
229 * don't initialize any of the driver model devices here.
231 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
237 device
->host
= &host
->base
;
238 host
->device
= device
;
244 * send a video mode command
246 * XXX: commands with data in MIPI_DPI_DATA?
248 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
251 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
252 struct drm_device
*dev
= encoder
->dev
;
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
265 /* XXX: old code skips write if control unchanged */
266 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
267 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
269 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
271 mask
= SPL_PKT_SENT_INTERRUPT
;
272 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
273 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
278 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
280 mutex_lock(&dev_priv
->sb_lock
);
282 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
283 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
284 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
286 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
287 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
289 mutex_unlock(&dev_priv
->sb_lock
);
292 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
294 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
297 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
299 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
302 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
303 struct intel_crtc_state
*pipe_config
)
305 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
306 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
308 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
309 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
310 const struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
311 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
316 pipe_config
->has_dsi_encoder
= true;
319 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
321 if (HAS_GMCH_DISPLAY(dev_priv
))
322 intel_gmch_panel_fitting(crtc
, pipe_config
,
323 intel_connector
->panel
.fitting_mode
);
325 intel_pch_panel_fitting(crtc
, pipe_config
,
326 intel_connector
->panel
.fitting_mode
);
329 /* DSI uses short packets for sync events, so clear mode flags for DSI */
330 adjusted_mode
->flags
= 0;
332 if (IS_BROXTON(dev_priv
)) {
333 /* Dual link goes to DSI transcoder A. */
334 if (intel_dsi
->ports
== BIT(PORT_C
))
335 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_C
;
337 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_A
;
340 ret
= intel_compute_dsi_pll(encoder
, pipe_config
);
344 pipe_config
->clock_set
= true;
349 static void bxt_dsi_device_ready(struct intel_encoder
*encoder
)
351 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
352 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
358 /* Exit Low power state in 4 steps*/
359 for_each_dsi_port(port
, intel_dsi
->ports
) {
361 /* 1. Enable MIPI PHY transparent latch */
362 val
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
363 I915_WRITE(BXT_MIPI_PORT_CTRL(port
), val
| LP_OUTPUT_HOLD
);
364 usleep_range(2000, 2500);
367 val
= I915_READ(MIPI_DEVICE_READY(port
));
368 val
&= ~ULPS_STATE_MASK
;
369 val
|= (ULPS_STATE_ENTER
| DEVICE_READY
);
370 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
374 val
= I915_READ(MIPI_DEVICE_READY(port
));
375 val
&= ~ULPS_STATE_MASK
;
376 val
|= (ULPS_STATE_EXIT
| DEVICE_READY
);
377 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
378 usleep_range(1000, 1500);
380 /* Clear ULPS and set device ready */
381 val
= I915_READ(MIPI_DEVICE_READY(port
));
382 val
&= ~ULPS_STATE_MASK
;
384 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
388 static void vlv_dsi_device_ready(struct intel_encoder
*encoder
)
390 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
391 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
397 mutex_lock(&dev_priv
->sb_lock
);
398 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
399 * needed everytime after power gate */
400 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
401 mutex_unlock(&dev_priv
->sb_lock
);
403 /* bandgap reset is needed after everytime we do power gate */
404 band_gap_reset(dev_priv
);
406 for_each_dsi_port(port
, intel_dsi
->ports
) {
408 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
409 usleep_range(2500, 3000);
411 /* Enable MIPI PHY transparent latch
412 * Common bit for both MIPI Port A & MIPI Port C
413 * No similar bit in MIPI Port C reg
415 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
416 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
417 usleep_range(1000, 1500);
419 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
420 usleep_range(2500, 3000);
422 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
423 usleep_range(2500, 3000);
427 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
429 struct drm_device
*dev
= encoder
->base
.dev
;
431 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
432 vlv_dsi_device_ready(encoder
);
433 else if (IS_BROXTON(dev
))
434 bxt_dsi_device_ready(encoder
);
437 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
439 struct drm_device
*dev
= encoder
->base
.dev
;
440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
442 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
445 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
448 temp
= I915_READ(VLV_CHICKEN_3
);
449 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
450 intel_dsi
->pixel_overlap
<<
451 PIXEL_OVERLAP_CNT_SHIFT
;
452 I915_WRITE(VLV_CHICKEN_3
, temp
);
455 for_each_dsi_port(port
, intel_dsi
->ports
) {
456 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
457 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
460 temp
= I915_READ(port_ctrl
);
462 temp
&= ~LANE_CONFIGURATION_MASK
;
463 temp
&= ~DUAL_LINK_MODE_MASK
;
465 if (intel_dsi
->ports
== (BIT(PORT_A
) | BIT(PORT_C
))) {
466 temp
|= (intel_dsi
->dual_link
- 1)
467 << DUAL_LINK_MODE_SHIFT
;
468 temp
|= intel_crtc
->pipe
?
469 LANE_CONFIGURATION_DUAL_LINK_B
:
470 LANE_CONFIGURATION_DUAL_LINK_A
;
472 /* assert ip_tg_enable signal */
473 I915_WRITE(port_ctrl
, temp
| DPI_ENABLE
);
474 POSTING_READ(port_ctrl
);
478 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
480 struct drm_device
*dev
= encoder
->base
.dev
;
481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
482 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
485 for_each_dsi_port(port
, intel_dsi
->ports
) {
486 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
487 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
490 /* de-assert ip_tg_enable signal */
491 temp
= I915_READ(port_ctrl
);
492 I915_WRITE(port_ctrl
, temp
& ~DPI_ENABLE
);
493 POSTING_READ(port_ctrl
);
497 static void intel_dsi_enable(struct intel_encoder
*encoder
)
499 struct drm_device
*dev
= encoder
->base
.dev
;
500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
501 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
506 if (is_cmd_mode(intel_dsi
)) {
507 for_each_dsi_port(port
, intel_dsi
->ports
)
508 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
510 msleep(20); /* XXX */
511 for_each_dsi_port(port
, intel_dsi
->ports
)
512 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
515 drm_panel_enable(intel_dsi
->panel
);
517 for_each_dsi_port(port
, intel_dsi
->ports
)
518 wait_for_dsi_fifo_empty(intel_dsi
, port
);
520 intel_dsi_port_enable(encoder
);
523 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
526 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
);
528 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
530 struct drm_device
*dev
= encoder
->base
.dev
;
531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
532 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
533 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
540 * The BIOS may leave the PLL in a wonky state where it doesn't
541 * lock. It needs to be fully powered down to fix it.
543 intel_disable_dsi_pll(encoder
);
544 intel_enable_dsi_pll(encoder
, crtc
->config
);
546 intel_dsi_prepare(encoder
);
548 /* Panel Enable over CRC PMIC */
549 if (intel_dsi
->gpio_panel
)
550 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
552 msleep(intel_dsi
->panel_on_delay
);
554 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
555 /* Disable DPOunit clock gating, can stall pipe */
556 tmp
= I915_READ(DSPCLK_GATE_D
);
557 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
558 I915_WRITE(DSPCLK_GATE_D
, tmp
);
561 /* put device in ready state */
562 intel_dsi_device_ready(encoder
);
564 drm_panel_prepare(intel_dsi
->panel
);
566 for_each_dsi_port(port
, intel_dsi
->ports
)
567 wait_for_dsi_fifo_empty(intel_dsi
, port
);
569 /* Enable port in pre-enable phase itself because as per hw team
570 * recommendation, port should be enabled befor plane & pipe */
571 intel_dsi_enable(encoder
);
574 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
578 /* for DSI port enable has to be done before pipe
579 * and plane enable, so port enable is done in
580 * pre_enable phase itself unlike other encoders
584 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
586 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
591 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
593 if (is_vid_mode(intel_dsi
)) {
594 /* Send Shutdown command to the panel in LP mode */
595 for_each_dsi_port(port
, intel_dsi
->ports
)
596 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
601 static void intel_dsi_disable(struct intel_encoder
*encoder
)
603 struct drm_device
*dev
= encoder
->base
.dev
;
604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
605 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
611 if (is_vid_mode(intel_dsi
)) {
612 for_each_dsi_port(port
, intel_dsi
->ports
)
613 wait_for_dsi_fifo_empty(intel_dsi
, port
);
615 intel_dsi_port_disable(encoder
);
619 for_each_dsi_port(port
, intel_dsi
->ports
) {
620 /* Panel commands can be sent when clock is in LP11 */
621 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
623 intel_dsi_reset_clocks(encoder
, port
);
624 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
626 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
627 temp
&= ~VID_MODE_FORMAT_MASK
;
628 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
630 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
632 /* if disable packets are sent before sending shutdown packet then in
633 * some next enable sequence send turn on packet error is observed */
634 drm_panel_disable(intel_dsi
->panel
);
636 for_each_dsi_port(port
, intel_dsi
->ports
)
637 wait_for_dsi_fifo_empty(intel_dsi
, port
);
640 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
642 struct drm_device
*dev
= encoder
->base
.dev
;
643 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
644 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
648 for_each_dsi_port(port
, intel_dsi
->ports
) {
649 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
650 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
651 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(PORT_A
);
654 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
656 usleep_range(2000, 2500);
658 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
660 usleep_range(2000, 2500);
662 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
664 usleep_range(2000, 2500);
666 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
667 * only. MIPI Port C has no similar bit for checking
669 if (wait_for(((I915_READ(port_ctrl
) & AFE_LATCHOUT
)
671 DRM_ERROR("DSI LP not going Low\n");
673 /* Disable MIPI PHY transparent latch */
674 val
= I915_READ(port_ctrl
);
675 I915_WRITE(port_ctrl
, val
& ~LP_OUTPUT_HOLD
);
676 usleep_range(1000, 1500);
678 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
679 usleep_range(2000, 2500);
682 intel_disable_dsi_pll(encoder
);
685 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
687 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
688 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
692 intel_dsi_disable(encoder
);
694 intel_dsi_clear_device_ready(encoder
);
696 if (!IS_BROXTON(dev_priv
)) {
699 val
= I915_READ(DSPCLK_GATE_D
);
700 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
701 I915_WRITE(DSPCLK_GATE_D
, val
);
704 drm_panel_unprepare(intel_dsi
->panel
);
706 msleep(intel_dsi
->panel_off_delay
);
708 /* Panel Disable over CRC PMIC */
709 if (intel_dsi
->gpio_panel
)
710 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
713 * FIXME As we do with eDP, just make a note of the time here
714 * and perform the wait before the next panel power on.
716 msleep(intel_dsi
->panel_pwr_cycle_delay
);
719 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
722 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
723 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
724 struct drm_device
*dev
= encoder
->base
.dev
;
725 enum intel_display_power_domain power_domain
;
731 power_domain
= intel_display_port_power_domain(encoder
);
732 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
736 * On Broxton the PLL needs to be enabled with a valid divider
737 * configuration, otherwise accessing DSI registers will hang the
738 * machine. See BSpec North Display Engine registers/MIPI[BXT].
740 if (IS_BROXTON(dev_priv
) && !intel_dsi_pll_is_enabled(dev_priv
))
743 /* XXX: this only works for one DSI output */
744 for_each_dsi_port(port
, intel_dsi
->ports
) {
745 i915_reg_t ctrl_reg
= IS_BROXTON(dev
) ?
746 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
747 bool enabled
= I915_READ(ctrl_reg
) & DPI_ENABLE
;
750 * Due to some hardware limitations on VLV/CHV, the DPI enable
751 * bit in port C control register does not get set. As a
752 * workaround, check pipe B conf instead.
754 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) && port
== PORT_C
)
755 enabled
= I915_READ(PIPECONF(PIPE_B
)) & PIPECONF_ENABLE
;
757 /* Try command mode if video mode not enabled */
759 u32 tmp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
760 enabled
= tmp
& CMD_MODE_DATA_WIDTH_MASK
;
766 if (!(I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
))
769 if (IS_BROXTON(dev_priv
)) {
770 u32 tmp
= I915_READ(MIPI_CTRL(port
));
771 tmp
&= BXT_PIPE_SELECT_MASK
;
772 tmp
>>= BXT_PIPE_SELECT_SHIFT
;
774 if (WARN_ON(tmp
> PIPE_C
))
779 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
787 intel_display_power_put(dev_priv
, power_domain
);
792 static void bxt_dsi_get_pipe_config(struct intel_encoder
*encoder
,
793 struct intel_crtc_state
*pipe_config
)
795 struct drm_device
*dev
= encoder
->base
.dev
;
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 struct drm_display_mode
*adjusted_mode
=
798 &pipe_config
->base
.adjusted_mode
;
799 struct drm_display_mode
*adjusted_mode_sw
;
800 struct intel_crtc
*intel_crtc
;
801 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
802 unsigned int lane_count
= intel_dsi
->lane_count
;
803 unsigned int bpp
, fmt
;
805 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
806 u16 hfp_sw
, hsync_sw
, hbp_sw
;
807 u16 crtc_htotal_sw
, crtc_hsync_start_sw
, crtc_hsync_end_sw
,
808 crtc_hblank_start_sw
, crtc_hblank_end_sw
;
810 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
811 adjusted_mode_sw
= &intel_crtc
->config
->base
.adjusted_mode
;
814 * Atleast one port is active as encoder->get_config called only if
815 * encoder->get_hw_state() returns true.
817 for_each_dsi_port(port
, intel_dsi
->ports
) {
818 if (I915_READ(BXT_MIPI_PORT_CTRL(port
)) & DPI_ENABLE
)
822 fmt
= I915_READ(MIPI_DSI_FUNC_PRG(port
)) & VID_MODE_FORMAT_MASK
;
823 pipe_config
->pipe_bpp
=
824 mipi_dsi_pixel_format_to_bpp(
825 pixel_format_from_register_bits(fmt
));
826 bpp
= pipe_config
->pipe_bpp
;
828 /* In terms of pixels */
829 adjusted_mode
->crtc_hdisplay
=
830 I915_READ(BXT_MIPI_TRANS_HACTIVE(port
));
831 adjusted_mode
->crtc_vdisplay
=
832 I915_READ(BXT_MIPI_TRANS_VACTIVE(port
));
833 adjusted_mode
->crtc_vtotal
=
834 I915_READ(BXT_MIPI_TRANS_VTOTAL(port
));
836 hactive
= adjusted_mode
->crtc_hdisplay
;
837 hfp
= I915_READ(MIPI_HFP_COUNT(port
));
840 * Meaningful for video mode non-burst sync pulse mode only,
841 * can be zero for non-burst sync events and burst modes
843 hsync
= I915_READ(MIPI_HSYNC_PADDING_COUNT(port
));
844 hbp
= I915_READ(MIPI_HBP_COUNT(port
));
846 /* harizontal values are in terms of high speed byte clock */
847 hfp
= pixels_from_txbyteclkhs(hfp
, bpp
, lane_count
,
848 intel_dsi
->burst_mode_ratio
);
849 hsync
= pixels_from_txbyteclkhs(hsync
, bpp
, lane_count
,
850 intel_dsi
->burst_mode_ratio
);
851 hbp
= pixels_from_txbyteclkhs(hbp
, bpp
, lane_count
,
852 intel_dsi
->burst_mode_ratio
);
854 if (intel_dsi
->dual_link
) {
860 /* vertical values are in terms of lines */
861 vfp
= I915_READ(MIPI_VFP_COUNT(port
));
862 vsync
= I915_READ(MIPI_VSYNC_PADDING_COUNT(port
));
863 vbp
= I915_READ(MIPI_VBP_COUNT(port
));
865 adjusted_mode
->crtc_htotal
= hactive
+ hfp
+ hsync
+ hbp
;
866 adjusted_mode
->crtc_hsync_start
= hfp
+ adjusted_mode
->crtc_hdisplay
;
867 adjusted_mode
->crtc_hsync_end
= hsync
+ adjusted_mode
->crtc_hsync_start
;
868 adjusted_mode
->crtc_hblank_start
= adjusted_mode
->crtc_hdisplay
;
869 adjusted_mode
->crtc_hblank_end
= adjusted_mode
->crtc_htotal
;
871 adjusted_mode
->crtc_vsync_start
= vfp
+ adjusted_mode
->crtc_vdisplay
;
872 adjusted_mode
->crtc_vsync_end
= vsync
+ adjusted_mode
->crtc_vsync_start
;
873 adjusted_mode
->crtc_vblank_start
= adjusted_mode
->crtc_vdisplay
;
874 adjusted_mode
->crtc_vblank_end
= adjusted_mode
->crtc_vtotal
;
877 * In BXT DSI there is no regs programmed with few horizontal timings
878 * in Pixels but txbyteclkhs.. So retrieval process adds some
879 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
880 * Actually here for the given adjusted_mode, we are calculating the
881 * value programmed to the port and then back to the horizontal timing
882 * param in pixels. This is the expected value, including roundup errors
883 * And if that is same as retrieved value from port, then
884 * (HW state) adjusted_mode's horizontal timings are corrected to
885 * match with SW state to nullify the errors.
887 /* Calculating the value programmed to the Port register */
888 hfp_sw
= adjusted_mode_sw
->crtc_hsync_start
-
889 adjusted_mode_sw
->crtc_hdisplay
;
890 hsync_sw
= adjusted_mode_sw
->crtc_hsync_end
-
891 adjusted_mode_sw
->crtc_hsync_start
;
892 hbp_sw
= adjusted_mode_sw
->crtc_htotal
-
893 adjusted_mode_sw
->crtc_hsync_end
;
895 if (intel_dsi
->dual_link
) {
901 hfp_sw
= txbyteclkhs(hfp_sw
, bpp
, lane_count
,
902 intel_dsi
->burst_mode_ratio
);
903 hsync_sw
= txbyteclkhs(hsync_sw
, bpp
, lane_count
,
904 intel_dsi
->burst_mode_ratio
);
905 hbp_sw
= txbyteclkhs(hbp_sw
, bpp
, lane_count
,
906 intel_dsi
->burst_mode_ratio
);
908 /* Reverse calculating the adjusted mode parameters from port reg vals*/
909 hfp_sw
= pixels_from_txbyteclkhs(hfp_sw
, bpp
, lane_count
,
910 intel_dsi
->burst_mode_ratio
);
911 hsync_sw
= pixels_from_txbyteclkhs(hsync_sw
, bpp
, lane_count
,
912 intel_dsi
->burst_mode_ratio
);
913 hbp_sw
= pixels_from_txbyteclkhs(hbp_sw
, bpp
, lane_count
,
914 intel_dsi
->burst_mode_ratio
);
916 if (intel_dsi
->dual_link
) {
922 crtc_htotal_sw
= adjusted_mode_sw
->crtc_hdisplay
+ hfp_sw
+
924 crtc_hsync_start_sw
= hfp_sw
+ adjusted_mode_sw
->crtc_hdisplay
;
925 crtc_hsync_end_sw
= hsync_sw
+ crtc_hsync_start_sw
;
926 crtc_hblank_start_sw
= adjusted_mode_sw
->crtc_hdisplay
;
927 crtc_hblank_end_sw
= crtc_htotal_sw
;
929 if (adjusted_mode
->crtc_htotal
== crtc_htotal_sw
)
930 adjusted_mode
->crtc_htotal
= adjusted_mode_sw
->crtc_htotal
;
932 if (adjusted_mode
->crtc_hsync_start
== crtc_hsync_start_sw
)
933 adjusted_mode
->crtc_hsync_start
=
934 adjusted_mode_sw
->crtc_hsync_start
;
936 if (adjusted_mode
->crtc_hsync_end
== crtc_hsync_end_sw
)
937 adjusted_mode
->crtc_hsync_end
=
938 adjusted_mode_sw
->crtc_hsync_end
;
940 if (adjusted_mode
->crtc_hblank_start
== crtc_hblank_start_sw
)
941 adjusted_mode
->crtc_hblank_start
=
942 adjusted_mode_sw
->crtc_hblank_start
;
944 if (adjusted_mode
->crtc_hblank_end
== crtc_hblank_end_sw
)
945 adjusted_mode
->crtc_hblank_end
=
946 adjusted_mode_sw
->crtc_hblank_end
;
949 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
950 struct intel_crtc_state
*pipe_config
)
952 struct drm_device
*dev
= encoder
->base
.dev
;
956 pipe_config
->has_dsi_encoder
= true;
959 bxt_dsi_get_pipe_config(encoder
, pipe_config
);
961 pclk
= intel_dsi_get_pclk(encoder
, pipe_config
->pipe_bpp
,
966 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
967 pipe_config
->port_clock
= pclk
;
970 static enum drm_mode_status
971 intel_dsi_mode_valid(struct drm_connector
*connector
,
972 struct drm_display_mode
*mode
)
974 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
975 const struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
976 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
980 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
981 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
982 return MODE_NO_DBLESCAN
;
986 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
988 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
990 if (fixed_mode
->clock
> max_dotclk
)
991 return MODE_CLOCK_HIGH
;
997 /* return txclkesc cycles in terms of divider and duration in us */
998 static u16
txclkesc(u32 divider
, unsigned int us
)
1001 case ESCAPE_CLOCK_DIVIDER_1
:
1004 case ESCAPE_CLOCK_DIVIDER_2
:
1006 case ESCAPE_CLOCK_DIVIDER_4
:
1011 static void set_dsi_timings(struct drm_encoder
*encoder
,
1012 const struct drm_display_mode
*adjusted_mode
)
1014 struct drm_device
*dev
= encoder
->dev
;
1015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1016 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1018 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
1019 unsigned int lane_count
= intel_dsi
->lane_count
;
1021 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
1023 hactive
= adjusted_mode
->crtc_hdisplay
;
1024 hfp
= adjusted_mode
->crtc_hsync_start
- adjusted_mode
->crtc_hdisplay
;
1025 hsync
= adjusted_mode
->crtc_hsync_end
- adjusted_mode
->crtc_hsync_start
;
1026 hbp
= adjusted_mode
->crtc_htotal
- adjusted_mode
->crtc_hsync_end
;
1028 if (intel_dsi
->dual_link
) {
1030 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
1031 hactive
+= intel_dsi
->pixel_overlap
;
1037 vfp
= adjusted_mode
->crtc_vsync_start
- adjusted_mode
->crtc_vdisplay
;
1038 vsync
= adjusted_mode
->crtc_vsync_end
- adjusted_mode
->crtc_vsync_start
;
1039 vbp
= adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vsync_end
;
1041 /* horizontal values are in terms of high speed byte clock */
1042 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
1043 intel_dsi
->burst_mode_ratio
);
1044 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
1045 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
1046 intel_dsi
->burst_mode_ratio
);
1047 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
1049 for_each_dsi_port(port
, intel_dsi
->ports
) {
1050 if (IS_BROXTON(dev
)) {
1052 * Program hdisplay and vdisplay on MIPI transcoder.
1053 * This is different from calculated hactive and
1054 * vactive, as they are calculated per channel basis,
1055 * whereas these values should be based on resolution.
1057 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port
),
1058 adjusted_mode
->crtc_hdisplay
);
1059 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port
),
1060 adjusted_mode
->crtc_vdisplay
);
1061 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port
),
1062 adjusted_mode
->crtc_vtotal
);
1065 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
1066 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
1068 /* meaningful for video mode non-burst sync pulse mode only,
1069 * can be zero for non-burst sync events and burst modes */
1070 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
1071 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
1073 /* vertical values are in terms of lines */
1074 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
1075 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
1076 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
1080 static u32
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt
)
1083 case MIPI_DSI_FMT_RGB888
:
1084 return VID_MODE_FORMAT_RGB888
;
1085 case MIPI_DSI_FMT_RGB666
:
1086 return VID_MODE_FORMAT_RGB666
;
1087 case MIPI_DSI_FMT_RGB666_PACKED
:
1088 return VID_MODE_FORMAT_RGB666_PACKED
;
1089 case MIPI_DSI_FMT_RGB565
:
1090 return VID_MODE_FORMAT_RGB565
;
1093 return VID_MODE_FORMAT_RGB666
;
1097 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
1099 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1100 struct drm_device
*dev
= encoder
->dev
;
1101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1102 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
1103 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1104 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
1106 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
1110 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
1112 mode_hdisplay
= adjusted_mode
->crtc_hdisplay
;
1114 if (intel_dsi
->dual_link
) {
1116 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
1117 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
1120 for_each_dsi_port(port
, intel_dsi
->ports
) {
1121 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1123 * escape clock divider, 20MHz, shared for A and C.
1124 * device ready must be off when doing this! txclkesc?
1126 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
1127 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
1128 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
|
1129 ESCAPE_CLOCK_DIVIDER_1
);
1131 /* read request priority is per pipe */
1132 tmp
= I915_READ(MIPI_CTRL(port
));
1133 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
1134 I915_WRITE(MIPI_CTRL(port
), tmp
|
1135 READ_REQUEST_PRIORITY_HIGH
);
1136 } else if (IS_BROXTON(dev
)) {
1137 enum pipe pipe
= intel_crtc
->pipe
;
1139 tmp
= I915_READ(MIPI_CTRL(port
));
1140 tmp
&= ~BXT_PIPE_SELECT_MASK
;
1142 tmp
|= BXT_PIPE_SELECT(pipe
);
1143 I915_WRITE(MIPI_CTRL(port
), tmp
);
1146 /* XXX: why here, why like this? handling in irq handler?! */
1147 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
1148 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
1150 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
1152 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
1153 adjusted_mode
->crtc_vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
1154 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
1157 set_dsi_timings(encoder
, adjusted_mode
);
1159 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
1160 if (is_cmd_mode(intel_dsi
)) {
1161 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
1162 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
1164 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
1165 val
|= pixel_format_to_reg(intel_dsi
->pixel_format
);
1169 if (intel_dsi
->eotp_pkt
== 0)
1171 if (intel_dsi
->clock_stop
)
1174 for_each_dsi_port(port
, intel_dsi
->ports
) {
1175 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
1177 /* timeouts for recovery. one frame IIUC. if counter expires,
1178 * EOT and stop state. */
1181 * In burst mode, value greater than one DPI line Time in byte
1182 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1183 * said value is recommended.
1185 * In non-burst mode, Value greater than one DPI frame time in
1186 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1187 * said value is recommended.
1189 * In DBI only mode, value greater than one DBI frame time in
1190 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1191 * said value is recommended.
1194 if (is_vid_mode(intel_dsi
) &&
1195 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
1196 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1197 txbyteclkhs(adjusted_mode
->crtc_htotal
, bpp
,
1198 intel_dsi
->lane_count
,
1199 intel_dsi
->burst_mode_ratio
) + 1);
1201 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1202 txbyteclkhs(adjusted_mode
->crtc_vtotal
*
1203 adjusted_mode
->crtc_htotal
,
1204 bpp
, intel_dsi
->lane_count
,
1205 intel_dsi
->burst_mode_ratio
) + 1);
1207 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
1208 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
1209 intel_dsi
->turn_arnd_val
);
1210 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
1211 intel_dsi
->rst_timer_val
);
1215 /* in terms of low power clock */
1216 I915_WRITE(MIPI_INIT_COUNT(port
),
1217 txclkesc(intel_dsi
->escape_clk_div
, 100));
1219 if (IS_BROXTON(dev
) && (!intel_dsi
->dual_link
)) {
1221 * BXT spec says write MIPI_INIT_COUNT for
1222 * both the ports, even if only one is
1223 * getting used. So write the other port
1224 * if not in dual link mode.
1226 I915_WRITE(MIPI_INIT_COUNT(port
==
1227 PORT_A
? PORT_C
: PORT_A
),
1228 intel_dsi
->init_count
);
1231 /* recovery disables */
1232 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
1234 /* in terms of low power clock */
1235 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
1237 /* in terms of txbyteclkhs. actual high to low switch +
1238 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1240 * XXX: write MIPI_STOP_STATE_STALL?
1242 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
1243 intel_dsi
->hs_to_lp_count
);
1245 /* XXX: low power clock equivalence in terms of byte clock.
1246 * the number of byte clocks occupied in one low power clock.
1247 * based on txbyteclkhs and txclkesc.
1248 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1251 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
1253 /* the bw essential for transmitting 16 long packets containing
1254 * 252 bytes meant for dcs write memory command is programmed in
1255 * this register in terms of byte clocks. based on dsi transfer
1256 * rate and the number of lanes configured the time taken to
1257 * transmit 16 long packets in a dsi stream varies. */
1258 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
1260 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
1261 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
1262 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
1264 if (is_vid_mode(intel_dsi
))
1265 /* Some panels might have resolution which is not a
1266 * multiple of 64 like 1366 x 768. Enable RANDOM
1267 * resolution support for such panels by default */
1268 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
1269 intel_dsi
->video_frmt_cfg_bits
|
1270 intel_dsi
->video_mode_format
|
1272 RANDOM_DPI_DISPLAY_RESOLUTION
);
1276 static enum drm_connector_status
1277 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
1279 return connector_status_connected
;
1282 static int intel_dsi_get_modes(struct drm_connector
*connector
)
1284 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1285 struct drm_display_mode
*mode
;
1287 DRM_DEBUG_KMS("\n");
1289 if (!intel_connector
->panel
.fixed_mode
) {
1290 DRM_DEBUG_KMS("no fixed mode\n");
1294 mode
= drm_mode_duplicate(connector
->dev
,
1295 intel_connector
->panel
.fixed_mode
);
1297 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1301 drm_mode_probed_add(connector
, mode
);
1305 static int intel_dsi_set_property(struct drm_connector
*connector
,
1306 struct drm_property
*property
,
1309 struct drm_device
*dev
= connector
->dev
;
1310 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1311 struct drm_crtc
*crtc
;
1314 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1318 if (property
== dev
->mode_config
.scaling_mode_property
) {
1319 if (val
== DRM_MODE_SCALE_NONE
) {
1320 DRM_DEBUG_KMS("no scaling not supported\n");
1323 if (HAS_GMCH_DISPLAY(dev
) &&
1324 val
== DRM_MODE_SCALE_CENTER
) {
1325 DRM_DEBUG_KMS("centering not supported\n");
1329 if (intel_connector
->panel
.fitting_mode
== val
)
1332 intel_connector
->panel
.fitting_mode
= val
;
1335 crtc
= intel_attached_encoder(connector
)->base
.crtc
;
1336 if (crtc
&& crtc
->state
->enable
) {
1338 * If the CRTC is enabled, the display will be changed
1339 * according to the new panel fitting mode.
1341 intel_crtc_restore_mode(crtc
);
1347 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
1349 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1351 DRM_DEBUG_KMS("\n");
1352 intel_panel_fini(&intel_connector
->panel
);
1353 drm_connector_cleanup(connector
);
1357 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1359 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1361 if (intel_dsi
->panel
) {
1362 drm_panel_detach(intel_dsi
->panel
);
1363 /* XXX: Logically this call belongs in the panel driver. */
1364 drm_panel_remove(intel_dsi
->panel
);
1367 /* dispose of the gpios */
1368 if (intel_dsi
->gpio_panel
)
1369 gpiod_put(intel_dsi
->gpio_panel
);
1371 intel_encoder_destroy(encoder
);
1374 static const struct drm_encoder_funcs intel_dsi_funcs
= {
1375 .destroy
= intel_dsi_encoder_destroy
,
1378 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
1379 .get_modes
= intel_dsi_get_modes
,
1380 .mode_valid
= intel_dsi_mode_valid
,
1381 .best_encoder
= intel_best_encoder
,
1384 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
1385 .dpms
= drm_atomic_helper_connector_dpms
,
1386 .detect
= intel_dsi_detect
,
1387 .destroy
= intel_dsi_connector_destroy
,
1388 .fill_modes
= drm_helper_probe_single_connector_modes
,
1389 .set_property
= intel_dsi_set_property
,
1390 .atomic_get_property
= intel_connector_atomic_get_property
,
1391 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1392 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1395 static void intel_dsi_add_properties(struct intel_connector
*connector
)
1397 struct drm_device
*dev
= connector
->base
.dev
;
1399 if (connector
->panel
.fixed_mode
) {
1400 drm_mode_create_scaling_mode_property(dev
);
1401 drm_object_attach_property(&connector
->base
.base
,
1402 dev
->mode_config
.scaling_mode_property
,
1403 DRM_MODE_SCALE_ASPECT
);
1404 connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
1408 void intel_dsi_init(struct drm_device
*dev
)
1410 struct intel_dsi
*intel_dsi
;
1411 struct intel_encoder
*intel_encoder
;
1412 struct drm_encoder
*encoder
;
1413 struct intel_connector
*intel_connector
;
1414 struct drm_connector
*connector
;
1415 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1420 DRM_DEBUG_KMS("\n");
1422 /* There is no detection method for MIPI so rely on VBT */
1423 if (!intel_bios_is_dsi_present(dev_priv
, &port
))
1426 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1427 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1428 } else if (IS_BROXTON(dev
)) {
1429 dev_priv
->mipi_mmio_base
= BXT_MIPI_BASE
;
1431 DRM_ERROR("Unsupported Mipi device to reg base");
1435 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1439 intel_connector
= intel_connector_alloc();
1440 if (!intel_connector
) {
1445 intel_encoder
= &intel_dsi
->base
;
1446 encoder
= &intel_encoder
->base
;
1447 intel_dsi
->attached_connector
= intel_connector
;
1449 connector
= &intel_connector
->base
;
1451 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
,
1454 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1455 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1456 intel_encoder
->enable
= intel_dsi_enable_nop
;
1457 intel_encoder
->disable
= intel_dsi_pre_disable
;
1458 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1459 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1460 intel_encoder
->get_config
= intel_dsi_get_config
;
1462 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1463 intel_connector
->unregister
= intel_connector_unregister
;
1466 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1467 * port C. BXT isn't limited like this.
1469 if (IS_BROXTON(dev_priv
))
1470 intel_encoder
->crtc_mask
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
);
1471 else if (port
== PORT_A
)
1472 intel_encoder
->crtc_mask
= BIT(PIPE_A
);
1474 intel_encoder
->crtc_mask
= BIT(PIPE_B
);
1476 if (dev_priv
->vbt
.dsi
.config
->dual_link
)
1477 intel_dsi
->ports
= BIT(PORT_A
) | BIT(PORT_C
);
1479 intel_dsi
->ports
= BIT(port
);
1481 /* Create a DSI host (and a device) for each port. */
1482 for_each_dsi_port(port
, intel_dsi
->ports
) {
1483 struct intel_dsi_host
*host
;
1485 host
= intel_dsi_host_init(intel_dsi
, port
);
1489 intel_dsi
->dsi_hosts
[port
] = host
;
1492 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1493 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1494 intel_dsi_drivers
[i
].panel_id
);
1495 if (intel_dsi
->panel
)
1499 if (!intel_dsi
->panel
) {
1500 DRM_DEBUG_KMS("no device found\n");
1505 * In case of BYT with CRC PMIC, we need to use GPIO for
1508 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1509 intel_dsi
->gpio_panel
=
1510 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1512 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1513 DRM_ERROR("Failed to own gpio for panel control\n");
1514 intel_dsi
->gpio_panel
= NULL
;
1518 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1519 intel_encoder
->cloneable
= 0;
1520 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1521 DRM_MODE_CONNECTOR_DSI
);
1523 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1525 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1526 connector
->interlace_allowed
= false;
1527 connector
->doublescan_allowed
= false;
1529 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1531 drm_panel_attach(intel_dsi
->panel
, connector
);
1533 mutex_lock(&dev
->mode_config
.mutex
);
1534 drm_panel_get_modes(intel_dsi
->panel
);
1535 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1536 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1537 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1541 mutex_unlock(&dev
->mode_config
.mutex
);
1544 DRM_DEBUG_KMS("no fixed mode\n");
1548 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1550 intel_dsi_add_properties(intel_connector
);
1552 drm_connector_register(connector
);
1554 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1559 drm_encoder_cleanup(&intel_encoder
->base
);
1561 kfree(intel_connector
);