2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
51 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
52 struct drm_device
*dev
= encoder
->dev
;
53 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
56 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
57 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
59 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
60 DRM_ERROR("DPI FIFOs are not empty\n");
63 static void write_data(struct drm_i915_private
*dev_priv
, u32 reg
,
64 const u8
*data
, u32 len
)
68 for (i
= 0; i
< len
; i
+= 4) {
71 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
72 val
|= *data
++ << 8 * j
;
78 static void read_data(struct drm_i915_private
*dev_priv
, u32 reg
,
83 for (i
= 0; i
< len
; i
+= 4) {
84 u32 val
= I915_READ(reg
);
86 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
87 *data
++ = val
>> 8 * j
;
91 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
92 const struct mipi_dsi_msg
*msg
)
94 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
95 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
96 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
97 enum port port
= intel_dsi_host
->port
;
98 struct mipi_dsi_packet packet
;
100 const u8
*header
, *data
;
101 u32 data_reg
, data_mask
, ctrl_reg
, ctrl_mask
;
103 ret
= mipi_dsi_create_packet(&packet
, msg
);
107 header
= packet
.header
;
108 data
= packet
.payload
;
110 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
111 data_reg
= MIPI_LP_GEN_DATA(port
);
112 data_mask
= LP_DATA_FIFO_FULL
;
113 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
114 ctrl_mask
= LP_CTRL_FIFO_FULL
;
116 data_reg
= MIPI_HS_GEN_DATA(port
);
117 data_mask
= HS_DATA_FIFO_FULL
;
118 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
119 ctrl_mask
= HS_CTRL_FIFO_FULL
;
122 /* note: this is never true for reads */
123 if (packet
.payload_length
) {
125 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
126 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
128 write_data(dev_priv
, data_reg
, packet
.payload
,
129 packet
.payload_length
);
133 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
136 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
137 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
140 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
142 /* ->rx_len is set only for reads */
144 data_mask
= GEN_READ_DATA_AVAIL
;
145 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
146 DRM_ERROR("Timeout waiting for read data.\n");
148 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
151 /* XXX: fix for reads and writes */
152 return 4 + packet
.payload_length
;
155 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
156 struct mipi_dsi_device
*dsi
)
161 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
162 struct mipi_dsi_device
*dsi
)
167 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
168 .attach
= intel_dsi_host_attach
,
169 .detach
= intel_dsi_host_detach
,
170 .transfer
= intel_dsi_host_transfer
,
173 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
176 struct intel_dsi_host
*host
;
177 struct mipi_dsi_device
*device
;
179 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
183 host
->base
.ops
= &intel_dsi_host_ops
;
184 host
->intel_dsi
= intel_dsi
;
188 * We should call mipi_dsi_host_register(&host->base) here, but we don't
189 * have a host->dev, and we don't have OF stuff either. So just use the
190 * dsi framework as a library and hope for the best. Create the dsi
191 * devices by ourselves here too. Need to be careful though, because we
192 * don't initialize any of the driver model devices here.
194 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
200 device
->host
= &host
->base
;
201 host
->device
= device
;
207 * send a video mode command
209 * XXX: commands with data in MIPI_DPI_DATA?
211 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
214 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
215 struct drm_device
*dev
= encoder
->dev
;
216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
226 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
228 /* XXX: old code skips write if control unchanged */
229 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
230 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
232 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
234 mask
= SPL_PKT_SENT_INTERRUPT
;
235 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
236 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
241 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
243 mutex_lock(&dev_priv
->sb_lock
);
245 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
246 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
247 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
249 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
250 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
252 mutex_unlock(&dev_priv
->sb_lock
);
255 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
257 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
260 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
262 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
265 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
266 struct intel_crtc_state
*config
)
268 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
270 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
271 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
272 struct drm_display_mode
*adjusted_mode
= &config
->base
.adjusted_mode
;
277 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
279 /* DSI uses short packets for sync events, so clear mode flags for DSI */
280 adjusted_mode
->flags
= 0;
285 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
287 struct drm_device
*dev
= encoder
->base
.dev
;
288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
289 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
290 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
294 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
295 temp
= I915_READ(VLV_CHICKEN_3
);
296 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
297 intel_dsi
->pixel_overlap
<<
298 PIXEL_OVERLAP_CNT_SHIFT
;
299 I915_WRITE(VLV_CHICKEN_3
, temp
);
302 for_each_dsi_port(port
, intel_dsi
->ports
) {
303 temp
= I915_READ(MIPI_PORT_CTRL(port
));
304 temp
&= ~LANE_CONFIGURATION_MASK
;
305 temp
&= ~DUAL_LINK_MODE_MASK
;
307 if (intel_dsi
->ports
== ((1 << PORT_A
) | (1 << PORT_C
))) {
308 temp
|= (intel_dsi
->dual_link
- 1)
309 << DUAL_LINK_MODE_SHIFT
;
310 temp
|= intel_crtc
->pipe
?
311 LANE_CONFIGURATION_DUAL_LINK_B
:
312 LANE_CONFIGURATION_DUAL_LINK_A
;
314 /* assert ip_tg_enable signal */
315 I915_WRITE(MIPI_PORT_CTRL(port
), temp
| DPI_ENABLE
);
316 POSTING_READ(MIPI_PORT_CTRL(port
));
320 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
322 struct drm_device
*dev
= encoder
->base
.dev
;
323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
328 for_each_dsi_port(port
, intel_dsi
->ports
) {
329 /* de-assert ip_tg_enable signal */
330 temp
= I915_READ(MIPI_PORT_CTRL(port
));
331 I915_WRITE(MIPI_PORT_CTRL(port
), temp
& ~DPI_ENABLE
);
332 POSTING_READ(MIPI_PORT_CTRL(port
));
336 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
338 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
339 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
345 mutex_lock(&dev_priv
->sb_lock
);
346 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
347 * needed everytime after power gate */
348 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
349 mutex_unlock(&dev_priv
->sb_lock
);
351 /* bandgap reset is needed after everytime we do power gate */
352 band_gap_reset(dev_priv
);
354 for_each_dsi_port(port
, intel_dsi
->ports
) {
356 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
357 usleep_range(2500, 3000);
359 /* Enable MIPI PHY transparent latch
360 * Common bit for both MIPI Port A & MIPI Port C
361 * No similar bit in MIPI Port C reg
363 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
364 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
365 usleep_range(1000, 1500);
367 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
368 usleep_range(2500, 3000);
370 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
371 usleep_range(2500, 3000);
375 static void intel_dsi_enable(struct intel_encoder
*encoder
)
377 struct drm_device
*dev
= encoder
->base
.dev
;
378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
379 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
384 if (is_cmd_mode(intel_dsi
)) {
385 for_each_dsi_port(port
, intel_dsi
->ports
)
386 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
388 msleep(20); /* XXX */
389 for_each_dsi_port(port
, intel_dsi
->ports
)
390 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
393 drm_panel_enable(intel_dsi
->panel
);
395 for_each_dsi_port(port
, intel_dsi
->ports
)
396 wait_for_dsi_fifo_empty(intel_dsi
, port
);
398 intel_dsi_port_enable(encoder
);
401 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
404 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
406 struct drm_device
*dev
= encoder
->base
.dev
;
407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
408 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
409 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
410 enum pipe pipe
= intel_crtc
->pipe
;
416 /* Panel Enable over CRC PMIC */
417 if (intel_dsi
->gpio_panel
)
418 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
420 msleep(intel_dsi
->panel_on_delay
);
422 /* Disable DPOunit clock gating, can stall pipe
423 * and we need DPLL REFA always enabled */
424 tmp
= I915_READ(DPLL(pipe
));
425 tmp
|= DPLL_REF_CLK_ENABLE_VLV
;
426 I915_WRITE(DPLL(pipe
), tmp
);
428 /* update the hw state for DPLL */
429 intel_crtc
->config
->dpll_hw_state
.dpll
= DPLL_INTEGRATED_REF_CLK_VLV
|
430 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
432 tmp
= I915_READ(DSPCLK_GATE_D
);
433 tmp
|= DPOUNIT_CLOCK_GATE_DISABLE
;
434 I915_WRITE(DSPCLK_GATE_D
, tmp
);
436 /* put device in ready state */
437 intel_dsi_device_ready(encoder
);
439 drm_panel_prepare(intel_dsi
->panel
);
441 for_each_dsi_port(port
, intel_dsi
->ports
)
442 wait_for_dsi_fifo_empty(intel_dsi
, port
);
444 /* Enable port in pre-enable phase itself because as per hw team
445 * recommendation, port should be enabled befor plane & pipe */
446 intel_dsi_enable(encoder
);
449 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
453 /* for DSI port enable has to be done before pipe
454 * and plane enable, so port enable is done in
455 * pre_enable phase itself unlike other encoders
459 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
461 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
466 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
468 if (is_vid_mode(intel_dsi
)) {
469 /* Send Shutdown command to the panel in LP mode */
470 for_each_dsi_port(port
, intel_dsi
->ports
)
471 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
476 static void intel_dsi_disable(struct intel_encoder
*encoder
)
478 struct drm_device
*dev
= encoder
->base
.dev
;
479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
480 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
486 if (is_vid_mode(intel_dsi
)) {
487 for_each_dsi_port(port
, intel_dsi
->ports
)
488 wait_for_dsi_fifo_empty(intel_dsi
, port
);
490 intel_dsi_port_disable(encoder
);
494 for_each_dsi_port(port
, intel_dsi
->ports
) {
495 /* Panel commands can be sent when clock is in LP11 */
496 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
498 temp
= I915_READ(MIPI_CTRL(port
));
499 temp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
500 I915_WRITE(MIPI_CTRL(port
), temp
|
501 intel_dsi
->escape_clk_div
<<
502 ESCAPE_CLOCK_DIVIDER_SHIFT
);
504 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
506 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
507 temp
&= ~VID_MODE_FORMAT_MASK
;
508 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
510 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
512 /* if disable packets are sent before sending shutdown packet then in
513 * some next enable sequence send turn on packet error is observed */
514 drm_panel_disable(intel_dsi
->panel
);
516 for_each_dsi_port(port
, intel_dsi
->ports
)
517 wait_for_dsi_fifo_empty(intel_dsi
, port
);
520 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
522 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
523 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
528 for_each_dsi_port(port
, intel_dsi
->ports
) {
530 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
532 usleep_range(2000, 2500);
534 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
536 usleep_range(2000, 2500);
538 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
540 usleep_range(2000, 2500);
542 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
543 * only. MIPI Port C has no similar bit for checking
545 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A
)) & AFE_LATCHOUT
)
547 DRM_ERROR("DSI LP not going Low\n");
549 /* Disable MIPI PHY transparent latch
550 * Common bit for both MIPI Port A & MIPI Port C
552 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
553 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
& ~LP_OUTPUT_HOLD
);
554 usleep_range(1000, 1500);
556 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
557 usleep_range(2000, 2500);
560 vlv_disable_dsi_pll(encoder
);
563 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
565 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
566 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
571 intel_dsi_disable(encoder
);
573 intel_dsi_clear_device_ready(encoder
);
575 val
= I915_READ(DSPCLK_GATE_D
);
576 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
577 I915_WRITE(DSPCLK_GATE_D
, val
);
579 drm_panel_unprepare(intel_dsi
->panel
);
581 msleep(intel_dsi
->panel_off_delay
);
582 msleep(intel_dsi
->panel_pwr_cycle_delay
);
584 /* Panel Disable over CRC PMIC */
585 if (intel_dsi
->gpio_panel
)
586 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
589 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
592 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
593 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
594 struct drm_device
*dev
= encoder
->base
.dev
;
595 enum intel_display_power_domain power_domain
;
596 u32 dpi_enabled
, func
;
601 power_domain
= intel_display_port_power_domain(encoder
);
602 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
605 /* XXX: this only works for one DSI output */
606 for_each_dsi_port(port
, intel_dsi
->ports
) {
607 func
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
608 dpi_enabled
= I915_READ(MIPI_PORT_CTRL(port
)) &
611 /* Due to some hardware limitations on BYT, MIPI Port C DPI
612 * Enable bit does not get set. To check whether DSI Port C
613 * was enabled in BIOS, check the Pipe B enable bit
615 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
) &&
617 dpi_enabled
= I915_READ(PIPECONF(PIPE_B
)) &
620 if (dpi_enabled
|| (func
& CMD_MODE_DATA_WIDTH_MASK
)) {
621 if (I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
) {
622 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
631 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
632 struct intel_crtc_state
*pipe_config
)
638 * DPLL_MD is not used in case of DSI, reading will get some default value
641 pipe_config
->dpll_hw_state
.dpll_md
= 0;
643 pclk
= vlv_get_dsi_pclk(encoder
, pipe_config
->pipe_bpp
);
647 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
648 pipe_config
->port_clock
= pclk
;
651 static enum drm_mode_status
652 intel_dsi_mode_valid(struct drm_connector
*connector
,
653 struct drm_display_mode
*mode
)
655 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
656 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
660 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
661 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
662 return MODE_NO_DBLESCAN
;
666 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
668 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
675 /* return txclkesc cycles in terms of divider and duration in us */
676 static u16
txclkesc(u32 divider
, unsigned int us
)
679 case ESCAPE_CLOCK_DIVIDER_1
:
682 case ESCAPE_CLOCK_DIVIDER_2
:
684 case ESCAPE_CLOCK_DIVIDER_4
:
689 /* return pixels in terms of txbyteclkhs */
690 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
691 u16 burst_mode_ratio
)
693 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
694 8 * 100), lane_count
);
697 static void set_dsi_timings(struct drm_encoder
*encoder
,
698 const struct drm_display_mode
*mode
)
700 struct drm_device
*dev
= encoder
->dev
;
701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
702 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
703 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
705 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
706 unsigned int lane_count
= intel_dsi
->lane_count
;
708 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
710 hactive
= mode
->hdisplay
;
711 hfp
= mode
->hsync_start
- mode
->hdisplay
;
712 hsync
= mode
->hsync_end
- mode
->hsync_start
;
713 hbp
= mode
->htotal
- mode
->hsync_end
;
715 if (intel_dsi
->dual_link
) {
717 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
718 hactive
+= intel_dsi
->pixel_overlap
;
724 vfp
= mode
->vsync_start
- mode
->vdisplay
;
725 vsync
= mode
->vsync_end
- mode
->vsync_start
;
726 vbp
= mode
->vtotal
- mode
->vsync_end
;
728 /* horizontal values are in terms of high speed byte clock */
729 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
730 intel_dsi
->burst_mode_ratio
);
731 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
732 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
733 intel_dsi
->burst_mode_ratio
);
734 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
736 for_each_dsi_port(port
, intel_dsi
->ports
) {
737 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
738 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
740 /* meaningful for video mode non-burst sync pulse mode only,
741 * can be zero for non-burst sync events and burst modes */
742 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
743 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
745 /* vertical values are in terms of lines */
746 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
747 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
748 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
752 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
754 struct drm_encoder
*encoder
= &intel_encoder
->base
;
755 struct drm_device
*dev
= encoder
->dev
;
756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
757 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
758 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
759 struct drm_display_mode
*adjusted_mode
=
760 &intel_crtc
->config
->base
.adjusted_mode
;
762 unsigned int bpp
= intel_crtc
->config
->pipe_bpp
;
766 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
768 mode_hdisplay
= adjusted_mode
->hdisplay
;
770 if (intel_dsi
->dual_link
) {
772 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
773 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
776 for_each_dsi_port(port
, intel_dsi
->ports
) {
777 /* escape clock divider, 20MHz, shared for A and C.
778 * device ready must be off when doing this! txclkesc? */
779 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
780 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
781 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
| ESCAPE_CLOCK_DIVIDER_1
);
783 /* read request priority is per pipe */
784 tmp
= I915_READ(MIPI_CTRL(port
));
785 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
786 I915_WRITE(MIPI_CTRL(port
), tmp
| READ_REQUEST_PRIORITY_HIGH
);
788 /* XXX: why here, why like this? handling in irq handler?! */
789 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
790 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
792 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
794 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
795 adjusted_mode
->vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
796 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
799 set_dsi_timings(encoder
, adjusted_mode
);
801 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
802 if (is_cmd_mode(intel_dsi
)) {
803 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
804 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
806 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
808 /* XXX: cross-check bpp vs. pixel format? */
809 val
|= intel_dsi
->pixel_format
;
813 if (intel_dsi
->eotp_pkt
== 0)
815 if (intel_dsi
->clock_stop
)
818 for_each_dsi_port(port
, intel_dsi
->ports
) {
819 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
821 /* timeouts for recovery. one frame IIUC. if counter expires,
822 * EOT and stop state. */
825 * In burst mode, value greater than one DPI line Time in byte
826 * clock (txbyteclkhs) To timeout this timer 1+ of the above
827 * said value is recommended.
829 * In non-burst mode, Value greater than one DPI frame time in
830 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
831 * said value is recommended.
833 * In DBI only mode, value greater than one DBI frame time in
834 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
835 * said value is recommended.
838 if (is_vid_mode(intel_dsi
) &&
839 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
840 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
841 txbyteclkhs(adjusted_mode
->htotal
, bpp
,
842 intel_dsi
->lane_count
,
843 intel_dsi
->burst_mode_ratio
) + 1);
845 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
846 txbyteclkhs(adjusted_mode
->vtotal
*
847 adjusted_mode
->htotal
,
848 bpp
, intel_dsi
->lane_count
,
849 intel_dsi
->burst_mode_ratio
) + 1);
851 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
852 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
853 intel_dsi
->turn_arnd_val
);
854 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
855 intel_dsi
->rst_timer_val
);
859 /* in terms of low power clock */
860 I915_WRITE(MIPI_INIT_COUNT(port
),
861 txclkesc(intel_dsi
->escape_clk_div
, 100));
864 /* recovery disables */
865 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
867 /* in terms of low power clock */
868 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
870 /* in terms of txbyteclkhs. actual high to low switch +
871 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
873 * XXX: write MIPI_STOP_STATE_STALL?
875 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
876 intel_dsi
->hs_to_lp_count
);
878 /* XXX: low power clock equivalence in terms of byte clock.
879 * the number of byte clocks occupied in one low power clock.
880 * based on txbyteclkhs and txclkesc.
881 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
884 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
886 /* the bw essential for transmitting 16 long packets containing
887 * 252 bytes meant for dcs write memory command is programmed in
888 * this register in terms of byte clocks. based on dsi transfer
889 * rate and the number of lanes configured the time taken to
890 * transmit 16 long packets in a dsi stream varies. */
891 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
893 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
894 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
895 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
897 if (is_vid_mode(intel_dsi
))
898 /* Some panels might have resolution which is not a
899 * multiple of 64 like 1366 x 768. Enable RANDOM
900 * resolution support for such panels by default */
901 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
902 intel_dsi
->video_frmt_cfg_bits
|
903 intel_dsi
->video_mode_format
|
905 RANDOM_DPI_DISPLAY_RESOLUTION
);
909 static void intel_dsi_pre_pll_enable(struct intel_encoder
*encoder
)
913 intel_dsi_prepare(encoder
);
915 vlv_enable_dsi_pll(encoder
);
918 static enum drm_connector_status
919 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
921 return connector_status_connected
;
924 static int intel_dsi_get_modes(struct drm_connector
*connector
)
926 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
927 struct drm_display_mode
*mode
;
931 if (!intel_connector
->panel
.fixed_mode
) {
932 DRM_DEBUG_KMS("no fixed mode\n");
936 mode
= drm_mode_duplicate(connector
->dev
,
937 intel_connector
->panel
.fixed_mode
);
939 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
943 drm_mode_probed_add(connector
, mode
);
947 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
949 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
952 intel_panel_fini(&intel_connector
->panel
);
953 drm_connector_cleanup(connector
);
957 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
959 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
961 if (intel_dsi
->panel
) {
962 drm_panel_detach(intel_dsi
->panel
);
963 /* XXX: Logically this call belongs in the panel driver. */
964 drm_panel_remove(intel_dsi
->panel
);
967 /* dispose of the gpios */
968 if (intel_dsi
->gpio_panel
)
969 gpiod_put(intel_dsi
->gpio_panel
);
971 intel_encoder_destroy(encoder
);
974 static const struct drm_encoder_funcs intel_dsi_funcs
= {
975 .destroy
= intel_dsi_encoder_destroy
,
978 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
979 .get_modes
= intel_dsi_get_modes
,
980 .mode_valid
= intel_dsi_mode_valid
,
981 .best_encoder
= intel_best_encoder
,
984 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
985 .dpms
= drm_atomic_helper_connector_dpms
,
986 .detect
= intel_dsi_detect
,
987 .destroy
= intel_dsi_connector_destroy
,
988 .fill_modes
= drm_helper_probe_single_connector_modes
,
989 .atomic_get_property
= intel_connector_atomic_get_property
,
990 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
991 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
994 void intel_dsi_init(struct drm_device
*dev
)
996 struct intel_dsi
*intel_dsi
;
997 struct intel_encoder
*intel_encoder
;
998 struct drm_encoder
*encoder
;
999 struct intel_connector
*intel_connector
;
1000 struct drm_connector
*connector
;
1001 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1006 DRM_DEBUG_KMS("\n");
1008 /* There is no detection method for MIPI so rely on VBT */
1009 if (!dev_priv
->vbt
.has_mipi
)
1012 if (IS_VALLEYVIEW(dev
)) {
1013 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1015 DRM_ERROR("Unsupported Mipi device to reg base");
1019 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1023 intel_connector
= intel_connector_alloc();
1024 if (!intel_connector
) {
1029 intel_encoder
= &intel_dsi
->base
;
1030 encoder
= &intel_encoder
->base
;
1031 intel_dsi
->attached_connector
= intel_connector
;
1033 connector
= &intel_connector
->base
;
1035 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
);
1037 /* XXX: very likely not all of these are needed */
1038 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1039 intel_encoder
->pre_pll_enable
= intel_dsi_pre_pll_enable
;
1040 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1041 intel_encoder
->enable
= intel_dsi_enable_nop
;
1042 intel_encoder
->disable
= intel_dsi_pre_disable
;
1043 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1044 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1045 intel_encoder
->get_config
= intel_dsi_get_config
;
1047 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1048 intel_connector
->unregister
= intel_connector_unregister
;
1050 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1051 if (dev_priv
->vbt
.dsi
.config
->dual_link
) {
1052 /* XXX: does dual link work on either pipe? */
1053 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1054 intel_dsi
->ports
= ((1 << PORT_A
) | (1 << PORT_C
));
1055 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIA
) {
1056 intel_encoder
->crtc_mask
= (1 << PIPE_A
);
1057 intel_dsi
->ports
= (1 << PORT_A
);
1058 } else if (dev_priv
->vbt
.dsi
.port
== DVO_PORT_MIPIC
) {
1059 intel_encoder
->crtc_mask
= (1 << PIPE_B
);
1060 intel_dsi
->ports
= (1 << PORT_C
);
1063 /* Create a DSI host (and a device) for each port. */
1064 for_each_dsi_port(port
, intel_dsi
->ports
) {
1065 struct intel_dsi_host
*host
;
1067 host
= intel_dsi_host_init(intel_dsi
, port
);
1071 intel_dsi
->dsi_hosts
[port
] = host
;
1074 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1075 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1076 intel_dsi_drivers
[i
].panel_id
);
1077 if (intel_dsi
->panel
)
1081 if (!intel_dsi
->panel
) {
1082 DRM_DEBUG_KMS("no device found\n");
1087 * In case of BYT with CRC PMIC, we need to use GPIO for
1090 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1091 intel_dsi
->gpio_panel
=
1092 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1094 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1095 DRM_ERROR("Failed to own gpio for panel control\n");
1096 intel_dsi
->gpio_panel
= NULL
;
1100 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1101 intel_encoder
->cloneable
= 0;
1102 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1103 DRM_MODE_CONNECTOR_DSI
);
1105 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1107 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1108 connector
->interlace_allowed
= false;
1109 connector
->doublescan_allowed
= false;
1111 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1113 drm_connector_register(connector
);
1115 drm_panel_attach(intel_dsi
->panel
, connector
);
1117 mutex_lock(&dev
->mode_config
.mutex
);
1118 drm_panel_get_modes(intel_dsi
->panel
);
1119 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1120 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1121 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1125 mutex_unlock(&dev
->mode_config
.mutex
);
1128 DRM_DEBUG_KMS("no fixed mode\n");
1132 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1133 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1138 drm_encoder_cleanup(&intel_encoder
->base
);
1140 kfree(intel_connector
);