2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Jani Nikula <jani.nikula@intel.com>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_mipi_dsi.h>
33 #include <linux/slab.h>
34 #include <linux/gpio/consumer.h>
36 #include "intel_drv.h"
37 #include "intel_dsi.h"
41 struct drm_panel
* (*init
)(struct intel_dsi
*intel_dsi
, u16 panel_id
);
42 } intel_dsi_drivers
[] = {
44 .panel_id
= MIPI_DSI_GENERIC_PANEL_ID
,
45 .init
= vbt_panel_init
,
49 enum mipi_dsi_pixel_format
pixel_format_from_register_bits(u32 fmt
)
51 /* It just so happens the VBT matches register contents. */
53 case VID_MODE_FORMAT_RGB888
:
54 return MIPI_DSI_FMT_RGB888
;
55 case VID_MODE_FORMAT_RGB666
:
56 return MIPI_DSI_FMT_RGB666
;
57 case VID_MODE_FORMAT_RGB666_PACKED
:
58 return MIPI_DSI_FMT_RGB666_PACKED
;
59 case VID_MODE_FORMAT_RGB565
:
60 return MIPI_DSI_FMT_RGB565
;
63 return MIPI_DSI_FMT_RGB666
;
67 static void wait_for_dsi_fifo_empty(struct intel_dsi
*intel_dsi
, enum port port
)
69 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
70 struct drm_device
*dev
= encoder
->dev
;
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 mask
= LP_CTRL_FIFO_EMPTY
| HS_CTRL_FIFO_EMPTY
|
75 LP_DATA_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
;
77 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & mask
) == mask
, 100))
78 DRM_ERROR("DPI FIFOs are not empty\n");
81 static void write_data(struct drm_i915_private
*dev_priv
,
83 const u8
*data
, u32 len
)
87 for (i
= 0; i
< len
; i
+= 4) {
90 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
91 val
|= *data
++ << 8 * j
;
97 static void read_data(struct drm_i915_private
*dev_priv
,
103 for (i
= 0; i
< len
; i
+= 4) {
104 u32 val
= I915_READ(reg
);
106 for (j
= 0; j
< min_t(u32
, len
- i
, 4); j
++)
107 *data
++ = val
>> 8 * j
;
111 static ssize_t
intel_dsi_host_transfer(struct mipi_dsi_host
*host
,
112 const struct mipi_dsi_msg
*msg
)
114 struct intel_dsi_host
*intel_dsi_host
= to_intel_dsi_host(host
);
115 struct drm_device
*dev
= intel_dsi_host
->intel_dsi
->base
.base
.dev
;
116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 enum port port
= intel_dsi_host
->port
;
118 struct mipi_dsi_packet packet
;
120 const u8
*header
, *data
;
121 i915_reg_t data_reg
, ctrl_reg
;
122 u32 data_mask
, ctrl_mask
;
124 ret
= mipi_dsi_create_packet(&packet
, msg
);
128 header
= packet
.header
;
129 data
= packet
.payload
;
131 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
) {
132 data_reg
= MIPI_LP_GEN_DATA(port
);
133 data_mask
= LP_DATA_FIFO_FULL
;
134 ctrl_reg
= MIPI_LP_GEN_CTRL(port
);
135 ctrl_mask
= LP_CTRL_FIFO_FULL
;
137 data_reg
= MIPI_HS_GEN_DATA(port
);
138 data_mask
= HS_DATA_FIFO_FULL
;
139 ctrl_reg
= MIPI_HS_GEN_CTRL(port
);
140 ctrl_mask
= HS_CTRL_FIFO_FULL
;
143 /* note: this is never true for reads */
144 if (packet
.payload_length
) {
146 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & data_mask
) == 0, 50))
147 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
149 write_data(dev_priv
, data_reg
, packet
.payload
,
150 packet
.payload_length
);
154 I915_WRITE(MIPI_INTR_STAT(port
), GEN_READ_DATA_AVAIL
);
157 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port
)) & ctrl_mask
) == 0, 50)) {
158 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
161 I915_WRITE(ctrl_reg
, header
[2] << 16 | header
[1] << 8 | header
[0]);
163 /* ->rx_len is set only for reads */
165 data_mask
= GEN_READ_DATA_AVAIL
;
166 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & data_mask
) == data_mask
, 50))
167 DRM_ERROR("Timeout waiting for read data.\n");
169 read_data(dev_priv
, data_reg
, msg
->rx_buf
, msg
->rx_len
);
172 /* XXX: fix for reads and writes */
173 return 4 + packet
.payload_length
;
176 static int intel_dsi_host_attach(struct mipi_dsi_host
*host
,
177 struct mipi_dsi_device
*dsi
)
182 static int intel_dsi_host_detach(struct mipi_dsi_host
*host
,
183 struct mipi_dsi_device
*dsi
)
188 static const struct mipi_dsi_host_ops intel_dsi_host_ops
= {
189 .attach
= intel_dsi_host_attach
,
190 .detach
= intel_dsi_host_detach
,
191 .transfer
= intel_dsi_host_transfer
,
194 static struct intel_dsi_host
*intel_dsi_host_init(struct intel_dsi
*intel_dsi
,
197 struct intel_dsi_host
*host
;
198 struct mipi_dsi_device
*device
;
200 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
204 host
->base
.ops
= &intel_dsi_host_ops
;
205 host
->intel_dsi
= intel_dsi
;
209 * We should call mipi_dsi_host_register(&host->base) here, but we don't
210 * have a host->dev, and we don't have OF stuff either. So just use the
211 * dsi framework as a library and hope for the best. Create the dsi
212 * devices by ourselves here too. Need to be careful though, because we
213 * don't initialize any of the driver model devices here.
215 device
= kzalloc(sizeof(*device
), GFP_KERNEL
);
221 device
->host
= &host
->base
;
222 host
->device
= device
;
228 * send a video mode command
230 * XXX: commands with data in MIPI_DPI_DATA?
232 static int dpi_send_cmd(struct intel_dsi
*intel_dsi
, u32 cmd
, bool hs
,
235 struct drm_encoder
*encoder
= &intel_dsi
->base
.base
;
236 struct drm_device
*dev
= encoder
->dev
;
237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 I915_WRITE(MIPI_INTR_STAT(port
), SPL_PKT_SENT_INTERRUPT
);
249 /* XXX: old code skips write if control unchanged */
250 if (cmd
== I915_READ(MIPI_DPI_CONTROL(port
)))
251 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd
);
253 I915_WRITE(MIPI_DPI_CONTROL(port
), cmd
);
255 mask
= SPL_PKT_SENT_INTERRUPT
;
256 if (wait_for((I915_READ(MIPI_INTR_STAT(port
)) & mask
) == mask
, 100))
257 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd
);
262 static void band_gap_reset(struct drm_i915_private
*dev_priv
)
264 mutex_lock(&dev_priv
->sb_lock
);
266 vlv_flisdsi_write(dev_priv
, 0x08, 0x0001);
267 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0005);
268 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0025);
270 vlv_flisdsi_write(dev_priv
, 0x0F, 0x0000);
271 vlv_flisdsi_write(dev_priv
, 0x08, 0x0000);
273 mutex_unlock(&dev_priv
->sb_lock
);
276 static inline bool is_vid_mode(struct intel_dsi
*intel_dsi
)
278 return intel_dsi
->operation_mode
== INTEL_DSI_VIDEO_MODE
;
281 static inline bool is_cmd_mode(struct intel_dsi
*intel_dsi
)
283 return intel_dsi
->operation_mode
== INTEL_DSI_COMMAND_MODE
;
286 static bool intel_dsi_compute_config(struct intel_encoder
*encoder
,
287 struct intel_crtc_state
*pipe_config
)
289 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
290 struct intel_dsi
*intel_dsi
= container_of(encoder
, struct intel_dsi
,
292 struct intel_connector
*intel_connector
= intel_dsi
->attached_connector
;
293 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
294 const struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
295 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
300 pipe_config
->has_dsi_encoder
= true;
303 intel_fixed_panel_mode(fixed_mode
, adjusted_mode
);
305 if (HAS_GMCH_DISPLAY(dev_priv
))
306 intel_gmch_panel_fitting(crtc
, pipe_config
,
307 intel_connector
->panel
.fitting_mode
);
309 intel_pch_panel_fitting(crtc
, pipe_config
,
310 intel_connector
->panel
.fitting_mode
);
313 /* DSI uses short packets for sync events, so clear mode flags for DSI */
314 adjusted_mode
->flags
= 0;
316 if (IS_BROXTON(dev_priv
)) {
317 /* Dual link goes to DSI transcoder A. */
318 if (intel_dsi
->ports
== BIT(PORT_C
))
319 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_C
;
321 pipe_config
->cpu_transcoder
= TRANSCODER_DSI_A
;
324 ret
= intel_compute_dsi_pll(encoder
, pipe_config
);
328 pipe_config
->clock_set
= true;
333 static void bxt_dsi_device_ready(struct intel_encoder
*encoder
)
335 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
336 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
342 /* Exit Low power state in 4 steps*/
343 for_each_dsi_port(port
, intel_dsi
->ports
) {
345 /* 1. Enable MIPI PHY transparent latch */
346 val
= I915_READ(BXT_MIPI_PORT_CTRL(port
));
347 I915_WRITE(BXT_MIPI_PORT_CTRL(port
), val
| LP_OUTPUT_HOLD
);
348 usleep_range(2000, 2500);
351 val
= I915_READ(MIPI_DEVICE_READY(port
));
352 val
&= ~ULPS_STATE_MASK
;
353 val
|= (ULPS_STATE_ENTER
| DEVICE_READY
);
354 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
358 val
= I915_READ(MIPI_DEVICE_READY(port
));
359 val
&= ~ULPS_STATE_MASK
;
360 val
|= (ULPS_STATE_EXIT
| DEVICE_READY
);
361 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
362 usleep_range(1000, 1500);
364 /* Clear ULPS and set device ready */
365 val
= I915_READ(MIPI_DEVICE_READY(port
));
366 val
&= ~ULPS_STATE_MASK
;
368 I915_WRITE(MIPI_DEVICE_READY(port
), val
);
372 static void vlv_dsi_device_ready(struct intel_encoder
*encoder
)
374 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
375 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
381 mutex_lock(&dev_priv
->sb_lock
);
382 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
383 * needed everytime after power gate */
384 vlv_flisdsi_write(dev_priv
, 0x04, 0x0004);
385 mutex_unlock(&dev_priv
->sb_lock
);
387 /* bandgap reset is needed after everytime we do power gate */
388 band_gap_reset(dev_priv
);
390 for_each_dsi_port(port
, intel_dsi
->ports
) {
392 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_ENTER
);
393 usleep_range(2500, 3000);
395 /* Enable MIPI PHY transparent latch
396 * Common bit for both MIPI Port A & MIPI Port C
397 * No similar bit in MIPI Port C reg
399 val
= I915_READ(MIPI_PORT_CTRL(PORT_A
));
400 I915_WRITE(MIPI_PORT_CTRL(PORT_A
), val
| LP_OUTPUT_HOLD
);
401 usleep_range(1000, 1500);
403 I915_WRITE(MIPI_DEVICE_READY(port
), ULPS_STATE_EXIT
);
404 usleep_range(2500, 3000);
406 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
);
407 usleep_range(2500, 3000);
411 static void intel_dsi_device_ready(struct intel_encoder
*encoder
)
413 struct drm_device
*dev
= encoder
->base
.dev
;
415 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
416 vlv_dsi_device_ready(encoder
);
417 else if (IS_BROXTON(dev
))
418 bxt_dsi_device_ready(encoder
);
421 static void intel_dsi_port_enable(struct intel_encoder
*encoder
)
423 struct drm_device
*dev
= encoder
->base
.dev
;
424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
425 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
426 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
429 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
) {
432 temp
= I915_READ(VLV_CHICKEN_3
);
433 temp
&= ~PIXEL_OVERLAP_CNT_MASK
|
434 intel_dsi
->pixel_overlap
<<
435 PIXEL_OVERLAP_CNT_SHIFT
;
436 I915_WRITE(VLV_CHICKEN_3
, temp
);
439 for_each_dsi_port(port
, intel_dsi
->ports
) {
440 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
441 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
444 temp
= I915_READ(port_ctrl
);
446 temp
&= ~LANE_CONFIGURATION_MASK
;
447 temp
&= ~DUAL_LINK_MODE_MASK
;
449 if (intel_dsi
->ports
== (BIT(PORT_A
) | BIT(PORT_C
))) {
450 temp
|= (intel_dsi
->dual_link
- 1)
451 << DUAL_LINK_MODE_SHIFT
;
452 temp
|= intel_crtc
->pipe
?
453 LANE_CONFIGURATION_DUAL_LINK_B
:
454 LANE_CONFIGURATION_DUAL_LINK_A
;
456 /* assert ip_tg_enable signal */
457 I915_WRITE(port_ctrl
, temp
| DPI_ENABLE
);
458 POSTING_READ(port_ctrl
);
462 static void intel_dsi_port_disable(struct intel_encoder
*encoder
)
464 struct drm_device
*dev
= encoder
->base
.dev
;
465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
466 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
469 for_each_dsi_port(port
, intel_dsi
->ports
) {
470 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
471 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
474 /* de-assert ip_tg_enable signal */
475 temp
= I915_READ(port_ctrl
);
476 I915_WRITE(port_ctrl
, temp
& ~DPI_ENABLE
);
477 POSTING_READ(port_ctrl
);
481 static void intel_dsi_enable(struct intel_encoder
*encoder
)
483 struct drm_device
*dev
= encoder
->base
.dev
;
484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
485 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
490 if (is_cmd_mode(intel_dsi
)) {
491 for_each_dsi_port(port
, intel_dsi
->ports
)
492 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port
), 8 * 4);
494 msleep(20); /* XXX */
495 for_each_dsi_port(port
, intel_dsi
->ports
)
496 dpi_send_cmd(intel_dsi
, TURN_ON
, false, port
);
499 drm_panel_enable(intel_dsi
->panel
);
501 for_each_dsi_port(port
, intel_dsi
->ports
)
502 wait_for_dsi_fifo_empty(intel_dsi
, port
);
504 intel_dsi_port_enable(encoder
);
507 intel_panel_enable_backlight(intel_dsi
->attached_connector
);
510 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
);
512 static void intel_dsi_pre_enable(struct intel_encoder
*encoder
)
514 struct drm_device
*dev
= encoder
->base
.dev
;
515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
516 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
517 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
523 * The BIOS may leave the PLL in a wonky state where it doesn't
524 * lock. It needs to be fully powered down to fix it.
526 intel_disable_dsi_pll(encoder
);
527 intel_enable_dsi_pll(encoder
, crtc
->config
);
529 intel_dsi_prepare(encoder
);
531 /* Panel Enable over CRC PMIC */
532 if (intel_dsi
->gpio_panel
)
533 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 1);
535 msleep(intel_dsi
->panel_on_delay
);
537 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
540 /* Disable DPOunit clock gating, can stall pipe */
541 val
= I915_READ(DSPCLK_GATE_D
);
542 val
|= DPOUNIT_CLOCK_GATE_DISABLE
;
543 I915_WRITE(DSPCLK_GATE_D
, val
);
546 /* put device in ready state */
547 intel_dsi_device_ready(encoder
);
549 drm_panel_prepare(intel_dsi
->panel
);
551 for_each_dsi_port(port
, intel_dsi
->ports
)
552 wait_for_dsi_fifo_empty(intel_dsi
, port
);
554 /* Enable port in pre-enable phase itself because as per hw team
555 * recommendation, port should be enabled befor plane & pipe */
556 intel_dsi_enable(encoder
);
559 static void intel_dsi_enable_nop(struct intel_encoder
*encoder
)
563 /* for DSI port enable has to be done before pipe
564 * and plane enable, so port enable is done in
565 * pre_enable phase itself unlike other encoders
569 static void intel_dsi_pre_disable(struct intel_encoder
*encoder
)
571 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
576 intel_panel_disable_backlight(intel_dsi
->attached_connector
);
578 if (is_vid_mode(intel_dsi
)) {
579 /* Send Shutdown command to the panel in LP mode */
580 for_each_dsi_port(port
, intel_dsi
->ports
)
581 dpi_send_cmd(intel_dsi
, SHUTDOWN
, false, port
);
586 static void intel_dsi_disable(struct intel_encoder
*encoder
)
588 struct drm_device
*dev
= encoder
->base
.dev
;
589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
590 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
596 if (is_vid_mode(intel_dsi
)) {
597 for_each_dsi_port(port
, intel_dsi
->ports
)
598 wait_for_dsi_fifo_empty(intel_dsi
, port
);
600 intel_dsi_port_disable(encoder
);
604 for_each_dsi_port(port
, intel_dsi
->ports
) {
605 /* Panel commands can be sent when clock is in LP11 */
606 I915_WRITE(MIPI_DEVICE_READY(port
), 0x0);
608 intel_dsi_reset_clocks(encoder
, port
);
609 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
611 temp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
612 temp
&= ~VID_MODE_FORMAT_MASK
;
613 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), temp
);
615 I915_WRITE(MIPI_DEVICE_READY(port
), 0x1);
617 /* if disable packets are sent before sending shutdown packet then in
618 * some next enable sequence send turn on packet error is observed */
619 drm_panel_disable(intel_dsi
->panel
);
621 for_each_dsi_port(port
, intel_dsi
->ports
)
622 wait_for_dsi_fifo_empty(intel_dsi
, port
);
625 static void intel_dsi_clear_device_ready(struct intel_encoder
*encoder
)
627 struct drm_device
*dev
= encoder
->base
.dev
;
628 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
629 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
633 for_each_dsi_port(port
, intel_dsi
->ports
) {
634 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
635 i915_reg_t port_ctrl
= IS_BROXTON(dev
) ?
636 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(PORT_A
);
639 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
641 usleep_range(2000, 2500);
643 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
645 usleep_range(2000, 2500);
647 I915_WRITE(MIPI_DEVICE_READY(port
), DEVICE_READY
|
649 usleep_range(2000, 2500);
651 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
652 * only. MIPI Port C has no similar bit for checking
654 if (wait_for(((I915_READ(port_ctrl
) & AFE_LATCHOUT
)
656 DRM_ERROR("DSI LP not going Low\n");
658 /* Disable MIPI PHY transparent latch */
659 val
= I915_READ(port_ctrl
);
660 I915_WRITE(port_ctrl
, val
& ~LP_OUTPUT_HOLD
);
661 usleep_range(1000, 1500);
663 I915_WRITE(MIPI_DEVICE_READY(port
), 0x00);
664 usleep_range(2000, 2500);
667 intel_disable_dsi_pll(encoder
);
670 static void intel_dsi_post_disable(struct intel_encoder
*encoder
)
672 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
673 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
677 intel_dsi_disable(encoder
);
679 intel_dsi_clear_device_ready(encoder
);
681 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
684 val
= I915_READ(DSPCLK_GATE_D
);
685 val
&= ~DPOUNIT_CLOCK_GATE_DISABLE
;
686 I915_WRITE(DSPCLK_GATE_D
, val
);
689 drm_panel_unprepare(intel_dsi
->panel
);
691 msleep(intel_dsi
->panel_off_delay
);
693 /* Panel Disable over CRC PMIC */
694 if (intel_dsi
->gpio_panel
)
695 gpiod_set_value_cansleep(intel_dsi
->gpio_panel
, 0);
698 * FIXME As we do with eDP, just make a note of the time here
699 * and perform the wait before the next panel power on.
701 msleep(intel_dsi
->panel_pwr_cycle_delay
);
704 static bool intel_dsi_get_hw_state(struct intel_encoder
*encoder
,
707 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
708 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
709 struct drm_device
*dev
= encoder
->base
.dev
;
710 enum intel_display_power_domain power_domain
;
716 power_domain
= intel_display_port_power_domain(encoder
);
717 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
721 * On Broxton the PLL needs to be enabled with a valid divider
722 * configuration, otherwise accessing DSI registers will hang the
723 * machine. See BSpec North Display Engine registers/MIPI[BXT].
725 if (IS_BROXTON(dev_priv
) && !intel_dsi_pll_is_enabled(dev_priv
))
728 /* XXX: this only works for one DSI output */
729 for_each_dsi_port(port
, intel_dsi
->ports
) {
730 i915_reg_t ctrl_reg
= IS_BROXTON(dev
) ?
731 BXT_MIPI_PORT_CTRL(port
) : MIPI_PORT_CTRL(port
);
732 bool enabled
= I915_READ(ctrl_reg
) & DPI_ENABLE
;
735 * Due to some hardware limitations on VLV/CHV, the DPI enable
736 * bit in port C control register does not get set. As a
737 * workaround, check pipe B conf instead.
739 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) && port
== PORT_C
)
740 enabled
= I915_READ(PIPECONF(PIPE_B
)) & PIPECONF_ENABLE
;
742 /* Try command mode if video mode not enabled */
744 u32 tmp
= I915_READ(MIPI_DSI_FUNC_PRG(port
));
745 enabled
= tmp
& CMD_MODE_DATA_WIDTH_MASK
;
751 if (!(I915_READ(MIPI_DEVICE_READY(port
)) & DEVICE_READY
))
754 if (IS_BROXTON(dev_priv
)) {
755 u32 tmp
= I915_READ(MIPI_CTRL(port
));
756 tmp
&= BXT_PIPE_SELECT_MASK
;
757 tmp
>>= BXT_PIPE_SELECT_SHIFT
;
759 if (WARN_ON(tmp
> PIPE_C
))
764 *pipe
= port
== PORT_A
? PIPE_A
: PIPE_B
;
772 intel_display_power_put(dev_priv
, power_domain
);
777 static void bxt_dsi_get_pipe_config(struct intel_encoder
*encoder
,
778 struct intel_crtc_state
*pipe_config
)
780 struct drm_device
*dev
= encoder
->base
.dev
;
781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
782 struct drm_display_mode
*adjusted_mode
=
783 &pipe_config
->base
.adjusted_mode
;
784 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
785 unsigned int bpp
, fmt
;
790 * Atleast one port is active as encoder->get_config called only if
791 * encoder->get_hw_state() returns true.
793 for_each_dsi_port(port
, intel_dsi
->ports
) {
794 if (I915_READ(BXT_MIPI_PORT_CTRL(port
)) & DPI_ENABLE
)
798 fmt
= I915_READ(MIPI_DSI_FUNC_PRG(port
)) & VID_MODE_FORMAT_MASK
;
799 pipe_config
->pipe_bpp
=
800 mipi_dsi_pixel_format_to_bpp(
801 pixel_format_from_register_bits(fmt
));
802 bpp
= pipe_config
->pipe_bpp
;
804 /* In terms of pixels */
805 adjusted_mode
->crtc_hdisplay
=
806 I915_READ(BXT_MIPI_TRANS_HACTIVE(port
));
807 adjusted_mode
->crtc_vdisplay
=
808 I915_READ(BXT_MIPI_TRANS_VACTIVE(port
));
809 adjusted_mode
->crtc_vtotal
=
810 I915_READ(BXT_MIPI_TRANS_VTOTAL(port
));
813 * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and
814 * calculate hsync_start, hsync_end, htotal and hblank_end
817 /* vertical values are in terms of lines */
818 vfp
= I915_READ(MIPI_VFP_COUNT(port
));
819 vsync
= I915_READ(MIPI_VSYNC_PADDING_COUNT(port
));
820 vbp
= I915_READ(MIPI_VBP_COUNT(port
));
822 adjusted_mode
->crtc_hblank_start
= adjusted_mode
->crtc_hdisplay
;
824 adjusted_mode
->crtc_vsync_start
=
825 vfp
+ adjusted_mode
->crtc_vdisplay
;
826 adjusted_mode
->crtc_vsync_end
=
827 vsync
+ adjusted_mode
->crtc_vsync_start
;
828 adjusted_mode
->crtc_vblank_start
= adjusted_mode
->crtc_vdisplay
;
829 adjusted_mode
->crtc_vblank_end
= adjusted_mode
->crtc_vtotal
;
833 static void intel_dsi_get_config(struct intel_encoder
*encoder
,
834 struct intel_crtc_state
*pipe_config
)
836 struct drm_device
*dev
= encoder
->base
.dev
;
840 pipe_config
->has_dsi_encoder
= true;
843 bxt_dsi_get_pipe_config(encoder
, pipe_config
);
845 pclk
= intel_dsi_get_pclk(encoder
, pipe_config
->pipe_bpp
,
850 pipe_config
->base
.adjusted_mode
.crtc_clock
= pclk
;
851 pipe_config
->port_clock
= pclk
;
854 static enum drm_mode_status
855 intel_dsi_mode_valid(struct drm_connector
*connector
,
856 struct drm_display_mode
*mode
)
858 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
859 const struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
860 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
864 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
865 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
866 return MODE_NO_DBLESCAN
;
870 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
872 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
874 if (fixed_mode
->clock
> max_dotclk
)
875 return MODE_CLOCK_HIGH
;
881 /* return txclkesc cycles in terms of divider and duration in us */
882 static u16
txclkesc(u32 divider
, unsigned int us
)
885 case ESCAPE_CLOCK_DIVIDER_1
:
888 case ESCAPE_CLOCK_DIVIDER_2
:
890 case ESCAPE_CLOCK_DIVIDER_4
:
895 /* return pixels in terms of txbyteclkhs */
896 static u16
txbyteclkhs(u16 pixels
, int bpp
, int lane_count
,
897 u16 burst_mode_ratio
)
899 return DIV_ROUND_UP(DIV_ROUND_UP(pixels
* bpp
* burst_mode_ratio
,
900 8 * 100), lane_count
);
903 static void set_dsi_timings(struct drm_encoder
*encoder
,
904 const struct drm_display_mode
*adjusted_mode
)
906 struct drm_device
*dev
= encoder
->dev
;
907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
908 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
910 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
911 unsigned int lane_count
= intel_dsi
->lane_count
;
913 u16 hactive
, hfp
, hsync
, hbp
, vfp
, vsync
, vbp
;
915 hactive
= adjusted_mode
->crtc_hdisplay
;
916 hfp
= adjusted_mode
->crtc_hsync_start
- adjusted_mode
->crtc_hdisplay
;
917 hsync
= adjusted_mode
->crtc_hsync_end
- adjusted_mode
->crtc_hsync_start
;
918 hbp
= adjusted_mode
->crtc_htotal
- adjusted_mode
->crtc_hsync_end
;
920 if (intel_dsi
->dual_link
) {
922 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
923 hactive
+= intel_dsi
->pixel_overlap
;
929 vfp
= adjusted_mode
->crtc_vsync_start
- adjusted_mode
->crtc_vdisplay
;
930 vsync
= adjusted_mode
->crtc_vsync_end
- adjusted_mode
->crtc_vsync_start
;
931 vbp
= adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vsync_end
;
933 /* horizontal values are in terms of high speed byte clock */
934 hactive
= txbyteclkhs(hactive
, bpp
, lane_count
,
935 intel_dsi
->burst_mode_ratio
);
936 hfp
= txbyteclkhs(hfp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
937 hsync
= txbyteclkhs(hsync
, bpp
, lane_count
,
938 intel_dsi
->burst_mode_ratio
);
939 hbp
= txbyteclkhs(hbp
, bpp
, lane_count
, intel_dsi
->burst_mode_ratio
);
941 for_each_dsi_port(port
, intel_dsi
->ports
) {
942 if (IS_BROXTON(dev
)) {
944 * Program hdisplay and vdisplay on MIPI transcoder.
945 * This is different from calculated hactive and
946 * vactive, as they are calculated per channel basis,
947 * whereas these values should be based on resolution.
949 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port
),
950 adjusted_mode
->crtc_hdisplay
);
951 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port
),
952 adjusted_mode
->crtc_vdisplay
);
953 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port
),
954 adjusted_mode
->crtc_vtotal
);
957 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port
), hactive
);
958 I915_WRITE(MIPI_HFP_COUNT(port
), hfp
);
960 /* meaningful for video mode non-burst sync pulse mode only,
961 * can be zero for non-burst sync events and burst modes */
962 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port
), hsync
);
963 I915_WRITE(MIPI_HBP_COUNT(port
), hbp
);
965 /* vertical values are in terms of lines */
966 I915_WRITE(MIPI_VFP_COUNT(port
), vfp
);
967 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port
), vsync
);
968 I915_WRITE(MIPI_VBP_COUNT(port
), vbp
);
972 static u32
pixel_format_to_reg(enum mipi_dsi_pixel_format fmt
)
975 case MIPI_DSI_FMT_RGB888
:
976 return VID_MODE_FORMAT_RGB888
;
977 case MIPI_DSI_FMT_RGB666
:
978 return VID_MODE_FORMAT_RGB666
;
979 case MIPI_DSI_FMT_RGB666_PACKED
:
980 return VID_MODE_FORMAT_RGB666_PACKED
;
981 case MIPI_DSI_FMT_RGB565
:
982 return VID_MODE_FORMAT_RGB565
;
985 return VID_MODE_FORMAT_RGB666
;
989 static void intel_dsi_prepare(struct intel_encoder
*intel_encoder
)
991 struct drm_encoder
*encoder
= &intel_encoder
->base
;
992 struct drm_device
*dev
= encoder
->dev
;
993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
995 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
996 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
998 unsigned int bpp
= mipi_dsi_pixel_format_to_bpp(intel_dsi
->pixel_format
);
1002 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc
->pipe
));
1004 mode_hdisplay
= adjusted_mode
->crtc_hdisplay
;
1006 if (intel_dsi
->dual_link
) {
1008 if (intel_dsi
->dual_link
== DSI_DUAL_LINK_FRONT_BACK
)
1009 mode_hdisplay
+= intel_dsi
->pixel_overlap
;
1012 for_each_dsi_port(port
, intel_dsi
->ports
) {
1013 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1015 * escape clock divider, 20MHz, shared for A and C.
1016 * device ready must be off when doing this! txclkesc?
1018 tmp
= I915_READ(MIPI_CTRL(PORT_A
));
1019 tmp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
1020 I915_WRITE(MIPI_CTRL(PORT_A
), tmp
|
1021 ESCAPE_CLOCK_DIVIDER_1
);
1023 /* read request priority is per pipe */
1024 tmp
= I915_READ(MIPI_CTRL(port
));
1025 tmp
&= ~READ_REQUEST_PRIORITY_MASK
;
1026 I915_WRITE(MIPI_CTRL(port
), tmp
|
1027 READ_REQUEST_PRIORITY_HIGH
);
1028 } else if (IS_BROXTON(dev
)) {
1029 enum pipe pipe
= intel_crtc
->pipe
;
1031 tmp
= I915_READ(MIPI_CTRL(port
));
1032 tmp
&= ~BXT_PIPE_SELECT_MASK
;
1034 tmp
|= BXT_PIPE_SELECT(pipe
);
1035 I915_WRITE(MIPI_CTRL(port
), tmp
);
1038 /* XXX: why here, why like this? handling in irq handler?! */
1039 I915_WRITE(MIPI_INTR_STAT(port
), 0xffffffff);
1040 I915_WRITE(MIPI_INTR_EN(port
), 0xffffffff);
1042 I915_WRITE(MIPI_DPHY_PARAM(port
), intel_dsi
->dphy_reg
);
1044 I915_WRITE(MIPI_DPI_RESOLUTION(port
),
1045 adjusted_mode
->crtc_vdisplay
<< VERTICAL_ADDRESS_SHIFT
|
1046 mode_hdisplay
<< HORIZONTAL_ADDRESS_SHIFT
);
1049 set_dsi_timings(encoder
, adjusted_mode
);
1051 val
= intel_dsi
->lane_count
<< DATA_LANES_PRG_REG_SHIFT
;
1052 if (is_cmd_mode(intel_dsi
)) {
1053 val
|= intel_dsi
->channel
<< CMD_MODE_CHANNEL_NUMBER_SHIFT
;
1054 val
|= CMD_MODE_DATA_WIDTH_8_BIT
; /* XXX */
1056 val
|= intel_dsi
->channel
<< VID_MODE_CHANNEL_NUMBER_SHIFT
;
1057 val
|= pixel_format_to_reg(intel_dsi
->pixel_format
);
1061 if (intel_dsi
->eotp_pkt
== 0)
1063 if (intel_dsi
->clock_stop
)
1066 for_each_dsi_port(port
, intel_dsi
->ports
) {
1067 I915_WRITE(MIPI_DSI_FUNC_PRG(port
), val
);
1069 /* timeouts for recovery. one frame IIUC. if counter expires,
1070 * EOT and stop state. */
1073 * In burst mode, value greater than one DPI line Time in byte
1074 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1075 * said value is recommended.
1077 * In non-burst mode, Value greater than one DPI frame time in
1078 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1079 * said value is recommended.
1081 * In DBI only mode, value greater than one DBI frame time in
1082 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1083 * said value is recommended.
1086 if (is_vid_mode(intel_dsi
) &&
1087 intel_dsi
->video_mode_format
== VIDEO_MODE_BURST
) {
1088 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1089 txbyteclkhs(adjusted_mode
->crtc_htotal
, bpp
,
1090 intel_dsi
->lane_count
,
1091 intel_dsi
->burst_mode_ratio
) + 1);
1093 I915_WRITE(MIPI_HS_TX_TIMEOUT(port
),
1094 txbyteclkhs(adjusted_mode
->crtc_vtotal
*
1095 adjusted_mode
->crtc_htotal
,
1096 bpp
, intel_dsi
->lane_count
,
1097 intel_dsi
->burst_mode_ratio
) + 1);
1099 I915_WRITE(MIPI_LP_RX_TIMEOUT(port
), intel_dsi
->lp_rx_timeout
);
1100 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port
),
1101 intel_dsi
->turn_arnd_val
);
1102 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port
),
1103 intel_dsi
->rst_timer_val
);
1107 /* in terms of low power clock */
1108 I915_WRITE(MIPI_INIT_COUNT(port
),
1109 txclkesc(intel_dsi
->escape_clk_div
, 100));
1111 if (IS_BROXTON(dev
) && (!intel_dsi
->dual_link
)) {
1113 * BXT spec says write MIPI_INIT_COUNT for
1114 * both the ports, even if only one is
1115 * getting used. So write the other port
1116 * if not in dual link mode.
1118 I915_WRITE(MIPI_INIT_COUNT(port
==
1119 PORT_A
? PORT_C
: PORT_A
),
1120 intel_dsi
->init_count
);
1123 /* recovery disables */
1124 I915_WRITE(MIPI_EOT_DISABLE(port
), tmp
);
1126 /* in terms of low power clock */
1127 I915_WRITE(MIPI_INIT_COUNT(port
), intel_dsi
->init_count
);
1129 /* in terms of txbyteclkhs. actual high to low switch +
1130 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1132 * XXX: write MIPI_STOP_STATE_STALL?
1134 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port
),
1135 intel_dsi
->hs_to_lp_count
);
1137 /* XXX: low power clock equivalence in terms of byte clock.
1138 * the number of byte clocks occupied in one low power clock.
1139 * based on txbyteclkhs and txclkesc.
1140 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1143 I915_WRITE(MIPI_LP_BYTECLK(port
), intel_dsi
->lp_byte_clk
);
1145 /* the bw essential for transmitting 16 long packets containing
1146 * 252 bytes meant for dcs write memory command is programmed in
1147 * this register in terms of byte clocks. based on dsi transfer
1148 * rate and the number of lanes configured the time taken to
1149 * transmit 16 long packets in a dsi stream varies. */
1150 I915_WRITE(MIPI_DBI_BW_CTRL(port
), intel_dsi
->bw_timer
);
1152 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port
),
1153 intel_dsi
->clk_lp_to_hs_count
<< LP_HS_SSW_CNT_SHIFT
|
1154 intel_dsi
->clk_hs_to_lp_count
<< HS_LP_PWR_SW_CNT_SHIFT
);
1156 if (is_vid_mode(intel_dsi
))
1157 /* Some panels might have resolution which is not a
1158 * multiple of 64 like 1366 x 768. Enable RANDOM
1159 * resolution support for such panels by default */
1160 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port
),
1161 intel_dsi
->video_frmt_cfg_bits
|
1162 intel_dsi
->video_mode_format
|
1164 RANDOM_DPI_DISPLAY_RESOLUTION
);
1168 static enum drm_connector_status
1169 intel_dsi_detect(struct drm_connector
*connector
, bool force
)
1171 return connector_status_connected
;
1174 static int intel_dsi_get_modes(struct drm_connector
*connector
)
1176 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1177 struct drm_display_mode
*mode
;
1179 DRM_DEBUG_KMS("\n");
1181 if (!intel_connector
->panel
.fixed_mode
) {
1182 DRM_DEBUG_KMS("no fixed mode\n");
1186 mode
= drm_mode_duplicate(connector
->dev
,
1187 intel_connector
->panel
.fixed_mode
);
1189 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1193 drm_mode_probed_add(connector
, mode
);
1197 static int intel_dsi_set_property(struct drm_connector
*connector
,
1198 struct drm_property
*property
,
1201 struct drm_device
*dev
= connector
->dev
;
1202 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1203 struct drm_crtc
*crtc
;
1206 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1210 if (property
== dev
->mode_config
.scaling_mode_property
) {
1211 if (val
== DRM_MODE_SCALE_NONE
) {
1212 DRM_DEBUG_KMS("no scaling not supported\n");
1215 if (HAS_GMCH_DISPLAY(dev
) &&
1216 val
== DRM_MODE_SCALE_CENTER
) {
1217 DRM_DEBUG_KMS("centering not supported\n");
1221 if (intel_connector
->panel
.fitting_mode
== val
)
1224 intel_connector
->panel
.fitting_mode
= val
;
1227 crtc
= intel_attached_encoder(connector
)->base
.crtc
;
1228 if (crtc
&& crtc
->state
->enable
) {
1230 * If the CRTC is enabled, the display will be changed
1231 * according to the new panel fitting mode.
1233 intel_crtc_restore_mode(crtc
);
1239 static void intel_dsi_connector_destroy(struct drm_connector
*connector
)
1241 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
1243 DRM_DEBUG_KMS("\n");
1244 intel_panel_fini(&intel_connector
->panel
);
1245 drm_connector_cleanup(connector
);
1249 static void intel_dsi_encoder_destroy(struct drm_encoder
*encoder
)
1251 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(encoder
);
1253 if (intel_dsi
->panel
) {
1254 drm_panel_detach(intel_dsi
->panel
);
1255 /* XXX: Logically this call belongs in the panel driver. */
1256 drm_panel_remove(intel_dsi
->panel
);
1259 /* dispose of the gpios */
1260 if (intel_dsi
->gpio_panel
)
1261 gpiod_put(intel_dsi
->gpio_panel
);
1263 intel_encoder_destroy(encoder
);
1266 static const struct drm_encoder_funcs intel_dsi_funcs
= {
1267 .destroy
= intel_dsi_encoder_destroy
,
1270 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
= {
1271 .get_modes
= intel_dsi_get_modes
,
1272 .mode_valid
= intel_dsi_mode_valid
,
1273 .best_encoder
= intel_best_encoder
,
1276 static const struct drm_connector_funcs intel_dsi_connector_funcs
= {
1277 .dpms
= drm_atomic_helper_connector_dpms
,
1278 .detect
= intel_dsi_detect
,
1279 .destroy
= intel_dsi_connector_destroy
,
1280 .fill_modes
= drm_helper_probe_single_connector_modes
,
1281 .set_property
= intel_dsi_set_property
,
1282 .atomic_get_property
= intel_connector_atomic_get_property
,
1283 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1284 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1287 static void intel_dsi_add_properties(struct intel_connector
*connector
)
1289 struct drm_device
*dev
= connector
->base
.dev
;
1291 if (connector
->panel
.fixed_mode
) {
1292 drm_mode_create_scaling_mode_property(dev
);
1293 drm_object_attach_property(&connector
->base
.base
,
1294 dev
->mode_config
.scaling_mode_property
,
1295 DRM_MODE_SCALE_ASPECT
);
1296 connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
1300 void intel_dsi_init(struct drm_device
*dev
)
1302 struct intel_dsi
*intel_dsi
;
1303 struct intel_encoder
*intel_encoder
;
1304 struct drm_encoder
*encoder
;
1305 struct intel_connector
*intel_connector
;
1306 struct drm_connector
*connector
;
1307 struct drm_display_mode
*scan
, *fixed_mode
= NULL
;
1308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1312 DRM_DEBUG_KMS("\n");
1314 /* There is no detection method for MIPI so rely on VBT */
1315 if (!intel_bios_is_dsi_present(dev_priv
, &port
))
1318 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1319 dev_priv
->mipi_mmio_base
= VLV_MIPI_BASE
;
1320 } else if (IS_BROXTON(dev
)) {
1321 dev_priv
->mipi_mmio_base
= BXT_MIPI_BASE
;
1323 DRM_ERROR("Unsupported Mipi device to reg base");
1327 intel_dsi
= kzalloc(sizeof(*intel_dsi
), GFP_KERNEL
);
1331 intel_connector
= intel_connector_alloc();
1332 if (!intel_connector
) {
1337 intel_encoder
= &intel_dsi
->base
;
1338 encoder
= &intel_encoder
->base
;
1339 intel_dsi
->attached_connector
= intel_connector
;
1341 connector
= &intel_connector
->base
;
1343 drm_encoder_init(dev
, encoder
, &intel_dsi_funcs
, DRM_MODE_ENCODER_DSI
,
1346 intel_encoder
->compute_config
= intel_dsi_compute_config
;
1347 intel_encoder
->pre_enable
= intel_dsi_pre_enable
;
1348 intel_encoder
->enable
= intel_dsi_enable_nop
;
1349 intel_encoder
->disable
= intel_dsi_pre_disable
;
1350 intel_encoder
->post_disable
= intel_dsi_post_disable
;
1351 intel_encoder
->get_hw_state
= intel_dsi_get_hw_state
;
1352 intel_encoder
->get_config
= intel_dsi_get_config
;
1354 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1355 intel_connector
->unregister
= intel_connector_unregister
;
1358 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1359 * port C. BXT isn't limited like this.
1361 if (IS_BROXTON(dev_priv
))
1362 intel_encoder
->crtc_mask
= BIT(PIPE_A
) | BIT(PIPE_B
) | BIT(PIPE_C
);
1363 else if (port
== PORT_A
)
1364 intel_encoder
->crtc_mask
= BIT(PIPE_A
);
1366 intel_encoder
->crtc_mask
= BIT(PIPE_B
);
1368 if (dev_priv
->vbt
.dsi
.config
->dual_link
)
1369 intel_dsi
->ports
= BIT(PORT_A
) | BIT(PORT_C
);
1371 intel_dsi
->ports
= BIT(port
);
1373 /* Create a DSI host (and a device) for each port. */
1374 for_each_dsi_port(port
, intel_dsi
->ports
) {
1375 struct intel_dsi_host
*host
;
1377 host
= intel_dsi_host_init(intel_dsi
, port
);
1381 intel_dsi
->dsi_hosts
[port
] = host
;
1384 for (i
= 0; i
< ARRAY_SIZE(intel_dsi_drivers
); i
++) {
1385 intel_dsi
->panel
= intel_dsi_drivers
[i
].init(intel_dsi
,
1386 intel_dsi_drivers
[i
].panel_id
);
1387 if (intel_dsi
->panel
)
1391 if (!intel_dsi
->panel
) {
1392 DRM_DEBUG_KMS("no device found\n");
1397 * In case of BYT with CRC PMIC, we need to use GPIO for
1400 if (dev_priv
->vbt
.dsi
.config
->pwm_blc
== PPS_BLC_PMIC
) {
1401 intel_dsi
->gpio_panel
=
1402 gpiod_get(dev
->dev
, "panel", GPIOD_OUT_HIGH
);
1404 if (IS_ERR(intel_dsi
->gpio_panel
)) {
1405 DRM_ERROR("Failed to own gpio for panel control\n");
1406 intel_dsi
->gpio_panel
= NULL
;
1410 intel_encoder
->type
= INTEL_OUTPUT_DSI
;
1411 intel_encoder
->cloneable
= 0;
1412 drm_connector_init(dev
, connector
, &intel_dsi_connector_funcs
,
1413 DRM_MODE_CONNECTOR_DSI
);
1415 drm_connector_helper_add(connector
, &intel_dsi_connector_helper_funcs
);
1417 connector
->display_info
.subpixel_order
= SubPixelHorizontalRGB
; /*XXX*/
1418 connector
->interlace_allowed
= false;
1419 connector
->doublescan_allowed
= false;
1421 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1423 drm_panel_attach(intel_dsi
->panel
, connector
);
1425 mutex_lock(&dev
->mode_config
.mutex
);
1426 drm_panel_get_modes(intel_dsi
->panel
);
1427 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
1428 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
1429 fixed_mode
= drm_mode_duplicate(dev
, scan
);
1433 mutex_unlock(&dev
->mode_config
.mutex
);
1436 DRM_DEBUG_KMS("no fixed mode\n");
1440 intel_panel_init(&intel_connector
->panel
, fixed_mode
, NULL
);
1442 intel_dsi_add_properties(intel_connector
);
1444 drm_connector_register(connector
);
1446 intel_panel_setup_backlight(connector
, INVALID_PIPE
);
1451 drm_encoder_cleanup(&intel_encoder
->base
);
1453 kfree(intel_connector
);