2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
28 #include <linux/kernel.h>
29 #include "intel_drv.h"
31 #include "intel_dsi.h"
33 static const u16 lfsr_converts
[] = {
34 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
35 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
36 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
37 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
40 /* Get DSI clock from pixel clock */
41 static u32
dsi_clk_from_pclk(u32 pclk
, enum mipi_dsi_pixel_format fmt
,
45 u32 bpp
= mipi_dsi_pixel_format_to_bpp(fmt
);
47 /* DSI data rate = pixel clock * bits per pixel / lane count
48 pixel clock is converted from KHz to Hz */
49 dsi_clk_khz
= DIV_ROUND_CLOSEST(pclk
* bpp
, lane_count
);
54 static int dsi_calc_mnp(struct drm_i915_private
*dev_priv
,
55 struct intel_crtc_state
*config
,
58 unsigned int calc_m
= 0, calc_p
= 0;
59 unsigned int m_min
, m_max
, p_min
= 2, p_max
= 6;
62 int delta
= target_dsi_clk
;
65 /* target_dsi_clk is expected in kHz */
66 if (target_dsi_clk
< 300000 || target_dsi_clk
> 1150000) {
67 DRM_ERROR("DSI CLK Out of Range\n");
71 if (IS_CHERRYVIEW(dev_priv
)) {
83 for (m
= m_min
; m
<= m_max
&& delta
; m
++) {
84 for (p
= p_min
; p
<= p_max
&& delta
; p
++) {
86 * Find the optimal m and p divisors with minimal delta
87 * +/- the required clock
89 int calc_dsi_clk
= (m
* ref_clk
) / (p
* n
);
90 int d
= abs(target_dsi_clk
- calc_dsi_clk
);
99 /* register has log2(N1), this works fine for powers of two */
101 m_seed
= lfsr_converts
[calc_m
- 62];
102 config
->dsi_pll
.ctrl
= 1 << (DSI_PLL_P1_POST_DIV_SHIFT
+ calc_p
- 2);
103 config
->dsi_pll
.div
= n
<< DSI_PLL_N1_DIV_SHIFT
|
104 m_seed
<< DSI_PLL_M1_DIV_SHIFT
;
110 * XXX: The muxing and gating is hard coded for now. Need to add support for
111 * sharing PLLs with two DSI outputs.
113 static int vlv_compute_dsi_pll(struct intel_encoder
*encoder
,
114 struct intel_crtc_state
*config
)
116 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
117 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
121 dsi_clk
= dsi_clk_from_pclk(intel_dsi
->pclk
, intel_dsi
->pixel_format
,
122 intel_dsi
->lane_count
);
124 ret
= dsi_calc_mnp(dev_priv
, config
, dsi_clk
);
126 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
130 if (intel_dsi
->ports
& (1 << PORT_A
))
131 config
->dsi_pll
.ctrl
|= DSI_PLL_CLK_GATE_DSI0_DSIPLL
;
133 if (intel_dsi
->ports
& (1 << PORT_C
))
134 config
->dsi_pll
.ctrl
|= DSI_PLL_CLK_GATE_DSI1_DSIPLL
;
136 config
->dsi_pll
.ctrl
|= DSI_PLL_VCO_EN
;
138 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
139 config
->dsi_pll
.div
, config
->dsi_pll
.ctrl
);
144 static void vlv_enable_dsi_pll(struct intel_encoder
*encoder
,
145 const struct intel_crtc_state
*config
)
147 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
151 mutex_lock(&dev_priv
->sb_lock
);
153 vlv_cck_write(dev_priv
, CCK_REG_DSI_PLL_CONTROL
, 0);
154 vlv_cck_write(dev_priv
, CCK_REG_DSI_PLL_DIVIDER
, config
->dsi_pll
.div
);
155 vlv_cck_write(dev_priv
, CCK_REG_DSI_PLL_CONTROL
,
156 config
->dsi_pll
.ctrl
& ~DSI_PLL_VCO_EN
);
158 /* wait at least 0.5 us after ungating before enabling VCO */
161 vlv_cck_write(dev_priv
, CCK_REG_DSI_PLL_CONTROL
, config
->dsi_pll
.ctrl
);
163 if (wait_for(vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
) &
166 mutex_unlock(&dev_priv
->sb_lock
);
167 DRM_ERROR("DSI PLL lock failed\n");
170 mutex_unlock(&dev_priv
->sb_lock
);
172 DRM_DEBUG_KMS("DSI PLL locked\n");
175 static void vlv_disable_dsi_pll(struct intel_encoder
*encoder
)
177 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
182 mutex_lock(&dev_priv
->sb_lock
);
184 tmp
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
185 tmp
&= ~DSI_PLL_VCO_EN
;
186 tmp
|= DSI_PLL_LDO_GATE
;
187 vlv_cck_write(dev_priv
, CCK_REG_DSI_PLL_CONTROL
, tmp
);
189 mutex_unlock(&dev_priv
->sb_lock
);
192 static bool bxt_dsi_pll_is_enabled(struct drm_i915_private
*dev_priv
)
198 mask
= BXT_DSI_PLL_DO_ENABLE
| BXT_DSI_PLL_LOCKED
;
199 val
= I915_READ(BXT_DSI_PLL_ENABLE
);
200 enabled
= (val
& mask
) == mask
;
206 * Both dividers must be programmed with valid values even if only one
207 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for
208 * paranoia, since BIOS is known to misconfigure PLLs in this way at
209 * times, and since accessing DSI registers with invalid dividers
210 * causes a system hang.
212 val
= I915_READ(BXT_DSI_PLL_CTL
);
213 if (!(val
& BXT_DSIA_16X_MASK
) || !(val
& BXT_DSIC_16X_MASK
)) {
214 DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
222 static void bxt_disable_dsi_pll(struct intel_encoder
*encoder
)
224 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
229 val
= I915_READ(BXT_DSI_PLL_ENABLE
);
230 val
&= ~BXT_DSI_PLL_DO_ENABLE
;
231 I915_WRITE(BXT_DSI_PLL_ENABLE
, val
);
234 * PLL lock should deassert within 200us.
235 * Wait up to 1ms before timing out.
237 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE
)
238 & BXT_DSI_PLL_LOCKED
) == 0, 1))
239 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
242 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt
, int pipe_bpp
)
244 int bpp
= mipi_dsi_pixel_format_to_bpp(fmt
);
246 WARN(bpp
!= pipe_bpp
,
247 "bpp match assertion failure (expected %d, current %d)\n",
251 static u32
vlv_dsi_get_pclk(struct intel_encoder
*encoder
, int pipe_bpp
,
252 struct intel_crtc_state
*config
)
254 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
255 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
257 u32 pll_ctl
, pll_div
;
259 int refclk
= IS_CHERRYVIEW(dev_priv
) ? 100000 : 25000;
264 mutex_lock(&dev_priv
->sb_lock
);
265 pll_ctl
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
266 pll_div
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_DIVIDER
);
267 mutex_unlock(&dev_priv
->sb_lock
);
269 config
->dsi_pll
.ctrl
= pll_ctl
& ~DSI_PLL_LOCK
;
270 config
->dsi_pll
.div
= pll_div
;
272 /* mask out other bits and extract the P1 divisor */
273 pll_ctl
&= DSI_PLL_P1_POST_DIV_MASK
;
274 pll_ctl
= pll_ctl
>> (DSI_PLL_P1_POST_DIV_SHIFT
- 2);
277 n
= (pll_div
& DSI_PLL_N1_DIV_MASK
) >> DSI_PLL_N1_DIV_SHIFT
;
278 n
= 1 << n
; /* register has log2(N1) */
280 /* mask out the other bits and extract the M1 divisor */
281 pll_div
&= DSI_PLL_M1_DIV_MASK
;
282 pll_div
= pll_div
>> DSI_PLL_M1_DIV_SHIFT
;
285 pll_ctl
= pll_ctl
>> 1;
291 DRM_ERROR("wrong P1 divisor\n");
295 for (i
= 0; i
< ARRAY_SIZE(lfsr_converts
); i
++) {
296 if (lfsr_converts
[i
] == pll_div
)
300 if (i
== ARRAY_SIZE(lfsr_converts
)) {
301 DRM_ERROR("wrong m_seed programmed\n");
307 dsi_clock
= (m
* refclk
) / (p
* n
);
309 /* pixel_format and pipe_bpp should agree */
310 assert_bpp_mismatch(intel_dsi
->pixel_format
, pipe_bpp
);
312 pclk
= DIV_ROUND_CLOSEST(dsi_clock
* intel_dsi
->lane_count
, pipe_bpp
);
317 static u32
bxt_dsi_get_pclk(struct intel_encoder
*encoder
, int pipe_bpp
,
318 struct intel_crtc_state
*config
)
323 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
324 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
328 DRM_ERROR("Invalid BPP(0)\n");
332 config
->dsi_pll
.ctrl
= I915_READ(BXT_DSI_PLL_CTL
);
334 dsi_ratio
= config
->dsi_pll
.ctrl
& BXT_DSI_PLL_RATIO_MASK
;
336 dsi_clk
= (dsi_ratio
* BXT_REF_CLOCK_KHZ
) / 2;
338 /* pixel_format and pipe_bpp should agree */
339 assert_bpp_mismatch(intel_dsi
->pixel_format
, pipe_bpp
);
341 pclk
= DIV_ROUND_CLOSEST(dsi_clk
* intel_dsi
->lane_count
, pipe_bpp
);
343 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk
);
347 u32
intel_dsi_get_pclk(struct intel_encoder
*encoder
, int pipe_bpp
,
348 struct intel_crtc_state
*config
)
350 if (IS_BROXTON(encoder
->base
.dev
))
351 return bxt_dsi_get_pclk(encoder
, pipe_bpp
, config
);
353 return vlv_dsi_get_pclk(encoder
, pipe_bpp
, config
);
356 static void vlv_dsi_reset_clocks(struct intel_encoder
*encoder
, enum port port
)
359 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
360 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
362 temp
= I915_READ(MIPI_CTRL(port
));
363 temp
&= ~ESCAPE_CLOCK_DIVIDER_MASK
;
364 I915_WRITE(MIPI_CTRL(port
), temp
|
365 intel_dsi
->escape_clk_div
<<
366 ESCAPE_CLOCK_DIVIDER_SHIFT
);
369 /* Program BXT Mipi clocks and dividers */
370 static void bxt_dsi_program_clocks(struct drm_device
*dev
, enum port port
,
371 const struct intel_crtc_state
*config
)
373 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 u32 mipi_8by3_divider
;
383 /* Clear old configurations */
384 tmp
= I915_READ(BXT_MIPI_CLOCK_CTL
);
385 tmp
&= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port
));
386 tmp
&= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port
));
387 tmp
&= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port
));
388 tmp
&= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port
));
390 /* Get the current DSI rate(actual) */
391 pll_ratio
= config
->dsi_pll
.ctrl
& BXT_DSI_PLL_RATIO_MASK
;
392 dsi_rate
= (BXT_REF_CLOCK_KHZ
* pll_ratio
) / 2;
395 * tx clock should be <= 20MHz and the div value must be
396 * subtracted by 1 as per bspec
398 tx_div
= DIV_ROUND_UP(dsi_rate
, 20000) - 1;
400 * rx clock should be <= 150MHz and the div value must be
401 * subtracted by 1 as per bspec
403 rx_div
= DIV_ROUND_UP(dsi_rate
, 150000) - 1;
406 * rx divider value needs to be updated in the
407 * two differnt bit fields in the register hence splitting the
408 * rx divider value accordingly
410 rx_div_lower
= rx_div
& RX_DIVIDER_BIT_1_2
;
411 rx_div_upper
= (rx_div
& RX_DIVIDER_BIT_3_4
) >> 2;
413 /* As per bpsec program the 8/3X clock divider to the below value */
414 if (dev_priv
->vbt
.dsi
.config
->is_cmd_mode
)
415 mipi_8by3_divider
= 0x2;
417 mipi_8by3_divider
= 0x3;
419 tmp
|= BXT_MIPI_8X_BY3_DIVIDER(port
, mipi_8by3_divider
);
420 tmp
|= BXT_MIPI_TX_ESCLK_DIVIDER(port
, tx_div
);
421 tmp
|= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port
, rx_div_lower
);
422 tmp
|= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port
, rx_div_upper
);
424 I915_WRITE(BXT_MIPI_CLOCK_CTL
, tmp
);
427 static int bxt_compute_dsi_pll(struct intel_encoder
*encoder
,
428 struct intel_crtc_state
*config
)
430 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
434 dsi_clk
= dsi_clk_from_pclk(intel_dsi
->pclk
, intel_dsi
->pixel_format
,
435 intel_dsi
->lane_count
);
438 * From clock diagram, to get PLL ratio divider, divide double of DSI
439 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
440 * round 'up' the result
442 dsi_ratio
= DIV_ROUND_UP(dsi_clk
* 2, BXT_REF_CLOCK_KHZ
);
443 if (dsi_ratio
< BXT_DSI_PLL_RATIO_MIN
||
444 dsi_ratio
> BXT_DSI_PLL_RATIO_MAX
) {
445 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
450 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
451 * Spec says both have to be programmed, even if one is not getting
452 * used. Configure MIPI_CLOCK_CTL dividers in modeset
454 config
->dsi_pll
.ctrl
= dsi_ratio
| BXT_DSIA_16X_BY2
| BXT_DSIC_16X_BY2
;
456 /* As per recommendation from hardware team,
457 * Prog PVD ratio =1 if dsi ratio <= 50
460 config
->dsi_pll
.ctrl
|= BXT_DSI_PLL_PVD_RATIO_1
;
465 static void bxt_enable_dsi_pll(struct intel_encoder
*encoder
,
466 const struct intel_crtc_state
*config
)
468 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
469 struct intel_dsi
*intel_dsi
= enc_to_intel_dsi(&encoder
->base
);
475 /* Configure PLL vales */
476 I915_WRITE(BXT_DSI_PLL_CTL
, config
->dsi_pll
.ctrl
);
477 POSTING_READ(BXT_DSI_PLL_CTL
);
479 /* Program TX, RX, Dphy clocks */
480 for_each_dsi_port(port
, intel_dsi
->ports
)
481 bxt_dsi_program_clocks(encoder
->base
.dev
, port
, config
);
484 val
= I915_READ(BXT_DSI_PLL_ENABLE
);
485 val
|= BXT_DSI_PLL_DO_ENABLE
;
486 I915_WRITE(BXT_DSI_PLL_ENABLE
, val
);
488 /* Timeout and fail if PLL not locked */
489 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE
) & BXT_DSI_PLL_LOCKED
, 1)) {
490 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
494 DRM_DEBUG_KMS("DSI PLL locked\n");
497 bool intel_dsi_pll_is_enabled(struct drm_i915_private
*dev_priv
)
499 if (IS_BROXTON(dev_priv
))
500 return bxt_dsi_pll_is_enabled(dev_priv
);
502 MISSING_CASE(INTEL_DEVID(dev_priv
));
507 int intel_compute_dsi_pll(struct intel_encoder
*encoder
,
508 struct intel_crtc_state
*config
)
510 struct drm_device
*dev
= encoder
->base
.dev
;
512 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
513 return vlv_compute_dsi_pll(encoder
, config
);
514 else if (IS_BROXTON(dev
))
515 return bxt_compute_dsi_pll(encoder
, config
);
520 void intel_enable_dsi_pll(struct intel_encoder
*encoder
,
521 const struct intel_crtc_state
*config
)
523 struct drm_device
*dev
= encoder
->base
.dev
;
525 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
526 vlv_enable_dsi_pll(encoder
, config
);
527 else if (IS_BROXTON(dev
))
528 bxt_enable_dsi_pll(encoder
, config
);
531 void intel_disable_dsi_pll(struct intel_encoder
*encoder
)
533 struct drm_device
*dev
= encoder
->base
.dev
;
535 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
536 vlv_disable_dsi_pll(encoder
);
537 else if (IS_BROXTON(dev
))
538 bxt_disable_dsi_pll(encoder
);
541 static void bxt_dsi_reset_clocks(struct intel_encoder
*encoder
, enum port port
)
544 struct drm_device
*dev
= encoder
->base
.dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
547 /* Clear old configurations */
548 tmp
= I915_READ(BXT_MIPI_CLOCK_CTL
);
549 tmp
&= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port
));
550 tmp
&= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port
));
551 tmp
&= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port
));
552 tmp
&= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port
));
553 I915_WRITE(BXT_MIPI_CLOCK_CTL
, tmp
);
554 I915_WRITE(MIPI_EOT_DISABLE(port
), CLOCKSTOP
);
557 void intel_dsi_reset_clocks(struct intel_encoder
*encoder
, enum port port
)
559 struct drm_device
*dev
= encoder
->base
.dev
;
562 bxt_dsi_reset_clocks(encoder
, port
);
563 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
564 vlv_dsi_reset_clocks(encoder
, port
);