2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static inline bool fbc_supported(struct drm_i915_private
*dev_priv
)
46 return dev_priv
->fbc
.activate
!= NULL
;
49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private
*dev_priv
)
51 return IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8;
54 static inline bool fbc_on_plane_a_only(struct drm_i915_private
*dev_priv
)
56 return INTEL_INFO(dev_priv
)->gen
< 4;
60 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
61 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
62 * origin so the x and y offsets can actually fit the registers. As a
63 * consequence, the fence doesn't really start exactly at the display plane
64 * address we program because it starts at the real start of the buffer, so we
65 * have to take this into consideration here.
67 static unsigned int get_crtc_fence_y_offset(struct intel_crtc
*crtc
)
69 return crtc
->base
.y
- crtc
->adjusted_y
;
73 * For SKL+, the plane source size used by the hardware is based on the value we
74 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
75 * we wrote to PIPESRC.
77 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache
*cache
,
78 int *width
, int *height
)
82 if (intel_rotation_90_or_270(cache
->plane
.rotation
)) {
83 w
= cache
->plane
.src_h
;
84 h
= cache
->plane
.src_w
;
86 w
= cache
->plane
.src_w
;
87 h
= cache
->plane
.src_h
;
96 static int intel_fbc_calculate_cfb_size(struct drm_i915_private
*dev_priv
,
97 struct intel_fbc_state_cache
*cache
)
101 intel_fbc_get_plane_source_size(cache
, NULL
, &lines
);
102 if (INTEL_INFO(dev_priv
)->gen
>= 7)
103 lines
= min(lines
, 2048);
105 /* Hardware needs the full buffer stride, not just the active area. */
106 return lines
* cache
->fb
.stride
;
109 static void i8xx_fbc_deactivate(struct drm_i915_private
*dev_priv
)
113 dev_priv
->fbc
.active
= false;
115 /* Disable compression */
116 fbc_ctl
= I915_READ(FBC_CONTROL
);
117 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
120 fbc_ctl
&= ~FBC_CTL_EN
;
121 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
123 /* Wait for compressing bit to clear */
124 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
125 DRM_DEBUG_KMS("FBC idle timed out\n");
130 static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv
)
132 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
137 dev_priv
->fbc
.active
= true;
139 /* Note: fbc.threshold == 1 for i8xx */
140 cfb_pitch
= params
->cfb_size
/ FBC_LL_SIZE
;
141 if (params
->fb
.stride
< cfb_pitch
)
142 cfb_pitch
= params
->fb
.stride
;
144 /* FBC_CTL wants 32B or 64B units */
145 if (IS_GEN2(dev_priv
))
146 cfb_pitch
= (cfb_pitch
/ 32) - 1;
148 cfb_pitch
= (cfb_pitch
/ 64) - 1;
151 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
152 I915_WRITE(FBC_TAG(i
), 0);
154 if (IS_GEN4(dev_priv
)) {
158 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
159 fbc_ctl2
|= FBC_CTL_PLANE(params
->crtc
.plane
);
160 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
161 I915_WRITE(FBC_FENCE_OFF
, params
->crtc
.fence_y_offset
);
165 fbc_ctl
= I915_READ(FBC_CONTROL
);
166 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
167 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
168 if (IS_I945GM(dev_priv
))
169 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
170 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
171 fbc_ctl
|= params
->fb
.fence_reg
;
172 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
175 static bool i8xx_fbc_is_active(struct drm_i915_private
*dev_priv
)
177 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
180 static void g4x_fbc_activate(struct drm_i915_private
*dev_priv
)
182 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
185 dev_priv
->fbc
.active
= true;
187 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
) | DPFC_SR_EN
;
188 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
189 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
191 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
192 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| params
->fb
.fence_reg
;
194 I915_WRITE(DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
197 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
200 static void g4x_fbc_deactivate(struct drm_i915_private
*dev_priv
)
204 dev_priv
->fbc
.active
= false;
206 /* Disable compression */
207 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
208 if (dpfc_ctl
& DPFC_CTL_EN
) {
209 dpfc_ctl
&= ~DPFC_CTL_EN
;
210 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
214 static bool g4x_fbc_is_active(struct drm_i915_private
*dev_priv
)
216 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
219 /* This function forces a CFB recompression through the nuke operation. */
220 static void intel_fbc_recompress(struct drm_i915_private
*dev_priv
)
222 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
223 POSTING_READ(MSG_FBC_REND_STATE
);
226 static void ilk_fbc_activate(struct drm_i915_private
*dev_priv
)
228 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
230 int threshold
= dev_priv
->fbc
.threshold
;
232 dev_priv
->fbc
.active
= true;
234 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
);
235 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
241 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
244 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
247 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
250 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
251 if (IS_GEN5(dev_priv
))
252 dpfc_ctl
|= params
->fb
.fence_reg
;
254 I915_WRITE(ILK_DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
255 I915_WRITE(ILK_FBC_RT_BASE
, params
->fb
.ggtt_offset
| ILK_FBC_RT_VALID
);
257 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
259 if (IS_GEN6(dev_priv
)) {
260 I915_WRITE(SNB_DPFC_CTL_SA
,
261 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
262 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
265 intel_fbc_recompress(dev_priv
);
268 static void ilk_fbc_deactivate(struct drm_i915_private
*dev_priv
)
272 dev_priv
->fbc
.active
= false;
274 /* Disable compression */
275 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
276 if (dpfc_ctl
& DPFC_CTL_EN
) {
277 dpfc_ctl
&= ~DPFC_CTL_EN
;
278 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
282 static bool ilk_fbc_is_active(struct drm_i915_private
*dev_priv
)
284 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
287 static void gen7_fbc_activate(struct drm_i915_private
*dev_priv
)
289 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
291 int threshold
= dev_priv
->fbc
.threshold
;
293 dev_priv
->fbc
.active
= true;
296 if (IS_IVYBRIDGE(dev_priv
))
297 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(params
->crtc
.plane
);
299 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
305 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
308 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
311 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
315 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
317 if (dev_priv
->fbc
.false_color
)
318 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
320 if (IS_IVYBRIDGE(dev_priv
)) {
321 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
322 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
323 I915_READ(ILK_DISPLAY_CHICKEN1
) |
325 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
326 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
327 I915_WRITE(CHICKEN_PIPESL_1(params
->crtc
.pipe
),
328 I915_READ(CHICKEN_PIPESL_1(params
->crtc
.pipe
)) |
332 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
334 I915_WRITE(SNB_DPFC_CTL_SA
,
335 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
336 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
338 intel_fbc_recompress(dev_priv
);
342 * intel_fbc_is_active - Is FBC active?
343 * @dev_priv: i915 device instance
345 * This function is used to verify the current state of FBC.
346 * FIXME: This should be tracked in the plane config eventually
347 * instead of queried at runtime for most callers.
349 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
)
351 return dev_priv
->fbc
.active
;
354 static void intel_fbc_work_fn(struct work_struct
*__work
)
356 struct drm_i915_private
*dev_priv
=
357 container_of(__work
, struct drm_i915_private
, fbc
.work
.work
);
358 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
359 struct intel_fbc_work
*work
= &fbc
->work
;
360 struct intel_crtc
*crtc
= fbc
->crtc
;
361 struct drm_vblank_crtc
*vblank
= &dev_priv
->dev
->vblank
[crtc
->pipe
];
363 if (drm_crtc_vblank_get(&crtc
->base
)) {
364 DRM_ERROR("vblank not available for FBC on pipe %c\n",
365 pipe_name(crtc
->pipe
));
367 mutex_lock(&fbc
->lock
);
368 work
->scheduled
= false;
369 mutex_unlock(&fbc
->lock
);
374 /* Delay the actual enabling to let pageflipping cease and the
375 * display to settle before starting the compression. Note that
376 * this delay also serves a second purpose: it allows for a
377 * vblank to pass after disabling the FBC before we attempt
378 * to modify the control registers.
380 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
382 * It is also worth mentioning that since work->scheduled_vblank can be
383 * updated multiple times by the other threads, hitting the timeout is
384 * not an error condition. We'll just end up hitting the "goto retry"
387 wait_event_timeout(vblank
->queue
,
388 drm_crtc_vblank_count(&crtc
->base
) != work
->scheduled_vblank
,
389 msecs_to_jiffies(50));
391 mutex_lock(&fbc
->lock
);
393 /* Were we cancelled? */
394 if (!work
->scheduled
)
397 /* Were we delayed again while this function was sleeping? */
398 if (drm_crtc_vblank_count(&crtc
->base
) == work
->scheduled_vblank
) {
399 mutex_unlock(&fbc
->lock
);
403 if (crtc
->base
.primary
->fb
== work
->fb
)
404 fbc
->activate(dev_priv
);
406 work
->scheduled
= false;
409 mutex_unlock(&fbc
->lock
);
410 drm_crtc_vblank_put(&crtc
->base
);
413 static void intel_fbc_cancel_work(struct drm_i915_private
*dev_priv
)
415 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
417 WARN_ON(!mutex_is_locked(&fbc
->lock
));
418 fbc
->work
.scheduled
= false;
421 static void intel_fbc_schedule_activation(struct intel_crtc
*crtc
)
423 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
424 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
425 struct intel_fbc_work
*work
= &fbc
->work
;
427 WARN_ON(!mutex_is_locked(&fbc
->lock
));
429 if (drm_crtc_vblank_get(&crtc
->base
)) {
430 DRM_ERROR("vblank not available for FBC on pipe %c\n",
431 pipe_name(crtc
->pipe
));
435 /* It is useless to call intel_fbc_cancel_work() in this function since
436 * we're not releasing fbc.lock, so it won't have an opportunity to grab
437 * it to discover that it was cancelled. So we just update the expected
439 work
->fb
= crtc
->base
.primary
->fb
;
440 work
->scheduled
= true;
441 work
->scheduled_vblank
= drm_crtc_vblank_count(&crtc
->base
);
442 drm_crtc_vblank_put(&crtc
->base
);
444 schedule_work(&work
->work
);
447 static void intel_fbc_deactivate(struct drm_i915_private
*dev_priv
)
449 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
451 WARN_ON(!mutex_is_locked(&fbc
->lock
));
453 intel_fbc_cancel_work(dev_priv
);
456 fbc
->deactivate(dev_priv
);
459 static void set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
462 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
464 if (fbc
->no_fbc_reason
== reason
)
467 fbc
->no_fbc_reason
= reason
;
468 DRM_DEBUG_KMS("Disabling FBC: %s\n", reason
);
471 static bool crtc_can_fbc(struct intel_crtc
*crtc
)
473 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
475 if (fbc_on_pipe_a_only(dev_priv
) && crtc
->pipe
!= PIPE_A
)
478 if (fbc_on_plane_a_only(dev_priv
) && crtc
->plane
!= PLANE_A
)
484 static bool multiple_pipes_ok(struct drm_i915_private
*dev_priv
)
488 struct drm_crtc
*crtc
;
490 if (INTEL_INFO(dev_priv
)->gen
> 4)
493 /* FIXME: we don't have the appropriate state locks to do this here. */
494 for_each_pipe(dev_priv
, pipe
) {
495 crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
497 if (intel_crtc_active(crtc
) &&
498 to_intel_plane_state(crtc
->primary
->state
)->visible
)
502 return (n_pipes
< 2);
505 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
506 struct drm_mm_node
*node
,
510 int compression_threshold
= 1;
514 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
515 * reserved range size, so it always assumes the maximum (8mb) is used.
516 * If we enable FBC using a CFB on that memory range we'll get FIFO
517 * underruns, even if that range is not reserved by the BIOS. */
518 if (IS_BROADWELL(dev_priv
) ||
519 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
520 end
= dev_priv
->gtt
.stolen_size
- 8 * 1024 * 1024;
522 end
= dev_priv
->gtt
.stolen_usable_size
;
524 /* HACK: This code depends on what we will do in *_enable_fbc. If that
525 * code changes, this code needs to change as well.
527 * The enable_fbc code will attempt to use one of our 2 compression
528 * thresholds, therefore, in that case, we only have 1 resort.
531 /* Try to over-allocate to reduce reallocations and fragmentation. */
532 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
535 return compression_threshold
;
538 /* HW's ability to limit the CFB is 1:4 */
539 if (compression_threshold
> 4 ||
540 (fb_cpp
== 2 && compression_threshold
== 2))
543 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
545 if (ret
&& INTEL_INFO(dev_priv
)->gen
<= 4) {
548 compression_threshold
<<= 1;
551 return compression_threshold
;
555 static int intel_fbc_alloc_cfb(struct intel_crtc
*crtc
)
557 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
558 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
559 struct drm_mm_node
*uninitialized_var(compressed_llb
);
560 int size
, fb_cpp
, ret
;
562 WARN_ON(drm_mm_node_allocated(&fbc
->compressed_fb
));
564 size
= intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
);
565 fb_cpp
= drm_format_plane_cpp(fbc
->state_cache
.fb
.pixel_format
, 0);
567 ret
= find_compression_threshold(dev_priv
, &fbc
->compressed_fb
,
572 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
576 fbc
->threshold
= ret
;
578 if (INTEL_INFO(dev_priv
)->gen
>= 5)
579 I915_WRITE(ILK_DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
580 else if (IS_GM45(dev_priv
)) {
581 I915_WRITE(DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
583 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
587 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
592 fbc
->compressed_llb
= compressed_llb
;
594 I915_WRITE(FBC_CFB_BASE
,
595 dev_priv
->mm
.stolen_base
+ fbc
->compressed_fb
.start
);
596 I915_WRITE(FBC_LL_BASE
,
597 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
600 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
601 fbc
->compressed_fb
.size
, fbc
->threshold
);
606 kfree(compressed_llb
);
607 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
609 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
613 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
615 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
617 if (drm_mm_node_allocated(&fbc
->compressed_fb
))
618 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
620 if (fbc
->compressed_llb
) {
621 i915_gem_stolen_remove_node(dev_priv
, fbc
->compressed_llb
);
622 kfree(fbc
->compressed_llb
);
626 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
628 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
630 if (!fbc_supported(dev_priv
))
633 mutex_lock(&fbc
->lock
);
634 __intel_fbc_cleanup_cfb(dev_priv
);
635 mutex_unlock(&fbc
->lock
);
638 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
641 /* These should have been caught earlier. */
642 WARN_ON(stride
< 512);
643 WARN_ON((stride
& (64 - 1)) != 0);
645 /* Below are the additional FBC restrictions. */
647 if (IS_GEN2(dev_priv
) || IS_GEN3(dev_priv
))
648 return stride
== 4096 || stride
== 8192;
650 if (IS_GEN4(dev_priv
) && !IS_G4X(dev_priv
) && stride
< 2048)
659 static bool pixel_format_is_valid(struct drm_i915_private
*dev_priv
,
660 uint32_t pixel_format
)
662 switch (pixel_format
) {
663 case DRM_FORMAT_XRGB8888
:
664 case DRM_FORMAT_XBGR8888
:
666 case DRM_FORMAT_XRGB1555
:
667 case DRM_FORMAT_RGB565
:
668 /* 16bpp not supported on gen2 */
669 if (IS_GEN2(dev_priv
))
671 /* WaFbcOnly1to1Ratio:ctg */
672 if (IS_G4X(dev_priv
))
681 * For some reason, the hardware tracking starts looking at whatever we
682 * programmed as the display plane base address register. It does not look at
683 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
684 * variables instead of just looking at the pipe/plane size.
686 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc
*crtc
)
688 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
689 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
690 unsigned int effective_w
, effective_h
, max_w
, max_h
;
692 if (INTEL_INFO(dev_priv
)->gen
>= 8 || IS_HASWELL(dev_priv
)) {
695 } else if (IS_G4X(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 5) {
703 intel_fbc_get_plane_source_size(&fbc
->state_cache
, &effective_w
,
705 effective_w
+= crtc
->adjusted_x
;
706 effective_h
+= crtc
->adjusted_y
;
708 return effective_w
<= max_w
&& effective_h
<= max_h
;
711 static void intel_fbc_update_state_cache(struct intel_crtc
*crtc
)
713 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
714 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
715 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
716 struct intel_crtc_state
*crtc_state
=
717 to_intel_crtc_state(crtc
->base
.state
);
718 struct intel_plane_state
*plane_state
=
719 to_intel_plane_state(crtc
->base
.primary
->state
);
720 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
721 struct drm_i915_gem_object
*obj
;
723 WARN_ON(!drm_modeset_is_locked(&crtc
->base
.mutex
));
724 WARN_ON(!drm_modeset_is_locked(&crtc
->base
.primary
->mutex
));
726 cache
->crtc
.mode_flags
= crtc_state
->base
.adjusted_mode
.flags
;
727 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
728 cache
->crtc
.hsw_bdw_pixel_rate
=
729 ilk_pipe_pixel_rate(crtc_state
);
731 cache
->plane
.rotation
= plane_state
->base
.rotation
;
732 cache
->plane
.src_w
= drm_rect_width(&plane_state
->src
) >> 16;
733 cache
->plane
.src_h
= drm_rect_height(&plane_state
->src
) >> 16;
734 cache
->plane
.visible
= plane_state
->visible
;
736 if (!cache
->plane
.visible
)
739 obj
= intel_fb_obj(fb
);
741 /* FIXME: We lack the proper locking here, so only run this on the
742 * platforms that need. */
743 if (dev_priv
->fbc
.activate
== ilk_fbc_activate
)
744 cache
->fb
.ilk_ggtt_offset
= i915_gem_obj_ggtt_offset(obj
);
745 cache
->fb
.id
= fb
->base
.id
;
746 cache
->fb
.pixel_format
= fb
->pixel_format
;
747 cache
->fb
.stride
= fb
->pitches
[0];
748 cache
->fb
.fence_reg
= obj
->fence_reg
;
749 cache
->fb
.tiling_mode
= obj
->tiling_mode
;
752 static bool intel_fbc_can_activate(struct intel_crtc
*crtc
)
754 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
755 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
756 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
758 if (!cache
->plane
.visible
) {
759 set_no_fbc_reason(dev_priv
, "primary plane not visible");
763 if ((cache
->crtc
.mode_flags
& DRM_MODE_FLAG_INTERLACE
) ||
764 (cache
->crtc
.mode_flags
& DRM_MODE_FLAG_DBLSCAN
)) {
765 set_no_fbc_reason(dev_priv
, "incompatible mode");
769 if (!intel_fbc_hw_tracking_covers_screen(crtc
)) {
770 set_no_fbc_reason(dev_priv
, "mode too large for compression");
774 /* The use of a CPU fence is mandatory in order to detect writes
775 * by the CPU to the scanout and trigger updates to the FBC.
777 if (cache
->fb
.tiling_mode
!= I915_TILING_X
||
778 cache
->fb
.fence_reg
== I915_FENCE_REG_NONE
) {
779 set_no_fbc_reason(dev_priv
, "framebuffer not tiled or fenced");
782 if (INTEL_INFO(dev_priv
)->gen
<= 4 && !IS_G4X(dev_priv
) &&
783 cache
->plane
.rotation
!= BIT(DRM_ROTATE_0
)) {
784 set_no_fbc_reason(dev_priv
, "rotation unsupported");
788 if (!stride_is_valid(dev_priv
, cache
->fb
.stride
)) {
789 set_no_fbc_reason(dev_priv
, "framebuffer stride not supported");
793 if (!pixel_format_is_valid(dev_priv
, cache
->fb
.pixel_format
)) {
794 set_no_fbc_reason(dev_priv
, "pixel format is invalid");
798 /* WaFbcExceedCdClockThreshold:hsw,bdw */
799 if ((IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) &&
800 cache
->crtc
.hsw_bdw_pixel_rate
>= dev_priv
->cdclk_freq
* 95 / 100) {
801 set_no_fbc_reason(dev_priv
, "pixel rate is too big");
805 /* It is possible for the required CFB size change without a
806 * crtc->disable + crtc->enable since it is possible to change the
807 * stride without triggering a full modeset. Since we try to
808 * over-allocate the CFB, there's a chance we may keep FBC enabled even
809 * if this happens, but if we exceed the current CFB size we'll have to
810 * disable FBC. Notice that it would be possible to disable FBC, wait
811 * for a frame, free the stolen node, then try to reenable FBC in case
812 * we didn't get any invalidate/deactivate calls, but this would require
813 * a lot of tracking just for a specific case. If we conclude it's an
814 * important case, we can implement it later. */
815 if (intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
) >
816 fbc
->compressed_fb
.size
* fbc
->threshold
) {
817 set_no_fbc_reason(dev_priv
, "CFB requirements changed");
824 static bool intel_fbc_can_enable(struct intel_crtc
*crtc
)
826 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
828 if (intel_vgpu_active(dev_priv
->dev
)) {
829 set_no_fbc_reason(dev_priv
, "VGPU is active");
833 if (i915
.enable_fbc
< 0) {
834 set_no_fbc_reason(dev_priv
, "disabled per chip default");
838 if (!i915
.enable_fbc
) {
839 set_no_fbc_reason(dev_priv
, "disabled per module param");
843 if (!crtc_can_fbc(crtc
)) {
844 set_no_fbc_reason(dev_priv
, "no enabled pipes can have FBC");
851 static void intel_fbc_get_reg_params(struct intel_crtc
*crtc
,
852 struct intel_fbc_reg_params
*params
)
854 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
855 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
856 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
858 /* Since all our fields are integer types, use memset here so the
859 * comparison function can rely on memcmp because the padding will be
861 memset(params
, 0, sizeof(*params
));
863 params
->crtc
.pipe
= crtc
->pipe
;
864 params
->crtc
.plane
= crtc
->plane
;
865 params
->crtc
.fence_y_offset
= get_crtc_fence_y_offset(crtc
);
867 params
->fb
.id
= cache
->fb
.id
;
868 params
->fb
.pixel_format
= cache
->fb
.pixel_format
;
869 params
->fb
.stride
= cache
->fb
.stride
;
870 params
->fb
.fence_reg
= cache
->fb
.fence_reg
;
872 params
->cfb_size
= intel_fbc_calculate_cfb_size(dev_priv
, cache
);
874 params
->fb
.ggtt_offset
= cache
->fb
.ilk_ggtt_offset
;
877 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params
*params1
,
878 struct intel_fbc_reg_params
*params2
)
880 /* We can use this since intel_fbc_get_reg_params() does a memset. */
881 return memcmp(params1
, params2
, sizeof(*params1
)) == 0;
884 void intel_fbc_pre_update(struct intel_crtc
*crtc
)
886 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
887 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
889 if (!fbc_supported(dev_priv
))
892 mutex_lock(&fbc
->lock
);
894 if (!multiple_pipes_ok(dev_priv
)) {
895 set_no_fbc_reason(dev_priv
, "more than one pipe active");
899 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
902 intel_fbc_update_state_cache(crtc
);
905 intel_fbc_deactivate(dev_priv
);
907 mutex_unlock(&fbc
->lock
);
910 static void __intel_fbc_post_update(struct intel_crtc
*crtc
)
912 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
913 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
914 struct intel_fbc_reg_params old_params
;
916 WARN_ON(!mutex_is_locked(&fbc
->lock
));
918 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
921 if (!intel_fbc_can_activate(crtc
)) {
922 WARN_ON(fbc
->active
);
926 old_params
= fbc
->params
;
927 intel_fbc_get_reg_params(crtc
, &fbc
->params
);
929 /* If the scanout has not changed, don't modify the FBC settings.
930 * Note that we make the fundamental assumption that the fb->obj
931 * cannot be unpinned (and have its GTT offset and fence revoked)
932 * without first being decoupled from the scanout and FBC disabled.
935 intel_fbc_reg_params_equal(&old_params
, &fbc
->params
))
938 intel_fbc_deactivate(dev_priv
);
939 intel_fbc_schedule_activation(crtc
);
940 fbc
->no_fbc_reason
= "FBC enabled (active or scheduled)";
943 void intel_fbc_post_update(struct intel_crtc
*crtc
)
945 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
946 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
948 if (!fbc_supported(dev_priv
))
951 mutex_lock(&fbc
->lock
);
952 __intel_fbc_post_update(crtc
);
953 mutex_unlock(&fbc
->lock
);
956 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc
*fbc
)
959 return to_intel_plane(fbc
->crtc
->base
.primary
)->frontbuffer_bit
;
961 return fbc
->possible_framebuffer_bits
;
964 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
965 unsigned int frontbuffer_bits
,
966 enum fb_op_origin origin
)
968 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
970 if (!fbc_supported(dev_priv
))
973 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
976 mutex_lock(&fbc
->lock
);
978 fbc
->busy_bits
|= intel_fbc_get_frontbuffer_bit(fbc
) & frontbuffer_bits
;
981 intel_fbc_deactivate(dev_priv
);
983 mutex_unlock(&fbc
->lock
);
986 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
987 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
989 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
991 if (!fbc_supported(dev_priv
))
994 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
997 mutex_lock(&fbc
->lock
);
999 fbc
->busy_bits
&= ~frontbuffer_bits
;
1001 if (!fbc
->busy_bits
&& fbc
->enabled
&&
1002 (frontbuffer_bits
& intel_fbc_get_frontbuffer_bit(fbc
))) {
1004 intel_fbc_recompress(dev_priv
);
1006 __intel_fbc_post_update(fbc
->crtc
);
1009 mutex_unlock(&fbc
->lock
);
1013 * intel_fbc_enable: tries to enable FBC on the CRTC
1016 * This function checks if it's possible to enable FBC on the following CRTC,
1017 * then enables it. Notice that it doesn't activate FBC.
1019 void intel_fbc_enable(struct intel_crtc
*crtc
)
1021 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1022 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1024 if (!fbc_supported(dev_priv
))
1027 mutex_lock(&fbc
->lock
);
1030 WARN_ON(fbc
->crtc
== crtc
);
1034 WARN_ON(fbc
->active
);
1035 WARN_ON(fbc
->crtc
!= NULL
);
1037 if (!intel_fbc_can_enable(crtc
))
1040 intel_fbc_update_state_cache(crtc
);
1041 if (intel_fbc_alloc_cfb(crtc
)) {
1042 set_no_fbc_reason(dev_priv
, "not enough stolen memory");
1046 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1047 fbc
->no_fbc_reason
= "FBC enabled but not active yet\n";
1049 fbc
->enabled
= true;
1052 mutex_unlock(&fbc
->lock
);
1056 * __intel_fbc_disable - disable FBC
1057 * @dev_priv: i915 device instance
1059 * This is the low level function that actually disables FBC. Callers should
1060 * grab the FBC lock.
1062 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
1064 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1065 struct intel_crtc
*crtc
= fbc
->crtc
;
1067 WARN_ON(!mutex_is_locked(&fbc
->lock
));
1068 WARN_ON(!fbc
->enabled
);
1069 WARN_ON(fbc
->active
);
1070 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1072 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1074 __intel_fbc_cleanup_cfb(dev_priv
);
1076 fbc
->enabled
= false;
1081 * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
1084 * This function disables FBC if it's associated with the provided CRTC.
1086 void intel_fbc_disable_crtc(struct intel_crtc
*crtc
)
1088 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1089 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1091 if (!fbc_supported(dev_priv
))
1094 mutex_lock(&fbc
->lock
);
1095 if (fbc
->crtc
== crtc
) {
1096 WARN_ON(!fbc
->enabled
);
1097 WARN_ON(fbc
->active
);
1098 __intel_fbc_disable(dev_priv
);
1100 mutex_unlock(&fbc
->lock
);
1104 * intel_fbc_disable - globally disable FBC
1105 * @dev_priv: i915 device instance
1107 * This function disables FBC regardless of which CRTC is associated with it.
1109 void intel_fbc_disable(struct drm_i915_private
*dev_priv
)
1111 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1113 if (!fbc_supported(dev_priv
))
1116 mutex_lock(&fbc
->lock
);
1118 __intel_fbc_disable(dev_priv
);
1119 mutex_unlock(&fbc
->lock
);
1123 * intel_fbc_init - Initialize FBC
1124 * @dev_priv: the i915 device
1126 * This function might be called during PM init process.
1128 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
1130 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1133 INIT_WORK(&fbc
->work
.work
, intel_fbc_work_fn
);
1134 mutex_init(&fbc
->lock
);
1135 fbc
->enabled
= false;
1136 fbc
->active
= false;
1137 fbc
->work
.scheduled
= false;
1139 if (!HAS_FBC(dev_priv
)) {
1140 fbc
->no_fbc_reason
= "unsupported by this chipset";
1144 for_each_pipe(dev_priv
, pipe
) {
1145 fbc
->possible_framebuffer_bits
|=
1146 INTEL_FRONTBUFFER_PRIMARY(pipe
);
1148 if (fbc_on_pipe_a_only(dev_priv
))
1152 if (INTEL_INFO(dev_priv
)->gen
>= 7) {
1153 fbc
->is_active
= ilk_fbc_is_active
;
1154 fbc
->activate
= gen7_fbc_activate
;
1155 fbc
->deactivate
= ilk_fbc_deactivate
;
1156 } else if (INTEL_INFO(dev_priv
)->gen
>= 5) {
1157 fbc
->is_active
= ilk_fbc_is_active
;
1158 fbc
->activate
= ilk_fbc_activate
;
1159 fbc
->deactivate
= ilk_fbc_deactivate
;
1160 } else if (IS_GM45(dev_priv
)) {
1161 fbc
->is_active
= g4x_fbc_is_active
;
1162 fbc
->activate
= g4x_fbc_activate
;
1163 fbc
->deactivate
= g4x_fbc_deactivate
;
1165 fbc
->is_active
= i8xx_fbc_is_active
;
1166 fbc
->activate
= i8xx_fbc_activate
;
1167 fbc
->deactivate
= i8xx_fbc_deactivate
;
1169 /* This value was pulled out of someone's hat */
1170 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1173 /* We still don't have any sort of hardware state readout for FBC, so
1174 * deactivate it in case the BIOS activated it to make sure software
1175 * matches the hardware state. */
1176 if (fbc
->is_active(dev_priv
))
1177 fbc
->deactivate(dev_priv
);