2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include "intel_drv.h"
32 * DOC: fifo underrun handling
34 * The i915 driver checks for display fifo underruns using the interrupt signals
35 * provided by the hardware. This is enabled by default and fairly useful to
36 * debug display issues, especially watermark settings.
38 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
39 * and occupying the cpu underrun interrupts are disabled after the first
40 * occurrence until the next modeset on a given pipe.
42 * Note that underrun detection on gmch platforms is a bit more ugly since there
43 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
44 * interrupt register). Also on some other platforms underrun interrupts are
45 * shared, which means that if we detect an underrun we need to disable underrun
46 * reporting on all pipes.
48 * The code also supports underrun detection on the PCH transcoder.
51 static bool ivb_can_enable_err_int(struct drm_device
*dev
)
53 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
54 struct intel_crtc
*crtc
;
57 assert_spin_locked(&dev_priv
->irq_lock
);
59 for_each_pipe(dev_priv
, pipe
) {
60 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
62 if (crtc
->cpu_fifo_underrun_disabled
)
69 static bool cpt_can_enable_serr_int(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
73 struct intel_crtc
*crtc
;
75 assert_spin_locked(&dev_priv
->irq_lock
);
77 for_each_pipe(dev_priv
, pipe
) {
78 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
80 if (crtc
->pch_fifo_underrun_disabled
)
87 static void i9xx_check_fifo_underruns(struct intel_crtc
*crtc
)
89 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
90 i915_reg_t reg
= PIPESTAT(crtc
->pipe
);
91 u32 pipestat
= I915_READ(reg
) & 0xffff0000;
93 assert_spin_locked(&dev_priv
->irq_lock
);
95 if ((pipestat
& PIPE_FIFO_UNDERRUN_STATUS
) == 0)
98 I915_WRITE(reg
, pipestat
| PIPE_FIFO_UNDERRUN_STATUS
);
101 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc
->pipe
));
104 static void i9xx_set_fifo_underrun_reporting(struct drm_device
*dev
,
106 bool enable
, bool old
)
108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
109 i915_reg_t reg
= PIPESTAT(pipe
);
110 u32 pipestat
= I915_READ(reg
) & 0xffff0000;
112 assert_spin_locked(&dev_priv
->irq_lock
);
115 I915_WRITE(reg
, pipestat
| PIPE_FIFO_UNDERRUN_STATUS
);
118 if (old
&& pipestat
& PIPE_FIFO_UNDERRUN_STATUS
)
119 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe
));
123 static void ironlake_set_fifo_underrun_reporting(struct drm_device
*dev
,
124 enum pipe pipe
, bool enable
)
126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
127 uint32_t bit
= (pipe
== PIPE_A
) ? DE_PIPEA_FIFO_UNDERRUN
:
128 DE_PIPEB_FIFO_UNDERRUN
;
131 ilk_enable_display_irq(dev_priv
, bit
);
133 ilk_disable_display_irq(dev_priv
, bit
);
136 static void ivybridge_check_fifo_underruns(struct intel_crtc
*crtc
)
138 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
139 enum pipe pipe
= crtc
->pipe
;
140 uint32_t err_int
= I915_READ(GEN7_ERR_INT
);
142 assert_spin_locked(&dev_priv
->irq_lock
);
144 if ((err_int
& ERR_INT_FIFO_UNDERRUN(pipe
)) == 0)
147 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
148 POSTING_READ(GEN7_ERR_INT
);
150 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe
));
153 static void ivybridge_set_fifo_underrun_reporting(struct drm_device
*dev
,
155 bool enable
, bool old
)
157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
159 I915_WRITE(GEN7_ERR_INT
, ERR_INT_FIFO_UNDERRUN(pipe
));
161 if (!ivb_can_enable_err_int(dev
))
164 ilk_enable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
166 ilk_disable_display_irq(dev_priv
, DE_ERR_INT_IVB
);
169 I915_READ(GEN7_ERR_INT
) & ERR_INT_FIFO_UNDERRUN(pipe
)) {
170 DRM_ERROR("uncleared fifo underrun on pipe %c\n",
176 static void broadwell_set_fifo_underrun_reporting(struct drm_device
*dev
,
177 enum pipe pipe
, bool enable
)
179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
182 bdw_enable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_FIFO_UNDERRUN
);
184 bdw_disable_pipe_irq(dev_priv
, pipe
, GEN8_PIPE_FIFO_UNDERRUN
);
187 static void ibx_set_fifo_underrun_reporting(struct drm_device
*dev
,
188 enum transcoder pch_transcoder
,
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 uint32_t bit
= (pch_transcoder
== TRANSCODER_A
) ?
193 SDE_TRANSA_FIFO_UNDER
: SDE_TRANSB_FIFO_UNDER
;
196 ibx_enable_display_interrupt(dev_priv
, bit
);
198 ibx_disable_display_interrupt(dev_priv
, bit
);
201 static void cpt_check_pch_fifo_underruns(struct intel_crtc
*crtc
)
203 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
204 enum transcoder pch_transcoder
= (enum transcoder
) crtc
->pipe
;
205 uint32_t serr_int
= I915_READ(SERR_INT
);
207 assert_spin_locked(&dev_priv
->irq_lock
);
209 if ((serr_int
& SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
)) == 0)
212 I915_WRITE(SERR_INT
, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
213 POSTING_READ(SERR_INT
);
215 DRM_ERROR("pch fifo underrun on pch transcoder %s\n",
216 transcoder_name(pch_transcoder
));
219 static void cpt_set_fifo_underrun_reporting(struct drm_device
*dev
,
220 enum transcoder pch_transcoder
,
221 bool enable
, bool old
)
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
));
229 if (!cpt_can_enable_serr_int(dev
))
232 ibx_enable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
234 ibx_disable_display_interrupt(dev_priv
, SDE_ERROR_CPT
);
236 if (old
&& I915_READ(SERR_INT
) &
237 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder
)) {
238 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n",
239 transcoder_name(pch_transcoder
));
244 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device
*dev
,
245 enum pipe pipe
, bool enable
)
247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
248 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
252 assert_spin_locked(&dev_priv
->irq_lock
);
254 old
= !intel_crtc
->cpu_fifo_underrun_disabled
;
255 intel_crtc
->cpu_fifo_underrun_disabled
= !enable
;
257 if (HAS_GMCH_DISPLAY(dev
))
258 i9xx_set_fifo_underrun_reporting(dev
, pipe
, enable
, old
);
259 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
260 ironlake_set_fifo_underrun_reporting(dev
, pipe
, enable
);
261 else if (IS_GEN7(dev
))
262 ivybridge_set_fifo_underrun_reporting(dev
, pipe
, enable
, old
);
263 else if (IS_GEN8(dev
) || IS_GEN9(dev
))
264 broadwell_set_fifo_underrun_reporting(dev
, pipe
, enable
);
270 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
271 * @dev_priv: i915 device instance
272 * @pipe: (CPU) pipe to set state for
273 * @enable: whether underruns should be reported or not
275 * This function sets the fifo underrun state for @pipe. It is used in the
276 * modeset code to avoid false positives since on many platforms underruns are
277 * expected when disabling or enabling the pipe.
279 * Notice that on some platforms disabling underrun reports for one pipe
280 * disables for all due to shared interrupts. Actual reporting is still per-pipe
283 * Returns the previous state of underrun reporting.
285 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
286 enum pipe pipe
, bool enable
)
291 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
292 ret
= __intel_set_cpu_fifo_underrun_reporting(dev_priv
->dev
, pipe
,
294 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
300 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
301 * @dev_priv: i915 device instance
302 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
303 * @enable: whether underruns should be reported or not
305 * This function makes us disable or enable PCH fifo underruns for a specific
306 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
307 * underrun reporting for one transcoder may also disable all the other PCH
308 * error interruts for the other transcoders, due to the fact that there's just
309 * one interrupt mask/enable bit for all the transcoders.
311 * Returns the previous state of underrun reporting.
313 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private
*dev_priv
,
314 enum transcoder pch_transcoder
,
317 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pch_transcoder
];
318 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
323 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
324 * has only one pch transcoder A that all pipes can use. To avoid racy
325 * pch transcoder -> pipe lookups from interrupt code simply store the
326 * underrun statistics in crtc A. Since we never expose this anywhere
327 * nor use it outside of the fifo underrun code here using the "wrong"
328 * crtc on LPT won't cause issues.
331 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
333 old
= !intel_crtc
->pch_fifo_underrun_disabled
;
334 intel_crtc
->pch_fifo_underrun_disabled
= !enable
;
336 if (HAS_PCH_IBX(dev_priv
))
337 ibx_set_fifo_underrun_reporting(dev_priv
->dev
, pch_transcoder
,
340 cpt_set_fifo_underrun_reporting(dev_priv
->dev
, pch_transcoder
,
343 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
348 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
349 * @dev_priv: i915 device instance
350 * @pipe: (CPU) pipe to set state for
352 * This handles a CPU fifo underrun interrupt, generating an underrun warning
353 * into dmesg if underrun reporting is enabled and then disables the underrun
354 * interrupt to avoid an irq storm.
356 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
359 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
361 /* We may be called too early in init, thanks BIOS! */
365 /* GMCH can't disable fifo underruns, filter them. */
366 if (HAS_GMCH_DISPLAY(dev_priv
) &&
367 to_intel_crtc(crtc
)->cpu_fifo_underrun_disabled
)
370 if (intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false))
371 DRM_ERROR("CPU pipe %c FIFO underrun\n",
376 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
377 * @dev_priv: i915 device instance
378 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
380 * This handles a PCH fifo underrun interrupt, generating an underrun warning
381 * into dmesg if underrun reporting is enabled and then disables the underrun
382 * interrupt to avoid an irq storm.
384 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private
*dev_priv
,
385 enum transcoder pch_transcoder
)
387 if (intel_set_pch_fifo_underrun_reporting(dev_priv
, pch_transcoder
,
389 DRM_ERROR("PCH transcoder %s FIFO underrun\n",
390 transcoder_name(pch_transcoder
));
394 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
395 * @dev_priv: i915 device instance
397 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
398 * error interrupt may have been disabled, and so CPU fifo underruns won't
399 * necessarily raise an interrupt, and on GMCH platforms where underruns never
400 * raise an interrupt.
402 void intel_check_cpu_fifo_underruns(struct drm_i915_private
*dev_priv
)
404 struct intel_crtc
*crtc
;
406 spin_lock_irq(&dev_priv
->irq_lock
);
408 for_each_intel_crtc(dev_priv
->dev
, crtc
) {
409 if (crtc
->cpu_fifo_underrun_disabled
)
412 if (HAS_GMCH_DISPLAY(dev_priv
))
413 i9xx_check_fifo_underruns(crtc
);
414 else if (IS_GEN7(dev_priv
))
415 ivybridge_check_fifo_underruns(crtc
);
418 spin_unlock_irq(&dev_priv
->irq_lock
);
422 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
423 * @dev_priv: i915 device instance
425 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
426 * error interrupt may have been disabled, and so PCH fifo underruns won't
427 * necessarily raise an interrupt.
429 void intel_check_pch_fifo_underruns(struct drm_i915_private
*dev_priv
)
431 struct intel_crtc
*crtc
;
433 spin_lock_irq(&dev_priv
->irq_lock
);
435 for_each_intel_crtc(dev_priv
->dev
, crtc
) {
436 if (crtc
->pch_fifo_underrun_disabled
)
439 if (HAS_PCH_CPT(dev_priv
))
440 cpt_check_pch_fifo_underruns(crtc
);
443 spin_unlock_irq(&dev_priv
->irq_lock
);