2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 #ifndef _INTEL_GUC_FWIF_H
24 #define _INTEL_GUC_FWIF_H
27 * This file is partially autogenerated, although currently with some manual
28 * fixups afterwards. In future, it should be entirely autogenerated, in order
29 * to ensure that the definitions herein remain in sync with those used by the
32 * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
35 #define GFXCORE_FAMILY_GEN9 12
36 #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff
38 #define GUC_CTX_PRIORITY_KMD_HIGH 0
39 #define GUC_CTX_PRIORITY_HIGH 1
40 #define GUC_CTX_PRIORITY_KMD_NORMAL 2
41 #define GUC_CTX_PRIORITY_NORMAL 3
42 #define GUC_CTX_PRIORITY_NUM 4
44 #define GUC_MAX_GPU_CONTEXTS 1024
45 #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
47 #define GUC_RENDER_ENGINE 0
48 #define GUC_VIDEO_ENGINE 1
49 #define GUC_BLITTER_ENGINE 2
50 #define GUC_VIDEOENHANCE_ENGINE 3
51 #define GUC_VIDEO_ENGINE2 4
52 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
54 /* Work queue item header definitions */
55 #define WQ_STATUS_ACTIVE 1
56 #define WQ_STATUS_SUSPENDED 2
57 #define WQ_STATUS_CMD_ERROR 3
58 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
59 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
60 #define WQ_TYPE_SHIFT 0
61 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
62 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
63 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
64 #define WQ_TARGET_SHIFT 10
65 #define WQ_LEN_SHIFT 16
66 #define WQ_NO_WCFLUSH_WAIT (1 << 27)
67 #define WQ_PRESENT_WORKLOAD (1 << 28)
68 #define WQ_WORKLOAD_SHIFT 29
69 #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT)
70 #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT)
71 #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT)
73 #define WQ_RING_TAIL_SHIFT 20
74 #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT)
76 #define GUC_DOORBELL_ENABLED 1
77 #define GUC_DOORBELL_DISABLED 0
79 #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0)
80 #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1)
81 #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2)
82 #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3)
83 #define GUC_CTX_DESC_ATTR_RESET (1 << 4)
84 #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5)
85 #define GUC_CTX_DESC_ATTR_PCH (1 << 6)
86 #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7)
88 /* The guc control data is 10 DWORDs */
89 #define GUC_CTL_CTXINFO 0
90 #define GUC_CTL_CTXNUM_IN16_SHIFT 0
91 #define GUC_CTL_BASE_ADDR_SHIFT 12
93 #define GUC_CTL_ARAT_HIGH 1
94 #define GUC_CTL_ARAT_LOW 2
96 #define GUC_CTL_DEVICE_INFO 3
97 #define GUC_CTL_GTTYPE_SHIFT 0
98 #define GUC_CTL_COREFAMILY_SHIFT 7
100 #define GUC_CTL_LOG_PARAMS 4
101 #define GUC_LOG_VALID (1 << 0)
102 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
103 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
104 #define GUC_LOG_CRASH_PAGES 1
105 #define GUC_LOG_CRASH_SHIFT 4
106 #define GUC_LOG_DPC_PAGES 3
107 #define GUC_LOG_DPC_SHIFT 6
108 #define GUC_LOG_ISR_PAGES 3
109 #define GUC_LOG_ISR_SHIFT 9
110 #define GUC_LOG_BUF_ADDR_SHIFT 12
112 #define GUC_CTL_PAGE_FAULT_CONTROL 5
115 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
117 #define GUC_CTL_FEATURE 7
118 #define GUC_CTL_VCS2_ENABLED (1 << 0)
119 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
120 #define GUC_CTL_FEATURE2 (1 << 2)
121 #define GUC_CTL_POWER_GATING (1 << 3)
122 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
123 #define GUC_CTL_PREEMPTION_LOG (1 << 5)
124 #define GUC_CTL_ENABLE_SLPC (1 << 7)
125 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
127 #define GUC_CTL_DEBUG 8
128 #define GUC_LOG_VERBOSITY_SHIFT 0
129 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
130 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
131 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
132 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
133 /* Verbosity range-check limits, without the shift */
134 #define GUC_LOG_VERBOSITY_MIN 0
135 #define GUC_LOG_VERBOSITY_MAX 3
136 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
137 #define GUC_LOG_DESTINATION_MASK (3 << 4)
138 #define GUC_LOG_DISABLED (1 << 6)
139 #define GUC_PROFILE_ENABLED (1 << 7)
140 #define GUC_WQ_TRACK_ENABLED (1 << 8)
141 #define GUC_ADS_ENABLED (1 << 9)
142 #define GUC_DEBUG_RESERVED (1 << 10)
143 #define GUC_ADS_ADDR_SHIFT 11
144 #define GUC_ADS_ADDR_MASK 0xfffff800
146 #define GUC_CTL_RSRVD 9
148 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
151 * DOC: GuC Firmware Layout
153 * The GuC firmware layout looks like this:
155 * +-------------------------------+
157 * | contains major/minor version |
158 * +-------------------------------+
160 * +-------------------------------+
162 * +-------------------------------+
164 * +-------------------------------+
166 * +-------------------------------+
168 * The firmware may or may not have modulus key and exponent data. The header,
169 * uCode and RSA signature are must-have components that will be used by driver.
170 * Length of each components, which is all in dwords, can be found in header.
171 * In the case that modulus and exponent are not present in fw, a.k.a truncated
172 * image, the length value still appears in header.
174 * Driver will do some basic fw size validation based on the following rules:
176 * 1. Header, uCode and RSA are must-have components.
177 * 2. All firmware components, if they present, are in the sequence illustrated
178 * in the layout table above.
179 * 3. Length info of each component can be found in header, in dwords.
180 * 4. Modulus and exponent key are not required by driver. They may not appear
181 * in fw. So driver will load a truncated firmware in this case.
184 struct guc_css_header
{
185 uint32_t module_type
;
186 /* header_size includes all non-uCode bits, including css_header, rsa
187 * key, modulus key and exponent data. */
188 uint32_t header_size_dw
;
189 uint32_t header_version
;
191 uint32_t module_vendor
;
200 uint32_t size_dw
; /* uCode plus header_size_dw */
201 uint32_t key_size_dw
;
202 uint32_t modulus_size_dw
;
203 uint32_t exponent_size_dw
;
214 char buildnumber
[12];
216 uint32_t guc_sw_version
;
217 uint32_t prod_preprod_fw
;
218 uint32_t reserved
[12];
219 uint32_t header_info
;
222 struct guc_doorbell_info
{
228 union guc_doorbell_qw
{
236 #define GUC_MAX_DOORBELLS 256
237 #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS)
239 #define GUC_DB_SIZE (PAGE_SIZE)
240 #define GUC_WQ_SIZE (PAGE_SIZE * 2)
242 /* Work item for submitting workloads into work queue of GuC. */
250 struct guc_process_desc
{
264 /* engine id and context id is packed into guc_execlist_context.context_id*/
265 #define GUC_ELC_CTXID_OFFSET 0
266 #define GUC_ELC_ENGINE_OFFSET 29
268 /* The execlist context including software and HW information */
269 struct guc_execlist_context
{
276 u32 ring_next_free_location
;
277 u32 ring_current_tail_pointer_value
;
278 u8 engine_state_submit_value
;
279 u8 engine_state_wait_value
;
281 u16 engine_submit_queue_count
;
284 /*Context descriptor for communicating between uKernel and Driver*/
285 struct guc_context_desc
{
286 u32 sched_common_area
;
295 struct guc_execlist_context lrc
[GUC_MAX_ENGINES_NUM
];
301 u32 wq_sampled_tail_offset
;
302 u32 wq_total_submit_enqueues
;
318 #define GUC_FORCEWAKE_RENDER (1 << 0)
319 #define GUC_FORCEWAKE_MEDIA (1 << 1)
321 #define GUC_POWER_UNSPECIFIED 0
322 #define GUC_POWER_D0 1
323 #define GUC_POWER_D1 2
324 #define GUC_POWER_D2 3
325 #define GUC_POWER_D3 4
327 /* Scheduling policy settings */
329 /* Reset engine upon preempt failure */
330 #define POLICY_RESET_ENGINE (1<<0)
331 /* Preempt to idle on quantum expiry */
332 #define POLICY_PREEMPT_TO_IDLE (1<<1)
334 #define POLICY_MAX_NUM_WI 15
337 /* Time for one workload to execute. (in micro seconds) */
338 u32 execution_quantum
;
341 /* Time to wait for a preemption request to completed before issuing a
342 * reset. (in micro seconds). */
345 /* How much time to allow to run after the first fault is observed.
346 * Then preempt afterwards. (in micro seconds) */
353 struct guc_policies
{
354 struct guc_policy policy
[GUC_CTX_PRIORITY_NUM
][GUC_MAX_ENGINES_NUM
];
356 /* In micro seconds. How much time to allow before DPC processing is
357 * called back via interrupt (to prevent DPC queue drain starving).
358 * Typically 1000s of micro seconds (example only, not granularity). */
359 u32 dpc_promote_time
;
361 /* Must be set to take these new values. */
364 /* Max number of WIs to process per call. A large value may keep CS
366 u32 max_num_work_items
;
371 /* GuC MMIO reg state struct */
373 #define GUC_REGSET_FLAGS_NONE 0x0
374 #define GUC_REGSET_POWERCYCLE 0x1
375 #define GUC_REGSET_MASKED 0x2
376 #define GUC_REGSET_ENGINERESET 0x4
377 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
378 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
380 #define GUC_REGSET_MAX_REGISTERS 25
381 #define GUC_MMIO_WHITE_LIST_START 0x24d0
382 #define GUC_MMIO_WHITE_LIST_MAX 12
383 #define GUC_S3_SAVE_SPACE_PAGES 10
385 struct guc_mmio_regset
{
390 } registers
[GUC_REGSET_MAX_REGISTERS
];
393 u32 number_of_registers
;
396 struct guc_mmio_reg_state
{
397 struct guc_mmio_regset global_reg
;
398 struct guc_mmio_regset engine_reg
[GUC_MAX_ENGINES_NUM
];
400 /* MMIO registers that are set as non privileged */
403 u32 offsets
[GUC_MMIO_WHITE_LIST_MAX
];
405 } mmio_white_list
[GUC_MAX_ENGINES_NUM
];
408 /* GuC Additional Data Struct */
412 u32 reg_state_buffer
;
413 u32 golden_context_lrca
;
414 u32 scheduler_policies
;
416 u32 eng_state_size
[GUC_MAX_ENGINES_NUM
];
420 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
421 enum host2guc_action
{
422 HOST2GUC_ACTION_DEFAULT
= 0x0,
423 HOST2GUC_ACTION_SAMPLE_FORCEWAKE
= 0x6,
424 HOST2GUC_ACTION_ALLOCATE_DOORBELL
= 0x10,
425 HOST2GUC_ACTION_DEALLOCATE_DOORBELL
= 0x20,
426 HOST2GUC_ACTION_ENTER_S_STATE
= 0x501,
427 HOST2GUC_ACTION_EXIT_S_STATE
= 0x502,
428 HOST2GUC_ACTION_SLPC_REQUEST
= 0x3003,
429 HOST2GUC_ACTION_LIMIT
433 * The GuC sends its response to a command by overwriting the
434 * command in SS0. The response is distinguishable from a command
435 * by the fact that all the MASK bits are set. The remaining bits
438 #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000)
439 #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK)
440 #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x))
442 /* GUC will return status back to SOFT_SCRATCH_O_REG */
443 enum guc2host_status
{
444 GUC2HOST_STATUS_SUCCESS
= GUC2HOST_STATUS(0x0),
445 GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL
= GUC2HOST_STATUS(0x10),
446 GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL
= GUC2HOST_STATUS(0x20),
447 GUC2HOST_STATUS_GENERIC_FAIL
= GUC2HOST_STATUS(0x0000F000)