2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
29 #include <linux/firmware.h>
31 #include "intel_guc.h"
34 * DOC: GuC-specific firmware loader
37 * Top level structure of guc. It handles firmware loading and manages client
38 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
39 * ExecList submission.
41 * Firmware versioning:
42 * The firmware build process will generate a version header file with major and
43 * minor version defined. The versions are built into CSS header of firmware.
44 * i915 kernel driver set the minimal firmware version required per platform.
45 * The firmware installation package will install (symbolic link) proper version
49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
50 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
52 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
55 * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
56 * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
57 * i915_guc_load_status will print out firmware loading status and scratch
62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6.bin"
63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE
);
65 /* User-friendly representation of an enum */
66 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status
)
69 case GUC_FIRMWARE_FAIL
:
71 case GUC_FIRMWARE_NONE
:
73 case GUC_FIRMWARE_PENDING
:
75 case GUC_FIRMWARE_SUCCESS
:
82 static void direct_interrupts_to_host(struct drm_i915_private
*dev_priv
)
84 struct intel_engine_cs
*engine
;
87 /* tell all command streamers NOT to forward interrupts and vblank to GuC */
88 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
89 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
90 for_each_engine(engine
, dev_priv
)
91 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
93 /* route all GT interrupts to the host */
94 I915_WRITE(GUC_BCS_RCS_IER
, 0);
95 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
96 I915_WRITE(GUC_WD_VECS_IER
, 0);
99 static void direct_interrupts_to_guc(struct drm_i915_private
*dev_priv
)
101 struct intel_engine_cs
*engine
;
104 /* tell all command streamers to forward interrupts and vblank to GuC */
105 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_ALWAYS
);
106 irqs
|= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
107 for_each_engine(engine
, dev_priv
)
108 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
110 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
111 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
112 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
113 /* These three registers have the same bit definitions */
114 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
115 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
116 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
119 static u32
get_gttype(struct drm_i915_private
*dev_priv
)
121 /* XXX: GT type based on PCI device ID? field seems unused by fw */
125 static u32
get_core_family(struct drm_i915_private
*dev_priv
)
127 switch (INTEL_INFO(dev_priv
)->gen
) {
129 return GFXCORE_FAMILY_GEN9
;
132 DRM_ERROR("GUC: unsupported core family\n");
133 return GFXCORE_FAMILY_UNKNOWN
;
137 static void set_guc_init_params(struct drm_i915_private
*dev_priv
)
139 struct intel_guc
*guc
= &dev_priv
->guc
;
140 u32 params
[GUC_CTL_MAX_DWORDS
];
143 memset(¶ms
, 0, sizeof(params
));
145 params
[GUC_CTL_DEVICE_INFO
] |=
146 (get_gttype(dev_priv
) << GUC_CTL_GTTYPE_SHIFT
) |
147 (get_core_family(dev_priv
) << GUC_CTL_COREFAMILY_SHIFT
);
150 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
151 * second. This ARAR is calculated by:
152 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
154 params
[GUC_CTL_ARAT_HIGH
] = 0;
155 params
[GUC_CTL_ARAT_LOW
] = 100000000;
157 params
[GUC_CTL_WA
] |= GUC_CTL_WA_UK_BY_DRIVER
;
159 params
[GUC_CTL_FEATURE
] |= GUC_CTL_DISABLE_SCHEDULER
|
160 GUC_CTL_VCS2_ENABLED
;
162 if (i915
.guc_log_level
>= 0) {
163 params
[GUC_CTL_LOG_PARAMS
] = guc
->log_flags
;
164 params
[GUC_CTL_DEBUG
] =
165 i915
.guc_log_level
<< GUC_LOG_VERBOSITY_SHIFT
;
169 u32 ads
= (u32
)i915_gem_obj_ggtt_offset(guc
->ads_obj
)
171 params
[GUC_CTL_DEBUG
] |= ads
<< GUC_ADS_ADDR_SHIFT
;
172 params
[GUC_CTL_DEBUG
] |= GUC_ADS_ENABLED
;
175 /* If GuC submission is enabled, set up additional parameters here */
176 if (i915
.enable_guc_submission
) {
177 u32 pgs
= i915_gem_obj_ggtt_offset(dev_priv
->guc
.ctx_pool_obj
);
178 u32 ctx_in_16
= GUC_MAX_GPU_CONTEXTS
/ 16;
181 params
[GUC_CTL_CTXINFO
] = (pgs
<< GUC_CTL_BASE_ADDR_SHIFT
) |
182 (ctx_in_16
<< GUC_CTL_CTXNUM_IN16_SHIFT
);
184 params
[GUC_CTL_FEATURE
] |= GUC_CTL_KERNEL_SUBMISSIONS
;
186 /* Unmask this bit to enable the GuC's internal scheduler */
187 params
[GUC_CTL_FEATURE
] &= ~GUC_CTL_DISABLE_SCHEDULER
;
190 I915_WRITE(SOFT_SCRATCH(0), 0);
192 for (i
= 0; i
< GUC_CTL_MAX_DWORDS
; i
++)
193 I915_WRITE(SOFT_SCRATCH(1 + i
), params
[i
]);
197 * Read the GuC status register (GUC_STATUS) and store it in the
198 * specified location; then return a boolean indicating whether
199 * the value matches either of two values representing completion
200 * of the GuC boot process.
202 * This is used for polling the GuC status in a wait_for()
205 static inline bool guc_ucode_response(struct drm_i915_private
*dev_priv
,
208 u32 val
= I915_READ(GUC_STATUS
);
209 u32 uk_val
= val
& GS_UKERNEL_MASK
;
211 return (uk_val
== GS_UKERNEL_READY
||
212 ((val
& GS_MIA_CORE_STATE
) && uk_val
== GS_UKERNEL_LAPIC_DONE
));
216 * Transfer the firmware image to RAM for execution by the microcontroller.
218 * Architecturally, the DMA engine is bidirectional, and can potentially even
219 * transfer between GTT locations. This functionality is left out of the API
220 * for now as there is no need for it.
222 * Note that GuC needs the CSS header plus uKernel code to be copied by the
223 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
225 static int guc_ucode_xfer_dma(struct drm_i915_private
*dev_priv
)
227 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
228 struct drm_i915_gem_object
*fw_obj
= guc_fw
->guc_fw_obj
;
229 unsigned long offset
;
230 struct sg_table
*sg
= fw_obj
->pages
;
231 u32 status
, rsa
[UOS_RSA_SCRATCH_MAX_COUNT
];
234 /* where RSA signature starts */
235 offset
= guc_fw
->rsa_offset
;
237 /* Copy RSA signature from the fw image to HW for verification */
238 sg_pcopy_to_buffer(sg
->sgl
, sg
->nents
, rsa
, sizeof(rsa
), offset
);
239 for (i
= 0; i
< UOS_RSA_SCRATCH_MAX_COUNT
; i
++)
240 I915_WRITE(UOS_RSA_SCRATCH(i
), rsa
[i
]);
242 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
243 * other components */
244 I915_WRITE(DMA_COPY_SIZE
, guc_fw
->header_size
+ guc_fw
->ucode_size
);
246 /* Set the source address for the new blob */
247 offset
= i915_gem_obj_ggtt_offset(fw_obj
) + guc_fw
->header_offset
;
248 I915_WRITE(DMA_ADDR_0_LOW
, lower_32_bits(offset
));
249 I915_WRITE(DMA_ADDR_0_HIGH
, upper_32_bits(offset
) & 0xFFFF);
252 * Set the DMA destination. Current uCode expects the code to be
253 * loaded at 8k; locations below this are used for the stack.
255 I915_WRITE(DMA_ADDR_1_LOW
, 0x2000);
256 I915_WRITE(DMA_ADDR_1_HIGH
, DMA_ADDRESS_SPACE_WOPCM
);
258 /* Finally start the DMA */
259 I915_WRITE(DMA_CTRL
, _MASKED_BIT_ENABLE(UOS_MOVE
| START_DMA
));
262 * Wait for the DMA to complete & the GuC to start up.
263 * NB: Docs recommend not using the interrupt for completion.
264 * Measurements indicate this should take no more than 20ms, so a
265 * timeout here indicates that the GuC has failed and is unusable.
266 * (Higher levels of the driver will attempt to fall back to
267 * execlist mode if this happens.)
269 ret
= wait_for(guc_ucode_response(dev_priv
, &status
), 100);
271 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
272 I915_READ(DMA_CTRL
), status
);
274 if ((status
& GS_BOOTROM_MASK
) == GS_BOOTROM_RSA_FAILED
) {
275 DRM_ERROR("GuC firmware signature verification failed\n");
279 DRM_DEBUG_DRIVER("returning %d\n", ret
);
285 * Load the GuC firmware blob into the MinuteIA.
287 static int guc_ucode_xfer(struct drm_i915_private
*dev_priv
)
289 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
290 struct drm_device
*dev
= dev_priv
->dev
;
293 ret
= i915_gem_object_set_to_gtt_domain(guc_fw
->guc_fw_obj
, false);
295 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret
);
299 ret
= i915_gem_obj_ggtt_pin(guc_fw
->guc_fw_obj
, 0, 0);
301 DRM_DEBUG_DRIVER("pin failed %d\n", ret
);
305 /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
306 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
308 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
311 I915_WRITE(GUC_WOPCM_SIZE
, GUC_WOPCM_SIZE_VALUE
);
312 I915_WRITE(DMA_GUC_WOPCM_OFFSET
, GUC_WOPCM_OFFSET_VALUE
);
314 /* Enable MIA caching. GuC clock gating is disabled. */
315 I915_WRITE(GUC_SHIM_CONTROL
, GUC_SHIM_CONTROL_VALUE
);
317 /* WaDisableMinuteIaClockGating:skl,bxt */
318 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
319 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
320 I915_WRITE(GUC_SHIM_CONTROL
, (I915_READ(GUC_SHIM_CONTROL
) &
321 ~GUC_ENABLE_MIA_CLOCK_GATING
));
324 /* WaC6DisallowByGfxPause*/
325 I915_WRITE(GEN6_GFXPAUSE
, 0x30FFF);
328 I915_WRITE(GEN9LP_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
330 I915_WRITE(GEN9_GT_PM_CONFIG
, GT_DOORBELL_ENABLE
);
333 /* DOP Clock Gating Enable for GuC clocks */
334 I915_WRITE(GEN7_MISCCPCTL
, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE
|
335 I915_READ(GEN7_MISCCPCTL
)));
337 /* allows for 5us before GT can go to RC6 */
338 I915_WRITE(GUC_ARAT_C6DIS
, 0x1FF);
341 set_guc_init_params(dev_priv
);
343 ret
= guc_ucode_xfer_dma(dev_priv
);
345 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
348 * We keep the object pages for reuse during resume. But we can unpin it
349 * now that DMA has completed, so it doesn't continue to take up space.
351 i915_gem_object_ggtt_unpin(guc_fw
->guc_fw_obj
);
356 static int i915_reset_guc(struct drm_i915_private
*dev_priv
)
361 ret
= intel_guc_reset(dev_priv
);
363 DRM_ERROR("GuC reset failed, ret = %d\n", ret
);
367 guc_status
= I915_READ(GUC_STATUS
);
368 WARN(!(guc_status
& GS_MIA_IN_RESET
),
369 "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status
);
375 * intel_guc_ucode_load() - load GuC uCode into the device
378 * Called from gem_init_hw() during driver loading and also after a GPU reset.
380 * The firmware image should have already been fetched into memory by the
381 * earlier call to intel_guc_ucode_init(), so here we need only check that
382 * is succeeded, and then transfer the image to the h/w.
384 * Return: non-zero code on error
386 int intel_guc_ucode_load(struct drm_device
*dev
)
388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
389 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
390 int retries
, err
= 0;
392 if (!i915
.enable_guc_submission
)
395 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
396 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
397 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
399 direct_interrupts_to_host(dev_priv
);
401 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_NONE
)
404 if (guc_fw
->guc_fw_fetch_status
== GUC_FIRMWARE_SUCCESS
&&
405 guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_FAIL
)
408 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_PENDING
;
410 DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
411 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
413 switch (guc_fw
->guc_fw_fetch_status
) {
414 case GUC_FIRMWARE_FAIL
:
415 /* something went wrong :( */
419 case GUC_FIRMWARE_NONE
:
420 case GUC_FIRMWARE_PENDING
:
423 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
425 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
426 guc_fw
->guc_fw_fetch_status
);
430 case GUC_FIRMWARE_SUCCESS
:
434 err
= i915_guc_submission_init(dev
);
439 * WaEnableuKernelHeaderValidFix:skl,bxt
440 * For BXT, this is only upto B0 but below WA is required for later
441 * steppings also so this is extended as well.
443 /* WaEnableGuCBootHashCheckNotSet:skl,bxt */
444 for (retries
= 3; ; ) {
446 * Always reset the GuC just before (re)loading, so
447 * that the state and timing are fairly predictable
449 err
= i915_reset_guc(dev_priv
);
451 DRM_ERROR("GuC reset failed, err %d\n", err
);
455 err
= guc_ucode_xfer(dev_priv
);
462 DRM_INFO("GuC fw load failed, err %d; will reset and "
463 "retry %d more time(s)\n", err
, retries
);
466 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_SUCCESS
;
468 DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
469 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
),
470 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
472 if (i915
.enable_guc_submission
) {
473 /* The execbuf_client will be recreated. Release it first. */
474 i915_guc_submission_disable(dev
);
476 err
= i915_guc_submission_enable(dev
);
479 direct_interrupts_to_guc(dev_priv
);
485 DRM_ERROR("GuC firmware load failed, err %d\n", err
);
486 if (guc_fw
->guc_fw_load_status
== GUC_FIRMWARE_PENDING
)
487 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_FAIL
;
489 direct_interrupts_to_host(dev_priv
);
490 i915_guc_submission_disable(dev
);
491 i915_guc_submission_fini(dev
);
496 static void guc_fw_fetch(struct drm_device
*dev
, struct intel_guc_fw
*guc_fw
)
498 struct drm_i915_gem_object
*obj
;
499 const struct firmware
*fw
;
500 struct guc_css_header
*css
;
504 DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
505 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
507 err
= request_firmware(&fw
, guc_fw
->guc_fw_path
, &dev
->pdev
->dev
);
513 DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
514 guc_fw
->guc_fw_path
, fw
);
516 /* Check the size of the blob before examining buffer contents */
517 if (fw
->size
< sizeof(struct guc_css_header
)) {
518 DRM_ERROR("Firmware header is missing\n");
522 css
= (struct guc_css_header
*)fw
->data
;
524 /* Firmware bits always start from header */
525 guc_fw
->header_offset
= 0;
526 guc_fw
->header_size
= (css
->header_size_dw
- css
->modulus_size_dw
-
527 css
->key_size_dw
- css
->exponent_size_dw
) * sizeof(u32
);
529 if (guc_fw
->header_size
!= sizeof(struct guc_css_header
)) {
530 DRM_ERROR("CSS header definition mismatch\n");
535 guc_fw
->ucode_offset
= guc_fw
->header_offset
+ guc_fw
->header_size
;
536 guc_fw
->ucode_size
= (css
->size_dw
- css
->header_size_dw
) * sizeof(u32
);
539 if (css
->key_size_dw
!= UOS_RSA_SCRATCH_MAX_COUNT
) {
540 DRM_ERROR("RSA key size is bad\n");
543 guc_fw
->rsa_offset
= guc_fw
->ucode_offset
+ guc_fw
->ucode_size
;
544 guc_fw
->rsa_size
= css
->key_size_dw
* sizeof(u32
);
546 /* At least, it should have header, uCode and RSA. Size of all three. */
547 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
+ guc_fw
->rsa_size
;
548 if (fw
->size
< size
) {
549 DRM_ERROR("Missing firmware components\n");
553 /* Header and uCode will be loaded to WOPCM. Size of the two. */
554 size
= guc_fw
->header_size
+ guc_fw
->ucode_size
;
556 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
557 if (size
> GUC_WOPCM_SIZE_VALUE
- 0x8000) {
558 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
563 * The GuC firmware image has the version number embedded at a well-known
564 * offset within the firmware blob; note that major / minor version are
565 * TWO bytes each (i.e. u16), although all pointers and offsets are defined
566 * in terms of bytes (u8).
568 guc_fw
->guc_fw_major_found
= css
->guc_sw_version
>> 16;
569 guc_fw
->guc_fw_minor_found
= css
->guc_sw_version
& 0xFFFF;
571 if (guc_fw
->guc_fw_major_found
!= guc_fw
->guc_fw_major_wanted
||
572 guc_fw
->guc_fw_minor_found
< guc_fw
->guc_fw_minor_wanted
) {
573 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
574 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
575 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
580 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
581 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
,
582 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
584 mutex_lock(&dev
->struct_mutex
);
585 obj
= i915_gem_object_create_from_data(dev
, fw
->data
, fw
->size
);
586 mutex_unlock(&dev
->struct_mutex
);
587 if (IS_ERR_OR_NULL(obj
)) {
588 err
= obj
? PTR_ERR(obj
) : -ENOMEM
;
592 guc_fw
->guc_fw_obj
= obj
;
593 guc_fw
->guc_fw_size
= fw
->size
;
595 DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
598 release_firmware(fw
);
599 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_SUCCESS
;
603 DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
604 err
, fw
, guc_fw
->guc_fw_obj
);
605 DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
606 guc_fw
->guc_fw_path
, err
);
608 mutex_lock(&dev
->struct_mutex
);
609 obj
= guc_fw
->guc_fw_obj
;
611 drm_gem_object_unreference(&obj
->base
);
612 guc_fw
->guc_fw_obj
= NULL
;
613 mutex_unlock(&dev
->struct_mutex
);
615 release_firmware(fw
); /* OK even if fw is NULL */
616 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
620 * intel_guc_ucode_init() - define parameters and fetch firmware
623 * Called early during driver load, but after GEM is initialised.
625 * The firmware will be transferred to the GuC's memory later,
626 * when intel_guc_ucode_load() is called.
628 void intel_guc_ucode_init(struct drm_device
*dev
)
630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
631 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
634 if (!HAS_GUC_SCHED(dev
))
635 i915
.enable_guc_submission
= false;
637 if (!HAS_GUC_UCODE(dev
)) {
639 } else if (IS_SKYLAKE(dev
)) {
640 fw_path
= I915_SKL_GUC_UCODE
;
641 guc_fw
->guc_fw_major_wanted
= 6;
642 guc_fw
->guc_fw_minor_wanted
= 1;
644 i915
.enable_guc_submission
= false;
645 fw_path
= ""; /* unknown device */
648 if (!i915
.enable_guc_submission
)
651 guc_fw
->guc_dev
= dev
;
652 guc_fw
->guc_fw_path
= fw_path
;
653 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;
654 guc_fw
->guc_fw_load_status
= GUC_FIRMWARE_NONE
;
659 if (*fw_path
== '\0') {
660 DRM_ERROR("No GuC firmware known for this platform\n");
661 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_FAIL
;
665 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_PENDING
;
666 DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path
);
667 guc_fw_fetch(dev
, guc_fw
);
668 /* status must now be FAIL or SUCCESS */
672 * intel_guc_ucode_fini() - clean up all allocated resources
675 void intel_guc_ucode_fini(struct drm_device
*dev
)
677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
678 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
680 mutex_lock(&dev
->struct_mutex
);
681 direct_interrupts_to_host(dev_priv
);
682 i915_guc_submission_disable(dev
);
683 i915_guc_submission_fini(dev
);
685 if (guc_fw
->guc_fw_obj
)
686 drm_gem_object_unreference(&guc_fw
->guc_fw_obj
->base
);
687 guc_fw
->guc_fw_obj
= NULL
;
688 mutex_unlock(&dev
->struct_mutex
);
690 guc_fw
->guc_fw_fetch_status
= GUC_FIRMWARE_NONE
;