2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
41 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
45 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
47 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
48 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
49 uint32_t enabled_bits
;
51 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
53 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
54 "HDMI port enabled, expecting disabled\n");
57 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
59 struct intel_digital_port
*intel_dig_port
=
60 container_of(encoder
, struct intel_digital_port
, base
.base
);
61 return &intel_dig_port
->hdmi
;
64 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
66 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
69 void intel_dip_infoframe_csum(struct dip_infoframe
*frame
)
71 uint8_t *data
= (uint8_t *)frame
;
78 for (i
= 0; i
< frame
->len
+ DIP_HEADER_SIZE
; i
++)
81 frame
->checksum
= 0x100 - sum
;
84 static u32
g4x_infoframe_index(struct dip_infoframe
*frame
)
86 switch (frame
->type
) {
88 return VIDEO_DIP_SELECT_AVI
;
90 return VIDEO_DIP_SELECT_SPD
;
92 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
97 static u32
g4x_infoframe_enable(struct dip_infoframe
*frame
)
99 switch (frame
->type
) {
101 return VIDEO_DIP_ENABLE_AVI
;
103 return VIDEO_DIP_ENABLE_SPD
;
105 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
110 static u32
hsw_infoframe_enable(struct dip_infoframe
*frame
)
112 switch (frame
->type
) {
114 return VIDEO_DIP_ENABLE_AVI_HSW
;
116 return VIDEO_DIP_ENABLE_SPD_HSW
;
118 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
123 static u32
hsw_infoframe_data_reg(struct dip_infoframe
*frame
,
124 enum transcoder cpu_transcoder
)
126 switch (frame
->type
) {
128 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
130 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
132 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
137 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
138 struct dip_infoframe
*frame
)
140 uint32_t *data
= (uint32_t *)frame
;
141 struct drm_device
*dev
= encoder
->dev
;
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 u32 val
= I915_READ(VIDEO_DIP_CTL
);
144 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
146 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
148 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
149 val
|= g4x_infoframe_index(frame
);
151 val
&= ~g4x_infoframe_enable(frame
);
153 I915_WRITE(VIDEO_DIP_CTL
, val
);
156 for (i
= 0; i
< len
; i
+= 4) {
157 I915_WRITE(VIDEO_DIP_DATA
, *data
);
160 /* Write every possible data byte to force correct ECC calculation. */
161 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
162 I915_WRITE(VIDEO_DIP_DATA
, 0);
165 val
|= g4x_infoframe_enable(frame
);
166 val
&= ~VIDEO_DIP_FREQ_MASK
;
167 val
|= VIDEO_DIP_FREQ_VSYNC
;
169 I915_WRITE(VIDEO_DIP_CTL
, val
);
170 POSTING_READ(VIDEO_DIP_CTL
);
173 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
174 struct dip_infoframe
*frame
)
176 uint32_t *data
= (uint32_t *)frame
;
177 struct drm_device
*dev
= encoder
->dev
;
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
179 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
180 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
181 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
182 u32 val
= I915_READ(reg
);
184 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
186 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
187 val
|= g4x_infoframe_index(frame
);
189 val
&= ~g4x_infoframe_enable(frame
);
191 I915_WRITE(reg
, val
);
194 for (i
= 0; i
< len
; i
+= 4) {
195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
198 /* Write every possible data byte to force correct ECC calculation. */
199 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
200 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
203 val
|= g4x_infoframe_enable(frame
);
204 val
&= ~VIDEO_DIP_FREQ_MASK
;
205 val
|= VIDEO_DIP_FREQ_VSYNC
;
207 I915_WRITE(reg
, val
);
211 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
212 struct dip_infoframe
*frame
)
214 uint32_t *data
= (uint32_t *)frame
;
215 struct drm_device
*dev
= encoder
->dev
;
216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
217 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
218 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
219 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
220 u32 val
= I915_READ(reg
);
222 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
224 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
225 val
|= g4x_infoframe_index(frame
);
227 /* The DIP control register spec says that we need to update the AVI
228 * infoframe without clearing its enable bit */
229 if (frame
->type
!= DIP_TYPE_AVI
)
230 val
&= ~g4x_infoframe_enable(frame
);
232 I915_WRITE(reg
, val
);
235 for (i
= 0; i
< len
; i
+= 4) {
236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
239 /* Write every possible data byte to force correct ECC calculation. */
240 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
241 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
244 val
|= g4x_infoframe_enable(frame
);
245 val
&= ~VIDEO_DIP_FREQ_MASK
;
246 val
|= VIDEO_DIP_FREQ_VSYNC
;
248 I915_WRITE(reg
, val
);
252 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
253 struct dip_infoframe
*frame
)
255 uint32_t *data
= (uint32_t *)frame
;
256 struct drm_device
*dev
= encoder
->dev
;
257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
259 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
260 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
261 u32 val
= I915_READ(reg
);
263 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
265 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
266 val
|= g4x_infoframe_index(frame
);
268 val
&= ~g4x_infoframe_enable(frame
);
270 I915_WRITE(reg
, val
);
273 for (i
= 0; i
< len
; i
+= 4) {
274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
279 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
282 val
|= g4x_infoframe_enable(frame
);
283 val
&= ~VIDEO_DIP_FREQ_MASK
;
284 val
|= VIDEO_DIP_FREQ_VSYNC
;
286 I915_WRITE(reg
, val
);
290 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
291 struct dip_infoframe
*frame
)
293 uint32_t *data
= (uint32_t *)frame
;
294 struct drm_device
*dev
= encoder
->dev
;
295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
296 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
297 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
298 u32 data_reg
= hsw_infoframe_data_reg(frame
, intel_crtc
->config
.cpu_transcoder
);
299 unsigned int i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
300 u32 val
= I915_READ(ctl_reg
);
305 val
&= ~hsw_infoframe_enable(frame
);
306 I915_WRITE(ctl_reg
, val
);
309 for (i
= 0; i
< len
; i
+= 4) {
310 I915_WRITE(data_reg
+ i
, *data
);
313 /* Write every possible data byte to force correct ECC calculation. */
314 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
315 I915_WRITE(data_reg
+ i
, 0);
318 val
|= hsw_infoframe_enable(frame
);
319 I915_WRITE(ctl_reg
, val
);
320 POSTING_READ(ctl_reg
);
323 static void intel_set_infoframe(struct drm_encoder
*encoder
,
324 struct dip_infoframe
*frame
)
326 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
328 intel_dip_infoframe_csum(frame
);
329 intel_hdmi
->write_infoframe(encoder
, frame
);
332 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
333 struct drm_display_mode
*adjusted_mode
)
335 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
336 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
337 struct dip_infoframe avi_if
= {
338 .type
= DIP_TYPE_AVI
,
339 .ver
= DIP_VERSION_AVI
,
343 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
344 avi_if
.body
.avi
.YQ_CN_PR
|= DIP_AVI_PR_2
;
346 if (intel_hdmi
->rgb_quant_range_selectable
) {
347 if (intel_crtc
->config
.limited_color_range
)
348 avi_if
.body
.avi
.ITC_EC_Q_SC
|= DIP_AVI_RGB_QUANT_RANGE_LIMITED
;
350 avi_if
.body
.avi
.ITC_EC_Q_SC
|= DIP_AVI_RGB_QUANT_RANGE_FULL
;
353 avi_if
.body
.avi
.VIC
= drm_match_cea_mode(adjusted_mode
);
355 intel_set_infoframe(encoder
, &avi_if
);
358 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
360 struct dip_infoframe spd_if
;
362 memset(&spd_if
, 0, sizeof(spd_if
));
363 spd_if
.type
= DIP_TYPE_SPD
;
364 spd_if
.ver
= DIP_VERSION_SPD
;
365 spd_if
.len
= DIP_LEN_SPD
;
366 strcpy(spd_if
.body
.spd
.vn
, "Intel");
367 strcpy(spd_if
.body
.spd
.pd
, "Integrated gfx");
368 spd_if
.body
.spd
.sdi
= DIP_SPD_PC
;
370 intel_set_infoframe(encoder
, &spd_if
);
373 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
374 struct drm_display_mode
*adjusted_mode
)
376 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
377 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
378 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
379 u32 reg
= VIDEO_DIP_CTL
;
380 u32 val
= I915_READ(reg
);
383 assert_hdmi_port_disabled(intel_hdmi
);
385 /* If the registers were not initialized yet, they might be zeroes,
386 * which means we're selecting the AVI DIP and we're setting its
387 * frequency to once. This seems to really confuse the HW and make
388 * things stop working (the register spec says the AVI always needs to
389 * be sent every VSync). So here we avoid writing to the register more
390 * than we need and also explicitly select the AVI DIP and explicitly
391 * set its frequency to every VSync. Avoiding to write it twice seems to
392 * be enough to solve the problem, but being defensive shouldn't hurt us
394 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
396 if (!intel_hdmi
->has_hdmi_sink
) {
397 if (!(val
& VIDEO_DIP_ENABLE
))
399 val
&= ~VIDEO_DIP_ENABLE
;
400 I915_WRITE(reg
, val
);
405 switch (intel_dig_port
->port
) {
407 port
= VIDEO_DIP_PORT_B
;
410 port
= VIDEO_DIP_PORT_C
;
417 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
418 if (val
& VIDEO_DIP_ENABLE
) {
419 val
&= ~VIDEO_DIP_ENABLE
;
420 I915_WRITE(reg
, val
);
423 val
&= ~VIDEO_DIP_PORT_MASK
;
427 val
|= VIDEO_DIP_ENABLE
;
428 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
430 I915_WRITE(reg
, val
);
433 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
434 intel_hdmi_set_spd_infoframe(encoder
);
437 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
438 struct drm_display_mode
*adjusted_mode
)
440 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
441 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
442 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
443 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
444 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
445 u32 val
= I915_READ(reg
);
448 assert_hdmi_port_disabled(intel_hdmi
);
450 /* See the big comment in g4x_set_infoframes() */
451 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
453 if (!intel_hdmi
->has_hdmi_sink
) {
454 if (!(val
& VIDEO_DIP_ENABLE
))
456 val
&= ~VIDEO_DIP_ENABLE
;
457 I915_WRITE(reg
, val
);
462 switch (intel_dig_port
->port
) {
464 port
= VIDEO_DIP_PORT_B
;
467 port
= VIDEO_DIP_PORT_C
;
470 port
= VIDEO_DIP_PORT_D
;
477 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
478 if (val
& VIDEO_DIP_ENABLE
) {
479 val
&= ~VIDEO_DIP_ENABLE
;
480 I915_WRITE(reg
, val
);
483 val
&= ~VIDEO_DIP_PORT_MASK
;
487 val
|= VIDEO_DIP_ENABLE
;
488 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
489 VIDEO_DIP_ENABLE_GCP
);
491 I915_WRITE(reg
, val
);
494 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
495 intel_hdmi_set_spd_infoframe(encoder
);
498 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
499 struct drm_display_mode
*adjusted_mode
)
501 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
502 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
503 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
504 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
505 u32 val
= I915_READ(reg
);
507 assert_hdmi_port_disabled(intel_hdmi
);
509 /* See the big comment in g4x_set_infoframes() */
510 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
512 if (!intel_hdmi
->has_hdmi_sink
) {
513 if (!(val
& VIDEO_DIP_ENABLE
))
515 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
516 I915_WRITE(reg
, val
);
521 /* Set both together, unset both together: see the spec. */
522 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
523 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
524 VIDEO_DIP_ENABLE_GCP
);
526 I915_WRITE(reg
, val
);
529 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
530 intel_hdmi_set_spd_infoframe(encoder
);
533 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
534 struct drm_display_mode
*adjusted_mode
)
536 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
537 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
538 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
539 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
540 u32 val
= I915_READ(reg
);
542 assert_hdmi_port_disabled(intel_hdmi
);
544 /* See the big comment in g4x_set_infoframes() */
545 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
547 if (!intel_hdmi
->has_hdmi_sink
) {
548 if (!(val
& VIDEO_DIP_ENABLE
))
550 val
&= ~VIDEO_DIP_ENABLE
;
551 I915_WRITE(reg
, val
);
556 val
|= VIDEO_DIP_ENABLE
;
557 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
558 VIDEO_DIP_ENABLE_GCP
);
560 I915_WRITE(reg
, val
);
563 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
564 intel_hdmi_set_spd_infoframe(encoder
);
567 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
568 struct drm_display_mode
*adjusted_mode
)
570 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
571 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
572 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
573 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
574 u32 val
= I915_READ(reg
);
576 assert_hdmi_port_disabled(intel_hdmi
);
578 if (!intel_hdmi
->has_hdmi_sink
) {
584 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
585 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
587 I915_WRITE(reg
, val
);
590 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
591 intel_hdmi_set_spd_infoframe(encoder
);
594 static void intel_hdmi_mode_set(struct intel_encoder
*encoder
)
596 struct drm_device
*dev
= encoder
->base
.dev
;
597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
598 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
599 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
600 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
603 hdmi_val
= SDVO_ENCODING_HDMI
;
604 if (!HAS_PCH_SPLIT(dev
))
605 hdmi_val
|= intel_hdmi
->color_range
;
606 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
607 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
608 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
609 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
611 if (crtc
->config
.pipe_bpp
> 24)
612 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
614 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
616 /* Required on CPT */
617 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
618 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
620 if (intel_hdmi
->has_audio
) {
621 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
622 pipe_name(crtc
->pipe
));
623 hdmi_val
|= SDVO_AUDIO_ENABLE
;
624 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
625 intel_write_eld(&encoder
->base
, adjusted_mode
);
628 if (HAS_PCH_CPT(dev
))
629 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
631 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
633 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
634 POSTING_READ(intel_hdmi
->hdmi_reg
);
636 intel_hdmi
->set_infoframes(&encoder
->base
, adjusted_mode
);
639 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
642 struct drm_device
*dev
= encoder
->base
.dev
;
643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
644 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
647 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
649 if (!(tmp
& SDVO_ENABLE
))
652 if (HAS_PCH_CPT(dev
))
653 *pipe
= PORT_TO_PIPE_CPT(tmp
);
655 *pipe
= PORT_TO_PIPE(tmp
);
660 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
661 struct intel_crtc_config
*pipe_config
)
663 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
664 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
667 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
669 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
670 flags
|= DRM_MODE_FLAG_PHSYNC
;
672 flags
|= DRM_MODE_FLAG_NHSYNC
;
674 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
675 flags
|= DRM_MODE_FLAG_PVSYNC
;
677 flags
|= DRM_MODE_FLAG_NVSYNC
;
679 pipe_config
->adjusted_mode
.flags
|= flags
;
682 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
684 struct drm_device
*dev
= encoder
->base
.dev
;
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
686 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
687 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
689 u32 enable_bits
= SDVO_ENABLE
;
691 if (intel_hdmi
->has_audio
)
692 enable_bits
|= SDVO_AUDIO_ENABLE
;
694 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
696 /* HW workaround for IBX, we need to move the port to transcoder A
697 * before disabling it, so restore the transcoder select bit here. */
698 if (HAS_PCH_IBX(dev
))
699 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
701 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
702 * we do this anyway which shows more stable in testing.
704 if (HAS_PCH_SPLIT(dev
)) {
705 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
706 POSTING_READ(intel_hdmi
->hdmi_reg
);
711 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
712 POSTING_READ(intel_hdmi
->hdmi_reg
);
714 /* HW workaround, need to write this twice for issue that may result
715 * in first write getting masked.
717 if (HAS_PCH_SPLIT(dev
)) {
718 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
719 POSTING_READ(intel_hdmi
->hdmi_reg
);
722 if (IS_VALLEYVIEW(dev
)) {
723 struct intel_digital_port
*dport
=
724 enc_to_dig_port(&encoder
->base
);
725 int channel
= vlv_dport_to_channel(dport
);
727 vlv_wait_port_ready(dev_priv
, channel
);
731 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
733 struct drm_device
*dev
= encoder
->base
.dev
;
734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
735 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
737 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
739 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
741 /* HW workaround for IBX, we need to move the port to transcoder A
742 * before disabling it. */
743 if (HAS_PCH_IBX(dev
)) {
744 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
745 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
747 if (temp
& SDVO_PIPE_B_SELECT
) {
748 temp
&= ~SDVO_PIPE_B_SELECT
;
749 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
750 POSTING_READ(intel_hdmi
->hdmi_reg
);
752 /* Again we need to write this twice. */
753 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
754 POSTING_READ(intel_hdmi
->hdmi_reg
);
756 /* Transcoder selection bits only update
757 * effectively on vblank. */
759 intel_wait_for_vblank(dev
, pipe
);
765 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
766 * we do this anyway which shows more stable in testing.
768 if (HAS_PCH_SPLIT(dev
)) {
769 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
770 POSTING_READ(intel_hdmi
->hdmi_reg
);
773 temp
&= ~enable_bits
;
775 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
776 POSTING_READ(intel_hdmi
->hdmi_reg
);
778 /* HW workaround, need to write this twice for issue that may result
779 * in first write getting masked.
781 if (HAS_PCH_SPLIT(dev
)) {
782 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
783 POSTING_READ(intel_hdmi
->hdmi_reg
);
787 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
788 struct drm_display_mode
*mode
)
790 if (mode
->clock
> 165000)
791 return MODE_CLOCK_HIGH
;
792 if (mode
->clock
< 20000)
793 return MODE_CLOCK_LOW
;
795 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
796 return MODE_NO_DBLESCAN
;
801 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
802 struct intel_crtc_config
*pipe_config
)
804 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
805 struct drm_device
*dev
= encoder
->base
.dev
;
806 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
807 int clock_12bpc
= pipe_config
->requested_mode
.clock
* 3 / 2;
810 if (intel_hdmi
->color_range_auto
) {
811 /* See CEA-861-E - 5.1 Default Encoding Parameters */
812 if (intel_hdmi
->has_hdmi_sink
&&
813 drm_match_cea_mode(adjusted_mode
) > 1)
814 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
816 intel_hdmi
->color_range
= 0;
819 if (intel_hdmi
->color_range
)
820 pipe_config
->limited_color_range
= true;
822 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
823 pipe_config
->has_pch_encoder
= true;
826 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
827 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
828 * outputs. We also need to check that the higher clock still fits
831 if (pipe_config
->pipe_bpp
> 8*3 && clock_12bpc
<= 225000
832 && HAS_PCH_SPLIT(dev
)) {
833 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
836 /* Need to adjust the port link by 1.5x for 12bpc. */
837 pipe_config
->port_clock
= clock_12bpc
;
839 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
843 if (!pipe_config
->bw_constrained
) {
844 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
845 pipe_config
->pipe_bpp
= desired_bpp
;
848 if (adjusted_mode
->clock
> 225000) {
849 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
856 static enum drm_connector_status
857 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
859 struct drm_device
*dev
= connector
->dev
;
860 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
861 struct intel_digital_port
*intel_dig_port
=
862 hdmi_to_dig_port(intel_hdmi
);
863 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
866 enum drm_connector_status status
= connector_status_disconnected
;
868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
869 connector
->base
.id
, drm_get_connector_name(connector
));
871 intel_hdmi
->has_hdmi_sink
= false;
872 intel_hdmi
->has_audio
= false;
873 intel_hdmi
->rgb_quant_range_selectable
= false;
874 edid
= drm_get_edid(connector
,
875 intel_gmbus_get_adapter(dev_priv
,
876 intel_hdmi
->ddc_bus
));
879 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
880 status
= connector_status_connected
;
881 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
882 intel_hdmi
->has_hdmi_sink
=
883 drm_detect_hdmi_monitor(edid
);
884 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
885 intel_hdmi
->rgb_quant_range_selectable
=
886 drm_rgb_quant_range_selectable(edid
);
891 if (status
== connector_status_connected
) {
892 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
893 intel_hdmi
->has_audio
=
894 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
895 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
901 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
903 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
904 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
906 /* We should parse the EDID data and find out if it's an HDMI sink so
907 * we can send audio to it.
910 return intel_ddc_get_modes(connector
,
911 intel_gmbus_get_adapter(dev_priv
,
912 intel_hdmi
->ddc_bus
));
916 intel_hdmi_detect_audio(struct drm_connector
*connector
)
918 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
919 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
921 bool has_audio
= false;
923 edid
= drm_get_edid(connector
,
924 intel_gmbus_get_adapter(dev_priv
,
925 intel_hdmi
->ddc_bus
));
927 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
928 has_audio
= drm_detect_monitor_audio(edid
);
936 intel_hdmi_set_property(struct drm_connector
*connector
,
937 struct drm_property
*property
,
940 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
941 struct intel_digital_port
*intel_dig_port
=
942 hdmi_to_dig_port(intel_hdmi
);
943 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
946 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
950 if (property
== dev_priv
->force_audio_property
) {
951 enum hdmi_force_audio i
= val
;
954 if (i
== intel_hdmi
->force_audio
)
957 intel_hdmi
->force_audio
= i
;
959 if (i
== HDMI_AUDIO_AUTO
)
960 has_audio
= intel_hdmi_detect_audio(connector
);
962 has_audio
= (i
== HDMI_AUDIO_ON
);
964 if (i
== HDMI_AUDIO_OFF_DVI
)
965 intel_hdmi
->has_hdmi_sink
= 0;
967 intel_hdmi
->has_audio
= has_audio
;
971 if (property
== dev_priv
->broadcast_rgb_property
) {
972 bool old_auto
= intel_hdmi
->color_range_auto
;
973 uint32_t old_range
= intel_hdmi
->color_range
;
976 case INTEL_BROADCAST_RGB_AUTO
:
977 intel_hdmi
->color_range_auto
= true;
979 case INTEL_BROADCAST_RGB_FULL
:
980 intel_hdmi
->color_range_auto
= false;
981 intel_hdmi
->color_range
= 0;
983 case INTEL_BROADCAST_RGB_LIMITED
:
984 intel_hdmi
->color_range_auto
= false;
985 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
991 if (old_auto
== intel_hdmi
->color_range_auto
&&
992 old_range
== intel_hdmi
->color_range
)
1001 if (intel_dig_port
->base
.base
.crtc
)
1002 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1007 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1009 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1010 struct drm_device
*dev
= encoder
->base
.dev
;
1011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1012 struct intel_crtc
*intel_crtc
=
1013 to_intel_crtc(encoder
->base
.crtc
);
1014 int port
= vlv_dport_to_channel(dport
);
1015 int pipe
= intel_crtc
->pipe
;
1018 if (!IS_VALLEYVIEW(dev
))
1021 /* Enable clock channels for this port */
1022 mutex_lock(&dev_priv
->dpio_lock
);
1023 val
= vlv_dpio_read(dev_priv
, DPIO_DATA_LANE_A(port
));
1030 vlv_dpio_write(dev_priv
, DPIO_DATA_CHANNEL(port
), val
);
1033 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
), 0);
1034 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL4(port
),
1036 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL2(port
),
1038 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL3(port
),
1040 vlv_dpio_write(dev_priv
, DPIO_TX3_SWING_CTL4(port
),
1042 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER0(port
), 0x00030000);
1043 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1045 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1046 DPIO_TX_OCALINIT_EN
);
1048 /* Program lane clock */
1049 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF0(port
),
1051 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF8(port
),
1053 mutex_unlock(&dev_priv
->dpio_lock
);
1056 static void intel_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1058 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1059 struct drm_device
*dev
= encoder
->base
.dev
;
1060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1061 int port
= vlv_dport_to_channel(dport
);
1063 if (!IS_VALLEYVIEW(dev
))
1066 /* Program Tx lane resets to default */
1067 mutex_lock(&dev_priv
->dpio_lock
);
1068 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
),
1069 DPIO_PCS_TX_LANE2_RESET
|
1070 DPIO_PCS_TX_LANE1_RESET
);
1071 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
),
1072 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1073 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1074 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1075 DPIO_PCS_CLK_SOFT_RESET
);
1077 /* Fix up inter-pair skew failure */
1078 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1079 vlv_dpio_write(dev_priv
, DPIO_TX_CTL(port
), 0x00001500);
1080 vlv_dpio_write(dev_priv
, DPIO_TX_LANE(port
), 0x40400000);
1082 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1084 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1085 DPIO_TX_OCALINIT_EN
);
1086 mutex_unlock(&dev_priv
->dpio_lock
);
1089 static void intel_hdmi_post_disable(struct intel_encoder
*encoder
)
1091 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1092 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1093 int port
= vlv_dport_to_channel(dport
);
1095 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1096 mutex_lock(&dev_priv
->dpio_lock
);
1097 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
), 0x00000000);
1098 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
), 0x00e00060);
1099 mutex_unlock(&dev_priv
->dpio_lock
);
1102 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1104 drm_sysfs_connector_remove(connector
);
1105 drm_connector_cleanup(connector
);
1109 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1110 .dpms
= intel_connector_dpms
,
1111 .detect
= intel_hdmi_detect
,
1112 .fill_modes
= drm_helper_probe_single_connector_modes
,
1113 .set_property
= intel_hdmi_set_property
,
1114 .destroy
= intel_hdmi_destroy
,
1117 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1118 .get_modes
= intel_hdmi_get_modes
,
1119 .mode_valid
= intel_hdmi_mode_valid
,
1120 .best_encoder
= intel_best_encoder
,
1123 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1124 .destroy
= intel_encoder_destroy
,
1128 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1130 intel_attach_force_audio_property(connector
);
1131 intel_attach_broadcast_rgb_property(connector
);
1132 intel_hdmi
->color_range_auto
= true;
1135 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1136 struct intel_connector
*intel_connector
)
1138 struct drm_connector
*connector
= &intel_connector
->base
;
1139 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1140 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1141 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1143 enum port port
= intel_dig_port
->port
;
1145 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1146 DRM_MODE_CONNECTOR_HDMIA
);
1147 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1149 connector
->interlace_allowed
= 1;
1150 connector
->doublescan_allowed
= 0;
1154 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1155 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1158 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1159 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1162 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1163 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1166 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1167 /* Internal port only for eDP. */
1172 if (IS_VALLEYVIEW(dev
)) {
1173 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1174 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1175 } else if (!HAS_PCH_SPLIT(dev
)) {
1176 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1177 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1178 } else if (HAS_DDI(dev
)) {
1179 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1180 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1181 } else if (HAS_PCH_IBX(dev
)) {
1182 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1183 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1185 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1186 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1190 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1192 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1194 intel_hdmi_add_properties(intel_hdmi
, connector
);
1196 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1197 drm_sysfs_connector_add(connector
);
1199 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1200 * 0xd. Failure to do so will result in spurious interrupts being
1201 * generated on the port when a cable is not attached.
1203 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1204 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1205 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1209 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1211 struct intel_digital_port
*intel_dig_port
;
1212 struct intel_encoder
*intel_encoder
;
1213 struct drm_encoder
*encoder
;
1214 struct intel_connector
*intel_connector
;
1216 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1217 if (!intel_dig_port
)
1220 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1221 if (!intel_connector
) {
1222 kfree(intel_dig_port
);
1226 intel_encoder
= &intel_dig_port
->base
;
1227 encoder
= &intel_encoder
->base
;
1229 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1230 DRM_MODE_ENCODER_TMDS
);
1232 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1233 intel_encoder
->mode_set
= intel_hdmi_mode_set
;
1234 intel_encoder
->enable
= intel_enable_hdmi
;
1235 intel_encoder
->disable
= intel_disable_hdmi
;
1236 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1237 intel_encoder
->get_config
= intel_hdmi_get_config
;
1238 if (IS_VALLEYVIEW(dev
)) {
1239 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
1240 intel_encoder
->pre_pll_enable
= intel_hdmi_pre_pll_enable
;
1241 intel_encoder
->post_disable
= intel_hdmi_post_disable
;
1244 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1245 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1246 intel_encoder
->cloneable
= false;
1248 intel_dig_port
->port
= port
;
1249 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1250 intel_dig_port
->dp
.output_reg
= 0;
1252 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);