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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39
40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
41 {
42 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
43 }
44
45 static void
46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47 {
48 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 uint32_t enabled_bits;
51
52 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
53
54 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
55 "HDMI port enabled, expecting disabled\n");
56 }
57
58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
59 {
60 struct intel_digital_port *intel_dig_port =
61 container_of(encoder, struct intel_digital_port, base.base);
62 return &intel_dig_port->hdmi;
63 }
64
65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
66 {
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
68 }
69
70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
71 {
72 switch (type) {
73 case HDMI_INFOFRAME_TYPE_AVI:
74 return VIDEO_DIP_SELECT_AVI;
75 case HDMI_INFOFRAME_TYPE_SPD:
76 return VIDEO_DIP_SELECT_SPD;
77 default:
78 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
79 return 0;
80 }
81 }
82
83 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
84 {
85 switch (type) {
86 case HDMI_INFOFRAME_TYPE_AVI:
87 return VIDEO_DIP_ENABLE_AVI;
88 case HDMI_INFOFRAME_TYPE_SPD:
89 return VIDEO_DIP_ENABLE_SPD;
90 default:
91 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
92 return 0;
93 }
94 }
95
96 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
97 {
98 switch (type) {
99 case HDMI_INFOFRAME_TYPE_AVI:
100 return VIDEO_DIP_ENABLE_AVI_HSW;
101 case HDMI_INFOFRAME_TYPE_SPD:
102 return VIDEO_DIP_ENABLE_SPD_HSW;
103 default:
104 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
105 return 0;
106 }
107 }
108
109 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
110 enum transcoder cpu_transcoder)
111 {
112 switch (type) {
113 case HDMI_INFOFRAME_TYPE_AVI:
114 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
115 case HDMI_INFOFRAME_TYPE_SPD:
116 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
117 default:
118 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
119 return 0;
120 }
121 }
122
123 static void g4x_write_infoframe(struct drm_encoder *encoder,
124 enum hdmi_infoframe_type type,
125 const uint8_t *frame, ssize_t len)
126 {
127 uint32_t *data = (uint32_t *)frame;
128 struct drm_device *dev = encoder->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 u32 val = I915_READ(VIDEO_DIP_CTL);
131 int i;
132
133 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
134
135 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
136 val |= g4x_infoframe_index(type);
137
138 val &= ~g4x_infoframe_enable(type);
139
140 I915_WRITE(VIDEO_DIP_CTL, val);
141
142 mmiowb();
143 for (i = 0; i < len; i += 4) {
144 I915_WRITE(VIDEO_DIP_DATA, *data);
145 data++;
146 }
147 /* Write every possible data byte to force correct ECC calculation. */
148 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
149 I915_WRITE(VIDEO_DIP_DATA, 0);
150 mmiowb();
151
152 val |= g4x_infoframe_enable(type);
153 val &= ~VIDEO_DIP_FREQ_MASK;
154 val |= VIDEO_DIP_FREQ_VSYNC;
155
156 I915_WRITE(VIDEO_DIP_CTL, val);
157 POSTING_READ(VIDEO_DIP_CTL);
158 }
159
160 static void ibx_write_infoframe(struct drm_encoder *encoder,
161 enum hdmi_infoframe_type type,
162 const uint8_t *frame, ssize_t len)
163 {
164 uint32_t *data = (uint32_t *)frame;
165 struct drm_device *dev = encoder->dev;
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
168 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
169 u32 val = I915_READ(reg);
170
171 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
172
173 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
174 val |= g4x_infoframe_index(type);
175
176 val &= ~g4x_infoframe_enable(type);
177
178 I915_WRITE(reg, val);
179
180 mmiowb();
181 for (i = 0; i < len; i += 4) {
182 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
183 data++;
184 }
185 /* Write every possible data byte to force correct ECC calculation. */
186 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
187 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
188 mmiowb();
189
190 val |= g4x_infoframe_enable(type);
191 val &= ~VIDEO_DIP_FREQ_MASK;
192 val |= VIDEO_DIP_FREQ_VSYNC;
193
194 I915_WRITE(reg, val);
195 POSTING_READ(reg);
196 }
197
198 static void cpt_write_infoframe(struct drm_encoder *encoder,
199 enum hdmi_infoframe_type type,
200 const uint8_t *frame, ssize_t len)
201 {
202 uint32_t *data = (uint32_t *)frame;
203 struct drm_device *dev = encoder->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
206 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
207 u32 val = I915_READ(reg);
208
209 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
210
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(type);
213
214 /* The DIP control register spec says that we need to update the AVI
215 * infoframe without clearing its enable bit */
216 if (type != HDMI_INFOFRAME_TYPE_AVI)
217 val &= ~g4x_infoframe_enable(type);
218
219 I915_WRITE(reg, val);
220
221 mmiowb();
222 for (i = 0; i < len; i += 4) {
223 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
224 data++;
225 }
226 /* Write every possible data byte to force correct ECC calculation. */
227 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
228 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
229 mmiowb();
230
231 val |= g4x_infoframe_enable(type);
232 val &= ~VIDEO_DIP_FREQ_MASK;
233 val |= VIDEO_DIP_FREQ_VSYNC;
234
235 I915_WRITE(reg, val);
236 POSTING_READ(reg);
237 }
238
239 static void vlv_write_infoframe(struct drm_encoder *encoder,
240 enum hdmi_infoframe_type type,
241 const uint8_t *frame, ssize_t len)
242 {
243 uint32_t *data = (uint32_t *)frame;
244 struct drm_device *dev = encoder->dev;
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
247 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
248 u32 val = I915_READ(reg);
249
250 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
251
252 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
253 val |= g4x_infoframe_index(type);
254
255 val &= ~g4x_infoframe_enable(type);
256
257 I915_WRITE(reg, val);
258
259 mmiowb();
260 for (i = 0; i < len; i += 4) {
261 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
262 data++;
263 }
264 /* Write every possible data byte to force correct ECC calculation. */
265 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
266 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
267 mmiowb();
268
269 val |= g4x_infoframe_enable(type);
270 val &= ~VIDEO_DIP_FREQ_MASK;
271 val |= VIDEO_DIP_FREQ_VSYNC;
272
273 I915_WRITE(reg, val);
274 POSTING_READ(reg);
275 }
276
277 static void hsw_write_infoframe(struct drm_encoder *encoder,
278 enum hdmi_infoframe_type type,
279 const uint8_t *frame, ssize_t len)
280 {
281 uint32_t *data = (uint32_t *)frame;
282 struct drm_device *dev = encoder->dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
285 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
286 u32 data_reg;
287 int i;
288 u32 val = I915_READ(ctl_reg);
289
290 data_reg = hsw_infoframe_data_reg(type,
291 intel_crtc->config.cpu_transcoder);
292 if (data_reg == 0)
293 return;
294
295 val &= ~hsw_infoframe_enable(type);
296 I915_WRITE(ctl_reg, val);
297
298 mmiowb();
299 for (i = 0; i < len; i += 4) {
300 I915_WRITE(data_reg + i, *data);
301 data++;
302 }
303 /* Write every possible data byte to force correct ECC calculation. */
304 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
305 I915_WRITE(data_reg + i, 0);
306 mmiowb();
307
308 val |= hsw_infoframe_enable(type);
309 I915_WRITE(ctl_reg, val);
310 POSTING_READ(ctl_reg);
311 }
312
313 /*
314 * The data we write to the DIP data buffer registers is 1 byte bigger than the
315 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
316 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
317 * used for both technologies.
318 *
319 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
320 * DW1: DB3 | DB2 | DB1 | DB0
321 * DW2: DB7 | DB6 | DB5 | DB4
322 * DW3: ...
323 *
324 * (HB is Header Byte, DB is Data Byte)
325 *
326 * The hdmi pack() functions don't know about that hardware specific hole so we
327 * trick them by giving an offset into the buffer and moving back the header
328 * bytes by one.
329 */
330 static void intel_set_infoframe(struct drm_encoder *encoder,
331 union hdmi_infoframe *frame)
332 {
333 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
334 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
335 ssize_t len;
336
337 /* see comment above for the reason for this offset */
338 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
339 if (len < 0)
340 return;
341
342 /* Insert the 'hole' (see big comment above) at position 3 */
343 buffer[0] = buffer[1];
344 buffer[1] = buffer[2];
345 buffer[2] = buffer[3];
346 buffer[3] = 0;
347 len++;
348
349 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
350 }
351
352 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
353 struct drm_display_mode *adjusted_mode)
354 {
355 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
356 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
357 union hdmi_infoframe frame;
358 int ret;
359
360 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
361 adjusted_mode);
362 if (ret < 0) {
363 DRM_ERROR("couldn't fill AVI infoframe\n");
364 return;
365 }
366
367 if (intel_hdmi->rgb_quant_range_selectable) {
368 if (intel_crtc->config.limited_color_range)
369 frame.avi.quantization_range =
370 HDMI_QUANTIZATION_RANGE_LIMITED;
371 else
372 frame.avi.quantization_range =
373 HDMI_QUANTIZATION_RANGE_FULL;
374 }
375
376 intel_set_infoframe(encoder, &frame);
377 }
378
379 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
380 {
381 union hdmi_infoframe frame;
382 int ret;
383
384 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
385 if (ret < 0) {
386 DRM_ERROR("couldn't fill SPD infoframe\n");
387 return;
388 }
389
390 frame.spd.sdi = HDMI_SPD_SDI_PC;
391
392 intel_set_infoframe(encoder, &frame);
393 }
394
395 static void g4x_set_infoframes(struct drm_encoder *encoder,
396 struct drm_display_mode *adjusted_mode)
397 {
398 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
399 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
400 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
401 u32 reg = VIDEO_DIP_CTL;
402 u32 val = I915_READ(reg);
403 u32 port;
404
405 assert_hdmi_port_disabled(intel_hdmi);
406
407 /* If the registers were not initialized yet, they might be zeroes,
408 * which means we're selecting the AVI DIP and we're setting its
409 * frequency to once. This seems to really confuse the HW and make
410 * things stop working (the register spec says the AVI always needs to
411 * be sent every VSync). So here we avoid writing to the register more
412 * than we need and also explicitly select the AVI DIP and explicitly
413 * set its frequency to every VSync. Avoiding to write it twice seems to
414 * be enough to solve the problem, but being defensive shouldn't hurt us
415 * either. */
416 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
417
418 if (!intel_hdmi->has_hdmi_sink) {
419 if (!(val & VIDEO_DIP_ENABLE))
420 return;
421 val &= ~VIDEO_DIP_ENABLE;
422 I915_WRITE(reg, val);
423 POSTING_READ(reg);
424 return;
425 }
426
427 switch (intel_dig_port->port) {
428 case PORT_B:
429 port = VIDEO_DIP_PORT_B;
430 break;
431 case PORT_C:
432 port = VIDEO_DIP_PORT_C;
433 break;
434 default:
435 BUG();
436 return;
437 }
438
439 if (port != (val & VIDEO_DIP_PORT_MASK)) {
440 if (val & VIDEO_DIP_ENABLE) {
441 val &= ~VIDEO_DIP_ENABLE;
442 I915_WRITE(reg, val);
443 POSTING_READ(reg);
444 }
445 val &= ~VIDEO_DIP_PORT_MASK;
446 val |= port;
447 }
448
449 val |= VIDEO_DIP_ENABLE;
450 val &= ~VIDEO_DIP_ENABLE_VENDOR;
451
452 I915_WRITE(reg, val);
453 POSTING_READ(reg);
454
455 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
456 intel_hdmi_set_spd_infoframe(encoder);
457 }
458
459 static void ibx_set_infoframes(struct drm_encoder *encoder,
460 struct drm_display_mode *adjusted_mode)
461 {
462 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
463 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
464 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
465 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
466 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
467 u32 val = I915_READ(reg);
468 u32 port;
469
470 assert_hdmi_port_disabled(intel_hdmi);
471
472 /* See the big comment in g4x_set_infoframes() */
473 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
474
475 if (!intel_hdmi->has_hdmi_sink) {
476 if (!(val & VIDEO_DIP_ENABLE))
477 return;
478 val &= ~VIDEO_DIP_ENABLE;
479 I915_WRITE(reg, val);
480 POSTING_READ(reg);
481 return;
482 }
483
484 switch (intel_dig_port->port) {
485 case PORT_B:
486 port = VIDEO_DIP_PORT_B;
487 break;
488 case PORT_C:
489 port = VIDEO_DIP_PORT_C;
490 break;
491 case PORT_D:
492 port = VIDEO_DIP_PORT_D;
493 break;
494 default:
495 BUG();
496 return;
497 }
498
499 if (port != (val & VIDEO_DIP_PORT_MASK)) {
500 if (val & VIDEO_DIP_ENABLE) {
501 val &= ~VIDEO_DIP_ENABLE;
502 I915_WRITE(reg, val);
503 POSTING_READ(reg);
504 }
505 val &= ~VIDEO_DIP_PORT_MASK;
506 val |= port;
507 }
508
509 val |= VIDEO_DIP_ENABLE;
510 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
511 VIDEO_DIP_ENABLE_GCP);
512
513 I915_WRITE(reg, val);
514 POSTING_READ(reg);
515
516 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
517 intel_hdmi_set_spd_infoframe(encoder);
518 }
519
520 static void cpt_set_infoframes(struct drm_encoder *encoder,
521 struct drm_display_mode *adjusted_mode)
522 {
523 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
524 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
525 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
526 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
527 u32 val = I915_READ(reg);
528
529 assert_hdmi_port_disabled(intel_hdmi);
530
531 /* See the big comment in g4x_set_infoframes() */
532 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
533
534 if (!intel_hdmi->has_hdmi_sink) {
535 if (!(val & VIDEO_DIP_ENABLE))
536 return;
537 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
538 I915_WRITE(reg, val);
539 POSTING_READ(reg);
540 return;
541 }
542
543 /* Set both together, unset both together: see the spec. */
544 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
545 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
546 VIDEO_DIP_ENABLE_GCP);
547
548 I915_WRITE(reg, val);
549 POSTING_READ(reg);
550
551 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
552 intel_hdmi_set_spd_infoframe(encoder);
553 }
554
555 static void vlv_set_infoframes(struct drm_encoder *encoder,
556 struct drm_display_mode *adjusted_mode)
557 {
558 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
559 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
560 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
561 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
562 u32 val = I915_READ(reg);
563
564 assert_hdmi_port_disabled(intel_hdmi);
565
566 /* See the big comment in g4x_set_infoframes() */
567 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
568
569 if (!intel_hdmi->has_hdmi_sink) {
570 if (!(val & VIDEO_DIP_ENABLE))
571 return;
572 val &= ~VIDEO_DIP_ENABLE;
573 I915_WRITE(reg, val);
574 POSTING_READ(reg);
575 return;
576 }
577
578 val |= VIDEO_DIP_ENABLE;
579 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
580 VIDEO_DIP_ENABLE_GCP);
581
582 I915_WRITE(reg, val);
583 POSTING_READ(reg);
584
585 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
586 intel_hdmi_set_spd_infoframe(encoder);
587 }
588
589 static void hsw_set_infoframes(struct drm_encoder *encoder,
590 struct drm_display_mode *adjusted_mode)
591 {
592 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
593 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
594 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
595 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
596 u32 val = I915_READ(reg);
597
598 assert_hdmi_port_disabled(intel_hdmi);
599
600 if (!intel_hdmi->has_hdmi_sink) {
601 I915_WRITE(reg, 0);
602 POSTING_READ(reg);
603 return;
604 }
605
606 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
607 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
608
609 I915_WRITE(reg, val);
610 POSTING_READ(reg);
611
612 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
613 intel_hdmi_set_spd_infoframe(encoder);
614 }
615
616 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
617 {
618 struct drm_device *dev = encoder->base.dev;
619 struct drm_i915_private *dev_priv = dev->dev_private;
620 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
621 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
622 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
623 u32 hdmi_val;
624
625 hdmi_val = SDVO_ENCODING_HDMI;
626 if (!HAS_PCH_SPLIT(dev))
627 hdmi_val |= intel_hdmi->color_range;
628 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
629 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
630 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
631 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
632
633 if (crtc->config.pipe_bpp > 24)
634 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
635 else
636 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
637
638 /* Required on CPT */
639 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
640 hdmi_val |= HDMI_MODE_SELECT_HDMI;
641
642 if (intel_hdmi->has_audio) {
643 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
644 pipe_name(crtc->pipe));
645 hdmi_val |= SDVO_AUDIO_ENABLE;
646 hdmi_val |= HDMI_MODE_SELECT_HDMI;
647 intel_write_eld(&encoder->base, adjusted_mode);
648 }
649
650 if (HAS_PCH_CPT(dev))
651 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
652 else
653 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
654
655 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
656 POSTING_READ(intel_hdmi->hdmi_reg);
657
658 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
659 }
660
661 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
662 enum pipe *pipe)
663 {
664 struct drm_device *dev = encoder->base.dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
667 u32 tmp;
668
669 tmp = I915_READ(intel_hdmi->hdmi_reg);
670
671 if (!(tmp & SDVO_ENABLE))
672 return false;
673
674 if (HAS_PCH_CPT(dev))
675 *pipe = PORT_TO_PIPE_CPT(tmp);
676 else
677 *pipe = PORT_TO_PIPE(tmp);
678
679 return true;
680 }
681
682 static void intel_hdmi_get_config(struct intel_encoder *encoder,
683 struct intel_crtc_config *pipe_config)
684 {
685 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
686 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
687 u32 tmp, flags = 0;
688
689 tmp = I915_READ(intel_hdmi->hdmi_reg);
690
691 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
692 flags |= DRM_MODE_FLAG_PHSYNC;
693 else
694 flags |= DRM_MODE_FLAG_NHSYNC;
695
696 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
697 flags |= DRM_MODE_FLAG_PVSYNC;
698 else
699 flags |= DRM_MODE_FLAG_NVSYNC;
700
701 pipe_config->adjusted_mode.flags |= flags;
702 }
703
704 static void intel_enable_hdmi(struct intel_encoder *encoder)
705 {
706 struct drm_device *dev = encoder->base.dev;
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
709 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
710 u32 temp;
711 u32 enable_bits = SDVO_ENABLE;
712
713 if (intel_hdmi->has_audio)
714 enable_bits |= SDVO_AUDIO_ENABLE;
715
716 temp = I915_READ(intel_hdmi->hdmi_reg);
717
718 /* HW workaround for IBX, we need to move the port to transcoder A
719 * before disabling it, so restore the transcoder select bit here. */
720 if (HAS_PCH_IBX(dev))
721 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
722
723 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
724 * we do this anyway which shows more stable in testing.
725 */
726 if (HAS_PCH_SPLIT(dev)) {
727 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
728 POSTING_READ(intel_hdmi->hdmi_reg);
729 }
730
731 temp |= enable_bits;
732
733 I915_WRITE(intel_hdmi->hdmi_reg, temp);
734 POSTING_READ(intel_hdmi->hdmi_reg);
735
736 /* HW workaround, need to write this twice for issue that may result
737 * in first write getting masked.
738 */
739 if (HAS_PCH_SPLIT(dev)) {
740 I915_WRITE(intel_hdmi->hdmi_reg, temp);
741 POSTING_READ(intel_hdmi->hdmi_reg);
742 }
743 }
744
745 static void vlv_enable_hdmi(struct intel_encoder *encoder)
746 {
747 }
748
749 static void intel_disable_hdmi(struct intel_encoder *encoder)
750 {
751 struct drm_device *dev = encoder->base.dev;
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
754 u32 temp;
755 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
756
757 temp = I915_READ(intel_hdmi->hdmi_reg);
758
759 /* HW workaround for IBX, we need to move the port to transcoder A
760 * before disabling it. */
761 if (HAS_PCH_IBX(dev)) {
762 struct drm_crtc *crtc = encoder->base.crtc;
763 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
764
765 if (temp & SDVO_PIPE_B_SELECT) {
766 temp &= ~SDVO_PIPE_B_SELECT;
767 I915_WRITE(intel_hdmi->hdmi_reg, temp);
768 POSTING_READ(intel_hdmi->hdmi_reg);
769
770 /* Again we need to write this twice. */
771 I915_WRITE(intel_hdmi->hdmi_reg, temp);
772 POSTING_READ(intel_hdmi->hdmi_reg);
773
774 /* Transcoder selection bits only update
775 * effectively on vblank. */
776 if (crtc)
777 intel_wait_for_vblank(dev, pipe);
778 else
779 msleep(50);
780 }
781 }
782
783 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
784 * we do this anyway which shows more stable in testing.
785 */
786 if (HAS_PCH_SPLIT(dev)) {
787 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
788 POSTING_READ(intel_hdmi->hdmi_reg);
789 }
790
791 temp &= ~enable_bits;
792
793 I915_WRITE(intel_hdmi->hdmi_reg, temp);
794 POSTING_READ(intel_hdmi->hdmi_reg);
795
796 /* HW workaround, need to write this twice for issue that may result
797 * in first write getting masked.
798 */
799 if (HAS_PCH_SPLIT(dev)) {
800 I915_WRITE(intel_hdmi->hdmi_reg, temp);
801 POSTING_READ(intel_hdmi->hdmi_reg);
802 }
803 }
804
805 static int intel_hdmi_mode_valid(struct drm_connector *connector,
806 struct drm_display_mode *mode)
807 {
808 if (mode->clock > 165000)
809 return MODE_CLOCK_HIGH;
810 if (mode->clock < 20000)
811 return MODE_CLOCK_LOW;
812
813 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
814 return MODE_NO_DBLESCAN;
815
816 return MODE_OK;
817 }
818
819 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
820 struct intel_crtc_config *pipe_config)
821 {
822 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
823 struct drm_device *dev = encoder->base.dev;
824 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
825 int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
826 int desired_bpp;
827
828 if (intel_hdmi->color_range_auto) {
829 /* See CEA-861-E - 5.1 Default Encoding Parameters */
830 if (intel_hdmi->has_hdmi_sink &&
831 drm_match_cea_mode(adjusted_mode) > 1)
832 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
833 else
834 intel_hdmi->color_range = 0;
835 }
836
837 if (intel_hdmi->color_range)
838 pipe_config->limited_color_range = true;
839
840 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
841 pipe_config->has_pch_encoder = true;
842
843 /*
844 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
845 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
846 * outputs. We also need to check that the higher clock still fits
847 * within limits.
848 */
849 if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
850 && HAS_PCH_SPLIT(dev)) {
851 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
852 desired_bpp = 12*3;
853
854 /* Need to adjust the port link by 1.5x for 12bpc. */
855 pipe_config->port_clock = clock_12bpc;
856 } else {
857 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
858 desired_bpp = 8*3;
859 }
860
861 if (!pipe_config->bw_constrained) {
862 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
863 pipe_config->pipe_bpp = desired_bpp;
864 }
865
866 if (adjusted_mode->clock > 225000) {
867 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
868 return false;
869 }
870
871 return true;
872 }
873
874 static enum drm_connector_status
875 intel_hdmi_detect(struct drm_connector *connector, bool force)
876 {
877 struct drm_device *dev = connector->dev;
878 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
879 struct intel_digital_port *intel_dig_port =
880 hdmi_to_dig_port(intel_hdmi);
881 struct intel_encoder *intel_encoder = &intel_dig_port->base;
882 struct drm_i915_private *dev_priv = dev->dev_private;
883 struct edid *edid;
884 enum drm_connector_status status = connector_status_disconnected;
885
886 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
887 connector->base.id, drm_get_connector_name(connector));
888
889 intel_hdmi->has_hdmi_sink = false;
890 intel_hdmi->has_audio = false;
891 intel_hdmi->rgb_quant_range_selectable = false;
892 edid = drm_get_edid(connector,
893 intel_gmbus_get_adapter(dev_priv,
894 intel_hdmi->ddc_bus));
895
896 if (edid) {
897 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
898 status = connector_status_connected;
899 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
900 intel_hdmi->has_hdmi_sink =
901 drm_detect_hdmi_monitor(edid);
902 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
903 intel_hdmi->rgb_quant_range_selectable =
904 drm_rgb_quant_range_selectable(edid);
905 }
906 kfree(edid);
907 }
908
909 if (status == connector_status_connected) {
910 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
911 intel_hdmi->has_audio =
912 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
913 intel_encoder->type = INTEL_OUTPUT_HDMI;
914 }
915
916 return status;
917 }
918
919 static int intel_hdmi_get_modes(struct drm_connector *connector)
920 {
921 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
922 struct drm_i915_private *dev_priv = connector->dev->dev_private;
923
924 /* We should parse the EDID data and find out if it's an HDMI sink so
925 * we can send audio to it.
926 */
927
928 return intel_ddc_get_modes(connector,
929 intel_gmbus_get_adapter(dev_priv,
930 intel_hdmi->ddc_bus));
931 }
932
933 static bool
934 intel_hdmi_detect_audio(struct drm_connector *connector)
935 {
936 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
937 struct drm_i915_private *dev_priv = connector->dev->dev_private;
938 struct edid *edid;
939 bool has_audio = false;
940
941 edid = drm_get_edid(connector,
942 intel_gmbus_get_adapter(dev_priv,
943 intel_hdmi->ddc_bus));
944 if (edid) {
945 if (edid->input & DRM_EDID_INPUT_DIGITAL)
946 has_audio = drm_detect_monitor_audio(edid);
947 kfree(edid);
948 }
949
950 return has_audio;
951 }
952
953 static int
954 intel_hdmi_set_property(struct drm_connector *connector,
955 struct drm_property *property,
956 uint64_t val)
957 {
958 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
959 struct intel_digital_port *intel_dig_port =
960 hdmi_to_dig_port(intel_hdmi);
961 struct drm_i915_private *dev_priv = connector->dev->dev_private;
962 int ret;
963
964 ret = drm_object_property_set_value(&connector->base, property, val);
965 if (ret)
966 return ret;
967
968 if (property == dev_priv->force_audio_property) {
969 enum hdmi_force_audio i = val;
970 bool has_audio;
971
972 if (i == intel_hdmi->force_audio)
973 return 0;
974
975 intel_hdmi->force_audio = i;
976
977 if (i == HDMI_AUDIO_AUTO)
978 has_audio = intel_hdmi_detect_audio(connector);
979 else
980 has_audio = (i == HDMI_AUDIO_ON);
981
982 if (i == HDMI_AUDIO_OFF_DVI)
983 intel_hdmi->has_hdmi_sink = 0;
984
985 intel_hdmi->has_audio = has_audio;
986 goto done;
987 }
988
989 if (property == dev_priv->broadcast_rgb_property) {
990 bool old_auto = intel_hdmi->color_range_auto;
991 uint32_t old_range = intel_hdmi->color_range;
992
993 switch (val) {
994 case INTEL_BROADCAST_RGB_AUTO:
995 intel_hdmi->color_range_auto = true;
996 break;
997 case INTEL_BROADCAST_RGB_FULL:
998 intel_hdmi->color_range_auto = false;
999 intel_hdmi->color_range = 0;
1000 break;
1001 case INTEL_BROADCAST_RGB_LIMITED:
1002 intel_hdmi->color_range_auto = false;
1003 intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1004 break;
1005 default:
1006 return -EINVAL;
1007 }
1008
1009 if (old_auto == intel_hdmi->color_range_auto &&
1010 old_range == intel_hdmi->color_range)
1011 return 0;
1012
1013 goto done;
1014 }
1015
1016 return -EINVAL;
1017
1018 done:
1019 if (intel_dig_port->base.base.crtc)
1020 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1021
1022 return 0;
1023 }
1024
1025 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1026 {
1027 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1028 struct drm_device *dev = encoder->base.dev;
1029 struct drm_i915_private *dev_priv = dev->dev_private;
1030 struct intel_crtc *intel_crtc =
1031 to_intel_crtc(encoder->base.crtc);
1032 int port = vlv_dport_to_channel(dport);
1033 int pipe = intel_crtc->pipe;
1034 u32 val;
1035
1036 if (!IS_VALLEYVIEW(dev))
1037 return;
1038
1039 /* Enable clock channels for this port */
1040 mutex_lock(&dev_priv->dpio_lock);
1041 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1042 val = 0;
1043 if (pipe)
1044 val |= (1<<21);
1045 else
1046 val &= ~(1<<21);
1047 val |= 0x001000c4;
1048 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1049
1050 /* HDMI 1.0V-2dB */
1051 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
1052 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
1053 0x2b245f5f);
1054 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1055 0x5578b83a);
1056 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
1057 0x0c782040);
1058 vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
1059 0x2b247878);
1060 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1061 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1062 0x00002000);
1063 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1064 DPIO_TX_OCALINIT_EN);
1065
1066 /* Program lane clock */
1067 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1068 0x00760018);
1069 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1070 0x00400888);
1071 mutex_unlock(&dev_priv->dpio_lock);
1072
1073 intel_enable_hdmi(encoder);
1074
1075 vlv_wait_port_ready(dev_priv, port);
1076 }
1077
1078 static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1079 {
1080 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1081 struct drm_device *dev = encoder->base.dev;
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 int port = vlv_dport_to_channel(dport);
1084
1085 if (!IS_VALLEYVIEW(dev))
1086 return;
1087
1088 /* Program Tx lane resets to default */
1089 mutex_lock(&dev_priv->dpio_lock);
1090 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1091 DPIO_PCS_TX_LANE2_RESET |
1092 DPIO_PCS_TX_LANE1_RESET);
1093 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1094 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1095 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1096 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1097 DPIO_PCS_CLK_SOFT_RESET);
1098
1099 /* Fix up inter-pair skew failure */
1100 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1101 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1102 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1103
1104 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1105 0x00002000);
1106 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1107 DPIO_TX_OCALINIT_EN);
1108 mutex_unlock(&dev_priv->dpio_lock);
1109 }
1110
1111 static void intel_hdmi_post_disable(struct intel_encoder *encoder)
1112 {
1113 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1114 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1115 int port = vlv_dport_to_channel(dport);
1116
1117 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1118 mutex_lock(&dev_priv->dpio_lock);
1119 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
1120 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
1121 mutex_unlock(&dev_priv->dpio_lock);
1122 }
1123
1124 static void intel_hdmi_destroy(struct drm_connector *connector)
1125 {
1126 drm_sysfs_connector_remove(connector);
1127 drm_connector_cleanup(connector);
1128 kfree(connector);
1129 }
1130
1131 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1132 .dpms = intel_connector_dpms,
1133 .detect = intel_hdmi_detect,
1134 .fill_modes = drm_helper_probe_single_connector_modes,
1135 .set_property = intel_hdmi_set_property,
1136 .destroy = intel_hdmi_destroy,
1137 };
1138
1139 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1140 .get_modes = intel_hdmi_get_modes,
1141 .mode_valid = intel_hdmi_mode_valid,
1142 .best_encoder = intel_best_encoder,
1143 };
1144
1145 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1146 .destroy = intel_encoder_destroy,
1147 };
1148
1149 static void
1150 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1151 {
1152 intel_attach_force_audio_property(connector);
1153 intel_attach_broadcast_rgb_property(connector);
1154 intel_hdmi->color_range_auto = true;
1155 }
1156
1157 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1158 struct intel_connector *intel_connector)
1159 {
1160 struct drm_connector *connector = &intel_connector->base;
1161 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1162 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163 struct drm_device *dev = intel_encoder->base.dev;
1164 struct drm_i915_private *dev_priv = dev->dev_private;
1165 enum port port = intel_dig_port->port;
1166
1167 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1168 DRM_MODE_CONNECTOR_HDMIA);
1169 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1170
1171 connector->interlace_allowed = 1;
1172 connector->doublescan_allowed = 0;
1173
1174 switch (port) {
1175 case PORT_B:
1176 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1177 intel_encoder->hpd_pin = HPD_PORT_B;
1178 break;
1179 case PORT_C:
1180 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1181 intel_encoder->hpd_pin = HPD_PORT_C;
1182 break;
1183 case PORT_D:
1184 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1185 intel_encoder->hpd_pin = HPD_PORT_D;
1186 break;
1187 case PORT_A:
1188 intel_encoder->hpd_pin = HPD_PORT_A;
1189 /* Internal port only for eDP. */
1190 default:
1191 BUG();
1192 }
1193
1194 if (IS_VALLEYVIEW(dev)) {
1195 intel_hdmi->write_infoframe = vlv_write_infoframe;
1196 intel_hdmi->set_infoframes = vlv_set_infoframes;
1197 } else if (!HAS_PCH_SPLIT(dev)) {
1198 intel_hdmi->write_infoframe = g4x_write_infoframe;
1199 intel_hdmi->set_infoframes = g4x_set_infoframes;
1200 } else if (HAS_DDI(dev)) {
1201 intel_hdmi->write_infoframe = hsw_write_infoframe;
1202 intel_hdmi->set_infoframes = hsw_set_infoframes;
1203 } else if (HAS_PCH_IBX(dev)) {
1204 intel_hdmi->write_infoframe = ibx_write_infoframe;
1205 intel_hdmi->set_infoframes = ibx_set_infoframes;
1206 } else {
1207 intel_hdmi->write_infoframe = cpt_write_infoframe;
1208 intel_hdmi->set_infoframes = cpt_set_infoframes;
1209 }
1210
1211 if (HAS_DDI(dev))
1212 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1213 else
1214 intel_connector->get_hw_state = intel_connector_get_hw_state;
1215
1216 intel_hdmi_add_properties(intel_hdmi, connector);
1217
1218 intel_connector_attach_encoder(intel_connector, intel_encoder);
1219 drm_sysfs_connector_add(connector);
1220
1221 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1222 * 0xd. Failure to do so will result in spurious interrupts being
1223 * generated on the port when a cable is not attached.
1224 */
1225 if (IS_G4X(dev) && !IS_GM45(dev)) {
1226 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1227 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1228 }
1229 }
1230
1231 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1232 {
1233 struct intel_digital_port *intel_dig_port;
1234 struct intel_encoder *intel_encoder;
1235 struct drm_encoder *encoder;
1236 struct intel_connector *intel_connector;
1237
1238 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1239 if (!intel_dig_port)
1240 return;
1241
1242 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1243 if (!intel_connector) {
1244 kfree(intel_dig_port);
1245 return;
1246 }
1247
1248 intel_encoder = &intel_dig_port->base;
1249 encoder = &intel_encoder->base;
1250
1251 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1252 DRM_MODE_ENCODER_TMDS);
1253
1254 intel_encoder->compute_config = intel_hdmi_compute_config;
1255 intel_encoder->mode_set = intel_hdmi_mode_set;
1256 intel_encoder->disable = intel_disable_hdmi;
1257 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1258 intel_encoder->get_config = intel_hdmi_get_config;
1259 if (IS_VALLEYVIEW(dev)) {
1260 intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
1261 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1262 intel_encoder->enable = vlv_enable_hdmi;
1263 intel_encoder->post_disable = intel_hdmi_post_disable;
1264 } else {
1265 intel_encoder->enable = intel_enable_hdmi;
1266 }
1267
1268 intel_encoder->type = INTEL_OUTPUT_HDMI;
1269 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1270 intel_encoder->cloneable = false;
1271
1272 intel_dig_port->port = port;
1273 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1274 intel_dig_port->dp.output_reg = 0;
1275
1276 intel_hdmi_init_connector(intel_dig_port, intel_connector);
1277 }
Linux kernel - Deliverables
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