drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static void ibx_write_infoframe(struct drm_encoder *encoder,
 170                                 enum hdmi_infoframe_type type,
 171                                 const void *frame, ssize_t len)
 172 {
 173         const uint32_t *data = frame;
 174         struct drm_device *dev = encoder->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 177         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 178         u32 val = I915_READ(reg);
 179
 180         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 181
 182         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 183         val |= g4x_infoframe_index(type);
 184
 185         val &= ~g4x_infoframe_enable(type);
 186
 187         I915_WRITE(reg, val);
 188
 189         mmiowb();
 190         for (i = 0; i < len; i += 4) {
 191                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 192                 data++;
 193         }
 194         /* Write every possible data byte to force correct ECC calculation. */
 195         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 196                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 197         mmiowb();
 198
 199         val |= g4x_infoframe_enable(type);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204         POSTING_READ(reg);
 205 }
 206
 207 static void cpt_write_infoframe(struct drm_encoder *encoder,
 208                                 enum hdmi_infoframe_type type,
 209                                 const void *frame, ssize_t len)
 210 {
 211         const uint32_t *data = frame;
 212         struct drm_device *dev = encoder->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 215         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 216         u32 val = I915_READ(reg);
 217
 218         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= g4x_infoframe_index(type);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (type != HDMI_INFOFRAME_TYPE_AVI)
 226                 val &= ~g4x_infoframe_enable(type);
 227
 228         I915_WRITE(reg, val);
 229
 230         mmiowb();
 231         for (i = 0; i < len; i += 4) {
 232                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 233                 data++;
 234         }
 235         /* Write every possible data byte to force correct ECC calculation. */
 236         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 237                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 238         mmiowb();
 239
 240         val |= g4x_infoframe_enable(type);
 241         val &= ~VIDEO_DIP_FREQ_MASK;
 242         val |= VIDEO_DIP_FREQ_VSYNC;
 243
 244         I915_WRITE(reg, val);
 245         POSTING_READ(reg);
 246 }
 247
 248 static void vlv_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258
 259         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 260
 261         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 262         val |= g4x_infoframe_index(type);
 263
 264         val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static void hsw_write_infoframe(struct drm_encoder *encoder,
 287                                 enum hdmi_infoframe_type type,
 288                                 const void *frame, ssize_t len)
 289 {
 290         const uint32_t *data = frame;
 291         struct drm_device *dev = encoder->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 294         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 295         u32 data_reg;
 296         int i;
 297         u32 val = I915_READ(ctl_reg);
 298
 299         data_reg = hsw_infoframe_data_reg(type,
 300                                           intel_crtc->config.cpu_transcoder,
 301                                           dev_priv);
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(type);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(type);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 /*
 324  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 325  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 326  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 327  * used for both technologies.
 328  *
 329  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 330  * DW1:       DB3       | DB2 | DB1 | DB0
 331  * DW2:       DB7       | DB6 | DB5 | DB4
 332  * DW3: ...
 333  *
 334  * (HB is Header Byte, DB is Data Byte)
 335  *
 336  * The hdmi pack() functions don't know about that hardware specific hole so we
 337  * trick them by giving an offset into the buffer and moving back the header
 338  * bytes by one.
 339  */
 340 static void intel_write_infoframe(struct drm_encoder *encoder,
 341                                   union hdmi_infoframe *frame)
 342 {
 343         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 344         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 345         ssize_t len;
 346
 347         /* see comment above for the reason for this offset */
 348         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 349         if (len < 0)
 350                 return;
 351
 352         /* Insert the 'hole' (see big comment above) at position 3 */
 353         buffer[0] = buffer[1];
 354         buffer[1] = buffer[2];
 355         buffer[2] = buffer[3];
 356         buffer[3] = 0;
 357         len++;
 358
 359         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 360 }
 361
 362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 363                                          struct drm_display_mode *adjusted_mode)
 364 {
 365         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 366         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 367         union hdmi_infoframe frame;
 368         int ret;
 369
 370         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 371                                                        adjusted_mode);
 372         if (ret < 0) {
 373                 DRM_ERROR("couldn't fill AVI infoframe\n");
 374                 return;
 375         }
 376
 377         if (intel_hdmi->rgb_quant_range_selectable) {
 378                 if (intel_crtc->config.limited_color_range)
 379                         frame.avi.quantization_range =
 380                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 381                 else
 382                         frame.avi.quantization_range =
 383                                 HDMI_QUANTIZATION_RANGE_FULL;
 384         }
 385
 386         intel_write_infoframe(encoder, &frame);
 387 }
 388
 389 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 390 {
 391         union hdmi_infoframe frame;
 392         int ret;
 393
 394         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 395         if (ret < 0) {
 396                 DRM_ERROR("couldn't fill SPD infoframe\n");
 397                 return;
 398         }
 399
 400         frame.spd.sdi = HDMI_SPD_SDI_PC;
 401
 402         intel_write_infoframe(encoder, &frame);
 403 }
 404
 405 static void
 406 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 407                               struct drm_display_mode *adjusted_mode)
 408 {
 409         union hdmi_infoframe frame;
 410         int ret;
 411
 412         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 413                                                           adjusted_mode);
 414         if (ret < 0)
 415                 return;
 416
 417         intel_write_infoframe(encoder, &frame);
 418 }
 419
 420 static void g4x_set_infoframes(struct drm_encoder *encoder,
 421                                struct drm_display_mode *adjusted_mode)
 422 {
 423         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 424         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 425         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 426         u32 reg = VIDEO_DIP_CTL;
 427         u32 val = I915_READ(reg);
 428         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 429
 430         assert_hdmi_port_disabled(intel_hdmi);
 431
 432         /* If the registers were not initialized yet, they might be zeroes,
 433          * which means we're selecting the AVI DIP and we're setting its
 434          * frequency to once. This seems to really confuse the HW and make
 435          * things stop working (the register spec says the AVI always needs to
 436          * be sent every VSync). So here we avoid writing to the register more
 437          * than we need and also explicitly select the AVI DIP and explicitly
 438          * set its frequency to every VSync. Avoiding to write it twice seems to
 439          * be enough to solve the problem, but being defensive shouldn't hurt us
 440          * either. */
 441         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 442
 443         if (!intel_hdmi->has_hdmi_sink) {
 444                 if (!(val & VIDEO_DIP_ENABLE))
 445                         return;
 446                 val &= ~VIDEO_DIP_ENABLE;
 447                 I915_WRITE(reg, val);
 448                 POSTING_READ(reg);
 449                 return;
 450         }
 451
 452         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 453                 if (val & VIDEO_DIP_ENABLE) {
 454                         val &= ~VIDEO_DIP_ENABLE;
 455                         I915_WRITE(reg, val);
 456                         POSTING_READ(reg);
 457                 }
 458                 val &= ~VIDEO_DIP_PORT_MASK;
 459                 val |= port;
 460         }
 461
 462         val |= VIDEO_DIP_ENABLE;
 463         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 464
 465         I915_WRITE(reg, val);
 466         POSTING_READ(reg);
 467
 468         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 469         intel_hdmi_set_spd_infoframe(encoder);
 470         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 471 }
 472
 473 static void ibx_set_infoframes(struct drm_encoder *encoder,
 474                                struct drm_display_mode *adjusted_mode)
 475 {
 476         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 477         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 478         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 479         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 480         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 481         u32 val = I915_READ(reg);
 482         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 483
 484         assert_hdmi_port_disabled(intel_hdmi);
 485
 486         /* See the big comment in g4x_set_infoframes() */
 487         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 488
 489         if (!intel_hdmi->has_hdmi_sink) {
 490                 if (!(val & VIDEO_DIP_ENABLE))
 491                         return;
 492                 val &= ~VIDEO_DIP_ENABLE;
 493                 I915_WRITE(reg, val);
 494                 POSTING_READ(reg);
 495                 return;
 496         }
 497
 498         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 499                 if (val & VIDEO_DIP_ENABLE) {
 500                         val &= ~VIDEO_DIP_ENABLE;
 501                         I915_WRITE(reg, val);
 502                         POSTING_READ(reg);
 503                 }
 504                 val &= ~VIDEO_DIP_PORT_MASK;
 505                 val |= port;
 506         }
 507
 508         val |= VIDEO_DIP_ENABLE;
 509         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 510                  VIDEO_DIP_ENABLE_GCP);
 511
 512         I915_WRITE(reg, val);
 513         POSTING_READ(reg);
 514
 515         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 516         intel_hdmi_set_spd_infoframe(encoder);
 517         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 518 }
 519
 520 static void cpt_set_infoframes(struct drm_encoder *encoder,
 521                                struct drm_display_mode *adjusted_mode)
 522 {
 523         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 524         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 525         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 526         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 527         u32 val = I915_READ(reg);
 528
 529         assert_hdmi_port_disabled(intel_hdmi);
 530
 531         /* See the big comment in g4x_set_infoframes() */
 532         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 533
 534         if (!intel_hdmi->has_hdmi_sink) {
 535                 if (!(val & VIDEO_DIP_ENABLE))
 536                         return;
 537                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 538                 I915_WRITE(reg, val);
 539                 POSTING_READ(reg);
 540                 return;
 541         }
 542
 543         /* Set both together, unset both together: see the spec. */
 544         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 545         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 546                  VIDEO_DIP_ENABLE_GCP);
 547
 548         I915_WRITE(reg, val);
 549         POSTING_READ(reg);
 550
 551         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 552         intel_hdmi_set_spd_infoframe(encoder);
 553         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 554 }
 555
 556 static void vlv_set_infoframes(struct drm_encoder *encoder,
 557                                struct drm_display_mode *adjusted_mode)
 558 {
 559         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 560         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 561         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 562         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 563         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 564         u32 val = I915_READ(reg);
 565         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 566
 567         assert_hdmi_port_disabled(intel_hdmi);
 568
 569         /* See the big comment in g4x_set_infoframes() */
 570         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 571
 572         if (!intel_hdmi->has_hdmi_sink) {
 573                 if (!(val & VIDEO_DIP_ENABLE))
 574                         return;
 575                 val &= ~VIDEO_DIP_ENABLE;
 576                 I915_WRITE(reg, val);
 577                 POSTING_READ(reg);
 578                 return;
 579         }
 580
 581         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 582                 if (val & VIDEO_DIP_ENABLE) {
 583                         val &= ~VIDEO_DIP_ENABLE;
 584                         I915_WRITE(reg, val);
 585                         POSTING_READ(reg);
 586                 }
 587                 val &= ~VIDEO_DIP_PORT_MASK;
 588                 val |= port;
 589         }
 590
 591         val |= VIDEO_DIP_ENABLE;
 592         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 593                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 594
 595         I915_WRITE(reg, val);
 596         POSTING_READ(reg);
 597
 598         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 599         intel_hdmi_set_spd_infoframe(encoder);
 600         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 601 }
 602
 603 static void hsw_set_infoframes(struct drm_encoder *encoder,
 604                                struct drm_display_mode *adjusted_mode)
 605 {
 606         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 607         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 608         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 609         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 610         u32 val = I915_READ(reg);
 611
 612         assert_hdmi_port_disabled(intel_hdmi);
 613
 614         if (!intel_hdmi->has_hdmi_sink) {
 615                 I915_WRITE(reg, 0);
 616                 POSTING_READ(reg);
 617                 return;
 618         }
 619
 620         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 621                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 622
 623         I915_WRITE(reg, val);
 624         POSTING_READ(reg);
 625
 626         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 627         intel_hdmi_set_spd_infoframe(encoder);
 628         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 629 }
 630
 631 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 632 {
 633         struct drm_device *dev = encoder->base.dev;
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 636         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 637         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 638         u32 hdmi_val;
 639
 640         hdmi_val = SDVO_ENCODING_HDMI;
 641         if (!HAS_PCH_SPLIT(dev))
 642                 hdmi_val |= intel_hdmi->color_range;
 643         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 644                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 645         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 646                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 647
 648         if (crtc->config.pipe_bpp > 24)
 649                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 650         else
 651                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 652
 653         if (intel_hdmi->has_hdmi_sink &&
 654             (HAS_PCH_CPT(dev) || IS_VALLEYVIEW(dev)))
 655                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 656
 657         if (intel_hdmi->has_audio) {
 658                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 659                                  pipe_name(crtc->pipe));
 660                 hdmi_val |= SDVO_AUDIO_ENABLE;
 661                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 662                 intel_write_eld(&encoder->base, adjusted_mode);
 663         }
 664
 665         if (HAS_PCH_CPT(dev))
 666                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 667         else if (IS_CHERRYVIEW(dev))
 668                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 669         else
 670                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 671
 672         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 673         POSTING_READ(intel_hdmi->hdmi_reg);
 674 }
 675
 676 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 677                                     enum pipe *pipe)
 678 {
 679         struct drm_device *dev = encoder->base.dev;
 680         struct drm_i915_private *dev_priv = dev->dev_private;
 681         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 682         enum intel_display_power_domain power_domain;
 683         u32 tmp;
 684
 685         power_domain = intel_display_port_power_domain(encoder);
 686         if (!intel_display_power_enabled(dev_priv, power_domain))
 687                 return false;
 688
 689         tmp = I915_READ(intel_hdmi->hdmi_reg);
 690
 691         if (!(tmp & SDVO_ENABLE))
 692                 return false;
 693
 694         if (HAS_PCH_CPT(dev))
 695                 *pipe = PORT_TO_PIPE_CPT(tmp);
 696         else
 697                 *pipe = PORT_TO_PIPE(tmp);
 698
 699         return true;
 700 }
 701
 702 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 703                                   struct intel_crtc_config *pipe_config)
 704 {
 705         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 706         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 707         u32 tmp, flags = 0;
 708         int dotclock;
 709
 710         tmp = I915_READ(intel_hdmi->hdmi_reg);
 711
 712         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 713                 flags |= DRM_MODE_FLAG_PHSYNC;
 714         else
 715                 flags |= DRM_MODE_FLAG_NHSYNC;
 716
 717         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 718                 flags |= DRM_MODE_FLAG_PVSYNC;
 719         else
 720                 flags |= DRM_MODE_FLAG_NVSYNC;
 721
 722         pipe_config->adjusted_mode.flags |= flags;
 723
 724         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 725                 dotclock = pipe_config->port_clock * 2 / 3;
 726         else
 727                 dotclock = pipe_config->port_clock;
 728
 729         if (HAS_PCH_SPLIT(dev_priv->dev))
 730                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 731
 732         pipe_config->adjusted_mode.crtc_clock = dotclock;
 733 }
 734
 735 static void intel_enable_hdmi(struct intel_encoder *encoder)
 736 {
 737         struct drm_device *dev = encoder->base.dev;
 738         struct drm_i915_private *dev_priv = dev->dev_private;
 739         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 740         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 741         u32 temp;
 742         u32 enable_bits = SDVO_ENABLE;
 743
 744         if (intel_hdmi->has_audio)
 745                 enable_bits |= SDVO_AUDIO_ENABLE;
 746
 747         temp = I915_READ(intel_hdmi->hdmi_reg);
 748
 749         /* HW workaround for IBX, we need to move the port to transcoder A
 750          * before disabling it, so restore the transcoder select bit here. */
 751         if (HAS_PCH_IBX(dev))
 752                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 753
 754         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 755          * we do this anyway which shows more stable in testing.
 756          */
 757         if (HAS_PCH_SPLIT(dev)) {
 758                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 759                 POSTING_READ(intel_hdmi->hdmi_reg);
 760         }
 761
 762         temp |= enable_bits;
 763
 764         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 765         POSTING_READ(intel_hdmi->hdmi_reg);
 766
 767         /* HW workaround, need to write this twice for issue that may result
 768          * in first write getting masked.
 769          */
 770         if (HAS_PCH_SPLIT(dev)) {
 771                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 772                 POSTING_READ(intel_hdmi->hdmi_reg);
 773         }
 774 }
 775
 776 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 777 {
 778 }
 779
 780 static void intel_disable_hdmi(struct intel_encoder *encoder)
 781 {
 782         struct drm_device *dev = encoder->base.dev;
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 785         u32 temp;
 786         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 787
 788         temp = I915_READ(intel_hdmi->hdmi_reg);
 789
 790         /* HW workaround for IBX, we need to move the port to transcoder A
 791          * before disabling it. */
 792         if (HAS_PCH_IBX(dev)) {
 793                 struct drm_crtc *crtc = encoder->base.crtc;
 794                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 795
 796                 if (temp & SDVO_PIPE_B_SELECT) {
 797                         temp &= ~SDVO_PIPE_B_SELECT;
 798                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 799                         POSTING_READ(intel_hdmi->hdmi_reg);
 800
 801                         /* Again we need to write this twice. */
 802                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 803                         POSTING_READ(intel_hdmi->hdmi_reg);
 804
 805                         /* Transcoder selection bits only update
 806                          * effectively on vblank. */
 807                         if (crtc)
 808                                 intel_wait_for_vblank(dev, pipe);
 809                         else
 810                                 msleep(50);
 811                 }
 812         }
 813
 814         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 815          * we do this anyway which shows more stable in testing.
 816          */
 817         if (HAS_PCH_SPLIT(dev)) {
 818                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 819                 POSTING_READ(intel_hdmi->hdmi_reg);
 820         }
 821
 822         temp &= ~enable_bits;
 823
 824         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 825         POSTING_READ(intel_hdmi->hdmi_reg);
 826
 827         /* HW workaround, need to write this twice for issue that may result
 828          * in first write getting masked.
 829          */
 830         if (HAS_PCH_SPLIT(dev)) {
 831                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 832                 POSTING_READ(intel_hdmi->hdmi_reg);
 833         }
 834 }
 835
 836 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 837 {
 838         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 839
 840         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 841                 return 165000;
 842         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 843                 return 300000;
 844         else
 845                 return 225000;
 846 }
 847
 848 static enum drm_mode_status
 849 intel_hdmi_mode_valid(struct drm_connector *connector,
 850                       struct drm_display_mode *mode)
 851 {
 852         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 853                                                true))
 854                 return MODE_CLOCK_HIGH;
 855         if (mode->clock < 20000)
 856                 return MODE_CLOCK_LOW;
 857
 858         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 859                 return MODE_NO_DBLESCAN;
 860
 861         return MODE_OK;
 862 }
 863
 864 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 865 {
 866         struct drm_device *dev = crtc->base.dev;
 867         struct intel_encoder *encoder;
 868         int count = 0, count_hdmi = 0;
 869
 870         if (!HAS_PCH_SPLIT(dev))
 871                 return false;
 872
 873         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 874                 if (encoder->new_crtc != crtc)
 875                         continue;
 876
 877                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 878                 count++;
 879         }
 880
 881         /*
 882          * HDMI 12bpc affects the clocks, so it's only possible
 883          * when not cloning with other encoder types.
 884          */
 885         return count_hdmi > 0 && count_hdmi == count;
 886 }
 887
 888 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 889                                struct intel_crtc_config *pipe_config)
 890 {
 891         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 892         struct drm_device *dev = encoder->base.dev;
 893         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 894         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 895         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 896         int desired_bpp;
 897
 898         if (intel_hdmi->color_range_auto) {
 899                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 900                 if (intel_hdmi->has_hdmi_sink &&
 901                     drm_match_cea_mode(adjusted_mode) > 1)
 902                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 903                 else
 904                         intel_hdmi->color_range = 0;
 905         }
 906
 907         if (intel_hdmi->color_range)
 908                 pipe_config->limited_color_range = true;
 909
 910         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 911                 pipe_config->has_pch_encoder = true;
 912
 913         /*
 914          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 915          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 916          * outputs. We also need to check that the higher clock still fits
 917          * within limits.
 918          */
 919         if (pipe_config->pipe_bpp > 8*3 && intel_hdmi->has_hdmi_sink &&
 920             clock_12bpc <= portclock_limit &&
 921             hdmi_12bpc_possible(encoder->new_crtc)) {
 922                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 923                 desired_bpp = 12*3;
 924
 925                 /* Need to adjust the port link by 1.5x for 12bpc. */
 926                 pipe_config->port_clock = clock_12bpc;
 927         } else {
 928                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 929                 desired_bpp = 8*3;
 930         }
 931
 932         if (!pipe_config->bw_constrained) {
 933                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 934                 pipe_config->pipe_bpp = desired_bpp;
 935         }
 936
 937         if (adjusted_mode->crtc_clock > portclock_limit) {
 938                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 939                 return false;
 940         }
 941
 942         return true;
 943 }
 944
 945 static enum drm_connector_status
 946 intel_hdmi_detect(struct drm_connector *connector, bool force)
 947 {
 948         struct drm_device *dev = connector->dev;
 949         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 950         struct intel_digital_port *intel_dig_port =
 951                 hdmi_to_dig_port(intel_hdmi);
 952         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         struct edid *edid;
 955         enum intel_display_power_domain power_domain;
 956         enum drm_connector_status status = connector_status_disconnected;
 957
 958         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 959                       connector->base.id, drm_get_connector_name(connector));
 960
 961         power_domain = intel_display_port_power_domain(intel_encoder);
 962         intel_display_power_get(dev_priv, power_domain);
 963
 964         intel_hdmi->has_hdmi_sink = false;
 965         intel_hdmi->has_audio = false;
 966         intel_hdmi->rgb_quant_range_selectable = false;
 967         edid = drm_get_edid(connector,
 968                             intel_gmbus_get_adapter(dev_priv,
 969                                                     intel_hdmi->ddc_bus));
 970
 971         if (edid) {
 972                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 973                         status = connector_status_connected;
 974                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 975                                 intel_hdmi->has_hdmi_sink =
 976                                                 drm_detect_hdmi_monitor(edid);
 977                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 978                         intel_hdmi->rgb_quant_range_selectable =
 979                                 drm_rgb_quant_range_selectable(edid);
 980                 }
 981                 kfree(edid);
 982         }
 983
 984         if (status == connector_status_connected) {
 985                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 986                         intel_hdmi->has_audio =
 987                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 988                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 989         }
 990
 991         intel_display_power_put(dev_priv, power_domain);
 992
 993         return status;
 994 }
 995
 996 static int intel_hdmi_get_modes(struct drm_connector *connector)
 997 {
 998         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
 999         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1000         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1001         enum intel_display_power_domain power_domain;
1002         int ret;
1003
1004         /* We should parse the EDID data and find out if it's an HDMI sink so
1005          * we can send audio to it.
1006          */
1007
1008         power_domain = intel_display_port_power_domain(intel_encoder);
1009         intel_display_power_get(dev_priv, power_domain);
1010
1011         ret = intel_ddc_get_modes(connector,
1012                                    intel_gmbus_get_adapter(dev_priv,
1013                                                            intel_hdmi->ddc_bus));
1014
1015         intel_display_power_put(dev_priv, power_domain);
1016
1017         return ret;
1018 }
1019
1020 static bool
1021 intel_hdmi_detect_audio(struct drm_connector *connector)
1022 {
1023         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1024         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1025         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1026         enum intel_display_power_domain power_domain;
1027         struct edid *edid;
1028         bool has_audio = false;
1029
1030         power_domain = intel_display_port_power_domain(intel_encoder);
1031         intel_display_power_get(dev_priv, power_domain);
1032
1033         edid = drm_get_edid(connector,
1034                             intel_gmbus_get_adapter(dev_priv,
1035                                                     intel_hdmi->ddc_bus));
1036         if (edid) {
1037                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1038                         has_audio = drm_detect_monitor_audio(edid);
1039                 kfree(edid);
1040         }
1041
1042         intel_display_power_put(dev_priv, power_domain);
1043
1044         return has_audio;
1045 }
1046
1047 static int
1048 intel_hdmi_set_property(struct drm_connector *connector,
1049                         struct drm_property *property,
1050                         uint64_t val)
1051 {
1052         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1053         struct intel_digital_port *intel_dig_port =
1054                 hdmi_to_dig_port(intel_hdmi);
1055         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1056         int ret;
1057
1058         ret = drm_object_property_set_value(&connector->base, property, val);
1059         if (ret)
1060                 return ret;
1061
1062         if (property == dev_priv->force_audio_property) {
1063                 enum hdmi_force_audio i = val;
1064                 bool has_audio;
1065
1066                 if (i == intel_hdmi->force_audio)
1067                         return 0;
1068
1069                 intel_hdmi->force_audio = i;
1070
1071                 if (i == HDMI_AUDIO_AUTO)
1072                         has_audio = intel_hdmi_detect_audio(connector);
1073                 else
1074                         has_audio = (i == HDMI_AUDIO_ON);
1075
1076                 if (i == HDMI_AUDIO_OFF_DVI)
1077                         intel_hdmi->has_hdmi_sink = 0;
1078
1079                 intel_hdmi->has_audio = has_audio;
1080                 goto done;
1081         }
1082
1083         if (property == dev_priv->broadcast_rgb_property) {
1084                 bool old_auto = intel_hdmi->color_range_auto;
1085                 uint32_t old_range = intel_hdmi->color_range;
1086
1087                 switch (val) {
1088                 case INTEL_BROADCAST_RGB_AUTO:
1089                         intel_hdmi->color_range_auto = true;
1090                         break;
1091                 case INTEL_BROADCAST_RGB_FULL:
1092                         intel_hdmi->color_range_auto = false;
1093                         intel_hdmi->color_range = 0;
1094                         break;
1095                 case INTEL_BROADCAST_RGB_LIMITED:
1096                         intel_hdmi->color_range_auto = false;
1097                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1098                         break;
1099                 default:
1100                         return -EINVAL;
1101                 }
1102
1103                 if (old_auto == intel_hdmi->color_range_auto &&
1104                     old_range == intel_hdmi->color_range)
1105                         return 0;
1106
1107                 goto done;
1108         }
1109
1110         return -EINVAL;
1111
1112 done:
1113         if (intel_dig_port->base.base.crtc)
1114                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1115
1116         return 0;
1117 }
1118
1119 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1120 {
1121         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1122         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1123         struct drm_display_mode *adjusted_mode =
1124                 &intel_crtc->config.adjusted_mode;
1125
1126         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
1127 }
1128
1129 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1130 {
1131         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1132         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1133         struct drm_device *dev = encoder->base.dev;
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         struct intel_crtc *intel_crtc =
1136                 to_intel_crtc(encoder->base.crtc);
1137         struct drm_display_mode *adjusted_mode =
1138                 &intel_crtc->config.adjusted_mode;
1139         enum dpio_channel port = vlv_dport_to_channel(dport);
1140         int pipe = intel_crtc->pipe;
1141         u32 val;
1142
1143         if (!IS_VALLEYVIEW(dev))
1144                 return;
1145
1146         /* Enable clock channels for this port */
1147         mutex_lock(&dev_priv->dpio_lock);
1148         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1149         val = 0;
1150         if (pipe)
1151                 val |= (1<<21);
1152         else
1153                 val &= ~(1<<21);
1154         val |= 0x001000c4;
1155         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1156
1157         /* HDMI 1.0V-2dB */
1158         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1159         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1160         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1161         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1162         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1163         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1164         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1165         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1166
1167         /* Program lane clock */
1168         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1169         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1170         mutex_unlock(&dev_priv->dpio_lock);
1171
1172         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
1173
1174         intel_enable_hdmi(encoder);
1175
1176         vlv_wait_port_ready(dev_priv, dport);
1177 }
1178
1179 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1180 {
1181         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1182         struct drm_device *dev = encoder->base.dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         struct intel_crtc *intel_crtc =
1185                 to_intel_crtc(encoder->base.crtc);
1186         enum dpio_channel port = vlv_dport_to_channel(dport);
1187         int pipe = intel_crtc->pipe;
1188
1189         if (!IS_VALLEYVIEW(dev))
1190                 return;
1191
1192         /* Program Tx lane resets to default */
1193         mutex_lock(&dev_priv->dpio_lock);
1194         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1195                          DPIO_PCS_TX_LANE2_RESET |
1196                          DPIO_PCS_TX_LANE1_RESET);
1197         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1198                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1199                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1200                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1201                          DPIO_PCS_CLK_SOFT_RESET);
1202
1203         /* Fix up inter-pair skew failure */
1204         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1205         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1206         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1207
1208         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1209         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1210         mutex_unlock(&dev_priv->dpio_lock);
1211 }
1212
1213 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1214 {
1215         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1216         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1217         struct intel_crtc *intel_crtc =
1218                 to_intel_crtc(encoder->base.crtc);
1219         enum dpio_channel port = vlv_dport_to_channel(dport);
1220         int pipe = intel_crtc->pipe;
1221
1222         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1223         mutex_lock(&dev_priv->dpio_lock);
1224         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1225         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1226         mutex_unlock(&dev_priv->dpio_lock);
1227 }
1228
1229 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1230 {
1231         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1232         struct drm_device *dev = encoder->base.dev;
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         struct intel_crtc *intel_crtc =
1235                 to_intel_crtc(encoder->base.crtc);
1236         enum dpio_channel ch = vlv_dport_to_channel(dport);
1237         int pipe = intel_crtc->pipe;
1238         int data, i;
1239         u32 val;
1240
1241         /* Program Tx latency optimal setting */
1242         mutex_lock(&dev_priv->dpio_lock);
1243         for (i = 0; i < 4; i++) {
1244                 /* Set the latency optimal bit */
1245                 data = (i == 1) ? 0x0 : 0x6;
1246                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1247                                 data << DPIO_FRC_LATENCY_SHFIT);
1248
1249                 /* Set the upar bit */
1250                 data = (i == 1) ? 0x0 : 0x1;
1251                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1252                                 data << DPIO_UPAR_SHIFT);
1253         }
1254
1255         /* Data lane stagger programming */
1256         /* FIXME: Fix up value only after power analysis */
1257
1258         /* Clear calc init */
1259         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
1260
1261         /* FIXME: Program the support xxx V-dB */
1262         /* Use 800mV-0dB */
1263         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
1264         val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1265         val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1266         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
1267
1268         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
1269         val &= ~DPIO_SWING_MARGIN_MASK;
1270         val |= 102 << DPIO_SWING_MARGIN_SHIFT;
1271         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val);
1272
1273         /* Disable unique transition scale */
1274         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1275         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1276         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1277
1278         /* Additional steps for 1200mV-0dB */
1279 #if 0
1280         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1281         if (ch)
1282                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1283         else
1284                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1285         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1286
1287         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1288                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1289                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1290 #endif
1291         /* Start swing calculation */
1292         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
1293                         DPIO_PCS_SWING_CALC_TX0_TX2 |
1294                         DPIO_PCS_SWING_CALC_TX1_TX3);
1295
1296         /* LRC Bypass */
1297         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1298         val |= DPIO_LRC_BYPASS;
1299         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1300
1301         mutex_unlock(&dev_priv->dpio_lock);
1302
1303         intel_enable_hdmi(encoder);
1304
1305         vlv_wait_port_ready(dev_priv, dport);
1306 }
1307
1308 static void intel_hdmi_destroy(struct drm_connector *connector)
1309 {
1310         drm_connector_cleanup(connector);
1311         kfree(connector);
1312 }
1313
1314 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1315         .dpms = intel_connector_dpms,
1316         .detect = intel_hdmi_detect,
1317         .fill_modes = drm_helper_probe_single_connector_modes,
1318         .set_property = intel_hdmi_set_property,
1319         .destroy = intel_hdmi_destroy,
1320 };
1321
1322 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1323         .get_modes = intel_hdmi_get_modes,
1324         .mode_valid = intel_hdmi_mode_valid,
1325         .best_encoder = intel_best_encoder,
1326 };
1327
1328 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1329         .destroy = intel_encoder_destroy,
1330 };
1331
1332 static void
1333 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1334 {
1335         intel_attach_force_audio_property(connector);
1336         intel_attach_broadcast_rgb_property(connector);
1337         intel_hdmi->color_range_auto = true;
1338 }
1339
1340 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1341                                struct intel_connector *intel_connector)
1342 {
1343         struct drm_connector *connector = &intel_connector->base;
1344         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1345         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1346         struct drm_device *dev = intel_encoder->base.dev;
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348         enum port port = intel_dig_port->port;
1349
1350         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1351                            DRM_MODE_CONNECTOR_HDMIA);
1352         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1353
1354         connector->interlace_allowed = 1;
1355         connector->doublescan_allowed = 0;
1356         connector->stereo_allowed = 1;
1357
1358         switch (port) {
1359         case PORT_B:
1360                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1361                 intel_encoder->hpd_pin = HPD_PORT_B;
1362                 break;
1363         case PORT_C:
1364                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1365                 intel_encoder->hpd_pin = HPD_PORT_C;
1366                 break;
1367         case PORT_D:
1368                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1369                 intel_encoder->hpd_pin = HPD_PORT_D;
1370                 break;
1371         case PORT_A:
1372                 intel_encoder->hpd_pin = HPD_PORT_A;
1373                 /* Internal port only for eDP. */
1374         default:
1375                 BUG();
1376         }
1377
1378         if (IS_VALLEYVIEW(dev)) {
1379                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1380                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1381         } else if (!HAS_PCH_SPLIT(dev)) {
1382                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1383                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1384         } else if (HAS_DDI(dev)) {
1385                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1386                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1387         } else if (HAS_PCH_IBX(dev)) {
1388                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1389                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1390         } else {
1391                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1392                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1393         }
1394
1395         if (HAS_DDI(dev))
1396                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1397         else
1398                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1399         intel_connector->unregister = intel_connector_unregister;
1400
1401         intel_hdmi_add_properties(intel_hdmi, connector);
1402
1403         intel_connector_attach_encoder(intel_connector, intel_encoder);
1404         drm_sysfs_connector_add(connector);
1405
1406         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1407          * 0xd.  Failure to do so will result in spurious interrupts being
1408          * generated on the port when a cable is not attached.
1409          */
1410         if (IS_G4X(dev) && !IS_GM45(dev)) {
1411                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1412                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1413         }
1414 }
1415
1416 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1417 {
1418         struct intel_digital_port *intel_dig_port;
1419         struct intel_encoder *intel_encoder;
1420         struct intel_connector *intel_connector;
1421
1422         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1423         if (!intel_dig_port)
1424                 return;
1425
1426         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1427         if (!intel_connector) {
1428                 kfree(intel_dig_port);
1429                 return;
1430         }
1431
1432         intel_encoder = &intel_dig_port->base;
1433
1434         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1435                          DRM_MODE_ENCODER_TMDS);
1436
1437         intel_encoder->compute_config = intel_hdmi_compute_config;
1438         intel_encoder->mode_set = intel_hdmi_mode_set;
1439         intel_encoder->disable = intel_disable_hdmi;
1440         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1441         intel_encoder->get_config = intel_hdmi_get_config;
1442         if (IS_CHERRYVIEW(dev)) {
1443                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1444                 intel_encoder->enable = vlv_enable_hdmi;
1445         } else if (IS_VALLEYVIEW(dev)) {
1446                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1447                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1448                 intel_encoder->enable = vlv_enable_hdmi;
1449                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1450         } else {
1451                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1452                 intel_encoder->enable = intel_enable_hdmi;
1453         }
1454
1455         intel_encoder->type = INTEL_OUTPUT_HDMI;
1456         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1457         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1458         /*
1459          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1460          * to work on real hardware. And since g4x can send infoframes to
1461          * only one port anyway, nothing is lost by allowing it.
1462          */
1463         if (IS_G4X(dev))
1464                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1465
1466         intel_dig_port->port = port;
1467         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1468         intel_dig_port->dp.output_reg = 0;
1469
1470         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1471 }