drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 117                                   enum transcoder cpu_transcoder,
 118                                   struct drm_i915_private *dev_priv)
 119 {
 120         switch (type) {
 121         case HDMI_INFOFRAME_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 125         case HDMI_INFOFRAME_TYPE_VENDOR:
 126                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 127         default:
 128                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 129                 return 0;
 130         }
 131 }
 132
 133 static void g4x_write_infoframe(struct drm_encoder *encoder,
 134                                 enum hdmi_infoframe_type type,
 135                                 const void *frame, ssize_t len)
 136 {
 137         const uint32_t *data = frame;
 138         struct drm_device *dev = encoder->dev;
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         int i;
 142
 143         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 144
 145         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 146         val |= g4x_infoframe_index(type);
 147
 148         val &= ~g4x_infoframe_enable(type);
 149
 150         I915_WRITE(VIDEO_DIP_CTL, val);
 151
 152         mmiowb();
 153         for (i = 0; i < len; i += 4) {
 154                 I915_WRITE(VIDEO_DIP_DATA, *data);
 155                 data++;
 156         }
 157         /* Write every possible data byte to force correct ECC calculation. */
 158         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 159                 I915_WRITE(VIDEO_DIP_DATA, 0);
 160         mmiowb();
 161
 162         val |= g4x_infoframe_enable(type);
 163         val &= ~VIDEO_DIP_FREQ_MASK;
 164         val |= VIDEO_DIP_FREQ_VSYNC;
 165
 166         I915_WRITE(VIDEO_DIP_CTL, val);
 167         POSTING_READ(VIDEO_DIP_CTL);
 168 }
 169
 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 175         u32 val = I915_READ(VIDEO_DIP_CTL);
 176
 177         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 178                 return val & VIDEO_DIP_ENABLE;
 179
 180         return false;
 181 }
 182
 183 static void ibx_write_infoframe(struct drm_encoder *encoder,
 184                                 enum hdmi_infoframe_type type,
 185                                 const void *frame, ssize_t len)
 186 {
 187         const uint32_t *data = frame;
 188         struct drm_device *dev = encoder->dev;
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 191         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 192         u32 val = I915_READ(reg);
 193
 194         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 195
 196         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 197         val |= g4x_infoframe_index(type);
 198
 199         val &= ~g4x_infoframe_enable(type);
 200
 201         I915_WRITE(reg, val);
 202
 203         mmiowb();
 204         for (i = 0; i < len; i += 4) {
 205                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 206                 data++;
 207         }
 208         /* Write every possible data byte to force correct ECC calculation. */
 209         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 210                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 211         mmiowb();
 212
 213         val |= g4x_infoframe_enable(type);
 214         val &= ~VIDEO_DIP_FREQ_MASK;
 215         val |= VIDEO_DIP_FREQ_VSYNC;
 216
 217         I915_WRITE(reg, val);
 218         POSTING_READ(reg);
 219 }
 220
 221 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 222 {
 223         struct drm_device *dev = encoder->dev;
 224         struct drm_i915_private *dev_priv = dev->dev_private;
 225         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 226         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 227         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 228         u32 val = I915_READ(reg);
 229
 230         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 231                 return val & VIDEO_DIP_ENABLE;
 232
 233         return false;
 234 }
 235
 236 static void cpt_write_infoframe(struct drm_encoder *encoder,
 237                                 enum hdmi_infoframe_type type,
 238                                 const void *frame, ssize_t len)
 239 {
 240         const uint32_t *data = frame;
 241         struct drm_device *dev = encoder->dev;
 242         struct drm_i915_private *dev_priv = dev->dev_private;
 243         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 244         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 245         u32 val = I915_READ(reg);
 246
 247         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 248
 249         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 250         val |= g4x_infoframe_index(type);
 251
 252         /* The DIP control register spec says that we need to update the AVI
 253          * infoframe without clearing its enable bit */
 254         if (type != HDMI_INFOFRAME_TYPE_AVI)
 255                 val &= ~g4x_infoframe_enable(type);
 256
 257         I915_WRITE(reg, val);
 258
 259         mmiowb();
 260         for (i = 0; i < len; i += 4) {
 261                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 262                 data++;
 263         }
 264         /* Write every possible data byte to force correct ECC calculation. */
 265         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 266                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 267         mmiowb();
 268
 269         val |= g4x_infoframe_enable(type);
 270         val &= ~VIDEO_DIP_FREQ_MASK;
 271         val |= VIDEO_DIP_FREQ_VSYNC;
 272
 273         I915_WRITE(reg, val);
 274         POSTING_READ(reg);
 275 }
 276
 277 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 278 {
 279         struct drm_device *dev = encoder->dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 282         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 283         u32 val = I915_READ(reg);
 284
 285         return val & VIDEO_DIP_ENABLE;
 286 }
 287
 288 static void vlv_write_infoframe(struct drm_encoder *encoder,
 289                                 enum hdmi_infoframe_type type,
 290                                 const void *frame, ssize_t len)
 291 {
 292         const uint32_t *data = frame;
 293         struct drm_device *dev = encoder->dev;
 294         struct drm_i915_private *dev_priv = dev->dev_private;
 295         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 296         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 297         u32 val = I915_READ(reg);
 298
 299         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 300
 301         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 302         val |= g4x_infoframe_index(type);
 303
 304         val &= ~g4x_infoframe_enable(type);
 305
 306         I915_WRITE(reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 316         mmiowb();
 317
 318         val |= g4x_infoframe_enable(type);
 319         val &= ~VIDEO_DIP_FREQ_MASK;
 320         val |= VIDEO_DIP_FREQ_VSYNC;
 321
 322         I915_WRITE(reg, val);
 323         POSTING_READ(reg);
 324 }
 325
 326 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 327 {
 328         struct drm_device *dev = encoder->dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 331         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 332         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 333         u32 val = I915_READ(reg);
 334
 335         if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
 336                 return val & VIDEO_DIP_ENABLE;
 337
 338         return false;
 339 }
 340
 341 static void hsw_write_infoframe(struct drm_encoder *encoder,
 342                                 enum hdmi_infoframe_type type,
 343                                 const void *frame, ssize_t len)
 344 {
 345         const uint32_t *data = frame;
 346         struct drm_device *dev = encoder->dev;
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 349         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 350         u32 data_reg;
 351         int i;
 352         u32 val = I915_READ(ctl_reg);
 353
 354         data_reg = hsw_infoframe_data_reg(type,
 355                                           intel_crtc->config->cpu_transcoder,
 356                                           dev_priv);
 357         if (data_reg == 0)
 358                 return;
 359
 360         val &= ~hsw_infoframe_enable(type);
 361         I915_WRITE(ctl_reg, val);
 362
 363         mmiowb();
 364         for (i = 0; i < len; i += 4) {
 365                 I915_WRITE(data_reg + i, *data);
 366                 data++;
 367         }
 368         /* Write every possible data byte to force correct ECC calculation. */
 369         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 370                 I915_WRITE(data_reg + i, 0);
 371         mmiowb();
 372
 373         val |= hsw_infoframe_enable(type);
 374         I915_WRITE(ctl_reg, val);
 375         POSTING_READ(ctl_reg);
 376 }
 377
 378 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 379 {
 380         struct drm_device *dev = encoder->dev;
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 383         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 384         u32 val = I915_READ(ctl_reg);
 385
 386         return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
 387                       VIDEO_DIP_ENABLE_VS_HSW);
 388 }
 389
 390 /*
 391  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 392  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 393  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 394  * used for both technologies.
 395  *
 396  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 397  * DW1:       DB3       | DB2 | DB1 | DB0
 398  * DW2:       DB7       | DB6 | DB5 | DB4
 399  * DW3: ...
 400  *
 401  * (HB is Header Byte, DB is Data Byte)
 402  *
 403  * The hdmi pack() functions don't know about that hardware specific hole so we
 404  * trick them by giving an offset into the buffer and moving back the header
 405  * bytes by one.
 406  */
 407 static void intel_write_infoframe(struct drm_encoder *encoder,
 408                                   union hdmi_infoframe *frame)
 409 {
 410         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 411         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 412         ssize_t len;
 413
 414         /* see comment above for the reason for this offset */
 415         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 416         if (len < 0)
 417                 return;
 418
 419         /* Insert the 'hole' (see big comment above) at position 3 */
 420         buffer[0] = buffer[1];
 421         buffer[1] = buffer[2];
 422         buffer[2] = buffer[3];
 423         buffer[3] = 0;
 424         len++;
 425
 426         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 427 }
 428
 429 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 430                                          struct drm_display_mode *adjusted_mode)
 431 {
 432         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 433         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 434         union hdmi_infoframe frame;
 435         int ret;
 436
 437         /* Set user selected PAR to incoming mode's member */
 438         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 439
 440         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 441                                                        adjusted_mode);
 442         if (ret < 0) {
 443                 DRM_ERROR("couldn't fill AVI infoframe\n");
 444                 return;
 445         }
 446
 447         if (intel_hdmi->rgb_quant_range_selectable) {
 448                 if (intel_crtc->config->limited_color_range)
 449                         frame.avi.quantization_range =
 450                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 451                 else
 452                         frame.avi.quantization_range =
 453                                 HDMI_QUANTIZATION_RANGE_FULL;
 454         }
 455
 456         intel_write_infoframe(encoder, &frame);
 457 }
 458
 459 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 460 {
 461         union hdmi_infoframe frame;
 462         int ret;
 463
 464         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 465         if (ret < 0) {
 466                 DRM_ERROR("couldn't fill SPD infoframe\n");
 467                 return;
 468         }
 469
 470         frame.spd.sdi = HDMI_SPD_SDI_PC;
 471
 472         intel_write_infoframe(encoder, &frame);
 473 }
 474
 475 static void
 476 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 477                               struct drm_display_mode *adjusted_mode)
 478 {
 479         union hdmi_infoframe frame;
 480         int ret;
 481
 482         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 483                                                           adjusted_mode);
 484         if (ret < 0)
 485                 return;
 486
 487         intel_write_infoframe(encoder, &frame);
 488 }
 489
 490 static void g4x_set_infoframes(struct drm_encoder *encoder,
 491                                bool enable,
 492                                struct drm_display_mode *adjusted_mode)
 493 {
 494         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 495         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 496         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 497         u32 reg = VIDEO_DIP_CTL;
 498         u32 val = I915_READ(reg);
 499         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 500
 501         assert_hdmi_port_disabled(intel_hdmi);
 502
 503         /* If the registers were not initialized yet, they might be zeroes,
 504          * which means we're selecting the AVI DIP and we're setting its
 505          * frequency to once. This seems to really confuse the HW and make
 506          * things stop working (the register spec says the AVI always needs to
 507          * be sent every VSync). So here we avoid writing to the register more
 508          * than we need and also explicitly select the AVI DIP and explicitly
 509          * set its frequency to every VSync. Avoiding to write it twice seems to
 510          * be enough to solve the problem, but being defensive shouldn't hurt us
 511          * either. */
 512         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 513
 514         if (!enable) {
 515                 if (!(val & VIDEO_DIP_ENABLE))
 516                         return;
 517                 val &= ~VIDEO_DIP_ENABLE;
 518                 I915_WRITE(reg, val);
 519                 POSTING_READ(reg);
 520                 return;
 521         }
 522
 523         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 524                 if (val & VIDEO_DIP_ENABLE) {
 525                         val &= ~VIDEO_DIP_ENABLE;
 526                         I915_WRITE(reg, val);
 527                         POSTING_READ(reg);
 528                 }
 529                 val &= ~VIDEO_DIP_PORT_MASK;
 530                 val |= port;
 531         }
 532
 533         val |= VIDEO_DIP_ENABLE;
 534         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 535
 536         I915_WRITE(reg, val);
 537         POSTING_READ(reg);
 538
 539         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 540         intel_hdmi_set_spd_infoframe(encoder);
 541         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 542 }
 543
 544 static void ibx_set_infoframes(struct drm_encoder *encoder,
 545                                bool enable,
 546                                struct drm_display_mode *adjusted_mode)
 547 {
 548         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 549         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 550         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 551         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 552         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 553         u32 val = I915_READ(reg);
 554         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 555
 556         assert_hdmi_port_disabled(intel_hdmi);
 557
 558         /* See the big comment in g4x_set_infoframes() */
 559         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 560
 561         if (!enable) {
 562                 if (!(val & VIDEO_DIP_ENABLE))
 563                         return;
 564                 val &= ~VIDEO_DIP_ENABLE;
 565                 I915_WRITE(reg, val);
 566                 POSTING_READ(reg);
 567                 return;
 568         }
 569
 570         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 571                 if (val & VIDEO_DIP_ENABLE) {
 572                         val &= ~VIDEO_DIP_ENABLE;
 573                         I915_WRITE(reg, val);
 574                         POSTING_READ(reg);
 575                 }
 576                 val &= ~VIDEO_DIP_PORT_MASK;
 577                 val |= port;
 578         }
 579
 580         val |= VIDEO_DIP_ENABLE;
 581         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 582                  VIDEO_DIP_ENABLE_GCP);
 583
 584         I915_WRITE(reg, val);
 585         POSTING_READ(reg);
 586
 587         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 588         intel_hdmi_set_spd_infoframe(encoder);
 589         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 590 }
 591
 592 static void cpt_set_infoframes(struct drm_encoder *encoder,
 593                                bool enable,
 594                                struct drm_display_mode *adjusted_mode)
 595 {
 596         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 597         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 598         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 599         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 600         u32 val = I915_READ(reg);
 601
 602         assert_hdmi_port_disabled(intel_hdmi);
 603
 604         /* See the big comment in g4x_set_infoframes() */
 605         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 606
 607         if (!enable) {
 608                 if (!(val & VIDEO_DIP_ENABLE))
 609                         return;
 610                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 611                 I915_WRITE(reg, val);
 612                 POSTING_READ(reg);
 613                 return;
 614         }
 615
 616         /* Set both together, unset both together: see the spec. */
 617         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 618         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 619                  VIDEO_DIP_ENABLE_GCP);
 620
 621         I915_WRITE(reg, val);
 622         POSTING_READ(reg);
 623
 624         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 625         intel_hdmi_set_spd_infoframe(encoder);
 626         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 627 }
 628
 629 static void vlv_set_infoframes(struct drm_encoder *encoder,
 630                                bool enable,
 631                                struct drm_display_mode *adjusted_mode)
 632 {
 633         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 634         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 635         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 636         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 637         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 638         u32 val = I915_READ(reg);
 639         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 640
 641         assert_hdmi_port_disabled(intel_hdmi);
 642
 643         /* See the big comment in g4x_set_infoframes() */
 644         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 645
 646         if (!enable) {
 647                 if (!(val & VIDEO_DIP_ENABLE))
 648                         return;
 649                 val &= ~VIDEO_DIP_ENABLE;
 650                 I915_WRITE(reg, val);
 651                 POSTING_READ(reg);
 652                 return;
 653         }
 654
 655         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 656                 if (val & VIDEO_DIP_ENABLE) {
 657                         val &= ~VIDEO_DIP_ENABLE;
 658                         I915_WRITE(reg, val);
 659                         POSTING_READ(reg);
 660                 }
 661                 val &= ~VIDEO_DIP_PORT_MASK;
 662                 val |= port;
 663         }
 664
 665         val |= VIDEO_DIP_ENABLE;
 666         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 667                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 668
 669         I915_WRITE(reg, val);
 670         POSTING_READ(reg);
 671
 672         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 673         intel_hdmi_set_spd_infoframe(encoder);
 674         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 675 }
 676
 677 static void hsw_set_infoframes(struct drm_encoder *encoder,
 678                                bool enable,
 679                                struct drm_display_mode *adjusted_mode)
 680 {
 681         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 682         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 683         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 684         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 685         u32 val = I915_READ(reg);
 686
 687         assert_hdmi_port_disabled(intel_hdmi);
 688
 689         if (!enable) {
 690                 I915_WRITE(reg, 0);
 691                 POSTING_READ(reg);
 692                 return;
 693         }
 694
 695         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 696                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 697
 698         I915_WRITE(reg, val);
 699         POSTING_READ(reg);
 700
 701         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 702         intel_hdmi_set_spd_infoframe(encoder);
 703         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 704 }
 705
 706 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 707 {
 708         struct drm_device *dev = encoder->base.dev;
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 711         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 712         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 713         u32 hdmi_val;
 714
 715         hdmi_val = SDVO_ENCODING_HDMI;
 716         if (!HAS_PCH_SPLIT(dev))
 717                 hdmi_val |= intel_hdmi->color_range;
 718         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 719                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 720         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 721                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 722
 723         if (crtc->config->pipe_bpp > 24)
 724                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 725         else
 726                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 727
 728         if (crtc->config->has_hdmi_sink)
 729                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 730
 731         if (HAS_PCH_CPT(dev))
 732                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 733         else if (IS_CHERRYVIEW(dev))
 734                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 735         else
 736                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 737
 738         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 739         POSTING_READ(intel_hdmi->hdmi_reg);
 740 }
 741
 742 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 743                                     enum pipe *pipe)
 744 {
 745         struct drm_device *dev = encoder->base.dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 748         enum intel_display_power_domain power_domain;
 749         u32 tmp;
 750
 751         power_domain = intel_display_port_power_domain(encoder);
 752         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 753                 return false;
 754
 755         tmp = I915_READ(intel_hdmi->hdmi_reg);
 756
 757         if (!(tmp & SDVO_ENABLE))
 758                 return false;
 759
 760         if (HAS_PCH_CPT(dev))
 761                 *pipe = PORT_TO_PIPE_CPT(tmp);
 762         else if (IS_CHERRYVIEW(dev))
 763                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 764         else
 765                 *pipe = PORT_TO_PIPE(tmp);
 766
 767         return true;
 768 }
 769
 770 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 771                                   struct intel_crtc_state *pipe_config)
 772 {
 773         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 774         struct drm_device *dev = encoder->base.dev;
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         u32 tmp, flags = 0;
 777         int dotclock;
 778
 779         tmp = I915_READ(intel_hdmi->hdmi_reg);
 780
 781         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 782                 flags |= DRM_MODE_FLAG_PHSYNC;
 783         else
 784                 flags |= DRM_MODE_FLAG_NHSYNC;
 785
 786         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 787                 flags |= DRM_MODE_FLAG_PVSYNC;
 788         else
 789                 flags |= DRM_MODE_FLAG_NVSYNC;
 790
 791         if (tmp & HDMI_MODE_SELECT_HDMI)
 792                 pipe_config->has_hdmi_sink = true;
 793
 794         if (intel_hdmi->infoframe_enabled(&encoder->base))
 795                 pipe_config->has_infoframe = true;
 796
 797         if (tmp & SDVO_AUDIO_ENABLE)
 798                 pipe_config->has_audio = true;
 799
 800         if (!HAS_PCH_SPLIT(dev) &&
 801             tmp & HDMI_COLOR_RANGE_16_235)
 802                 pipe_config->limited_color_range = true;
 803
 804         pipe_config->base.adjusted_mode.flags |= flags;
 805
 806         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 807                 dotclock = pipe_config->port_clock * 2 / 3;
 808         else
 809                 dotclock = pipe_config->port_clock;
 810
 811         if (HAS_PCH_SPLIT(dev_priv->dev))
 812                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 813
 814         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 815 }
 816
 817 static void intel_enable_hdmi(struct intel_encoder *encoder)
 818 {
 819         struct drm_device *dev = encoder->base.dev;
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 822         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 823         u32 temp;
 824         u32 enable_bits = SDVO_ENABLE;
 825
 826         if (intel_crtc->config->has_audio)
 827                 enable_bits |= SDVO_AUDIO_ENABLE;
 828
 829         temp = I915_READ(intel_hdmi->hdmi_reg);
 830
 831         /* HW workaround for IBX, we need to move the port to transcoder A
 832          * before disabling it, so restore the transcoder select bit here. */
 833         if (HAS_PCH_IBX(dev))
 834                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 835
 836         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 837          * we do this anyway which shows more stable in testing.
 838          */
 839         if (HAS_PCH_SPLIT(dev)) {
 840                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 841                 POSTING_READ(intel_hdmi->hdmi_reg);
 842         }
 843
 844         temp |= enable_bits;
 845
 846         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 847         POSTING_READ(intel_hdmi->hdmi_reg);
 848
 849         /* HW workaround, need to write this twice for issue that may result
 850          * in first write getting masked.
 851          */
 852         if (HAS_PCH_SPLIT(dev)) {
 853                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 854                 POSTING_READ(intel_hdmi->hdmi_reg);
 855         }
 856
 857         if (intel_crtc->config->has_audio) {
 858                 WARN_ON(!intel_crtc->config->has_hdmi_sink);
 859                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 860                                  pipe_name(intel_crtc->pipe));
 861                 intel_audio_codec_enable(encoder);
 862         }
 863 }
 864
 865 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 866 {
 867 }
 868
 869 static void intel_disable_hdmi(struct intel_encoder *encoder)
 870 {
 871         struct drm_device *dev = encoder->base.dev;
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 874         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 875         u32 temp;
 876
 877         temp = I915_READ(intel_hdmi->hdmi_reg);
 878
 879         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
 880         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 881         POSTING_READ(intel_hdmi->hdmi_reg);
 882
 883         /*
 884          * HW workaround for IBX, we need to move the port
 885          * to transcoder A after disabling it to allow the
 886          * matching DP port to be enabled on transcoder A.
 887          */
 888         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
 889                 temp &= ~SDVO_PIPE_B_SELECT;
 890                 temp |= SDVO_ENABLE;
 891                 /*
 892                  * HW workaround, need to write this twice for issue
 893                  * that may result in first write getting masked.
 894                  */
 895                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 896                 POSTING_READ(intel_hdmi->hdmi_reg);
 897                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 898                 POSTING_READ(intel_hdmi->hdmi_reg);
 899
 900                 temp &= ~SDVO_ENABLE;
 901                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 902                 POSTING_READ(intel_hdmi->hdmi_reg);
 903         }
 904 }
 905
 906 static void g4x_disable_hdmi(struct intel_encoder *encoder)
 907 {
 908         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 909
 910         if (crtc->config->has_audio)
 911                 intel_audio_codec_disable(encoder);
 912
 913         intel_disable_hdmi(encoder);
 914 }
 915
 916 static void pch_disable_hdmi(struct intel_encoder *encoder)
 917 {
 918         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 919
 920         if (crtc->config->has_audio)
 921                 intel_audio_codec_disable(encoder);
 922 }
 923
 924 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
 925 {
 926         intel_disable_hdmi(encoder);
 927 }
 928
 929 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 930 {
 931         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 932
 933         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 934                 return 165000;
 935         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 936                 return 300000;
 937         else
 938                 return 225000;
 939 }
 940
 941 static enum drm_mode_status
 942 intel_hdmi_mode_valid(struct drm_connector *connector,
 943                       struct drm_display_mode *mode)
 944 {
 945         int clock = mode->clock;
 946
 947         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 948                 clock *= 2;
 949
 950         if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 951                                          true))
 952                 return MODE_CLOCK_HIGH;
 953         if (clock < 20000)
 954                 return MODE_CLOCK_LOW;
 955
 956         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 957                 return MODE_NO_DBLESCAN;
 958
 959         return MODE_OK;
 960 }
 961
 962 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
 963 {
 964         struct drm_device *dev = crtc_state->base.crtc->dev;
 965         struct drm_atomic_state *state;
 966         struct intel_encoder *encoder;
 967         struct drm_connector *connector;
 968         struct drm_connector_state *connector_state;
 969         int count = 0, count_hdmi = 0;
 970         int i;
 971
 972         if (HAS_GMCH_DISPLAY(dev))
 973                 return false;
 974
 975         state = crtc_state->base.state;
 976
 977         for_each_connector_in_state(state, connector, connector_state, i) {
 978                 if (connector_state->crtc != crtc_state->base.crtc)
 979                         continue;
 980
 981                 encoder = to_intel_encoder(connector_state->best_encoder);
 982
 983                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 984                 count++;
 985         }
 986
 987         /*
 988          * HDMI 12bpc affects the clocks, so it's only possible
 989          * when not cloning with other encoder types.
 990          */
 991         return count_hdmi > 0 && count_hdmi == count;
 992 }
 993
 994 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 995                                struct intel_crtc_state *pipe_config)
 996 {
 997         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 998         struct drm_device *dev = encoder->base.dev;
 999         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1000         int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
1001         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
1002         int desired_bpp;
1003
1004         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1005
1006         if (pipe_config->has_hdmi_sink)
1007                 pipe_config->has_infoframe = true;
1008
1009         if (intel_hdmi->color_range_auto) {
1010                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1011                 if (pipe_config->has_hdmi_sink &&
1012                     drm_match_cea_mode(adjusted_mode) > 1)
1013                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1014                 else
1015                         intel_hdmi->color_range = 0;
1016         }
1017
1018         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1019                 pipe_config->pixel_multiplier = 2;
1020         }
1021
1022         if (intel_hdmi->color_range)
1023                 pipe_config->limited_color_range = true;
1024
1025         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1026                 pipe_config->has_pch_encoder = true;
1027
1028         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1029                 pipe_config->has_audio = true;
1030
1031         /*
1032          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1033          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1034          * outputs. We also need to check that the higher clock still fits
1035          * within limits.
1036          */
1037         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1038             clock_12bpc <= portclock_limit &&
1039             hdmi_12bpc_possible(pipe_config) &&
1040             0 /* FIXME 12bpc support totally broken */) {
1041                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1042                 desired_bpp = 12*3;
1043
1044                 /* Need to adjust the port link by 1.5x for 12bpc. */
1045                 pipe_config->port_clock = clock_12bpc;
1046         } else {
1047                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1048                 desired_bpp = 8*3;
1049         }
1050
1051         if (!pipe_config->bw_constrained) {
1052                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1053                 pipe_config->pipe_bpp = desired_bpp;
1054         }
1055
1056         if (adjusted_mode->crtc_clock > portclock_limit) {
1057                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
1058                 return false;
1059         }
1060
1061         return true;
1062 }
1063
1064 static void
1065 intel_hdmi_unset_edid(struct drm_connector *connector)
1066 {
1067         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1068
1069         intel_hdmi->has_hdmi_sink = false;
1070         intel_hdmi->has_audio = false;
1071         intel_hdmi->rgb_quant_range_selectable = false;
1072
1073         kfree(to_intel_connector(connector)->detect_edid);
1074         to_intel_connector(connector)->detect_edid = NULL;
1075 }
1076
1077 static bool
1078 intel_hdmi_set_edid(struct drm_connector *connector)
1079 {
1080         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1081         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1082         struct intel_encoder *intel_encoder =
1083                 &hdmi_to_dig_port(intel_hdmi)->base;
1084         enum intel_display_power_domain power_domain;
1085         struct edid *edid;
1086         bool connected = false;
1087
1088         power_domain = intel_display_port_power_domain(intel_encoder);
1089         intel_display_power_get(dev_priv, power_domain);
1090
1091         edid = drm_get_edid(connector,
1092                             intel_gmbus_get_adapter(dev_priv,
1093                                                     intel_hdmi->ddc_bus));
1094
1095         intel_display_power_put(dev_priv, power_domain);
1096
1097         to_intel_connector(connector)->detect_edid = edid;
1098         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1099                 intel_hdmi->rgb_quant_range_selectable =
1100                         drm_rgb_quant_range_selectable(edid);
1101
1102                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1103                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1104                         intel_hdmi->has_audio =
1105                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1106
1107                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1108                         intel_hdmi->has_hdmi_sink =
1109                                 drm_detect_hdmi_monitor(edid);
1110
1111                 connected = true;
1112         }
1113
1114         return connected;
1115 }
1116
1117 static enum drm_connector_status
1118 intel_hdmi_detect(struct drm_connector *connector, bool force)
1119 {
1120         enum drm_connector_status status;
1121
1122         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1123                       connector->base.id, connector->name);
1124
1125         intel_hdmi_unset_edid(connector);
1126
1127         if (intel_hdmi_set_edid(connector)) {
1128                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1129
1130                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1131                 status = connector_status_connected;
1132         } else
1133                 status = connector_status_disconnected;
1134
1135         return status;
1136 }
1137
1138 static void
1139 intel_hdmi_force(struct drm_connector *connector)
1140 {
1141         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1142
1143         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1144                       connector->base.id, connector->name);
1145
1146         intel_hdmi_unset_edid(connector);
1147
1148         if (connector->status != connector_status_connected)
1149                 return;
1150
1151         intel_hdmi_set_edid(connector);
1152         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1153 }
1154
1155 static int intel_hdmi_get_modes(struct drm_connector *connector)
1156 {
1157         struct edid *edid;
1158
1159         edid = to_intel_connector(connector)->detect_edid;
1160         if (edid == NULL)
1161                 return 0;
1162
1163         return intel_connector_update_modes(connector, edid);
1164 }
1165
1166 static bool
1167 intel_hdmi_detect_audio(struct drm_connector *connector)
1168 {
1169         bool has_audio = false;
1170         struct edid *edid;
1171
1172         edid = to_intel_connector(connector)->detect_edid;
1173         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1174                 has_audio = drm_detect_monitor_audio(edid);
1175
1176         return has_audio;
1177 }
1178
1179 static int
1180 intel_hdmi_set_property(struct drm_connector *connector,
1181                         struct drm_property *property,
1182                         uint64_t val)
1183 {
1184         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1185         struct intel_digital_port *intel_dig_port =
1186                 hdmi_to_dig_port(intel_hdmi);
1187         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1188         int ret;
1189
1190         ret = drm_object_property_set_value(&connector->base, property, val);
1191         if (ret)
1192                 return ret;
1193
1194         if (property == dev_priv->force_audio_property) {
1195                 enum hdmi_force_audio i = val;
1196                 bool has_audio;
1197
1198                 if (i == intel_hdmi->force_audio)
1199                         return 0;
1200
1201                 intel_hdmi->force_audio = i;
1202
1203                 if (i == HDMI_AUDIO_AUTO)
1204                         has_audio = intel_hdmi_detect_audio(connector);
1205                 else
1206                         has_audio = (i == HDMI_AUDIO_ON);
1207
1208                 if (i == HDMI_AUDIO_OFF_DVI)
1209                         intel_hdmi->has_hdmi_sink = 0;
1210
1211                 intel_hdmi->has_audio = has_audio;
1212                 goto done;
1213         }
1214
1215         if (property == dev_priv->broadcast_rgb_property) {
1216                 bool old_auto = intel_hdmi->color_range_auto;
1217                 uint32_t old_range = intel_hdmi->color_range;
1218
1219                 switch (val) {
1220                 case INTEL_BROADCAST_RGB_AUTO:
1221                         intel_hdmi->color_range_auto = true;
1222                         break;
1223                 case INTEL_BROADCAST_RGB_FULL:
1224                         intel_hdmi->color_range_auto = false;
1225                         intel_hdmi->color_range = 0;
1226                         break;
1227                 case INTEL_BROADCAST_RGB_LIMITED:
1228                         intel_hdmi->color_range_auto = false;
1229                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1230                         break;
1231                 default:
1232                         return -EINVAL;
1233                 }
1234
1235                 if (old_auto == intel_hdmi->color_range_auto &&
1236                     old_range == intel_hdmi->color_range)
1237                         return 0;
1238
1239                 goto done;
1240         }
1241
1242         if (property == connector->dev->mode_config.aspect_ratio_property) {
1243                 switch (val) {
1244                 case DRM_MODE_PICTURE_ASPECT_NONE:
1245                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1246                         break;
1247                 case DRM_MODE_PICTURE_ASPECT_4_3:
1248                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1249                         break;
1250                 case DRM_MODE_PICTURE_ASPECT_16_9:
1251                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1252                         break;
1253                 default:
1254                         return -EINVAL;
1255                 }
1256                 goto done;
1257         }
1258
1259         return -EINVAL;
1260
1261 done:
1262         if (intel_dig_port->base.base.crtc)
1263                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1264
1265         return 0;
1266 }
1267
1268 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1269 {
1270         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1271         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1272         struct drm_display_mode *adjusted_mode =
1273                 &intel_crtc->config->base.adjusted_mode;
1274
1275         intel_hdmi_prepare(encoder);
1276
1277         intel_hdmi->set_infoframes(&encoder->base,
1278                                    intel_crtc->config->has_hdmi_sink,
1279                                    adjusted_mode);
1280 }
1281
1282 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1283 {
1284         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1285         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1286         struct drm_device *dev = encoder->base.dev;
1287         struct drm_i915_private *dev_priv = dev->dev_private;
1288         struct intel_crtc *intel_crtc =
1289                 to_intel_crtc(encoder->base.crtc);
1290         struct drm_display_mode *adjusted_mode =
1291                 &intel_crtc->config->base.adjusted_mode;
1292         enum dpio_channel port = vlv_dport_to_channel(dport);
1293         int pipe = intel_crtc->pipe;
1294         u32 val;
1295
1296         /* Enable clock channels for this port */
1297         mutex_lock(&dev_priv->sb_lock);
1298         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1299         val = 0;
1300         if (pipe)
1301                 val |= (1<<21);
1302         else
1303                 val &= ~(1<<21);
1304         val |= 0x001000c4;
1305         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1306
1307         /* HDMI 1.0V-2dB */
1308         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1309         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1310         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1311         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1312         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1313         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1314         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1315         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1316
1317         /* Program lane clock */
1318         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1319         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1320         mutex_unlock(&dev_priv->sb_lock);
1321
1322         intel_hdmi->set_infoframes(&encoder->base,
1323                                    intel_crtc->config->has_hdmi_sink,
1324                                    adjusted_mode);
1325
1326         intel_enable_hdmi(encoder);
1327
1328         vlv_wait_port_ready(dev_priv, dport, 0x0);
1329 }
1330
1331 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1332 {
1333         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1334         struct drm_device *dev = encoder->base.dev;
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         struct intel_crtc *intel_crtc =
1337                 to_intel_crtc(encoder->base.crtc);
1338         enum dpio_channel port = vlv_dport_to_channel(dport);
1339         int pipe = intel_crtc->pipe;
1340
1341         intel_hdmi_prepare(encoder);
1342
1343         /* Program Tx lane resets to default */
1344         mutex_lock(&dev_priv->sb_lock);
1345         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1346                          DPIO_PCS_TX_LANE2_RESET |
1347                          DPIO_PCS_TX_LANE1_RESET);
1348         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1349                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1350                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1351                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1352                          DPIO_PCS_CLK_SOFT_RESET);
1353
1354         /* Fix up inter-pair skew failure */
1355         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1356         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1357         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1358
1359         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1360         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1361         mutex_unlock(&dev_priv->sb_lock);
1362 }
1363
1364 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1365 {
1366         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1367         struct drm_device *dev = encoder->base.dev;
1368         struct drm_i915_private *dev_priv = dev->dev_private;
1369         struct intel_crtc *intel_crtc =
1370                 to_intel_crtc(encoder->base.crtc);
1371         enum dpio_channel ch = vlv_dport_to_channel(dport);
1372         enum pipe pipe = intel_crtc->pipe;
1373         u32 val;
1374
1375         intel_hdmi_prepare(encoder);
1376
1377         mutex_lock(&dev_priv->sb_lock);
1378
1379         /* program left/right clock distribution */
1380         if (pipe != PIPE_B) {
1381                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1382                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1383                 if (ch == DPIO_CH0)
1384                         val |= CHV_BUFLEFTENA1_FORCE;
1385                 if (ch == DPIO_CH1)
1386                         val |= CHV_BUFRIGHTENA1_FORCE;
1387                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1388         } else {
1389                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1390                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1391                 if (ch == DPIO_CH0)
1392                         val |= CHV_BUFLEFTENA2_FORCE;
1393                 if (ch == DPIO_CH1)
1394                         val |= CHV_BUFRIGHTENA2_FORCE;
1395                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1396         }
1397
1398         /* program clock channel usage */
1399         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1400         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1401         if (pipe != PIPE_B)
1402                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1403         else
1404                 val |= CHV_PCS_USEDCLKCHANNEL;
1405         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1406
1407         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1408         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1409         if (pipe != PIPE_B)
1410                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1411         else
1412                 val |= CHV_PCS_USEDCLKCHANNEL;
1413         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1414
1415         /*
1416          * This a a bit weird since generally CL
1417          * matches the pipe, but here we need to
1418          * pick the CL based on the port.
1419          */
1420         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1421         if (pipe != PIPE_B)
1422                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1423         else
1424                 val |= CHV_CMN_USEDCLKCHANNEL;
1425         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1426
1427         mutex_unlock(&dev_priv->sb_lock);
1428 }
1429
1430 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1431 {
1432         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1433         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1434         struct intel_crtc *intel_crtc =
1435                 to_intel_crtc(encoder->base.crtc);
1436         enum dpio_channel port = vlv_dport_to_channel(dport);
1437         int pipe = intel_crtc->pipe;
1438
1439         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1440         mutex_lock(&dev_priv->sb_lock);
1441         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1442         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1443         mutex_unlock(&dev_priv->sb_lock);
1444 }
1445
1446 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1447 {
1448         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1449         struct drm_device *dev = encoder->base.dev;
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         struct intel_crtc *intel_crtc =
1452                 to_intel_crtc(encoder->base.crtc);
1453         enum dpio_channel ch = vlv_dport_to_channel(dport);
1454         enum pipe pipe = intel_crtc->pipe;
1455         u32 val;
1456
1457         mutex_lock(&dev_priv->sb_lock);
1458
1459         /* Propagate soft reset to data lane reset */
1460         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1461         val |= CHV_PCS_REQ_SOFTRESET_EN;
1462         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1463
1464         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1465         val |= CHV_PCS_REQ_SOFTRESET_EN;
1466         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1467
1468         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1469         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1470         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1471
1472         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1473         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1474         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1475
1476         mutex_unlock(&dev_priv->sb_lock);
1477 }
1478
1479 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1480 {
1481         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1482         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1483         struct drm_device *dev = encoder->base.dev;
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         struct intel_crtc *intel_crtc =
1486                 to_intel_crtc(encoder->base.crtc);
1487         struct drm_display_mode *adjusted_mode =
1488                 &intel_crtc->config->base.adjusted_mode;
1489         enum dpio_channel ch = vlv_dport_to_channel(dport);
1490         int pipe = intel_crtc->pipe;
1491         int data, i, stagger;
1492         u32 val;
1493
1494         mutex_lock(&dev_priv->sb_lock);
1495
1496         /* allow hardware to manage TX FIFO reset source */
1497         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1498         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1499         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1500
1501         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1502         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1503         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1504
1505         /* Deassert soft data lane reset*/
1506         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1507         val |= CHV_PCS_REQ_SOFTRESET_EN;
1508         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1509
1510         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1511         val |= CHV_PCS_REQ_SOFTRESET_EN;
1512         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1513
1514         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1515         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1516         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1517
1518         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1519         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1520         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1521
1522         /* Program Tx latency optimal setting */
1523         for (i = 0; i < 4; i++) {
1524                 /* Set the upar bit */
1525                 data = (i == 1) ? 0x0 : 0x1;
1526                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1527                                 data << DPIO_UPAR_SHIFT);
1528         }
1529
1530         /* Data lane stagger programming */
1531         if (intel_crtc->config->port_clock > 270000)
1532                 stagger = 0x18;
1533         else if (intel_crtc->config->port_clock > 135000)
1534                 stagger = 0xd;
1535         else if (intel_crtc->config->port_clock > 67500)
1536                 stagger = 0x7;
1537         else if (intel_crtc->config->port_clock > 33750)
1538                 stagger = 0x4;
1539         else
1540                 stagger = 0x2;
1541
1542         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1543         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1544         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1545
1546         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1547         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1548         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1549
1550         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1551                        DPIO_LANESTAGGER_STRAP(stagger) |
1552                        DPIO_LANESTAGGER_STRAP_OVRD |
1553                        DPIO_TX1_STAGGER_MASK(0x1f) |
1554                        DPIO_TX1_STAGGER_MULT(6) |
1555                        DPIO_TX2_STAGGER_MULT(0));
1556
1557         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1558                        DPIO_LANESTAGGER_STRAP(stagger) |
1559                        DPIO_LANESTAGGER_STRAP_OVRD |
1560                        DPIO_TX1_STAGGER_MASK(0x1f) |
1561                        DPIO_TX1_STAGGER_MULT(7) |
1562                        DPIO_TX2_STAGGER_MULT(5));
1563
1564         /* Clear calc init */
1565         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1566         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1567         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1568         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1569         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1570
1571         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1572         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1573         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1574         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1575         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1576
1577         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1578         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1579         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1580         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1581
1582         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1583         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1584         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1585         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1586
1587         /* FIXME: Program the support xxx V-dB */
1588         /* Use 800mV-0dB */
1589         for (i = 0; i < 4; i++) {
1590                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1591                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1592                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1593                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1594         }
1595
1596         for (i = 0; i < 4; i++) {
1597                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1598                 val &= ~DPIO_SWING_MARGIN000_MASK;
1599                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1600                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1601         }
1602
1603         /* Disable unique transition scale */
1604         for (i = 0; i < 4; i++) {
1605                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1606                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1607                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1608         }
1609
1610         /* Additional steps for 1200mV-0dB */
1611 #if 0
1612         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1613         if (ch)
1614                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1615         else
1616                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1617         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1618
1619         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1620                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1621                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1622 #endif
1623         /* Start swing calculation */
1624         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1625         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1626         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1627
1628         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1629         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1630         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1631
1632         /* LRC Bypass */
1633         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1634         val |= DPIO_LRC_BYPASS;
1635         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1636
1637         mutex_unlock(&dev_priv->sb_lock);
1638
1639         intel_hdmi->set_infoframes(&encoder->base,
1640                                    intel_crtc->config->has_hdmi_sink,
1641                                    adjusted_mode);
1642
1643         intel_enable_hdmi(encoder);
1644
1645         vlv_wait_port_ready(dev_priv, dport, 0x0);
1646 }
1647
1648 static void intel_hdmi_destroy(struct drm_connector *connector)
1649 {
1650         kfree(to_intel_connector(connector)->detect_edid);
1651         drm_connector_cleanup(connector);
1652         kfree(connector);
1653 }
1654
1655 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1656         .dpms = intel_connector_dpms,
1657         .detect = intel_hdmi_detect,
1658         .force = intel_hdmi_force,
1659         .fill_modes = drm_helper_probe_single_connector_modes,
1660         .set_property = intel_hdmi_set_property,
1661         .atomic_get_property = intel_connector_atomic_get_property,
1662         .destroy = intel_hdmi_destroy,
1663         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1664         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1665 };
1666
1667 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1668         .get_modes = intel_hdmi_get_modes,
1669         .mode_valid = intel_hdmi_mode_valid,
1670         .best_encoder = intel_best_encoder,
1671 };
1672
1673 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1674         .destroy = intel_encoder_destroy,
1675 };
1676
1677 static void
1678 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1679 {
1680         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1681                 drm_object_attach_property(&connector->base,
1682                         connector->dev->mode_config.aspect_ratio_property,
1683                         DRM_MODE_PICTURE_ASPECT_NONE);
1684 }
1685
1686 static void
1687 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1688 {
1689         intel_attach_force_audio_property(connector);
1690         intel_attach_broadcast_rgb_property(connector);
1691         intel_hdmi->color_range_auto = true;
1692         intel_attach_aspect_ratio_property(connector);
1693         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1694 }
1695
1696 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1697                                struct intel_connector *intel_connector)
1698 {
1699         struct drm_connector *connector = &intel_connector->base;
1700         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1701         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1702         struct drm_device *dev = intel_encoder->base.dev;
1703         struct drm_i915_private *dev_priv = dev->dev_private;
1704         enum port port = intel_dig_port->port;
1705
1706         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1707                            DRM_MODE_CONNECTOR_HDMIA);
1708         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1709
1710         connector->interlace_allowed = 1;
1711         connector->doublescan_allowed = 0;
1712         connector->stereo_allowed = 1;
1713
1714         switch (port) {
1715         case PORT_B:
1716                 if (IS_BROXTON(dev_priv))
1717                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1718                 else
1719                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1720                 intel_encoder->hpd_pin = HPD_PORT_B;
1721                 break;
1722         case PORT_C:
1723                 if (IS_BROXTON(dev_priv))
1724                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1725                 else
1726                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1727                 intel_encoder->hpd_pin = HPD_PORT_C;
1728                 break;
1729         case PORT_D:
1730                 if (WARN_ON(IS_BROXTON(dev_priv)))
1731                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1732                 else if (IS_CHERRYVIEW(dev_priv))
1733                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1734                 else
1735                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1736                 intel_encoder->hpd_pin = HPD_PORT_D;
1737                 break;
1738         case PORT_A:
1739                 intel_encoder->hpd_pin = HPD_PORT_A;
1740                 /* Internal port only for eDP. */
1741         default:
1742                 BUG();
1743         }
1744
1745         if (IS_VALLEYVIEW(dev)) {
1746                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1747                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1748                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1749         } else if (IS_G4X(dev)) {
1750                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1751                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1752                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1753         } else if (HAS_DDI(dev)) {
1754                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1755                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1756                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1757         } else if (HAS_PCH_IBX(dev)) {
1758                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1759                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1760                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1761         } else {
1762                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1763                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1764                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1765         }
1766
1767         if (HAS_DDI(dev))
1768                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1769         else
1770                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1771         intel_connector->unregister = intel_connector_unregister;
1772
1773         intel_hdmi_add_properties(intel_hdmi, connector);
1774
1775         intel_connector_attach_encoder(intel_connector, intel_encoder);
1776         drm_connector_register(connector);
1777
1778         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1779          * 0xd.  Failure to do so will result in spurious interrupts being
1780          * generated on the port when a cable is not attached.
1781          */
1782         if (IS_G4X(dev) && !IS_GM45(dev)) {
1783                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1784                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1785         }
1786 }
1787
1788 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1789 {
1790         struct intel_digital_port *intel_dig_port;
1791         struct intel_encoder *intel_encoder;
1792         struct intel_connector *intel_connector;
1793
1794         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1795         if (!intel_dig_port)
1796                 return;
1797
1798         intel_connector = intel_connector_alloc();
1799         if (!intel_connector) {
1800                 kfree(intel_dig_port);
1801                 return;
1802         }
1803
1804         intel_encoder = &intel_dig_port->base;
1805
1806         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1807                          DRM_MODE_ENCODER_TMDS);
1808
1809         intel_encoder->compute_config = intel_hdmi_compute_config;
1810         if (HAS_PCH_SPLIT(dev)) {
1811                 intel_encoder->disable = pch_disable_hdmi;
1812                 intel_encoder->post_disable = pch_post_disable_hdmi;
1813         } else {
1814                 intel_encoder->disable = g4x_disable_hdmi;
1815         }
1816         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1817         intel_encoder->get_config = intel_hdmi_get_config;
1818         if (IS_CHERRYVIEW(dev)) {
1819                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1820                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1821                 intel_encoder->enable = vlv_enable_hdmi;
1822                 intel_encoder->post_disable = chv_hdmi_post_disable;
1823         } else if (IS_VALLEYVIEW(dev)) {
1824                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1825                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1826                 intel_encoder->enable = vlv_enable_hdmi;
1827                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1828         } else {
1829                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1830                 intel_encoder->enable = intel_enable_hdmi;
1831         }
1832
1833         intel_encoder->type = INTEL_OUTPUT_HDMI;
1834         if (IS_CHERRYVIEW(dev)) {
1835                 if (port == PORT_D)
1836                         intel_encoder->crtc_mask = 1 << 2;
1837                 else
1838                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1839         } else {
1840                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1841         }
1842         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1843         /*
1844          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1845          * to work on real hardware. And since g4x can send infoframes to
1846          * only one port anyway, nothing is lost by allowing it.
1847          */
1848         if (IS_G4X(dev))
1849                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1850
1851         intel_dig_port->port = port;
1852         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1853         intel_dig_port->dp.output_reg = 0;
1854
1855         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1856 }