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Merge branch 'linus' into sched/urgent, to pick up dependencies
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
39 #include "i915_drv.h"
40
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42 {
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
44 }
45
46 static void
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48 {
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
54
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
57 }
58
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
60 {
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
64 }
65
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67 {
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 }
70
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
72 {
73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
80 default:
81 MISSING_CASE(type);
82 return 0;
83 }
84 }
85
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
87 {
88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
95 default:
96 MISSING_CASE(type);
97 return 0;
98 }
99 }
100
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
102 {
103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
110 default:
111 MISSING_CASE(type);
112 return 0;
113 }
114 }
115
116 static i915_reg_t
117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
121 {
122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
125 case HDMI_INFOFRAME_TYPE_SPD:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_VENDOR:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
129 default:
130 MISSING_CASE(type);
131 return INVALID_MMIO_REG;
132 }
133 }
134
135 static void g4x_write_infoframe(struct drm_encoder *encoder,
136 enum hdmi_infoframe_type type,
137 const void *frame, ssize_t len)
138 {
139 const uint32_t *data = frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 u32 val = I915_READ(VIDEO_DIP_CTL);
143 int i;
144
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(type);
149
150 val &= ~g4x_infoframe_enable(type);
151
152 I915_WRITE(VIDEO_DIP_CTL, val);
153
154 mmiowb();
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
162 mmiowb();
163
164 val |= g4x_infoframe_enable(type);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
167
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
170 }
171
172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
174 {
175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
181
182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
187 }
188
189 static void ibx_write_infoframe(struct drm_encoder *encoder,
190 enum hdmi_infoframe_type type,
191 const void *frame, ssize_t len)
192 {
193 const uint32_t *data = frame;
194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
198 u32 val = I915_READ(reg);
199 int i;
200
201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
204 val |= g4x_infoframe_index(type);
205
206 val &= ~g4x_infoframe_enable(type);
207
208 I915_WRITE(reg, val);
209
210 mmiowb();
211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
218 mmiowb();
219
220 val |= g4x_infoframe_enable(type);
221 val &= ~VIDEO_DIP_FREQ_MASK;
222 val |= VIDEO_DIP_FREQ_VSYNC;
223
224 I915_WRITE(reg, val);
225 POSTING_READ(reg);
226 }
227
228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
230 {
231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
235 u32 val = I915_READ(reg);
236
237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
239
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
242
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
246 }
247
248 static void cpt_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
251 {
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
258 int i;
259
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
264
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
269
270 I915_WRITE(reg, val);
271
272 mmiowb();
273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
280 mmiowb();
281
282 val |= g4x_infoframe_enable(type);
283 val &= ~VIDEO_DIP_FREQ_MASK;
284 val |= VIDEO_DIP_FREQ_VSYNC;
285
286 I915_WRITE(reg, val);
287 POSTING_READ(reg);
288 }
289
290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
292 {
293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
296
297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
303 }
304
305 static void vlv_write_infoframe(struct drm_encoder *encoder,
306 enum hdmi_infoframe_type type,
307 const void *frame, ssize_t len)
308 {
309 const uint32_t *data = frame;
310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
314 u32 val = I915_READ(reg);
315 int i;
316
317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
321
322 val &= ~g4x_infoframe_enable(type);
323
324 I915_WRITE(reg, val);
325
326 mmiowb();
327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
334 mmiowb();
335
336 val |= g4x_infoframe_enable(type);
337 val &= ~VIDEO_DIP_FREQ_MASK;
338 val |= VIDEO_DIP_FREQ_VSYNC;
339
340 I915_WRITE(reg, val);
341 POSTING_READ(reg);
342 }
343
344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
346 {
347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
351
352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
357
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
361 }
362
363 static void hsw_write_infoframe(struct drm_encoder *encoder,
364 enum hdmi_infoframe_type type,
365 const void *frame, ssize_t len)
366 {
367 const uint32_t *data = frame;
368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
374 int i;
375 u32 val = I915_READ(ctl_reg);
376
377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
378
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
381
382 mmiowb();
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
386 data++;
387 }
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
392 mmiowb();
393
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
397 }
398
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
401 {
402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
404
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
408 }
409
410 /*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
429 {
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
433
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
445
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
447 }
448
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 const struct drm_display_mode *adjusted_mode)
451 {
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
455 int ret;
456
457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
463
464 if (intel_hdmi->rgb_quant_range_selectable) {
465 if (intel_crtc->config->limited_color_range)
466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
468 else
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
471 }
472
473 intel_write_infoframe(encoder, &frame);
474 }
475
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
477 {
478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
486
487 frame.spd.sdi = HDMI_SPD_SDI_PC;
488
489 intel_write_infoframe(encoder, &frame);
490 }
491
492 static void
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
494 const struct drm_display_mode *adjusted_mode)
495 {
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505 }
506
507 static void g4x_set_infoframes(struct drm_encoder *encoder,
508 bool enable,
509 const struct drm_display_mode *adjusted_mode)
510 {
511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
514 i915_reg_t reg = VIDEO_DIP_CTL;
515 u32 val = I915_READ(reg);
516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
517
518 assert_hdmi_port_disabled(intel_hdmi);
519
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
531 if (!enable) {
532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
541 I915_WRITE(reg, val);
542 POSTING_READ(reg);
543 return;
544 }
545
546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
556 val |= VIDEO_DIP_ENABLE;
557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
559
560 I915_WRITE(reg, val);
561 POSTING_READ(reg);
562
563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
566 }
567
568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569 {
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585 }
586
587 /*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599 {
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628 }
629
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631 {
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
634 i915_reg_t reg;
635 u32 val = 0;
636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv->dev))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
655 I915_WRITE(reg, val);
656
657 return val != 0;
658 }
659
660 static void ibx_set_infoframes(struct drm_encoder *encoder,
661 bool enable,
662 const struct drm_display_mode *adjusted_mode)
663 {
664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
669 u32 val = I915_READ(reg);
670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
671
672 assert_hdmi_port_disabled(intel_hdmi);
673
674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
677 if (!enable) {
678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
683 I915_WRITE(reg, val);
684 POSTING_READ(reg);
685 return;
686 }
687
688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
696 val |= VIDEO_DIP_ENABLE;
697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
700
701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
704 I915_WRITE(reg, val);
705 POSTING_READ(reg);
706
707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
710 }
711
712 static void cpt_set_infoframes(struct drm_encoder *encoder,
713 bool enable,
714 const struct drm_display_mode *adjusted_mode)
715 {
716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
720 u32 val = I915_READ(reg);
721
722 assert_hdmi_port_disabled(intel_hdmi);
723
724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
727 if (!enable) {
728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733 I915_WRITE(reg, val);
734 POSTING_READ(reg);
735 return;
736 }
737
738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
742
743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
746 I915_WRITE(reg, val);
747 POSTING_READ(reg);
748
749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
752 }
753
754 static void vlv_set_infoframes(struct drm_encoder *encoder,
755 bool enable,
756 const struct drm_display_mode *adjusted_mode)
757 {
758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
763 u32 val = I915_READ(reg);
764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
765
766 assert_hdmi_port_disabled(intel_hdmi);
767
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
771 if (!enable) {
772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
778 POSTING_READ(reg);
779 return;
780 }
781
782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
790 val |= VIDEO_DIP_ENABLE;
791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
794
795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
798 I915_WRITE(reg, val);
799 POSTING_READ(reg);
800
801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
804 }
805
806 static void hsw_set_infoframes(struct drm_encoder *encoder,
807 bool enable,
808 const struct drm_display_mode *adjusted_mode)
809 {
810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
814 u32 val = I915_READ(reg);
815
816 assert_hdmi_port_disabled(intel_hdmi);
817
818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
822 if (!enable) {
823 I915_WRITE(reg, val);
824 POSTING_READ(reg);
825 return;
826 }
827
828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
831 I915_WRITE(reg, val);
832 POSTING_READ(reg);
833
834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
837 }
838
839 static void intel_hdmi_prepare(struct intel_encoder *encoder)
840 {
841 struct drm_device *dev = encoder->base.dev;
842 struct drm_i915_private *dev_priv = dev->dev_private;
843 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
844 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
846 u32 hdmi_val;
847
848 hdmi_val = SDVO_ENCODING_HDMI;
849 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
850 hdmi_val |= HDMI_COLOR_RANGE_16_235;
851 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
852 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
854 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
855
856 if (crtc->config->pipe_bpp > 24)
857 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
858 else
859 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
860
861 if (crtc->config->has_hdmi_sink)
862 hdmi_val |= HDMI_MODE_SELECT_HDMI;
863
864 if (HAS_PCH_CPT(dev))
865 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
866 else if (IS_CHERRYVIEW(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
868 else
869 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
870
871 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
872 POSTING_READ(intel_hdmi->hdmi_reg);
873 }
874
875 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
876 enum pipe *pipe)
877 {
878 struct drm_device *dev = encoder->base.dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
881 enum intel_display_power_domain power_domain;
882 u32 tmp;
883 bool ret;
884
885 power_domain = intel_display_port_power_domain(encoder);
886 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
887 return false;
888
889 ret = false;
890
891 tmp = I915_READ(intel_hdmi->hdmi_reg);
892
893 if (!(tmp & SDVO_ENABLE))
894 goto out;
895
896 if (HAS_PCH_CPT(dev))
897 *pipe = PORT_TO_PIPE_CPT(tmp);
898 else if (IS_CHERRYVIEW(dev))
899 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
900 else
901 *pipe = PORT_TO_PIPE(tmp);
902
903 ret = true;
904
905 out:
906 intel_display_power_put(dev_priv, power_domain);
907
908 return ret;
909 }
910
911 static void intel_hdmi_get_config(struct intel_encoder *encoder,
912 struct intel_crtc_state *pipe_config)
913 {
914 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
915 struct drm_device *dev = encoder->base.dev;
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 u32 tmp, flags = 0;
918 int dotclock;
919
920 tmp = I915_READ(intel_hdmi->hdmi_reg);
921
922 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
923 flags |= DRM_MODE_FLAG_PHSYNC;
924 else
925 flags |= DRM_MODE_FLAG_NHSYNC;
926
927 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
928 flags |= DRM_MODE_FLAG_PVSYNC;
929 else
930 flags |= DRM_MODE_FLAG_NVSYNC;
931
932 if (tmp & HDMI_MODE_SELECT_HDMI)
933 pipe_config->has_hdmi_sink = true;
934
935 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
936 pipe_config->has_infoframe = true;
937
938 if (tmp & SDVO_AUDIO_ENABLE)
939 pipe_config->has_audio = true;
940
941 if (!HAS_PCH_SPLIT(dev) &&
942 tmp & HDMI_COLOR_RANGE_16_235)
943 pipe_config->limited_color_range = true;
944
945 pipe_config->base.adjusted_mode.flags |= flags;
946
947 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
948 dotclock = pipe_config->port_clock * 2 / 3;
949 else
950 dotclock = pipe_config->port_clock;
951
952 if (pipe_config->pixel_multiplier)
953 dotclock /= pipe_config->pixel_multiplier;
954
955 if (HAS_PCH_SPLIT(dev_priv->dev))
956 ironlake_check_encoder_dotclock(pipe_config, dotclock);
957
958 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
959 }
960
961 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
962 {
963 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
964
965 WARN_ON(!crtc->config->has_hdmi_sink);
966 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
967 pipe_name(crtc->pipe));
968 intel_audio_codec_enable(encoder);
969 }
970
971 static void g4x_enable_hdmi(struct intel_encoder *encoder)
972 {
973 struct drm_device *dev = encoder->base.dev;
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
976 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
977 u32 temp;
978
979 temp = I915_READ(intel_hdmi->hdmi_reg);
980
981 temp |= SDVO_ENABLE;
982 if (crtc->config->has_audio)
983 temp |= SDVO_AUDIO_ENABLE;
984
985 I915_WRITE(intel_hdmi->hdmi_reg, temp);
986 POSTING_READ(intel_hdmi->hdmi_reg);
987
988 if (crtc->config->has_audio)
989 intel_enable_hdmi_audio(encoder);
990 }
991
992 static void ibx_enable_hdmi(struct intel_encoder *encoder)
993 {
994 struct drm_device *dev = encoder->base.dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
997 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
998 u32 temp;
999
1000 temp = I915_READ(intel_hdmi->hdmi_reg);
1001
1002 temp |= SDVO_ENABLE;
1003 if (crtc->config->has_audio)
1004 temp |= SDVO_AUDIO_ENABLE;
1005
1006 /*
1007 * HW workaround, need to write this twice for issue
1008 * that may result in first write getting masked.
1009 */
1010 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1011 POSTING_READ(intel_hdmi->hdmi_reg);
1012 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1013 POSTING_READ(intel_hdmi->hdmi_reg);
1014
1015 /*
1016 * HW workaround, need to toggle enable bit off and on
1017 * for 12bpc with pixel repeat.
1018 *
1019 * FIXME: BSpec says this should be done at the end of
1020 * of the modeset sequence, so not sure if this isn't too soon.
1021 */
1022 if (crtc->config->pipe_bpp > 24 &&
1023 crtc->config->pixel_multiplier > 1) {
1024 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1025 POSTING_READ(intel_hdmi->hdmi_reg);
1026
1027 /*
1028 * HW workaround, need to write this twice for issue
1029 * that may result in first write getting masked.
1030 */
1031 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1032 POSTING_READ(intel_hdmi->hdmi_reg);
1033 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1034 POSTING_READ(intel_hdmi->hdmi_reg);
1035 }
1036
1037 if (crtc->config->has_audio)
1038 intel_enable_hdmi_audio(encoder);
1039 }
1040
1041 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1042 {
1043 struct drm_device *dev = encoder->base.dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1046 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1047 enum pipe pipe = crtc->pipe;
1048 u32 temp;
1049
1050 temp = I915_READ(intel_hdmi->hdmi_reg);
1051
1052 temp |= SDVO_ENABLE;
1053 if (crtc->config->has_audio)
1054 temp |= SDVO_AUDIO_ENABLE;
1055
1056 /*
1057 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1058 *
1059 * The procedure for 12bpc is as follows:
1060 * 1. disable HDMI clock gating
1061 * 2. enable HDMI with 8bpc
1062 * 3. enable HDMI with 12bpc
1063 * 4. enable HDMI clock gating
1064 */
1065
1066 if (crtc->config->pipe_bpp > 24) {
1067 I915_WRITE(TRANS_CHICKEN1(pipe),
1068 I915_READ(TRANS_CHICKEN1(pipe)) |
1069 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1070
1071 temp &= ~SDVO_COLOR_FORMAT_MASK;
1072 temp |= SDVO_COLOR_FORMAT_8bpc;
1073 }
1074
1075 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1076 POSTING_READ(intel_hdmi->hdmi_reg);
1077
1078 if (crtc->config->pipe_bpp > 24) {
1079 temp &= ~SDVO_COLOR_FORMAT_MASK;
1080 temp |= HDMI_COLOR_FORMAT_12bpc;
1081
1082 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1083 POSTING_READ(intel_hdmi->hdmi_reg);
1084
1085 I915_WRITE(TRANS_CHICKEN1(pipe),
1086 I915_READ(TRANS_CHICKEN1(pipe)) &
1087 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1088 }
1089
1090 if (crtc->config->has_audio)
1091 intel_enable_hdmi_audio(encoder);
1092 }
1093
1094 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1095 {
1096 }
1097
1098 static void intel_disable_hdmi(struct intel_encoder *encoder)
1099 {
1100 struct drm_device *dev = encoder->base.dev;
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1103 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1104 u32 temp;
1105
1106 temp = I915_READ(intel_hdmi->hdmi_reg);
1107
1108 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1109 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1110 POSTING_READ(intel_hdmi->hdmi_reg);
1111
1112 /*
1113 * HW workaround for IBX, we need to move the port
1114 * to transcoder A after disabling it to allow the
1115 * matching DP port to be enabled on transcoder A.
1116 */
1117 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1118 /*
1119 * We get CPU/PCH FIFO underruns on the other pipe when
1120 * doing the workaround. Sweep them under the rug.
1121 */
1122 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1123 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1124
1125 temp &= ~SDVO_PIPE_B_SELECT;
1126 temp |= SDVO_ENABLE;
1127 /*
1128 * HW workaround, need to write this twice for issue
1129 * that may result in first write getting masked.
1130 */
1131 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1132 POSTING_READ(intel_hdmi->hdmi_reg);
1133 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1134 POSTING_READ(intel_hdmi->hdmi_reg);
1135
1136 temp &= ~SDVO_ENABLE;
1137 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1138 POSTING_READ(intel_hdmi->hdmi_reg);
1139
1140 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1141 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1142 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1143 }
1144
1145 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1146 }
1147
1148 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1149 {
1150 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1151
1152 if (crtc->config->has_audio)
1153 intel_audio_codec_disable(encoder);
1154
1155 intel_disable_hdmi(encoder);
1156 }
1157
1158 static void pch_disable_hdmi(struct intel_encoder *encoder)
1159 {
1160 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1161
1162 if (crtc->config->has_audio)
1163 intel_audio_codec_disable(encoder);
1164 }
1165
1166 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1167 {
1168 intel_disable_hdmi(encoder);
1169 }
1170
1171 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1172 {
1173 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1174
1175 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1176 return 165000;
1177 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1178 return 300000;
1179 else
1180 return 225000;
1181 }
1182
1183 static enum drm_mode_status
1184 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1185 int clock, bool respect_dvi_limit)
1186 {
1187 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1188
1189 if (clock < 25000)
1190 return MODE_CLOCK_LOW;
1191 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1192 return MODE_CLOCK_HIGH;
1193
1194 /* BXT DPLL can't generate 223-240 MHz */
1195 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1196 return MODE_CLOCK_RANGE;
1197
1198 /* CHV DPLL can't generate 216-240 MHz */
1199 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1200 return MODE_CLOCK_RANGE;
1201
1202 return MODE_OK;
1203 }
1204
1205 static enum drm_mode_status
1206 intel_hdmi_mode_valid(struct drm_connector *connector,
1207 struct drm_display_mode *mode)
1208 {
1209 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1210 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1211 enum drm_mode_status status;
1212 int clock;
1213
1214 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1215 return MODE_NO_DBLESCAN;
1216
1217 clock = mode->clock;
1218 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1219 clock *= 2;
1220
1221 /* check if we can do 8bpc */
1222 status = hdmi_port_clock_valid(hdmi, clock, true);
1223
1224 /* if we can't do 8bpc we may still be able to do 12bpc */
1225 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1226 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1227
1228 return status;
1229 }
1230
1231 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1232 {
1233 struct drm_device *dev = crtc_state->base.crtc->dev;
1234 struct drm_atomic_state *state;
1235 struct intel_encoder *encoder;
1236 struct drm_connector *connector;
1237 struct drm_connector_state *connector_state;
1238 int count = 0, count_hdmi = 0;
1239 int i;
1240
1241 if (HAS_GMCH_DISPLAY(dev))
1242 return false;
1243
1244 state = crtc_state->base.state;
1245
1246 for_each_connector_in_state(state, connector, connector_state, i) {
1247 if (connector_state->crtc != crtc_state->base.crtc)
1248 continue;
1249
1250 encoder = to_intel_encoder(connector_state->best_encoder);
1251
1252 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1253 count++;
1254 }
1255
1256 /*
1257 * HDMI 12bpc affects the clocks, so it's only possible
1258 * when not cloning with other encoder types.
1259 */
1260 return count_hdmi > 0 && count_hdmi == count;
1261 }
1262
1263 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1264 struct intel_crtc_state *pipe_config)
1265 {
1266 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1267 struct drm_device *dev = encoder->base.dev;
1268 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1269 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1270 int clock_12bpc = clock_8bpc * 3 / 2;
1271 int desired_bpp;
1272
1273 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1274
1275 if (pipe_config->has_hdmi_sink)
1276 pipe_config->has_infoframe = true;
1277
1278 if (intel_hdmi->color_range_auto) {
1279 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1280 pipe_config->limited_color_range =
1281 pipe_config->has_hdmi_sink &&
1282 drm_match_cea_mode(adjusted_mode) > 1;
1283 } else {
1284 pipe_config->limited_color_range =
1285 intel_hdmi->limited_color_range;
1286 }
1287
1288 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1289 pipe_config->pixel_multiplier = 2;
1290 clock_8bpc *= 2;
1291 clock_12bpc *= 2;
1292 }
1293
1294 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1295 pipe_config->has_pch_encoder = true;
1296
1297 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1298 pipe_config->has_audio = true;
1299
1300 /*
1301 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1302 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1303 * outputs. We also need to check that the higher clock still fits
1304 * within limits.
1305 */
1306 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1307 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1308 hdmi_12bpc_possible(pipe_config)) {
1309 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1310 desired_bpp = 12*3;
1311
1312 /* Need to adjust the port link by 1.5x for 12bpc. */
1313 pipe_config->port_clock = clock_12bpc;
1314 } else {
1315 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1316 desired_bpp = 8*3;
1317
1318 pipe_config->port_clock = clock_8bpc;
1319 }
1320
1321 if (!pipe_config->bw_constrained) {
1322 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1323 pipe_config->pipe_bpp = desired_bpp;
1324 }
1325
1326 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1327 false) != MODE_OK) {
1328 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1329 return false;
1330 }
1331
1332 /* Set user selected PAR to incoming mode's member */
1333 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1334
1335 return true;
1336 }
1337
1338 static void
1339 intel_hdmi_unset_edid(struct drm_connector *connector)
1340 {
1341 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1342
1343 intel_hdmi->has_hdmi_sink = false;
1344 intel_hdmi->has_audio = false;
1345 intel_hdmi->rgb_quant_range_selectable = false;
1346
1347 kfree(to_intel_connector(connector)->detect_edid);
1348 to_intel_connector(connector)->detect_edid = NULL;
1349 }
1350
1351 static bool
1352 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1353 {
1354 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1355 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1356 struct edid *edid = NULL;
1357 bool connected = false;
1358
1359 if (force) {
1360 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1361
1362 edid = drm_get_edid(connector,
1363 intel_gmbus_get_adapter(dev_priv,
1364 intel_hdmi->ddc_bus));
1365
1366 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1367 }
1368
1369 to_intel_connector(connector)->detect_edid = edid;
1370 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1371 intel_hdmi->rgb_quant_range_selectable =
1372 drm_rgb_quant_range_selectable(edid);
1373
1374 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1375 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1376 intel_hdmi->has_audio =
1377 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1378
1379 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1380 intel_hdmi->has_hdmi_sink =
1381 drm_detect_hdmi_monitor(edid);
1382
1383 connected = true;
1384 }
1385
1386 return connected;
1387 }
1388
1389 static enum drm_connector_status
1390 intel_hdmi_detect(struct drm_connector *connector, bool force)
1391 {
1392 enum drm_connector_status status;
1393 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1394 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1395 bool live_status = false;
1396 unsigned int try;
1397
1398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1399 connector->base.id, connector->name);
1400
1401 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1402
1403 for (try = 0; !live_status && try < 9; try++) {
1404 if (try)
1405 msleep(10);
1406 live_status = intel_digital_port_connected(dev_priv,
1407 hdmi_to_dig_port(intel_hdmi));
1408 }
1409
1410 if (!live_status)
1411 DRM_DEBUG_KMS("Live status not up!");
1412
1413 intel_hdmi_unset_edid(connector);
1414
1415 if (intel_hdmi_set_edid(connector, live_status)) {
1416 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1417
1418 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1419 status = connector_status_connected;
1420 } else
1421 status = connector_status_disconnected;
1422
1423 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1424
1425 return status;
1426 }
1427
1428 static void
1429 intel_hdmi_force(struct drm_connector *connector)
1430 {
1431 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1432
1433 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1434 connector->base.id, connector->name);
1435
1436 intel_hdmi_unset_edid(connector);
1437
1438 if (connector->status != connector_status_connected)
1439 return;
1440
1441 intel_hdmi_set_edid(connector, true);
1442 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1443 }
1444
1445 static int intel_hdmi_get_modes(struct drm_connector *connector)
1446 {
1447 struct edid *edid;
1448
1449 edid = to_intel_connector(connector)->detect_edid;
1450 if (edid == NULL)
1451 return 0;
1452
1453 return intel_connector_update_modes(connector, edid);
1454 }
1455
1456 static bool
1457 intel_hdmi_detect_audio(struct drm_connector *connector)
1458 {
1459 bool has_audio = false;
1460 struct edid *edid;
1461
1462 edid = to_intel_connector(connector)->detect_edid;
1463 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1464 has_audio = drm_detect_monitor_audio(edid);
1465
1466 return has_audio;
1467 }
1468
1469 static int
1470 intel_hdmi_set_property(struct drm_connector *connector,
1471 struct drm_property *property,
1472 uint64_t val)
1473 {
1474 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1475 struct intel_digital_port *intel_dig_port =
1476 hdmi_to_dig_port(intel_hdmi);
1477 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1478 int ret;
1479
1480 ret = drm_object_property_set_value(&connector->base, property, val);
1481 if (ret)
1482 return ret;
1483
1484 if (property == dev_priv->force_audio_property) {
1485 enum hdmi_force_audio i = val;
1486 bool has_audio;
1487
1488 if (i == intel_hdmi->force_audio)
1489 return 0;
1490
1491 intel_hdmi->force_audio = i;
1492
1493 if (i == HDMI_AUDIO_AUTO)
1494 has_audio = intel_hdmi_detect_audio(connector);
1495 else
1496 has_audio = (i == HDMI_AUDIO_ON);
1497
1498 if (i == HDMI_AUDIO_OFF_DVI)
1499 intel_hdmi->has_hdmi_sink = 0;
1500
1501 intel_hdmi->has_audio = has_audio;
1502 goto done;
1503 }
1504
1505 if (property == dev_priv->broadcast_rgb_property) {
1506 bool old_auto = intel_hdmi->color_range_auto;
1507 bool old_range = intel_hdmi->limited_color_range;
1508
1509 switch (val) {
1510 case INTEL_BROADCAST_RGB_AUTO:
1511 intel_hdmi->color_range_auto = true;
1512 break;
1513 case INTEL_BROADCAST_RGB_FULL:
1514 intel_hdmi->color_range_auto = false;
1515 intel_hdmi->limited_color_range = false;
1516 break;
1517 case INTEL_BROADCAST_RGB_LIMITED:
1518 intel_hdmi->color_range_auto = false;
1519 intel_hdmi->limited_color_range = true;
1520 break;
1521 default:
1522 return -EINVAL;
1523 }
1524
1525 if (old_auto == intel_hdmi->color_range_auto &&
1526 old_range == intel_hdmi->limited_color_range)
1527 return 0;
1528
1529 goto done;
1530 }
1531
1532 if (property == connector->dev->mode_config.aspect_ratio_property) {
1533 switch (val) {
1534 case DRM_MODE_PICTURE_ASPECT_NONE:
1535 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1536 break;
1537 case DRM_MODE_PICTURE_ASPECT_4_3:
1538 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1539 break;
1540 case DRM_MODE_PICTURE_ASPECT_16_9:
1541 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1542 break;
1543 default:
1544 return -EINVAL;
1545 }
1546 goto done;
1547 }
1548
1549 return -EINVAL;
1550
1551 done:
1552 if (intel_dig_port->base.base.crtc)
1553 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1554
1555 return 0;
1556 }
1557
1558 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1559 {
1560 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1561 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1562 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1563
1564 intel_hdmi_prepare(encoder);
1565
1566 intel_hdmi->set_infoframes(&encoder->base,
1567 intel_crtc->config->has_hdmi_sink,
1568 adjusted_mode);
1569 }
1570
1571 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1572 {
1573 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1574 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1575 struct drm_device *dev = encoder->base.dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 struct intel_crtc *intel_crtc =
1578 to_intel_crtc(encoder->base.crtc);
1579 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1580 enum dpio_channel port = vlv_dport_to_channel(dport);
1581 int pipe = intel_crtc->pipe;
1582 u32 val;
1583
1584 /* Enable clock channels for this port */
1585 mutex_lock(&dev_priv->sb_lock);
1586 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1587 val = 0;
1588 if (pipe)
1589 val |= (1<<21);
1590 else
1591 val &= ~(1<<21);
1592 val |= 0x001000c4;
1593 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1594
1595 /* HDMI 1.0V-2dB */
1596 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1597 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1598 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1599 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1600 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1601 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1602 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1603 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1604
1605 /* Program lane clock */
1606 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1607 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1608 mutex_unlock(&dev_priv->sb_lock);
1609
1610 intel_hdmi->set_infoframes(&encoder->base,
1611 intel_crtc->config->has_hdmi_sink,
1612 adjusted_mode);
1613
1614 g4x_enable_hdmi(encoder);
1615
1616 vlv_wait_port_ready(dev_priv, dport, 0x0);
1617 }
1618
1619 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1620 {
1621 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1622 struct drm_device *dev = encoder->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct intel_crtc *intel_crtc =
1625 to_intel_crtc(encoder->base.crtc);
1626 enum dpio_channel port = vlv_dport_to_channel(dport);
1627 int pipe = intel_crtc->pipe;
1628
1629 intel_hdmi_prepare(encoder);
1630
1631 /* Program Tx lane resets to default */
1632 mutex_lock(&dev_priv->sb_lock);
1633 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1634 DPIO_PCS_TX_LANE2_RESET |
1635 DPIO_PCS_TX_LANE1_RESET);
1636 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1637 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1638 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1639 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1640 DPIO_PCS_CLK_SOFT_RESET);
1641
1642 /* Fix up inter-pair skew failure */
1643 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1644 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1645 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1646
1647 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1648 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1649 mutex_unlock(&dev_priv->sb_lock);
1650 }
1651
1652 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1653 bool reset)
1654 {
1655 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1656 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1657 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1658 enum pipe pipe = crtc->pipe;
1659 uint32_t val;
1660
1661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1662 if (reset)
1663 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1664 else
1665 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1666 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1667
1668 if (crtc->config->lane_count > 2) {
1669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1670 if (reset)
1671 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1672 else
1673 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1674 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1675 }
1676
1677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1678 val |= CHV_PCS_REQ_SOFTRESET_EN;
1679 if (reset)
1680 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1681 else
1682 val |= DPIO_PCS_CLK_SOFT_RESET;
1683 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1684
1685 if (crtc->config->lane_count > 2) {
1686 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1687 val |= CHV_PCS_REQ_SOFTRESET_EN;
1688 if (reset)
1689 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1690 else
1691 val |= DPIO_PCS_CLK_SOFT_RESET;
1692 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1693 }
1694 }
1695
1696 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1697 {
1698 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1699 struct drm_device *dev = encoder->base.dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 struct intel_crtc *intel_crtc =
1702 to_intel_crtc(encoder->base.crtc);
1703 enum dpio_channel ch = vlv_dport_to_channel(dport);
1704 enum pipe pipe = intel_crtc->pipe;
1705 u32 val;
1706
1707 intel_hdmi_prepare(encoder);
1708
1709 /*
1710 * Must trick the second common lane into life.
1711 * Otherwise we can't even access the PLL.
1712 */
1713 if (ch == DPIO_CH0 && pipe == PIPE_B)
1714 dport->release_cl2_override =
1715 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1716
1717 chv_phy_powergate_lanes(encoder, true, 0x0);
1718
1719 mutex_lock(&dev_priv->sb_lock);
1720
1721 /* Assert data lane reset */
1722 chv_data_lane_soft_reset(encoder, true);
1723
1724 /* program left/right clock distribution */
1725 if (pipe != PIPE_B) {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1727 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1728 if (ch == DPIO_CH0)
1729 val |= CHV_BUFLEFTENA1_FORCE;
1730 if (ch == DPIO_CH1)
1731 val |= CHV_BUFRIGHTENA1_FORCE;
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1733 } else {
1734 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1735 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1736 if (ch == DPIO_CH0)
1737 val |= CHV_BUFLEFTENA2_FORCE;
1738 if (ch == DPIO_CH1)
1739 val |= CHV_BUFRIGHTENA2_FORCE;
1740 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1741 }
1742
1743 /* program clock channel usage */
1744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1745 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1746 if (pipe != PIPE_B)
1747 val &= ~CHV_PCS_USEDCLKCHANNEL;
1748 else
1749 val |= CHV_PCS_USEDCLKCHANNEL;
1750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1751
1752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1753 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1754 if (pipe != PIPE_B)
1755 val &= ~CHV_PCS_USEDCLKCHANNEL;
1756 else
1757 val |= CHV_PCS_USEDCLKCHANNEL;
1758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1759
1760 /*
1761 * This a a bit weird since generally CL
1762 * matches the pipe, but here we need to
1763 * pick the CL based on the port.
1764 */
1765 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1766 if (pipe != PIPE_B)
1767 val &= ~CHV_CMN_USEDCLKCHANNEL;
1768 else
1769 val |= CHV_CMN_USEDCLKCHANNEL;
1770 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1771
1772 mutex_unlock(&dev_priv->sb_lock);
1773 }
1774
1775 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1776 {
1777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1778 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1779 u32 val;
1780
1781 mutex_lock(&dev_priv->sb_lock);
1782
1783 /* disable left/right clock distribution */
1784 if (pipe != PIPE_B) {
1785 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1786 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1787 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1788 } else {
1789 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1790 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1791 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1792 }
1793
1794 mutex_unlock(&dev_priv->sb_lock);
1795
1796 /*
1797 * Leave the power down bit cleared for at least one
1798 * lane so that chv_powergate_phy_ch() will power
1799 * on something when the channel is otherwise unused.
1800 * When the port is off and the override is removed
1801 * the lanes power down anyway, so otherwise it doesn't
1802 * really matter what the state of power down bits is
1803 * after this.
1804 */
1805 chv_phy_powergate_lanes(encoder, false, 0x0);
1806 }
1807
1808 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1809 {
1810 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1811 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1812 struct intel_crtc *intel_crtc =
1813 to_intel_crtc(encoder->base.crtc);
1814 enum dpio_channel port = vlv_dport_to_channel(dport);
1815 int pipe = intel_crtc->pipe;
1816
1817 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1818 mutex_lock(&dev_priv->sb_lock);
1819 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1820 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1821 mutex_unlock(&dev_priv->sb_lock);
1822 }
1823
1824 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1825 {
1826 struct drm_device *dev = encoder->base.dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829 mutex_lock(&dev_priv->sb_lock);
1830
1831 /* Assert data lane reset */
1832 chv_data_lane_soft_reset(encoder, true);
1833
1834 mutex_unlock(&dev_priv->sb_lock);
1835 }
1836
1837 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1838 {
1839 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1840 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1841 struct drm_device *dev = encoder->base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct intel_crtc *intel_crtc =
1844 to_intel_crtc(encoder->base.crtc);
1845 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1846 enum dpio_channel ch = vlv_dport_to_channel(dport);
1847 int pipe = intel_crtc->pipe;
1848 int data, i, stagger;
1849 u32 val;
1850
1851 mutex_lock(&dev_priv->sb_lock);
1852
1853 /* allow hardware to manage TX FIFO reset source */
1854 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1855 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1856 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1857
1858 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1859 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1860 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1861
1862 /* Program Tx latency optimal setting */
1863 for (i = 0; i < 4; i++) {
1864 /* Set the upar bit */
1865 data = (i == 1) ? 0x0 : 0x1;
1866 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1867 data << DPIO_UPAR_SHIFT);
1868 }
1869
1870 /* Data lane stagger programming */
1871 if (intel_crtc->config->port_clock > 270000)
1872 stagger = 0x18;
1873 else if (intel_crtc->config->port_clock > 135000)
1874 stagger = 0xd;
1875 else if (intel_crtc->config->port_clock > 67500)
1876 stagger = 0x7;
1877 else if (intel_crtc->config->port_clock > 33750)
1878 stagger = 0x4;
1879 else
1880 stagger = 0x2;
1881
1882 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1883 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1884 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1885
1886 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1887 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1888 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1889
1890 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1891 DPIO_LANESTAGGER_STRAP(stagger) |
1892 DPIO_LANESTAGGER_STRAP_OVRD |
1893 DPIO_TX1_STAGGER_MASK(0x1f) |
1894 DPIO_TX1_STAGGER_MULT(6) |
1895 DPIO_TX2_STAGGER_MULT(0));
1896
1897 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1898 DPIO_LANESTAGGER_STRAP(stagger) |
1899 DPIO_LANESTAGGER_STRAP_OVRD |
1900 DPIO_TX1_STAGGER_MASK(0x1f) |
1901 DPIO_TX1_STAGGER_MULT(7) |
1902 DPIO_TX2_STAGGER_MULT(5));
1903
1904 /* Deassert data lane reset */
1905 chv_data_lane_soft_reset(encoder, false);
1906
1907 /* Clear calc init */
1908 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1909 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1910 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1911 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1912 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1913
1914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1915 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1916 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1917 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1918 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1919
1920 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1921 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1922 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1923 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1924
1925 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1926 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1927 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1928 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1929
1930 /* FIXME: Program the support xxx V-dB */
1931 /* Use 800mV-0dB */
1932 for (i = 0; i < 4; i++) {
1933 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1934 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1935 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1936 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1937 }
1938
1939 for (i = 0; i < 4; i++) {
1940 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1941
1942 val &= ~DPIO_SWING_MARGIN000_MASK;
1943 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1944
1945 /*
1946 * Supposedly this value shouldn't matter when unique transition
1947 * scale is disabled, but in fact it does matter. Let's just
1948 * always program the same value and hope it's OK.
1949 */
1950 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1951 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1952
1953 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1954 }
1955
1956 /*
1957 * The document said it needs to set bit 27 for ch0 and bit 26
1958 * for ch1. Might be a typo in the doc.
1959 * For now, for this unique transition scale selection, set bit
1960 * 27 for ch0 and ch1.
1961 */
1962 for (i = 0; i < 4; i++) {
1963 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1964 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1965 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1966 }
1967
1968 /* Start swing calculation */
1969 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1970 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1971 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1972
1973 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1974 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1975 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1976
1977 mutex_unlock(&dev_priv->sb_lock);
1978
1979 intel_hdmi->set_infoframes(&encoder->base,
1980 intel_crtc->config->has_hdmi_sink,
1981 adjusted_mode);
1982
1983 g4x_enable_hdmi(encoder);
1984
1985 vlv_wait_port_ready(dev_priv, dport, 0x0);
1986
1987 /* Second common lane will stay alive on its own now */
1988 if (dport->release_cl2_override) {
1989 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1990 dport->release_cl2_override = false;
1991 }
1992 }
1993
1994 static void intel_hdmi_destroy(struct drm_connector *connector)
1995 {
1996 kfree(to_intel_connector(connector)->detect_edid);
1997 drm_connector_cleanup(connector);
1998 kfree(connector);
1999 }
2000
2001 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2002 .dpms = drm_atomic_helper_connector_dpms,
2003 .detect = intel_hdmi_detect,
2004 .force = intel_hdmi_force,
2005 .fill_modes = drm_helper_probe_single_connector_modes,
2006 .set_property = intel_hdmi_set_property,
2007 .atomic_get_property = intel_connector_atomic_get_property,
2008 .destroy = intel_hdmi_destroy,
2009 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2010 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2011 };
2012
2013 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2014 .get_modes = intel_hdmi_get_modes,
2015 .mode_valid = intel_hdmi_mode_valid,
2016 .best_encoder = intel_best_encoder,
2017 };
2018
2019 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2020 .destroy = intel_encoder_destroy,
2021 };
2022
2023 static void
2024 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2025 {
2026 intel_attach_force_audio_property(connector);
2027 intel_attach_broadcast_rgb_property(connector);
2028 intel_hdmi->color_range_auto = true;
2029 intel_attach_aspect_ratio_property(connector);
2030 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2031 }
2032
2033 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2034 struct intel_connector *intel_connector)
2035 {
2036 struct drm_connector *connector = &intel_connector->base;
2037 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2038 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2039 struct drm_device *dev = intel_encoder->base.dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041 enum port port = intel_dig_port->port;
2042 uint8_t alternate_ddc_pin;
2043
2044 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2045 DRM_MODE_CONNECTOR_HDMIA);
2046 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2047
2048 connector->interlace_allowed = 1;
2049 connector->doublescan_allowed = 0;
2050 connector->stereo_allowed = 1;
2051
2052 switch (port) {
2053 case PORT_B:
2054 if (IS_BROXTON(dev_priv))
2055 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2056 else
2057 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2058 /*
2059 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2060 * interrupts to check the external panel connection.
2061 */
2062 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2063 intel_encoder->hpd_pin = HPD_PORT_A;
2064 else
2065 intel_encoder->hpd_pin = HPD_PORT_B;
2066 break;
2067 case PORT_C:
2068 if (IS_BROXTON(dev_priv))
2069 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2070 else
2071 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2072 intel_encoder->hpd_pin = HPD_PORT_C;
2073 break;
2074 case PORT_D:
2075 if (WARN_ON(IS_BROXTON(dev_priv)))
2076 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2077 else if (IS_CHERRYVIEW(dev_priv))
2078 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2079 else
2080 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2081 intel_encoder->hpd_pin = HPD_PORT_D;
2082 break;
2083 case PORT_E:
2084 /* On SKL PORT E doesn't have seperate GMBUS pin
2085 * We rely on VBT to set a proper alternate GMBUS pin. */
2086 alternate_ddc_pin =
2087 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2088 switch (alternate_ddc_pin) {
2089 case DDC_PIN_B:
2090 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2091 break;
2092 case DDC_PIN_C:
2093 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2094 break;
2095 case DDC_PIN_D:
2096 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2097 break;
2098 default:
2099 MISSING_CASE(alternate_ddc_pin);
2100 }
2101 intel_encoder->hpd_pin = HPD_PORT_E;
2102 break;
2103 case PORT_A:
2104 intel_encoder->hpd_pin = HPD_PORT_A;
2105 /* Internal port only for eDP. */
2106 default:
2107 BUG();
2108 }
2109
2110 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2111 intel_hdmi->write_infoframe = vlv_write_infoframe;
2112 intel_hdmi->set_infoframes = vlv_set_infoframes;
2113 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2114 } else if (IS_G4X(dev)) {
2115 intel_hdmi->write_infoframe = g4x_write_infoframe;
2116 intel_hdmi->set_infoframes = g4x_set_infoframes;
2117 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2118 } else if (HAS_DDI(dev)) {
2119 intel_hdmi->write_infoframe = hsw_write_infoframe;
2120 intel_hdmi->set_infoframes = hsw_set_infoframes;
2121 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2122 } else if (HAS_PCH_IBX(dev)) {
2123 intel_hdmi->write_infoframe = ibx_write_infoframe;
2124 intel_hdmi->set_infoframes = ibx_set_infoframes;
2125 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2126 } else {
2127 intel_hdmi->write_infoframe = cpt_write_infoframe;
2128 intel_hdmi->set_infoframes = cpt_set_infoframes;
2129 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2130 }
2131
2132 if (HAS_DDI(dev))
2133 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2134 else
2135 intel_connector->get_hw_state = intel_connector_get_hw_state;
2136 intel_connector->unregister = intel_connector_unregister;
2137
2138 intel_hdmi_add_properties(intel_hdmi, connector);
2139
2140 intel_connector_attach_encoder(intel_connector, intel_encoder);
2141 drm_connector_register(connector);
2142 intel_hdmi->attached_connector = intel_connector;
2143
2144 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2145 * 0xd. Failure to do so will result in spurious interrupts being
2146 * generated on the port when a cable is not attached.
2147 */
2148 if (IS_G4X(dev) && !IS_GM45(dev)) {
2149 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2150 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2151 }
2152 }
2153
2154 void intel_hdmi_init(struct drm_device *dev,
2155 i915_reg_t hdmi_reg, enum port port)
2156 {
2157 struct intel_digital_port *intel_dig_port;
2158 struct intel_encoder *intel_encoder;
2159 struct intel_connector *intel_connector;
2160
2161 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2162 if (!intel_dig_port)
2163 return;
2164
2165 intel_connector = intel_connector_alloc();
2166 if (!intel_connector) {
2167 kfree(intel_dig_port);
2168 return;
2169 }
2170
2171 intel_encoder = &intel_dig_port->base;
2172
2173 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2174 DRM_MODE_ENCODER_TMDS, NULL);
2175
2176 intel_encoder->compute_config = intel_hdmi_compute_config;
2177 if (HAS_PCH_SPLIT(dev)) {
2178 intel_encoder->disable = pch_disable_hdmi;
2179 intel_encoder->post_disable = pch_post_disable_hdmi;
2180 } else {
2181 intel_encoder->disable = g4x_disable_hdmi;
2182 }
2183 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2184 intel_encoder->get_config = intel_hdmi_get_config;
2185 if (IS_CHERRYVIEW(dev)) {
2186 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2187 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2188 intel_encoder->enable = vlv_enable_hdmi;
2189 intel_encoder->post_disable = chv_hdmi_post_disable;
2190 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2191 } else if (IS_VALLEYVIEW(dev)) {
2192 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2193 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2194 intel_encoder->enable = vlv_enable_hdmi;
2195 intel_encoder->post_disable = vlv_hdmi_post_disable;
2196 } else {
2197 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2198 if (HAS_PCH_CPT(dev))
2199 intel_encoder->enable = cpt_enable_hdmi;
2200 else if (HAS_PCH_IBX(dev))
2201 intel_encoder->enable = ibx_enable_hdmi;
2202 else
2203 intel_encoder->enable = g4x_enable_hdmi;
2204 }
2205
2206 intel_encoder->type = INTEL_OUTPUT_HDMI;
2207 if (IS_CHERRYVIEW(dev)) {
2208 if (port == PORT_D)
2209 intel_encoder->crtc_mask = 1 << 2;
2210 else
2211 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2212 } else {
2213 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2214 }
2215 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2216 /*
2217 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2218 * to work on real hardware. And since g4x can send infoframes to
2219 * only one port anyway, nothing is lost by allowing it.
2220 */
2221 if (IS_G4X(dev))
2222 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2223
2224 intel_dig_port->port = port;
2225 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2226 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2227
2228 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2229 }
Linux kernel - Deliverables
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