2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
40 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
42 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
46 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
48 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
49 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
50 uint32_t enabled_bits
;
52 enabled_bits
= HAS_DDI(dev
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
54 WARN(I915_READ(intel_hdmi
->hdmi_reg
) & enabled_bits
,
55 "HDMI port enabled, expecting disabled\n");
58 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
60 struct intel_digital_port
*intel_dig_port
=
61 container_of(encoder
, struct intel_digital_port
, base
.base
);
62 return &intel_dig_port
->hdmi
;
65 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
67 return enc_to_intel_hdmi(&intel_attached_encoder(connector
)->base
);
70 static u32
g4x_infoframe_index(enum hdmi_infoframe_type type
)
73 case HDMI_INFOFRAME_TYPE_AVI
:
74 return VIDEO_DIP_SELECT_AVI
;
75 case HDMI_INFOFRAME_TYPE_SPD
:
76 return VIDEO_DIP_SELECT_SPD
;
77 case HDMI_INFOFRAME_TYPE_VENDOR
:
78 return VIDEO_DIP_SELECT_VENDOR
;
80 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
85 static u32
g4x_infoframe_enable(enum hdmi_infoframe_type type
)
88 case HDMI_INFOFRAME_TYPE_AVI
:
89 return VIDEO_DIP_ENABLE_AVI
;
90 case HDMI_INFOFRAME_TYPE_SPD
:
91 return VIDEO_DIP_ENABLE_SPD
;
92 case HDMI_INFOFRAME_TYPE_VENDOR
:
93 return VIDEO_DIP_ENABLE_VENDOR
;
95 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
100 static u32
hsw_infoframe_enable(enum hdmi_infoframe_type type
)
103 case HDMI_INFOFRAME_TYPE_AVI
:
104 return VIDEO_DIP_ENABLE_AVI_HSW
;
105 case HDMI_INFOFRAME_TYPE_SPD
:
106 return VIDEO_DIP_ENABLE_SPD_HSW
;
107 case HDMI_INFOFRAME_TYPE_VENDOR
:
108 return VIDEO_DIP_ENABLE_VS_HSW
;
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
115 static u32
hsw_infoframe_data_reg(enum hdmi_infoframe_type type
,
116 enum transcoder cpu_transcoder
)
119 case HDMI_INFOFRAME_TYPE_AVI
:
120 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
);
121 case HDMI_INFOFRAME_TYPE_SPD
:
122 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
);
123 case HDMI_INFOFRAME_TYPE_VENDOR
:
124 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
);
126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type
);
131 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
132 enum hdmi_infoframe_type type
,
133 const uint8_t *frame
, ssize_t len
)
135 uint32_t *data
= (uint32_t *)frame
;
136 struct drm_device
*dev
= encoder
->dev
;
137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
138 u32 val
= I915_READ(VIDEO_DIP_CTL
);
141 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
143 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
144 val
|= g4x_infoframe_index(type
);
146 val
&= ~g4x_infoframe_enable(type
);
148 I915_WRITE(VIDEO_DIP_CTL
, val
);
151 for (i
= 0; i
< len
; i
+= 4) {
152 I915_WRITE(VIDEO_DIP_DATA
, *data
);
155 /* Write every possible data byte to force correct ECC calculation. */
156 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
157 I915_WRITE(VIDEO_DIP_DATA
, 0);
160 val
|= g4x_infoframe_enable(type
);
161 val
&= ~VIDEO_DIP_FREQ_MASK
;
162 val
|= VIDEO_DIP_FREQ_VSYNC
;
164 I915_WRITE(VIDEO_DIP_CTL
, val
);
165 POSTING_READ(VIDEO_DIP_CTL
);
168 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
169 enum hdmi_infoframe_type type
,
170 const uint8_t *frame
, ssize_t len
)
172 uint32_t *data
= (uint32_t *)frame
;
173 struct drm_device
*dev
= encoder
->dev
;
174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
175 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
176 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
177 u32 val
= I915_READ(reg
);
179 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
181 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
182 val
|= g4x_infoframe_index(type
);
184 val
&= ~g4x_infoframe_enable(type
);
186 I915_WRITE(reg
, val
);
189 for (i
= 0; i
< len
; i
+= 4) {
190 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
193 /* Write every possible data byte to force correct ECC calculation. */
194 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
198 val
|= g4x_infoframe_enable(type
);
199 val
&= ~VIDEO_DIP_FREQ_MASK
;
200 val
|= VIDEO_DIP_FREQ_VSYNC
;
202 I915_WRITE(reg
, val
);
206 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
207 enum hdmi_infoframe_type type
,
208 const uint8_t *frame
, ssize_t len
)
210 uint32_t *data
= (uint32_t *)frame
;
211 struct drm_device
*dev
= encoder
->dev
;
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
214 int i
, reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
215 u32 val
= I915_READ(reg
);
217 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
219 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
220 val
|= g4x_infoframe_index(type
);
222 /* The DIP control register spec says that we need to update the AVI
223 * infoframe without clearing its enable bit */
224 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
225 val
&= ~g4x_infoframe_enable(type
);
227 I915_WRITE(reg
, val
);
230 for (i
= 0; i
< len
; i
+= 4) {
231 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
234 /* Write every possible data byte to force correct ECC calculation. */
235 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
239 val
|= g4x_infoframe_enable(type
);
240 val
&= ~VIDEO_DIP_FREQ_MASK
;
241 val
|= VIDEO_DIP_FREQ_VSYNC
;
243 I915_WRITE(reg
, val
);
247 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
248 enum hdmi_infoframe_type type
,
249 const uint8_t *frame
, ssize_t len
)
251 uint32_t *data
= (uint32_t *)frame
;
252 struct drm_device
*dev
= encoder
->dev
;
253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
254 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
255 int i
, reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
256 u32 val
= I915_READ(reg
);
258 WARN(!(val
& VIDEO_DIP_ENABLE
), "Writing DIP with CTL reg disabled\n");
260 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
261 val
|= g4x_infoframe_index(type
);
263 val
&= ~g4x_infoframe_enable(type
);
265 I915_WRITE(reg
, val
);
268 for (i
= 0; i
< len
; i
+= 4) {
269 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
272 /* Write every possible data byte to force correct ECC calculation. */
273 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
274 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
277 val
|= g4x_infoframe_enable(type
);
278 val
&= ~VIDEO_DIP_FREQ_MASK
;
279 val
|= VIDEO_DIP_FREQ_VSYNC
;
281 I915_WRITE(reg
, val
);
285 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
286 enum hdmi_infoframe_type type
,
287 const uint8_t *frame
, ssize_t len
)
289 uint32_t *data
= (uint32_t *)frame
;
290 struct drm_device
*dev
= encoder
->dev
;
291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
292 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
293 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
296 u32 val
= I915_READ(ctl_reg
);
298 data_reg
= hsw_infoframe_data_reg(type
,
299 intel_crtc
->config
.cpu_transcoder
);
303 val
&= ~hsw_infoframe_enable(type
);
304 I915_WRITE(ctl_reg
, val
);
307 for (i
= 0; i
< len
; i
+= 4) {
308 I915_WRITE(data_reg
+ i
, *data
);
311 /* Write every possible data byte to force correct ECC calculation. */
312 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
313 I915_WRITE(data_reg
+ i
, 0);
316 val
|= hsw_infoframe_enable(type
);
317 I915_WRITE(ctl_reg
, val
);
318 POSTING_READ(ctl_reg
);
322 * The data we write to the DIP data buffer registers is 1 byte bigger than the
323 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
324 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
325 * used for both technologies.
327 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
328 * DW1: DB3 | DB2 | DB1 | DB0
329 * DW2: DB7 | DB6 | DB5 | DB4
332 * (HB is Header Byte, DB is Data Byte)
334 * The hdmi pack() functions don't know about that hardware specific hole so we
335 * trick them by giving an offset into the buffer and moving back the header
338 static void intel_write_infoframe(struct drm_encoder
*encoder
,
339 union hdmi_infoframe
*frame
)
341 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
342 uint8_t buffer
[VIDEO_DIP_DATA_SIZE
];
345 /* see comment above for the reason for this offset */
346 len
= hdmi_infoframe_pack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
350 /* Insert the 'hole' (see big comment above) at position 3 */
351 buffer
[0] = buffer
[1];
352 buffer
[1] = buffer
[2];
353 buffer
[2] = buffer
[3];
357 intel_hdmi
->write_infoframe(encoder
, frame
->any
.type
, buffer
, len
);
360 static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
361 struct drm_display_mode
*adjusted_mode
)
363 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
364 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
365 union hdmi_infoframe frame
;
368 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
,
371 DRM_ERROR("couldn't fill AVI infoframe\n");
375 if (intel_hdmi
->rgb_quant_range_selectable
) {
376 if (intel_crtc
->config
.limited_color_range
)
377 frame
.avi
.quantization_range
=
378 HDMI_QUANTIZATION_RANGE_LIMITED
;
380 frame
.avi
.quantization_range
=
381 HDMI_QUANTIZATION_RANGE_FULL
;
384 intel_write_infoframe(encoder
, &frame
);
387 static void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
389 union hdmi_infoframe frame
;
392 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Intel", "Integrated gfx");
394 DRM_ERROR("couldn't fill SPD infoframe\n");
398 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
400 intel_write_infoframe(encoder
, &frame
);
404 intel_hdmi_set_hdmi_infoframe(struct drm_encoder
*encoder
,
405 struct drm_display_mode
*adjusted_mode
)
407 union hdmi_infoframe frame
;
410 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&frame
.vendor
.hdmi
,
415 intel_write_infoframe(encoder
, &frame
);
418 static void g4x_set_infoframes(struct drm_encoder
*encoder
,
419 struct drm_display_mode
*adjusted_mode
)
421 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
422 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
423 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
424 u32 reg
= VIDEO_DIP_CTL
;
425 u32 val
= I915_READ(reg
);
428 assert_hdmi_port_disabled(intel_hdmi
);
430 /* If the registers were not initialized yet, they might be zeroes,
431 * which means we're selecting the AVI DIP and we're setting its
432 * frequency to once. This seems to really confuse the HW and make
433 * things stop working (the register spec says the AVI always needs to
434 * be sent every VSync). So here we avoid writing to the register more
435 * than we need and also explicitly select the AVI DIP and explicitly
436 * set its frequency to every VSync. Avoiding to write it twice seems to
437 * be enough to solve the problem, but being defensive shouldn't hurt us
439 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
441 if (!intel_hdmi
->has_hdmi_sink
) {
442 if (!(val
& VIDEO_DIP_ENABLE
))
444 val
&= ~VIDEO_DIP_ENABLE
;
445 I915_WRITE(reg
, val
);
450 switch (intel_dig_port
->port
) {
452 port
= VIDEO_DIP_PORT_B
;
455 port
= VIDEO_DIP_PORT_C
;
462 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
463 if (val
& VIDEO_DIP_ENABLE
) {
464 val
&= ~VIDEO_DIP_ENABLE
;
465 I915_WRITE(reg
, val
);
468 val
&= ~VIDEO_DIP_PORT_MASK
;
472 val
|= VIDEO_DIP_ENABLE
;
473 val
&= ~VIDEO_DIP_ENABLE_VENDOR
;
475 I915_WRITE(reg
, val
);
478 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
479 intel_hdmi_set_spd_infoframe(encoder
);
480 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
483 static void ibx_set_infoframes(struct drm_encoder
*encoder
,
484 struct drm_display_mode
*adjusted_mode
)
486 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
487 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
488 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
489 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
490 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
491 u32 val
= I915_READ(reg
);
494 assert_hdmi_port_disabled(intel_hdmi
);
496 /* See the big comment in g4x_set_infoframes() */
497 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
499 if (!intel_hdmi
->has_hdmi_sink
) {
500 if (!(val
& VIDEO_DIP_ENABLE
))
502 val
&= ~VIDEO_DIP_ENABLE
;
503 I915_WRITE(reg
, val
);
508 switch (intel_dig_port
->port
) {
510 port
= VIDEO_DIP_PORT_B
;
513 port
= VIDEO_DIP_PORT_C
;
516 port
= VIDEO_DIP_PORT_D
;
523 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
524 if (val
& VIDEO_DIP_ENABLE
) {
525 val
&= ~VIDEO_DIP_ENABLE
;
526 I915_WRITE(reg
, val
);
529 val
&= ~VIDEO_DIP_PORT_MASK
;
533 val
|= VIDEO_DIP_ENABLE
;
534 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
535 VIDEO_DIP_ENABLE_GCP
);
537 I915_WRITE(reg
, val
);
540 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
541 intel_hdmi_set_spd_infoframe(encoder
);
542 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
545 static void cpt_set_infoframes(struct drm_encoder
*encoder
,
546 struct drm_display_mode
*adjusted_mode
)
548 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
549 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
550 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
551 u32 reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
552 u32 val
= I915_READ(reg
);
554 assert_hdmi_port_disabled(intel_hdmi
);
556 /* See the big comment in g4x_set_infoframes() */
557 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
559 if (!intel_hdmi
->has_hdmi_sink
) {
560 if (!(val
& VIDEO_DIP_ENABLE
))
562 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
);
563 I915_WRITE(reg
, val
);
568 /* Set both together, unset both together: see the spec. */
569 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
570 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
571 VIDEO_DIP_ENABLE_GCP
);
573 I915_WRITE(reg
, val
);
576 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
577 intel_hdmi_set_spd_infoframe(encoder
);
578 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
581 static void vlv_set_infoframes(struct drm_encoder
*encoder
,
582 struct drm_display_mode
*adjusted_mode
)
584 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
585 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
586 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
587 u32 reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
588 u32 val
= I915_READ(reg
);
590 assert_hdmi_port_disabled(intel_hdmi
);
592 /* See the big comment in g4x_set_infoframes() */
593 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
595 if (!intel_hdmi
->has_hdmi_sink
) {
596 if (!(val
& VIDEO_DIP_ENABLE
))
598 val
&= ~VIDEO_DIP_ENABLE
;
599 I915_WRITE(reg
, val
);
604 val
|= VIDEO_DIP_ENABLE
;
605 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
606 VIDEO_DIP_ENABLE_GCP
);
608 I915_WRITE(reg
, val
);
611 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
612 intel_hdmi_set_spd_infoframe(encoder
);
613 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
616 static void hsw_set_infoframes(struct drm_encoder
*encoder
,
617 struct drm_display_mode
*adjusted_mode
)
619 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
620 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
621 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
622 u32 reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->config
.cpu_transcoder
);
623 u32 val
= I915_READ(reg
);
625 assert_hdmi_port_disabled(intel_hdmi
);
627 if (!intel_hdmi
->has_hdmi_sink
) {
633 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_GCP_HSW
|
634 VIDEO_DIP_ENABLE_VS_HSW
| VIDEO_DIP_ENABLE_GMP_HSW
);
636 I915_WRITE(reg
, val
);
639 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
640 intel_hdmi_set_spd_infoframe(encoder
);
641 intel_hdmi_set_hdmi_infoframe(encoder
, adjusted_mode
);
644 static void intel_hdmi_mode_set(struct intel_encoder
*encoder
)
646 struct drm_device
*dev
= encoder
->base
.dev
;
647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
648 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
649 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
650 struct drm_display_mode
*adjusted_mode
= &crtc
->config
.adjusted_mode
;
653 hdmi_val
= SDVO_ENCODING_HDMI
;
654 if (!HAS_PCH_SPLIT(dev
))
655 hdmi_val
|= intel_hdmi
->color_range
;
656 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
657 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
658 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
659 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
661 if (crtc
->config
.pipe_bpp
> 24)
662 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
664 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
666 /* Required on CPT */
667 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
668 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
670 if (intel_hdmi
->has_audio
) {
671 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
672 pipe_name(crtc
->pipe
));
673 hdmi_val
|= SDVO_AUDIO_ENABLE
;
674 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
675 intel_write_eld(&encoder
->base
, adjusted_mode
);
678 if (HAS_PCH_CPT(dev
))
679 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
681 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
683 I915_WRITE(intel_hdmi
->hdmi_reg
, hdmi_val
);
684 POSTING_READ(intel_hdmi
->hdmi_reg
);
686 intel_hdmi
->set_infoframes(&encoder
->base
, adjusted_mode
);
689 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
692 struct drm_device
*dev
= encoder
->base
.dev
;
693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
694 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
697 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
699 if (!(tmp
& SDVO_ENABLE
))
702 if (HAS_PCH_CPT(dev
))
703 *pipe
= PORT_TO_PIPE_CPT(tmp
);
705 *pipe
= PORT_TO_PIPE(tmp
);
710 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
711 struct intel_crtc_config
*pipe_config
)
713 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
714 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
717 tmp
= I915_READ(intel_hdmi
->hdmi_reg
);
719 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
720 flags
|= DRM_MODE_FLAG_PHSYNC
;
722 flags
|= DRM_MODE_FLAG_NHSYNC
;
724 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
725 flags
|= DRM_MODE_FLAG_PVSYNC
;
727 flags
|= DRM_MODE_FLAG_NVSYNC
;
729 pipe_config
->adjusted_mode
.flags
|= flags
;
732 static void intel_enable_hdmi(struct intel_encoder
*encoder
)
734 struct drm_device
*dev
= encoder
->base
.dev
;
735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
737 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
739 u32 enable_bits
= SDVO_ENABLE
;
741 if (intel_hdmi
->has_audio
)
742 enable_bits
|= SDVO_AUDIO_ENABLE
;
744 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
746 /* HW workaround for IBX, we need to move the port to transcoder A
747 * before disabling it, so restore the transcoder select bit here. */
748 if (HAS_PCH_IBX(dev
))
749 enable_bits
|= SDVO_PIPE_SEL(intel_crtc
->pipe
);
751 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
752 * we do this anyway which shows more stable in testing.
754 if (HAS_PCH_SPLIT(dev
)) {
755 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
756 POSTING_READ(intel_hdmi
->hdmi_reg
);
761 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
762 POSTING_READ(intel_hdmi
->hdmi_reg
);
764 /* HW workaround, need to write this twice for issue that may result
765 * in first write getting masked.
767 if (HAS_PCH_SPLIT(dev
)) {
768 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
769 POSTING_READ(intel_hdmi
->hdmi_reg
);
773 static void vlv_enable_hdmi(struct intel_encoder
*encoder
)
777 static void intel_disable_hdmi(struct intel_encoder
*encoder
)
779 struct drm_device
*dev
= encoder
->base
.dev
;
780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
781 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
783 u32 enable_bits
= SDVO_ENABLE
| SDVO_AUDIO_ENABLE
;
785 temp
= I915_READ(intel_hdmi
->hdmi_reg
);
787 /* HW workaround for IBX, we need to move the port to transcoder A
788 * before disabling it. */
789 if (HAS_PCH_IBX(dev
)) {
790 struct drm_crtc
*crtc
= encoder
->base
.crtc
;
791 int pipe
= crtc
? to_intel_crtc(crtc
)->pipe
: -1;
793 if (temp
& SDVO_PIPE_B_SELECT
) {
794 temp
&= ~SDVO_PIPE_B_SELECT
;
795 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
796 POSTING_READ(intel_hdmi
->hdmi_reg
);
798 /* Again we need to write this twice. */
799 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
800 POSTING_READ(intel_hdmi
->hdmi_reg
);
802 /* Transcoder selection bits only update
803 * effectively on vblank. */
805 intel_wait_for_vblank(dev
, pipe
);
811 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
812 * we do this anyway which shows more stable in testing.
814 if (HAS_PCH_SPLIT(dev
)) {
815 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
& ~SDVO_ENABLE
);
816 POSTING_READ(intel_hdmi
->hdmi_reg
);
819 temp
&= ~enable_bits
;
821 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
822 POSTING_READ(intel_hdmi
->hdmi_reg
);
824 /* HW workaround, need to write this twice for issue that may result
825 * in first write getting masked.
827 if (HAS_PCH_SPLIT(dev
)) {
828 I915_WRITE(intel_hdmi
->hdmi_reg
, temp
);
829 POSTING_READ(intel_hdmi
->hdmi_reg
);
833 static int hdmi_portclock_limit(struct intel_hdmi
*hdmi
)
835 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
839 else if (IS_HASWELL(dev
))
845 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
846 struct drm_display_mode
*mode
)
848 if (mode
->clock
> hdmi_portclock_limit(intel_attached_hdmi(connector
)))
849 return MODE_CLOCK_HIGH
;
850 if (mode
->clock
< 20000)
851 return MODE_CLOCK_LOW
;
853 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
854 return MODE_NO_DBLESCAN
;
859 bool intel_hdmi_compute_config(struct intel_encoder
*encoder
,
860 struct intel_crtc_config
*pipe_config
)
862 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&encoder
->base
);
863 struct drm_device
*dev
= encoder
->base
.dev
;
864 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
865 int clock_12bpc
= pipe_config
->requested_mode
.clock
* 3 / 2;
866 int portclock_limit
= hdmi_portclock_limit(intel_hdmi
);
869 if (intel_hdmi
->color_range_auto
) {
870 /* See CEA-861-E - 5.1 Default Encoding Parameters */
871 if (intel_hdmi
->has_hdmi_sink
&&
872 drm_match_cea_mode(adjusted_mode
) > 1)
873 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
875 intel_hdmi
->color_range
= 0;
878 if (intel_hdmi
->color_range
)
879 pipe_config
->limited_color_range
= true;
881 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
))
882 pipe_config
->has_pch_encoder
= true;
885 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
886 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
887 * outputs. We also need to check that the higher clock still fits
890 if (pipe_config
->pipe_bpp
> 8*3 && clock_12bpc
<= portclock_limit
891 && HAS_PCH_SPLIT(dev
)) {
892 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
895 /* Need to adjust the port link by 1.5x for 12bpc. */
896 pipe_config
->port_clock
= clock_12bpc
;
898 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
902 if (!pipe_config
->bw_constrained
) {
903 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp
);
904 pipe_config
->pipe_bpp
= desired_bpp
;
907 if (adjusted_mode
->clock
> portclock_limit
) {
908 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
915 static enum drm_connector_status
916 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
918 struct drm_device
*dev
= connector
->dev
;
919 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
920 struct intel_digital_port
*intel_dig_port
=
921 hdmi_to_dig_port(intel_hdmi
);
922 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
923 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
925 enum drm_connector_status status
= connector_status_disconnected
;
927 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
928 connector
->base
.id
, drm_get_connector_name(connector
));
930 intel_hdmi
->has_hdmi_sink
= false;
931 intel_hdmi
->has_audio
= false;
932 intel_hdmi
->rgb_quant_range_selectable
= false;
933 edid
= drm_get_edid(connector
,
934 intel_gmbus_get_adapter(dev_priv
,
935 intel_hdmi
->ddc_bus
));
938 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
939 status
= connector_status_connected
;
940 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
941 intel_hdmi
->has_hdmi_sink
=
942 drm_detect_hdmi_monitor(edid
);
943 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
944 intel_hdmi
->rgb_quant_range_selectable
=
945 drm_rgb_quant_range_selectable(edid
);
950 if (status
== connector_status_connected
) {
951 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
952 intel_hdmi
->has_audio
=
953 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
954 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
960 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
962 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
963 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
965 /* We should parse the EDID data and find out if it's an HDMI sink so
966 * we can send audio to it.
969 return intel_ddc_get_modes(connector
,
970 intel_gmbus_get_adapter(dev_priv
,
971 intel_hdmi
->ddc_bus
));
975 intel_hdmi_detect_audio(struct drm_connector
*connector
)
977 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
978 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
980 bool has_audio
= false;
982 edid
= drm_get_edid(connector
,
983 intel_gmbus_get_adapter(dev_priv
,
984 intel_hdmi
->ddc_bus
));
986 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
987 has_audio
= drm_detect_monitor_audio(edid
);
995 intel_hdmi_set_property(struct drm_connector
*connector
,
996 struct drm_property
*property
,
999 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
1000 struct intel_digital_port
*intel_dig_port
=
1001 hdmi_to_dig_port(intel_hdmi
);
1002 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
1005 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
1009 if (property
== dev_priv
->force_audio_property
) {
1010 enum hdmi_force_audio i
= val
;
1013 if (i
== intel_hdmi
->force_audio
)
1016 intel_hdmi
->force_audio
= i
;
1018 if (i
== HDMI_AUDIO_AUTO
)
1019 has_audio
= intel_hdmi_detect_audio(connector
);
1021 has_audio
= (i
== HDMI_AUDIO_ON
);
1023 if (i
== HDMI_AUDIO_OFF_DVI
)
1024 intel_hdmi
->has_hdmi_sink
= 0;
1026 intel_hdmi
->has_audio
= has_audio
;
1030 if (property
== dev_priv
->broadcast_rgb_property
) {
1031 bool old_auto
= intel_hdmi
->color_range_auto
;
1032 uint32_t old_range
= intel_hdmi
->color_range
;
1035 case INTEL_BROADCAST_RGB_AUTO
:
1036 intel_hdmi
->color_range_auto
= true;
1038 case INTEL_BROADCAST_RGB_FULL
:
1039 intel_hdmi
->color_range_auto
= false;
1040 intel_hdmi
->color_range
= 0;
1042 case INTEL_BROADCAST_RGB_LIMITED
:
1043 intel_hdmi
->color_range_auto
= false;
1044 intel_hdmi
->color_range
= HDMI_COLOR_RANGE_16_235
;
1050 if (old_auto
== intel_hdmi
->color_range_auto
&&
1051 old_range
== intel_hdmi
->color_range
)
1060 if (intel_dig_port
->base
.base
.crtc
)
1061 intel_crtc_restore_mode(intel_dig_port
->base
.base
.crtc
);
1066 static void intel_hdmi_pre_enable(struct intel_encoder
*encoder
)
1068 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1069 struct drm_device
*dev
= encoder
->base
.dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 struct intel_crtc
*intel_crtc
=
1072 to_intel_crtc(encoder
->base
.crtc
);
1073 int port
= vlv_dport_to_channel(dport
);
1074 int pipe
= intel_crtc
->pipe
;
1077 if (!IS_VALLEYVIEW(dev
))
1080 /* Enable clock channels for this port */
1081 mutex_lock(&dev_priv
->dpio_lock
);
1082 val
= vlv_dpio_read(dev_priv
, DPIO_DATA_LANE_A(port
));
1089 vlv_dpio_write(dev_priv
, DPIO_DATA_CHANNEL(port
), val
);
1092 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
), 0);
1093 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL4(port
),
1095 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL2(port
),
1097 vlv_dpio_write(dev_priv
, DPIO_TX_SWING_CTL3(port
),
1099 vlv_dpio_write(dev_priv
, DPIO_TX3_SWING_CTL4(port
),
1101 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER0(port
), 0x00030000);
1102 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1104 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1105 DPIO_TX_OCALINIT_EN
);
1107 /* Program lane clock */
1108 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF0(port
),
1110 vlv_dpio_write(dev_priv
, DPIO_PCS_CLOCKBUF8(port
),
1112 mutex_unlock(&dev_priv
->dpio_lock
);
1114 intel_enable_hdmi(encoder
);
1116 vlv_wait_port_ready(dev_priv
, port
);
1119 static void intel_hdmi_pre_pll_enable(struct intel_encoder
*encoder
)
1121 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1122 struct drm_device
*dev
= encoder
->base
.dev
;
1123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1124 int port
= vlv_dport_to_channel(dport
);
1126 if (!IS_VALLEYVIEW(dev
))
1129 /* Program Tx lane resets to default */
1130 mutex_lock(&dev_priv
->dpio_lock
);
1131 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
),
1132 DPIO_PCS_TX_LANE2_RESET
|
1133 DPIO_PCS_TX_LANE1_RESET
);
1134 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
),
1135 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
1136 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
1137 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
1138 DPIO_PCS_CLK_SOFT_RESET
);
1140 /* Fix up inter-pair skew failure */
1141 vlv_dpio_write(dev_priv
, DPIO_PCS_STAGGER1(port
), 0x00750f00);
1142 vlv_dpio_write(dev_priv
, DPIO_TX_CTL(port
), 0x00001500);
1143 vlv_dpio_write(dev_priv
, DPIO_TX_LANE(port
), 0x40400000);
1145 vlv_dpio_write(dev_priv
, DPIO_PCS_CTL_OVER1(port
),
1147 vlv_dpio_write(dev_priv
, DPIO_TX_OCALINIT(port
),
1148 DPIO_TX_OCALINIT_EN
);
1149 mutex_unlock(&dev_priv
->dpio_lock
);
1152 static void intel_hdmi_post_disable(struct intel_encoder
*encoder
)
1154 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
1155 struct drm_i915_private
*dev_priv
= encoder
->base
.dev
->dev_private
;
1156 int port
= vlv_dport_to_channel(dport
);
1158 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1159 mutex_lock(&dev_priv
->dpio_lock
);
1160 vlv_dpio_write(dev_priv
, DPIO_PCS_TX(port
), 0x00000000);
1161 vlv_dpio_write(dev_priv
, DPIO_PCS_CLK(port
), 0x00e00060);
1162 mutex_unlock(&dev_priv
->dpio_lock
);
1165 static void intel_hdmi_destroy(struct drm_connector
*connector
)
1167 drm_sysfs_connector_remove(connector
);
1168 drm_connector_cleanup(connector
);
1172 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
1173 .dpms
= intel_connector_dpms
,
1174 .detect
= intel_hdmi_detect
,
1175 .fill_modes
= drm_helper_probe_single_connector_modes
,
1176 .set_property
= intel_hdmi_set_property
,
1177 .destroy
= intel_hdmi_destroy
,
1180 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
1181 .get_modes
= intel_hdmi_get_modes
,
1182 .mode_valid
= intel_hdmi_mode_valid
,
1183 .best_encoder
= intel_best_encoder
,
1186 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
1187 .destroy
= intel_encoder_destroy
,
1191 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
1193 intel_attach_force_audio_property(connector
);
1194 intel_attach_broadcast_rgb_property(connector
);
1195 intel_hdmi
->color_range_auto
= true;
1198 void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port
,
1199 struct intel_connector
*intel_connector
)
1201 struct drm_connector
*connector
= &intel_connector
->base
;
1202 struct intel_hdmi
*intel_hdmi
= &intel_dig_port
->hdmi
;
1203 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1204 struct drm_device
*dev
= intel_encoder
->base
.dev
;
1205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1206 enum port port
= intel_dig_port
->port
;
1208 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
1209 DRM_MODE_CONNECTOR_HDMIA
);
1210 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
1212 connector
->interlace_allowed
= 1;
1213 connector
->doublescan_allowed
= 0;
1217 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
1218 intel_encoder
->hpd_pin
= HPD_PORT_B
;
1221 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
1222 intel_encoder
->hpd_pin
= HPD_PORT_C
;
1225 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
1226 intel_encoder
->hpd_pin
= HPD_PORT_D
;
1229 intel_encoder
->hpd_pin
= HPD_PORT_A
;
1230 /* Internal port only for eDP. */
1235 if (IS_VALLEYVIEW(dev
)) {
1236 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
1237 intel_hdmi
->set_infoframes
= vlv_set_infoframes
;
1238 } else if (!HAS_PCH_SPLIT(dev
)) {
1239 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
1240 intel_hdmi
->set_infoframes
= g4x_set_infoframes
;
1241 } else if (HAS_DDI(dev
)) {
1242 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
1243 intel_hdmi
->set_infoframes
= hsw_set_infoframes
;
1244 } else if (HAS_PCH_IBX(dev
)) {
1245 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
1246 intel_hdmi
->set_infoframes
= ibx_set_infoframes
;
1248 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
1249 intel_hdmi
->set_infoframes
= cpt_set_infoframes
;
1253 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
1255 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
1257 intel_hdmi_add_properties(intel_hdmi
, connector
);
1259 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
1260 drm_sysfs_connector_add(connector
);
1262 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1263 * 0xd. Failure to do so will result in spurious interrupts being
1264 * generated on the port when a cable is not attached.
1266 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1267 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1268 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
1272 void intel_hdmi_init(struct drm_device
*dev
, int hdmi_reg
, enum port port
)
1274 struct intel_digital_port
*intel_dig_port
;
1275 struct intel_encoder
*intel_encoder
;
1276 struct intel_connector
*intel_connector
;
1278 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1279 if (!intel_dig_port
)
1282 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1283 if (!intel_connector
) {
1284 kfree(intel_dig_port
);
1288 intel_encoder
= &intel_dig_port
->base
;
1290 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
1291 DRM_MODE_ENCODER_TMDS
);
1293 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
1294 intel_encoder
->mode_set
= intel_hdmi_mode_set
;
1295 intel_encoder
->disable
= intel_disable_hdmi
;
1296 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
1297 intel_encoder
->get_config
= intel_hdmi_get_config
;
1298 if (IS_VALLEYVIEW(dev
)) {
1299 intel_encoder
->pre_pll_enable
= intel_hdmi_pre_pll_enable
;
1300 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
1301 intel_encoder
->enable
= vlv_enable_hdmi
;
1302 intel_encoder
->post_disable
= intel_hdmi_post_disable
;
1304 intel_encoder
->enable
= intel_enable_hdmi
;
1307 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
1308 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1309 intel_encoder
->cloneable
= false;
1311 intel_dig_port
->port
= port
;
1312 intel_dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
1313 intel_dig_port
->dp
.output_reg
= 0;
1315 intel_hdmi_init_connector(intel_dig_port
, intel_connector
);