2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
33 * These expanded contexts enable a number of new abilities, especially
34 * "Execlists" (also implemented in this file).
36 * Execlists are the new method by which, on gen8+ hardware, workloads are
37 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
41 #include <drm/i915_drm.h>
44 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
45 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
47 #define GEN8_LR_CONTEXT_ALIGN 4096
49 #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
50 #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
51 #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
53 #define CTX_LRI_HEADER_0 0x01
54 #define CTX_CONTEXT_CONTROL 0x02
55 #define CTX_RING_HEAD 0x04
56 #define CTX_RING_TAIL 0x06
57 #define CTX_RING_BUFFER_START 0x08
58 #define CTX_RING_BUFFER_CONTROL 0x0a
59 #define CTX_BB_HEAD_U 0x0c
60 #define CTX_BB_HEAD_L 0x0e
61 #define CTX_BB_STATE 0x10
62 #define CTX_SECOND_BB_HEAD_U 0x12
63 #define CTX_SECOND_BB_HEAD_L 0x14
64 #define CTX_SECOND_BB_STATE 0x16
65 #define CTX_BB_PER_CTX_PTR 0x18
66 #define CTX_RCS_INDIRECT_CTX 0x1a
67 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
68 #define CTX_LRI_HEADER_1 0x21
69 #define CTX_CTX_TIMESTAMP 0x22
70 #define CTX_PDP3_UDW 0x24
71 #define CTX_PDP3_LDW 0x26
72 #define CTX_PDP2_UDW 0x28
73 #define CTX_PDP2_LDW 0x2a
74 #define CTX_PDP1_UDW 0x2c
75 #define CTX_PDP1_LDW 0x2e
76 #define CTX_PDP0_UDW 0x30
77 #define CTX_PDP0_LDW 0x32
78 #define CTX_LRI_HEADER_2 0x41
79 #define CTX_R_PWR_CLK_STATE 0x42
80 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
82 #define GEN8_CTX_VALID (1<<0)
83 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
84 #define GEN8_CTX_FORCE_RESTORE (1<<2)
85 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
86 #define GEN8_CTX_PRIVILEGE (1<<8)
93 #define GEN8_CTX_MODE_SHIFT 3
96 FAULT_AND_HALT
, /* Debug only */
98 FAULT_AND_CONTINUE
/* Unsupported */
100 #define GEN8_CTX_ID_SHIFT 32
102 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
104 WARN_ON(i915
.enable_ppgtt
== -1);
106 if (enable_execlists
== 0)
109 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
110 i915
.use_mmio_flip
>= 0)
116 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
118 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
120 /* LRCA is required to be 4K aligned so the more significant 20 bits
121 * are globally unique */
125 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object
*ctx_obj
)
128 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
129 BUG_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
131 desc
= GEN8_CTX_VALID
;
132 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
133 desc
|= GEN8_CTX_L3LLC_COHERENT
;
134 desc
|= GEN8_CTX_PRIVILEGE
;
136 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
138 /* TODO: WaDisableLiteRestore when we start using semaphore
139 * signalling between Command Streamers */
140 /* desc |= GEN8_CTX_FORCE_RESTORE; */
145 static void execlists_elsp_write(struct intel_engine_cs
*ring
,
146 struct drm_i915_gem_object
*ctx_obj0
,
147 struct drm_i915_gem_object
*ctx_obj1
)
149 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
153 /* XXX: You must always write both descriptors in the order below. */
155 temp
= execlists_ctx_descriptor(ctx_obj1
);
158 desc
[1] = (u32
)(temp
>> 32);
161 temp
= execlists_ctx_descriptor(ctx_obj0
);
162 desc
[3] = (u32
)(temp
>> 32);
165 /* Set Force Wakeup bit to prevent GT from entering C6 while
166 * ELSP writes are in progress */
167 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
169 I915_WRITE(RING_ELSP(ring
), desc
[1]);
170 I915_WRITE(RING_ELSP(ring
), desc
[0]);
171 I915_WRITE(RING_ELSP(ring
), desc
[3]);
172 /* The context is automatically loaded after the following */
173 I915_WRITE(RING_ELSP(ring
), desc
[2]);
175 /* ELSP is a wo register, so use another nearby reg for posting instead */
176 POSTING_READ(RING_EXECLIST_STATUS(ring
));
178 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
181 static int execlists_ctx_write_tail(struct drm_i915_gem_object
*ctx_obj
, u32 tail
)
186 page
= i915_gem_object_get_page(ctx_obj
, 1);
187 reg_state
= kmap_atomic(page
);
189 reg_state
[CTX_RING_TAIL
+1] = tail
;
191 kunmap_atomic(reg_state
);
196 static int execlists_submit_context(struct intel_engine_cs
*ring
,
197 struct intel_context
*to0
, u32 tail0
,
198 struct intel_context
*to1
, u32 tail1
)
200 struct drm_i915_gem_object
*ctx_obj0
;
201 struct drm_i915_gem_object
*ctx_obj1
= NULL
;
203 ctx_obj0
= to0
->engine
[ring
->id
].state
;
205 BUG_ON(!i915_gem_obj_is_pinned(ctx_obj0
));
207 execlists_ctx_write_tail(ctx_obj0
, tail0
);
210 ctx_obj1
= to1
->engine
[ring
->id
].state
;
212 BUG_ON(!i915_gem_obj_is_pinned(ctx_obj1
));
214 execlists_ctx_write_tail(ctx_obj1
, tail1
);
217 execlists_elsp_write(ring
, ctx_obj0
, ctx_obj1
);
222 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer
*ringbuf
)
224 struct intel_engine_cs
*ring
= ringbuf
->ring
;
225 uint32_t flush_domains
;
229 if (ring
->gpu_caches_dirty
)
230 flush_domains
= I915_GEM_GPU_DOMAINS
;
232 ret
= ring
->emit_flush(ringbuf
, I915_GEM_GPU_DOMAINS
, flush_domains
);
236 ring
->gpu_caches_dirty
= false;
240 static int execlists_move_to_gpu(struct intel_ringbuffer
*ringbuf
,
241 struct list_head
*vmas
)
243 struct intel_engine_cs
*ring
= ringbuf
->ring
;
244 struct i915_vma
*vma
;
245 uint32_t flush_domains
= 0;
246 bool flush_chipset
= false;
249 list_for_each_entry(vma
, vmas
, exec_list
) {
250 struct drm_i915_gem_object
*obj
= vma
->obj
;
252 ret
= i915_gem_object_sync(obj
, ring
);
256 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
257 flush_chipset
|= i915_gem_clflush_object(obj
, false);
259 flush_domains
|= obj
->base
.write_domain
;
262 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
265 /* Unconditionally invalidate gpu caches and ensure that we do flush
266 * any residual writes from the previous batch.
268 return logical_ring_invalidate_all_caches(ringbuf
);
271 int intel_execlists_submission(struct drm_device
*dev
, struct drm_file
*file
,
272 struct intel_engine_cs
*ring
,
273 struct intel_context
*ctx
,
274 struct drm_i915_gem_execbuffer2
*args
,
275 struct list_head
*vmas
,
276 struct drm_i915_gem_object
*batch_obj
,
277 u64 exec_start
, u32 flags
)
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
280 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
285 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
286 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
287 switch (instp_mode
) {
288 case I915_EXEC_CONSTANTS_REL_GENERAL
:
289 case I915_EXEC_CONSTANTS_ABSOLUTE
:
290 case I915_EXEC_CONSTANTS_REL_SURFACE
:
291 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
292 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
296 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
297 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
298 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
302 /* The HW changed the meaning on this bit on gen6 */
303 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
307 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
311 if (args
->num_cliprects
!= 0) {
312 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
315 if (args
->DR4
== 0xffffffff) {
316 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
320 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
321 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
326 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
327 DRM_DEBUG("sol reset is gen7 only\n");
331 ret
= execlists_move_to_gpu(ringbuf
, vmas
);
335 if (ring
== &dev_priv
->ring
[RCS
] &&
336 instp_mode
!= dev_priv
->relative_constants_mode
) {
337 ret
= intel_logical_ring_begin(ringbuf
, 4);
341 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
342 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
343 intel_logical_ring_emit(ringbuf
, INSTPM
);
344 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
345 intel_logical_ring_advance(ringbuf
);
347 dev_priv
->relative_constants_mode
= instp_mode
;
350 ret
= ring
->emit_bb_start(ringbuf
, exec_start
, flags
);
354 i915_gem_execbuffer_move_to_active(vmas
, ring
);
355 i915_gem_execbuffer_retire_commands(dev
, file
, ring
, batch_obj
);
360 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
362 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
365 if (!intel_ring_initialized(ring
))
368 ret
= intel_ring_idle(ring
);
369 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
370 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
373 /* TODO: Is this correct with Execlists enabled? */
374 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
375 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
376 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
379 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
382 int logical_ring_flush_all_caches(struct intel_ringbuffer
*ringbuf
)
384 struct intel_engine_cs
*ring
= ringbuf
->ring
;
387 if (!ring
->gpu_caches_dirty
)
390 ret
= ring
->emit_flush(ringbuf
, 0, I915_GEM_GPU_DOMAINS
);
394 ring
->gpu_caches_dirty
= false;
398 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer
*ringbuf
)
400 struct intel_engine_cs
*ring
= ringbuf
->ring
;
401 struct intel_context
*ctx
= ringbuf
->FIXME_lrc_ctx
;
403 intel_logical_ring_advance(ringbuf
);
405 if (intel_ring_stopped(ring
))
408 /* FIXME: too cheeky, we don't even check if the ELSP is ready */
409 execlists_submit_context(ring
, ctx
, ringbuf
->tail
, NULL
, 0);
412 static int logical_ring_alloc_seqno(struct intel_engine_cs
*ring
,
413 struct intel_context
*ctx
)
415 if (ring
->outstanding_lazy_seqno
)
418 if (ring
->preallocated_lazy_request
== NULL
) {
419 struct drm_i915_gem_request
*request
;
421 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
425 /* Hold a reference to the context this request belongs to
426 * (we will need it when the time comes to emit/retire the
430 i915_gem_context_reference(request
->ctx
);
432 ring
->preallocated_lazy_request
= request
;
435 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
438 static int logical_ring_wait_request(struct intel_ringbuffer
*ringbuf
,
441 struct intel_engine_cs
*ring
= ringbuf
->ring
;
442 struct drm_i915_gem_request
*request
;
446 if (ringbuf
->last_retired_head
!= -1) {
447 ringbuf
->head
= ringbuf
->last_retired_head
;
448 ringbuf
->last_retired_head
= -1;
450 ringbuf
->space
= intel_ring_space(ringbuf
);
451 if (ringbuf
->space
>= bytes
)
455 list_for_each_entry(request
, &ring
->request_list
, list
) {
456 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
457 ringbuf
->size
) >= bytes
) {
458 seqno
= request
->seqno
;
466 ret
= i915_wait_seqno(ring
, seqno
);
470 i915_gem_retire_requests_ring(ring
);
471 ringbuf
->head
= ringbuf
->last_retired_head
;
472 ringbuf
->last_retired_head
= -1;
474 ringbuf
->space
= intel_ring_space(ringbuf
);
478 static int logical_ring_wait_for_space(struct intel_ringbuffer
*ringbuf
,
481 struct intel_engine_cs
*ring
= ringbuf
->ring
;
482 struct drm_device
*dev
= ring
->dev
;
483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
487 ret
= logical_ring_wait_request(ringbuf
, bytes
);
491 /* Force the context submission in case we have been skipping it */
492 intel_logical_ring_advance_and_submit(ringbuf
);
494 /* With GEM the hangcheck timer should kick us out of the loop,
495 * leaving it early runs the risk of corrupting GEM state (due
496 * to running on almost untested codepaths). But on resume
497 * timers don't work yet, so prevent a complete hang in that
498 * case by choosing an insanely large timeout. */
499 end
= jiffies
+ 60 * HZ
;
502 ringbuf
->head
= I915_READ_HEAD(ring
);
503 ringbuf
->space
= intel_ring_space(ringbuf
);
504 if (ringbuf
->space
>= bytes
) {
511 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
516 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
517 dev_priv
->mm
.interruptible
);
521 if (time_after(jiffies
, end
)) {
530 static int logical_ring_wrap_buffer(struct intel_ringbuffer
*ringbuf
)
532 uint32_t __iomem
*virt
;
533 int rem
= ringbuf
->size
- ringbuf
->tail
;
535 if (ringbuf
->space
< rem
) {
536 int ret
= logical_ring_wait_for_space(ringbuf
, rem
);
542 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
545 iowrite32(MI_NOOP
, virt
++);
548 ringbuf
->space
= intel_ring_space(ringbuf
);
553 static int logical_ring_prepare(struct intel_ringbuffer
*ringbuf
, int bytes
)
557 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
558 ret
= logical_ring_wrap_buffer(ringbuf
);
563 if (unlikely(ringbuf
->space
< bytes
)) {
564 ret
= logical_ring_wait_for_space(ringbuf
, bytes
);
572 int intel_logical_ring_begin(struct intel_ringbuffer
*ringbuf
, int num_dwords
)
574 struct intel_engine_cs
*ring
= ringbuf
->ring
;
575 struct drm_device
*dev
= ring
->dev
;
576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
579 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
580 dev_priv
->mm
.interruptible
);
584 ret
= logical_ring_prepare(ringbuf
, num_dwords
* sizeof(uint32_t));
588 /* Preallocate the olr before touching the ring */
589 ret
= logical_ring_alloc_seqno(ring
, ringbuf
->FIXME_lrc_ctx
);
593 ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
597 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
599 struct drm_device
*dev
= ring
->dev
;
600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
602 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
603 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
605 I915_WRITE(RING_MODE_GEN7(ring
),
606 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
607 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
608 POSTING_READ(RING_MODE_GEN7(ring
));
609 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
611 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
616 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
618 struct drm_device
*dev
= ring
->dev
;
619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
622 ret
= gen8_init_common_ring(ring
);
626 /* We need to disable the AsyncFlip performance optimisations in order
627 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
628 * programmed to '1' on all products.
630 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
632 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
634 ret
= intel_init_pipe_control(ring
);
638 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
643 static int gen8_emit_bb_start(struct intel_ringbuffer
*ringbuf
,
644 u64 offset
, unsigned flags
)
646 bool ppgtt
= !(flags
& I915_DISPATCH_SECURE
);
649 ret
= intel_logical_ring_begin(ringbuf
, 4);
653 /* FIXME(BDW): Address space and security selectors. */
654 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
655 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
656 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
657 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
658 intel_logical_ring_advance(ringbuf
);
663 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
665 struct drm_device
*dev
= ring
->dev
;
666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 if (!dev
->irq_enabled
)
672 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
673 if (ring
->irq_refcount
++ == 0) {
674 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
675 POSTING_READ(RING_IMR(ring
->mmio_base
));
677 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
682 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
684 struct drm_device
*dev
= ring
->dev
;
685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
688 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
689 if (--ring
->irq_refcount
== 0) {
690 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
691 POSTING_READ(RING_IMR(ring
->mmio_base
));
693 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
696 static int gen8_emit_flush(struct intel_ringbuffer
*ringbuf
,
697 u32 invalidate_domains
,
700 struct intel_engine_cs
*ring
= ringbuf
->ring
;
701 struct drm_device
*dev
= ring
->dev
;
702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
706 ret
= intel_logical_ring_begin(ringbuf
, 4);
710 cmd
= MI_FLUSH_DW
+ 1;
712 if (ring
== &dev_priv
->ring
[VCS
]) {
713 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
714 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
715 MI_FLUSH_DW_STORE_INDEX
|
716 MI_FLUSH_DW_OP_STOREDW
;
718 if (invalidate_domains
& I915_GEM_DOMAIN_RENDER
)
719 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
720 MI_FLUSH_DW_OP_STOREDW
;
723 intel_logical_ring_emit(ringbuf
, cmd
);
724 intel_logical_ring_emit(ringbuf
,
725 I915_GEM_HWS_SCRATCH_ADDR
|
726 MI_FLUSH_DW_USE_GTT
);
727 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
728 intel_logical_ring_emit(ringbuf
, 0); /* value */
729 intel_logical_ring_advance(ringbuf
);
734 static int gen8_emit_flush_render(struct intel_ringbuffer
*ringbuf
,
735 u32 invalidate_domains
,
738 struct intel_engine_cs
*ring
= ringbuf
->ring
;
739 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
743 flags
|= PIPE_CONTROL_CS_STALL
;
746 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
747 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
750 if (invalidate_domains
) {
751 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
752 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
753 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
754 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
755 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
756 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
757 flags
|= PIPE_CONTROL_QW_WRITE
;
758 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
761 ret
= intel_logical_ring_begin(ringbuf
, 6);
765 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
766 intel_logical_ring_emit(ringbuf
, flags
);
767 intel_logical_ring_emit(ringbuf
, scratch_addr
);
768 intel_logical_ring_emit(ringbuf
, 0);
769 intel_logical_ring_emit(ringbuf
, 0);
770 intel_logical_ring_emit(ringbuf
, 0);
771 intel_logical_ring_advance(ringbuf
);
776 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
778 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
781 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
783 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
786 static int gen8_emit_request(struct intel_ringbuffer
*ringbuf
)
788 struct intel_engine_cs
*ring
= ringbuf
->ring
;
792 ret
= intel_logical_ring_begin(ringbuf
, 6);
796 cmd
= MI_STORE_DWORD_IMM_GEN8
;
797 cmd
|= MI_GLOBAL_GTT
;
799 intel_logical_ring_emit(ringbuf
, cmd
);
800 intel_logical_ring_emit(ringbuf
,
801 (ring
->status_page
.gfx_addr
+
802 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
803 intel_logical_ring_emit(ringbuf
, 0);
804 intel_logical_ring_emit(ringbuf
, ring
->outstanding_lazy_seqno
);
805 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
806 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
807 intel_logical_ring_advance_and_submit(ringbuf
);
812 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
814 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
816 if (!intel_ring_initialized(ring
))
819 intel_logical_ring_stop(ring
);
820 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
821 ring
->preallocated_lazy_request
= NULL
;
822 ring
->outstanding_lazy_seqno
= 0;
827 i915_cmd_parser_fini_ring(ring
);
829 if (ring
->status_page
.obj
) {
830 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
831 ring
->status_page
.obj
= NULL
;
835 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
838 struct intel_context
*dctx
= ring
->default_context
;
839 struct drm_i915_gem_object
*dctx_obj
;
841 /* Intentionally left blank. */
845 INIT_LIST_HEAD(&ring
->active_list
);
846 INIT_LIST_HEAD(&ring
->request_list
);
847 init_waitqueue_head(&ring
->irq_queue
);
849 ret
= intel_lr_context_deferred_create(dctx
, ring
);
853 /* The status page is offset 0 from the context object in LRCs. */
854 dctx_obj
= dctx
->engine
[ring
->id
].state
;
855 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
);
856 ring
->status_page
.page_addr
= kmap(sg_page(dctx_obj
->pages
->sgl
));
857 if (ring
->status_page
.page_addr
== NULL
)
859 ring
->status_page
.obj
= dctx_obj
;
861 ret
= i915_cmd_parser_init_ring(ring
);
866 ret
= ring
->init(ring
);
874 static int logical_render_ring_init(struct drm_device
*dev
)
876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
877 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
879 ring
->name
= "render ring";
881 ring
->mmio_base
= RENDER_RING_BASE
;
882 ring
->irq_enable_mask
=
883 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
884 ring
->irq_keep_mask
=
885 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
887 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
889 ring
->init
= gen8_init_render_ring
;
890 ring
->cleanup
= intel_fini_pipe_control
;
891 ring
->get_seqno
= gen8_get_seqno
;
892 ring
->set_seqno
= gen8_set_seqno
;
893 ring
->emit_request
= gen8_emit_request
;
894 ring
->emit_flush
= gen8_emit_flush_render
;
895 ring
->irq_get
= gen8_logical_ring_get_irq
;
896 ring
->irq_put
= gen8_logical_ring_put_irq
;
897 ring
->emit_bb_start
= gen8_emit_bb_start
;
899 return logical_ring_init(dev
, ring
);
902 static int logical_bsd_ring_init(struct drm_device
*dev
)
904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
905 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
907 ring
->name
= "bsd ring";
909 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
910 ring
->irq_enable_mask
=
911 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
912 ring
->irq_keep_mask
=
913 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
915 ring
->init
= gen8_init_common_ring
;
916 ring
->get_seqno
= gen8_get_seqno
;
917 ring
->set_seqno
= gen8_set_seqno
;
918 ring
->emit_request
= gen8_emit_request
;
919 ring
->emit_flush
= gen8_emit_flush
;
920 ring
->irq_get
= gen8_logical_ring_get_irq
;
921 ring
->irq_put
= gen8_logical_ring_put_irq
;
922 ring
->emit_bb_start
= gen8_emit_bb_start
;
924 return logical_ring_init(dev
, ring
);
927 static int logical_bsd2_ring_init(struct drm_device
*dev
)
929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
930 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
932 ring
->name
= "bds2 ring";
934 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
935 ring
->irq_enable_mask
=
936 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
937 ring
->irq_keep_mask
=
938 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
940 ring
->init
= gen8_init_common_ring
;
941 ring
->get_seqno
= gen8_get_seqno
;
942 ring
->set_seqno
= gen8_set_seqno
;
943 ring
->emit_request
= gen8_emit_request
;
944 ring
->emit_flush
= gen8_emit_flush
;
945 ring
->irq_get
= gen8_logical_ring_get_irq
;
946 ring
->irq_put
= gen8_logical_ring_put_irq
;
947 ring
->emit_bb_start
= gen8_emit_bb_start
;
949 return logical_ring_init(dev
, ring
);
952 static int logical_blt_ring_init(struct drm_device
*dev
)
954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
955 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
957 ring
->name
= "blitter ring";
959 ring
->mmio_base
= BLT_RING_BASE
;
960 ring
->irq_enable_mask
=
961 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
962 ring
->irq_keep_mask
=
963 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
965 ring
->init
= gen8_init_common_ring
;
966 ring
->get_seqno
= gen8_get_seqno
;
967 ring
->set_seqno
= gen8_set_seqno
;
968 ring
->emit_request
= gen8_emit_request
;
969 ring
->emit_flush
= gen8_emit_flush
;
970 ring
->irq_get
= gen8_logical_ring_get_irq
;
971 ring
->irq_put
= gen8_logical_ring_put_irq
;
972 ring
->emit_bb_start
= gen8_emit_bb_start
;
974 return logical_ring_init(dev
, ring
);
977 static int logical_vebox_ring_init(struct drm_device
*dev
)
979 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
980 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
982 ring
->name
= "video enhancement ring";
984 ring
->mmio_base
= VEBOX_RING_BASE
;
985 ring
->irq_enable_mask
=
986 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
987 ring
->irq_keep_mask
=
988 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
990 ring
->init
= gen8_init_common_ring
;
991 ring
->get_seqno
= gen8_get_seqno
;
992 ring
->set_seqno
= gen8_set_seqno
;
993 ring
->emit_request
= gen8_emit_request
;
994 ring
->emit_flush
= gen8_emit_flush
;
995 ring
->irq_get
= gen8_logical_ring_get_irq
;
996 ring
->irq_put
= gen8_logical_ring_put_irq
;
997 ring
->emit_bb_start
= gen8_emit_bb_start
;
999 return logical_ring_init(dev
, ring
);
1002 int intel_logical_rings_init(struct drm_device
*dev
)
1004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1007 ret
= logical_render_ring_init(dev
);
1012 ret
= logical_bsd_ring_init(dev
);
1014 goto cleanup_render_ring
;
1018 ret
= logical_blt_ring_init(dev
);
1020 goto cleanup_bsd_ring
;
1023 if (HAS_VEBOX(dev
)) {
1024 ret
= logical_vebox_ring_init(dev
);
1026 goto cleanup_blt_ring
;
1029 if (HAS_BSD2(dev
)) {
1030 ret
= logical_bsd2_ring_init(dev
);
1032 goto cleanup_vebox_ring
;
1035 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
1037 goto cleanup_bsd2_ring
;
1042 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
1044 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
1046 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
1048 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
1049 cleanup_render_ring
:
1050 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
1056 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
1057 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
1059 struct drm_i915_gem_object
*ring_obj
= ringbuf
->obj
;
1060 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
1062 uint32_t *reg_state
;
1065 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
1067 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1071 ret
= i915_gem_object_get_pages(ctx_obj
);
1073 DRM_DEBUG_DRIVER("Could not get object pages\n");
1077 i915_gem_object_pin_pages(ctx_obj
);
1079 /* The second page of the context object contains some fields which must
1080 * be set up prior to the first execution. */
1081 page
= i915_gem_object_get_page(ctx_obj
, 1);
1082 reg_state
= kmap_atomic(page
);
1084 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1085 * commands followed by (reg, value) pairs. The values we are setting here are
1086 * only for the first context restore: on a subsequent save, the GPU will
1087 * recreate this batchbuffer with new values (including all the missing
1088 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1089 if (ring
->id
== RCS
)
1090 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
1092 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
1093 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
1094 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
1095 reg_state
[CTX_CONTEXT_CONTROL
+1] =
1096 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT
);
1097 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
1098 reg_state
[CTX_RING_HEAD
+1] = 0;
1099 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
1100 reg_state
[CTX_RING_TAIL
+1] = 0;
1101 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
1102 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(ring_obj
);
1103 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
1104 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
1105 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
1106 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
1107 reg_state
[CTX_BB_HEAD_U
+1] = 0;
1108 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
1109 reg_state
[CTX_BB_HEAD_L
+1] = 0;
1110 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
1111 reg_state
[CTX_BB_STATE
+1] = (1<<5);
1112 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
1113 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
1114 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
1115 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
1116 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
1117 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
1118 if (ring
->id
== RCS
) {
1119 /* TODO: according to BSpec, the register state context
1120 * for CHV does not have these. OTOH, these registers do
1121 * exist in CHV. I'm waiting for a clarification */
1122 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
1123 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
1124 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
1125 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
1126 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
1127 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
1129 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
1130 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
1131 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
1132 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
1133 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
1134 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
1135 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
1136 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
1137 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
1138 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
1139 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
1140 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
1141 reg_state
[CTX_PDP3_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[3]);
1142 reg_state
[CTX_PDP3_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[3]);
1143 reg_state
[CTX_PDP2_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[2]);
1144 reg_state
[CTX_PDP2_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[2]);
1145 reg_state
[CTX_PDP1_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[1]);
1146 reg_state
[CTX_PDP1_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[1]);
1147 reg_state
[CTX_PDP0_UDW
+1] = upper_32_bits(ppgtt
->pd_dma_addr
[0]);
1148 reg_state
[CTX_PDP0_LDW
+1] = lower_32_bits(ppgtt
->pd_dma_addr
[0]);
1149 if (ring
->id
== RCS
) {
1150 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
1151 reg_state
[CTX_R_PWR_CLK_STATE
] = 0x20c8;
1152 reg_state
[CTX_R_PWR_CLK_STATE
+1] = 0;
1155 kunmap_atomic(reg_state
);
1158 set_page_dirty(page
);
1159 i915_gem_object_unpin_pages(ctx_obj
);
1164 void intel_lr_context_free(struct intel_context
*ctx
)
1168 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1169 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
1170 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
1173 intel_destroy_ringbuffer_obj(ringbuf
);
1175 i915_gem_object_ggtt_unpin(ctx_obj
);
1176 drm_gem_object_unreference(&ctx_obj
->base
);
1181 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
1185 WARN_ON(INTEL_INFO(ring
->dev
)->gen
!= 8);
1189 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
1195 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
1202 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
1203 struct intel_engine_cs
*ring
)
1205 struct drm_device
*dev
= ring
->dev
;
1206 struct drm_i915_gem_object
*ctx_obj
;
1207 uint32_t context_size
;
1208 struct intel_ringbuffer
*ringbuf
;
1211 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
1212 if (ctx
->engine
[ring
->id
].state
)
1215 context_size
= round_up(get_lr_context_size(ring
), 4096);
1217 ctx_obj
= i915_gem_alloc_context_obj(dev
, context_size
);
1218 if (IS_ERR(ctx_obj
)) {
1219 ret
= PTR_ERR(ctx_obj
);
1220 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret
);
1224 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
1226 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret
);
1227 drm_gem_object_unreference(&ctx_obj
->base
);
1231 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1233 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1235 i915_gem_object_ggtt_unpin(ctx_obj
);
1236 drm_gem_object_unreference(&ctx_obj
->base
);
1241 ringbuf
->ring
= ring
;
1242 ringbuf
->FIXME_lrc_ctx
= ctx
;
1244 ringbuf
->size
= 32 * PAGE_SIZE
;
1245 ringbuf
->effective_size
= ringbuf
->size
;
1248 ringbuf
->space
= ringbuf
->size
;
1249 ringbuf
->last_retired_head
= -1;
1251 /* TODO: For now we put this in the mappable region so that we can reuse
1252 * the existing ringbuffer code which ioremaps it. When we start
1253 * creating many contexts, this will no longer work and we must switch
1254 * to a kmapish interface.
1256 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1258 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n",
1263 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
1265 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
1266 intel_destroy_ringbuffer_obj(ringbuf
);
1270 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
1271 ctx
->engine
[ring
->id
].state
= ctx_obj
;
1277 i915_gem_object_ggtt_unpin(ctx_obj
);
1278 drm_gem_object_unreference(&ctx_obj
->base
);