2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
211 ADVANCED_CONTEXT
= 0,
216 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
217 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
218 LEGACY_64B_CONTEXT :\
222 FAULT_AND_HALT
, /* Debug only */
224 FAULT_AND_CONTINUE
/* Unsupported */
226 #define GEN8_CTX_ID_SHIFT 32
227 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
228 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
230 static int intel_lr_context_pin(struct intel_context
*ctx
,
231 struct intel_engine_cs
*engine
);
234 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
236 * @enable_execlists: value of i915.enable_execlists module parameter.
238 * Only certain platforms support Execlists (the prerequisites being
239 * support for Logical Ring Contexts and Aliasing PPGTT or better).
241 * Return: 1 if Execlists is supported and has to be enabled.
243 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
245 WARN_ON(i915
.enable_ppgtt
== -1);
247 /* On platforms with execlist available, vGPU will only
248 * support execlist mode, no ring buffer mode.
250 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
253 if (INTEL_INFO(dev
)->gen
>= 9)
256 if (enable_execlists
== 0)
259 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
260 i915
.use_mmio_flip
>= 0)
267 logical_ring_init_platform_invariants(struct intel_engine_cs
*engine
)
269 struct drm_device
*dev
= engine
->dev
;
271 if (IS_GEN8(dev
) || IS_GEN9(dev
))
272 engine
->idle_lite_restore_wa
= ~0;
274 engine
->disable_lite_restore_wa
= (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
275 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) &&
276 (engine
->id
== VCS
|| engine
->id
== VCS2
);
278 engine
->ctx_desc_template
= GEN8_CTX_VALID
;
279 engine
->ctx_desc_template
|= GEN8_CTX_ADDRESSING_MODE(dev
) <<
280 GEN8_CTX_ADDRESSING_MODE_SHIFT
;
282 engine
->ctx_desc_template
|= GEN8_CTX_L3LLC_COHERENT
;
283 engine
->ctx_desc_template
|= GEN8_CTX_PRIVILEGE
;
285 /* TODO: WaDisableLiteRestore when we start using semaphore
286 * signalling between Command Streamers */
287 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
289 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
290 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
291 if (engine
->disable_lite_restore_wa
)
292 engine
->ctx_desc_template
|= GEN8_CTX_FORCE_RESTORE
;
296 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
297 * descriptor for a pinned context
299 * @ctx: Context to work on
300 * @ring: Engine the descriptor will be used with
302 * The context descriptor encodes various attributes of a context,
303 * including its GTT address and some flags. Because it's fairly
304 * expensive to calculate, we'll just do it once and cache the result,
305 * which remains valid until the context is unpinned.
307 * This is what a descriptor looks like, from LSB to MSB:
308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
310 * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
311 * bits 52-63: reserved, may encode the engine ID (for GuC)
314 intel_lr_context_descriptor_update(struct intel_context
*ctx
,
315 struct intel_engine_cs
*engine
)
319 lrca
= ctx
->engine
[engine
->id
].lrc_vma
->node
.start
+
320 LRC_PPHWSP_PN
* PAGE_SIZE
;
322 desc
= engine
->ctx_desc_template
; /* bits 0-11 */
323 desc
|= lrca
; /* bits 12-31 */
324 desc
|= (lrca
>> PAGE_SHIFT
) << GEN8_CTX_ID_SHIFT
; /* bits 32-51 */
326 ctx
->engine
[engine
->id
].lrc_desc
= desc
;
329 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
330 struct intel_engine_cs
*engine
)
332 return ctx
->engine
[engine
->id
].lrc_desc
;
336 * intel_execlists_ctx_id() - get the Execlists Context ID
337 * @ctx: Context to get the ID for
338 * @ring: Engine to get the ID for
340 * Do not confuse with ctx->id! Unfortunately we have a name overload
341 * here: the old context ID we pass to userspace as a handler so that
342 * they can refer to a context, and the new context ID we pass to the
343 * ELSP so that the GPU can inform us of the context status via
346 * The context ID is a portion of the context descriptor, so we can
347 * just extract the required part from the cached descriptor.
349 * Return: 20-bits globally unique context ID.
351 u32
intel_execlists_ctx_id(struct intel_context
*ctx
,
352 struct intel_engine_cs
*engine
)
354 return intel_lr_context_descriptor(ctx
, engine
) >> GEN8_CTX_ID_SHIFT
;
357 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
358 struct drm_i915_gem_request
*rq1
)
361 struct intel_engine_cs
*engine
= rq0
->engine
;
362 struct drm_device
*dev
= engine
->dev
;
363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
367 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->engine
);
368 rq1
->elsp_submitted
++;
373 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->engine
);
374 rq0
->elsp_submitted
++;
376 /* You must always write both descriptors in the order below. */
377 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[1]));
378 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[1]));
380 I915_WRITE_FW(RING_ELSP(engine
), upper_32_bits(desc
[0]));
381 /* The context is automatically loaded after the following */
382 I915_WRITE_FW(RING_ELSP(engine
), lower_32_bits(desc
[0]));
384 /* ELSP is a wo register, use another nearby reg for posting */
385 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine
));
389 execlists_update_context_pdps(struct i915_hw_ppgtt
*ppgtt
, u32
*reg_state
)
391 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
392 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
393 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
394 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
397 static void execlists_update_context(struct drm_i915_gem_request
*rq
)
399 struct intel_engine_cs
*engine
= rq
->engine
;
400 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
401 uint32_t *reg_state
= rq
->ctx
->engine
[engine
->id
].lrc_reg_state
;
403 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
405 /* True 32b PPGTT with dynamic page allocation: update PDP
406 * registers and point the unallocated PDPs to scratch page.
407 * PML4 is allocated during ppgtt init, so this is not needed
410 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
))
411 execlists_update_context_pdps(ppgtt
, reg_state
);
414 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
415 struct drm_i915_gem_request
*rq1
)
417 struct drm_i915_private
*dev_priv
= rq0
->i915
;
418 unsigned int fw_domains
= rq0
->engine
->fw_domains
;
420 execlists_update_context(rq0
);
423 execlists_update_context(rq1
);
425 spin_lock_irq(&dev_priv
->uncore
.lock
);
426 intel_uncore_forcewake_get__locked(dev_priv
, fw_domains
);
428 execlists_elsp_write(rq0
, rq1
);
430 intel_uncore_forcewake_put__locked(dev_priv
, fw_domains
);
431 spin_unlock_irq(&dev_priv
->uncore
.lock
);
434 static void execlists_context_unqueue(struct intel_engine_cs
*engine
)
436 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
437 struct drm_i915_gem_request
*cursor
, *tmp
;
439 assert_spin_locked(&engine
->execlist_lock
);
442 * If irqs are not active generate a warning as batches that finish
443 * without the irqs may get lost and a GPU Hang may occur.
445 WARN_ON(!intel_irqs_enabled(engine
->dev
->dev_private
));
447 /* Try to read in pairs */
448 list_for_each_entry_safe(cursor
, tmp
, &engine
->execlist_queue
,
452 } else if (req0
->ctx
== cursor
->ctx
) {
453 /* Same ctx: ignore first request, as second request
454 * will update tail past first request's workload */
455 cursor
->elsp_submitted
= req0
->elsp_submitted
;
456 list_move_tail(&req0
->execlist_link
,
457 &engine
->execlist_retired_req_list
);
461 WARN_ON(req1
->elsp_submitted
);
469 if (req0
->elsp_submitted
& engine
->idle_lite_restore_wa
) {
471 * WaIdleLiteRestore: make sure we never cause a lite restore
474 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
475 * resubmit the request. See gen8_emit_request() for where we
476 * prepare the padding after the end of the request.
478 struct intel_ringbuffer
*ringbuf
;
480 ringbuf
= req0
->ctx
->engine
[engine
->id
].ringbuf
;
482 req0
->tail
&= ringbuf
->size
- 1;
485 execlists_submit_requests(req0
, req1
);
489 execlists_check_remove_request(struct intel_engine_cs
*engine
, u32 request_id
)
491 struct drm_i915_gem_request
*head_req
;
493 assert_spin_locked(&engine
->execlist_lock
);
495 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
496 struct drm_i915_gem_request
,
502 if (unlikely(intel_execlists_ctx_id(head_req
->ctx
, engine
) != request_id
))
505 WARN(head_req
->elsp_submitted
== 0, "Never submitted head request\n");
507 if (--head_req
->elsp_submitted
> 0)
510 list_move_tail(&head_req
->execlist_link
,
511 &engine
->execlist_retired_req_list
);
517 get_context_status(struct intel_engine_cs
*engine
, unsigned int read_pointer
,
520 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
523 read_pointer
%= GEN8_CSB_ENTRIES
;
525 status
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine
, read_pointer
));
527 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
530 *context_id
= I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine
,
537 * intel_lrc_irq_handler() - handle Context Switch interrupts
538 * @engine: Engine Command Streamer to handle.
540 * Check the unread Context Status Buffers and manage the submission of new
541 * contexts to the ELSP accordingly.
543 static void intel_lrc_irq_handler(unsigned long data
)
545 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
546 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
548 unsigned int read_pointer
, write_pointer
;
549 u32 csb
[GEN8_CSB_ENTRIES
][2];
550 unsigned int csb_read
= 0, i
;
551 unsigned int submit_contexts
= 0;
553 intel_uncore_forcewake_get(dev_priv
, engine
->fw_domains
);
555 status_pointer
= I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine
));
557 read_pointer
= engine
->next_context_status_buffer
;
558 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
559 if (read_pointer
> write_pointer
)
560 write_pointer
+= GEN8_CSB_ENTRIES
;
562 while (read_pointer
< write_pointer
) {
563 if (WARN_ON_ONCE(csb_read
== GEN8_CSB_ENTRIES
))
565 csb
[csb_read
][0] = get_context_status(engine
, ++read_pointer
,
570 engine
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
572 /* Update the read pointer to the old write pointer. Manual ringbuffer
573 * management ftw </sarcasm> */
574 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine
),
575 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK
,
576 engine
->next_context_status_buffer
<< 8));
578 intel_uncore_forcewake_put(dev_priv
, engine
->fw_domains
);
580 spin_lock(&engine
->execlist_lock
);
582 for (i
= 0; i
< csb_read
; i
++) {
583 if (unlikely(csb
[i
][0] & GEN8_CTX_STATUS_PREEMPTED
)) {
584 if (csb
[i
][0] & GEN8_CTX_STATUS_LITE_RESTORE
) {
585 if (execlists_check_remove_request(engine
, csb
[i
][1]))
586 WARN(1, "Lite Restored request removed from queue\n");
588 WARN(1, "Preemption without Lite Restore\n");
591 if (csb
[i
][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE
|
592 GEN8_CTX_STATUS_ELEMENT_SWITCH
))
594 execlists_check_remove_request(engine
, csb
[i
][1]);
597 if (submit_contexts
) {
598 if (!engine
->disable_lite_restore_wa
||
599 (csb
[i
][0] & GEN8_CTX_STATUS_ACTIVE_IDLE
))
600 execlists_context_unqueue(engine
);
603 spin_unlock(&engine
->execlist_lock
);
605 if (unlikely(submit_contexts
> 2))
606 DRM_ERROR("More than two context complete events?\n");
609 static void execlists_context_queue(struct drm_i915_gem_request
*request
)
611 struct intel_engine_cs
*engine
= request
->engine
;
612 struct drm_i915_gem_request
*cursor
;
613 int num_elements
= 0;
615 if (request
->ctx
!= request
->i915
->kernel_context
)
616 intel_lr_context_pin(request
->ctx
, engine
);
618 i915_gem_request_reference(request
);
620 spin_lock_bh(&engine
->execlist_lock
);
622 list_for_each_entry(cursor
, &engine
->execlist_queue
, execlist_link
)
623 if (++num_elements
> 2)
626 if (num_elements
> 2) {
627 struct drm_i915_gem_request
*tail_req
;
629 tail_req
= list_last_entry(&engine
->execlist_queue
,
630 struct drm_i915_gem_request
,
633 if (request
->ctx
== tail_req
->ctx
) {
634 WARN(tail_req
->elsp_submitted
!= 0,
635 "More than 2 already-submitted reqs queued\n");
636 list_move_tail(&tail_req
->execlist_link
,
637 &engine
->execlist_retired_req_list
);
641 list_add_tail(&request
->execlist_link
, &engine
->execlist_queue
);
642 if (num_elements
== 0)
643 execlists_context_unqueue(engine
);
645 spin_unlock_bh(&engine
->execlist_lock
);
648 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
650 struct intel_engine_cs
*engine
= req
->engine
;
651 uint32_t flush_domains
;
655 if (engine
->gpu_caches_dirty
)
656 flush_domains
= I915_GEM_GPU_DOMAINS
;
658 ret
= engine
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
662 engine
->gpu_caches_dirty
= false;
666 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
667 struct list_head
*vmas
)
669 const unsigned other_rings
= ~intel_engine_flag(req
->engine
);
670 struct i915_vma
*vma
;
671 uint32_t flush_domains
= 0;
672 bool flush_chipset
= false;
675 list_for_each_entry(vma
, vmas
, exec_list
) {
676 struct drm_i915_gem_object
*obj
= vma
->obj
;
678 if (obj
->active
& other_rings
) {
679 ret
= i915_gem_object_sync(obj
, req
->engine
, &req
);
684 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
685 flush_chipset
|= i915_gem_clflush_object(obj
, false);
687 flush_domains
|= obj
->base
.write_domain
;
690 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
693 /* Unconditionally invalidate gpu caches and ensure that we do flush
694 * any residual writes from the previous batch.
696 return logical_ring_invalidate_all_caches(req
);
699 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
703 request
->ringbuf
= request
->ctx
->engine
[request
->engine
->id
].ringbuf
;
705 if (i915
.enable_guc_submission
) {
707 * Check that the GuC has space for the request before
708 * going any further, as the i915_add_request() call
709 * later on mustn't fail ...
711 struct intel_guc
*guc
= &request
->i915
->guc
;
713 ret
= i915_guc_wq_check_space(guc
->execbuf_client
);
718 if (request
->ctx
!= request
->i915
->kernel_context
)
719 ret
= intel_lr_context_pin(request
->ctx
, request
->engine
);
724 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
727 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
728 struct intel_engine_cs
*engine
= req
->engine
;
729 struct drm_i915_gem_request
*target
;
733 if (intel_ring_space(ringbuf
) >= bytes
)
736 /* The whole point of reserving space is to not wait! */
737 WARN_ON(ringbuf
->reserved_in_use
);
739 list_for_each_entry(target
, &engine
->request_list
, list
) {
741 * The request queue is per-engine, so can contain requests
742 * from multiple ringbuffers. Here, we must ignore any that
743 * aren't from the ringbuffer we're considering.
745 if (target
->ringbuf
!= ringbuf
)
748 /* Would completion of this request free enough space? */
749 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
755 if (WARN_ON(&target
->list
== &engine
->request_list
))
758 ret
= i915_wait_request(target
);
762 ringbuf
->space
= space
;
767 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
768 * @request: Request to advance the logical ringbuffer of.
770 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
771 * really happens during submission is that the context and current tail will be placed
772 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
773 * point, the tail *inside* the context is updated and the ELSP written to.
776 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
778 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
779 struct drm_i915_private
*dev_priv
= request
->i915
;
780 struct intel_engine_cs
*engine
= request
->engine
;
782 intel_logical_ring_advance(ringbuf
);
783 request
->tail
= ringbuf
->tail
;
786 * Here we add two extra NOOPs as padding to avoid
787 * lite restore of a context with HEAD==TAIL.
789 * Caller must reserve WA_TAIL_DWORDS for us!
791 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
792 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
793 intel_logical_ring_advance(ringbuf
);
795 if (intel_engine_stopped(engine
))
798 if (engine
->last_context
!= request
->ctx
) {
799 if (engine
->last_context
)
800 intel_lr_context_unpin(engine
->last_context
, engine
);
801 if (request
->ctx
!= request
->i915
->kernel_context
) {
802 intel_lr_context_pin(request
->ctx
, engine
);
803 engine
->last_context
= request
->ctx
;
805 engine
->last_context
= NULL
;
809 if (dev_priv
->guc
.execbuf_client
)
810 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
812 execlists_context_queue(request
);
817 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
819 uint32_t __iomem
*virt
;
820 int rem
= ringbuf
->size
- ringbuf
->tail
;
822 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
825 iowrite32(MI_NOOP
, virt
++);
828 intel_ring_update_space(ringbuf
);
831 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
833 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
834 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
835 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
836 int ret
, total_bytes
, wait_bytes
= 0;
837 bool need_wrap
= false;
839 if (ringbuf
->reserved_in_use
)
842 total_bytes
= bytes
+ ringbuf
->reserved_size
;
844 if (unlikely(bytes
> remain_usable
)) {
846 * Not enough space for the basic request. So need to flush
847 * out the remainder and then wait for base + reserved.
849 wait_bytes
= remain_actual
+ total_bytes
;
852 if (unlikely(total_bytes
> remain_usable
)) {
854 * The base request will fit but the reserved space
855 * falls off the end. So don't need an immediate wrap
856 * and only need to effectively wait for the reserved
857 * size space from the start of ringbuffer.
859 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
860 } else if (total_bytes
> ringbuf
->space
) {
861 /* No wrapping required, just waiting. */
862 wait_bytes
= total_bytes
;
867 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
872 __wrap_ring_buffer(ringbuf
);
879 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
881 * @req: The request to start some new work for
882 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
884 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
885 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
886 * and also preallocates a request (every workload submission is still mediated through
887 * requests, same as it did with legacy ringbuffer submission).
889 * Return: non-zero if the ringbuffer is not ready to be written to.
891 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
895 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
899 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
903 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
906 * The first call merely notes the reserve request and is common for
907 * all back ends. The subsequent localised _begin() call actually
908 * ensures that the reservation is available. Without the begin, if
909 * the request creator immediately submitted the request without
910 * adding any commands to it then there might not actually be
911 * sufficient room for the submission commands.
913 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
915 return intel_logical_ring_begin(request
, 0);
919 * execlists_submission() - submit a batchbuffer for execution, Execlists style
922 * @ring: Engine Command Streamer to submit to.
923 * @ctx: Context to employ for this submission.
924 * @args: execbuffer call arguments.
925 * @vmas: list of vmas.
926 * @batch_obj: the batchbuffer to submit.
927 * @exec_start: batchbuffer start virtual address pointer.
928 * @dispatch_flags: translated execbuffer call flags.
930 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
931 * away the submission details of the execbuffer ioctl call.
933 * Return: non-zero if the submission fails.
935 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
936 struct drm_i915_gem_execbuffer2
*args
,
937 struct list_head
*vmas
)
939 struct drm_device
*dev
= params
->dev
;
940 struct intel_engine_cs
*engine
= params
->engine
;
941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
942 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[engine
->id
].ringbuf
;
948 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
949 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
950 switch (instp_mode
) {
951 case I915_EXEC_CONSTANTS_REL_GENERAL
:
952 case I915_EXEC_CONSTANTS_ABSOLUTE
:
953 case I915_EXEC_CONSTANTS_REL_SURFACE
:
954 if (instp_mode
!= 0 && engine
!= &dev_priv
->engine
[RCS
]) {
955 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
959 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
960 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
961 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
965 /* The HW changed the meaning on this bit on gen6 */
966 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
970 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
974 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
975 DRM_DEBUG("sol reset is gen7 only\n");
979 ret
= execlists_move_to_gpu(params
->request
, vmas
);
983 if (engine
== &dev_priv
->engine
[RCS
] &&
984 instp_mode
!= dev_priv
->relative_constants_mode
) {
985 ret
= intel_logical_ring_begin(params
->request
, 4);
989 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
990 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
991 intel_logical_ring_emit_reg(ringbuf
, INSTPM
);
992 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
993 intel_logical_ring_advance(ringbuf
);
995 dev_priv
->relative_constants_mode
= instp_mode
;
998 exec_start
= params
->batch_obj_vm_offset
+
999 args
->batch_start_offset
;
1001 ret
= engine
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
1005 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
1007 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
1012 void intel_execlists_retire_requests(struct intel_engine_cs
*engine
)
1014 struct drm_i915_gem_request
*req
, *tmp
;
1015 struct list_head retired_list
;
1017 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
1018 if (list_empty(&engine
->execlist_retired_req_list
))
1021 INIT_LIST_HEAD(&retired_list
);
1022 spin_lock_bh(&engine
->execlist_lock
);
1023 list_replace_init(&engine
->execlist_retired_req_list
, &retired_list
);
1024 spin_unlock_bh(&engine
->execlist_lock
);
1026 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
1027 struct intel_context
*ctx
= req
->ctx
;
1028 struct drm_i915_gem_object
*ctx_obj
=
1029 ctx
->engine
[engine
->id
].state
;
1031 if (ctx_obj
&& (ctx
!= req
->i915
->kernel_context
))
1032 intel_lr_context_unpin(ctx
, engine
);
1034 list_del(&req
->execlist_link
);
1035 i915_gem_request_unreference(req
);
1039 void intel_logical_ring_stop(struct intel_engine_cs
*engine
)
1041 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1044 if (!intel_engine_initialized(engine
))
1047 ret
= intel_engine_idle(engine
);
1049 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1052 /* TODO: Is this correct with Execlists enabled? */
1053 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
1054 if (wait_for((I915_READ_MODE(engine
) & MODE_IDLE
) != 0, 1000)) {
1055 DRM_ERROR("%s :timed out trying to stop ring\n", engine
->name
);
1058 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
1061 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
1063 struct intel_engine_cs
*engine
= req
->engine
;
1066 if (!engine
->gpu_caches_dirty
)
1069 ret
= engine
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1073 engine
->gpu_caches_dirty
= false;
1077 static int intel_lr_context_do_pin(struct intel_context
*ctx
,
1078 struct intel_engine_cs
*engine
)
1080 struct drm_device
*dev
= engine
->dev
;
1081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1082 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1083 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[engine
->id
].ringbuf
;
1088 WARN_ON(!mutex_is_locked(&engine
->dev
->struct_mutex
));
1090 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1091 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1095 vaddr
= i915_gem_object_pin_map(ctx_obj
);
1096 if (IS_ERR(vaddr
)) {
1097 ret
= PTR_ERR(vaddr
);
1101 lrc_reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
1103 ret
= intel_pin_and_map_ringbuffer_obj(engine
->dev
, ringbuf
);
1107 ctx
->engine
[engine
->id
].lrc_vma
= i915_gem_obj_to_ggtt(ctx_obj
);
1108 intel_lr_context_descriptor_update(ctx
, engine
);
1109 lrc_reg_state
[CTX_RING_BUFFER_START
+1] = ringbuf
->vma
->node
.start
;
1110 ctx
->engine
[engine
->id
].lrc_reg_state
= lrc_reg_state
;
1111 ctx_obj
->dirty
= true;
1113 /* Invalidate GuC TLB. */
1114 if (i915
.enable_guc_submission
)
1115 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1120 i915_gem_object_unpin_map(ctx_obj
);
1122 i915_gem_object_ggtt_unpin(ctx_obj
);
1127 static int intel_lr_context_pin(struct intel_context
*ctx
,
1128 struct intel_engine_cs
*engine
)
1132 if (ctx
->engine
[engine
->id
].pin_count
++ == 0) {
1133 ret
= intel_lr_context_do_pin(ctx
, engine
);
1135 goto reset_pin_count
;
1137 i915_gem_context_reference(ctx
);
1142 ctx
->engine
[engine
->id
].pin_count
= 0;
1146 void intel_lr_context_unpin(struct intel_context
*ctx
,
1147 struct intel_engine_cs
*engine
)
1149 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
1151 WARN_ON(!mutex_is_locked(&ctx
->i915
->dev
->struct_mutex
));
1152 if (--ctx
->engine
[engine
->id
].pin_count
== 0) {
1153 i915_gem_object_unpin_map(ctx_obj
);
1154 intel_unpin_ringbuffer_obj(ctx
->engine
[engine
->id
].ringbuf
);
1155 i915_gem_object_ggtt_unpin(ctx_obj
);
1156 ctx
->engine
[engine
->id
].lrc_vma
= NULL
;
1157 ctx
->engine
[engine
->id
].lrc_desc
= 0;
1158 ctx
->engine
[engine
->id
].lrc_reg_state
= NULL
;
1160 i915_gem_context_unreference(ctx
);
1164 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1167 struct intel_engine_cs
*engine
= req
->engine
;
1168 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1169 struct drm_device
*dev
= engine
->dev
;
1170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1171 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1176 engine
->gpu_caches_dirty
= true;
1177 ret
= logical_ring_flush_all_caches(req
);
1181 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1185 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1186 for (i
= 0; i
< w
->count
; i
++) {
1187 intel_logical_ring_emit_reg(ringbuf
, w
->reg
[i
].addr
);
1188 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1190 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1192 intel_logical_ring_advance(ringbuf
);
1194 engine
->gpu_caches_dirty
= true;
1195 ret
= logical_ring_flush_all_caches(req
);
1202 #define wa_ctx_emit(batch, index, cmd) \
1204 int __index = (index)++; \
1205 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1208 batch[__index] = (cmd); \
1211 #define wa_ctx_emit_reg(batch, index, reg) \
1212 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
1215 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1216 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1217 * but there is a slight complication as this is applied in WA batch where the
1218 * values are only initialized once so we cannot take register value at the
1219 * beginning and reuse it further; hence we save its value to memory, upload a
1220 * constant value with bit21 set and then we restore it back with the saved value.
1221 * To simplify the WA, a constant value is formed by using the default value
1222 * of this register. This shouldn't be a problem because we are only modifying
1223 * it for a short period and this batch in non-premptible. We can ofcourse
1224 * use additional instructions that read the actual value of the register
1225 * at that time and set our bit of interest but it makes the WA complicated.
1227 * This WA is also required for Gen9 so extracting as a function avoids
1230 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*engine
,
1231 uint32_t *const batch
,
1234 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1237 * WaDisableLSQCROPERFforOCL:skl
1238 * This WA is implemented in skl_init_clock_gating() but since
1239 * this batch updates GEN8_L3SQCREG4 with default value we need to
1240 * set this bit here to retain the WA during flush.
1242 if (IS_SKL_REVID(engine
->dev
, 0, SKL_REVID_E0
))
1243 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1245 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1246 MI_SRM_LRM_GLOBAL_GTT
));
1247 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1248 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1249 wa_ctx_emit(batch
, index
, 0);
1251 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1252 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1253 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1255 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1256 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1257 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1258 wa_ctx_emit(batch
, index
, 0);
1259 wa_ctx_emit(batch
, index
, 0);
1260 wa_ctx_emit(batch
, index
, 0);
1261 wa_ctx_emit(batch
, index
, 0);
1263 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1264 MI_SRM_LRM_GLOBAL_GTT
));
1265 wa_ctx_emit_reg(batch
, index
, GEN8_L3SQCREG4
);
1266 wa_ctx_emit(batch
, index
, engine
->scratch
.gtt_offset
+ 256);
1267 wa_ctx_emit(batch
, index
, 0);
1272 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1274 uint32_t start_alignment
)
1276 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1279 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1281 uint32_t size_alignment
)
1283 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1285 WARN(wa_ctx
->size
% size_alignment
,
1286 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1287 wa_ctx
->size
, size_alignment
);
1292 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1294 * @ring: only applicable for RCS
1295 * @wa_ctx: structure representing wa_ctx
1296 * offset: specifies start of the batch, should be cache-aligned. This is updated
1297 * with the offset value received as input.
1298 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1299 * @batch: page in which WA are loaded
1300 * @offset: This field specifies the start of the batch, it should be
1301 * cache-aligned otherwise it is adjusted accordingly.
1302 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1303 * initialized at the beginning and shared across all contexts but this field
1304 * helps us to have multiple batches at different offsets and select them based
1305 * on a criteria. At the moment this batch always start at the beginning of the page
1306 * and at this point we don't have multiple wa_ctx batch buffers.
1308 * The number of WA applied are not known at the beginning; we use this field
1309 * to return the no of DWORDS written.
1311 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1312 * so it adds NOOPs as padding to make it cacheline aligned.
1313 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1314 * makes a complete batch buffer.
1316 * Return: non-zero if we exceed the PAGE_SIZE limit.
1319 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1320 struct i915_wa_ctx_bb
*wa_ctx
,
1321 uint32_t *const batch
,
1324 uint32_t scratch_addr
;
1325 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1327 /* WaDisableCtxRestoreArbitration:bdw,chv */
1328 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1330 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1331 if (IS_BROADWELL(engine
->dev
)) {
1332 int rc
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1338 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1339 /* Actual scratch location is at 128 bytes offset */
1340 scratch_addr
= engine
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1342 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1343 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1344 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1345 PIPE_CONTROL_CS_STALL
|
1346 PIPE_CONTROL_QW_WRITE
));
1347 wa_ctx_emit(batch
, index
, scratch_addr
);
1348 wa_ctx_emit(batch
, index
, 0);
1349 wa_ctx_emit(batch
, index
, 0);
1350 wa_ctx_emit(batch
, index
, 0);
1352 /* Pad to end of cacheline */
1353 while (index
% CACHELINE_DWORDS
)
1354 wa_ctx_emit(batch
, index
, MI_NOOP
);
1357 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1358 * execution depends on the length specified in terms of cache lines
1359 * in the register CTX_RCS_INDIRECT_CTX
1362 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1366 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1368 * @ring: only applicable for RCS
1369 * @wa_ctx: structure representing wa_ctx
1370 * offset: specifies start of the batch, should be cache-aligned.
1371 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1372 * @batch: page in which WA are loaded
1373 * @offset: This field specifies the start of this batch.
1374 * This batch is started immediately after indirect_ctx batch. Since we ensure
1375 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1377 * The number of DWORDS written are returned using this field.
1379 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1380 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1382 static int gen8_init_perctx_bb(struct intel_engine_cs
*engine
,
1383 struct i915_wa_ctx_bb
*wa_ctx
,
1384 uint32_t *const batch
,
1387 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1389 /* WaDisableCtxRestoreArbitration:bdw,chv */
1390 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1392 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1394 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1397 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*engine
,
1398 struct i915_wa_ctx_bb
*wa_ctx
,
1399 uint32_t *const batch
,
1403 struct drm_device
*dev
= engine
->dev
;
1404 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1406 /* WaDisableCtxRestoreArbitration:skl,bxt */
1407 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1408 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1409 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1411 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1412 ret
= gen8_emit_flush_coherentl3_wa(engine
, batch
, index
);
1417 /* Pad to end of cacheline */
1418 while (index
% CACHELINE_DWORDS
)
1419 wa_ctx_emit(batch
, index
, MI_NOOP
);
1421 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1424 static int gen9_init_perctx_bb(struct intel_engine_cs
*engine
,
1425 struct i915_wa_ctx_bb
*wa_ctx
,
1426 uint32_t *const batch
,
1429 struct drm_device
*dev
= engine
->dev
;
1430 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1432 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1433 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
1434 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1435 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1436 wa_ctx_emit_reg(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1437 wa_ctx_emit(batch
, index
,
1438 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1439 wa_ctx_emit(batch
, index
, MI_NOOP
);
1442 /* WaClearTdlStateAckDirtyBits:bxt */
1443 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1444 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(4));
1446 wa_ctx_emit_reg(batch
, index
, GEN8_STATE_ACK
);
1447 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1449 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE1
);
1450 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1452 wa_ctx_emit_reg(batch
, index
, GEN9_STATE_ACK_SLICE2
);
1453 wa_ctx_emit(batch
, index
, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS
));
1455 wa_ctx_emit_reg(batch
, index
, GEN7_ROW_CHICKEN2
);
1456 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1457 wa_ctx_emit(batch
, index
, 0x0);
1458 wa_ctx_emit(batch
, index
, MI_NOOP
);
1461 /* WaDisableCtxRestoreArbitration:skl,bxt */
1462 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
) ||
1463 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1464 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1466 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1468 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1471 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*engine
, u32 size
)
1475 engine
->wa_ctx
.obj
= i915_gem_alloc_object(engine
->dev
,
1477 if (!engine
->wa_ctx
.obj
) {
1478 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1482 ret
= i915_gem_obj_ggtt_pin(engine
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1484 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1486 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1493 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*engine
)
1495 if (engine
->wa_ctx
.obj
) {
1496 i915_gem_object_ggtt_unpin(engine
->wa_ctx
.obj
);
1497 drm_gem_object_unreference(&engine
->wa_ctx
.obj
->base
);
1498 engine
->wa_ctx
.obj
= NULL
;
1502 static int intel_init_workaround_bb(struct intel_engine_cs
*engine
)
1508 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
1510 WARN_ON(engine
->id
!= RCS
);
1512 /* update this when WA for higher Gen are added */
1513 if (INTEL_INFO(engine
->dev
)->gen
> 9) {
1514 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1515 INTEL_INFO(engine
->dev
)->gen
);
1519 /* some WA perform writes to scratch page, ensure it is valid */
1520 if (engine
->scratch
.obj
== NULL
) {
1521 DRM_ERROR("scratch page not allocated for %s\n", engine
->name
);
1525 ret
= lrc_setup_wa_ctx_obj(engine
, PAGE_SIZE
);
1527 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1531 page
= i915_gem_object_get_dirty_page(wa_ctx
->obj
, 0);
1532 batch
= kmap_atomic(page
);
1535 if (INTEL_INFO(engine
->dev
)->gen
== 8) {
1536 ret
= gen8_init_indirectctx_bb(engine
,
1537 &wa_ctx
->indirect_ctx
,
1543 ret
= gen8_init_perctx_bb(engine
,
1549 } else if (INTEL_INFO(engine
->dev
)->gen
== 9) {
1550 ret
= gen9_init_indirectctx_bb(engine
,
1551 &wa_ctx
->indirect_ctx
,
1557 ret
= gen9_init_perctx_bb(engine
,
1566 kunmap_atomic(batch
);
1568 lrc_destroy_wa_ctx_obj(engine
);
1573 static void lrc_init_hws(struct intel_engine_cs
*engine
)
1575 struct drm_i915_private
*dev_priv
= engine
->dev
->dev_private
;
1577 I915_WRITE(RING_HWS_PGA(engine
->mmio_base
),
1578 (u32
)engine
->status_page
.gfx_addr
);
1579 POSTING_READ(RING_HWS_PGA(engine
->mmio_base
));
1582 static int gen8_init_common_ring(struct intel_engine_cs
*engine
)
1584 struct drm_device
*dev
= engine
->dev
;
1585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1586 unsigned int next_context_status_buffer_hw
;
1588 lrc_init_hws(engine
);
1590 I915_WRITE_IMR(engine
,
1591 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1592 I915_WRITE(RING_HWSTAM(engine
->mmio_base
), 0xffffffff);
1594 I915_WRITE(RING_MODE_GEN7(engine
),
1595 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1596 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1597 POSTING_READ(RING_MODE_GEN7(engine
));
1600 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1601 * zero, we need to read the write pointer from hardware and use its
1602 * value because "this register is power context save restored".
1603 * Effectively, these states have been observed:
1605 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1606 * BDW | CSB regs not reset | CSB regs reset |
1607 * CHT | CSB regs not reset | CSB regs not reset |
1611 next_context_status_buffer_hw
=
1612 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine
)));
1615 * When the CSB registers are reset (also after power-up / gpu reset),
1616 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1617 * this special case, so the first element read is CSB[0].
1619 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1620 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1622 engine
->next_context_status_buffer
= next_context_status_buffer_hw
;
1623 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine
->name
);
1625 intel_engine_init_hangcheck(engine
);
1627 return intel_mocs_init_engine(engine
);
1630 static int gen8_init_render_ring(struct intel_engine_cs
*engine
)
1632 struct drm_device
*dev
= engine
->dev
;
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1636 ret
= gen8_init_common_ring(engine
);
1640 /* We need to disable the AsyncFlip performance optimisations in order
1641 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1642 * programmed to '1' on all products.
1644 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1646 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1648 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1650 return init_workarounds_ring(engine
);
1653 static int gen9_init_render_ring(struct intel_engine_cs
*engine
)
1657 ret
= gen8_init_common_ring(engine
);
1661 return init_workarounds_ring(engine
);
1664 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1666 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1667 struct intel_engine_cs
*engine
= req
->engine
;
1668 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1669 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1672 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1676 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1677 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1678 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1680 intel_logical_ring_emit_reg(ringbuf
,
1681 GEN8_RING_PDP_UDW(engine
, i
));
1682 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1683 intel_logical_ring_emit_reg(ringbuf
,
1684 GEN8_RING_PDP_LDW(engine
, i
));
1685 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1688 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1689 intel_logical_ring_advance(ringbuf
);
1694 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1695 u64 offset
, unsigned dispatch_flags
)
1697 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1698 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1701 /* Don't rely in hw updating PDPs, specially in lite-restore.
1702 * Ideally, we should set Force PD Restore in ctx descriptor,
1703 * but we can't. Force Restore would be a second option, but
1704 * it is unsafe in case of lite-restore (because the ctx is
1705 * not idle). PML4 is allocated during ppgtt init so this is
1706 * not needed in 48-bit.*/
1707 if (req
->ctx
->ppgtt
&&
1708 (intel_engine_flag(req
->engine
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1709 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1710 !intel_vgpu_active(req
->i915
->dev
)) {
1711 ret
= intel_logical_ring_emit_pdps(req
);
1716 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_engine_flag(req
->engine
);
1719 ret
= intel_logical_ring_begin(req
, 4);
1723 /* FIXME(BDW): Address space and security selectors. */
1724 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1726 (dispatch_flags
& I915_DISPATCH_RS
?
1727 MI_BATCH_RESOURCE_STREAMER
: 0));
1728 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1729 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1730 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1731 intel_logical_ring_advance(ringbuf
);
1736 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*engine
)
1738 struct drm_device
*dev
= engine
->dev
;
1739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1740 unsigned long flags
;
1742 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1745 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1746 if (engine
->irq_refcount
++ == 0) {
1747 I915_WRITE_IMR(engine
,
1748 ~(engine
->irq_enable_mask
| engine
->irq_keep_mask
));
1749 POSTING_READ(RING_IMR(engine
->mmio_base
));
1751 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1756 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*engine
)
1758 struct drm_device
*dev
= engine
->dev
;
1759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1760 unsigned long flags
;
1762 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1763 if (--engine
->irq_refcount
== 0) {
1764 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1765 POSTING_READ(RING_IMR(engine
->mmio_base
));
1767 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1770 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1771 u32 invalidate_domains
,
1774 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1775 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1776 struct drm_device
*dev
= engine
->dev
;
1777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1781 ret
= intel_logical_ring_begin(request
, 4);
1785 cmd
= MI_FLUSH_DW
+ 1;
1787 /* We always require a command barrier so that subsequent
1788 * commands, such as breadcrumb interrupts, are strictly ordered
1789 * wrt the contents of the write cache being flushed to memory
1790 * (and thus being coherent from the CPU).
1792 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1794 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1795 cmd
|= MI_INVALIDATE_TLB
;
1796 if (engine
== &dev_priv
->engine
[VCS
])
1797 cmd
|= MI_INVALIDATE_BSD
;
1800 intel_logical_ring_emit(ringbuf
, cmd
);
1801 intel_logical_ring_emit(ringbuf
,
1802 I915_GEM_HWS_SCRATCH_ADDR
|
1803 MI_FLUSH_DW_USE_GTT
);
1804 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1805 intel_logical_ring_emit(ringbuf
, 0); /* value */
1806 intel_logical_ring_advance(ringbuf
);
1811 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1812 u32 invalidate_domains
,
1815 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1816 struct intel_engine_cs
*engine
= ringbuf
->engine
;
1817 u32 scratch_addr
= engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1818 bool vf_flush_wa
= false;
1822 flags
|= PIPE_CONTROL_CS_STALL
;
1824 if (flush_domains
) {
1825 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1826 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1827 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
1828 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
1831 if (invalidate_domains
) {
1832 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1833 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1834 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1835 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1836 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1837 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1838 flags
|= PIPE_CONTROL_QW_WRITE
;
1839 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1842 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1845 if (IS_GEN9(engine
->dev
))
1849 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1854 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1855 intel_logical_ring_emit(ringbuf
, 0);
1856 intel_logical_ring_emit(ringbuf
, 0);
1857 intel_logical_ring_emit(ringbuf
, 0);
1858 intel_logical_ring_emit(ringbuf
, 0);
1859 intel_logical_ring_emit(ringbuf
, 0);
1862 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1863 intel_logical_ring_emit(ringbuf
, flags
);
1864 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1865 intel_logical_ring_emit(ringbuf
, 0);
1866 intel_logical_ring_emit(ringbuf
, 0);
1867 intel_logical_ring_emit(ringbuf
, 0);
1868 intel_logical_ring_advance(ringbuf
);
1873 static u32
gen8_get_seqno(struct intel_engine_cs
*engine
)
1875 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
1878 static void gen8_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1880 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1883 static void bxt_a_seqno_barrier(struct intel_engine_cs
*engine
)
1886 * On BXT A steppings there is a HW coherency issue whereby the
1887 * MI_STORE_DATA_IMM storing the completed request's seqno
1888 * occasionally doesn't invalidate the CPU cache. Work around this by
1889 * clflushing the corresponding cacheline whenever the caller wants
1890 * the coherency to be guaranteed. Note that this cacheline is known
1891 * to be clean at this point, since we only write it in
1892 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1893 * this clflush in practice becomes an invalidate operation.
1895 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1898 static void bxt_a_set_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
1900 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
1902 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1903 intel_flush_status_page(engine
, I915_GEM_HWS_INDEX
);
1907 * Reserve space for 2 NOOPs at the end of each request to be
1908 * used as a workaround for not being allowed to do lite
1909 * restore with HEAD==TAIL (WaIdleLiteRestore).
1911 #define WA_TAIL_DWORDS 2
1913 static inline u32
hws_seqno_address(struct intel_engine_cs
*engine
)
1915 return engine
->status_page
.gfx_addr
+ I915_GEM_HWS_INDEX_ADDR
;
1918 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1920 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1923 ret
= intel_logical_ring_begin(request
, 6 + WA_TAIL_DWORDS
);
1927 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1928 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR
& (1 << 5));
1930 intel_logical_ring_emit(ringbuf
,
1931 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1932 intel_logical_ring_emit(ringbuf
,
1933 hws_seqno_address(request
->engine
) |
1934 MI_FLUSH_DW_USE_GTT
);
1935 intel_logical_ring_emit(ringbuf
, 0);
1936 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1937 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1938 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1939 return intel_logical_ring_advance_and_submit(request
);
1942 static int gen8_emit_request_render(struct drm_i915_gem_request
*request
)
1944 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1947 ret
= intel_logical_ring_begin(request
, 8 + WA_TAIL_DWORDS
);
1951 /* We're using qword write, seqno should be aligned to 8 bytes. */
1952 BUILD_BUG_ON(I915_GEM_HWS_INDEX
& 1);
1954 /* w/a for post sync ops following a GPGPU operation we
1955 * need a prior CS_STALL, which is emitted by the flush
1956 * following the batch.
1958 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1959 intel_logical_ring_emit(ringbuf
,
1960 (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1961 PIPE_CONTROL_CS_STALL
|
1962 PIPE_CONTROL_QW_WRITE
));
1963 intel_logical_ring_emit(ringbuf
, hws_seqno_address(request
->engine
));
1964 intel_logical_ring_emit(ringbuf
, 0);
1965 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1966 /* We're thrashing one dword of HWS. */
1967 intel_logical_ring_emit(ringbuf
, 0);
1968 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1969 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1970 return intel_logical_ring_advance_and_submit(request
);
1973 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1975 struct render_state so
;
1978 ret
= i915_gem_render_state_prepare(req
->engine
, &so
);
1982 if (so
.rodata
== NULL
)
1985 ret
= req
->engine
->emit_bb_start(req
, so
.ggtt_offset
,
1986 I915_DISPATCH_SECURE
);
1990 ret
= req
->engine
->emit_bb_start(req
,
1991 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1992 I915_DISPATCH_SECURE
);
1996 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1999 i915_gem_render_state_fini(&so
);
2003 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
2007 ret
= intel_logical_ring_workarounds_emit(req
);
2011 ret
= intel_rcs_context_init_mocs(req
);
2013 * Failing to program the MOCS is non-fatal.The system will not
2014 * run at peak performance. So generate an error and carry on.
2017 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2019 return intel_lr_context_render_state_init(req
);
2023 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2025 * @ring: Engine Command Streamer.
2028 void intel_logical_ring_cleanup(struct intel_engine_cs
*engine
)
2030 struct drm_i915_private
*dev_priv
;
2032 if (!intel_engine_initialized(engine
))
2036 * Tasklet cannot be active at this point due intel_mark_active/idle
2037 * so this is just for documentation.
2039 if (WARN_ON(test_bit(TASKLET_STATE_SCHED
, &engine
->irq_tasklet
.state
)))
2040 tasklet_kill(&engine
->irq_tasklet
);
2042 dev_priv
= engine
->dev
->dev_private
;
2044 if (engine
->buffer
) {
2045 intel_logical_ring_stop(engine
);
2046 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2049 if (engine
->cleanup
)
2050 engine
->cleanup(engine
);
2052 i915_cmd_parser_fini_ring(engine
);
2053 i915_gem_batch_pool_fini(&engine
->batch_pool
);
2055 if (engine
->status_page
.obj
) {
2056 i915_gem_object_unpin_map(engine
->status_page
.obj
);
2057 engine
->status_page
.obj
= NULL
;
2060 engine
->idle_lite_restore_wa
= 0;
2061 engine
->disable_lite_restore_wa
= false;
2062 engine
->ctx_desc_template
= 0;
2064 lrc_destroy_wa_ctx_obj(engine
);
2069 logical_ring_default_vfuncs(struct drm_device
*dev
,
2070 struct intel_engine_cs
*engine
)
2072 /* Default vfuncs which can be overriden by each engine. */
2073 engine
->init_hw
= gen8_init_common_ring
;
2074 engine
->emit_request
= gen8_emit_request
;
2075 engine
->emit_flush
= gen8_emit_flush
;
2076 engine
->irq_get
= gen8_logical_ring_get_irq
;
2077 engine
->irq_put
= gen8_logical_ring_put_irq
;
2078 engine
->emit_bb_start
= gen8_emit_bb_start
;
2079 engine
->get_seqno
= gen8_get_seqno
;
2080 engine
->set_seqno
= gen8_set_seqno
;
2081 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
2082 engine
->irq_seqno_barrier
= bxt_a_seqno_barrier
;
2083 engine
->set_seqno
= bxt_a_set_seqno
;
2088 logical_ring_default_irqs(struct intel_engine_cs
*engine
, unsigned shift
)
2090 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< shift
;
2091 engine
->irq_keep_mask
= GT_CONTEXT_SWITCH_INTERRUPT
<< shift
;
2095 lrc_setup_hws(struct intel_engine_cs
*engine
,
2096 struct drm_i915_gem_object
*dctx_obj
)
2100 /* The HWSP is part of the default context object in LRC mode. */
2101 engine
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(dctx_obj
) +
2102 LRC_PPHWSP_PN
* PAGE_SIZE
;
2103 hws
= i915_gem_object_pin_map(dctx_obj
);
2105 return PTR_ERR(hws
);
2106 engine
->status_page
.page_addr
= hws
+ LRC_PPHWSP_PN
* PAGE_SIZE
;
2107 engine
->status_page
.obj
= dctx_obj
;
2113 logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*engine
)
2115 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2116 struct intel_context
*dctx
= dev_priv
->kernel_context
;
2117 enum forcewake_domains fw_domains
;
2120 /* Intentionally left blank. */
2121 engine
->buffer
= NULL
;
2124 INIT_LIST_HEAD(&engine
->active_list
);
2125 INIT_LIST_HEAD(&engine
->request_list
);
2126 i915_gem_batch_pool_init(dev
, &engine
->batch_pool
);
2127 init_waitqueue_head(&engine
->irq_queue
);
2129 INIT_LIST_HEAD(&engine
->buffers
);
2130 INIT_LIST_HEAD(&engine
->execlist_queue
);
2131 INIT_LIST_HEAD(&engine
->execlist_retired_req_list
);
2132 spin_lock_init(&engine
->execlist_lock
);
2134 tasklet_init(&engine
->irq_tasklet
,
2135 intel_lrc_irq_handler
, (unsigned long)engine
);
2137 logical_ring_init_platform_invariants(engine
);
2139 fw_domains
= intel_uncore_forcewake_for_reg(dev_priv
,
2143 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2144 RING_CONTEXT_STATUS_PTR(engine
),
2145 FW_REG_READ
| FW_REG_WRITE
);
2147 fw_domains
|= intel_uncore_forcewake_for_reg(dev_priv
,
2148 RING_CONTEXT_STATUS_BUF_BASE(engine
),
2151 engine
->fw_domains
= fw_domains
;
2153 ret
= i915_cmd_parser_init_ring(engine
);
2157 ret
= intel_lr_context_deferred_alloc(dctx
, engine
);
2161 /* As this is the default context, always pin it */
2162 ret
= intel_lr_context_do_pin(dctx
, engine
);
2165 "Failed to pin and map ringbuffer %s: %d\n",
2170 /* And setup the hardware status page. */
2171 ret
= lrc_setup_hws(engine
, dctx
->engine
[engine
->id
].state
);
2173 DRM_ERROR("Failed to set up hws %s: %d\n", engine
->name
, ret
);
2180 intel_logical_ring_cleanup(engine
);
2184 static int logical_render_ring_init(struct drm_device
*dev
)
2186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2187 struct intel_engine_cs
*engine
= &dev_priv
->engine
[RCS
];
2190 engine
->name
= "render ring";
2192 engine
->exec_id
= I915_EXEC_RENDER
;
2193 engine
->guc_id
= GUC_RENDER_ENGINE
;
2194 engine
->mmio_base
= RENDER_RING_BASE
;
2196 logical_ring_default_irqs(engine
, GEN8_RCS_IRQ_SHIFT
);
2197 if (HAS_L3_DPF(dev
))
2198 engine
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2200 logical_ring_default_vfuncs(dev
, engine
);
2202 /* Override some for render ring. */
2203 if (INTEL_INFO(dev
)->gen
>= 9)
2204 engine
->init_hw
= gen9_init_render_ring
;
2206 engine
->init_hw
= gen8_init_render_ring
;
2207 engine
->init_context
= gen8_init_rcs_context
;
2208 engine
->cleanup
= intel_fini_pipe_control
;
2209 engine
->emit_flush
= gen8_emit_flush_render
;
2210 engine
->emit_request
= gen8_emit_request_render
;
2214 ret
= intel_init_pipe_control(engine
);
2218 ret
= intel_init_workaround_bb(engine
);
2221 * We continue even if we fail to initialize WA batch
2222 * because we only expect rare glitches but nothing
2223 * critical to prevent us from using GPU
2225 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2229 ret
= logical_ring_init(dev
, engine
);
2231 lrc_destroy_wa_ctx_obj(engine
);
2237 static int logical_bsd_ring_init(struct drm_device
*dev
)
2239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2240 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS
];
2242 engine
->name
= "bsd ring";
2244 engine
->exec_id
= I915_EXEC_BSD
;
2245 engine
->guc_id
= GUC_VIDEO_ENGINE
;
2246 engine
->mmio_base
= GEN6_BSD_RING_BASE
;
2248 logical_ring_default_irqs(engine
, GEN8_VCS1_IRQ_SHIFT
);
2249 logical_ring_default_vfuncs(dev
, engine
);
2251 return logical_ring_init(dev
, engine
);
2254 static int logical_bsd2_ring_init(struct drm_device
*dev
)
2256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2257 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VCS2
];
2259 engine
->name
= "bsd2 ring";
2261 engine
->exec_id
= I915_EXEC_BSD
;
2262 engine
->guc_id
= GUC_VIDEO_ENGINE2
;
2263 engine
->mmio_base
= GEN8_BSD2_RING_BASE
;
2265 logical_ring_default_irqs(engine
, GEN8_VCS2_IRQ_SHIFT
);
2266 logical_ring_default_vfuncs(dev
, engine
);
2268 return logical_ring_init(dev
, engine
);
2271 static int logical_blt_ring_init(struct drm_device
*dev
)
2273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2274 struct intel_engine_cs
*engine
= &dev_priv
->engine
[BCS
];
2276 engine
->name
= "blitter ring";
2278 engine
->exec_id
= I915_EXEC_BLT
;
2279 engine
->guc_id
= GUC_BLITTER_ENGINE
;
2280 engine
->mmio_base
= BLT_RING_BASE
;
2282 logical_ring_default_irqs(engine
, GEN8_BCS_IRQ_SHIFT
);
2283 logical_ring_default_vfuncs(dev
, engine
);
2285 return logical_ring_init(dev
, engine
);
2288 static int logical_vebox_ring_init(struct drm_device
*dev
)
2290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2291 struct intel_engine_cs
*engine
= &dev_priv
->engine
[VECS
];
2293 engine
->name
= "video enhancement ring";
2295 engine
->exec_id
= I915_EXEC_VEBOX
;
2296 engine
->guc_id
= GUC_VIDEOENHANCE_ENGINE
;
2297 engine
->mmio_base
= VEBOX_RING_BASE
;
2299 logical_ring_default_irqs(engine
, GEN8_VECS_IRQ_SHIFT
);
2300 logical_ring_default_vfuncs(dev
, engine
);
2302 return logical_ring_init(dev
, engine
);
2306 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2309 * This function inits the engines for an Execlists submission style (the equivalent in the
2310 * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for
2311 * those engines that are present in the hardware.
2313 * Return: non-zero if the initialization failed.
2315 int intel_logical_rings_init(struct drm_device
*dev
)
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2320 ret
= logical_render_ring_init(dev
);
2325 ret
= logical_bsd_ring_init(dev
);
2327 goto cleanup_render_ring
;
2331 ret
= logical_blt_ring_init(dev
);
2333 goto cleanup_bsd_ring
;
2336 if (HAS_VEBOX(dev
)) {
2337 ret
= logical_vebox_ring_init(dev
);
2339 goto cleanup_blt_ring
;
2342 if (HAS_BSD2(dev
)) {
2343 ret
= logical_bsd2_ring_init(dev
);
2345 goto cleanup_vebox_ring
;
2351 intel_logical_ring_cleanup(&dev_priv
->engine
[VECS
]);
2353 intel_logical_ring_cleanup(&dev_priv
->engine
[BCS
]);
2355 intel_logical_ring_cleanup(&dev_priv
->engine
[VCS
]);
2356 cleanup_render_ring
:
2357 intel_logical_ring_cleanup(&dev_priv
->engine
[RCS
]);
2363 make_rpcs(struct drm_device
*dev
)
2368 * No explicit RPCS request is needed to ensure full
2369 * slice/subslice/EU enablement prior to Gen9.
2371 if (INTEL_INFO(dev
)->gen
< 9)
2375 * Starting in Gen9, render power gating can leave
2376 * slice/subslice/EU in a partially enabled state. We
2377 * must make an explicit request through RPCS for full
2380 if (INTEL_INFO(dev
)->has_slice_pg
) {
2381 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2382 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2383 GEN8_RPCS_S_CNT_SHIFT
;
2384 rpcs
|= GEN8_RPCS_ENABLE
;
2387 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2388 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2389 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2390 GEN8_RPCS_SS_CNT_SHIFT
;
2391 rpcs
|= GEN8_RPCS_ENABLE
;
2394 if (INTEL_INFO(dev
)->has_eu_pg
) {
2395 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2396 GEN8_RPCS_EU_MIN_SHIFT
;
2397 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2398 GEN8_RPCS_EU_MAX_SHIFT
;
2399 rpcs
|= GEN8_RPCS_ENABLE
;
2405 static u32
intel_lr_indirect_ctx_offset(struct intel_engine_cs
*engine
)
2407 u32 indirect_ctx_offset
;
2409 switch (INTEL_INFO(engine
->dev
)->gen
) {
2411 MISSING_CASE(INTEL_INFO(engine
->dev
)->gen
);
2414 indirect_ctx_offset
=
2415 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2418 indirect_ctx_offset
=
2419 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
;
2423 return indirect_ctx_offset
;
2427 populate_lr_context(struct intel_context
*ctx
,
2428 struct drm_i915_gem_object
*ctx_obj
,
2429 struct intel_engine_cs
*engine
,
2430 struct intel_ringbuffer
*ringbuf
)
2432 struct drm_device
*dev
= engine
->dev
;
2433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2434 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2440 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2442 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2444 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2448 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2449 if (IS_ERR(vaddr
)) {
2450 ret
= PTR_ERR(vaddr
);
2451 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret
);
2454 ctx_obj
->dirty
= true;
2456 /* The second page of the context object contains some fields which must
2457 * be set up prior to the first execution. */
2458 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2460 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2461 * commands followed by (reg, value) pairs. The values we are setting here are
2462 * only for the first context restore: on a subsequent save, the GPU will
2463 * recreate this batchbuffer with new values (including all the missing
2464 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2465 reg_state
[CTX_LRI_HEADER_0
] =
2466 MI_LOAD_REGISTER_IMM(engine
->id
== RCS
? 14 : 11) | MI_LRI_FORCE_POSTED
;
2467 ASSIGN_CTX_REG(reg_state
, CTX_CONTEXT_CONTROL
,
2468 RING_CONTEXT_CONTROL(engine
),
2469 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2470 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2471 (HAS_RESOURCE_STREAMER(dev
) ?
2472 CTX_CTRL_RS_CTX_ENABLE
: 0)));
2473 ASSIGN_CTX_REG(reg_state
, CTX_RING_HEAD
, RING_HEAD(engine
->mmio_base
),
2475 ASSIGN_CTX_REG(reg_state
, CTX_RING_TAIL
, RING_TAIL(engine
->mmio_base
),
2477 /* Ring buffer start address is not known until the buffer is pinned.
2478 * It is written to the context image in execlists_update_context()
2480 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_START
,
2481 RING_START(engine
->mmio_base
), 0);
2482 ASSIGN_CTX_REG(reg_state
, CTX_RING_BUFFER_CONTROL
,
2483 RING_CTL(engine
->mmio_base
),
2484 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
);
2485 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_U
,
2486 RING_BBADDR_UDW(engine
->mmio_base
), 0);
2487 ASSIGN_CTX_REG(reg_state
, CTX_BB_HEAD_L
,
2488 RING_BBADDR(engine
->mmio_base
), 0);
2489 ASSIGN_CTX_REG(reg_state
, CTX_BB_STATE
,
2490 RING_BBSTATE(engine
->mmio_base
),
2492 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_U
,
2493 RING_SBBADDR_UDW(engine
->mmio_base
), 0);
2494 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_HEAD_L
,
2495 RING_SBBADDR(engine
->mmio_base
), 0);
2496 ASSIGN_CTX_REG(reg_state
, CTX_SECOND_BB_STATE
,
2497 RING_SBBSTATE(engine
->mmio_base
), 0);
2498 if (engine
->id
== RCS
) {
2499 ASSIGN_CTX_REG(reg_state
, CTX_BB_PER_CTX_PTR
,
2500 RING_BB_PER_CTX_PTR(engine
->mmio_base
), 0);
2501 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX
,
2502 RING_INDIRECT_CTX(engine
->mmio_base
), 0);
2503 ASSIGN_CTX_REG(reg_state
, CTX_RCS_INDIRECT_CTX_OFFSET
,
2504 RING_INDIRECT_CTX_OFFSET(engine
->mmio_base
), 0);
2505 if (engine
->wa_ctx
.obj
) {
2506 struct i915_ctx_workarounds
*wa_ctx
= &engine
->wa_ctx
;
2507 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2509 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2510 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2511 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2513 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2514 intel_lr_indirect_ctx_offset(engine
) << 6;
2516 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2517 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2521 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED
;
2522 ASSIGN_CTX_REG(reg_state
, CTX_CTX_TIMESTAMP
,
2523 RING_CTX_TIMESTAMP(engine
->mmio_base
), 0);
2524 /* PDP values well be assigned later if needed */
2525 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_UDW
, GEN8_RING_PDP_UDW(engine
, 3),
2527 ASSIGN_CTX_REG(reg_state
, CTX_PDP3_LDW
, GEN8_RING_PDP_LDW(engine
, 3),
2529 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_UDW
, GEN8_RING_PDP_UDW(engine
, 2),
2531 ASSIGN_CTX_REG(reg_state
, CTX_PDP2_LDW
, GEN8_RING_PDP_LDW(engine
, 2),
2533 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_UDW
, GEN8_RING_PDP_UDW(engine
, 1),
2535 ASSIGN_CTX_REG(reg_state
, CTX_PDP1_LDW
, GEN8_RING_PDP_LDW(engine
, 1),
2537 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_UDW
, GEN8_RING_PDP_UDW(engine
, 0),
2539 ASSIGN_CTX_REG(reg_state
, CTX_PDP0_LDW
, GEN8_RING_PDP_LDW(engine
, 0),
2542 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2543 /* 64b PPGTT (48bit canonical)
2544 * PDP0_DESCRIPTOR contains the base address to PML4 and
2545 * other PDP Descriptors are ignored.
2547 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2550 * PDP*_DESCRIPTOR contains the base address of space supported.
2551 * With dynamic page allocation, PDPs may not be allocated at
2552 * this point. Point the unallocated PDPs to the scratch page
2554 execlists_update_context_pdps(ppgtt
, reg_state
);
2557 if (engine
->id
== RCS
) {
2558 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2559 ASSIGN_CTX_REG(reg_state
, CTX_R_PWR_CLK_STATE
, GEN8_R_PWR_CLK_STATE
,
2563 i915_gem_object_unpin_map(ctx_obj
);
2569 * intel_lr_context_free() - free the LRC specific bits of a context
2570 * @ctx: the LR context to free.
2572 * The real context freeing is done in i915_gem_context_free: this only
2573 * takes care of the bits that are LRC related: the per-engine backing
2574 * objects and the logical ringbuffer.
2576 void intel_lr_context_free(struct intel_context
*ctx
)
2580 for (i
= I915_NUM_ENGINES
; --i
>= 0; ) {
2581 struct intel_ringbuffer
*ringbuf
= ctx
->engine
[i
].ringbuf
;
2582 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2587 if (ctx
== ctx
->i915
->kernel_context
) {
2588 intel_unpin_ringbuffer_obj(ringbuf
);
2589 i915_gem_object_ggtt_unpin(ctx_obj
);
2590 i915_gem_object_unpin_map(ctx_obj
);
2593 WARN_ON(ctx
->engine
[i
].pin_count
);
2594 intel_ringbuffer_free(ringbuf
);
2595 drm_gem_object_unreference(&ctx_obj
->base
);
2600 * intel_lr_context_size() - return the size of the context for an engine
2601 * @ring: which engine to find the context size for
2603 * Each engine may require a different amount of space for a context image,
2604 * so when allocating (or copying) an image, this function can be used to
2605 * find the right size for the specific engine.
2607 * Return: size (in bytes) of an engine-specific context image
2609 * Note: this size includes the HWSP, which is part of the context image
2610 * in LRC mode, but does not include the "shared data page" used with
2611 * GuC submission. The caller should account for this if using the GuC.
2613 uint32_t intel_lr_context_size(struct intel_engine_cs
*engine
)
2617 WARN_ON(INTEL_INFO(engine
->dev
)->gen
< 8);
2619 switch (engine
->id
) {
2621 if (INTEL_INFO(engine
->dev
)->gen
>= 9)
2622 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2624 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2630 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2638 * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
2639 * @ctx: LR context to create.
2640 * @ring: engine to be used with the context.
2642 * This function can be called more than once, with different engines, if we plan
2643 * to use the context with them. The context backing objects and the ringbuffers
2644 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2645 * the creation is a deferred call: it's better to make sure first that we need to use
2646 * a given ring with the context.
2648 * Return: non-zero on error.
2651 int intel_lr_context_deferred_alloc(struct intel_context
*ctx
,
2652 struct intel_engine_cs
*engine
)
2654 struct drm_device
*dev
= engine
->dev
;
2655 struct drm_i915_gem_object
*ctx_obj
;
2656 uint32_t context_size
;
2657 struct intel_ringbuffer
*ringbuf
;
2660 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2661 WARN_ON(ctx
->engine
[engine
->id
].state
);
2663 context_size
= round_up(intel_lr_context_size(engine
), 4096);
2665 /* One extra page as the sharing data between driver and GuC */
2666 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2668 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2670 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2674 ringbuf
= intel_engine_create_ringbuffer(engine
, 4 * PAGE_SIZE
);
2675 if (IS_ERR(ringbuf
)) {
2676 ret
= PTR_ERR(ringbuf
);
2677 goto error_deref_obj
;
2680 ret
= populate_lr_context(ctx
, ctx_obj
, engine
, ringbuf
);
2682 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2686 ctx
->engine
[engine
->id
].ringbuf
= ringbuf
;
2687 ctx
->engine
[engine
->id
].state
= ctx_obj
;
2689 if (ctx
!= ctx
->i915
->kernel_context
&& engine
->init_context
) {
2690 struct drm_i915_gem_request
*req
;
2692 req
= i915_gem_request_alloc(engine
, ctx
);
2695 DRM_ERROR("ring create req: %d\n", ret
);
2699 ret
= engine
->init_context(req
);
2700 i915_add_request_no_flush(req
);
2702 DRM_ERROR("ring init context: %d\n",
2710 intel_ringbuffer_free(ringbuf
);
2712 drm_gem_object_unreference(&ctx_obj
->base
);
2713 ctx
->engine
[engine
->id
].ringbuf
= NULL
;
2714 ctx
->engine
[engine
->id
].state
= NULL
;
2718 void intel_lr_context_reset(struct drm_i915_private
*dev_priv
,
2719 struct intel_context
*ctx
)
2721 struct intel_engine_cs
*engine
;
2723 for_each_engine(engine
, dev_priv
) {
2724 struct drm_i915_gem_object
*ctx_obj
=
2725 ctx
->engine
[engine
->id
].state
;
2726 struct intel_ringbuffer
*ringbuf
=
2727 ctx
->engine
[engine
->id
].ringbuf
;
2729 uint32_t *reg_state
;
2734 vaddr
= i915_gem_object_pin_map(ctx_obj
);
2735 if (WARN_ON(IS_ERR(vaddr
)))
2738 reg_state
= vaddr
+ LRC_STATE_PN
* PAGE_SIZE
;
2739 ctx_obj
->dirty
= true;
2741 reg_state
[CTX_RING_HEAD
+1] = 0;
2742 reg_state
[CTX_RING_TAIL
+1] = 0;
2744 i915_gem_object_unpin_map(ctx_obj
);