2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
199 #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \
200 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
201 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 ADVANCED_CONTEXT
= 0,
210 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
211 #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
212 LEGACY_64B_CONTEXT :\
216 FAULT_AND_HALT
, /* Debug only */
218 FAULT_AND_CONTINUE
/* Unsupported */
220 #define GEN8_CTX_ID_SHIFT 32
221 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
223 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
226 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
228 * @enable_execlists: value of i915.enable_execlists module parameter.
230 * Only certain platforms support Execlists (the prerequisites being
231 * support for Logical Ring Contexts and Aliasing PPGTT or better).
233 * Return: 1 if Execlists is supported and has to be enabled.
235 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
237 WARN_ON(i915
.enable_ppgtt
== -1);
239 /* On platforms with execlist available, vGPU will only
240 * support execlist mode, no ring buffer mode.
242 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && intel_vgpu_active(dev
))
245 if (INTEL_INFO(dev
)->gen
>= 9)
248 if (enable_execlists
== 0)
251 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
252 i915
.use_mmio_flip
>= 0)
259 * intel_execlists_ctx_id() - get the Execlists Context ID
260 * @ctx_obj: Logical Ring Context backing object.
262 * Do not confuse with ctx->id! Unfortunately we have a name overload
263 * here: the old context ID we pass to userspace as a handler so that
264 * they can refer to a context, and the new context ID we pass to the
265 * ELSP so that the GPU can inform us of the context status via
268 * Return: 20-bits globally unique context ID.
270 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
272 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
273 LRC_PPHWSP_PN
* PAGE_SIZE
;
275 /* LRCA is required to be 4K aligned so the more significant 20 bits
276 * are globally unique */
280 uint64_t intel_lr_context_descriptor(struct intel_context
*ctx
,
281 struct intel_engine_cs
*ring
)
283 struct drm_device
*dev
= ring
->dev
;
284 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[ring
->id
].state
;
286 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
) +
287 LRC_PPHWSP_PN
* PAGE_SIZE
;
289 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
291 desc
= GEN8_CTX_VALID
;
292 desc
|= GEN8_CTX_ADDRESSING_MODE(dev
) << GEN8_CTX_ADDRESSING_MODE_SHIFT
;
293 if (IS_GEN8(ctx_obj
->base
.dev
))
294 desc
|= GEN8_CTX_L3LLC_COHERENT
;
295 desc
|= GEN8_CTX_PRIVILEGE
;
297 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
299 /* TODO: WaDisableLiteRestore when we start using semaphore
300 * signalling between Command Streamers */
301 /* desc |= GEN8_CTX_FORCE_RESTORE; */
303 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
305 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
306 (ring
->id
== BCS
|| ring
->id
== VCS
||
307 ring
->id
== VECS
|| ring
->id
== VCS2
))
308 desc
|= GEN8_CTX_FORCE_RESTORE
;
313 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
314 struct drm_i915_gem_request
*rq1
)
317 struct intel_engine_cs
*ring
= rq0
->ring
;
318 struct drm_device
*dev
= ring
->dev
;
319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
323 desc
[1] = intel_lr_context_descriptor(rq1
->ctx
, rq1
->ring
);
324 rq1
->elsp_submitted
++;
329 desc
[0] = intel_lr_context_descriptor(rq0
->ctx
, rq0
->ring
);
330 rq0
->elsp_submitted
++;
332 /* You must always write both descriptors in the order below. */
333 spin_lock(&dev_priv
->uncore
.lock
);
334 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
335 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
336 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
338 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
339 /* The context is automatically loaded after the following */
340 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
342 /* ELSP is a wo register, use another nearby reg for posting */
343 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
344 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
345 spin_unlock(&dev_priv
->uncore
.lock
);
348 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
350 struct intel_engine_cs
*ring
= rq
->ring
;
351 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
352 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
353 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
358 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
359 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
361 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
362 reg_state
= kmap_atomic(page
);
364 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
365 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
367 if (ppgtt
&& !USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
368 /* True 32b PPGTT with dynamic page allocation: update PDP
369 * registers and point the unallocated PDPs to scratch page.
370 * PML4 is allocated during ppgtt init, so this is not needed
373 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
374 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
375 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
376 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
379 kunmap_atomic(reg_state
);
384 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
385 struct drm_i915_gem_request
*rq1
)
387 execlists_update_context(rq0
);
390 execlists_update_context(rq1
);
392 execlists_elsp_write(rq0
, rq1
);
395 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
397 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
398 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
400 assert_spin_locked(&ring
->execlist_lock
);
403 * If irqs are not active generate a warning as batches that finish
404 * without the irqs may get lost and a GPU Hang may occur.
406 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
408 if (list_empty(&ring
->execlist_queue
))
411 /* Try to read in pairs */
412 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
416 } else if (req0
->ctx
== cursor
->ctx
) {
417 /* Same ctx: ignore first request, as second request
418 * will update tail past first request's workload */
419 cursor
->elsp_submitted
= req0
->elsp_submitted
;
420 list_del(&req0
->execlist_link
);
421 list_add_tail(&req0
->execlist_link
,
422 &ring
->execlist_retired_req_list
);
430 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
432 * WaIdleLiteRestore: make sure we never cause a lite
433 * restore with HEAD==TAIL
435 if (req0
->elsp_submitted
) {
437 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
438 * as we resubmit the request. See gen8_emit_request()
439 * for where we prepare the padding after the end of the
442 struct intel_ringbuffer
*ringbuf
;
444 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
446 req0
->tail
&= ringbuf
->size
- 1;
450 WARN_ON(req1
&& req1
->elsp_submitted
);
452 execlists_submit_requests(req0
, req1
);
455 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
458 struct drm_i915_gem_request
*head_req
;
460 assert_spin_locked(&ring
->execlist_lock
);
462 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
463 struct drm_i915_gem_request
,
466 if (head_req
!= NULL
) {
467 struct drm_i915_gem_object
*ctx_obj
=
468 head_req
->ctx
->engine
[ring
->id
].state
;
469 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
470 WARN(head_req
->elsp_submitted
== 0,
471 "Never submitted head request\n");
473 if (--head_req
->elsp_submitted
<= 0) {
474 list_del(&head_req
->execlist_link
);
475 list_add_tail(&head_req
->execlist_link
,
476 &ring
->execlist_retired_req_list
);
486 * intel_lrc_irq_handler() - handle Context Switch interrupts
487 * @ring: Engine Command Streamer to handle.
489 * Check the unread Context Status Buffers and manage the submission of new
490 * contexts to the ELSP accordingly.
492 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
494 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
500 u32 submit_contexts
= 0;
502 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
504 read_pointer
= ring
->next_context_status_buffer
;
505 write_pointer
= status_pointer
& 0x07;
506 if (read_pointer
> write_pointer
)
509 spin_lock(&ring
->execlist_lock
);
511 while (read_pointer
< write_pointer
) {
513 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
514 (read_pointer
% 6) * 8);
515 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
516 (read_pointer
% 6) * 8 + 4);
518 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
521 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
522 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
523 if (execlists_check_remove_request(ring
, status_id
))
524 WARN(1, "Lite Restored request removed from queue\n");
526 WARN(1, "Preemption without Lite Restore\n");
529 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
530 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
531 if (execlists_check_remove_request(ring
, status_id
))
536 if (submit_contexts
!= 0)
537 execlists_context_unqueue(ring
);
539 spin_unlock(&ring
->execlist_lock
);
541 WARN(submit_contexts
> 2, "More than two context complete events?\n");
542 ring
->next_context_status_buffer
= write_pointer
% 6;
544 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
545 _MASKED_FIELD(0x07 << 8, ((u32
)ring
->next_context_status_buffer
& 0x07) << 8));
548 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
550 struct intel_engine_cs
*ring
= request
->ring
;
551 struct drm_i915_gem_request
*cursor
;
552 int num_elements
= 0;
554 if (request
->ctx
!= ring
->default_context
)
555 intel_lr_context_pin(request
);
557 i915_gem_request_reference(request
);
559 spin_lock_irq(&ring
->execlist_lock
);
561 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
562 if (++num_elements
> 2)
565 if (num_elements
> 2) {
566 struct drm_i915_gem_request
*tail_req
;
568 tail_req
= list_last_entry(&ring
->execlist_queue
,
569 struct drm_i915_gem_request
,
572 if (request
->ctx
== tail_req
->ctx
) {
573 WARN(tail_req
->elsp_submitted
!= 0,
574 "More than 2 already-submitted reqs queued\n");
575 list_del(&tail_req
->execlist_link
);
576 list_add_tail(&tail_req
->execlist_link
,
577 &ring
->execlist_retired_req_list
);
581 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
582 if (num_elements
== 0)
583 execlists_context_unqueue(ring
);
585 spin_unlock_irq(&ring
->execlist_lock
);
590 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
592 struct intel_engine_cs
*ring
= req
->ring
;
593 uint32_t flush_domains
;
597 if (ring
->gpu_caches_dirty
)
598 flush_domains
= I915_GEM_GPU_DOMAINS
;
600 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
604 ring
->gpu_caches_dirty
= false;
608 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
609 struct list_head
*vmas
)
611 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
612 struct i915_vma
*vma
;
613 uint32_t flush_domains
= 0;
614 bool flush_chipset
= false;
617 list_for_each_entry(vma
, vmas
, exec_list
) {
618 struct drm_i915_gem_object
*obj
= vma
->obj
;
620 if (obj
->active
& other_rings
) {
621 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
626 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
627 flush_chipset
|= i915_gem_clflush_object(obj
, false);
629 flush_domains
|= obj
->base
.write_domain
;
632 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
635 /* Unconditionally invalidate gpu caches and ensure that we do flush
636 * any residual writes from the previous batch.
638 return logical_ring_invalidate_all_caches(req
);
641 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
645 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
647 if (request
->ctx
!= request
->ring
->default_context
) {
648 ret
= intel_lr_context_pin(request
);
656 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
659 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
660 struct intel_engine_cs
*ring
= req
->ring
;
661 struct drm_i915_gem_request
*target
;
665 if (intel_ring_space(ringbuf
) >= bytes
)
668 /* The whole point of reserving space is to not wait! */
669 WARN_ON(ringbuf
->reserved_in_use
);
671 list_for_each_entry(target
, &ring
->request_list
, list
) {
673 * The request queue is per-engine, so can contain requests
674 * from multiple ringbuffers. Here, we must ignore any that
675 * aren't from the ringbuffer we're considering.
677 if (target
->ringbuf
!= ringbuf
)
680 /* Would completion of this request free enough space? */
681 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
687 if (WARN_ON(&target
->list
== &ring
->request_list
))
690 ret
= i915_wait_request(target
);
694 ringbuf
->space
= space
;
699 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
700 * @request: Request to advance the logical ringbuffer of.
702 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
703 * really happens during submission is that the context and current tail will be placed
704 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
705 * point, the tail *inside* the context is updated and the ELSP written to.
708 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
710 struct intel_engine_cs
*ring
= request
->ring
;
711 struct drm_i915_private
*dev_priv
= request
->i915
;
713 intel_logical_ring_advance(request
->ringbuf
);
715 request
->tail
= request
->ringbuf
->tail
;
717 if (intel_ring_stopped(ring
))
720 if (dev_priv
->guc
.execbuf_client
)
721 i915_guc_submit(dev_priv
->guc
.execbuf_client
, request
);
723 execlists_context_queue(request
);
726 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
728 uint32_t __iomem
*virt
;
729 int rem
= ringbuf
->size
- ringbuf
->tail
;
731 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
734 iowrite32(MI_NOOP
, virt
++);
737 intel_ring_update_space(ringbuf
);
740 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
742 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
743 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
744 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
745 int ret
, total_bytes
, wait_bytes
= 0;
746 bool need_wrap
= false;
748 if (ringbuf
->reserved_in_use
)
751 total_bytes
= bytes
+ ringbuf
->reserved_size
;
753 if (unlikely(bytes
> remain_usable
)) {
755 * Not enough space for the basic request. So need to flush
756 * out the remainder and then wait for base + reserved.
758 wait_bytes
= remain_actual
+ total_bytes
;
761 if (unlikely(total_bytes
> remain_usable
)) {
763 * The base request will fit but the reserved space
764 * falls off the end. So only need to to wait for the
765 * reserved size after flushing out the remainder.
767 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
769 } else if (total_bytes
> ringbuf
->space
) {
770 /* No wrapping required, just waiting. */
771 wait_bytes
= total_bytes
;
776 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
781 __wrap_ring_buffer(ringbuf
);
788 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
790 * @request: The request to start some new work for
791 * @ctx: Logical ring context whose ringbuffer is being prepared.
792 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
794 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
795 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
796 * and also preallocates a request (every workload submission is still mediated through
797 * requests, same as it did with legacy ringbuffer submission).
799 * Return: non-zero if the ringbuffer is not ready to be written to.
801 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
803 struct drm_i915_private
*dev_priv
;
806 WARN_ON(req
== NULL
);
807 dev_priv
= req
->ring
->dev
->dev_private
;
809 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
810 dev_priv
->mm
.interruptible
);
814 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
818 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
822 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
825 * The first call merely notes the reserve request and is common for
826 * all back ends. The subsequent localised _begin() call actually
827 * ensures that the reservation is available. Without the begin, if
828 * the request creator immediately submitted the request without
829 * adding any commands to it then there might not actually be
830 * sufficient room for the submission commands.
832 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
834 return intel_logical_ring_begin(request
, 0);
838 * execlists_submission() - submit a batchbuffer for execution, Execlists style
841 * @ring: Engine Command Streamer to submit to.
842 * @ctx: Context to employ for this submission.
843 * @args: execbuffer call arguments.
844 * @vmas: list of vmas.
845 * @batch_obj: the batchbuffer to submit.
846 * @exec_start: batchbuffer start virtual address pointer.
847 * @dispatch_flags: translated execbuffer call flags.
849 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
850 * away the submission details of the execbuffer ioctl call.
852 * Return: non-zero if the submission fails.
854 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
855 struct drm_i915_gem_execbuffer2
*args
,
856 struct list_head
*vmas
)
858 struct drm_device
*dev
= params
->dev
;
859 struct intel_engine_cs
*ring
= params
->ring
;
860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
861 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
867 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
868 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
869 switch (instp_mode
) {
870 case I915_EXEC_CONSTANTS_REL_GENERAL
:
871 case I915_EXEC_CONSTANTS_ABSOLUTE
:
872 case I915_EXEC_CONSTANTS_REL_SURFACE
:
873 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
874 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
878 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
879 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
880 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
884 /* The HW changed the meaning on this bit on gen6 */
885 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
889 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
893 if (args
->num_cliprects
!= 0) {
894 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
897 if (args
->DR4
== 0xffffffff) {
898 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
902 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
903 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
908 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
909 DRM_DEBUG("sol reset is gen7 only\n");
913 ret
= execlists_move_to_gpu(params
->request
, vmas
);
917 if (ring
== &dev_priv
->ring
[RCS
] &&
918 instp_mode
!= dev_priv
->relative_constants_mode
) {
919 ret
= intel_logical_ring_begin(params
->request
, 4);
923 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
924 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
925 intel_logical_ring_emit(ringbuf
, INSTPM
);
926 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
927 intel_logical_ring_advance(ringbuf
);
929 dev_priv
->relative_constants_mode
= instp_mode
;
932 exec_start
= params
->batch_obj_vm_offset
+
933 args
->batch_start_offset
;
935 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
939 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
941 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
942 i915_gem_execbuffer_retire_commands(params
);
947 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
949 struct drm_i915_gem_request
*req
, *tmp
;
950 struct list_head retired_list
;
952 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
953 if (list_empty(&ring
->execlist_retired_req_list
))
956 INIT_LIST_HEAD(&retired_list
);
957 spin_lock_irq(&ring
->execlist_lock
);
958 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
959 spin_unlock_irq(&ring
->execlist_lock
);
961 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
962 struct intel_context
*ctx
= req
->ctx
;
963 struct drm_i915_gem_object
*ctx_obj
=
964 ctx
->engine
[ring
->id
].state
;
966 if (ctx_obj
&& (ctx
!= ring
->default_context
))
967 intel_lr_context_unpin(req
);
968 list_del(&req
->execlist_link
);
969 i915_gem_request_unreference(req
);
973 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
975 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
978 if (!intel_ring_initialized(ring
))
981 ret
= intel_ring_idle(ring
);
982 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
983 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
986 /* TODO: Is this correct with Execlists enabled? */
987 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
988 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
989 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
992 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
995 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
997 struct intel_engine_cs
*ring
= req
->ring
;
1000 if (!ring
->gpu_caches_dirty
)
1003 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
1007 ring
->gpu_caches_dirty
= false;
1011 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
1013 struct drm_i915_private
*dev_priv
= rq
->i915
;
1014 struct intel_engine_cs
*ring
= rq
->ring
;
1015 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1016 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1019 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1020 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1021 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
1022 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
1024 goto reset_pin_count
;
1026 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1030 /* Invalidate GuC TLB. */
1031 if (i915
.enable_guc_submission
)
1032 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
1038 i915_gem_object_ggtt_unpin(ctx_obj
);
1040 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1045 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1047 struct intel_engine_cs
*ring
= rq
->ring
;
1048 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1049 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1052 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1053 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1054 intel_unpin_ringbuffer_obj(ringbuf
);
1055 i915_gem_object_ggtt_unpin(ctx_obj
);
1060 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1063 struct intel_engine_cs
*ring
= req
->ring
;
1064 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1065 struct drm_device
*dev
= ring
->dev
;
1066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1069 if (WARN_ON_ONCE(w
->count
== 0))
1072 ring
->gpu_caches_dirty
= true;
1073 ret
= logical_ring_flush_all_caches(req
);
1077 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1081 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1082 for (i
= 0; i
< w
->count
; i
++) {
1083 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1084 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1086 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1088 intel_logical_ring_advance(ringbuf
);
1090 ring
->gpu_caches_dirty
= true;
1091 ret
= logical_ring_flush_all_caches(req
);
1098 #define wa_ctx_emit(batch, index, cmd) \
1100 int __index = (index)++; \
1101 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1104 batch[__index] = (cmd); \
1109 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1110 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1111 * but there is a slight complication as this is applied in WA batch where the
1112 * values are only initialized once so we cannot take register value at the
1113 * beginning and reuse it further; hence we save its value to memory, upload a
1114 * constant value with bit21 set and then we restore it back with the saved value.
1115 * To simplify the WA, a constant value is formed by using the default value
1116 * of this register. This shouldn't be a problem because we are only modifying
1117 * it for a short period and this batch in non-premptible. We can ofcourse
1118 * use additional instructions that read the actual value of the register
1119 * at that time and set our bit of interest but it makes the WA complicated.
1121 * This WA is also required for Gen9 so extracting as a function avoids
1124 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1125 uint32_t *const batch
,
1128 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1131 * WaDisableLSQCROPERFforOCL:skl
1132 * This WA is implemented in skl_init_clock_gating() but since
1133 * this batch updates GEN8_L3SQCREG4 with default value we need to
1134 * set this bit here to retain the WA during flush.
1136 if (IS_SKYLAKE(ring
->dev
) && INTEL_REVID(ring
->dev
) <= SKL_REVID_E0
)
1137 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1139 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8
|
1140 MI_SRM_LRM_GLOBAL_GTT
));
1141 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1142 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1143 wa_ctx_emit(batch
, index
, 0);
1145 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1146 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1147 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1149 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1150 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1151 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1152 wa_ctx_emit(batch
, index
, 0);
1153 wa_ctx_emit(batch
, index
, 0);
1154 wa_ctx_emit(batch
, index
, 0);
1155 wa_ctx_emit(batch
, index
, 0);
1157 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8
|
1158 MI_SRM_LRM_GLOBAL_GTT
));
1159 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1160 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1161 wa_ctx_emit(batch
, index
, 0);
1166 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1168 uint32_t start_alignment
)
1170 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1173 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1175 uint32_t size_alignment
)
1177 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1179 WARN(wa_ctx
->size
% size_alignment
,
1180 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1181 wa_ctx
->size
, size_alignment
);
1186 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1188 * @ring: only applicable for RCS
1189 * @wa_ctx: structure representing wa_ctx
1190 * offset: specifies start of the batch, should be cache-aligned. This is updated
1191 * with the offset value received as input.
1192 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1193 * @batch: page in which WA are loaded
1194 * @offset: This field specifies the start of the batch, it should be
1195 * cache-aligned otherwise it is adjusted accordingly.
1196 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1197 * initialized at the beginning and shared across all contexts but this field
1198 * helps us to have multiple batches at different offsets and select them based
1199 * on a criteria. At the moment this batch always start at the beginning of the page
1200 * and at this point we don't have multiple wa_ctx batch buffers.
1202 * The number of WA applied are not known at the beginning; we use this field
1203 * to return the no of DWORDS written.
1205 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1206 * so it adds NOOPs as padding to make it cacheline aligned.
1207 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1208 * makes a complete batch buffer.
1210 * Return: non-zero if we exceed the PAGE_SIZE limit.
1213 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1214 struct i915_wa_ctx_bb
*wa_ctx
,
1215 uint32_t *const batch
,
1218 uint32_t scratch_addr
;
1219 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1221 /* WaDisableCtxRestoreArbitration:bdw,chv */
1222 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1224 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1225 if (IS_BROADWELL(ring
->dev
)) {
1226 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1231 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1232 /* Actual scratch location is at 128 bytes offset */
1233 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1235 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1236 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1237 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1238 PIPE_CONTROL_CS_STALL
|
1239 PIPE_CONTROL_QW_WRITE
));
1240 wa_ctx_emit(batch
, index
, scratch_addr
);
1241 wa_ctx_emit(batch
, index
, 0);
1242 wa_ctx_emit(batch
, index
, 0);
1243 wa_ctx_emit(batch
, index
, 0);
1245 /* Pad to end of cacheline */
1246 while (index
% CACHELINE_DWORDS
)
1247 wa_ctx_emit(batch
, index
, MI_NOOP
);
1250 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1251 * execution depends on the length specified in terms of cache lines
1252 * in the register CTX_RCS_INDIRECT_CTX
1255 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1259 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1261 * @ring: only applicable for RCS
1262 * @wa_ctx: structure representing wa_ctx
1263 * offset: specifies start of the batch, should be cache-aligned.
1264 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1265 * @batch: page in which WA are loaded
1266 * @offset: This field specifies the start of this batch.
1267 * This batch is started immediately after indirect_ctx batch. Since we ensure
1268 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1270 * The number of DWORDS written are returned using this field.
1272 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1273 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1275 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1276 struct i915_wa_ctx_bb
*wa_ctx
,
1277 uint32_t *const batch
,
1280 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1282 /* WaDisableCtxRestoreArbitration:bdw,chv */
1283 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1285 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1287 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1290 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1291 struct i915_wa_ctx_bb
*wa_ctx
,
1292 uint32_t *const batch
,
1296 struct drm_device
*dev
= ring
->dev
;
1297 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1299 /* WaDisableCtxRestoreArbitration:skl,bxt */
1300 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1301 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1302 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1304 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1305 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1310 /* Pad to end of cacheline */
1311 while (index
% CACHELINE_DWORDS
)
1312 wa_ctx_emit(batch
, index
, MI_NOOP
);
1314 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1317 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1318 struct i915_wa_ctx_bb
*wa_ctx
,
1319 uint32_t *const batch
,
1322 struct drm_device
*dev
= ring
->dev
;
1323 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1325 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1326 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_B0
)) ||
1327 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
))) {
1328 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1329 wa_ctx_emit(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1330 wa_ctx_emit(batch
, index
,
1331 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1332 wa_ctx_emit(batch
, index
, MI_NOOP
);
1335 /* WaDisableCtxRestoreArbitration:skl,bxt */
1336 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1337 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1338 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1340 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1342 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1345 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1349 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1350 if (!ring
->wa_ctx
.obj
) {
1351 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1355 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1357 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1359 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1366 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1368 if (ring
->wa_ctx
.obj
) {
1369 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1370 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1371 ring
->wa_ctx
.obj
= NULL
;
1375 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1381 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1383 WARN_ON(ring
->id
!= RCS
);
1385 /* update this when WA for higher Gen are added */
1386 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1387 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1388 INTEL_INFO(ring
->dev
)->gen
);
1392 /* some WA perform writes to scratch page, ensure it is valid */
1393 if (ring
->scratch
.obj
== NULL
) {
1394 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1398 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1400 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1404 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1405 batch
= kmap_atomic(page
);
1408 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1409 ret
= gen8_init_indirectctx_bb(ring
,
1410 &wa_ctx
->indirect_ctx
,
1416 ret
= gen8_init_perctx_bb(ring
,
1422 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1423 ret
= gen9_init_indirectctx_bb(ring
,
1424 &wa_ctx
->indirect_ctx
,
1430 ret
= gen9_init_perctx_bb(ring
,
1439 kunmap_atomic(batch
);
1441 lrc_destroy_wa_ctx_obj(ring
);
1446 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1448 struct drm_device
*dev
= ring
->dev
;
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1452 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1454 if (ring
->status_page
.obj
) {
1455 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1456 (u32
)ring
->status_page
.gfx_addr
);
1457 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1460 I915_WRITE(RING_MODE_GEN7(ring
),
1461 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1462 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1463 POSTING_READ(RING_MODE_GEN7(ring
));
1464 ring
->next_context_status_buffer
= 0;
1465 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1467 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1472 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1474 struct drm_device
*dev
= ring
->dev
;
1475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1478 ret
= gen8_init_common_ring(ring
);
1482 /* We need to disable the AsyncFlip performance optimisations in order
1483 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1484 * programmed to '1' on all products.
1486 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1488 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1490 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1492 return init_workarounds_ring(ring
);
1495 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1499 ret
= gen8_init_common_ring(ring
);
1503 return init_workarounds_ring(ring
);
1506 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1508 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1509 struct intel_engine_cs
*ring
= req
->ring
;
1510 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1511 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1514 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1518 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1519 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1520 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1522 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1523 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1524 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1525 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1528 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1529 intel_logical_ring_advance(ringbuf
);
1534 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1535 u64 offset
, unsigned dispatch_flags
)
1537 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1538 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1541 /* Don't rely in hw updating PDPs, specially in lite-restore.
1542 * Ideally, we should set Force PD Restore in ctx descriptor,
1543 * but we can't. Force Restore would be a second option, but
1544 * it is unsafe in case of lite-restore (because the ctx is
1545 * not idle). PML4 is allocated during ppgtt init so this is
1546 * not needed in 48-bit.*/
1547 if (req
->ctx
->ppgtt
&&
1548 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1549 if (!USES_FULL_48BIT_PPGTT(req
->i915
) &&
1550 !intel_vgpu_active(req
->i915
->dev
)) {
1551 ret
= intel_logical_ring_emit_pdps(req
);
1556 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1559 ret
= intel_logical_ring_begin(req
, 4);
1563 /* FIXME(BDW): Address space and security selectors. */
1564 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1566 (dispatch_flags
& I915_DISPATCH_RS
?
1567 MI_BATCH_RESOURCE_STREAMER
: 0));
1568 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1569 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1570 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1571 intel_logical_ring_advance(ringbuf
);
1576 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1578 struct drm_device
*dev
= ring
->dev
;
1579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1580 unsigned long flags
;
1582 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1585 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1586 if (ring
->irq_refcount
++ == 0) {
1587 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1588 POSTING_READ(RING_IMR(ring
->mmio_base
));
1590 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1595 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1597 struct drm_device
*dev
= ring
->dev
;
1598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1599 unsigned long flags
;
1601 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1602 if (--ring
->irq_refcount
== 0) {
1603 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1604 POSTING_READ(RING_IMR(ring
->mmio_base
));
1606 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1609 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1610 u32 invalidate_domains
,
1613 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1614 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1615 struct drm_device
*dev
= ring
->dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1620 ret
= intel_logical_ring_begin(request
, 4);
1624 cmd
= MI_FLUSH_DW
+ 1;
1626 /* We always require a command barrier so that subsequent
1627 * commands, such as breadcrumb interrupts, are strictly ordered
1628 * wrt the contents of the write cache being flushed to memory
1629 * (and thus being coherent from the CPU).
1631 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1633 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1634 cmd
|= MI_INVALIDATE_TLB
;
1635 if (ring
== &dev_priv
->ring
[VCS
])
1636 cmd
|= MI_INVALIDATE_BSD
;
1639 intel_logical_ring_emit(ringbuf
, cmd
);
1640 intel_logical_ring_emit(ringbuf
,
1641 I915_GEM_HWS_SCRATCH_ADDR
|
1642 MI_FLUSH_DW_USE_GTT
);
1643 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1644 intel_logical_ring_emit(ringbuf
, 0); /* value */
1645 intel_logical_ring_advance(ringbuf
);
1650 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1651 u32 invalidate_domains
,
1654 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1655 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1656 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1661 flags
|= PIPE_CONTROL_CS_STALL
;
1663 if (flush_domains
) {
1664 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1665 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1668 if (invalidate_domains
) {
1669 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1670 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1671 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1672 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1673 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1674 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1675 flags
|= PIPE_CONTROL_QW_WRITE
;
1676 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1680 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1683 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1684 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1686 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1691 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1692 intel_logical_ring_emit(ringbuf
, 0);
1693 intel_logical_ring_emit(ringbuf
, 0);
1694 intel_logical_ring_emit(ringbuf
, 0);
1695 intel_logical_ring_emit(ringbuf
, 0);
1696 intel_logical_ring_emit(ringbuf
, 0);
1699 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1700 intel_logical_ring_emit(ringbuf
, flags
);
1701 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1702 intel_logical_ring_emit(ringbuf
, 0);
1703 intel_logical_ring_emit(ringbuf
, 0);
1704 intel_logical_ring_emit(ringbuf
, 0);
1705 intel_logical_ring_advance(ringbuf
);
1710 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1712 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1715 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1717 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1720 static u32
bxt_a_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1724 * On BXT A steppings there is a HW coherency issue whereby the
1725 * MI_STORE_DATA_IMM storing the completed request's seqno
1726 * occasionally doesn't invalidate the CPU cache. Work around this by
1727 * clflushing the corresponding cacheline whenever the caller wants
1728 * the coherency to be guaranteed. Note that this cacheline is known
1729 * to be clean at this point, since we only write it in
1730 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1731 * this clflush in practice becomes an invalidate operation.
1734 if (!lazy_coherency
)
1735 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1737 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1740 static void bxt_a_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1742 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1744 /* See bxt_a_get_seqno() explaining the reason for the clflush. */
1745 intel_flush_status_page(ring
, I915_GEM_HWS_INDEX
);
1748 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1750 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1751 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1756 * Reserve space for 2 NOOPs at the end of each request to be
1757 * used as a workaround for not being allowed to do lite
1758 * restore with HEAD==TAIL (WaIdleLiteRestore).
1760 ret
= intel_logical_ring_begin(request
, 8);
1764 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1765 cmd
|= MI_GLOBAL_GTT
;
1767 intel_logical_ring_emit(ringbuf
, cmd
);
1768 intel_logical_ring_emit(ringbuf
,
1769 (ring
->status_page
.gfx_addr
+
1770 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1771 intel_logical_ring_emit(ringbuf
, 0);
1772 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1773 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1774 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1775 intel_logical_ring_advance_and_submit(request
);
1778 * Here we add two extra NOOPs as padding to avoid
1779 * lite restore of a context with HEAD==TAIL.
1781 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1782 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1783 intel_logical_ring_advance(ringbuf
);
1788 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1790 struct render_state so
;
1793 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1797 if (so
.rodata
== NULL
)
1800 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1801 I915_DISPATCH_SECURE
);
1805 ret
= req
->ring
->emit_bb_start(req
,
1806 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1807 I915_DISPATCH_SECURE
);
1811 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1814 i915_gem_render_state_fini(&so
);
1818 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1822 ret
= intel_logical_ring_workarounds_emit(req
);
1826 ret
= intel_rcs_context_init_mocs(req
);
1828 * Failing to program the MOCS is non-fatal.The system will not
1829 * run at peak performance. So generate an error and carry on.
1832 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1834 return intel_lr_context_render_state_init(req
);
1838 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1840 * @ring: Engine Command Streamer.
1843 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1845 struct drm_i915_private
*dev_priv
;
1847 if (!intel_ring_initialized(ring
))
1850 dev_priv
= ring
->dev
->dev_private
;
1852 intel_logical_ring_stop(ring
);
1853 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1856 ring
->cleanup(ring
);
1858 i915_cmd_parser_fini_ring(ring
);
1859 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1861 if (ring
->status_page
.obj
) {
1862 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1863 ring
->status_page
.obj
= NULL
;
1866 lrc_destroy_wa_ctx_obj(ring
);
1869 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1873 /* Intentionally left blank. */
1874 ring
->buffer
= NULL
;
1877 INIT_LIST_HEAD(&ring
->active_list
);
1878 INIT_LIST_HEAD(&ring
->request_list
);
1879 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1880 init_waitqueue_head(&ring
->irq_queue
);
1882 INIT_LIST_HEAD(&ring
->execlist_queue
);
1883 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1884 spin_lock_init(&ring
->execlist_lock
);
1886 ret
= i915_cmd_parser_init_ring(ring
);
1890 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1895 static int logical_render_ring_init(struct drm_device
*dev
)
1897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1898 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1901 ring
->name
= "render ring";
1903 ring
->mmio_base
= RENDER_RING_BASE
;
1904 ring
->irq_enable_mask
=
1905 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1906 ring
->irq_keep_mask
=
1907 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1908 if (HAS_L3_DPF(dev
))
1909 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1911 if (INTEL_INFO(dev
)->gen
>= 9)
1912 ring
->init_hw
= gen9_init_render_ring
;
1914 ring
->init_hw
= gen8_init_render_ring
;
1915 ring
->init_context
= gen8_init_rcs_context
;
1916 ring
->cleanup
= intel_fini_pipe_control
;
1917 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
1918 ring
->get_seqno
= bxt_a_get_seqno
;
1919 ring
->set_seqno
= bxt_a_set_seqno
;
1921 ring
->get_seqno
= gen8_get_seqno
;
1922 ring
->set_seqno
= gen8_set_seqno
;
1924 ring
->emit_request
= gen8_emit_request
;
1925 ring
->emit_flush
= gen8_emit_flush_render
;
1926 ring
->irq_get
= gen8_logical_ring_get_irq
;
1927 ring
->irq_put
= gen8_logical_ring_put_irq
;
1928 ring
->emit_bb_start
= gen8_emit_bb_start
;
1932 ret
= intel_init_pipe_control(ring
);
1936 ret
= intel_init_workaround_bb(ring
);
1939 * We continue even if we fail to initialize WA batch
1940 * because we only expect rare glitches but nothing
1941 * critical to prevent us from using GPU
1943 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1947 ret
= logical_ring_init(dev
, ring
);
1949 lrc_destroy_wa_ctx_obj(ring
);
1955 static int logical_bsd_ring_init(struct drm_device
*dev
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1958 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1960 ring
->name
= "bsd ring";
1962 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1963 ring
->irq_enable_mask
=
1964 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1965 ring
->irq_keep_mask
=
1966 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1968 ring
->init_hw
= gen8_init_common_ring
;
1969 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
1970 ring
->get_seqno
= bxt_a_get_seqno
;
1971 ring
->set_seqno
= bxt_a_set_seqno
;
1973 ring
->get_seqno
= gen8_get_seqno
;
1974 ring
->set_seqno
= gen8_set_seqno
;
1976 ring
->emit_request
= gen8_emit_request
;
1977 ring
->emit_flush
= gen8_emit_flush
;
1978 ring
->irq_get
= gen8_logical_ring_get_irq
;
1979 ring
->irq_put
= gen8_logical_ring_put_irq
;
1980 ring
->emit_bb_start
= gen8_emit_bb_start
;
1982 return logical_ring_init(dev
, ring
);
1985 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1988 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1990 ring
->name
= "bds2 ring";
1992 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1993 ring
->irq_enable_mask
=
1994 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1995 ring
->irq_keep_mask
=
1996 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1998 ring
->init_hw
= gen8_init_common_ring
;
1999 ring
->get_seqno
= gen8_get_seqno
;
2000 ring
->set_seqno
= gen8_set_seqno
;
2001 ring
->emit_request
= gen8_emit_request
;
2002 ring
->emit_flush
= gen8_emit_flush
;
2003 ring
->irq_get
= gen8_logical_ring_get_irq
;
2004 ring
->irq_put
= gen8_logical_ring_put_irq
;
2005 ring
->emit_bb_start
= gen8_emit_bb_start
;
2007 return logical_ring_init(dev
, ring
);
2010 static int logical_blt_ring_init(struct drm_device
*dev
)
2012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2013 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2015 ring
->name
= "blitter ring";
2017 ring
->mmio_base
= BLT_RING_BASE
;
2018 ring
->irq_enable_mask
=
2019 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2020 ring
->irq_keep_mask
=
2021 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2023 ring
->init_hw
= gen8_init_common_ring
;
2024 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2025 ring
->get_seqno
= bxt_a_get_seqno
;
2026 ring
->set_seqno
= bxt_a_set_seqno
;
2028 ring
->get_seqno
= gen8_get_seqno
;
2029 ring
->set_seqno
= gen8_set_seqno
;
2031 ring
->emit_request
= gen8_emit_request
;
2032 ring
->emit_flush
= gen8_emit_flush
;
2033 ring
->irq_get
= gen8_logical_ring_get_irq
;
2034 ring
->irq_put
= gen8_logical_ring_put_irq
;
2035 ring
->emit_bb_start
= gen8_emit_bb_start
;
2037 return logical_ring_init(dev
, ring
);
2040 static int logical_vebox_ring_init(struct drm_device
*dev
)
2042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2043 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2045 ring
->name
= "video enhancement ring";
2047 ring
->mmio_base
= VEBOX_RING_BASE
;
2048 ring
->irq_enable_mask
=
2049 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2050 ring
->irq_keep_mask
=
2051 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2053 ring
->init_hw
= gen8_init_common_ring
;
2054 if (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
) {
2055 ring
->get_seqno
= bxt_a_get_seqno
;
2056 ring
->set_seqno
= bxt_a_set_seqno
;
2058 ring
->get_seqno
= gen8_get_seqno
;
2059 ring
->set_seqno
= gen8_set_seqno
;
2061 ring
->emit_request
= gen8_emit_request
;
2062 ring
->emit_flush
= gen8_emit_flush
;
2063 ring
->irq_get
= gen8_logical_ring_get_irq
;
2064 ring
->irq_put
= gen8_logical_ring_put_irq
;
2065 ring
->emit_bb_start
= gen8_emit_bb_start
;
2067 return logical_ring_init(dev
, ring
);
2071 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2074 * This function inits the engines for an Execlists submission style (the equivalent in the
2075 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2076 * those engines that are present in the hardware.
2078 * Return: non-zero if the initialization failed.
2080 int intel_logical_rings_init(struct drm_device
*dev
)
2082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2085 ret
= logical_render_ring_init(dev
);
2090 ret
= logical_bsd_ring_init(dev
);
2092 goto cleanup_render_ring
;
2096 ret
= logical_blt_ring_init(dev
);
2098 goto cleanup_bsd_ring
;
2101 if (HAS_VEBOX(dev
)) {
2102 ret
= logical_vebox_ring_init(dev
);
2104 goto cleanup_blt_ring
;
2107 if (HAS_BSD2(dev
)) {
2108 ret
= logical_bsd2_ring_init(dev
);
2110 goto cleanup_vebox_ring
;
2113 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
2115 goto cleanup_bsd2_ring
;
2120 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
2122 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2124 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2126 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2127 cleanup_render_ring
:
2128 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2134 make_rpcs(struct drm_device
*dev
)
2139 * No explicit RPCS request is needed to ensure full
2140 * slice/subslice/EU enablement prior to Gen9.
2142 if (INTEL_INFO(dev
)->gen
< 9)
2146 * Starting in Gen9, render power gating can leave
2147 * slice/subslice/EU in a partially enabled state. We
2148 * must make an explicit request through RPCS for full
2151 if (INTEL_INFO(dev
)->has_slice_pg
) {
2152 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2153 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2154 GEN8_RPCS_S_CNT_SHIFT
;
2155 rpcs
|= GEN8_RPCS_ENABLE
;
2158 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2159 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2160 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2161 GEN8_RPCS_SS_CNT_SHIFT
;
2162 rpcs
|= GEN8_RPCS_ENABLE
;
2165 if (INTEL_INFO(dev
)->has_eu_pg
) {
2166 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2167 GEN8_RPCS_EU_MIN_SHIFT
;
2168 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2169 GEN8_RPCS_EU_MAX_SHIFT
;
2170 rpcs
|= GEN8_RPCS_ENABLE
;
2177 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2178 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2180 struct drm_device
*dev
= ring
->dev
;
2181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2182 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2184 uint32_t *reg_state
;
2188 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2190 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2192 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2196 ret
= i915_gem_object_get_pages(ctx_obj
);
2198 DRM_DEBUG_DRIVER("Could not get object pages\n");
2202 i915_gem_object_pin_pages(ctx_obj
);
2204 /* The second page of the context object contains some fields which must
2205 * be set up prior to the first execution. */
2206 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2207 reg_state
= kmap_atomic(page
);
2209 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2210 * commands followed by (reg, value) pairs. The values we are setting here are
2211 * only for the first context restore: on a subsequent save, the GPU will
2212 * recreate this batchbuffer with new values (including all the missing
2213 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2214 if (ring
->id
== RCS
)
2215 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2217 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2218 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2219 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2220 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2221 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2222 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2223 CTX_CTRL_RS_CTX_ENABLE
);
2224 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2225 reg_state
[CTX_RING_HEAD
+1] = 0;
2226 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2227 reg_state
[CTX_RING_TAIL
+1] = 0;
2228 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2229 /* Ring buffer start address is not known until the buffer is pinned.
2230 * It is written to the context image in execlists_update_context()
2232 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2233 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2234 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2235 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2236 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2237 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2238 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2239 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2240 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2241 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2242 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2243 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2244 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2245 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2246 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2247 if (ring
->id
== RCS
) {
2248 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2249 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2250 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2251 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2252 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2253 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2254 if (ring
->wa_ctx
.obj
) {
2255 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2256 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2258 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2259 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2260 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2262 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2263 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2265 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2266 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2270 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2271 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2272 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2273 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2274 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2275 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2276 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2277 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2278 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2279 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2280 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2281 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2283 if (USES_FULL_48BIT_PPGTT(ppgtt
->base
.dev
)) {
2284 /* 64b PPGTT (48bit canonical)
2285 * PDP0_DESCRIPTOR contains the base address to PML4 and
2286 * other PDP Descriptors are ignored.
2288 ASSIGN_CTX_PML4(ppgtt
, reg_state
);
2291 * PDP*_DESCRIPTOR contains the base address of space supported.
2292 * With dynamic page allocation, PDPs may not be allocated at
2293 * this point. Point the unallocated PDPs to the scratch page
2295 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2296 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2297 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2298 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2301 if (ring
->id
== RCS
) {
2302 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2303 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2304 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2307 kunmap_atomic(reg_state
);
2310 set_page_dirty(page
);
2311 i915_gem_object_unpin_pages(ctx_obj
);
2317 * intel_lr_context_free() - free the LRC specific bits of a context
2318 * @ctx: the LR context to free.
2320 * The real context freeing is done in i915_gem_context_free: this only
2321 * takes care of the bits that are LRC related: the per-engine backing
2322 * objects and the logical ringbuffer.
2324 void intel_lr_context_free(struct intel_context
*ctx
)
2328 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2329 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2332 struct intel_ringbuffer
*ringbuf
=
2333 ctx
->engine
[i
].ringbuf
;
2334 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2336 if (ctx
== ring
->default_context
) {
2337 intel_unpin_ringbuffer_obj(ringbuf
);
2338 i915_gem_object_ggtt_unpin(ctx_obj
);
2340 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2341 intel_destroy_ringbuffer_obj(ringbuf
);
2343 drm_gem_object_unreference(&ctx_obj
->base
);
2348 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2352 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2356 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2357 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2359 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2365 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2372 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2373 struct drm_i915_gem_object
*default_ctx_obj
)
2375 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2378 /* The HWSP is part of the default context object in LRC mode. */
2379 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
)
2380 + LRC_PPHWSP_PN
* PAGE_SIZE
;
2381 page
= i915_gem_object_get_page(default_ctx_obj
, LRC_PPHWSP_PN
);
2382 ring
->status_page
.page_addr
= kmap(page
);
2383 ring
->status_page
.obj
= default_ctx_obj
;
2385 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2386 (u32
)ring
->status_page
.gfx_addr
);
2387 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2391 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2392 * @ctx: LR context to create.
2393 * @ring: engine to be used with the context.
2395 * This function can be called more than once, with different engines, if we plan
2396 * to use the context with them. The context backing objects and the ringbuffers
2397 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2398 * the creation is a deferred call: it's better to make sure first that we need to use
2399 * a given ring with the context.
2401 * Return: non-zero on error.
2403 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2404 struct intel_engine_cs
*ring
)
2406 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2407 struct drm_device
*dev
= ring
->dev
;
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2409 struct drm_i915_gem_object
*ctx_obj
;
2410 uint32_t context_size
;
2411 struct intel_ringbuffer
*ringbuf
;
2414 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2415 WARN_ON(ctx
->engine
[ring
->id
].state
);
2417 context_size
= round_up(get_lr_context_size(ring
), 4096);
2419 /* One extra page as the sharing data between driver and GuC */
2420 context_size
+= PAGE_SIZE
* LRC_PPHWSP_PN
;
2422 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2424 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2428 if (is_global_default_ctx
) {
2429 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
,
2430 PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
2432 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2434 drm_gem_object_unreference(&ctx_obj
->base
);
2438 /* Invalidate GuC TLB. */
2439 if (i915
.enable_guc_submission
)
2440 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
2443 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2445 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2448 goto error_unpin_ctx
;
2451 ringbuf
->ring
= ring
;
2453 ringbuf
->size
= 4 * PAGE_SIZE
;
2454 ringbuf
->effective_size
= ringbuf
->size
;
2457 ringbuf
->last_retired_head
= -1;
2458 intel_ring_update_space(ringbuf
);
2460 if (ringbuf
->obj
== NULL
) {
2461 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2464 "Failed to allocate ringbuffer obj %s: %d\n",
2466 goto error_free_rbuf
;
2469 if (is_global_default_ctx
) {
2470 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2473 "Failed to pin and map ringbuffer %s: %d\n",
2475 goto error_destroy_rbuf
;
2481 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2483 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2487 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2488 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2490 if (ctx
== ring
->default_context
)
2491 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2492 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2493 if (ring
->init_context
) {
2494 struct drm_i915_gem_request
*req
;
2496 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2500 ret
= ring
->init_context(req
);
2502 DRM_ERROR("ring init context: %d\n", ret
);
2503 i915_gem_request_cancel(req
);
2504 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2505 ctx
->engine
[ring
->id
].state
= NULL
;
2509 i915_add_request_no_flush(req
);
2512 ctx
->rcs_initialized
= true;
2518 if (is_global_default_ctx
)
2519 intel_unpin_ringbuffer_obj(ringbuf
);
2521 intel_destroy_ringbuffer_obj(ringbuf
);
2525 if (is_global_default_ctx
)
2526 i915_gem_object_ggtt_unpin(ctx_obj
);
2527 drm_gem_object_unreference(&ctx_obj
->base
);
2531 void intel_lr_context_reset(struct drm_device
*dev
,
2532 struct intel_context
*ctx
)
2534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2535 struct intel_engine_cs
*ring
;
2538 for_each_ring(ring
, dev_priv
, i
) {
2539 struct drm_i915_gem_object
*ctx_obj
=
2540 ctx
->engine
[ring
->id
].state
;
2541 struct intel_ringbuffer
*ringbuf
=
2542 ctx
->engine
[ring
->id
].ringbuf
;
2543 uint32_t *reg_state
;
2549 if (i915_gem_object_get_pages(ctx_obj
)) {
2550 WARN(1, "Failed get_pages for context obj\n");
2553 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2554 reg_state
= kmap_atomic(page
);
2556 reg_state
[CTX_RING_HEAD
+1] = 0;
2557 reg_state
[CTX_RING_TAIL
+1] = 0;
2559 kunmap_atomic(reg_state
);