2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "intel_mocs.h"
140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
144 #define RING_EXECLIST_QFULL (1 << 0x2)
145 #define RING_EXECLIST1_VALID (1 << 0x3)
146 #define RING_EXECLIST0_VALID (1 << 0x4)
147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
148 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
149 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
158 #define CTX_LRI_HEADER_0 0x01
159 #define CTX_CONTEXT_CONTROL 0x02
160 #define CTX_RING_HEAD 0x04
161 #define CTX_RING_TAIL 0x06
162 #define CTX_RING_BUFFER_START 0x08
163 #define CTX_RING_BUFFER_CONTROL 0x0a
164 #define CTX_BB_HEAD_U 0x0c
165 #define CTX_BB_HEAD_L 0x0e
166 #define CTX_BB_STATE 0x10
167 #define CTX_SECOND_BB_HEAD_U 0x12
168 #define CTX_SECOND_BB_HEAD_L 0x14
169 #define CTX_SECOND_BB_STATE 0x16
170 #define CTX_BB_PER_CTX_PTR 0x18
171 #define CTX_RCS_INDIRECT_CTX 0x1a
172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
173 #define CTX_LRI_HEADER_1 0x21
174 #define CTX_CTX_TIMESTAMP 0x22
175 #define CTX_PDP3_UDW 0x24
176 #define CTX_PDP3_LDW 0x26
177 #define CTX_PDP2_UDW 0x28
178 #define CTX_PDP2_LDW 0x2a
179 #define CTX_PDP1_UDW 0x2c
180 #define CTX_PDP1_LDW 0x2e
181 #define CTX_PDP0_UDW 0x30
182 #define CTX_PDP0_LDW 0x32
183 #define CTX_LRI_HEADER_2 0x41
184 #define CTX_R_PWR_CLK_STATE 0x42
185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
187 #define GEN8_CTX_VALID (1<<0)
188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
189 #define GEN8_CTX_FORCE_RESTORE (1<<2)
190 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
191 #define GEN8_CTX_PRIVILEGE (1<<8)
193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
194 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
195 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
196 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 ADVANCED_CONTEXT
= 0,
205 #define GEN8_CTX_MODE_SHIFT 3
208 FAULT_AND_HALT
, /* Debug only */
210 FAULT_AND_CONTINUE
/* Unsupported */
212 #define GEN8_CTX_ID_SHIFT 32
213 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
215 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
);
218 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
220 * @enable_execlists: value of i915.enable_execlists module parameter.
222 * Only certain platforms support Execlists (the prerequisites being
223 * support for Logical Ring Contexts and Aliasing PPGTT or better).
225 * Return: 1 if Execlists is supported and has to be enabled.
227 int intel_sanitize_enable_execlists(struct drm_device
*dev
, int enable_execlists
)
229 WARN_ON(i915
.enable_ppgtt
== -1);
231 if (INTEL_INFO(dev
)->gen
>= 9)
234 if (enable_execlists
== 0)
237 if (HAS_LOGICAL_RING_CONTEXTS(dev
) && USES_PPGTT(dev
) &&
238 i915
.use_mmio_flip
>= 0)
245 * intel_execlists_ctx_id() - get the Execlists Context ID
246 * @ctx_obj: Logical Ring Context backing object.
248 * Do not confuse with ctx->id! Unfortunately we have a name overload
249 * here: the old context ID we pass to userspace as a handler so that
250 * they can refer to a context, and the new context ID we pass to the
251 * ELSP so that the GPU can inform us of the context status via
254 * Return: 20-bits globally unique context ID.
256 u32
intel_execlists_ctx_id(struct drm_i915_gem_object
*ctx_obj
)
258 u32 lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
260 /* LRCA is required to be 4K aligned so the more significant 20 bits
261 * are globally unique */
265 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request
*rq
)
267 struct intel_engine_cs
*ring
= rq
->ring
;
268 struct drm_device
*dev
= ring
->dev
;
269 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
271 uint64_t lrca
= i915_gem_obj_ggtt_offset(ctx_obj
);
273 WARN_ON(lrca
& 0xFFFFFFFF00000FFFULL
);
275 desc
= GEN8_CTX_VALID
;
276 desc
|= LEGACY_CONTEXT
<< GEN8_CTX_MODE_SHIFT
;
277 if (IS_GEN8(ctx_obj
->base
.dev
))
278 desc
|= GEN8_CTX_L3LLC_COHERENT
;
279 desc
|= GEN8_CTX_PRIVILEGE
;
281 desc
|= (u64
)intel_execlists_ctx_id(ctx_obj
) << GEN8_CTX_ID_SHIFT
;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev
) <= SKL_REVID_B0
&&
290 (ring
->id
== BCS
|| ring
->id
== VCS
||
291 ring
->id
== VECS
|| ring
->id
== VCS2
))
292 desc
|= GEN8_CTX_FORCE_RESTORE
;
297 static void execlists_elsp_write(struct drm_i915_gem_request
*rq0
,
298 struct drm_i915_gem_request
*rq1
)
301 struct intel_engine_cs
*ring
= rq0
->ring
;
302 struct drm_device
*dev
= ring
->dev
;
303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
307 desc
[1] = execlists_ctx_descriptor(rq1
);
308 rq1
->elsp_submitted
++;
313 desc
[0] = execlists_ctx_descriptor(rq0
);
314 rq0
->elsp_submitted
++;
316 /* You must always write both descriptors in the order below. */
317 spin_lock(&dev_priv
->uncore
.lock
);
318 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
319 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[1]));
320 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[1]));
322 I915_WRITE_FW(RING_ELSP(ring
), upper_32_bits(desc
[0]));
323 /* The context is automatically loaded after the following */
324 I915_WRITE_FW(RING_ELSP(ring
), lower_32_bits(desc
[0]));
326 /* ELSP is a wo register, use another nearby reg for posting */
327 POSTING_READ_FW(RING_EXECLIST_STATUS(ring
));
328 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
329 spin_unlock(&dev_priv
->uncore
.lock
);
332 static int execlists_update_context(struct drm_i915_gem_request
*rq
)
334 struct intel_engine_cs
*ring
= rq
->ring
;
335 struct i915_hw_ppgtt
*ppgtt
= rq
->ctx
->ppgtt
;
336 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
337 struct drm_i915_gem_object
*rb_obj
= rq
->ringbuf
->obj
;
342 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj
));
343 WARN_ON(!i915_gem_obj_is_pinned(rb_obj
));
345 page
= i915_gem_object_get_page(ctx_obj
, 1);
346 reg_state
= kmap_atomic(page
);
348 reg_state
[CTX_RING_TAIL
+1] = rq
->tail
;
349 reg_state
[CTX_RING_BUFFER_START
+1] = i915_gem_obj_ggtt_offset(rb_obj
);
351 /* True PPGTT with dynamic page allocation: update PDP registers and
352 * point the unallocated PDPs to the scratch page
355 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
356 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
357 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
358 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
361 kunmap_atomic(reg_state
);
366 static void execlists_submit_requests(struct drm_i915_gem_request
*rq0
,
367 struct drm_i915_gem_request
*rq1
)
369 execlists_update_context(rq0
);
372 execlists_update_context(rq1
);
374 execlists_elsp_write(rq0
, rq1
);
377 static void execlists_context_unqueue(struct intel_engine_cs
*ring
)
379 struct drm_i915_gem_request
*req0
= NULL
, *req1
= NULL
;
380 struct drm_i915_gem_request
*cursor
= NULL
, *tmp
= NULL
;
382 assert_spin_locked(&ring
->execlist_lock
);
385 * If irqs are not active generate a warning as batches that finish
386 * without the irqs may get lost and a GPU Hang may occur.
388 WARN_ON(!intel_irqs_enabled(ring
->dev
->dev_private
));
390 if (list_empty(&ring
->execlist_queue
))
393 /* Try to read in pairs */
394 list_for_each_entry_safe(cursor
, tmp
, &ring
->execlist_queue
,
398 } else if (req0
->ctx
== cursor
->ctx
) {
399 /* Same ctx: ignore first request, as second request
400 * will update tail past first request's workload */
401 cursor
->elsp_submitted
= req0
->elsp_submitted
;
402 list_del(&req0
->execlist_link
);
403 list_add_tail(&req0
->execlist_link
,
404 &ring
->execlist_retired_req_list
);
412 if (IS_GEN8(ring
->dev
) || IS_GEN9(ring
->dev
)) {
414 * WaIdleLiteRestore: make sure we never cause a lite
415 * restore with HEAD==TAIL
417 if (req0
->elsp_submitted
) {
419 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
420 * as we resubmit the request. See gen8_emit_request()
421 * for where we prepare the padding after the end of the
424 struct intel_ringbuffer
*ringbuf
;
426 ringbuf
= req0
->ctx
->engine
[ring
->id
].ringbuf
;
428 req0
->tail
&= ringbuf
->size
- 1;
432 WARN_ON(req1
&& req1
->elsp_submitted
);
434 execlists_submit_requests(req0
, req1
);
437 static bool execlists_check_remove_request(struct intel_engine_cs
*ring
,
440 struct drm_i915_gem_request
*head_req
;
442 assert_spin_locked(&ring
->execlist_lock
);
444 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
445 struct drm_i915_gem_request
,
448 if (head_req
!= NULL
) {
449 struct drm_i915_gem_object
*ctx_obj
=
450 head_req
->ctx
->engine
[ring
->id
].state
;
451 if (intel_execlists_ctx_id(ctx_obj
) == request_id
) {
452 WARN(head_req
->elsp_submitted
== 0,
453 "Never submitted head request\n");
455 if (--head_req
->elsp_submitted
<= 0) {
456 list_del(&head_req
->execlist_link
);
457 list_add_tail(&head_req
->execlist_link
,
458 &ring
->execlist_retired_req_list
);
468 * intel_lrc_irq_handler() - handle Context Switch interrupts
469 * @ring: Engine Command Streamer to handle.
471 * Check the unread Context Status Buffers and manage the submission of new
472 * contexts to the ELSP accordingly.
474 void intel_lrc_irq_handler(struct intel_engine_cs
*ring
)
476 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
482 u32 submit_contexts
= 0;
484 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
486 read_pointer
= ring
->next_context_status_buffer
;
487 write_pointer
= status_pointer
& GEN8_CSB_PTR_MASK
;
488 if (read_pointer
> write_pointer
)
489 write_pointer
+= GEN8_CSB_ENTRIES
;
491 spin_lock(&ring
->execlist_lock
);
493 while (read_pointer
< write_pointer
) {
495 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
496 (read_pointer
% GEN8_CSB_ENTRIES
) * 8);
497 status_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) +
498 (read_pointer
% GEN8_CSB_ENTRIES
) * 8 + 4);
500 if (status
& GEN8_CTX_STATUS_IDLE_ACTIVE
)
503 if (status
& GEN8_CTX_STATUS_PREEMPTED
) {
504 if (status
& GEN8_CTX_STATUS_LITE_RESTORE
) {
505 if (execlists_check_remove_request(ring
, status_id
))
506 WARN(1, "Lite Restored request removed from queue\n");
508 WARN(1, "Preemption without Lite Restore\n");
511 if ((status
& GEN8_CTX_STATUS_ACTIVE_IDLE
) ||
512 (status
& GEN8_CTX_STATUS_ELEMENT_SWITCH
)) {
513 if (execlists_check_remove_request(ring
, status_id
))
518 if (submit_contexts
!= 0)
519 execlists_context_unqueue(ring
);
521 spin_unlock(&ring
->execlist_lock
);
523 WARN(submit_contexts
> 2, "More than two context complete events?\n");
524 ring
->next_context_status_buffer
= write_pointer
% GEN8_CSB_ENTRIES
;
526 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring
),
527 _MASKED_FIELD(GEN8_CSB_PTR_MASK
<< 8,
528 ((u32
)ring
->next_context_status_buffer
&
529 GEN8_CSB_PTR_MASK
) << 8));
532 static int execlists_context_queue(struct drm_i915_gem_request
*request
)
534 struct intel_engine_cs
*ring
= request
->ring
;
535 struct drm_i915_gem_request
*cursor
;
536 int num_elements
= 0;
538 if (request
->ctx
!= ring
->default_context
)
539 intel_lr_context_pin(request
);
541 i915_gem_request_reference(request
);
543 request
->tail
= request
->ringbuf
->tail
;
545 spin_lock_irq(&ring
->execlist_lock
);
547 list_for_each_entry(cursor
, &ring
->execlist_queue
, execlist_link
)
548 if (++num_elements
> 2)
551 if (num_elements
> 2) {
552 struct drm_i915_gem_request
*tail_req
;
554 tail_req
= list_last_entry(&ring
->execlist_queue
,
555 struct drm_i915_gem_request
,
558 if (request
->ctx
== tail_req
->ctx
) {
559 WARN(tail_req
->elsp_submitted
!= 0,
560 "More than 2 already-submitted reqs queued\n");
561 list_del(&tail_req
->execlist_link
);
562 list_add_tail(&tail_req
->execlist_link
,
563 &ring
->execlist_retired_req_list
);
567 list_add_tail(&request
->execlist_link
, &ring
->execlist_queue
);
568 if (num_elements
== 0)
569 execlists_context_unqueue(ring
);
571 spin_unlock_irq(&ring
->execlist_lock
);
576 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
578 struct intel_engine_cs
*ring
= req
->ring
;
579 uint32_t flush_domains
;
583 if (ring
->gpu_caches_dirty
)
584 flush_domains
= I915_GEM_GPU_DOMAINS
;
586 ret
= ring
->emit_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
590 ring
->gpu_caches_dirty
= false;
594 static int execlists_move_to_gpu(struct drm_i915_gem_request
*req
,
595 struct list_head
*vmas
)
597 const unsigned other_rings
= ~intel_ring_flag(req
->ring
);
598 struct i915_vma
*vma
;
599 uint32_t flush_domains
= 0;
600 bool flush_chipset
= false;
603 list_for_each_entry(vma
, vmas
, exec_list
) {
604 struct drm_i915_gem_object
*obj
= vma
->obj
;
606 if (obj
->active
& other_rings
) {
607 ret
= i915_gem_object_sync(obj
, req
->ring
, &req
);
612 if (obj
->base
.write_domain
& I915_GEM_DOMAIN_CPU
)
613 flush_chipset
|= i915_gem_clflush_object(obj
, false);
615 flush_domains
|= obj
->base
.write_domain
;
618 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
621 /* Unconditionally invalidate gpu caches and ensure that we do flush
622 * any residual writes from the previous batch.
624 return logical_ring_invalidate_all_caches(req
);
627 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
631 request
->ringbuf
= request
->ctx
->engine
[request
->ring
->id
].ringbuf
;
633 if (request
->ctx
!= request
->ring
->default_context
) {
634 ret
= intel_lr_context_pin(request
);
642 static int logical_ring_wait_for_space(struct drm_i915_gem_request
*req
,
645 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
646 struct intel_engine_cs
*ring
= req
->ring
;
647 struct drm_i915_gem_request
*target
;
651 if (intel_ring_space(ringbuf
) >= bytes
)
654 /* The whole point of reserving space is to not wait! */
655 WARN_ON(ringbuf
->reserved_in_use
);
657 list_for_each_entry(target
, &ring
->request_list
, list
) {
659 * The request queue is per-engine, so can contain requests
660 * from multiple ringbuffers. Here, we must ignore any that
661 * aren't from the ringbuffer we're considering.
663 if (target
->ringbuf
!= ringbuf
)
666 /* Would completion of this request free enough space? */
667 space
= __intel_ring_space(target
->postfix
, ringbuf
->tail
,
673 if (WARN_ON(&target
->list
== &ring
->request_list
))
676 ret
= i915_wait_request(target
);
680 ringbuf
->space
= space
;
685 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
686 * @request: Request to advance the logical ringbuffer of.
688 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
689 * really happens during submission is that the context and current tail will be placed
690 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
691 * point, the tail *inside* the context is updated and the ELSP written to.
694 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request
*request
)
696 struct intel_engine_cs
*ring
= request
->ring
;
698 intel_logical_ring_advance(request
->ringbuf
);
700 if (intel_ring_stopped(ring
))
703 execlists_context_queue(request
);
706 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
708 uint32_t __iomem
*virt
;
709 int rem
= ringbuf
->size
- ringbuf
->tail
;
711 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
714 iowrite32(MI_NOOP
, virt
++);
717 intel_ring_update_space(ringbuf
);
720 static int logical_ring_prepare(struct drm_i915_gem_request
*req
, int bytes
)
722 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
723 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
724 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
725 int ret
, total_bytes
, wait_bytes
= 0;
726 bool need_wrap
= false;
728 if (ringbuf
->reserved_in_use
)
731 total_bytes
= bytes
+ ringbuf
->reserved_size
;
733 if (unlikely(bytes
> remain_usable
)) {
735 * Not enough space for the basic request. So need to flush
736 * out the remainder and then wait for base + reserved.
738 wait_bytes
= remain_actual
+ total_bytes
;
741 if (unlikely(total_bytes
> remain_usable
)) {
743 * The base request will fit but the reserved space
744 * falls off the end. So only need to to wait for the
745 * reserved size after flushing out the remainder.
747 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
749 } else if (total_bytes
> ringbuf
->space
) {
750 /* No wrapping required, just waiting. */
751 wait_bytes
= total_bytes
;
756 ret
= logical_ring_wait_for_space(req
, wait_bytes
);
761 __wrap_ring_buffer(ringbuf
);
768 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
770 * @request: The request to start some new work for
771 * @ctx: Logical ring context whose ringbuffer is being prepared.
772 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
774 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
775 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
776 * and also preallocates a request (every workload submission is still mediated through
777 * requests, same as it did with legacy ringbuffer submission).
779 * Return: non-zero if the ringbuffer is not ready to be written to.
781 int intel_logical_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
783 struct drm_i915_private
*dev_priv
;
786 WARN_ON(req
== NULL
);
787 dev_priv
= req
->ring
->dev
->dev_private
;
789 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
790 dev_priv
->mm
.interruptible
);
794 ret
= logical_ring_prepare(req
, num_dwords
* sizeof(uint32_t));
798 req
->ringbuf
->space
-= num_dwords
* sizeof(uint32_t);
802 int intel_logical_ring_reserve_space(struct drm_i915_gem_request
*request
)
805 * The first call merely notes the reserve request and is common for
806 * all back ends. The subsequent localised _begin() call actually
807 * ensures that the reservation is available. Without the begin, if
808 * the request creator immediately submitted the request without
809 * adding any commands to it then there might not actually be
810 * sufficient room for the submission commands.
812 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
814 return intel_logical_ring_begin(request
, 0);
818 * execlists_submission() - submit a batchbuffer for execution, Execlists style
821 * @ring: Engine Command Streamer to submit to.
822 * @ctx: Context to employ for this submission.
823 * @args: execbuffer call arguments.
824 * @vmas: list of vmas.
825 * @batch_obj: the batchbuffer to submit.
826 * @exec_start: batchbuffer start virtual address pointer.
827 * @dispatch_flags: translated execbuffer call flags.
829 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
830 * away the submission details of the execbuffer ioctl call.
832 * Return: non-zero if the submission fails.
834 int intel_execlists_submission(struct i915_execbuffer_params
*params
,
835 struct drm_i915_gem_execbuffer2
*args
,
836 struct list_head
*vmas
)
838 struct drm_device
*dev
= params
->dev
;
839 struct intel_engine_cs
*ring
= params
->ring
;
840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
841 struct intel_ringbuffer
*ringbuf
= params
->ctx
->engine
[ring
->id
].ringbuf
;
847 instp_mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
848 instp_mask
= I915_EXEC_CONSTANTS_MASK
;
849 switch (instp_mode
) {
850 case I915_EXEC_CONSTANTS_REL_GENERAL
:
851 case I915_EXEC_CONSTANTS_ABSOLUTE
:
852 case I915_EXEC_CONSTANTS_REL_SURFACE
:
853 if (instp_mode
!= 0 && ring
!= &dev_priv
->ring
[RCS
]) {
854 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
858 if (instp_mode
!= dev_priv
->relative_constants_mode
) {
859 if (instp_mode
== I915_EXEC_CONSTANTS_REL_SURFACE
) {
860 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
864 /* The HW changed the meaning on this bit on gen6 */
865 instp_mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
869 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode
);
873 if (args
->num_cliprects
!= 0) {
874 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
877 if (args
->DR4
== 0xffffffff) {
878 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
882 if (args
->DR1
|| args
->DR4
|| args
->cliprects_ptr
) {
883 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
888 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
889 DRM_DEBUG("sol reset is gen7 only\n");
893 ret
= execlists_move_to_gpu(params
->request
, vmas
);
897 if (ring
== &dev_priv
->ring
[RCS
] &&
898 instp_mode
!= dev_priv
->relative_constants_mode
) {
899 ret
= intel_logical_ring_begin(params
->request
, 4);
903 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
904 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(1));
905 intel_logical_ring_emit(ringbuf
, INSTPM
);
906 intel_logical_ring_emit(ringbuf
, instp_mask
<< 16 | instp_mode
);
907 intel_logical_ring_advance(ringbuf
);
909 dev_priv
->relative_constants_mode
= instp_mode
;
912 exec_start
= params
->batch_obj_vm_offset
+
913 args
->batch_start_offset
;
915 ret
= ring
->emit_bb_start(params
->request
, exec_start
, params
->dispatch_flags
);
919 trace_i915_gem_ring_dispatch(params
->request
, params
->dispatch_flags
);
921 i915_gem_execbuffer_move_to_active(vmas
, params
->request
);
922 i915_gem_execbuffer_retire_commands(params
);
927 void intel_execlists_retire_requests(struct intel_engine_cs
*ring
)
929 struct drm_i915_gem_request
*req
, *tmp
;
930 struct list_head retired_list
;
932 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
933 if (list_empty(&ring
->execlist_retired_req_list
))
936 INIT_LIST_HEAD(&retired_list
);
937 spin_lock_irq(&ring
->execlist_lock
);
938 list_replace_init(&ring
->execlist_retired_req_list
, &retired_list
);
939 spin_unlock_irq(&ring
->execlist_lock
);
941 list_for_each_entry_safe(req
, tmp
, &retired_list
, execlist_link
) {
942 struct intel_context
*ctx
= req
->ctx
;
943 struct drm_i915_gem_object
*ctx_obj
=
944 ctx
->engine
[ring
->id
].state
;
946 if (ctx_obj
&& (ctx
!= ring
->default_context
))
947 intel_lr_context_unpin(req
);
948 list_del(&req
->execlist_link
);
949 i915_gem_request_unreference(req
);
953 void intel_logical_ring_stop(struct intel_engine_cs
*ring
)
955 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
958 if (!intel_ring_initialized(ring
))
961 ret
= intel_ring_idle(ring
);
962 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
963 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
966 /* TODO: Is this correct with Execlists enabled? */
967 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
968 if (wait_for_atomic((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
969 DRM_ERROR("%s :timed out trying to stop ring\n", ring
->name
);
972 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
975 int logical_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
977 struct intel_engine_cs
*ring
= req
->ring
;
980 if (!ring
->gpu_caches_dirty
)
983 ret
= ring
->emit_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
987 ring
->gpu_caches_dirty
= false;
991 static int intel_lr_context_pin(struct drm_i915_gem_request
*rq
)
993 struct intel_engine_cs
*ring
= rq
->ring
;
994 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
995 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
998 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
999 if (rq
->ctx
->engine
[ring
->id
].pin_count
++ == 0) {
1000 ret
= i915_gem_obj_ggtt_pin(ctx_obj
,
1001 GEN8_LR_CONTEXT_ALIGN
, 0);
1003 goto reset_pin_count
;
1005 ret
= intel_pin_and_map_ringbuffer_obj(ring
->dev
, ringbuf
);
1009 ctx_obj
->dirty
= true;
1015 i915_gem_object_ggtt_unpin(ctx_obj
);
1017 rq
->ctx
->engine
[ring
->id
].pin_count
= 0;
1022 void intel_lr_context_unpin(struct drm_i915_gem_request
*rq
)
1024 struct intel_engine_cs
*ring
= rq
->ring
;
1025 struct drm_i915_gem_object
*ctx_obj
= rq
->ctx
->engine
[ring
->id
].state
;
1026 struct intel_ringbuffer
*ringbuf
= rq
->ringbuf
;
1029 WARN_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1030 if (--rq
->ctx
->engine
[ring
->id
].pin_count
== 0) {
1031 intel_unpin_ringbuffer_obj(ringbuf
);
1032 i915_gem_object_ggtt_unpin(ctx_obj
);
1037 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
1040 struct intel_engine_cs
*ring
= req
->ring
;
1041 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1042 struct drm_device
*dev
= ring
->dev
;
1043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1044 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
1046 if (WARN_ON_ONCE(w
->count
== 0))
1049 ring
->gpu_caches_dirty
= true;
1050 ret
= logical_ring_flush_all_caches(req
);
1054 ret
= intel_logical_ring_begin(req
, w
->count
* 2 + 2);
1058 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(w
->count
));
1059 for (i
= 0; i
< w
->count
; i
++) {
1060 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].addr
);
1061 intel_logical_ring_emit(ringbuf
, w
->reg
[i
].value
);
1063 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1065 intel_logical_ring_advance(ringbuf
);
1067 ring
->gpu_caches_dirty
= true;
1068 ret
= logical_ring_flush_all_caches(req
);
1075 #define wa_ctx_emit(batch, index, cmd) \
1077 int __index = (index)++; \
1078 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
1081 batch[__index] = (cmd); \
1086 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1087 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1088 * but there is a slight complication as this is applied in WA batch where the
1089 * values are only initialized once so we cannot take register value at the
1090 * beginning and reuse it further; hence we save its value to memory, upload a
1091 * constant value with bit21 set and then we restore it back with the saved value.
1092 * To simplify the WA, a constant value is formed by using the default value
1093 * of this register. This shouldn't be a problem because we are only modifying
1094 * it for a short period and this batch in non-premptible. We can ofcourse
1095 * use additional instructions that read the actual value of the register
1096 * at that time and set our bit of interest but it makes the WA complicated.
1098 * This WA is also required for Gen9 so extracting as a function avoids
1101 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs
*ring
,
1102 uint32_t *const batch
,
1105 uint32_t l3sqc4_flush
= (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES
);
1108 * WaDisableLSQCROPERFforOCL:skl
1109 * This WA is implemented in skl_init_clock_gating() but since
1110 * this batch updates GEN8_L3SQCREG4 with default value we need to
1111 * set this bit here to retain the WA during flush.
1113 if (IS_SKYLAKE(ring
->dev
) && INTEL_REVID(ring
->dev
) <= SKL_REVID_E0
)
1114 l3sqc4_flush
|= GEN8_LQSC_RO_PERF_DIS
;
1116 wa_ctx_emit(batch
, index
, (MI_STORE_REGISTER_MEM_GEN8(1) |
1117 MI_SRM_LRM_GLOBAL_GTT
));
1118 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1119 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1120 wa_ctx_emit(batch
, index
, 0);
1122 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1123 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1124 wa_ctx_emit(batch
, index
, l3sqc4_flush
);
1126 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1127 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_CS_STALL
|
1128 PIPE_CONTROL_DC_FLUSH_ENABLE
));
1129 wa_ctx_emit(batch
, index
, 0);
1130 wa_ctx_emit(batch
, index
, 0);
1131 wa_ctx_emit(batch
, index
, 0);
1132 wa_ctx_emit(batch
, index
, 0);
1134 wa_ctx_emit(batch
, index
, (MI_LOAD_REGISTER_MEM_GEN8(1) |
1135 MI_SRM_LRM_GLOBAL_GTT
));
1136 wa_ctx_emit(batch
, index
, GEN8_L3SQCREG4
);
1137 wa_ctx_emit(batch
, index
, ring
->scratch
.gtt_offset
+ 256);
1138 wa_ctx_emit(batch
, index
, 0);
1143 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb
*wa_ctx
,
1145 uint32_t start_alignment
)
1147 return wa_ctx
->offset
= ALIGN(offset
, start_alignment
);
1150 static inline int wa_ctx_end(struct i915_wa_ctx_bb
*wa_ctx
,
1152 uint32_t size_alignment
)
1154 wa_ctx
->size
= offset
- wa_ctx
->offset
;
1156 WARN(wa_ctx
->size
% size_alignment
,
1157 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1158 wa_ctx
->size
, size_alignment
);
1163 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
1165 * @ring: only applicable for RCS
1166 * @wa_ctx: structure representing wa_ctx
1167 * offset: specifies start of the batch, should be cache-aligned. This is updated
1168 * with the offset value received as input.
1169 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1170 * @batch: page in which WA are loaded
1171 * @offset: This field specifies the start of the batch, it should be
1172 * cache-aligned otherwise it is adjusted accordingly.
1173 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1174 * initialized at the beginning and shared across all contexts but this field
1175 * helps us to have multiple batches at different offsets and select them based
1176 * on a criteria. At the moment this batch always start at the beginning of the page
1177 * and at this point we don't have multiple wa_ctx batch buffers.
1179 * The number of WA applied are not known at the beginning; we use this field
1180 * to return the no of DWORDS written.
1182 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1183 * so it adds NOOPs as padding to make it cacheline aligned.
1184 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1185 * makes a complete batch buffer.
1187 * Return: non-zero if we exceed the PAGE_SIZE limit.
1190 static int gen8_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1191 struct i915_wa_ctx_bb
*wa_ctx
,
1192 uint32_t *const batch
,
1195 uint32_t scratch_addr
;
1196 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1198 /* WaDisableCtxRestoreArbitration:bdw,chv */
1199 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1201 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1202 if (IS_BROADWELL(ring
->dev
)) {
1203 index
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1208 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1209 /* Actual scratch location is at 128 bytes offset */
1210 scratch_addr
= ring
->scratch
.gtt_offset
+ 2*CACHELINE_BYTES
;
1212 wa_ctx_emit(batch
, index
, GFX_OP_PIPE_CONTROL(6));
1213 wa_ctx_emit(batch
, index
, (PIPE_CONTROL_FLUSH_L3
|
1214 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1215 PIPE_CONTROL_CS_STALL
|
1216 PIPE_CONTROL_QW_WRITE
));
1217 wa_ctx_emit(batch
, index
, scratch_addr
);
1218 wa_ctx_emit(batch
, index
, 0);
1219 wa_ctx_emit(batch
, index
, 0);
1220 wa_ctx_emit(batch
, index
, 0);
1222 /* Pad to end of cacheline */
1223 while (index
% CACHELINE_DWORDS
)
1224 wa_ctx_emit(batch
, index
, MI_NOOP
);
1227 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1228 * execution depends on the length specified in terms of cache lines
1229 * in the register CTX_RCS_INDIRECT_CTX
1232 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1236 * gen8_init_perctx_bb() - initialize per ctx batch with WA
1238 * @ring: only applicable for RCS
1239 * @wa_ctx: structure representing wa_ctx
1240 * offset: specifies start of the batch, should be cache-aligned.
1241 * size: size of the batch in DWORDS but HW expects in terms of cachelines
1242 * @batch: page in which WA are loaded
1243 * @offset: This field specifies the start of this batch.
1244 * This batch is started immediately after indirect_ctx batch. Since we ensure
1245 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1247 * The number of DWORDS written are returned using this field.
1249 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1250 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1252 static int gen8_init_perctx_bb(struct intel_engine_cs
*ring
,
1253 struct i915_wa_ctx_bb
*wa_ctx
,
1254 uint32_t *const batch
,
1257 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1259 /* WaDisableCtxRestoreArbitration:bdw,chv */
1260 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1262 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1264 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1267 static int gen9_init_indirectctx_bb(struct intel_engine_cs
*ring
,
1268 struct i915_wa_ctx_bb
*wa_ctx
,
1269 uint32_t *const batch
,
1273 struct drm_device
*dev
= ring
->dev
;
1274 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1276 /* WaDisableCtxRestoreArbitration:skl,bxt */
1277 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1278 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1279 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_DISABLE
);
1281 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1282 ret
= gen8_emit_flush_coherentl3_wa(ring
, batch
, index
);
1287 /* Pad to end of cacheline */
1288 while (index
% CACHELINE_DWORDS
)
1289 wa_ctx_emit(batch
, index
, MI_NOOP
);
1291 return wa_ctx_end(wa_ctx
, *offset
= index
, CACHELINE_DWORDS
);
1294 static int gen9_init_perctx_bb(struct intel_engine_cs
*ring
,
1295 struct i915_wa_ctx_bb
*wa_ctx
,
1296 uint32_t *const batch
,
1299 struct drm_device
*dev
= ring
->dev
;
1300 uint32_t index
= wa_ctx_start(wa_ctx
, *offset
, CACHELINE_DWORDS
);
1302 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1303 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_B0
)) ||
1304 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
))) {
1305 wa_ctx_emit(batch
, index
, MI_LOAD_REGISTER_IMM(1));
1306 wa_ctx_emit(batch
, index
, GEN9_SLICE_COMMON_ECO_CHICKEN0
);
1307 wa_ctx_emit(batch
, index
,
1308 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING
));
1309 wa_ctx_emit(batch
, index
, MI_NOOP
);
1312 /* WaDisableCtxRestoreArbitration:skl,bxt */
1313 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) <= SKL_REVID_D0
)) ||
1314 (IS_BROXTON(dev
) && (INTEL_REVID(dev
) == BXT_REVID_A0
)))
1315 wa_ctx_emit(batch
, index
, MI_ARB_ON_OFF
| MI_ARB_ENABLE
);
1317 wa_ctx_emit(batch
, index
, MI_BATCH_BUFFER_END
);
1319 return wa_ctx_end(wa_ctx
, *offset
= index
, 1);
1322 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs
*ring
, u32 size
)
1326 ring
->wa_ctx
.obj
= i915_gem_alloc_object(ring
->dev
, PAGE_ALIGN(size
));
1327 if (!ring
->wa_ctx
.obj
) {
1328 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1332 ret
= i915_gem_obj_ggtt_pin(ring
->wa_ctx
.obj
, PAGE_SIZE
, 0);
1334 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1336 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1343 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs
*ring
)
1345 if (ring
->wa_ctx
.obj
) {
1346 i915_gem_object_ggtt_unpin(ring
->wa_ctx
.obj
);
1347 drm_gem_object_unreference(&ring
->wa_ctx
.obj
->base
);
1348 ring
->wa_ctx
.obj
= NULL
;
1352 static int intel_init_workaround_bb(struct intel_engine_cs
*ring
)
1358 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
1360 WARN_ON(ring
->id
!= RCS
);
1362 /* update this when WA for higher Gen are added */
1363 if (INTEL_INFO(ring
->dev
)->gen
> 9) {
1364 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1365 INTEL_INFO(ring
->dev
)->gen
);
1369 /* some WA perform writes to scratch page, ensure it is valid */
1370 if (ring
->scratch
.obj
== NULL
) {
1371 DRM_ERROR("scratch page not allocated for %s\n", ring
->name
);
1375 ret
= lrc_setup_wa_ctx_obj(ring
, PAGE_SIZE
);
1377 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret
);
1381 page
= i915_gem_object_get_page(wa_ctx
->obj
, 0);
1382 batch
= kmap_atomic(page
);
1385 if (INTEL_INFO(ring
->dev
)->gen
== 8) {
1386 ret
= gen8_init_indirectctx_bb(ring
,
1387 &wa_ctx
->indirect_ctx
,
1393 ret
= gen8_init_perctx_bb(ring
,
1399 } else if (INTEL_INFO(ring
->dev
)->gen
== 9) {
1400 ret
= gen9_init_indirectctx_bb(ring
,
1401 &wa_ctx
->indirect_ctx
,
1407 ret
= gen9_init_perctx_bb(ring
,
1416 kunmap_atomic(batch
);
1418 lrc_destroy_wa_ctx_obj(ring
);
1423 static int gen8_init_common_ring(struct intel_engine_cs
*ring
)
1425 struct drm_device
*dev
= ring
->dev
;
1426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1427 u8 next_context_status_buffer_hw
;
1429 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1430 I915_WRITE(RING_HWSTAM(ring
->mmio_base
), 0xffffffff);
1432 if (ring
->status_page
.obj
) {
1433 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
1434 (u32
)ring
->status_page
.gfx_addr
);
1435 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
1438 I915_WRITE(RING_MODE_GEN7(ring
),
1439 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE
) |
1440 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE
));
1441 POSTING_READ(RING_MODE_GEN7(ring
));
1444 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1445 * zero, we need to read the write pointer from hardware and use its
1446 * value because "this register is power context save restored".
1447 * Effectively, these states have been observed:
1449 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1450 * BDW | CSB regs not reset | CSB regs reset |
1451 * CHT | CSB regs not reset | CSB regs not reset |
1453 next_context_status_buffer_hw
= (I915_READ(RING_CONTEXT_STATUS_PTR(ring
))
1454 & GEN8_CSB_PTR_MASK
);
1457 * When the CSB registers are reset (also after power-up / gpu reset),
1458 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1459 * this special case, so the first element read is CSB[0].
1461 if (next_context_status_buffer_hw
== GEN8_CSB_PTR_MASK
)
1462 next_context_status_buffer_hw
= (GEN8_CSB_ENTRIES
- 1);
1464 ring
->next_context_status_buffer
= next_context_status_buffer_hw
;
1465 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring
->name
);
1467 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
1472 static int gen8_init_render_ring(struct intel_engine_cs
*ring
)
1474 struct drm_device
*dev
= ring
->dev
;
1475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1478 ret
= gen8_init_common_ring(ring
);
1482 /* We need to disable the AsyncFlip performance optimisations in order
1483 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1484 * programmed to '1' on all products.
1486 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1488 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1490 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1492 return init_workarounds_ring(ring
);
1495 static int gen9_init_render_ring(struct intel_engine_cs
*ring
)
1499 ret
= gen8_init_common_ring(ring
);
1503 return init_workarounds_ring(ring
);
1506 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request
*req
)
1508 struct i915_hw_ppgtt
*ppgtt
= req
->ctx
->ppgtt
;
1509 struct intel_engine_cs
*ring
= req
->ring
;
1510 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1511 const int num_lri_cmds
= GEN8_LEGACY_PDPES
* 2;
1514 ret
= intel_logical_ring_begin(req
, num_lri_cmds
* 2 + 2);
1518 intel_logical_ring_emit(ringbuf
, MI_LOAD_REGISTER_IMM(num_lri_cmds
));
1519 for (i
= GEN8_LEGACY_PDPES
- 1; i
>= 0; i
--) {
1520 const dma_addr_t pd_daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1522 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_UDW(ring
, i
));
1523 intel_logical_ring_emit(ringbuf
, upper_32_bits(pd_daddr
));
1524 intel_logical_ring_emit(ringbuf
, GEN8_RING_PDP_LDW(ring
, i
));
1525 intel_logical_ring_emit(ringbuf
, lower_32_bits(pd_daddr
));
1528 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1529 intel_logical_ring_advance(ringbuf
);
1534 static int gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
1535 u64 offset
, unsigned dispatch_flags
)
1537 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
1538 bool ppgtt
= !(dispatch_flags
& I915_DISPATCH_SECURE
);
1541 /* Don't rely in hw updating PDPs, specially in lite-restore.
1542 * Ideally, we should set Force PD Restore in ctx descriptor,
1543 * but we can't. Force Restore would be a second option, but
1544 * it is unsafe in case of lite-restore (because the ctx is
1546 if (req
->ctx
->ppgtt
&&
1547 (intel_ring_flag(req
->ring
) & req
->ctx
->ppgtt
->pd_dirty_rings
)) {
1548 ret
= intel_logical_ring_emit_pdps(req
);
1552 req
->ctx
->ppgtt
->pd_dirty_rings
&= ~intel_ring_flag(req
->ring
);
1555 ret
= intel_logical_ring_begin(req
, 4);
1559 /* FIXME(BDW): Address space and security selectors. */
1560 intel_logical_ring_emit(ringbuf
, MI_BATCH_BUFFER_START_GEN8
|
1562 (dispatch_flags
& I915_DISPATCH_RS
?
1563 MI_BATCH_RESOURCE_STREAMER
: 0));
1564 intel_logical_ring_emit(ringbuf
, lower_32_bits(offset
));
1565 intel_logical_ring_emit(ringbuf
, upper_32_bits(offset
));
1566 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1567 intel_logical_ring_advance(ringbuf
);
1572 static bool gen8_logical_ring_get_irq(struct intel_engine_cs
*ring
)
1574 struct drm_device
*dev
= ring
->dev
;
1575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1576 unsigned long flags
;
1578 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1581 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1582 if (ring
->irq_refcount
++ == 0) {
1583 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
| ring
->irq_keep_mask
));
1584 POSTING_READ(RING_IMR(ring
->mmio_base
));
1586 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1591 static void gen8_logical_ring_put_irq(struct intel_engine_cs
*ring
)
1593 struct drm_device
*dev
= ring
->dev
;
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1595 unsigned long flags
;
1597 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1598 if (--ring
->irq_refcount
== 0) {
1599 I915_WRITE_IMR(ring
, ~ring
->irq_keep_mask
);
1600 POSTING_READ(RING_IMR(ring
->mmio_base
));
1602 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1605 static int gen8_emit_flush(struct drm_i915_gem_request
*request
,
1606 u32 invalidate_domains
,
1609 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1610 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1611 struct drm_device
*dev
= ring
->dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1616 ret
= intel_logical_ring_begin(request
, 4);
1620 cmd
= MI_FLUSH_DW
+ 1;
1622 /* We always require a command barrier so that subsequent
1623 * commands, such as breadcrumb interrupts, are strictly ordered
1624 * wrt the contents of the write cache being flushed to memory
1625 * (and thus being coherent from the CPU).
1627 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1629 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
) {
1630 cmd
|= MI_INVALIDATE_TLB
;
1631 if (ring
== &dev_priv
->ring
[VCS
])
1632 cmd
|= MI_INVALIDATE_BSD
;
1635 intel_logical_ring_emit(ringbuf
, cmd
);
1636 intel_logical_ring_emit(ringbuf
,
1637 I915_GEM_HWS_SCRATCH_ADDR
|
1638 MI_FLUSH_DW_USE_GTT
);
1639 intel_logical_ring_emit(ringbuf
, 0); /* upper addr */
1640 intel_logical_ring_emit(ringbuf
, 0); /* value */
1641 intel_logical_ring_advance(ringbuf
);
1646 static int gen8_emit_flush_render(struct drm_i915_gem_request
*request
,
1647 u32 invalidate_domains
,
1650 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1651 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1652 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1657 flags
|= PIPE_CONTROL_CS_STALL
;
1659 if (flush_domains
) {
1660 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
1661 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
1664 if (invalidate_domains
) {
1665 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
1666 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
1667 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
1668 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1669 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
1670 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
1671 flags
|= PIPE_CONTROL_QW_WRITE
;
1672 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
1676 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1679 vf_flush_wa
= INTEL_INFO(ring
->dev
)->gen
>= 9 &&
1680 flags
& PIPE_CONTROL_VF_CACHE_INVALIDATE
;
1682 ret
= intel_logical_ring_begin(request
, vf_flush_wa
? 12 : 6);
1687 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1688 intel_logical_ring_emit(ringbuf
, 0);
1689 intel_logical_ring_emit(ringbuf
, 0);
1690 intel_logical_ring_emit(ringbuf
, 0);
1691 intel_logical_ring_emit(ringbuf
, 0);
1692 intel_logical_ring_emit(ringbuf
, 0);
1695 intel_logical_ring_emit(ringbuf
, GFX_OP_PIPE_CONTROL(6));
1696 intel_logical_ring_emit(ringbuf
, flags
);
1697 intel_logical_ring_emit(ringbuf
, scratch_addr
);
1698 intel_logical_ring_emit(ringbuf
, 0);
1699 intel_logical_ring_emit(ringbuf
, 0);
1700 intel_logical_ring_emit(ringbuf
, 0);
1701 intel_logical_ring_advance(ringbuf
);
1706 static u32
gen8_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1708 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1711 static void gen8_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1713 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1716 static int gen8_emit_request(struct drm_i915_gem_request
*request
)
1718 struct intel_ringbuffer
*ringbuf
= request
->ringbuf
;
1719 struct intel_engine_cs
*ring
= ringbuf
->ring
;
1724 * Reserve space for 2 NOOPs at the end of each request to be
1725 * used as a workaround for not being allowed to do lite
1726 * restore with HEAD==TAIL (WaIdleLiteRestore).
1728 ret
= intel_logical_ring_begin(request
, 8);
1732 cmd
= MI_STORE_DWORD_IMM_GEN4
;
1733 cmd
|= MI_GLOBAL_GTT
;
1735 intel_logical_ring_emit(ringbuf
, cmd
);
1736 intel_logical_ring_emit(ringbuf
,
1737 (ring
->status_page
.gfx_addr
+
1738 (I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
)));
1739 intel_logical_ring_emit(ringbuf
, 0);
1740 intel_logical_ring_emit(ringbuf
, i915_gem_request_get_seqno(request
));
1741 intel_logical_ring_emit(ringbuf
, MI_USER_INTERRUPT
);
1742 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1743 intel_logical_ring_advance_and_submit(request
);
1746 * Here we add two extra NOOPs as padding to avoid
1747 * lite restore of a context with HEAD==TAIL.
1749 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1750 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
1751 intel_logical_ring_advance(ringbuf
);
1756 static int intel_lr_context_render_state_init(struct drm_i915_gem_request
*req
)
1758 struct render_state so
;
1761 ret
= i915_gem_render_state_prepare(req
->ring
, &so
);
1765 if (so
.rodata
== NULL
)
1768 ret
= req
->ring
->emit_bb_start(req
, so
.ggtt_offset
,
1769 I915_DISPATCH_SECURE
);
1773 ret
= req
->ring
->emit_bb_start(req
,
1774 (so
.ggtt_offset
+ so
.aux_batch_offset
),
1775 I915_DISPATCH_SECURE
);
1779 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so
.obj
), req
);
1782 i915_gem_render_state_fini(&so
);
1786 static int gen8_init_rcs_context(struct drm_i915_gem_request
*req
)
1790 ret
= intel_logical_ring_workarounds_emit(req
);
1794 ret
= intel_rcs_context_init_mocs(req
);
1796 * Failing to program the MOCS is non-fatal.The system will not
1797 * run at peak performance. So generate an error and carry on.
1800 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1802 return intel_lr_context_render_state_init(req
);
1806 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1808 * @ring: Engine Command Streamer.
1811 void intel_logical_ring_cleanup(struct intel_engine_cs
*ring
)
1813 struct drm_i915_private
*dev_priv
;
1815 if (!intel_ring_initialized(ring
))
1818 dev_priv
= ring
->dev
->dev_private
;
1820 intel_logical_ring_stop(ring
);
1821 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1824 ring
->cleanup(ring
);
1826 i915_cmd_parser_fini_ring(ring
);
1827 i915_gem_batch_pool_fini(&ring
->batch_pool
);
1829 if (ring
->status_page
.obj
) {
1830 kunmap(sg_page(ring
->status_page
.obj
->pages
->sgl
));
1831 ring
->status_page
.obj
= NULL
;
1834 lrc_destroy_wa_ctx_obj(ring
);
1837 static int logical_ring_init(struct drm_device
*dev
, struct intel_engine_cs
*ring
)
1841 /* Intentionally left blank. */
1842 ring
->buffer
= NULL
;
1845 INIT_LIST_HEAD(&ring
->active_list
);
1846 INIT_LIST_HEAD(&ring
->request_list
);
1847 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
1848 init_waitqueue_head(&ring
->irq_queue
);
1850 INIT_LIST_HEAD(&ring
->execlist_queue
);
1851 INIT_LIST_HEAD(&ring
->execlist_retired_req_list
);
1852 spin_lock_init(&ring
->execlist_lock
);
1854 ret
= i915_cmd_parser_init_ring(ring
);
1858 ret
= intel_lr_context_deferred_create(ring
->default_context
, ring
);
1863 static int logical_render_ring_init(struct drm_device
*dev
)
1865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1866 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
1869 ring
->name
= "render ring";
1871 ring
->mmio_base
= RENDER_RING_BASE
;
1872 ring
->irq_enable_mask
=
1873 GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1874 ring
->irq_keep_mask
=
1875 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
;
1876 if (HAS_L3_DPF(dev
))
1877 ring
->irq_keep_mask
|= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
1879 if (INTEL_INFO(dev
)->gen
>= 9)
1880 ring
->init_hw
= gen9_init_render_ring
;
1882 ring
->init_hw
= gen8_init_render_ring
;
1883 ring
->init_context
= gen8_init_rcs_context
;
1884 ring
->cleanup
= intel_fini_pipe_control
;
1885 ring
->get_seqno
= gen8_get_seqno
;
1886 ring
->set_seqno
= gen8_set_seqno
;
1887 ring
->emit_request
= gen8_emit_request
;
1888 ring
->emit_flush
= gen8_emit_flush_render
;
1889 ring
->irq_get
= gen8_logical_ring_get_irq
;
1890 ring
->irq_put
= gen8_logical_ring_put_irq
;
1891 ring
->emit_bb_start
= gen8_emit_bb_start
;
1895 ret
= intel_init_pipe_control(ring
);
1899 ret
= intel_init_workaround_bb(ring
);
1902 * We continue even if we fail to initialize WA batch
1903 * because we only expect rare glitches but nothing
1904 * critical to prevent us from using GPU
1906 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1910 ret
= logical_ring_init(dev
, ring
);
1912 lrc_destroy_wa_ctx_obj(ring
);
1918 static int logical_bsd_ring_init(struct drm_device
*dev
)
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
1923 ring
->name
= "bsd ring";
1925 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1926 ring
->irq_enable_mask
=
1927 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1928 ring
->irq_keep_mask
=
1929 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
1931 ring
->init_hw
= gen8_init_common_ring
;
1932 ring
->get_seqno
= gen8_get_seqno
;
1933 ring
->set_seqno
= gen8_set_seqno
;
1934 ring
->emit_request
= gen8_emit_request
;
1935 ring
->emit_flush
= gen8_emit_flush
;
1936 ring
->irq_get
= gen8_logical_ring_get_irq
;
1937 ring
->irq_put
= gen8_logical_ring_put_irq
;
1938 ring
->emit_bb_start
= gen8_emit_bb_start
;
1940 return logical_ring_init(dev
, ring
);
1943 static int logical_bsd2_ring_init(struct drm_device
*dev
)
1945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1946 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
1948 ring
->name
= "bds2 ring";
1950 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
1951 ring
->irq_enable_mask
=
1952 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1953 ring
->irq_keep_mask
=
1954 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
1956 ring
->init_hw
= gen8_init_common_ring
;
1957 ring
->get_seqno
= gen8_get_seqno
;
1958 ring
->set_seqno
= gen8_set_seqno
;
1959 ring
->emit_request
= gen8_emit_request
;
1960 ring
->emit_flush
= gen8_emit_flush
;
1961 ring
->irq_get
= gen8_logical_ring_get_irq
;
1962 ring
->irq_put
= gen8_logical_ring_put_irq
;
1963 ring
->emit_bb_start
= gen8_emit_bb_start
;
1965 return logical_ring_init(dev
, ring
);
1968 static int logical_blt_ring_init(struct drm_device
*dev
)
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
1973 ring
->name
= "blitter ring";
1975 ring
->mmio_base
= BLT_RING_BASE
;
1976 ring
->irq_enable_mask
=
1977 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1978 ring
->irq_keep_mask
=
1979 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1981 ring
->init_hw
= gen8_init_common_ring
;
1982 ring
->get_seqno
= gen8_get_seqno
;
1983 ring
->set_seqno
= gen8_set_seqno
;
1984 ring
->emit_request
= gen8_emit_request
;
1985 ring
->emit_flush
= gen8_emit_flush
;
1986 ring
->irq_get
= gen8_logical_ring_get_irq
;
1987 ring
->irq_put
= gen8_logical_ring_put_irq
;
1988 ring
->emit_bb_start
= gen8_emit_bb_start
;
1990 return logical_ring_init(dev
, ring
);
1993 static int logical_vebox_ring_init(struct drm_device
*dev
)
1995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
1998 ring
->name
= "video enhancement ring";
2000 ring
->mmio_base
= VEBOX_RING_BASE
;
2001 ring
->irq_enable_mask
=
2002 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2003 ring
->irq_keep_mask
=
2004 GT_CONTEXT_SWITCH_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2006 ring
->init_hw
= gen8_init_common_ring
;
2007 ring
->get_seqno
= gen8_get_seqno
;
2008 ring
->set_seqno
= gen8_set_seqno
;
2009 ring
->emit_request
= gen8_emit_request
;
2010 ring
->emit_flush
= gen8_emit_flush
;
2011 ring
->irq_get
= gen8_logical_ring_get_irq
;
2012 ring
->irq_put
= gen8_logical_ring_put_irq
;
2013 ring
->emit_bb_start
= gen8_emit_bb_start
;
2015 return logical_ring_init(dev
, ring
);
2019 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
2022 * This function inits the engines for an Execlists submission style (the equivalent in the
2023 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
2024 * those engines that are present in the hardware.
2026 * Return: non-zero if the initialization failed.
2028 int intel_logical_rings_init(struct drm_device
*dev
)
2030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2033 ret
= logical_render_ring_init(dev
);
2038 ret
= logical_bsd_ring_init(dev
);
2040 goto cleanup_render_ring
;
2044 ret
= logical_blt_ring_init(dev
);
2046 goto cleanup_bsd_ring
;
2049 if (HAS_VEBOX(dev
)) {
2050 ret
= logical_vebox_ring_init(dev
);
2052 goto cleanup_blt_ring
;
2055 if (HAS_BSD2(dev
)) {
2056 ret
= logical_bsd2_ring_init(dev
);
2058 goto cleanup_vebox_ring
;
2061 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
2063 goto cleanup_bsd2_ring
;
2068 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS2
]);
2070 intel_logical_ring_cleanup(&dev_priv
->ring
[VECS
]);
2072 intel_logical_ring_cleanup(&dev_priv
->ring
[BCS
]);
2074 intel_logical_ring_cleanup(&dev_priv
->ring
[VCS
]);
2075 cleanup_render_ring
:
2076 intel_logical_ring_cleanup(&dev_priv
->ring
[RCS
]);
2082 make_rpcs(struct drm_device
*dev
)
2087 * No explicit RPCS request is needed to ensure full
2088 * slice/subslice/EU enablement prior to Gen9.
2090 if (INTEL_INFO(dev
)->gen
< 9)
2094 * Starting in Gen9, render power gating can leave
2095 * slice/subslice/EU in a partially enabled state. We
2096 * must make an explicit request through RPCS for full
2099 if (INTEL_INFO(dev
)->has_slice_pg
) {
2100 rpcs
|= GEN8_RPCS_S_CNT_ENABLE
;
2101 rpcs
|= INTEL_INFO(dev
)->slice_total
<<
2102 GEN8_RPCS_S_CNT_SHIFT
;
2103 rpcs
|= GEN8_RPCS_ENABLE
;
2106 if (INTEL_INFO(dev
)->has_subslice_pg
) {
2107 rpcs
|= GEN8_RPCS_SS_CNT_ENABLE
;
2108 rpcs
|= INTEL_INFO(dev
)->subslice_per_slice
<<
2109 GEN8_RPCS_SS_CNT_SHIFT
;
2110 rpcs
|= GEN8_RPCS_ENABLE
;
2113 if (INTEL_INFO(dev
)->has_eu_pg
) {
2114 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2115 GEN8_RPCS_EU_MIN_SHIFT
;
2116 rpcs
|= INTEL_INFO(dev
)->eu_per_subslice
<<
2117 GEN8_RPCS_EU_MAX_SHIFT
;
2118 rpcs
|= GEN8_RPCS_ENABLE
;
2125 populate_lr_context(struct intel_context
*ctx
, struct drm_i915_gem_object
*ctx_obj
,
2126 struct intel_engine_cs
*ring
, struct intel_ringbuffer
*ringbuf
)
2128 struct drm_device
*dev
= ring
->dev
;
2129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2132 uint32_t *reg_state
;
2136 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2138 ret
= i915_gem_object_set_to_cpu_domain(ctx_obj
, true);
2140 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2144 ret
= i915_gem_object_get_pages(ctx_obj
);
2146 DRM_DEBUG_DRIVER("Could not get object pages\n");
2150 i915_gem_object_pin_pages(ctx_obj
);
2152 /* The second page of the context object contains some fields which must
2153 * be set up prior to the first execution. */
2154 page
= i915_gem_object_get_page(ctx_obj
, 1);
2155 reg_state
= kmap_atomic(page
);
2157 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2158 * commands followed by (reg, value) pairs. The values we are setting here are
2159 * only for the first context restore: on a subsequent save, the GPU will
2160 * recreate this batchbuffer with new values (including all the missing
2161 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2162 if (ring
->id
== RCS
)
2163 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(14);
2165 reg_state
[CTX_LRI_HEADER_0
] = MI_LOAD_REGISTER_IMM(11);
2166 reg_state
[CTX_LRI_HEADER_0
] |= MI_LRI_FORCE_POSTED
;
2167 reg_state
[CTX_CONTEXT_CONTROL
] = RING_CONTEXT_CONTROL(ring
);
2168 reg_state
[CTX_CONTEXT_CONTROL
+1] =
2169 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH
|
2170 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT
|
2171 CTX_CTRL_RS_CTX_ENABLE
);
2172 reg_state
[CTX_RING_HEAD
] = RING_HEAD(ring
->mmio_base
);
2173 reg_state
[CTX_RING_HEAD
+1] = 0;
2174 reg_state
[CTX_RING_TAIL
] = RING_TAIL(ring
->mmio_base
);
2175 reg_state
[CTX_RING_TAIL
+1] = 0;
2176 reg_state
[CTX_RING_BUFFER_START
] = RING_START(ring
->mmio_base
);
2177 /* Ring buffer start address is not known until the buffer is pinned.
2178 * It is written to the context image in execlists_update_context()
2180 reg_state
[CTX_RING_BUFFER_CONTROL
] = RING_CTL(ring
->mmio_base
);
2181 reg_state
[CTX_RING_BUFFER_CONTROL
+1] =
2182 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
) | RING_VALID
;
2183 reg_state
[CTX_BB_HEAD_U
] = ring
->mmio_base
+ 0x168;
2184 reg_state
[CTX_BB_HEAD_U
+1] = 0;
2185 reg_state
[CTX_BB_HEAD_L
] = ring
->mmio_base
+ 0x140;
2186 reg_state
[CTX_BB_HEAD_L
+1] = 0;
2187 reg_state
[CTX_BB_STATE
] = ring
->mmio_base
+ 0x110;
2188 reg_state
[CTX_BB_STATE
+1] = (1<<5);
2189 reg_state
[CTX_SECOND_BB_HEAD_U
] = ring
->mmio_base
+ 0x11c;
2190 reg_state
[CTX_SECOND_BB_HEAD_U
+1] = 0;
2191 reg_state
[CTX_SECOND_BB_HEAD_L
] = ring
->mmio_base
+ 0x114;
2192 reg_state
[CTX_SECOND_BB_HEAD_L
+1] = 0;
2193 reg_state
[CTX_SECOND_BB_STATE
] = ring
->mmio_base
+ 0x118;
2194 reg_state
[CTX_SECOND_BB_STATE
+1] = 0;
2195 if (ring
->id
== RCS
) {
2196 reg_state
[CTX_BB_PER_CTX_PTR
] = ring
->mmio_base
+ 0x1c0;
2197 reg_state
[CTX_BB_PER_CTX_PTR
+1] = 0;
2198 reg_state
[CTX_RCS_INDIRECT_CTX
] = ring
->mmio_base
+ 0x1c4;
2199 reg_state
[CTX_RCS_INDIRECT_CTX
+1] = 0;
2200 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
] = ring
->mmio_base
+ 0x1c8;
2201 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] = 0;
2202 if (ring
->wa_ctx
.obj
) {
2203 struct i915_ctx_workarounds
*wa_ctx
= &ring
->wa_ctx
;
2204 uint32_t ggtt_offset
= i915_gem_obj_ggtt_offset(wa_ctx
->obj
);
2206 reg_state
[CTX_RCS_INDIRECT_CTX
+1] =
2207 (ggtt_offset
+ wa_ctx
->indirect_ctx
.offset
* sizeof(uint32_t)) |
2208 (wa_ctx
->indirect_ctx
.size
/ CACHELINE_DWORDS
);
2210 reg_state
[CTX_RCS_INDIRECT_CTX_OFFSET
+1] =
2211 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
<< 6;
2213 reg_state
[CTX_BB_PER_CTX_PTR
+1] =
2214 (ggtt_offset
+ wa_ctx
->per_ctx
.offset
* sizeof(uint32_t)) |
2218 reg_state
[CTX_LRI_HEADER_1
] = MI_LOAD_REGISTER_IMM(9);
2219 reg_state
[CTX_LRI_HEADER_1
] |= MI_LRI_FORCE_POSTED
;
2220 reg_state
[CTX_CTX_TIMESTAMP
] = ring
->mmio_base
+ 0x3a8;
2221 reg_state
[CTX_CTX_TIMESTAMP
+1] = 0;
2222 reg_state
[CTX_PDP3_UDW
] = GEN8_RING_PDP_UDW(ring
, 3);
2223 reg_state
[CTX_PDP3_LDW
] = GEN8_RING_PDP_LDW(ring
, 3);
2224 reg_state
[CTX_PDP2_UDW
] = GEN8_RING_PDP_UDW(ring
, 2);
2225 reg_state
[CTX_PDP2_LDW
] = GEN8_RING_PDP_LDW(ring
, 2);
2226 reg_state
[CTX_PDP1_UDW
] = GEN8_RING_PDP_UDW(ring
, 1);
2227 reg_state
[CTX_PDP1_LDW
] = GEN8_RING_PDP_LDW(ring
, 1);
2228 reg_state
[CTX_PDP0_UDW
] = GEN8_RING_PDP_UDW(ring
, 0);
2229 reg_state
[CTX_PDP0_LDW
] = GEN8_RING_PDP_LDW(ring
, 0);
2231 /* With dynamic page allocation, PDPs may not be allocated at this point,
2232 * Point the unallocated PDPs to the scratch page
2234 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 3);
2235 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 2);
2236 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 1);
2237 ASSIGN_CTX_PDP(ppgtt
, reg_state
, 0);
2238 if (ring
->id
== RCS
) {
2239 reg_state
[CTX_LRI_HEADER_2
] = MI_LOAD_REGISTER_IMM(1);
2240 reg_state
[CTX_R_PWR_CLK_STATE
] = GEN8_R_PWR_CLK_STATE
;
2241 reg_state
[CTX_R_PWR_CLK_STATE
+1] = make_rpcs(dev
);
2244 kunmap_atomic(reg_state
);
2247 set_page_dirty(page
);
2248 i915_gem_object_unpin_pages(ctx_obj
);
2254 * intel_lr_context_free() - free the LRC specific bits of a context
2255 * @ctx: the LR context to free.
2257 * The real context freeing is done in i915_gem_context_free: this only
2258 * takes care of the bits that are LRC related: the per-engine backing
2259 * objects and the logical ringbuffer.
2261 void intel_lr_context_free(struct intel_context
*ctx
)
2265 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2266 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[i
].state
;
2269 struct intel_ringbuffer
*ringbuf
=
2270 ctx
->engine
[i
].ringbuf
;
2271 struct intel_engine_cs
*ring
= ringbuf
->ring
;
2273 if (ctx
== ring
->default_context
) {
2274 intel_unpin_ringbuffer_obj(ringbuf
);
2275 i915_gem_object_ggtt_unpin(ctx_obj
);
2277 WARN_ON(ctx
->engine
[ring
->id
].pin_count
);
2278 intel_destroy_ringbuffer_obj(ringbuf
);
2280 drm_gem_object_unreference(&ctx_obj
->base
);
2285 static uint32_t get_lr_context_size(struct intel_engine_cs
*ring
)
2289 WARN_ON(INTEL_INFO(ring
->dev
)->gen
< 8);
2293 if (INTEL_INFO(ring
->dev
)->gen
>= 9)
2294 ret
= GEN9_LR_CONTEXT_RENDER_SIZE
;
2296 ret
= GEN8_LR_CONTEXT_RENDER_SIZE
;
2302 ret
= GEN8_LR_CONTEXT_OTHER_SIZE
;
2309 static void lrc_setup_hardware_status_page(struct intel_engine_cs
*ring
,
2310 struct drm_i915_gem_object
*default_ctx_obj
)
2312 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2314 /* The status page is offset 0 from the default context object
2316 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(default_ctx_obj
);
2317 ring
->status_page
.page_addr
=
2318 kmap(sg_page(default_ctx_obj
->pages
->sgl
));
2319 ring
->status_page
.obj
= default_ctx_obj
;
2321 I915_WRITE(RING_HWS_PGA(ring
->mmio_base
),
2322 (u32
)ring
->status_page
.gfx_addr
);
2323 POSTING_READ(RING_HWS_PGA(ring
->mmio_base
));
2327 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
2328 * @ctx: LR context to create.
2329 * @ring: engine to be used with the context.
2331 * This function can be called more than once, with different engines, if we plan
2332 * to use the context with them. The context backing objects and the ringbuffers
2333 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
2334 * the creation is a deferred call: it's better to make sure first that we need to use
2335 * a given ring with the context.
2337 * Return: non-zero on error.
2339 int intel_lr_context_deferred_create(struct intel_context
*ctx
,
2340 struct intel_engine_cs
*ring
)
2342 const bool is_global_default_ctx
= (ctx
== ring
->default_context
);
2343 struct drm_device
*dev
= ring
->dev
;
2344 struct drm_i915_gem_object
*ctx_obj
;
2345 uint32_t context_size
;
2346 struct intel_ringbuffer
*ringbuf
;
2349 WARN_ON(ctx
->legacy_hw_ctx
.rcs_state
!= NULL
);
2350 WARN_ON(ctx
->engine
[ring
->id
].state
);
2352 context_size
= round_up(get_lr_context_size(ring
), 4096);
2354 ctx_obj
= i915_gem_alloc_object(dev
, context_size
);
2356 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2360 if (is_global_default_ctx
) {
2361 ret
= i915_gem_obj_ggtt_pin(ctx_obj
, GEN8_LR_CONTEXT_ALIGN
, 0);
2363 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
2365 drm_gem_object_unreference(&ctx_obj
->base
);
2370 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2372 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2375 goto error_unpin_ctx
;
2378 ringbuf
->ring
= ring
;
2380 ringbuf
->size
= 32 * PAGE_SIZE
;
2381 ringbuf
->effective_size
= ringbuf
->size
;
2384 ringbuf
->last_retired_head
= -1;
2385 intel_ring_update_space(ringbuf
);
2387 if (ringbuf
->obj
== NULL
) {
2388 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2391 "Failed to allocate ringbuffer obj %s: %d\n",
2393 goto error_free_rbuf
;
2396 if (is_global_default_ctx
) {
2397 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2400 "Failed to pin and map ringbuffer %s: %d\n",
2402 goto error_destroy_rbuf
;
2408 ret
= populate_lr_context(ctx
, ctx_obj
, ring
, ringbuf
);
2410 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret
);
2414 ctx
->engine
[ring
->id
].ringbuf
= ringbuf
;
2415 ctx
->engine
[ring
->id
].state
= ctx_obj
;
2417 if (ctx
== ring
->default_context
)
2418 lrc_setup_hardware_status_page(ring
, ctx_obj
);
2419 else if (ring
->id
== RCS
&& !ctx
->rcs_initialized
) {
2420 if (ring
->init_context
) {
2421 struct drm_i915_gem_request
*req
;
2423 ret
= i915_gem_request_alloc(ring
, ctx
, &req
);
2427 ret
= ring
->init_context(req
);
2429 DRM_ERROR("ring init context: %d\n", ret
);
2430 i915_gem_request_cancel(req
);
2431 ctx
->engine
[ring
->id
].ringbuf
= NULL
;
2432 ctx
->engine
[ring
->id
].state
= NULL
;
2436 i915_add_request_no_flush(req
);
2439 ctx
->rcs_initialized
= true;
2445 if (is_global_default_ctx
)
2446 intel_unpin_ringbuffer_obj(ringbuf
);
2448 intel_destroy_ringbuffer_obj(ringbuf
);
2452 if (is_global_default_ctx
)
2453 i915_gem_object_ggtt_unpin(ctx_obj
);
2454 drm_gem_object_unreference(&ctx_obj
->base
);
2458 void intel_lr_context_reset(struct drm_device
*dev
,
2459 struct intel_context
*ctx
)
2461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2462 struct intel_engine_cs
*ring
;
2465 for_each_ring(ring
, dev_priv
, i
) {
2466 struct drm_i915_gem_object
*ctx_obj
=
2467 ctx
->engine
[ring
->id
].state
;
2468 struct intel_ringbuffer
*ringbuf
=
2469 ctx
->engine
[ring
->id
].ringbuf
;
2470 uint32_t *reg_state
;
2476 if (i915_gem_object_get_pages(ctx_obj
)) {
2477 WARN(1, "Failed get_pages for context obj\n");
2480 page
= i915_gem_object_get_page(ctx_obj
, 1);
2481 reg_state
= kmap_atomic(page
);
2483 reg_state
[CTX_RING_HEAD
+1] = 0;
2484 reg_state
[CTX_RING_TAIL
+1] = 0;
2486 kunmap_atomic(reg_state
);