0794dc84ff01732ffe2c79e5c90bd99da54e5d45
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30 #include <acpi/button.h>
31 #include <linux/dmi.h>
32 #include <linux/i2c.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include "i915_drv.h"
41 #include <linux/acpi.h>
42
43 /* Private structure for the integrated LVDS support */
44 struct intel_lvds_connector {
45 struct intel_connector base;
46
47 struct notifier_block lid_notifier;
48 };
49
50 struct intel_lvds_encoder {
51 struct intel_encoder base;
52
53 bool is_dual_link;
54 u32 reg;
55 u32 a3_power;
56
57 struct intel_lvds_connector *attached_connector;
58 };
59
60 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
61 {
62 return container_of(encoder, struct intel_lvds_encoder, base.base);
63 }
64
65 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
66 {
67 return container_of(connector, struct intel_lvds_connector, base.base);
68 }
69
70 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
71 enum pipe *pipe)
72 {
73 struct drm_device *dev = encoder->base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
75 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
76 enum intel_display_power_domain power_domain;
77 u32 tmp;
78
79 power_domain = intel_display_port_power_domain(encoder);
80 if (!intel_display_power_is_enabled(dev_priv, power_domain))
81 return false;
82
83 tmp = I915_READ(lvds_encoder->reg);
84
85 if (!(tmp & LVDS_PORT_EN))
86 return false;
87
88 if (HAS_PCH_CPT(dev))
89 *pipe = PORT_TO_PIPE_CPT(tmp);
90 else
91 *pipe = PORT_TO_PIPE(tmp);
92
93 return true;
94 }
95
96 static void intel_lvds_get_config(struct intel_encoder *encoder,
97 struct intel_crtc_state *pipe_config)
98 {
99 struct drm_device *dev = encoder->base.dev;
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 u32 lvds_reg, tmp, flags = 0;
102 int dotclock;
103
104 if (HAS_PCH_SPLIT(dev))
105 lvds_reg = PCH_LVDS;
106 else
107 lvds_reg = LVDS;
108
109 tmp = I915_READ(lvds_reg);
110 if (tmp & LVDS_HSYNC_POLARITY)
111 flags |= DRM_MODE_FLAG_NHSYNC;
112 else
113 flags |= DRM_MODE_FLAG_PHSYNC;
114 if (tmp & LVDS_VSYNC_POLARITY)
115 flags |= DRM_MODE_FLAG_NVSYNC;
116 else
117 flags |= DRM_MODE_FLAG_PVSYNC;
118
119 pipe_config->base.adjusted_mode.flags |= flags;
120
121 /* gen2/3 store dither state in pfit control, needs to match */
122 if (INTEL_INFO(dev)->gen < 4) {
123 tmp = I915_READ(PFIT_CONTROL);
124
125 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
126 }
127
128 dotclock = pipe_config->port_clock;
129
130 if (HAS_PCH_SPLIT(dev_priv->dev))
131 ironlake_check_encoder_dotclock(pipe_config, dotclock);
132
133 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
134 }
135
136 static void intel_pre_enable_lvds(struct intel_encoder *encoder)
137 {
138 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
139 struct drm_device *dev = encoder->base.dev;
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
142 const struct drm_display_mode *adjusted_mode =
143 &crtc->config->base.adjusted_mode;
144 int pipe = crtc->pipe;
145 u32 temp;
146
147 if (HAS_PCH_SPLIT(dev)) {
148 assert_fdi_rx_pll_disabled(dev_priv, pipe);
149 assert_shared_dpll_disabled(dev_priv,
150 intel_crtc_to_shared_dpll(crtc));
151 } else {
152 assert_pll_disabled(dev_priv, pipe);
153 }
154
155 temp = I915_READ(lvds_encoder->reg);
156 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
157
158 if (HAS_PCH_CPT(dev)) {
159 temp &= ~PORT_TRANS_SEL_MASK;
160 temp |= PORT_TRANS_SEL_CPT(pipe);
161 } else {
162 if (pipe == 1) {
163 temp |= LVDS_PIPEB_SELECT;
164 } else {
165 temp &= ~LVDS_PIPEB_SELECT;
166 }
167 }
168
169 /* set the corresponsding LVDS_BORDER bit */
170 temp &= ~LVDS_BORDER_ENABLE;
171 temp |= crtc->config->gmch_pfit.lvds_border_bits;
172 /* Set the B0-B3 data pairs corresponding to whether we're going to
173 * set the DPLLs for dual-channel mode or not.
174 */
175 if (lvds_encoder->is_dual_link)
176 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
177 else
178 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
179
180 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
181 * appropriately here, but we need to look more thoroughly into how
182 * panels behave in the two modes. For now, let's just maintain the
183 * value we got from the BIOS.
184 */
185 temp &= ~LVDS_A3_POWER_MASK;
186 temp |= lvds_encoder->a3_power;
187
188 /* Set the dithering flag on LVDS as needed, note that there is no
189 * special lvds dither control bit on pch-split platforms, dithering is
190 * only controlled through the PIPECONF reg. */
191 if (INTEL_INFO(dev)->gen == 4) {
192 /* Bspec wording suggests that LVDS port dithering only exists
193 * for 18bpp panels. */
194 if (crtc->config->dither && crtc->config->pipe_bpp == 18)
195 temp |= LVDS_ENABLE_DITHER;
196 else
197 temp &= ~LVDS_ENABLE_DITHER;
198 }
199 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
200 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
201 temp |= LVDS_HSYNC_POLARITY;
202 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
203 temp |= LVDS_VSYNC_POLARITY;
204
205 I915_WRITE(lvds_encoder->reg, temp);
206 }
207
208 /**
209 * Sets the power state for the panel.
210 */
211 static void intel_enable_lvds(struct intel_encoder *encoder)
212 {
213 struct drm_device *dev = encoder->base.dev;
214 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
215 struct intel_connector *intel_connector =
216 &lvds_encoder->attached_connector->base;
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 u32 ctl_reg, stat_reg;
219
220 if (HAS_PCH_SPLIT(dev)) {
221 ctl_reg = PCH_PP_CONTROL;
222 stat_reg = PCH_PP_STATUS;
223 } else {
224 ctl_reg = PP_CONTROL;
225 stat_reg = PP_STATUS;
226 }
227
228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
229
230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
231 POSTING_READ(lvds_encoder->reg);
232 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
233 DRM_ERROR("timed out waiting for panel to power on\n");
234
235 intel_panel_enable_backlight(intel_connector);
236 }
237
238 static void intel_disable_lvds(struct intel_encoder *encoder)
239 {
240 struct drm_device *dev = encoder->base.dev;
241 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 u32 ctl_reg, stat_reg;
244
245 if (HAS_PCH_SPLIT(dev)) {
246 ctl_reg = PCH_PP_CONTROL;
247 stat_reg = PCH_PP_STATUS;
248 } else {
249 ctl_reg = PP_CONTROL;
250 stat_reg = PP_STATUS;
251 }
252
253 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
254 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
255 DRM_ERROR("timed out waiting for panel to power off\n");
256
257 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
258 POSTING_READ(lvds_encoder->reg);
259 }
260
261 static void gmch_disable_lvds(struct intel_encoder *encoder)
262 {
263 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
264 struct intel_connector *intel_connector =
265 &lvds_encoder->attached_connector->base;
266
267 intel_panel_disable_backlight(intel_connector);
268
269 intel_disable_lvds(encoder);
270 }
271
272 static void pch_disable_lvds(struct intel_encoder *encoder)
273 {
274 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
275 struct intel_connector *intel_connector =
276 &lvds_encoder->attached_connector->base;
277
278 intel_panel_disable_backlight(intel_connector);
279 }
280
281 static void pch_post_disable_lvds(struct intel_encoder *encoder)
282 {
283 intel_disable_lvds(encoder);
284 }
285
286 static enum drm_mode_status
287 intel_lvds_mode_valid(struct drm_connector *connector,
288 struct drm_display_mode *mode)
289 {
290 struct intel_connector *intel_connector = to_intel_connector(connector);
291 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
292 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
293
294 if (mode->hdisplay > fixed_mode->hdisplay)
295 return MODE_PANEL;
296 if (mode->vdisplay > fixed_mode->vdisplay)
297 return MODE_PANEL;
298 if (fixed_mode->clock > max_pixclk)
299 return MODE_CLOCK_HIGH;
300
301 return MODE_OK;
302 }
303
304 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
305 struct intel_crtc_state *pipe_config)
306 {
307 struct drm_device *dev = intel_encoder->base.dev;
308 struct intel_lvds_encoder *lvds_encoder =
309 to_lvds_encoder(&intel_encoder->base);
310 struct intel_connector *intel_connector =
311 &lvds_encoder->attached_connector->base;
312 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
313 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
314 unsigned int lvds_bpp;
315
316 /* Should never happen!! */
317 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
318 DRM_ERROR("Can't support LVDS on pipe A\n");
319 return false;
320 }
321
322 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
323 lvds_bpp = 8*3;
324 else
325 lvds_bpp = 6*3;
326
327 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
328 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
329 pipe_config->pipe_bpp, lvds_bpp);
330 pipe_config->pipe_bpp = lvds_bpp;
331 }
332
333 /*
334 * We have timings from the BIOS for the panel, put them in
335 * to the adjusted mode. The CRTC will be set up for this mode,
336 * with the panel scaling set up to source from the H/VDisplay
337 * of the original mode.
338 */
339 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
340 adjusted_mode);
341
342 if (HAS_PCH_SPLIT(dev)) {
343 pipe_config->has_pch_encoder = true;
344
345 intel_pch_panel_fitting(intel_crtc, pipe_config,
346 intel_connector->panel.fitting_mode);
347 } else {
348 intel_gmch_panel_fitting(intel_crtc, pipe_config,
349 intel_connector->panel.fitting_mode);
350
351 }
352
353 /*
354 * XXX: It would be nice to support lower refresh rates on the
355 * panels to reduce power consumption, and perhaps match the
356 * user's requested refresh rate.
357 */
358
359 return true;
360 }
361
362 /**
363 * Detect the LVDS connection.
364 *
365 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
366 * connected and closed means disconnected. We also send hotplug events as
367 * needed, using lid status notification from the input layer.
368 */
369 static enum drm_connector_status
370 intel_lvds_detect(struct drm_connector *connector, bool force)
371 {
372 struct drm_device *dev = connector->dev;
373 enum drm_connector_status status;
374
375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
376 connector->base.id, connector->name);
377
378 status = intel_panel_detect(dev);
379 if (status != connector_status_unknown)
380 return status;
381
382 return connector_status_connected;
383 }
384
385 /**
386 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
387 */
388 static int intel_lvds_get_modes(struct drm_connector *connector)
389 {
390 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
391 struct drm_device *dev = connector->dev;
392 struct drm_display_mode *mode;
393
394 /* use cached edid if we have one */
395 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
396 return drm_add_edid_modes(connector, lvds_connector->base.edid);
397
398 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
399 if (mode == NULL)
400 return 0;
401
402 drm_mode_probed_add(connector, mode);
403 return 1;
404 }
405
406 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
407 {
408 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
409 return 1;
410 }
411
412 /* The GPU hangs up on these systems if modeset is performed on LID open */
413 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
414 {
415 .callback = intel_no_modeset_on_lid_dmi_callback,
416 .ident = "Toshiba Tecra A11",
417 .matches = {
418 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
419 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
420 },
421 },
422
423 { } /* terminating entry */
424 };
425
426 /*
427 * Lid events. Note the use of 'modeset':
428 * - we set it to MODESET_ON_LID_OPEN on lid close,
429 * and set it to MODESET_DONE on open
430 * - we use it as a "only once" bit (ie we ignore
431 * duplicate events where it was already properly set)
432 * - the suspend/resume paths will set it to
433 * MODESET_SUSPENDED and ignore the lid open event,
434 * because they restore the mode ("lid open").
435 */
436 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
437 void *unused)
438 {
439 struct intel_lvds_connector *lvds_connector =
440 container_of(nb, struct intel_lvds_connector, lid_notifier);
441 struct drm_connector *connector = &lvds_connector->base.base;
442 struct drm_device *dev = connector->dev;
443 struct drm_i915_private *dev_priv = dev->dev_private;
444
445 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
446 return NOTIFY_OK;
447
448 mutex_lock(&dev_priv->modeset_restore_lock);
449 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
450 goto exit;
451 /*
452 * check and update the status of LVDS connector after receiving
453 * the LID nofication event.
454 */
455 connector->status = connector->funcs->detect(connector, false);
456
457 /* Don't force modeset on machines where it causes a GPU lockup */
458 if (dmi_check_system(intel_no_modeset_on_lid))
459 goto exit;
460 if (!acpi_lid_open()) {
461 /* do modeset on next lid open event */
462 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
463 goto exit;
464 }
465
466 if (dev_priv->modeset_restore == MODESET_DONE)
467 goto exit;
468
469 /*
470 * Some old platform's BIOS love to wreak havoc while the lid is closed.
471 * We try to detect this here and undo any damage. The split for PCH
472 * platforms is rather conservative and a bit arbitrary expect that on
473 * those platforms VGA disabling requires actual legacy VGA I/O access,
474 * and as part of the cleanup in the hw state restore we also redisable
475 * the vga plane.
476 */
477 if (!HAS_PCH_SPLIT(dev)) {
478 drm_modeset_lock_all(dev);
479 intel_display_resume(dev);
480 drm_modeset_unlock_all(dev);
481 }
482
483 dev_priv->modeset_restore = MODESET_DONE;
484
485 exit:
486 mutex_unlock(&dev_priv->modeset_restore_lock);
487 return NOTIFY_OK;
488 }
489
490 /**
491 * intel_lvds_destroy - unregister and free LVDS structures
492 * @connector: connector to free
493 *
494 * Unregister the DDC bus for this connector then free the driver private
495 * structure.
496 */
497 static void intel_lvds_destroy(struct drm_connector *connector)
498 {
499 struct intel_lvds_connector *lvds_connector =
500 to_lvds_connector(connector);
501
502 if (lvds_connector->lid_notifier.notifier_call)
503 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
504
505 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
506 kfree(lvds_connector->base.edid);
507
508 intel_panel_fini(&lvds_connector->base.panel);
509
510 drm_connector_cleanup(connector);
511 kfree(connector);
512 }
513
514 static int intel_lvds_set_property(struct drm_connector *connector,
515 struct drm_property *property,
516 uint64_t value)
517 {
518 struct intel_connector *intel_connector = to_intel_connector(connector);
519 struct drm_device *dev = connector->dev;
520
521 if (property == dev->mode_config.scaling_mode_property) {
522 struct drm_crtc *crtc;
523
524 if (value == DRM_MODE_SCALE_NONE) {
525 DRM_DEBUG_KMS("no scaling not supported\n");
526 return -EINVAL;
527 }
528
529 if (intel_connector->panel.fitting_mode == value) {
530 /* the LVDS scaling property is not changed */
531 return 0;
532 }
533 intel_connector->panel.fitting_mode = value;
534
535 crtc = intel_attached_encoder(connector)->base.crtc;
536 if (crtc && crtc->state->enable) {
537 /*
538 * If the CRTC is enabled, the display will be changed
539 * according to the new panel fitting mode.
540 */
541 intel_crtc_restore_mode(crtc);
542 }
543 }
544
545 return 0;
546 }
547
548 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
549 .get_modes = intel_lvds_get_modes,
550 .mode_valid = intel_lvds_mode_valid,
551 .best_encoder = intel_best_encoder,
552 };
553
554 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
555 .dpms = drm_atomic_helper_connector_dpms,
556 .detect = intel_lvds_detect,
557 .fill_modes = drm_helper_probe_single_connector_modes,
558 .set_property = intel_lvds_set_property,
559 .atomic_get_property = intel_connector_atomic_get_property,
560 .destroy = intel_lvds_destroy,
561 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
562 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
563 };
564
565 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
566 .destroy = intel_encoder_destroy,
567 };
568
569 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
570 {
571 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
572 return 1;
573 }
574
575 /* These systems claim to have LVDS, but really don't */
576 static const struct dmi_system_id intel_no_lvds[] = {
577 {
578 .callback = intel_no_lvds_dmi_callback,
579 .ident = "Apple Mac Mini (Core series)",
580 .matches = {
581 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
582 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
583 },
584 },
585 {
586 .callback = intel_no_lvds_dmi_callback,
587 .ident = "Apple Mac Mini (Core 2 series)",
588 .matches = {
589 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
590 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
591 },
592 },
593 {
594 .callback = intel_no_lvds_dmi_callback,
595 .ident = "MSI IM-945GSE-A",
596 .matches = {
597 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
598 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
599 },
600 },
601 {
602 .callback = intel_no_lvds_dmi_callback,
603 .ident = "Dell Studio Hybrid",
604 .matches = {
605 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
606 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
607 },
608 },
609 {
610 .callback = intel_no_lvds_dmi_callback,
611 .ident = "Dell OptiPlex FX170",
612 .matches = {
613 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
614 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
615 },
616 },
617 {
618 .callback = intel_no_lvds_dmi_callback,
619 .ident = "AOpen Mini PC",
620 .matches = {
621 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
622 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
623 },
624 },
625 {
626 .callback = intel_no_lvds_dmi_callback,
627 .ident = "AOpen Mini PC MP915",
628 .matches = {
629 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
630 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
631 },
632 },
633 {
634 .callback = intel_no_lvds_dmi_callback,
635 .ident = "AOpen i915GMm-HFS",
636 .matches = {
637 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
638 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
639 },
640 },
641 {
642 .callback = intel_no_lvds_dmi_callback,
643 .ident = "AOpen i45GMx-I",
644 .matches = {
645 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
646 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
647 },
648 },
649 {
650 .callback = intel_no_lvds_dmi_callback,
651 .ident = "Aopen i945GTt-VFA",
652 .matches = {
653 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
654 },
655 },
656 {
657 .callback = intel_no_lvds_dmi_callback,
658 .ident = "Clientron U800",
659 .matches = {
660 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
661 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
662 },
663 },
664 {
665 .callback = intel_no_lvds_dmi_callback,
666 .ident = "Clientron E830",
667 .matches = {
668 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
669 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
670 },
671 },
672 {
673 .callback = intel_no_lvds_dmi_callback,
674 .ident = "Asus EeeBox PC EB1007",
675 .matches = {
676 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
677 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
678 },
679 },
680 {
681 .callback = intel_no_lvds_dmi_callback,
682 .ident = "Asus AT5NM10T-I",
683 .matches = {
684 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
685 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
686 },
687 },
688 {
689 .callback = intel_no_lvds_dmi_callback,
690 .ident = "Hewlett-Packard HP t5740",
691 .matches = {
692 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
693 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
694 },
695 },
696 {
697 .callback = intel_no_lvds_dmi_callback,
698 .ident = "Hewlett-Packard t5745",
699 .matches = {
700 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
701 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
702 },
703 },
704 {
705 .callback = intel_no_lvds_dmi_callback,
706 .ident = "Hewlett-Packard st5747",
707 .matches = {
708 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
709 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
710 },
711 },
712 {
713 .callback = intel_no_lvds_dmi_callback,
714 .ident = "MSI Wind Box DC500",
715 .matches = {
716 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
717 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
718 },
719 },
720 {
721 .callback = intel_no_lvds_dmi_callback,
722 .ident = "Gigabyte GA-D525TUD",
723 .matches = {
724 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
725 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
726 },
727 },
728 {
729 .callback = intel_no_lvds_dmi_callback,
730 .ident = "Supermicro X7SPA-H",
731 .matches = {
732 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
733 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
734 },
735 },
736 {
737 .callback = intel_no_lvds_dmi_callback,
738 .ident = "Fujitsu Esprimo Q900",
739 .matches = {
740 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
741 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
742 },
743 },
744 {
745 .callback = intel_no_lvds_dmi_callback,
746 .ident = "Intel D410PT",
747 .matches = {
748 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
749 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
750 },
751 },
752 {
753 .callback = intel_no_lvds_dmi_callback,
754 .ident = "Intel D425KT",
755 .matches = {
756 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
757 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
758 },
759 },
760 {
761 .callback = intel_no_lvds_dmi_callback,
762 .ident = "Intel D510MO",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
765 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
766 },
767 },
768 {
769 .callback = intel_no_lvds_dmi_callback,
770 .ident = "Intel D525MW",
771 .matches = {
772 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
773 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
774 },
775 },
776
777 { } /* terminating entry */
778 };
779
780 /*
781 * Enumerate the child dev array parsed from VBT to check whether
782 * the LVDS is present.
783 * If it is present, return 1.
784 * If it is not present, return false.
785 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
786 */
787 static bool lvds_is_present_in_vbt(struct drm_device *dev,
788 u8 *i2c_pin)
789 {
790 struct drm_i915_private *dev_priv = dev->dev_private;
791 int i;
792
793 if (!dev_priv->vbt.child_dev_num)
794 return true;
795
796 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
797 union child_device_config *uchild = dev_priv->vbt.child_dev + i;
798 struct old_child_dev_config *child = &uchild->old;
799
800 /* If the device type is not LFP, continue.
801 * We have to check both the new identifiers as well as the
802 * old for compatibility with some BIOSes.
803 */
804 if (child->device_type != DEVICE_TYPE_INT_LFP &&
805 child->device_type != DEVICE_TYPE_LFP)
806 continue;
807
808 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
809 *i2c_pin = child->i2c_pin;
810
811 /* However, we cannot trust the BIOS writers to populate
812 * the VBT correctly. Since LVDS requires additional
813 * information from AIM blocks, a non-zero addin offset is
814 * a good indicator that the LVDS is actually present.
815 */
816 if (child->addin_offset)
817 return true;
818
819 /* But even then some BIOS writers perform some black magic
820 * and instantiate the device without reference to any
821 * additional data. Trust that if the VBT was written into
822 * the OpRegion then they have validated the LVDS's existence.
823 */
824 if (dev_priv->opregion.vbt)
825 return true;
826 }
827
828 return false;
829 }
830
831 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
832 {
833 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
834 return 1;
835 }
836
837 static const struct dmi_system_id intel_dual_link_lvds[] = {
838 {
839 .callback = intel_dual_link_lvds_callback,
840 .ident = "Apple MacBook Pro 15\" (2010)",
841 .matches = {
842 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
843 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
844 },
845 },
846 {
847 .callback = intel_dual_link_lvds_callback,
848 .ident = "Apple MacBook Pro 15\" (2011)",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
851 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
852 },
853 },
854 {
855 .callback = intel_dual_link_lvds_callback,
856 .ident = "Apple MacBook Pro 15\" (2012)",
857 .matches = {
858 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
859 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
860 },
861 },
862 { } /* terminating entry */
863 };
864
865 bool intel_is_dual_link_lvds(struct drm_device *dev)
866 {
867 struct intel_encoder *encoder;
868 struct intel_lvds_encoder *lvds_encoder;
869
870 for_each_intel_encoder(dev, encoder) {
871 if (encoder->type == INTEL_OUTPUT_LVDS) {
872 lvds_encoder = to_lvds_encoder(&encoder->base);
873
874 return lvds_encoder->is_dual_link;
875 }
876 }
877
878 return false;
879 }
880
881 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
882 {
883 struct drm_device *dev = lvds_encoder->base.base.dev;
884 unsigned int val;
885 struct drm_i915_private *dev_priv = dev->dev_private;
886
887 /* use the module option value if specified */
888 if (i915.lvds_channel_mode > 0)
889 return i915.lvds_channel_mode == 2;
890
891 /* single channel LVDS is limited to 112 MHz */
892 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
893 > 112999)
894 return true;
895
896 if (dmi_check_system(intel_dual_link_lvds))
897 return true;
898
899 /* BIOS should set the proper LVDS register value at boot, but
900 * in reality, it doesn't set the value when the lid is closed;
901 * we need to check "the value to be set" in VBT when LVDS
902 * register is uninitialized.
903 */
904 val = I915_READ(lvds_encoder->reg);
905 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
906 val = dev_priv->vbt.bios_lvds_val;
907
908 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
909 }
910
911 static bool intel_lvds_supported(struct drm_device *dev)
912 {
913 /* With the introduction of the PCH we gained a dedicated
914 * LVDS presence pin, use it. */
915 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
916 return true;
917
918 /* Otherwise LVDS was only attached to mobile products,
919 * except for the inglorious 830gm */
920 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
921 return true;
922
923 return false;
924 }
925
926 /**
927 * intel_lvds_init - setup LVDS connectors on this device
928 * @dev: drm device
929 *
930 * Create the connector, register the LVDS DDC bus, and try to figure out what
931 * modes we can display on the LVDS panel (if present).
932 */
933 void intel_lvds_init(struct drm_device *dev)
934 {
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 struct intel_lvds_encoder *lvds_encoder;
937 struct intel_encoder *intel_encoder;
938 struct intel_lvds_connector *lvds_connector;
939 struct intel_connector *intel_connector;
940 struct drm_connector *connector;
941 struct drm_encoder *encoder;
942 struct drm_display_mode *scan; /* *modes, *bios_mode; */
943 struct drm_display_mode *fixed_mode = NULL;
944 struct drm_display_mode *downclock_mode = NULL;
945 struct edid *edid;
946 struct drm_crtc *crtc;
947 u32 lvds;
948 int pipe;
949 u8 pin;
950
951 /*
952 * Unlock registers and just leave them unlocked. Do this before
953 * checking quirk lists to avoid bogus WARNINGs.
954 */
955 if (HAS_PCH_SPLIT(dev)) {
956 I915_WRITE(PCH_PP_CONTROL,
957 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
958 } else {
959 I915_WRITE(PP_CONTROL,
960 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
961 }
962 if (!intel_lvds_supported(dev))
963 return;
964
965 /* Skip init on machines we know falsely report LVDS */
966 if (dmi_check_system(intel_no_lvds))
967 return;
968
969 if (HAS_PCH_SPLIT(dev)) {
970 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
971 return;
972 if (dev_priv->vbt.edp_support) {
973 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
974 return;
975 }
976 }
977
978 pin = GMBUS_PIN_PANEL;
979 if (!lvds_is_present_in_vbt(dev, &pin)) {
980 u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
981 if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
982 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
983 return;
984 }
985 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
986 }
987
988 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
989 if (!lvds_encoder)
990 return;
991
992 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
993 if (!lvds_connector) {
994 kfree(lvds_encoder);
995 return;
996 }
997
998 if (intel_connector_init(&lvds_connector->base) < 0) {
999 kfree(lvds_connector);
1000 kfree(lvds_encoder);
1001 return;
1002 }
1003
1004 lvds_encoder->attached_connector = lvds_connector;
1005
1006 intel_encoder = &lvds_encoder->base;
1007 encoder = &intel_encoder->base;
1008 intel_connector = &lvds_connector->base;
1009 connector = &intel_connector->base;
1010 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1011 DRM_MODE_CONNECTOR_LVDS);
1012
1013 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1014 DRM_MODE_ENCODER_LVDS);
1015
1016 intel_encoder->enable = intel_enable_lvds;
1017 intel_encoder->pre_enable = intel_pre_enable_lvds;
1018 intel_encoder->compute_config = intel_lvds_compute_config;
1019 if (HAS_PCH_SPLIT(dev_priv)) {
1020 intel_encoder->disable = pch_disable_lvds;
1021 intel_encoder->post_disable = pch_post_disable_lvds;
1022 } else {
1023 intel_encoder->disable = gmch_disable_lvds;
1024 }
1025 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1026 intel_encoder->get_config = intel_lvds_get_config;
1027 intel_connector->get_hw_state = intel_connector_get_hw_state;
1028 intel_connector->unregister = intel_connector_unregister;
1029
1030 intel_connector_attach_encoder(intel_connector, intel_encoder);
1031 intel_encoder->type = INTEL_OUTPUT_LVDS;
1032
1033 intel_encoder->cloneable = 0;
1034 if (HAS_PCH_SPLIT(dev))
1035 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1036 else if (IS_GEN4(dev))
1037 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1038 else
1039 intel_encoder->crtc_mask = (1 << 1);
1040
1041 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1042 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1043 connector->interlace_allowed = false;
1044 connector->doublescan_allowed = false;
1045
1046 if (HAS_PCH_SPLIT(dev)) {
1047 lvds_encoder->reg = PCH_LVDS;
1048 } else {
1049 lvds_encoder->reg = LVDS;
1050 }
1051
1052 /* create the scaling mode property */
1053 drm_mode_create_scaling_mode_property(dev);
1054 drm_object_attach_property(&connector->base,
1055 dev->mode_config.scaling_mode_property,
1056 DRM_MODE_SCALE_ASPECT);
1057 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1058 /*
1059 * LVDS discovery:
1060 * 1) check for EDID on DDC
1061 * 2) check for VBT data
1062 * 3) check to see if LVDS is already on
1063 * if none of the above, no panel
1064 * 4) make sure lid is open
1065 * if closed, act like it's not there for now
1066 */
1067
1068 /*
1069 * Attempt to get the fixed panel mode from DDC. Assume that the
1070 * preferred mode is the right one.
1071 */
1072 mutex_lock(&dev->mode_config.mutex);
1073 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1074 if (edid) {
1075 if (drm_add_edid_modes(connector, edid)) {
1076 drm_mode_connector_update_edid_property(connector,
1077 edid);
1078 } else {
1079 kfree(edid);
1080 edid = ERR_PTR(-EINVAL);
1081 }
1082 } else {
1083 edid = ERR_PTR(-ENOENT);
1084 }
1085 lvds_connector->base.edid = edid;
1086
1087 if (IS_ERR_OR_NULL(edid)) {
1088 /* Didn't get an EDID, so
1089 * Set wide sync ranges so we get all modes
1090 * handed to valid_mode for checking
1091 */
1092 connector->display_info.min_vfreq = 0;
1093 connector->display_info.max_vfreq = 200;
1094 connector->display_info.min_hfreq = 0;
1095 connector->display_info.max_hfreq = 200;
1096 }
1097
1098 list_for_each_entry(scan, &connector->probed_modes, head) {
1099 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1100 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1101 drm_mode_debug_printmodeline(scan);
1102
1103 fixed_mode = drm_mode_duplicate(dev, scan);
1104 if (fixed_mode)
1105 goto out;
1106 }
1107 }
1108
1109 /* Failed to get EDID, what about VBT? */
1110 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1111 DRM_DEBUG_KMS("using mode from VBT: ");
1112 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1113
1114 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1115 if (fixed_mode) {
1116 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1117 goto out;
1118 }
1119 }
1120
1121 /*
1122 * If we didn't get EDID, try checking if the panel is already turned
1123 * on. If so, assume that whatever is currently programmed is the
1124 * correct mode.
1125 */
1126
1127 /* Ironlake: FIXME if still fail, not try pipe mode now */
1128 if (HAS_PCH_SPLIT(dev))
1129 goto failed;
1130
1131 lvds = I915_READ(LVDS);
1132 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1133 crtc = intel_get_crtc_for_pipe(dev, pipe);
1134
1135 if (crtc && (lvds & LVDS_PORT_EN)) {
1136 fixed_mode = intel_crtc_mode_get(dev, crtc);
1137 if (fixed_mode) {
1138 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1139 drm_mode_debug_printmodeline(fixed_mode);
1140 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1141 goto out;
1142 }
1143 }
1144
1145 /* If we still don't have a mode after all that, give up. */
1146 if (!fixed_mode)
1147 goto failed;
1148
1149 out:
1150 mutex_unlock(&dev->mode_config.mutex);
1151
1152 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1153
1154 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1155 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1156 lvds_encoder->is_dual_link ? "dual" : "single");
1157
1158 lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
1159 LVDS_A3_POWER_MASK;
1160
1161 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1162 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1163 DRM_DEBUG_KMS("lid notifier registration failed\n");
1164 lvds_connector->lid_notifier.notifier_call = NULL;
1165 }
1166 drm_connector_register(connector);
1167
1168 intel_panel_setup_backlight(connector, INVALID_PIPE);
1169
1170 return;
1171
1172 failed:
1173 mutex_unlock(&dev->mode_config.mutex);
1174
1175 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1176 drm_connector_cleanup(connector);
1177 drm_encoder_cleanup(encoder);
1178 kfree(lvds_encoder);
1179 kfree(lvds_connector);
1180 return;
1181 }
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