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23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry
{
33 struct drm_i915_mocs_table
{
35 const struct drm_i915_mocs_entry
*table
;
38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
39 #define LE_CACHEABILITY(value) ((value) << 0)
40 #define LE_TGT_CACHE(value) ((value) << 2)
41 #define LE_LRUM(value) ((value) << 4)
42 #define LE_AOM(value) ((value) << 6)
43 #define LE_RSC(value) ((value) << 7)
44 #define LE_SCC(value) ((value) << 8)
45 #define LE_PFM(value) ((value) << 11)
46 #define LE_SCF(value) ((value) << 14)
48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
49 #define L3_ESC(value) ((value) << 0)
50 #define L3_SCC(value) ((value) << 1)
51 #define L3_CACHEABILITY(value) ((value) << 4)
54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
56 /* (e)LLC caching options */
57 #define LE_PAGETABLE 0
62 /* L3 caching options */
76 * These are the MOCS tables that are programmed across all the rings.
77 * The control value is programmed to all the rings that support the
78 * MOCS registers. While the l3cc_values are only programmed to the
79 * LNCFCMOCS0 - LNCFCMOCS32 registers.
81 * These tables are intended to be kept reasonably consistent across
82 * platforms. However some of the fields are not applicable to all of
85 * Entries not part of the following tables are undefined as far as
86 * userspace is concerned and shouldn't be relied upon. For the time
87 * being they will be implicitly initialized to the strictest caching
88 * configuration (uncached) to guarantee forwards compatibility with
89 * userspace programs written against more recent kernels providing
90 * additional MOCS entries.
92 * NOTE: These tables MUST start with being uncached and the length
93 * MUST be less than 63 as the last two registers are reserved
94 * by the hardware. These tables are part of the kernel ABI and
95 * may only be updated incrementally by adding entries at the
98 static const struct drm_i915_mocs_entry skylake_mocs_table
[] = {
99 /* { 0x00000009, 0x0010 } */
100 { (LE_CACHEABILITY(LE_UC
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(0) |
101 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
102 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
)) },
103 /* { 0x00000038, 0x0030 } */
104 { (LE_CACHEABILITY(LE_PAGETABLE
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
105 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
106 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) },
107 /* { 0x0000003b, 0x0030 } */
108 { (LE_CACHEABILITY(LE_WB
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
109 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
110 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) }
113 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
114 static const struct drm_i915_mocs_entry broxton_mocs_table
[] = {
115 /* { 0x00000009, 0x0010 } */
116 { (LE_CACHEABILITY(LE_UC
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(0) |
117 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
118 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC
)) },
119 /* { 0x00000038, 0x0030 } */
120 { (LE_CACHEABILITY(LE_PAGETABLE
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
121 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
122 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) },
123 /* { 0x0000003b, 0x0030 } */
124 { (LE_CACHEABILITY(LE_WB
) | LE_TGT_CACHE(LLC_ELLC
) | LE_LRUM(3) |
125 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
126 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB
)) }
130 * get_mocs_settings()
131 * @dev_priv: i915 device.
132 * @table: Output table that will be made to point at appropriate
133 * MOCS values for the device.
135 * This function will return the values of the MOCS table that needs to
136 * be programmed for the platform. It will return the values that need
137 * to be programmed and if they need to be programmed.
139 * Return: true if there are applicable MOCS settings for the device.
141 static bool get_mocs_settings(struct drm_i915_private
*dev_priv
,
142 struct drm_i915_mocs_table
*table
)
146 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
147 table
->size
= ARRAY_SIZE(skylake_mocs_table
);
148 table
->table
= skylake_mocs_table
;
150 } else if (IS_BROXTON(dev_priv
)) {
151 table
->size
= ARRAY_SIZE(broxton_mocs_table
);
152 table
->table
= broxton_mocs_table
;
155 WARN_ONCE(INTEL_INFO(dev_priv
)->gen
>= 9,
156 "Platform that should have a MOCS table does not.\n");
162 static i915_reg_t
mocs_register(enum intel_engine_id ring
, int index
)
166 return GEN9_GFX_MOCS(index
);
168 return GEN9_MFX0_MOCS(index
);
170 return GEN9_BLT_MOCS(index
);
172 return GEN9_VEBOX_MOCS(index
);
174 return GEN9_MFX1_MOCS(index
);
177 return INVALID_MMIO_REG
;
182 * intel_mocs_init_engine() - emit the mocs control table
183 * @engine: The engine for whom to emit the registers.
185 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
186 * given table starting at the given address.
188 * Return: 0 on success, otherwise the error status.
190 int intel_mocs_init_engine(struct intel_engine_cs
*engine
)
192 struct drm_i915_private
*dev_priv
= engine
->i915
;
193 struct drm_i915_mocs_table table
;
196 if (!get_mocs_settings(dev_priv
, &table
))
199 if (WARN_ON(table
.size
> GEN9_NUM_MOCS_ENTRIES
))
202 for (index
= 0; index
< table
.size
; index
++)
203 I915_WRITE(mocs_register(engine
->id
, index
),
204 table
.table
[index
].control_value
);
207 * Ok, now set the unused entries to uncached. These entries
208 * are officially undefined and no contract for the contents
209 * and settings is given for these entries.
211 * Entry 0 in the table is uncached - so we are just writing
212 * that value to all the used entries.
214 for (; index
< GEN9_NUM_MOCS_ENTRIES
; index
++)
215 I915_WRITE(mocs_register(engine
->id
, index
),
216 table
.table
[0].control_value
);
222 * emit_mocs_control_table() - emit the mocs control table
223 * @req: Request to set up the MOCS table for.
224 * @table: The values to program into the control regs.
226 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
227 * given table starting at the given address.
229 * Return: 0 on success, otherwise the error status.
231 static int emit_mocs_control_table(struct drm_i915_gem_request
*req
,
232 const struct drm_i915_mocs_table
*table
)
234 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
235 enum intel_engine_id engine
= req
->engine
->id
;
239 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
242 ret
= intel_ring_begin(req
, 2 + 2 * GEN9_NUM_MOCS_ENTRIES
);
246 intel_logical_ring_emit(ringbuf
,
247 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
));
249 for (index
= 0; index
< table
->size
; index
++) {
250 intel_logical_ring_emit_reg(ringbuf
,
251 mocs_register(engine
, index
));
252 intel_logical_ring_emit(ringbuf
,
253 table
->table
[index
].control_value
);
257 * Ok, now set the unused entries to uncached. These entries
258 * are officially undefined and no contract for the contents
259 * and settings is given for these entries.
261 * Entry 0 in the table is uncached - so we are just writing
262 * that value to all the used entries.
264 for (; index
< GEN9_NUM_MOCS_ENTRIES
; index
++) {
265 intel_logical_ring_emit_reg(ringbuf
,
266 mocs_register(engine
, index
));
267 intel_logical_ring_emit(ringbuf
,
268 table
->table
[0].control_value
);
271 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
272 intel_logical_ring_advance(ringbuf
);
277 static inline u32
l3cc_combine(const struct drm_i915_mocs_table
*table
,
281 return table
->table
[low
].l3cc_value
|
282 table
->table
[high
].l3cc_value
<< 16;
286 * emit_mocs_l3cc_table() - emit the mocs control table
287 * @req: Request to set up the MOCS table for.
288 * @table: The values to program into the control regs.
290 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
291 * given table starting at the given address. This register set is
292 * programmed in pairs.
294 * Return: 0 on success, otherwise the error status.
296 static int emit_mocs_l3cc_table(struct drm_i915_gem_request
*req
,
297 const struct drm_i915_mocs_table
*table
)
299 struct intel_ringbuffer
*ringbuf
= req
->ringbuf
;
303 if (WARN_ON(table
->size
> GEN9_NUM_MOCS_ENTRIES
))
306 ret
= intel_ring_begin(req
, 2 + GEN9_NUM_MOCS_ENTRIES
);
310 intel_logical_ring_emit(ringbuf
,
311 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES
/ 2));
313 for (i
= 0; i
< table
->size
/2; i
++) {
314 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
315 intel_logical_ring_emit(ringbuf
,
316 l3cc_combine(table
, 2*i
, 2*i
+1));
319 if (table
->size
& 0x01) {
320 /* Odd table size - 1 left over */
321 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
322 intel_logical_ring_emit(ringbuf
, l3cc_combine(table
, 2*i
, 0));
327 * Now set the rest of the table to uncached - use entry 0 as
328 * this will be uncached. Leave the last pair uninitialised as
329 * they are reserved by the hardware.
331 for (; i
< GEN9_NUM_MOCS_ENTRIES
/ 2; i
++) {
332 intel_logical_ring_emit_reg(ringbuf
, GEN9_LNCFCMOCS(i
));
333 intel_logical_ring_emit(ringbuf
, l3cc_combine(table
, 0, 0));
336 intel_logical_ring_emit(ringbuf
, MI_NOOP
);
337 intel_logical_ring_advance(ringbuf
);
343 * intel_mocs_init_l3cc_table() - program the mocs control table
344 * @dev: The the device to be programmed.
346 * This function simply programs the mocs registers for the given table
347 * starting at the given address. This register set is programmed in pairs.
349 * These registers may get programmed more than once, it is simpler to
350 * re-program 32 registers than maintain the state of when they were programmed.
351 * We are always reprogramming with the same values and this only on context
356 void intel_mocs_init_l3cc_table(struct drm_device
*dev
)
358 struct drm_i915_private
*dev_priv
= to_i915(dev
);
359 struct drm_i915_mocs_table table
;
362 if (!get_mocs_settings(dev_priv
, &table
))
365 for (i
= 0; i
< table
.size
/2; i
++)
366 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 2*i
, 2*i
+1));
368 /* Odd table size - 1 left over */
369 if (table
.size
& 0x01) {
370 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 2*i
, 0));
375 * Now set the rest of the table to uncached - use entry 0 as
376 * this will be uncached. Leave the last pair as initialised as
377 * they are reserved by the hardware.
379 for (; i
< (GEN9_NUM_MOCS_ENTRIES
/ 2); i
++)
380 I915_WRITE(GEN9_LNCFCMOCS(i
), l3cc_combine(&table
, 0, 0));
384 * intel_rcs_context_init_mocs() - program the MOCS register.
385 * @req: Request to set up the MOCS tables for.
387 * This function will emit a batch buffer with the values required for
388 * programming the MOCS register values for all the currently supported
391 * These registers are partially stored in the RCS context, so they are
392 * emitted at the same time so that when a context is created these registers
393 * are set up. These registers have to be emitted into the start of the
394 * context as setting the ELSP will re-init some of these registers back
397 * Return: 0 on success, otherwise the error status.
399 int intel_rcs_context_init_mocs(struct drm_i915_gem_request
*req
)
401 struct drm_i915_mocs_table t
;
404 if (get_mocs_settings(req
->i915
, &t
)) {
405 /* Program the RCS control registers */
406 ret
= emit_mocs_control_table(req
, &t
);
410 /* Now program the l3cc registers */
411 ret
= emit_mocs_l3cc_table(req
, &t
);